/****************************************************************************
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* @file pan_adc.h
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* @version V1.00
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* $Revision: 2 $
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* $Date: 2023/11/08 16:08 $
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* @brief Panchip series ADC driver header file
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*
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* @note
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* Copyright (C) 2023 Panchip Technology Corp. All rights reserved.
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*****************************************************************************/
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#ifndef __PAN_ADC_H__
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#define __PAN_ADC_H__
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/**
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* @brief Adc Interface
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* @defgroup adc_interface Adc Interface
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* @{
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*/
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#define ADC_INPUTRANGE_HIGH (1UL) /*!< ADC input range 0.4V~2.4V */
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#define ADC_INPUTRANGE_LOW (0UL) /*!< ADC input range 0.4V~1.4V */
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#define ADC_CH8_EXT (0UL) /*!< Use external input pin as ADC channel 8 source */
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#define ADC_CH8_BGP (ADC_CHEN_CH8SEL_Msk) /*!< Use internal band-gap voltage (VBG) as channel 8 source. */
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#define ADC_CMP0_LESS_THAN (0UL << ADC_CMP0_CMPCOND_Pos) /*!< ADC compare condition less than */
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#define ADC_CMP1_LESS_THAN (0UL << ADC_CMP1_CMPCOND_Pos) /*!< ADC compare condition less than */
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#define ADC_CMP0_GREATER_OR_EQUAL_TO (1ul << ADC_CMP0_CMPCOND_Pos) /*!< ADC compare condition greater or equal to */
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#define ADC_CMP1_GREATER_OR_EQUAL_TO (1ul << ADC_CMP1_CMPCOND_Pos) /*!< ADC compare condition greater or equal to */
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#define ADC_TRIGGER_BY_EXT_PIN (0UL << ADC_CTL_HWTRGSEL_Pos) /*!< ADC trigger by STADC (P3.2) pin */
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#define ADC_TRIGGER_BY_PWM (ADC_CTL_HWTRGSEL_Msk) /*!< ADC trigger by PWM events */
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#define ADC_FALLING_EDGE_TRIGGER (0UL << ADC_CTL_HWTRGCOND_Pos) /*!< External pin falling edge trigger ADC */
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#define ADC_RISING_EDGE_TRIGGER (ADC_CTL_HWTRGCOND_Msk) /*!< External pin rising edge trigger ADC */
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/**@defgroup ADC_INT_FLAG Adc interrupt
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* @brief Adc interrupt control
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* @{ */
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#define ADC_ADIF_INT (ADC_STATUS_ADIF_Msk) /*!< ADC convert complete interrupt */
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#define ADC_CMP0_INT (ADC_STATUS_ADCMPIF0_Msk) /*!< ADC comparator 0 interrupt */
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#define ADC_CMP1_INT (ADC_STATUS_ADCMPIF1_Msk) /*!< ADC comparator 1 interrupt */
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#define ADC_FIFO_FULL_INT (ADC_STATUS_INTFLG_FULL_Msk) /*!< ADC fifo full interrupt */
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#define ADC_FIFO_EMPTY_INT (ADC_STATUS_INTFLG_EMPTY_Msk) /*!< ADC fifo empty interrupt */
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#define ADC_FIFO_OVER_INT (ADC_STATUS_INTFLG_OVER_Msk) /*!< ADC fifo overflow interrupt */
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#define ADC_FIFO_HALF_INT (ADC_STATUS_INTFLG_HALF_Msk) /*!< ADC fifo half full interrupt */
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/**@} */
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/**@defgroup ADC_SEQMODE_FLAG Adc sequential mode
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* @brief Adc sequential mode control
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* @{ */
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#define ADC_SAMPLE_CLOCK_0 (0UL) /*!< ADC sample time is 0 ADC clock */
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#define ADC_SAMPLE_CLOCK_1 (1UL) /*!< ADC sample time is 1 ADC clock */
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#define ADC_SAMPLE_CLOCK_2 (2UL) /*!< ADC sample time is 2 ADC clock */
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#define ADC_SAMPLE_CLOCK_4 (3UL) /*!< ADC sample time is 4 ADC clock */
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#define ADC_SAMPLE_CLOCK_8 (4UL) /*!< ADC sample time is 8 ADC clock */
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#define ADC_SAMPLE_CLOCK_16 (5UL) /*!< ADC sample time is 16 ADC clock */
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#define ADC_SAMPLE_CLOCK_32 (6UL) /*!< ADC sample time is 32 ADC clock */
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#define ADC_SAMPLE_CLOCK_64 (7UL) /*!< ADC sample time is 64 ADC clock */
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#define ADC_SAMPLE_CLOCK_128 (8UL) /*!< ADC sample time is 128 ADC clock */
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#define ADC_SAMPLE_CLOCK_256 (9UL) /*!< ADC sample time is 256 ADC clock */
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#define ADC_SAMPLE_CLOCK_512 (10UL) /*!< ADC sample time is 512 ADC clock */
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#define ADC_SAMPLE_CLOCK_1024 (11UL) /*!< ADC sample time is 1024 ADC clock */
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#define ADC_SEQMODE_TYPE_23SHUNT (0UL) /*!< ADC sequential mode 23-shunt type */
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#define ADC_SEQMODE_TYPE_1SHUNT (1UL) /*!< ADC sequential mode 1-shunt type */
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#define ADC_SEQMODE_MODESELECT_CH01 (0UL) /*!< ADC channel 0 then channel 1 conversion */
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#define ADC_SEQMODE_MODESELECT_CH12 (1UL) /*!< ADC channel 1 then channel 2 conversion */
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#define ADC_SEQMODE_MODESELECT_CH02 (2UL) /*!< ADC channel 0 then channel 2 conversion */
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#define ADC_SEQMODE_MODESELECT_ONE (3UL) /*!< ADC channel 0 then channel 2 conversion */
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#define ADC_SEQMODE_PWM0_RISING (0UL) /*!< ADC sequential mode PWM0 rising trigger ADC*/
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#define ADC_SEQMODE_PWM0_CENTER (1UL) /*!< ADC sequential mode PWM0 center trigger ADC*/
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#define ADC_SEQMODE_PWM0_FALLING (2UL) /*!< ADC sequential mode PWM0 falling trigger ADC*/
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#define ADC_SEQMODE_PWM0_PERIOD (3UL) /*!< ADC sequential mode PWM0 period trigger ADC*/
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#define ADC_SEQMODE_PWM2_RISING (4UL) /*!< ADC sequential mode PWM2 rising trigger ADC*/
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#define ADC_SEQMODE_PWM2_CENTER (5UL) /*!< ADC sequential mode PWM2 center trigger ADC*/
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#define ADC_SEQMODE_PWM2_FALLING (6UL) /*!< ADC sequential mode PWM2 falling trigger ADC*/
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#define ADC_SEQMODE_PWM2_PERIOD (7UL) /*!< ADC sequential mode PWM2 period trigger ADC*/
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#define ADC_SEQMODE_PWM4_RISING (8UL) /*!< ADC sequential mode PWM4 rising trigger ADC*/
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#define ADC_SEQMODE_PWM4_CENTER (9UL) /*!< ADC sequential mode PWM4 center trigger ADC*/
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#define ADC_SEQMODE_PWM4_FALLING (10UL) /*!< ADC sequential mode PWM4 falling trigger ADC*/
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#define ADC_SEQMODE_PWM4_PERIOD (11UL) /*!< ADC sequential mode PWM4 period trigger ADC*/
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#define ADC_SEQMODE_PWM6_RISING (12UL) /*!< ADC sequential mode PWM4 rising trigger ADC*/
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#define ADC_SEQMODE_PWM6_CENTER (13UL) /*!< ADC sequential mode PWM4 center trigger ADC*/
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#define ADC_SEQMODE_PWM6_FALLING (14UL) /*!< ADC sequential mode PWM4 falling trigger ADC*/
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#define ADC_SEQMODE_PWM6_PERIOD (15UL) /*!< ADC sequential mode PWM4 period trigger ADC*/
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/**@} */
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#define ADC_COMPARATOR_0 (0) /*!< ADC comparator 0 selected */
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#define ADC_COMPARATOR_1 (1) /*!< ADC comparator 0 selected */
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#define ADC_FIFO_TRIG_LEVEL_HALF (0) /*!< ADC half fifo threshold level setted */
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#define ADC_FIFO_TRIG_LEVEL_FULL (1) /*!< ADC full fifo threshold level setted */
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typedef struct {
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uint8_t chip_info; // otp offset: 0x75
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uint8_t ft_version; // otp offset: 0x77
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int8_t adc_vdd_b; // otp offset: 0x5B
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uint16_t adc_vdd_k; // otp offset: 0x59, 0x5A
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uint16_t adc_vbg_k; // otp offset: 0x5C, 0x5D
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int16_t adc_vbg_b; // otp offset: 0x5E, 0x5F
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uint16_t adc_temp_volt; // otp offset: 0x60, 0x61
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int16_t current_temp_value; // otp offset: 0x62, 0x63
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uint8_t adc_vbg_1v20_trim : 6; // otp offset: 0x30 (bit 0 ~ 5
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uint8_t rsvd_0x30 : 2; // otp offset: 0x30 (bit 6 ~ 7)
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ADC_VBG_KB_T adc_vbg_kb[7]; // otp offset: 0xA0 ~ 0xBB <ft v3>
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uint16_t adc_vbat_k; // otp offset: 0xBC, 0xBD
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int16_t adc_vbat_b; // otp offset: 0xBE, 0xBF
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int16_t adc_vbat_dtemp_k; // otp offset: 0xC0, 0xC1 <ft v5>
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int16_t adc_vbat_dtemp_b; // otp offset: 0xC2, 0xC3 <ft v5>
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float adc_temp_k; // otp offset: 0xC4 ~ 0xC7 <ft v6>
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uint32_t adc_ctrl2; // otp offset: 0xC8 ~ 0xCB <ft v6>
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uint32_t adc_extsmpt; // otp offset: 0xCC ~ 0xCF <ft v6>
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} ADC_OPT_T;
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extern ADC_OPT_T m_adc_opt;
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extern uint32_t global_calc_vbat_mv;
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extern void ADC_SetCalirationParams(OTP_STRUCT_T *opt);
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/**
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* @brief Get the latest ADC conversion data
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* @param[in] ADCx Base address of ADC module
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* @return Latest ADC conversion data
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* \hideinitializer
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*/
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__STATIC_INLINE uint32_t ADC_GetConversionData(ADC_T *ADCx)
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{
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return (ADCx->DAT & ADC_DAT_RESULT_Msk);
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}
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/**
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* @brief Get raw status flag
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* @param[in] ADCx Base address of ADC module
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* @param[in] IntMask The combination of following status bits. Each bit corresponds to a status flag.
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* - \ref ADC_STATUS_ADCF_Msk
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* - \ref ADC_STATUS_ADCMPF0_Msk
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* - \ref ADC_STATUS_ADCMPF1_Msk
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* - \ref ADC_STATUS_FLAG_FULL_Msk
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* - \ref ADC_STATUS_FLAG_EMPTY_Msk
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* - \ref ADC_STATUS_FLAG_OVER_Msk
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* - \ref ADC_STATUS_FLAG_HALF_Msk
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* @return True or false
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*/
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__STATIC_INLINE bool ADC_StatusFlag(ADC_T *ADCx,uint32_t IntMask)
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{
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return (ADCx->STATUS & IntMask)?(true):(false);
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}
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/**
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* @brief Clear specified interrupt flag
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* @param[in] ADCx Base address of ADC module
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* @param[in] IntMask The combination of following status bits. Each bit corresponds to a status flag.
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* - \ref ADC_STATUS_ADCF_Msk
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* - \ref ADC_STATUS_ADCMPF0_Msk
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* - \ref ADC_STATUS_ADCMPF1_Msk
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* - \ref ADC_STATUS_FLAG_FULL_Msk
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* - \ref ADC_STATUS_FLAG_EMPTY_Msk
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* - \ref ADC_STATUS_FLAG_OVER_Msk
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* - \ref ADC_STATUS_FLAG_HALF_Msk
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* @return None
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*/
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__STATIC_INLINE void ADC_ClearStatusFlag(ADC_T *ADCx,uint32_t IntMask)
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{
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ADCx->STATUS |= IntMask;
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}
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/**
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* @brief Set interrupt mask,if masked,interrupt will not be happened
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* @param[in] ADCx Base address of ADC module
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* @param[in] u32Mask The combination of following interrupt mask bits. Each bit corresponds to a interrupt mask flag.
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* - \ref ADC_STATUS_INTMSK_FULL_Msk
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* - \ref ADC_STATUS_INTMSK_EMPTY_Msk
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* - \ref ADC_STATUS_INTMSK_OVER_Msk
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* - \ref ADC_STATUS_INTMSK_HALF_Msk
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* - \ref ADC_STATUS_INTMSK_AD_Msk
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* - \ref ADC_STATUS_INTMSK_CMP0_Msk
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* - \ref ADC_STATUS_INTMSK_CMP1_Msk
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* @param[in] NewState: new state of adc interrupt mask
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* @return none
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* \hideinitializer
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*/
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__STATIC_INLINE void ADC_IntMask(ADC_T *ADCx,uint32_t IntMask,FunctionalState NewState)
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{
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(NewState == DISABLE)?(ADCx->STATUS |= IntMask):(ADCx->STATUS &= ~IntMask);
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}
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/**
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* @brief adjust the user-specified interrupt occured or not
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* @param[in] ADCx Base address of ADC module
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* @param[in] IntMask The combination of following interrupt status bits. Each bit corresponds to a interrupt status.
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* - \ref ADC_ADIF_INT
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* - \ref ADC_CMP0_INT
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* - \ref ADC_CMP1_INT
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* - \ref ADC_FIFO_FULL_INT
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* - \ref ADC_FIFO_EMPTY_INT
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* - \ref ADC_FIFO_OVER_INT
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* - \ref ADC_FIFO_HALF_INT
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* @return User specified interrupt flags
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* \hideinitializer
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*/
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__STATIC_INLINE bool ADC_IsIntOccured(ADC_T *ADCx,uint32_t IntMask)
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{
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return (ADCx->STATUS & IntMask)?(true):(false);
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}
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/**
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* @brief This macro clear the selected interrupt status bits
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* @param[in] ADCx Base address of ADC module
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* @param[in] IntMask The combination of following interrupt status bits. Each bit corresponds to a interrupt status.
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* - \ref ADC_ADIF_INT
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* - \ref ADC_CMP0_INT
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* - \ref ADC_CMP1_INT
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* - \ref ADC_FIFO_FULL_INT
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* - \ref ADC_FIFO_EMPTY_INT
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* - \ref ADC_FIFO_OVER_INT
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* - \ref ADC_FIFO_HALF_INT
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* @return None
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* \hideinitializer
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*/
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__STATIC_INLINE void ADC_ClearIntFlag(ADC_T *ADCx,uint32_t IntMask)
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{
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ADCx->STATUS = ADCx->STATUS | IntMask;
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}
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/**
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* @brief Get the busy state of ADC
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* @param[in] ADCx Base address of ADC module
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* @return busy state of ADC
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* @retval 0 ADC is not busy
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* @retval 1 ADC is busy
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* \hideinitializer
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*/
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__STATIC_INLINE bool ADC_IsBusy(ADC_T *ADCx)
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{
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return (ADCx->STATUS & ADC_STATUS_BUSY_Msk)?(true):(false);
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}
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/**
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* @brief Check if the ADC conversion data is over written or not
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* @param[in] ADCx Base address of ADC module
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* @return Over run state of ADC data
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* @retval 0 ADC data is not overrun
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* @retval 1 ADC data is overrun
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* \hideinitializer
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*/
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__STATIC_INLINE bool ADC_IsDataOverrun(ADC_T *ADCx)
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{
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return (ADCx->STATUS & ADC_STATUS_OV_Msk)?(true):(false);
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}
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/**
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* @brief Check if the ADC conversion data is valid or not
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* @param[in] ADCx Base address of ADC module
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* @return Valid state of ADC data
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* @retval 0 ADC data is not valid
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* @retval 1 ADC data us valid
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* \hideinitializer
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*/
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__STATIC_INLINE bool ADC_IsDataValid(ADC_T *ADCx)
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{
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return (ADCx->STATUS & ADC_STATUS_VALID_Msk)?(true):(false);
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}
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/**
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* @brief Power down ADC module
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* @param[in] ADCx Base address of ADC module
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* @return None
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* \hideinitializer
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*/
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__STATIC_INLINE void ADC_PowerDown(ADC_T *ADCx)
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{
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ADCx->CTL = ADCx->CTL & ~ADC_CTL_ADCEN_Msk;
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}
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/**
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* @brief Power on ADC module
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* @param[in] ADCx Base address of ADC module
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* @return None
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* \hideinitializer
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*/
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__STATIC_INLINE void ADC_PowerOn(ADC_T *ADCx)
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{
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ADCx->CTL = ADCx->CTL | ADC_CTL_ADCEN_Msk;
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}
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/**
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* @brief ADC sequential mode Disabled
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* @param[in] ADCx Base address of ADC module
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* @return None
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* \hideinitializer
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*/
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__STATIC_INLINE void ADC_SequentialModeDisable(ADC_T *ADCx)
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{
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ADCx->SEQCTL = ADCx->SEQCTL & ~ADC_SEQCTL_SEQEN_Msk;
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}
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/**
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* @brief TRG1CTL select for 1-shunt sequential mode
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* @param[in] ADCx Base address of ADC module
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* @param[in] NewState: new state of adc sequence mode
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* @return None
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* \hideinitializer
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*/
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__STATIC_INLINE void ADC_Trigger2Select(ADC_T *ADCx,FunctionalState NewState)
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{
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(NewState == ENABLE)?(ADCx->SEQCTL |= ADC_SEQCTL_TRG_SEL_Msk):(ADCx->SEQCTL &= ~ADC_SEQCTL_TRG_SEL_Msk);
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}
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/**
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* @brief Disable comparator 0
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* @param[in] ADCx Base address of ADC module
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* @return None
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*/
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__STATIC_INLINE void ADC_DisableCompare0(ADC_T *ADCx)
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{
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ADCx->CMP0 = 0;
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}
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/**
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* @brief Disable comparator 1
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* @param[in] ADCx Base address of ADC module
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* @return None
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*/
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__STATIC_INLINE void ADC_DisableCompare1(ADC_T *ADCx)
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{
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ADCx->CMP1 = 0;
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}
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/**
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* @brief Start the A/D conversion.
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* @param[in] ADCx Base address of ADC module
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* @return None
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*/
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__STATIC_INLINE void ADC_StartConvert(ADC_T *ADCx)
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{
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ADCx->CTL = ADCx->CTL | ADC_CTL_SWTRG_Msk;
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}
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/**
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* @brief Stop the A/D conversion.
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* @param[in] ADCx Base address of ADC module
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* @return None
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*/
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__STATIC_INLINE void ADC_StopConvert(ADC_T *ADCx)
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{
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ADCx->CTL &= ~ADC_CTL_SWTRG_Msk;
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}
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/**
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* @brief Enable the A/D test mode.
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* @param[in] ADCx Base address of ADC module
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* @return None
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* \hideinitializer
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*/
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__STATIC_INLINE void ADC_TestModeEnable(ADC_T *ADCx)
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{
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ADCx->CTL2 |= ADC_CTL2_TESTMODE_Msk;
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}
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/**
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* @brief Disable the A/D test mode.
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* @param[in] ADCx Base address of ADC module
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* @return None
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* \hideinitializer
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*/
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__STATIC_INLINE void ADC_TestModeDisable(ADC_T *ADCx)
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{
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ADCx->CTL2 &= ~ADC_CTL2_TESTMODE_Msk;
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}
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/**
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* @brief Enable the A/D dma mode.
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* @param[in] ADCx Base address of ADC module
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* @param[in] NewState: new state of clear mode in pwm sequence one channel mode
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* @return None
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* \hideinitializer
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*/
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__STATIC_INLINE void ADC_DmaModeEnable(ADC_T *ADCx,FunctionalState NewState)
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{
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(NewState == ENABLE)?(ADCx->CTL2 |= ADC_CTL2_DMA_EN_Msk):(ADCx->CTL2 &= ~ADC_CTL2_DMA_EN_Msk);
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}
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/**
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* @brief Set the A/D clock division.
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* @param[in] ADCx Base address of ADC module
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* @param[in] Divider Adc clk divider
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* @return None
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* \hideinitializer
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*/
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__STATIC_INLINE void ADC_SetClockDivider(ADC_T *ADCx,uint32_t Divider)
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{
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ADCx->CTL2 = (ADCx->CTL2 & ~ADC_CTL2_CLKDIV_Msk) | (Divider << ADC_CTL2_CLKDIV_Pos);
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}
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/**
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* @brief This API configures ADC module to be ready for convert the input from selected channel
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* @param[in] ADCx Base address of ADC module
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* @param[in] ChMask Channel enable bit. Each bit corresponds to a input channel. Bit 0 is channel 0, bit 1 is channel 1...
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* @return None
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* @note Panchip series MCU ADC can only convert 1 channel at a time. If more than 1 channels are enabled, only channel
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* with smallest number will be convert.
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* @note This API does not turn on ADC power nor does trigger ADC conversion
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*/
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__STATIC_INLINE void ADC_Open(ADC_T *ADCx,uint32_t ChMask)
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{
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ADCx->CHEN = (ADCx->CHEN & ~ADC_CHEN_ALL_Msk) | ChMask;
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}
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/**
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* @brief Select ADC range of input sample signal.
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* @param[in] ADCx Base address of ADC module
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* @param[in] If EnableHigh is 1,adc input range is 0.4V~2.4V;if u32EnableHigh is 0,adc input range is 0.4V~1.4V.
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* 0.4V~2.4V & 0.4V~1.4V both is theoretical value,the real range is determined by bandgap voltage.
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* @return None
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*/
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__STATIC_INLINE void ADC_SelInputRange(ADC_T *ADCx,uint32_t EnableHigh)
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{
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ADCx->CTL2 = (ADCx->CTL2 & ~ADC_SEL_VREF_Msk) | (EnableHigh << ADC_SEL_VREF_Pos);
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}
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/**
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* @brief Delay ADC start conversion time after PWM trigger
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* @param[in] ADCx Base address of ADC module
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* @param[in] Data for Delay time
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* @return None
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*/
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__STATIC_INLINE void ADC_TriggerDelay(ADC_T *ADCx,uint32_t Data)
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{
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ADCx->TRGDLY = Data;
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}
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/**
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* @brief Set ADC sample time for designated channel.
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* @param[in] ADCx Base address of ADC module
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* @param[in] u32SampleTime ADC sample ADC time, valid values are
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* - \ref ADC_SAMPLE_CLOCK_0
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* - \ref ADC_SAMPLE_CLOCK_1
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* - \ref ADC_SAMPLE_CLOCK_2
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* - \ref ADC_SAMPLE_CLOCK_4
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* - \ref ADC_SAMPLE_CLOCK_8
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* - \ref ADC_SAMPLE_CLOCK_16
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* - \ref ADC_SAMPLE_CLOCK_32
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* - \ref ADC_SAMPLE_CLOCK_64
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* - \ref ADC_SAMPLE_CLOCK_128
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* - \ref ADC_SAMPLE_CLOCK_256
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* - \ref ADC_SAMPLE_CLOCK_512
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* - \ref ADC_SAMPLE_CLOCK_1024
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* @return None
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*/
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__STATIC_INLINE void ADC_SetExtraSampleTime(ADC_T *ADCx,uint32_t SampleTime)
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{
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ADCx->EXTSMPT = (ADCx->EXTSMPT & ~ADC_EXTSMPT_EXTSMPT_Msk) | SampleTime;
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}
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/**
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* @brief adjust pwm sequence convert end or not in adc one channel
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* @param[in] ADCx Base address of ADC module
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* @return true of false
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* \hideinitializer
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*/
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__STATIC_INLINE bool ADC_IsOneChConvertEnd(ADC_T *ADCx)
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{
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return (ADCx->STATUS & ADC_STATUS_ONE_CH_FLAG_Msk)?(true):(false);
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}
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/**
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* @brief clear pwm sequence end flag
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* @param[in] ADCx Base address of ADC module
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* @param[in] NewState: new state of clear mode in pwm sequence one channel mode
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* @return None
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* \hideinitializer
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*/
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__STATIC_INLINE void ADC_ClearByHw(ADC_T *ADCx,FunctionalState NewState)
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{
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(NewState == ENABLE)?(ADCx->STATUS |= ADC_STATUS_ONE_CH_CLR_SEL_Msk):(ADCx->STATUS &= ~ADC_STATUS_ONE_CH_CLR_SEL_Msk);
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}
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/**
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* @brief enable left shift function,if enable,adc data {adc_output[11:0],4'b0 }
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* @param[in] ADCx Base address of ADC module
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* @param[in] NewState: new state of left shift function
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* @return None
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* \hideinitializer
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*/
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__STATIC_INLINE void ADC_LeftShiftEn(ADC_T *ADCx,FunctionalState NewState)
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{
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(NewState == ENABLE)?(ADCx->CTL |= ADC_CTL_LEFT_SHIFT_EN_Msk):(ADCx->CTL &= ~ADC_CTL_LEFT_SHIFT_EN_Msk);
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}
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/**
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* @brief enable subtract bias function
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* @param[in] ADCx Base address of ADC module
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* @param[in] NewState: new state of subtract bias function
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* @return None
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* \hideinitializer
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*/
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__STATIC_INLINE void ADC_SubtractBiasEn(ADC_T *ADCx,FunctionalState NewState)
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{
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(NewState == ENABLE)?(ADCx->CTL |= ADC_CTL_SUB_BIAS_EN_Msk):(ADCx->CTL &= ~ADC_CTL_SUB_BIAS_EN_Msk);
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}
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/**
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* @brief set bias data
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* @param[in] ADCx Base address of ADC module
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* @param[in] BiasData data value
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* @return none
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* \hideinitializer
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*/
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__STATIC_INLINE void ADC_SetBiasData(ADC_T *ADCx,uint32_t BiasData)
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{
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ADCx->CTL = (ADCx->CTL & ~ADC_CTL_BIAS_VALUE_Msk) | (BiasData << ADC_CTL_BIAS_VALUE_Pos);
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}
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/**
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* @brief set adc fifo trig level
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* @param[in] ADCx Base address of ADC module
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* @param[in] Level dma request level
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* \ref ADC_FIFO_TRIG_LEVEL_HALF
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* \ref ADC_FIFO_TRIG_LEVEL_FULL
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* @return none
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* \hideinitializer
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*/
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__STATIC_INLINE void ADC_SetFifoTrigLevel(ADC_T *ADCx,uint8_t Level)
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{
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ADCx->CTL = (ADCx->CTL & ~ADC_CTL_FIFO_THRE_STATE_Msk) | ((Level << ADC_CTL_FIFO_THRE_STATE_Pos)|ADC_CTL_FIFO_EN_Msk);
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}
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/**
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* @brief pwm sequential enable in adc one channel mode
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* @param[in] ADCx Base address of ADC module
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* @param[in] NewState: new state of adc sequence mode
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* @return None
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* \hideinitializer
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*/
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__STATIC_INLINE void ADC_SeqModeOneChEn(ADC_T *ADCx,FunctionalState NewState)
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{
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(NewState)?(ADCx->SEQCTL |= ADC_SEQCTL_ONE_CH_EN_Msk):(ADCx->SEQCTL &= ~ADC_SEQCTL_ONE_CH_EN_Msk);
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}
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/**
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* @brief Init ADC config parameters
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* @param[in] ADCx Base address of ADC module
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* @param[in] buf_en Enable or disable buffer
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* @return None
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*/
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bool ADC_Init(ADC_T *ADCx, bool buf_en);
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/**
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* @brief Prepare ADC VBG fitting curve paramters due to SoC VBAT level
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* @param[in] ADCx Base address of ADC module
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* @return None
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*/
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void ADC_PrepareVbgCalibData(ADC_T *ADCx);
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/**
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* @brief Convert adc code to voltage in uV
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* @param[in] ADCx Base address of ADC module
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* @param[in] adc_code Code sampled by ADC module
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* @return ADC sample voltage output in uV
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*/
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float ADC_OutputVoltage(ADC_T *ADCx, uint32_t adc_code);
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/**
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* @brief Start sampling many data codes, trim several largest and smallest codes and calculate average valu
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* @param[in] ADCx Base address of ADC module
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* @param[in] sample_buf Buffer to temporarily store ADC sample code
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* @param[in] sample_cnt Total sampling count
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* @param[in] trim_cnt Total trim count, that means throw away the smallest trim_cnt/2 and largest trim_cnt/2 sample codes
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* @return ADC sample voltage output in mV
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*/
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uint32_t ADC_SamplingCodeTrimMean(ADC_T *ADCx, uint16_t *sample_buf, uint32_t sample_cnt, uint32_t trim_cnt);
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/**
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* @brief Measure SoC Temperature using the ADC internal Channel 9
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* @param[in] ADCx Base address of ADC module
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* @return ADC measured temperature in Celsius
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*/
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float ADC_MeasureSocTemperature(ADC_T *ADCx);
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/**
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* @brief Measure SoC Temperature More Fast using the ADC internal Channel 9
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* @param[in] ADCx Base address of ADC module
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* @return ADC measured temperature in Celsius
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*/
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float ADC_MeasureSocTemperatureFast(ADC_T *ADCx);
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/**
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* @brief Measure SoC VBAT using the ADC internal Channel 10
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* @param[in] ADCx Base address of ADC module
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* @return ADC measured VBAT voltage in mV
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*/
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uint16_t ADC_MeasureSocVbat(ADC_T *ADCx);
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/**
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* @brief Disable the specified ADC module.
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*
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* This function disables the specified ADC module.
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*
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* @param[in] ADCx Base address of the ADC module to disable.
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*
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* @return None
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*/
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void ADC_Disable(ADC_T *ADCx);
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/**
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* @brief Close and deinitialize the ADC.
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*
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* This function closes and deinitializes the ADC, releasing any allocated resources.
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*
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* @return None
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*/
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void ADC_Close(void);
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/**
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* @brief Configure the hardware trigger condition and enable hardware trigger
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* @param[in] ADCx Base address of ADC module
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* @param[in] Source Decides the hardware trigger source. Valid values are:
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* - \ref ADC_TRIGGER_BY_EXT_PIN
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* - \ref ADC_TRIGGER_BY_PWM
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* @param[in] Param While ADC trigger by PWM, this parameter is used to set the delay between PWM
|
* trigger and ADC conversion. Valid values are from 0 ~ 0xFF, and actual delay
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* time is (4 * u32Param * HCLK). While ADC trigger by external pin, this parameter
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* is used to set trigger condition. Valid values are:
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* - \ref ADC_FALLING_EDGE_TRIGGER
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* - \ref ADC_RISING_EDGE_TRIGGER
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* @return None
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*/
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void ADC_EnableHWTrigger(ADC_T *ADCx,
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uint32_t Source,
|
uint32_t Param);
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/**
|
* @brief Disable hardware trigger ADC function.
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* @param[in] ADCx Base address of ADC module
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* @return None
|
*/
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void ADC_DisableHWTrigger(ADC_T *ADCx);
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/**
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* @brief Enable the interrupt(s) selected by u32Mask parameter.
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* @param[in] ADCx Base address of ADC module
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* @param[in] Mask The combination of interrupt status bits listed below. Each bit
|
* corresponds to a interrupt status. This parameter decides which
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* interrupts will be enabled.
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* - \ref ADC_ADIF_INT
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* - \ref ADC_CMP0_INT
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* - \ref ADC_CMP1_INT
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* @return None
|
*/
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void ADC_EnableInt(ADC_T *ADCx, uint32_t Mask);
|
/**
|
* @brief Disable the interrupt(s) selected by u32Mask parameter.
|
* @param[in] ADCx Base address of ADC module
|
* @param[in] Mask The combination of interrupt status bits listed below. Each bit
|
* corresponds to a interrupt status. This parameter decides which
|
* interrupts will be disabled.
|
* - \ref ADC_ADIF_INT
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* - \ref ADC_CMP0_INT
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* - \ref ADC_CMP1_INT
|
* @return None
|
*/
|
void ADC_DisableInt(ADC_T *ADCx, uint32_t Mask);
|
|
/**
|
* @brief ADC PWM Sequential Mode Control.
|
* @param[in] ADCx Base address of ADC module
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* @param[in] SeqTYPE This parameter decides which type will be selected.
|
* - \ref ADC_SEQMODE_TYPE_23SHUNT
|
* - \ref ADC_SEQMODE_TYPE_1SHUNT
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* @param[in] ModeSel This parameter decides which mode will be selected.
|
* - \ref ADC_SEQMODE_MODESELECT_CH01
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* - \ref ADC_SEQMODE_MODESELECT_CH12
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* - \ref ADC_SEQMODE_MODESELECT_CH02
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* - \ref ADC_SEQMODE_MODESELECT_ONE
|
* @return None
|
*/
|
void ADC_SeqModeEnable(ADC_T *ADCx, uint32_t SeqTYPE, uint32_t ModeSel);
|
/**
|
* @brief ADC PWM Sequential Mode PWM Trigger Source and type.
|
* @param[in] ADCx Base address of ADC module
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* @param[in] SeqModeTriSrc This parameter decides first PWM trigger source and type.
|
*
|
* @return None
|
*/
|
void ADC_SeqModeTriggerSrc(ADC_T *ADCx, uint32_t SeqModeTriSrc);
|
/**
|
* @brief Configure the comparator 0 and enable it
|
* @param[in] ADCx Base address of ADC module
|
* @param[in] ChNum Specifies the source channel, valid value are from 0 to 7
|
* @param[in] CmpCondition Specifies the compare condition
|
* - \ref ADC_CMP0_LESS_THAN
|
* - \ref ADC_CMP0_GREATER_OR_EQUAL_TO
|
* @param[in] CmpData Specifies the compare value. Valid value are between 0 ~ 0x3FF
|
* @param[in] MatchCnt Specifies the match count setting, valid values are between 1~16
|
* @param[in] CmpSelect comparator select,0 or 1
|
* @return None
|
* @details For example, ADC_CompareEnable(ADC, 5, ADC_CMP_GREATER_OR_EQUAL_TO, 0x800, 10,ADC_COMPARATOR_0);
|
* Means ADC will assert comparator 0 flag if channel 5 conversion result is
|
* greater or equal to 0x800 for 10 times continuously.
|
*/
|
void ADC_CompareEnable(ADC_T *ADCx,
|
uint32_t ChNum,
|
uint32_t CmpCondition,
|
uint32_t CmpData,
|
uint32_t MatchCnt,
|
uint32_t CmpSelect);
|
/**
|
* @brief set ADC PWM one channel Sequential Mode configuration.
|
* @param[in] ADCx Base address of ADC module
|
* @param[in] Trig This parameter decides first PWM trigger source and type.
|
* @param[in] Level This parameter decides fifo threshold value.
|
* @param[in] DmaEn This parameter decides dma is used or not.
|
* @param[in] HwClrEN This parameter decides PWM trigger flag cleared by hardware or software.
|
* @return None
|
*
|
* @code:
|
*
|
* ADC_SeqOneChModeConfig(ADC,ADC_FALLING_EDGE_TRIGGER,ADC_FIFO_TRIG_LEVEL_HALF,1,1,5);
|
*
|
* @endcode
|
*/
|
void ADC_SeqOneChModeConfig(ADC_T *ADCx,
|
uint32_t Trig,
|
uint8_t Level,
|
uint8_t DmaEn,
|
uint8_t HwClrEN);
|
|
/**@} */
|
|
#ifdef __cplusplus
|
}
|
#endif
|
|
#endif //__PAN_ADC_H__
|
|
/*** (C) COPYRIGHT 2016 Panchip Technology Corp. ***/
|
