/**************************************************************************//**
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* @file adc.c
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* @version V1.00
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* $Revision: 2$
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* $Date: 16/02/25 15:53 $
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* @brief Panchip series ADC driver source file
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*
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* @note
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* Copyright (C) 2016 Panchip Technology Corp. All rights reserved.
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*****************************************************************************/
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#include "PanSeries.h"
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#include "pan_adc.h"
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#include "pan_sys.h"
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#include "math.h"
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/** @addtogroup Panchip_Device_Driver Panchip Device Driver
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@{
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*/
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/** @addtogroup Panchip_ADC_Driver ADC Driver
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@{
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*/
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/** @addtogroup Panchip_ADC_EXPORTED_FUNCTIONS ADC Exported Functions
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@{
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*/
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ADC_OPT_T m_adc_opt;
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uint32_t global_calc_vbat_mv = 3300;
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static void bubble_sort_uint16(uint16_t *arr, size_t len)
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{
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uint16_t temp;
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for (size_t i = 0; i < len - 1; i++) {
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for (size_t j = 0; j < len - 1 - i; j++) {
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if (arr[j] > arr[j + 1]) {
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temp = arr[j];
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arr[j] = arr[j + 1];
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arr[j + 1] = temp;
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}
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}
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}
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}
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static void bubble_sort_float(float *arr, size_t len)
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{
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float temp;
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for (size_t i = 0; i < len - 1; i++) {
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for (size_t j = 0; j < len - 1 - i; j++) {
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if (arr[j] > arr[j + 1]) {
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temp = arr[j];
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arr[j] = arr[j + 1];
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arr[j + 1] = temp;
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}
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}
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}
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}
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/**
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* @brief Init ADC config parameters
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* @param[in] ADCx Base address of ADC module
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* @param[in] buf_en Enable ADC buffer or not
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* @return None
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*/
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bool ADC_Init(ADC_T *ADCx, bool buf_en)
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{
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uint32_t tmpreg;
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ADCx->BV_CTL |= BIT0; // Enable Bias Voltage Ctrl
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ADCx->BV_CTL = (ADCx->BV_CTL & ~BIT1) | (buf_en ? BIT1 : 0u); // Enable or disable buffer
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if (!isFtDataValid)
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{
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return false;
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}
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if (m_adc_opt.ft_version >= 6)
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{
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ADCx->CTL2 = m_adc_opt.adc_ctrl2;
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ADCx->EXTSMPT = m_adc_opt.adc_extsmpt;
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}
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else
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{
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// bit13:11 0'b100, bit10:8 0'b101
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tmpreg = ADCx->CTL2;
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tmpreg &= ~(0x7ul << 8);
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tmpreg |= 5 << 8;
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tmpreg &= ~(0x7ul << 11);
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tmpreg |= 4 << 11;
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tmpreg &= ~(0x7ul << 20);
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tmpreg |= 7 << 20;
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tmpreg &= ~(0x7ul << 24);
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tmpreg |= 7 << 24;
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ADCx->CTL2 = tmpreg;
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ADCx->EXTSMPT = 0x00000008;
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}
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tmpreg = ADCx->BV_CTL;
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tmpreg &= ~(0x3Fu << 3);
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tmpreg |= m_adc_opt.adc_vbg_1v20_trim << 3;
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ADCx->BV_CTL = tmpreg;
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return true;
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}
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/**
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* @brief Prepare ADC VBG fitting curve paramters due to SoC VBAT level
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* @param[in] ADCx Base address of ADC module
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* @return None
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*/
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void ADC_PrepareVbgCalibData(ADC_T *ADCx)
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{
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// NOTE1: We assume ADC is already initialized!
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// NOTE2: We assume ADC input range is already specified!
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uint32_t chen_bkp = 0;
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uint32_t sample_code = 0;
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if (m_adc_opt.ft_version < 3) {
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// Only use in the SoC which ft_verison >= 3
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return;
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}
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if (ADCx->CTL2 & ADC_SEL_VREF_Msk) {
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// Only use when the ADC reference is 1.2v VBG
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return;
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}
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if (ADCx->CHEN) {
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chen_bkp = ADCx->CHEN;
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}
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// Enable channel 10 (internal channel connected to vbat/4)
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ADC_Open(ADCx, ADC_CHEN_CH10_VDD_4_Msk);
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// Power on ADC
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ADC_PowerOn(ADCx);
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// Delay a while to wait adc stable
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if (m_adc_opt.chip_info >= 0x20) {
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SYS_delay_10nop(500); // Delay 100us+
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} else {
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SYS_delay_10nop(10000); // Delay 3ms+
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}
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for (size_t i = 0; i < 8; i++) {
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/* Start sampling */
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ADC_StartConvert(ADC);
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/* Wait for sampling done */
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while (!ADC_IsDataValid(ADC)) {}
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/* Process sampling result data */
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sample_code += ADC_GetConversionData(ADC);
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// Delay 200us+ to wait adc stable
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if (m_adc_opt.chip_info < 0x20) {
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SYS_delay_10nop(1000);
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}
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}
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sample_code /= 8;
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// Power down ADC
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ADC_PowerDown(ADC);
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if (chen_bkp) {
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ADCx->CHEN = chen_bkp;
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}
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global_calc_vbat_mv = ((uint32_t)(m_adc_opt.adc_vbat_k / 10000.0 * sample_code + m_adc_opt.adc_vbat_b / 100.0));;
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}
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/**
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* @brief Convert adc code to voltage in uV
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* @param[in] ADCx Base address of ADC module
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* @param[in] adc_code Code sampled by ADC module
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* @return ADC sample voltage output in mV
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*/
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float ADC_OutputVoltage(ADC_T *ADCx, uint32_t adc_code)
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{
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float voltage_mv = 0;
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if (ADCx->CTL2 & ADC_SEL_VREF_Msk) // Ref src is Vbat
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{
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voltage_mv = m_adc_opt.adc_vdd_k / 10000.0 * adc_code + m_adc_opt.adc_vdd_b; // code to code
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voltage_mv = voltage_mv * global_calc_vbat_mv / 4096;
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}
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else // Ref src is ADC VBG (1.2v)
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{
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if (m_adc_opt.ft_version >= 3)
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{
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uint32_t calc_vbat_mv = global_calc_vbat_mv;
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uint32_t vol_list[] = {1800, 2100, 2400, 2700, 3000, 3300, 3600};
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float V1, V2;
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float A;
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uint8_t vol_index = 0;
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for (uint8_t i = 0; i < 7; i++)
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{
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if (calc_vbat_mv <= vol_list[0])
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{
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voltage_mv = (float)m_adc_opt.adc_vbg_kb[0].adc_vbg_k / 100000.0 * adc_code + m_adc_opt.adc_vbg_kb[0].adc_vbg_b / 100.0;
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break;
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}
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else if (calc_vbat_mv >= vol_list[6])
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{
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voltage_mv = (float)m_adc_opt.adc_vbg_kb[6].adc_vbg_k / 100000.0 * adc_code + m_adc_opt.adc_vbg_kb[6].adc_vbg_b / 100.0;
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break;
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}
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if (calc_vbat_mv < vol_list[i])
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{
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vol_index = i;
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V1 = (float)m_adc_opt.adc_vbg_kb[vol_index - 1].adc_vbg_k / 100000.0 * adc_code + m_adc_opt.adc_vbg_kb[vol_index - 1].adc_vbg_b / 100.0;
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V2 = (float)m_adc_opt.adc_vbg_kb[vol_index].adc_vbg_k / 100000.0 * adc_code + m_adc_opt.adc_vbg_kb[vol_index].adc_vbg_b / 100.0;
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A = (float)(calc_vbat_mv - vol_list[vol_index - 1]) / 300;
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voltage_mv = A * V2 + (1 - A) * V1;
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break;
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}
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}
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}
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else
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{
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voltage_mv = m_adc_opt.adc_vbg_k / 100000.0 * adc_code + m_adc_opt.adc_vbg_b / 100.0;
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}
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}
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return voltage_mv;
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}
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/**
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* @brief get caliration params relatd adc ft process
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* @param[in] ADC_OPT_T hold adc ft parameters
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* @return NULL
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*/
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void ADC_SetCalirationParams(OTP_STRUCT_T *opt)
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{
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m_adc_opt.chip_info = opt->m.chip_info;
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m_adc_opt.ft_version = opt->m.ft_version;
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m_adc_opt.adc_temp_volt = opt->m.adc_temp_volt;
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m_adc_opt.adc_vbg_1v20_trim = opt->m.adc_vbg_1v20_trim;
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m_adc_opt.adc_vbg_b = opt->m.adc_vbg_b;
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m_adc_opt.adc_vbg_k = opt->m.adc_vbg_k;
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m_adc_opt.adc_vdd_b = opt->m.adc_vdd_b;
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m_adc_opt.adc_vdd_k = opt->m.adc_vdd_k;
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m_adc_opt.current_temp_value = opt->m.current_temp_value;
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m_adc_opt.adc_vbat_k = opt->m_v2.adc_vbat_k;
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m_adc_opt.adc_vbat_b = opt->m_v2.adc_vbat_b;
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m_adc_opt.adc_vbat_dtemp_k = opt->m_v2.adc_vbat_dtemp_k;
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m_adc_opt.adc_vbat_dtemp_b = opt->m_v2.adc_vbat_dtemp_b;
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memcpy(m_adc_opt.adc_vbg_kb, opt->m_v2.adc_vbg_kb, sizeof(ADC_VBG_KB_T) * 7);
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m_adc_opt.adc_temp_k = opt->m_v2.adc_temp_k;
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m_adc_opt.adc_ctrl2 = opt->m_v2.adc_ctrl2;
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m_adc_opt.adc_extsmpt = opt->m_v2.adc_extsmpt;
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}
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/**
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* @brief Start sampling many data codes, trim several largest and smallest codes and calculate average valu
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* @param[in] ADCx Base address of ADC module
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* @param[in] sample_buf Buffer to temporarily store ADC sample code
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* @param[in] sample_cnt Total sampling count
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* @param[in] trim_cnt Total trim count, that means throw away the smallest trim_cnt/2 and largest trim_cnt/2 sample codes
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* @return ADC calculated sample code
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*/
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uint32_t ADC_SamplingCodeTrimMean(ADC_T *ADCx, uint16_t *sample_buf, uint32_t sample_cnt, uint32_t trim_cnt)
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{
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uint32_t sample_code = 0;
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// Handle exception
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if (sample_cnt <= trim_cnt) {
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return UINT32_MAX; // Error occurred
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}
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// Start sampling
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for (int i = 0; i < sample_cnt; i++) {
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ADC_StartConvert(ADCx);
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// Wait for sampling done
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while (!ADC_IsDataValid(ADCx)) {
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}
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// Process sampling result data
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sample_buf[i] = ADC_GetConversionData(ADCx);
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// Delay 200us+ to wait adc stable
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if (m_adc_opt.chip_info < 0x20) {
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SYS_delay_10nop(1000);
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}
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}
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// Filter out several largest and smallest data and calculate average value
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bubble_sort_uint16(sample_buf, sample_cnt);
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for (int i = trim_cnt / 2; i < (sample_cnt - trim_cnt / 2); i++) {
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sample_code += sample_buf[i];
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}
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sample_code /= sample_cnt - trim_cnt;
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return sample_code;
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}
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/**
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* @brief Measure SoC Temperature using the ADC internal Channel 9
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* @param[in] ADCx Base address of ADC module
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* @return ADC measured temperature in Celsius
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*/
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float ADC_MeasureSocTemperature(ADC_T *ADCx)
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{
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uint32_t u32TempReg = 0;
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float temp_param_k = (m_adc_opt.chip_info >= 0x20) ? (m_adc_opt.ft_version >= 6 ? m_adc_opt.adc_temp_k : 0.35) : -0.69; // t = k * (v - vFT) + tFT
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float voltage = 0;
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float temp_voltage_arr[128];
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// Enable ADC channel 9
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ADC_Open(ADCx, ADC_CHEN_CH9_TMP_Msk);
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// Change ADC Ref to ADC-VBG (1.2v) if is not
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if (ADCx->CTL2 & ADC_SEL_VREF_Msk) {
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ADC_SelInputRange(ADCx, ADC_INPUTRANGE_LOW);
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}
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// Prepare ADC vbg calib paramter due to currnet soc vbat after setting input range to the 0~1.2v ref
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ADC_PrepareVbgCalibData(ADCx);
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// Power on ADC
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ADC_PowerOn(ADCx);
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// Delay a while to wait adc stable
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if (m_adc_opt.chip_info >= 0x20) {
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SYS_delay_10nop(500); // Delay 100us+
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} else {
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SYS_delay_10nop(50000); // Delay 15ms+
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}
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// Start sampling
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for (int i = 0; i < 128; i++) {
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ADC_StartConvert(ADCx);
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// Wait for sampling done
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while (!ADC_IsDataValid(ADCx)) {
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}
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// Process sampling result data
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u32TempReg = ADC_GetConversionData(ADCx);
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temp_voltage_arr[i] = ADC_OutputVoltage(ADCx, u32TempReg);
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}
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// Power down ADC
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ADC_PowerDown(ADCx);
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// Filter out largest 8 and smallest 8 data and calculate average value
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bubble_sort_float(temp_voltage_arr, 128);
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for (int i = 8; i < 120; i++) {
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voltage += temp_voltage_arr[i];
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}
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voltage /= 112;
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// Calculate and return current temp by formula: t = k * (v - vFT) + tFT - tDelta
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return temp_param_k * (voltage - (double)m_adc_opt.adc_temp_volt / 10.0) + (double)m_adc_opt.current_temp_value / 100.0
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- (m_adc_opt.ft_version >= 5 ? ((double)m_adc_opt.adc_vbat_dtemp_k / 10000000.0 * global_calc_vbat_mv + (double)m_adc_opt.adc_vbat_dtemp_b / 1000.0) : 0);
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}
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/**
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* @brief Measure SoC Temperature More Fast using the ADC internal Channel 9
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* @param[in] ADCx Base address of ADC module
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* @return ADC measured temperature in Celsius
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*/
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float ADC_MeasureSocTemperatureFast(ADC_T *ADCx)
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{
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uint32_t temp_code = 0;
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float temp_param_k = (m_adc_opt.chip_info >= 0x20) ? (m_adc_opt.ft_version >= 6 ? m_adc_opt.adc_temp_k : 0.35) : -0.69; // t = k * (v - vFT) + tFT
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float voltage = 0;
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uint16_t temp_code_arr[128];
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// Check if current chip support this API
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if (m_adc_opt.chip_info < 0x20) {
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return -1.0f;
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}
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// Enable ADC channel 9
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ADC_Open(ADCx, ADC_CHEN_CH9_TMP_Msk);
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// Change ADC Ref to ADC-VBG (1.2v) if is not
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if (ADCx->CTL2 & ADC_SEL_VREF_Msk) {
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ADC_SelInputRange(ADCx, ADC_INPUTRANGE_LOW);
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}
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// Prepare ADC vbg calib paramter due to currnet soc vbat after setting input range to the 0~1.2v ref
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ADC_PrepareVbgCalibData(ADCx);
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// Power on ADC
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ADC_PowerOn(ADCx);
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// Delay a while to wait adc stable
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SYS_delay_10nop(500); // Delay 100us+
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// Start sampling
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for (int i = 0; i < 128; i++) {
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ADC_StartConvert(ADCx);
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// Wait for sampling done
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while (!ADC_IsDataValid(ADCx)) {
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}
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// Process sampling result data
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temp_code_arr[i] = ADC_GetConversionData(ADCx);
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}
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// Power down ADC
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ADC_PowerDown(ADCx);
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// Filter out largest 8 and smallest 8 data and calculate average value
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bubble_sort_uint16(temp_code_arr, 128);
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for (int i = 8; i < 120; i++) {
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temp_code += temp_code_arr[i];
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}
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temp_code /= 112;
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// Calculate voltage of temp sensor
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voltage = ADC_OutputVoltage(ADCx, temp_code);
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// Calculate and return current temp by formula: t = k * (v - vFT) + tFT - tDelta
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return temp_param_k * (voltage - (double)m_adc_opt.adc_temp_volt / 10.0) + (double)m_adc_opt.current_temp_value / 100.0
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- (m_adc_opt.ft_version >= 5 ? ((double)m_adc_opt.adc_vbat_dtemp_k / 10000000.0 * global_calc_vbat_mv + (double)m_adc_opt.adc_vbat_dtemp_b / 1000.0) : 0);
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}
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/**
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* @brief Measure SoC VBAT using the ADC internal Channel 10
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* @param[in] ADCx Base address of ADC module
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* @return ADC measured VBAT voltage in mV
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*/
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uint16_t ADC_MeasureSocVbat(ADC_T *ADCx)
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{
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uint32_t u32TempReg = 0;
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float voltage = 0;
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float temp_voltage_arr[32];
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// Enable channel 10 (internal channel connected to vbat/4)
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ADC_Open(ADCx, ADC_CHEN_CH10_VDD_4_Msk);
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// Change ADC Ref to ADC-VBG (1.2v) if is not
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if (ADCx->CTL2 & ADC_SEL_VREF_Msk) {
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ADC_SelInputRange(ADCx, ADC_INPUTRANGE_LOW);
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}
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// if (m_adc_opt.chip_info < 0x20) {
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// // Prepare ADC vbg calib paramter due to currnet soc vbat after setting input range to the 0~1.2v ref
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// ADC_PrepareVbgCalibData(ADCx);
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// }
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// Power on ADC
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ADC_PowerOn(ADCx);
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// Delay a while to wait adc stable
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if (m_adc_opt.chip_info >= 0x20) {
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SYS_delay_10nop(500); // Delay 100us+
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} else {
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SYS_delay_10nop(50000); // Delay 15ms+
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}
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// Start sampling
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for (int i = 0; i < 32; i++) {
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ADC_StartConvert(ADCx);
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// Wait for sampling done
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while (!ADC_IsDataValid(ADCx)) {
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}
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// Process sampling result data
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u32TempReg = ADC_GetConversionData(ADCx);
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if (m_adc_opt.ft_version >= 3) {
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temp_voltage_arr[i] = ((float)(m_adc_opt.adc_vbat_k / 10000.0 * u32TempReg + m_adc_opt.adc_vbat_b / 100.0));
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} else {
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temp_voltage_arr[i] = ADC_OutputVoltage(ADCx, u32TempReg);
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}
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}
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// Power down ADC
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ADC_PowerDown(ADCx);
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// Filter out largest 8 and smallest 8 data and calculate average value
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bubble_sort_float(temp_voltage_arr, 32);
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for (int i = 8; i < 24; i++) {
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voltage += temp_voltage_arr[i];
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}
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voltage /= 16;
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if (m_adc_opt.ft_version < 3) {
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voltage = (uint16_t)(4 * voltage + 0.5); // Rounding off
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}
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return voltage;
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}
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/**
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* @brief Disable ADC Power
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* @param[in] adc Base address of ADC module
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* @return None
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*/
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void ADC_Disable(ADC_T *ADCx)
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{
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// SYS->IPRST1 |= SYS_IPRST1_ADCRST_Msk;
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// SYS->IPRST1 &= ~SYS_IPRST1_ADCRST_Msk;
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ADCx->CTL &= ~ADC_CTL_ADCEN_Msk;
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return;
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}
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/**
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* @brief Disable ADC module
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* @param[in] adc Base address of ADC module
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* @return None
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*/
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void ADC_Close(void)
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{
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// SYS->IPRST1 |= SYS_IPRST1_ADCRST_Msk;
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// SYS->IPRST1 &= ~SYS_IPRST1_ADCRST_Msk;
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// return;
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}
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/**
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* @brief Configure the hardware trigger condition and enable hardware trigger
|
* @param[in] adc Base address of ADC module
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* @param[in] u32Source Decides the hardware trigger source. Valid values are:
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* - \ref ADC_TRIGGER_BY_EXT_PIN
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* - \ref ADC_TRIGGER_BY_PWM
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* @param[in] u32Param While ADC trigger by PWM, this parameter is used to set the delay between PWM
|
* trigger and ADC conversion. Valid values are from 0 ~ 0xFF, and actual delay
|
* time is (4 * u32Param * HCLK). While ADC trigger by external pin, this parameter
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* is used to set trigger condition. Valid values are:
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* - \ref ADC_FALLING_EDGE_TRIGGER
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* - \ref ADC_RISING_EDGE_TRIGGER
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* @return None
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*/
|
void ADC_EnableHWTrigger(ADC_T *ADCx,uint32_t Source,uint32_t TrgCondition)
|
{
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ADCx->CTL &= ~(ADC_TRIGGER_BY_PWM | ADC_RISING_EDGE_TRIGGER | ADC_CTL_HWTRGEN_Msk);
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if(Source == ADC_TRIGGER_BY_EXT_PIN) {
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ADCx->CTL &= ~(ADC_CTL_HWTRGSEL_Msk | ADC_CTL_HWTRGCOND_Msk);
|
ADCx->CTL |= (Source | TrgCondition);
|
} else {
|
ADCx->CTL |= Source;
|
}
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ADCx->CTL |= ADC_CTL_HWTRGEN_Msk;
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return;
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}
|
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/**
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* @brief Disable hardware trigger ADC function.
|
* @param[in] adc Base address of ADC module
|
* @return None
|
*/
|
void ADC_DisableHWTrigger(ADC_T *ADCx)
|
{
|
ADCx->CTL &= ~(ADC_TRIGGER_BY_PWM | ADC_RISING_EDGE_TRIGGER | ADC_CTL_HWTRGEN_Msk);
|
}
|
|
/**
|
* @brief Enable the interrupt(s) selected by u32Mask parameter.
|
* @param[in] adc Base address of ADC module
|
* @param[in] u32Mask The combination of interrupt status bits listed below. Each bit
|
* corresponds to a interrupt status. This parameter decides which
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* interrupts will be enabled.
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* - \ref ADC_ADIF_INT
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* - \ref ADC_CMP0_INT
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* - \ref ADC_CMP1_INT
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* @return None
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*/
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void ADC_EnableInt(ADC_T *ADCx, uint32_t Mask)
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{
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if(Mask & ADC_ADIF_INT)
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ADCx->CTL |= ADC_CTL_ADCIEN_Msk;
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if(Mask & ADC_CMP0_INT)
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ADCx->CMP0 |= ADC_CMP0_ADCMPIE_Msk;
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if(Mask & ADC_CMP1_INT)
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ADCx->CMP1 |= ADC_CMP1_ADCMPIE_Msk;
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return;
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}
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/**
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* @brief Disable the interrupt(s) selected by u32Mask parameter.
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* @param[in] adc Base address of ADC module
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* @param[in] u32Mask The combination of interrupt status bits listed below. Each bit
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* corresponds to a interrupt status. This parameter decides which
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* interrupts will be disabled.
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* - \ref ADC_ADIF_INT
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* - \ref ADC_CMP0_INT
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* - \ref ADC_CMP1_INT
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* @return None
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*/
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void ADC_DisableInt(ADC_T *ADCx, uint32_t Mask)
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{
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if(Mask & ADC_ADIF_INT)
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ADCx->CTL &= ~ADC_CTL_ADCIEN_Msk;
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if(Mask & ADC_CMP0_INT)
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ADCx->CMP0 &= ~ADC_CMP0_ADCMPIE_Msk;
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if(Mask & ADC_CMP1_INT)
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ADCx->CMP1 &= ~ADC_CMP1_ADCMPIE_Msk;
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return;
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}
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/**
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* @brief ADC PWM Sequential Mode Control.
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* @param[in] adc Base address of ADC module
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* @param[in] u32SeqTYPE This parameter decides which type will be selected.
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* - \ref ADC_SEQMODE_TYPE_23SHUNT
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* - \ref ADC_SEQMODE_TYPE_1SHUNT
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* @param[in] u32ModeSel This parameter decides which mode will be selected.
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* - \ref ADC_SEQMODE_MODESELECT_CH01
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* - \ref ADC_SEQMODE_MODESELECT_CH12
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* - \ref ADC_SEQMODE_MODESELECT_CH02
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* - \ref ADC_SEQMODE_MODESELECT_ONE
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* @return None
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*/
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void ADC_SeqModeEnable(ADC_T *ADCx, uint32_t SeqType, uint32_t ModeSel)
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{
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// Enable ADC Sequential Mode
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ADCx->SEQCTL = ADCx->SEQCTL | ADC_SEQCTL_SEQEN_Msk;
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// Select ADC Sequential Mode Type
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ADCx->SEQCTL = (ADCx->SEQCTL & ~(ADC_SEQCTL_SEQTYPE_Msk)) | (SeqType << ADC_SEQCTL_SEQTYPE_Pos);
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// Select ADC Sequential Mode Type
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ADCx->SEQCTL = (ADCx->SEQCTL & ~(ADC_SEQCTL_MODESEL_Msk)) | (ModeSel << ADC_SEQCTL_MODESEL_Pos);
|
|
return;
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}
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/**
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* @brief ADC PWM Sequential Mode PWM Trigger Source and type.
|
* @param[in] adc Base address of ADC module
|
* @param[in] u32SeqModeTriSrc1 This parameter decides first PWM trigger source and type.
|
*
|
*
|
* @return None
|
*/
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void ADC_SeqModeTriggerSrc(ADC_T *ADCx, uint32_t SeqModeTriSrc)
|
{
|
// Select PWM Trigger Source Selection for TRG1CTL or TRG2CTL
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if(ADCx->SEQCTL & ADC_SEQCTL_TRG_SEL_Msk)
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ADCx->SEQCTL = (ADCx->SEQCTL & ~(ADC_SEQCTL_TRG2CTL_Msk)) | (SeqModeTriSrc << ADC_SEQCTL_TRG2CTL_Pos);
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else
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ADCx->SEQCTL = (ADCx->SEQCTL & ~(ADC_SEQCTL_TRG1CTL_Msk)) | (SeqModeTriSrc << ADC_SEQCTL_TRG1CTL_Pos);
|
return;
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}
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/**
|
* @brief Configure the comparator 0 and enable it
|
* @param[in] adc Base address of ADC module
|
* @param[in] ChNum Specifies the source channel, valid value are from 0 to 7
|
* @param[in] CmpCondition Specifies the compare condition
|
* - \ref ADC_CMP0_LESS_THAN
|
* - \ref ADC_CMP0_GREATER_OR_EQUAL_TO
|
* @param[in] CmpData Specifies the compare value. Valid value are between 0 ~ 0x3FF
|
* @param[in] MatchCnt Specifies the match count setting, valid values are between 1~16
|
* @param[in] CmpSelect comparator select,0 or 1
|
* @return None
|
* @details For example, ADC_CompareEnable(ADC, 5, ADC_CMP_GREATER_OR_EQUAL_TO, 0x800, 10,ADC_COMPARATOR_0);
|
* Means ADC will assert comparator 0 flag if channel 5 conversion result is
|
* greater or equal to 0x800 for 10 times continuously.
|
* \hideinitializer
|
*/
|
void ADC_CompareEnable(ADC_T *ADCx,
|
uint32_t ChNum,
|
uint32_t CmpCondition,
|
uint32_t CmpData,
|
uint32_t MatchCnt,
|
uint32_t CmpSelect)
|
{
|
uint32_t TmpRegister;
|
|
if(ADC_COMPARATOR_1 == CmpSelect)
|
TmpRegister = ADC->CMP1;
|
else
|
TmpRegister = ADC->CMP0;
|
|
TmpRegister |= (ChNum << ADC_CMP0_CMPCH_Pos); //select compare channel
|
TmpRegister |= CmpCondition; //select compare condition(less than or greater than )
|
TmpRegister |= (CmpData << ADC_CMP0_CMPDAT_Pos); //set expect compare data
|
TmpRegister |= ((MatchCnt - 1) << ADC_CMP0_CMPMCNT_Pos); //set compare match count
|
if(ADC_COMPARATOR_1 == CmpSelect){
|
TmpRegister |= ADC_CMP1_ADCMPEN_Msk; //comparator enable
|
ADC->CMP1 = TmpRegister;
|
}
|
else{
|
TmpRegister |= ADC_CMP0_ADCMPEN_Msk; //comparator enable
|
ADC->CMP0 = TmpRegister;
|
}
|
}
|
|
/**
|
* @brief set ADC PWM one channel Sequential Mode configuration.
|
* @param[in] adc Base address of ADC module
|
* @param[in] Trig This parameter decides first PWM trigger source and type.
|
* @param[in] Level This parameter decides fifo threshold value.
|
* @param[in] DmaEn This parameter decides dma is used or not.
|
* @param[in] HwClrEN This parameter decides PWM trigger flag cleared by hardware or software.
|
* @param[in] AdcCh This parameter decides which adc channel selected.
|
* @return None
|
*/
|
void ADC_SeqOneChModeConfig(ADC_T *ADCx,
|
uint32_t Trig,
|
uint8_t Level,
|
uint8_t DmaEn,
|
uint8_t HwClrEN)
|
{
|
// ADC Hardware External trigger Enabled by PMW
|
ADC_EnableHWTrigger(ADCx, ADC_TRIGGER_BY_PWM, Trig);
|
ADC_SetFifoTrigLevel(ADCx,Level);
|
if(DmaEn)
|
ADC_DmaModeEnable(ADCx,ENABLE);
|
else
|
ADC_DmaModeEnable(ADCx,DISABLE);
|
|
// ADC Sequential mode & type Enable
|
ADC_SeqModeEnable(ADCx,ADC_SEQMODE_TYPE_23SHUNT,ADC_SEQMODE_MODESELECT_ONE);
|
ADC_SeqModeOneChEn(ADCx,ENABLE);
|
if(HwClrEN)
|
ADC_ClearByHw(ADCx,ENABLE);
|
else
|
ADC_ClearByHw(ADCx,DISABLE);
|
}
|
|
/*@}*/ /* end of group Panchip_ADC_EXPORTED_FUNCTIONS */
|
|
/*@}*/ /* end of group Panchip_ADC_Driver */
|
|
/*@}*/ /* end of group Panchip_Device_Driver */
|
|
/*** (C) COPYRIGHT 2016 Panchip Technology Corp. ***/
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