/**************************************************************************//**
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* @file pan_hal_spi.c
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* @version V0.0.0
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* $Revision: 1 $
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* $Date: 23/09/10 $
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* @brief Panchip series SPI (Serial Peripheral Interface) HAL source file.
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* @note
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* Copyright (C) 2023 Panchip Technology Corp. All rights reserved.
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*****************************************************************************/
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#include "pan_hal.h"
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SPI_HandleTypeDef spiHandleArray[2] =
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{
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{
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.pSpix = SPI0,
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.initObj = {0},
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.interruptObj = {0},
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.xferStat = SPI_STAT_NULL,
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.pTxBuffPtr = NULL,
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.txXferSize = 0,
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.txXferCount = 0,
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.pRxBuffPtr = NULL,
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.rxXferSize = 0,
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.rxXferCount = 0,
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.IRQn = SPI0_IRQn, // Adjust this to appropriate IRQn_Type value
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.rxIntCallback = NULL,
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.txIntCallback = NULL,
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.dmaSrc = DMAC_Peripheral_SPI0_Rx,
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.dmaDst = DMAC_Peripheral_SPI0_Tx,
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.errorCode = 0
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},
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{
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.pSpix = SPI1,
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.initObj = {0},
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.interruptObj = {0},
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.xferStat = SPI_STAT_NULL,
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.pTxBuffPtr = NULL,
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.txXferSize = 0,
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.txXferCount = 0,
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.pRxBuffPtr = NULL,
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.rxXferSize = 0,
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.rxXferCount = 0,
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.IRQn = SPI1_IRQn, // Adjust this to appropriate IRQn_Type value
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.rxIntCallback = NULL,
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.txIntCallback = NULL,
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.dmaSrc = DMAC_Peripheral_SPI1_Rx,
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.dmaDst = DMAC_Peripheral_SPI1_Tx,
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.errorCode = 0
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}
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};
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void HAL_SPI_Init(SPI_HandleTypeDef *pSpi)
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{
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uint32_t tmpreg = 0;
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//uint8_t baud_div = CalcDivisorByBaudrate(pSpi);
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if(SPI_IsSpiEnabled(pSpi->pSpix))
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SPI_DisableSpi(pSpi->pSpix);
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tmpreg = pSpi->pSpix->CR0;
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tmpreg &= ~(SPI_CR0_SPH_Msk | SPI_CR0_SPO_Msk | SPI_CR0_DSS_Msk);
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tmpreg |= (
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((pSpi->initObj.clkPhase << SPI_CR0_SPH_Pos) & SPI_CR0_SPH_Msk ) | \
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((pSpi->initObj.clkPolarity << SPI_CR0_SPO_Pos) & SPI_CR0_SPO_Msk ) | \
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((pSpi->initObj.dataSize << SPI_CR0_DSS_Pos) & SPI_CR0_DSS_Msk ) \
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);
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tmpreg &= ~(SPI_CR0_FRF_Msk);
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tmpreg |= (pSpi->initObj.format << SPI_CR0_FRF_Pos);
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tmpreg &= ~(SPI_CR0_SCR_Msk);
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// tmpreg |= ((pSpi->SPI_InitStruct->SPI_baudRateDiv-1) << SPI_CR0_SCR_Pos); //Fixed SCR to 0, only use CPSR to config baudrate
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//tmpreg |= ((baud_div-1) << SPI_CR0_SCR_Pos); //Fixed SCR to 0, only use CPSR to config baudrate
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tmpreg |= ((pSpi->initObj.baudrateDiv-1) << SPI_CR0_SCR_Pos); //Fixed SCR to 0, only use CPSR to config baudrate
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pSpi->pSpix->CR0 = tmpreg;
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//Baudrate Config, expect_baudrate = apb_clk / ((1 + SCR) * CPSR)
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pSpi->pSpix->CPSR = 2;//SPI_InitStruct->SPI_baudRateDiv;
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//role Select
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if(pSpi->initObj.role == SPI_RoleSlave)
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{
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pSpi->pSpix->CR1 |= SPI_CR1_MS_Msk;
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}
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else
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{
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pSpi->pSpix->CR1 &= ~SPI_CR1_MS_Msk;
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}
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SPI_EnableSpi(pSpi->pSpix);
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}
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void HAL_SPI_DeInit(SPI_HandleTypeDef *pSpi){
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SPI_DisableSpi(pSpi->pSpix);
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}
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void HAL_SPI_Init_INT(SPI_HandleTypeDef *pSpi){
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SPI_EnableIrq(pSpi->pSpix, pSpi->interruptObj.Mode);
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}
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void HAL_SPI_DeInit_INT(SPI_HandleTypeDef *pSpi){
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SPI_DisableIrq(pSpi->pSpix, pSpi->interruptObj.Mode);
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}
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// Receive multiple data from specified SPI, and return the size of actual data received
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static size_t HAL_SPI_RecvMultiDataAsync(SPI_T* pSpix, uint16_t* data, size_t expectRecvSize)
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{
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size_t i = 0;
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for (; i < expectRecvSize; i++)
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{
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// Fetch data from Rx FIFO until it's empty
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if (!SPI_IsRxFifoEmpty(pSpix))
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{
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data[i] = SPI_ReceiveData(pSpix);
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}
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else
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{
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break;
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}
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}
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return i;
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}
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// Send multiple data to specified SPI, and return the size of actual data sent
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static size_t HAL_SPI_SendMultiDataAsync(SPI_T* pSpix, const uint16_t* data, size_t expectSendSize)
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{
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size_t i = 0;
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for (; i < expectSendSize; i++)
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{
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// Fill data into Tx FIFO until it's full
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if (!SPI_IsTxFifoFull(pSpix))
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{
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SPI_SendData(pSpix, data[i]);
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}
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else
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{
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break;
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}
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}
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return i;
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}
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void HAL_SPI_SendData(SPI_HandleTypeDef *pSpi, uint16_t *pBuf, size_t size, uint32_t timeout)
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{
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pSpi->txXferSize = size;
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pSpi->txXferCount =0;
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pSpi->pTxBuffPtr = pBuf;
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while (pSpi->txXferCount < pSpi->txXferSize)
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{
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if (!SPI_IsTxFifoFull(pSpi->pSpix))
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{
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SPI_SendData(pSpi->pSpix, pSpi->pTxBuffPtr[pSpi->txXferCount++]);
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}
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}
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while(SPI_IsBusy(pSpi->pSpix)){}
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}
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uint16_t debug_shuzu[20];
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void HAL_SPI_ReceiveData(SPI_HandleTypeDef *pSpi, uint16_t *pBuf, size_t size, uint32_t timeout)
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{
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pSpi->rxXferCount = 0;
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pSpi->rxXferSize =size;
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pSpi->pRxBuffPtr = pBuf;
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if(pSpi->initObj.role == SPI_RoleMaster)
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{
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pSpi->txXferCount = 0;
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pSpi->txXferSize =size;
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while (!(pSpi->txXferCount == pSpi->txXferSize && pSpi->rxXferCount == pSpi->rxXferSize))
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{
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if (pSpi->txXferCount < pSpi->txXferSize)
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{
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if (!SPI_IsTxFifoFull(pSpi->pSpix)) {
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SPI_SendData(pSpi->pSpix, '\0');
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pSpi->txXferCount++;
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}
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}
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if (pSpi->rxXferCount < pSpi->rxXferSize)
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{
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if (!SPI_IsRxFifoEmpty(pSpi->pSpix)) {
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pSpi->pRxBuffPtr[pSpi->rxXferCount++] = SPI_ReceiveData(pSpi->pSpix);
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}
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}
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}
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}
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else if (pSpi->initObj.role == SPI_RoleSlave)
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{
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while (pSpi->rxXferCount < pSpi->rxXferSize)
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{
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if (!SPI_IsRxFifoEmpty(pSpi->pSpix))
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{
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pSpi->pRxBuffPtr[pSpi->rxXferCount++] = SPI_ReceiveData(pSpi->pSpix);
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// debug_shuzu[pSpi->rxXferCount++]= SPI_ReceiveData(pSpi->pSpix);
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}
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}
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}
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}
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void HAL_SPI_SendReceiveData (SPI_HandleTypeDef *pSpi, uint16_t* pSendBuf, size_t sendBufSize, uint16_t* pRecvBuf, size_t recvBufSize)
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{
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pSpi->rxXferCount = 0;
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pSpi->rxXferSize =recvBufSize;
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pSpi->pRxBuffPtr = pRecvBuf;
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pSpi->txXferCount = 0;
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pSpi->txXferSize =sendBufSize;
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pSpi->pTxBuffPtr = pSendBuf;
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while (!(pSpi->txXferCount == pSpi->txXferSize && pSpi->rxXferCount == pSpi->rxXferSize))
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{
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if (pSpi->txXferCount < pSpi->txXferSize)
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{
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pSpi->txXferCount += HAL_SPI_SendMultiDataAsync(pSpi->pSpix, (uint16_t*)(pSpi->pTxBuffPtr + pSpi->txXferCount), pSpi->txXferSize - pSpi->txXferCount);
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}
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if (pSpi->rxXferCount < pSpi->rxXferSize)
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{
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pSpi->rxXferCount += HAL_SPI_RecvMultiDataAsync(pSpi->pSpix, (uint16_t*)(pSpi->pRxBuffPtr + pSpi->rxXferCount), pSpi->rxXferSize - pSpi->rxXferCount);
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}
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}
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}
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void HAL_SPI_SendData_INT(SPI_HandleTypeDef *pSpi, uint16_t *pBuf, size_t size, SPI_CallbackFunc callback)
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{
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pSpi->xferStat = SPI_STAT_TX;
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/* Enable Interrupt of target SPI */
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// pSpi->interruptObj.Mode = SPI_IRQ_ALL;
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pSpi->txXferSize = size;
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pSpi->txXferCount =0;
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pSpi->pTxBuffPtr = pBuf;
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pSpi->txIntCallback = callback;
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// HAL_SPI_Init_INT(pSpi);
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SPI_EnableIrq(pSpi->pSpix, SPI_IRQ_TX_HALF_EMPTY);
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NVIC_EnableIRQ(pSpi->IRQn);
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}
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void HAL_SPI_ReceiveData_INT(SPI_HandleTypeDef *pSpi, uint16_t* pBuf, size_t size,SPI_CallbackFunc callback)
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{
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pSpi->xferStat = SPI_STAT_RX;
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pSpi->rxXferSize = size;
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pSpi->rxXferCount =0;
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pSpi->pRxBuffPtr = pBuf;
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pSpi->rxIntCallback = callback;
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SPI_EnableIrq(pSpi->pSpix, SPI_IRQ_RX_HALF_FULL | SPI_IRQ_RX_TIMEOUT);
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NVIC_EnableIRQ(pSpi->IRQn);
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}
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void HAL_SPI_SendReceiveData_INT(SPI_HandleTypeDef *pSpi, uint16_t* pSendBuf, size_t sendBufSize,SPI_CallbackFunc sendCallback, uint16_t* pRecvBuf, size_t recvBufSize,SPI_CallbackFunc recvCallback)
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{
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pSpi->xferStat = SPI_STAT_RXTX;
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pSpi->txXferSize = sendBufSize;
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pSpi->txXferCount =0;
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pSpi->pTxBuffPtr = pSendBuf;
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pSpi->txIntCallback = sendCallback;
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pSpi->rxXferSize = recvBufSize;
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pSpi->rxXferCount =0;
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pSpi->pRxBuffPtr = pRecvBuf;
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pSpi->rxIntCallback = recvCallback;
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SPI_EnableIrq(pSpi->pSpix, SPI_IRQ_ALL);
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NVIC_EnableIRQ(pSpi->IRQn);
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}
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uint32_t HAL_SPI_SendData_DMA(SPI_HandleTypeDef *pSpi, uint16_t *pBuf, size_t size,SPI_CallbackFunc callback)
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{
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DMAC_Init(DMA);
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NVIC_EnableIRQ(DMA_IRQn);
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SPI_EnableDmaTx(pSpi->pSpix);
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pSpi->xferStat = SPI_STAT_TX;
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pSpi->txXferCount =0;
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pSpi->txXferSize = size;
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pSpi->pTxBuffPtr =pBuf;
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uint32_t dmaChNum = 0xFF;
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/* Get free DMA channel */
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dmaChNum = DMAC_AcquireChannel(DMA);
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/* Enable DMA transfer interrupt */
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DMAC_ClrIntFlagMsk(DMA, dmaChNum, DMAC_FLAG_INDEX_TFR);
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DMAC_ClrIntFlagMsk(DMA, dmaChNum, DMAC_FLAG_INDEX_DSTTFR);
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DMAC_ClrIntFlagMsk(DMA, dmaChNum, DMAC_FLAG_INDEX_ERR);
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dma_mem2spi_config.PeripheralDst = pSpi->dmaDst;
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DMAC_Channel_Array[dmaChNum].ConfigTmp = dma_mem2spi_config;
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DMAC_Channel_Array[dmaChNum].CallbackSpi = callback;
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// DMAC_Channel_Array[dmaChNum].StopFlag = false;
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DMAC_Channel_Array[dmaChNum].pBuffPtr = (uint32_t *)pSpi->pTxBuffPtr;
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DMAC_Channel_Array[dmaChNum].XferSize = pSpi->txXferSize;
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DMAC_Channel_Array[dmaChNum].PeriMode = DMAC_Peri_SPI;
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DMAC_SetChannelConfig(DMA, dmaChNum, &DMAC_Channel_Array[dmaChNum].ConfigTmp);
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/* Condition check */
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uint32_t DataWidthInByteSrc = DMAC_Channel_Array[dmaChNum].ConfigTmp.DataWidthSrc;
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// uint32_t DataWidthInByteSrc = 1 << DMAC_Channel_Array[dmaChNum].ConfigTmp.DataWidthSrc;
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uint32_t IsNotDivisible = pSpi->txXferSize % DataWidthInByteSrc;
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uint32_t BlockSize = pSpi->txXferSize / DataWidthInByteSrc; //BlockSize = DataLen / DataWidthInByteSrc
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/* Start DMA Tx channel */
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DMAC_StartChannel(DMA, dmaChNum, pSpi->pTxBuffPtr, (void*)&(pSpi->pSpix->DR), BlockSize);
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return dmaChNum;
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}
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uint32_t HAL_SPI_ReceiveData_DMA(SPI_HandleTypeDef *pSpi, uint16_t *pBuf, size_t size, SPI_CallbackFunc callback)
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{
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DMAC_Init(DMA);
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NVIC_EnableIRQ(DMA_IRQn);
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pSpi->xferStat = SPI_STAT_RX;
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pSpi->rxXferCount =0;
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pSpi->rxXferSize = size;
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pSpi->pRxBuffPtr =pBuf;
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// Initialize the DMA controller
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uint32_t dmaChNum = 0xff;
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/* Get free DMA channel */
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dmaChNum = DMAC_AcquireChannel(DMA);
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/* Enable DMA transfer interrupt */
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DMAC_ClrIntFlagMsk(DMA, dmaChNum, DMAC_FLAG_INDEX_TFR);
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DMAC_ClrIntFlagMsk(DMA, dmaChNum, DMAC_FLAG_INDEX_SRCTFR);
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DMAC_ClrIntFlagMsk(DMA, dmaChNum, DMAC_FLAG_INDEX_ERR);
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dma_spi2mem_config.PeripheralSrc = pSpi->dmaSrc;
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DMAC_Channel_Array[dmaChNum].ConfigTmp = dma_spi2mem_config;
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DMAC_Channel_Array[dmaChNum].CallbackSpi = callback;
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// DMAC_Channel_Array[dmaChNum].StopFlag = false;
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DMAC_Channel_Array[dmaChNum].pBuffPtr = (uint32_t *)pSpi->pRxBuffPtr;
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DMAC_Channel_Array[dmaChNum].XferSize = pSpi->rxXferSize;
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DMAC_Channel_Array[dmaChNum].PeriMode = DMAC_Peri_SPI;
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DMAC_SetChannelConfig(DMA, dmaChNum, &DMAC_Channel_Array[dmaChNum].ConfigTmp);
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/* Condition check */
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uint32_t RxDataWidthInByteSrc = DMAC_Channel_Array[dmaChNum].ConfigTmp.DataWidthSrc;
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uint32_t RxIsNotDivisible = pSpi->rxXferSize % RxDataWidthInByteSrc;
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uint32_t RxBlockSize = pSpi->rxXferSize / RxDataWidthInByteSrc; //BlockSize = DataLen / DataWidthInByteSrc
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/*We should clear rx fifo before rx start*/
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while (!SPI_IsRxFifoEmpty(pSpi->pSpix)) {
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(void)(pSpi->pSpix->DR);
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}
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SPI_EnableDmaRx(pSpi->pSpix);
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/* Start DMA Rx channel */
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DMAC_StartChannel(DMA, dmaChNum, (void*)&(pSpi->pSpix->DR), pSpi->pRxBuffPtr, RxBlockSize);
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return dmaChNum;
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}
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static uint32_t HAL_SPI_SendData_DMA_ForSR(SPI_HandleTypeDef *pSpi, uint16_t *pBuf, size_t size,SPI_CallbackFunc callback)
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{
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SPI_EnableDmaTx(pSpi->pSpix);
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pSpi->xferStat = SPI_STAT_RXTX;
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pSpi->txXferCount =0;
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pSpi->txXferSize = size;
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pSpi->pTxBuffPtr =pBuf;
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uint32_t dmaChNum = 0xFF;
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/* Get free DMA channel */
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dmaChNum = DMAC_AcquireChannel(DMA);
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/* Enable DMA transfer interrupt */
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DMAC_ClrIntFlagMsk(DMA, dmaChNum, DMAC_FLAG_INDEX_TFR);
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DMAC_ClrIntFlagMsk(DMA, dmaChNum, DMAC_FLAG_INDEX_DSTTFR);
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DMAC_ClrIntFlagMsk(DMA, dmaChNum, DMAC_FLAG_INDEX_ERR);
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dma_mem2spi_config.PeripheralDst = pSpi->dmaDst;
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DMAC_Channel_Array[dmaChNum].ConfigTmp = dma_mem2spi_config;
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DMAC_Channel_Array[dmaChNum].CallbackSpi = callback;
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// DMAC_Channel_Array[dmaChNum].StopFlag = false;
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DMAC_Channel_Array[dmaChNum].pBuffPtr = (uint32_t *)pSpi->pTxBuffPtr;
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DMAC_Channel_Array[dmaChNum].XferSize = pSpi->txXferSize;
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DMAC_Channel_Array[dmaChNum].PeriMode = DMAC_Peri_SPI;
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DMAC_SetChannelConfig(DMA, dmaChNum, &DMAC_Channel_Array[dmaChNum].ConfigTmp);
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return dmaChNum;
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}
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static uint32_t HAL_SPI_ReceiveData_DMA_ForSR(SPI_HandleTypeDef *pSpi, uint16_t *pBuf, size_t size, SPI_CallbackFunc callback)
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{
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pSpi->xferStat = SPI_STAT_RXTX;
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pSpi->rxXferCount =0;
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pSpi->rxXferSize = size;
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pSpi->pRxBuffPtr =pBuf;
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// Initialize the DMA controller
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uint32_t dmaChNum = 0xff;
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/* Get free DMA channel */
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dmaChNum = DMAC_AcquireChannel(DMA);
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/* Enable DMA transfer interrupt */
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DMAC_ClrIntFlagMsk(DMA, dmaChNum, DMAC_FLAG_INDEX_TFR);
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DMAC_ClrIntFlagMsk(DMA, dmaChNum, DMAC_FLAG_INDEX_SRCTFR);
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DMAC_ClrIntFlagMsk(DMA, dmaChNum, DMAC_FLAG_INDEX_ERR);
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dma_spi2mem_config.PeripheralSrc = pSpi->dmaSrc;
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DMAC_Channel_Array[dmaChNum].ConfigTmp = dma_spi2mem_config;
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DMAC_Channel_Array[dmaChNum].CallbackSpi = callback;
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// DMAC_Channel_Array[dmaChNum].StopFlag = false;
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DMAC_Channel_Array[dmaChNum].pBuffPtr = (uint32_t *)pSpi->pRxBuffPtr;
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DMAC_Channel_Array[dmaChNum].XferSize = pSpi->rxXferSize;
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DMAC_Channel_Array[dmaChNum].PeriMode = DMAC_Peri_SPI;
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DMAC_SetChannelConfig(DMA, dmaChNum, &DMAC_Channel_Array[dmaChNum].ConfigTmp);
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while (!SPI_IsRxFifoEmpty(pSpi->pSpix)) {
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(void)(pSpi->pSpix->DR);
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}
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SPI_EnableDmaRx(pSpi->pSpix);
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return dmaChNum;
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}
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void HAL_SPI_SendReceiveData_DMA(SPI_HandleTypeDef *pSpi, uint16_t* pSendBuf, size_t sendBufSize,SPI_CallbackFunc sendCallback, uint16_t* pRecvBuf, size_t recvBufSize,SPI_CallbackFunc recvCallback)
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{
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uint32_t rxChNum = 0xFF;
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uint32_t txChNum = 0xFF;
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/* We should clear rx fifo before rx start */
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DMAC_Init(DMA);
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NVIC_EnableIRQ(DMA_IRQn);
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txChNum = HAL_SPI_SendData_DMA_ForSR(pSpi,pSendBuf,sendBufSize,sendCallback);
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rxChNum = HAL_SPI_ReceiveData_DMA_ForSR(pSpi,pRecvBuf,recvBufSize,recvCallback);
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/* Condition check */
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uint32_t RxDataWidthInByteSrc = DMAC_Channel_Array[rxChNum].ConfigTmp.DataWidthSrc;
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uint32_t RxIsNotDivisible = pSpi->rxXferSize % RxDataWidthInByteSrc;
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uint32_t RxBlockSize = pSpi->rxXferSize / RxDataWidthInByteSrc; //BlockSize = DataLen / DataWidthInByteSrc
|
|
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/* Condition check */
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uint32_t TxDataWidthInByteSrc = DMAC_Channel_Array[txChNum].ConfigTmp.DataWidthSrc;
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// uint32_t DataWidthInByteSrc = 1 << DMAC_Channel_Array[dmaChNum].ConfigTmp.DataWidthSrc;
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uint32_t TxIsNotDivisible = pSpi->txXferSize % TxDataWidthInByteSrc;
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uint32_t TxBlockSize = pSpi->txXferSize / TxDataWidthInByteSrc; //BlockSize = DataLen / DataWidthInByteSrc
|
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/* Start DMA Rx channel */
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DMAC_StartChannel(DMA, rxChNum, (void*)&(pSpi->pSpix->DR), pSpi->pRxBuffPtr, RxBlockSize);
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/* Start DMA Tx channel */
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DMAC_StartChannel(DMA, txChNum, pSpi->pTxBuffPtr, (void*)&(pSpi->pSpix->DR), TxBlockSize);
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}
|
|
static void SPI_HandleReceivedData(SPI_HandleTypeDef *pSpi)
|
{
|
while (!SPI_IsRxFifoEmpty(pSpi->pSpix))
|
{
|
pSpi->pRxBuffPtr[pSpi->rxXferCount++] = SPI_ReceiveData(pSpi->pSpix);
|
|
if (pSpi->rxXferCount >= pSpi->rxXferSize) // Rx buffer full // if (pSpi->rxXferCount >= pSpi->rxXferSize) //Rx buffer full
|
{
|
if (pSpi->rxIntCallback != NULL)
|
{
|
pSpi->rxIntCallback(SPI_CB_FLAG_INT, pSpi->pRxBuffPtr, pSpi->rxXferCount);
|
}
|
SPI_DisableIrq(pSpi->pSpix, SPI_IRQ_RX_HALF_FULL|SPI_IRQ_RX_TIMEOUT);
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break;
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}
|
}
|
}
|
|
static void SPI_HandleTransmittingData(SPI_HandleTypeDef *pSpi)
|
{
|
while (!SPI_IsTxFifoFull(pSpi->pSpix))
|
{
|
if (pSpi->txXferCount < pSpi->txXferSize)
|
{
|
SPI_SendData(pSpi->pSpix, pSpi->pTxBuffPtr[pSpi->txXferCount++]);
|
}
|
if (pSpi->txXferCount >= pSpi->txXferSize)
|
{
|
while(SPI_IsBusy(pSpi->pSpix)){}
|
SPI_DisableIrq(pSpi->pSpix, SPI_IRQ_TX_HALF_EMPTY);
|
if (pSpi->txIntCallback != NULL)
|
{
|
pSpi->txIntCallback(SPI_CB_FLAG_INT, pSpi->pTxBuffPtr, pSpi->txXferCount);
|
}
|
break;
|
}
|
}
|
if (pSpi->xferStat == SPI_STAT_TX) {
|
while (!SPI_IsRxFifoEmpty(pSpi->pSpix)) {
|
(void)(pSpi->pSpix->DR);
|
}
|
}
|
}
|
void SPI_HandleProc(SPI_HandleTypeDef *pSpi)
|
{
|
if (SPI_IsIrqActive(pSpi->pSpix, SPI_IRQ_RX_OVERRUN))
|
{
|
SPI_ClearIrq(pSpi->pSpix, SPI_IRQ_RX_OVERRUN); // Clear overrun INT flag manually
|
return;
|
}
|
|
if (SPI_IsIrqActive(pSpi->pSpix, SPI_IRQ_RX_HALF_FULL))
|
{
|
SPI_HandleReceivedData(pSpi);
|
}
|
else if (SPI_IsIrqActive(pSpi->pSpix, SPI_IRQ_RX_TIMEOUT))
|
{
|
SPI_HandleReceivedData(pSpi);
|
}
|
|
if (SPI_IsIrqActive(pSpi->pSpix, SPI_IRQ_TX_HALF_EMPTY))
|
{
|
SPI_HandleTransmittingData(pSpi);
|
}
|
}
|
|
void SPI0_IRQHandler(void)
|
{
|
SPI_HandleProc(&spiHandleArray[0]);
|
}
|
|
void SPI1_IRQHandler(void)
|
{
|
SPI_HandleProc(&spiHandleArray[1]);
|
}
|
