/**************************************************************************//**
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* @file PWM.c
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* @version V1.00
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* $Revision: 3 $
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* $Date: 19/11/18 19:41 $
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* @brief Panchip series PWM driver source file
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*
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* @note
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* Copyright (C) 2016 Panchip Technology Corp. All rights reserved.
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*****************************************************************************/
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#include "PanSeries.h"
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#include "pan_pwm.h"
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#include "pan_clk.h"
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/** @addtogroup Panchip_Device_Driver Panchip Device Driver
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@{
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*/
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/** @addtogroup Panchip_PWM_Driver PWM Driver
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@{
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*/
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/** @addtogroup Panchip_PWM_EXPORTED_FUNCTIONS PWM Exported Functions
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@{
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*/
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/**
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* @brief This function config PWM generator and get the nearest frequency in edge aligned auto-reload mode
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~7
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* @param[in] u32Frequency Target generator frequency
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* @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
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* @param[in] OperateType Target operation type.Valid value Edge-aligned,Center-Aligned,Precise Center-Aligned
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* @return Nearest frequency clock in nano second
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* @note Since every two channels, (0 & 1), (2 & 3), (4 & 5), (6 & 7) shares a prescaler. Call this API to configure PWM frequency may affect
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* existing frequency of other channel.
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*/
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uint32_t PWM_ConfigOutputChannel (PWM_T *pwm,
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uint32_t u32ChannelNum,
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uint32_t u32Frequency,
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uint32_t u32DutyCycle,
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PWM_OperateTypeDef OperateType)
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{
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uint32_t i = SystemCoreClock / u32Frequency;
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uint8_t u8Divider = 1, u8Prescale = 0xFF;
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uint16_t u16period = 0xFFFF;
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// uint32_t u32Hclk = SystemCoreClock;
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uint32_t u32clk;
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// Judge clock source
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if (!(CLK->APB1_CLK_CTRL & (0x1ul << ((u32ChannelNum / 2) + CLK_APB1CLK_PWM01_CLK_SEL_Pos))))
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{
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u32clk = CLK_GetPCLK1Freq();
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}
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else
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{
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if (CLK->CLK_TOP_CTRL_3V & CLK_TOPCTL_32K_CLK_SEL_Msk_3v)
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{
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u32clk = FREQ_XTL;
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}
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else
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{
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u32clk = FREQ_RCL;
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}
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}
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for (; u8Divider < 17; u8Divider <<= 1)
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{ // clk divider could only be 1, 2, 4, 8, 16
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/*u32Frequency = SystemCoreClock /((u8Prescale+1)*(u8Divider))/( PERIODn+1) ==>
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(u8Prescale+1)*(PERIODn+1) = SystemCoreClock/u32Frequency/u8Divider */
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i = (u32clk / u32Frequency) / u8Divider;
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/* If target value is larger than (u16period+1)*(u8Prescale+1), need to use a larger divider*/
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if (i > (0x10000 * 0x100))
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continue;
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/* u16period = 0xFFFF + 1, get a prescaler that u16period value is below 0xFFFF
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Must first determine a variable value, now we choose u16period*/
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if ((pwm->CLKPSC >> ((u32ChannelNum >> 1) * 8) & 0xff) > 0)
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{
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u8Prescale = (pwm->CLKPSC >> ((u32ChannelNum >> 1) * 8) & 0xff) + 1;
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}
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else
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{
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u8Prescale = (i + 0xFFFF) / 0x10000;
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}
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/* u8Prescale must at least be 2, otherwise the output stop*/
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if (u8Prescale < 3)
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u8Prescale = 2;
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/* (PERIODn+1) = i / u8Prescale */
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i /= u8Prescale;
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/*u16period must less than 0xFFFF*/
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if (i <= 0x10000)
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{
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if (i == 1)
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{
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u16period = 1; // Too fast, and PWM cannot generate expected frequency...
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}
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else
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{
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if (OperateType == OPERATION_EDGE_ALIGNED)
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u16period = i;
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else if (OperateType == OPERATION_CENTER_ALIGNED)
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u16period = i / 2;
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else if (OperateType == OPERATION_PRECISE_CENTER_ALIGNED)
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u16period = i;
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}
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break;
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}
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}
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/* Store return value here 'cos we're gonna change u8Divider & u8Prescale & u16period to the real value to fill into register*/
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i = u32clk / (u8Prescale * u8Divider * u16period);
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u8Prescale -= 1;
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if(OperateType == OPERATION_PRECISE_CENTER_ALIGNED)
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u16period = u16period;
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else
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u16period -= 1;
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/* convert to real register value*/
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if(u8Divider == 1)
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u8Divider = 4;
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else if (u8Divider == 2)
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u8Divider = 0;
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else if (u8Divider == 4)
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u8Divider = 1;
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else if (u8Divider == 8)
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u8Divider = 2;
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else // 16
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u8Divider = 3;
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/* every two channels share a prescaler*/
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pwm->CLKPSC = (pwm->CLKPSC & ~(PWM_CLKPSC_CLKPSC01_Msk << ((u32ChannelNum >> 1) * 8))) | (u8Prescale << ((u32ChannelNum >> 1) * 8));
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pwm->CLKDIV = (pwm->CLKDIV & ~(PWM_CLKDIV_CLKDIV0_Msk << (4 * u32ChannelNum))) | (u8Divider << (4 * u32ChannelNum));
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/*set cnt mode as auto reload*/
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/* PWM_SetCntMode(pwm,u32ChannelNum,PWM_CNTMODE_AUTO_RELOAD); */
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/*set cnt type as edge align*/
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PWM_SetAlignedType(pwm, u32ChannelNum, PWM_EDGE_ALIGNED);
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if((OperateType == OPERATION_CENTER_ALIGNED)||(OperateType == OPERATION_PRECISE_CENTER_ALIGNED)){
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/*set cnt type as center align*/
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PWM_SetAlignedType(pwm, u32ChannelNum, PWM_CENTER_ALIGNED);
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if(OperateType == OPERATION_PRECISE_CENTER_ALIGNED)
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PWM_EnablePCA(pwm); //Precise center-aligned type Enabled.
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else
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PWM_DisablePCA(pwm);
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}
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/*update compare data register, Duty ratio = (CMPn+1)/(PERIODn+1).*/
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if(u32DutyCycle == 0){
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*((__IO uint32_t *)((((uint32_t) & ((pwm)->CMPDAT0)) + u32ChannelNum * 4))) = 0;
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}else{
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if(OperateType == OPERATION_EDGE_ALIGNED){
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/*set cnt type as edge align compare data*/
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*((__IO uint32_t *)((((uint32_t) & ((pwm)->CMPDAT0)) + u32ChannelNum * 4))) = u32DutyCycle * (u16period + 1) / 100 - 1;
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}
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else if(OperateType == OPERATION_CENTER_ALIGNED){
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/*set cnt type as center align compare data*/
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*((__IO uint32_t *)((((uint32_t) & ((pwm)->CMPDAT0)) + u32ChannelNum * 4))) = u16period-(u32DutyCycle * (u16period + 1) / 100) ;
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}
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else if(OperateType == OPERATION_PRECISE_CENTER_ALIGNED){
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/*set cnt type as precise center align compare data*/
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*((__IO uint32_t *)((((uint32_t) & ((pwm)->CMPDAT0)) + u32ChannelNum * 4))) = (u16period-(u16period*u32DutyCycle/100))/2-1 ;
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}
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}
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/*update Counter data register*/
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*((__IO uint32_t *)((((uint32_t) & ((pwm)->PERIOD0)) + (u32ChannelNum) * 4))) = u16period;
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return(i);
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}
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/**
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* @brief This function configures PWM generator to set period/duty cycles and output level mode.
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~7
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* @param[in] u16PeriodCycle Target period cycles to set
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* @param[in] u16PulseCycle Target pulse (high level) cycles to set
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* @note IF u16PeriodCycle = 0 OR u16PulseCycle = 0, THEN the output is always low;
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* ELSE IF u16PeriodCycle < u16PulseCycle, THEN the output is always high;
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* ELSE the final output PWM waveform meets the following formulas:
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* Actual period cycles = u16PeriodCycle + 1
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* Actual high-level cycles = u16PulseCycle + 1
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* Actual low-level cycles = u16PeriodCycle - u16PulseCycle
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* Actual duty cycle = (u16PulseCycle + 1) / (u16PeriodCycle + 1)
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* @return None
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*/
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void PWM_SetPeriodAndDuty(PWM_T *pwm, uint32_t u32ChannelNum, uint16_t u16PeriodCycle, uint16_t u16PulseCycle)
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{
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PWM_SetCNR(pwm, u32ChannelNum, u16PeriodCycle);
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PWM_SetCMR(pwm, u32ChannelNum, u16PulseCycle);
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}
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/**
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* @brief This function start PWM module
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
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* Bit 0 is channel 0, bit 1 is channel 1...
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* @return None
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*/
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void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask)
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{
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uint32_t u32Mask = 0, i;
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for(i = 0; i < PWM_CHANNEL_NUM; i ++) {
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if(u32ChannelMask & (1 << i)) {
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u32Mask |= (PWM_CTL_CNTEN0_Msk << (i * 4));
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}
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}
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pwm->CTL |= u32Mask;
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}
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/**
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* @brief This function stop PWM module
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
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* Bit 0 is channel 0, bit 1 is channel 1...
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* @return None
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*/
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void PWM_Stop(PWM_T *pwm, uint32_t u32ChannelMask)
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{
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uint32_t i;
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for(i = 0; i < PWM_CHANNEL_NUM; i ++) {
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if(u32ChannelMask & (1 << i)) {
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*((__IO uint32_t *)((((uint32_t) & ((pwm)->PERIOD0)) + (i) * 4))) = 0;
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}
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}
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}
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/**
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* @brief This function stop PWM generation immediately by clear channel enable bit
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
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* Bit 0 is channel 0, bit 1 is channel 1...
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* @return None
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*/
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void PWM_ForceStop(PWM_T *pwm, uint32_t u32ChannelMask)
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{
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uint32_t u32Mask = 0, i;
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for(i = 0; i < PWM_CHANNEL_NUM; i ++) {
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if(u32ChannelMask & (1 << i)) {
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u32Mask |= (PWM_CTL_CNTEN0_Msk << (i * 4));
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}
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}
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pwm->CTL &= ~u32Mask;
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}
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/**
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* @brief This function enable output inverter of specified channel(s)
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
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* Bit 0 represents channel 0, bit 1 represents channel 1...
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* @return None
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* \hideinitializer
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*/
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void PWM_EnableOutputInverter(PWM_T *pwm, uint32_t u32ChannelMask)
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{
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//pwm->CTL &= ~(PWM_CTL_PINV0_Msk|PWM_CTL_PINV1_Msk|PWM_CTL_PINV2_Msk|PWM_CTL_PINV3_Msk|PWM_CTL_PINV4_Msk|PWM_CTL_PINV5_Msk|PWM_CTL_PINV6_Msk|PWM_CTL_PINV7_Msk);
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uint32_t tmpCtlReg = pwm->CTL;
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for(size_t i = 0; i < 8; i++)
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{
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if((u32ChannelMask) & (1 << i))
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tmpCtlReg |= (1 << (PWM_CTL_PINV0_Pos + (i * 4)));
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}
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pwm->CTL = tmpCtlReg;
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}
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/**
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* @brief This function disable output inverter of specified channel(s)
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelMask Combination of channels to disable. Each bit corresponds to a channel
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* Bit 0 represents channel 0, bit 1 represents channel 1...
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* @return None
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* \hideinitializer
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*/
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void PWM_DisableOutputInverter(PWM_T *pwm, uint32_t u32ChannelMask)
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{
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uint32_t tmpCtlReg = pwm->CTL;
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for(size_t i = 0; i < 8; i++)
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{
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if((u32ChannelMask) & (1 << i))
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tmpCtlReg &= ~(1 << (PWM_CTL_PINV0_Pos + (i * 4)));
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}
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pwm->CTL = tmpCtlReg;
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}
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#if 0
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/**
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* @brief This function enable selected channel to trigger ADC
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~7
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* @param[in] u32Condition The condition to trigger ADC. Combination of following conditions:
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* - \ref PWM_TRIGGER_ADC_CNTR_IS_0
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* - \ref PWM_TRIGGER_ADC_CNTR_IS_CMR_D
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* - \ref PWM_TRIGGER_ADC_CNTR_IS_CNR
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* - \ref PWM_TRIGGER_ADC_CNTR_IS_CMR_U
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* @return None
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*/
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void PWM_EnableADCTrigger (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
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{
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if(u32ChannelNum < 4) {
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pwm->ADCTCTL0 = (pwm->ADCTCTL0 & ~((PWM_TRIGGER_ADC_CNTR_IS_0 |
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PWM_TRIGGER_ADC_CNTR_IS_CMR_D |
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PWM_TRIGGER_ADC_CNTR_IS_CNR |
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PWM_TRIGGER_ADC_CNTR_IS_CMR_U ) << (8 * u32ChannelNum))) | (u32Condition << (8 * u32ChannelNum));
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} else {
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pwm->ADCTCTL1 = (pwm->ADCTCTL1 & ~((PWM_TRIGGER_ADC_CNTR_IS_0 |
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PWM_TRIGGER_ADC_CNTR_IS_CMR_D |
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PWM_TRIGGER_ADC_CNTR_IS_CNR |
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PWM_TRIGGER_ADC_CNTR_IS_CMR_U ) << (8 * (u32ChannelNum - 4)))) | (u32Condition << (8 * (u32ChannelNum - 4)));
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}
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}
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/**
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* @brief This function disable selected channel to trigger ADC
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~7
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* @return None
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*/
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void PWM_DisableADCTrigger (PWM_T *pwm, uint32_t u32ChannelNum)
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{
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if(u32ChannelNum < 4) {
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pwm->ADCTCTL0 = (pwm->ADCTCTL0 & ~((PWM_TRIGGER_ADC_CNTR_IS_0 |
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PWM_TRIGGER_ADC_CNTR_IS_CMR_D |
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PWM_TRIGGER_ADC_CNTR_IS_CNR |
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PWM_TRIGGER_ADC_CNTR_IS_CMR_U ) << (8 * u32ChannelNum)));
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} else {
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pwm->ADCTCTL1 = (pwm->ADCTCTL1 & ~((PWM_TRIGGER_ADC_CNTR_IS_0 |
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PWM_TRIGGER_ADC_CNTR_IS_CMR_D |
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PWM_TRIGGER_ADC_CNTR_IS_CNR |
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PWM_TRIGGER_ADC_CNTR_IS_CMR_U ) << (8 * (u32ChannelNum - 4))));
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}
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}
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/**
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* @brief This function clear selected channel trigger ADC flag
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~7
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* @param[in] u32Condition PWM triggered ADC flag to be cleared.
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* @return None
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*/
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void PWM_ClearADCTriggerFlag (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
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{
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if(u32ChannelNum < 4) {
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pwm->ADCTSTS0 |= (u32Condition << (8 * u32ChannelNum));
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} else {
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pwm->ADCTSTS1 |= (u32Condition << (8 * (u32ChannelNum - 4)));
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}
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}
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/**
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* @brief This function get selected channel trigger ADC flag
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* @param[in] pwm The base address of PWM module
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* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~7
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* @param[in] u32Condition PWM triggered ADC flag to be selected.
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* @return Get status of the selected channel trigger ADC
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*/
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uint32_t PWM_GetADCTriggerFlag (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
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{
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if(u32ChannelNum < 4) {
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return(pwm->ADCTSTS0 & (u32Condition << (8 * u32ChannelNum)) ? 1 : 0);
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} else {
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return(pwm->ADCTSTS1 & (u32Condition << (8 * (u32ChannelNum - 4))) ? 1 : 0);
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}
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}
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#endif
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/*@}*/ /* end of group Panchip_PWM_EXPORTED_FUNCTIONS */
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/*@}*/ /* end of group Panchip_PWM_Driver */
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/*@}*/ /* end of group Panchip_Device_Driver */
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/*** (C) COPYRIGHT 2016 Panchip Technology Corp. ***/
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