/**************************************************************************//**
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* @file timer.c
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* @version V1.00
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* $Revision: 2 $
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* $Date: 16/02/24 15:37 $
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* @brief Panchip series TIMER driver source file
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*
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* @note
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* Copyright (C) 2016 Panchip Technology Corp. All rights reserved.
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*****************************************************************************/
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#include "PanSeries.h"
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#include "pan_timer.h"
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#include "pan_clk.h"
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/** @addtogroup Panchip_Device_Driver Panchip Device Driver
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@{
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*/
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/** @addtogroup Panchip_TIMER_Driver TIMER Driver
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@{
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*/
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/** @addtogroup Panchip_TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions
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@{
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*/
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/**
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* @brief This API is used to configure timer to operate in specified mode
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* and frequency. If timer cannot work in target frequency, a closest
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* frequency will be chose and returned.
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* @param[in] timer The base address of Timer module
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* @param[in] cntMode Operation mode. Possible options are
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* - \ref TIMER_ONESHOT_MODE
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* - \ref TIMER_PERIODIC_MODE
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* - \ref TIMER_TOGGLE_MODE
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* - \ref TIMER_CONTINUOUS_MODE
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* @param[in] u32Freq Timer Target working frequency
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* @return Real Timer working frequency
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* @note After calling this API, Timer is \b NOT running yet. But could start timer running be calling
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* \ref TIMER_Start macro or program registers directly
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*/
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uint32_t TIMER_Open(TIMER_T *timer, TIMER_CntModeDef cntMode, uint32_t u32Freq)
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{
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uint32_t u32Clk = CLK_GetPeripheralFreq(timer);
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uint32_t u32Prescale = 0;
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uint32_t u32RealFreq = u32Freq;
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if (u32RealFreq > u32Clk)
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u32RealFreq = u32Clk;
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else if (u32RealFreq == 0)
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u32RealFreq = 1;
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u32Prescale = u32Clk / u32RealFreq - 1;
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if (u32Prescale > 0xFF)
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u32Prescale = 0xFF; //Prescale is 8bit in reg
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timer->CTL = ((timer->CTL & ~TIMER_CTL_PSC_Msk) |u32Prescale);
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timer->CTL = (( timer->CTL& ~TIMER_CTL_OPMODE_Msk)|cntMode);
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// Calc real frequency and return
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u32RealFreq = u32Clk / (u32Prescale + 1);
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return u32RealFreq;
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}
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/**
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* @brief This API stops Timer counting and disable the Timer interrupt function
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* @param[in] timer The base address of Timer module
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* @return None
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*/
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void TIMER_Close(TIMER_T *timer)
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{
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timer->CTL = 0;
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timer->EXTCTL = 0;
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}
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/**
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* @brief This API is used to create a delay loop for u32usec micro seconds
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* @param[in] timer The base address of Timer module
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* @param[in] u32Usec Delay period in micro seconds with 10 usec every step. Valid values are between 10~1000000 (10 micro second ~ 1 second)
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* @return None
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* @note This API overwrites the register setting of the timer used to count the delay time.
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* @note This API use polling mode. So there is no need to enable interrupt for the timer module used to generate delay
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*/
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void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec)
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{
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uint32_t u32Clk = CLK_GetPeripheralFreq(timer);
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uint32_t u32Prescale = 0, delay = SystemCoreClock / u32Clk;
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float fCmpr;
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// Clear current timer configuration
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timer->CTL = 0;
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timer->EXTCTL = 0;
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if(u32Clk == 10000) { // min delay is 100us if timer clock source is LIRC 10k
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u32Usec = ((u32Usec + 99) / 100) * 100;
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} else { // 10 usec every step
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u32Usec = ((u32Usec + 9) / 10) * 10;
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}
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if(u32Clk >= 0x2000000) {
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u32Prescale = 3; // real prescaler value is 4
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u32Clk >>= 2;
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} else if(u32Clk >= 0x1000000) {
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u32Prescale = 1; // real prescaler value is 2
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u32Clk >>= 1;
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}
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// u32Usec * u32Clk might overflow if using uint32_t
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fCmpr = (float)u32Usec * u32Clk / 1000000.0f;
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timer->CMP = (uint32_t)fCmpr;
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timer->CTL = TIMER_CTL_CNTEN_Msk | u32Prescale; // one shot mode
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// When system clock is faster than timer clock, it is possible timer active bit cannot set in time while we check it.
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// And the while loop below return immediately, so put a tiny delay here allowing timer start counting and raise active flag.
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for(; delay > 0; delay--) {
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__NOP();
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}
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while(timer->CTL & TIMER_CTL_ACTSTS_Msk);
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}
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void TIMER_SetCmpValue(TIMER_T *timer, TIMER0_CmpSelDef cmp_seq, uint32_t u32Value)
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{
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uint32_t cnt_per_apb_clks = 0, clk_src = 0;
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uint8_t psc_store_value = timer->CTL & TIMER_CTL_PSC_Msk;
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uint8_t compare_compensate = 0, remainder = FIXED_DEVIATION;
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/*count freq = apbclock / (psc + 1), so 1 hw timer count = (psc + 1) apb clks */
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cnt_per_apb_clks = psc_store_value + 1;
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if (timer == TIMER0) {
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clk_src = CLK->APB1_CLK_CTRL & CLK_APB1CLK_TMR0SRC_SEL_Msk;
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} else if(timer == TIMER1){
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clk_src = CLK->APB2_CLK_CTRL & CLK_APB2CLK_TMR1SRC_SEL_Msk;
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} else if(timer == TIMER2){
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clk_src = CLK->APB2_CLK_CTRL & CLK_APB2CLK_TMR2SRC_SEL_Msk;
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}
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/*timer clk source is apb clk */
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if (clk_src == 0) {
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if (FIXED_DEVIATION >= cnt_per_apb_clks) {
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compare_compensate = FIXED_DEVIATION / cnt_per_apb_clks;
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remainder = FIXED_DEVIATION - compare_compensate * cnt_per_apb_clks;
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}
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if (remainder * 2 >= cnt_per_apb_clks) {
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compare_compensate += 1;
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}
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}
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/*here has 12 apb clk for hw timer sync operation*/
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if (timer == TIMER0) {
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switch (cmp_seq) {
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case TMR0_COMPARATOR_SEL_CMP:
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timer->CMP = u32Value - compare_compensate;
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TIMER0->CTL |= (BIT0 << 8);
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break;
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case TMR0_COMPARATOR_SEL_CMP1:
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timer->CMP1 = u32Value - compare_compensate;
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TIMER0->CTL |= (BIT1 << 8);
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break;
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case TMR0_COMPARATOR_SEL_CMP2:
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timer->CMP2 = u32Value - compare_compensate;
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TIMER0->CTL |= (BIT2 << 8);
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break;
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default:
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timer->CMP = u32Value - compare_compensate;
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break;
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}
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} else if ((timer == TIMER1) || (timer == TIMER2)){
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timer->CMP = u32Value - compare_compensate;
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}
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}
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/*@}*/ /* end of group Panchip_TIMER_EXPORTED_FUNCTIONS */
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/*@}*/ /* end of group Panchip_TIMER_Driver */
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/*@}*/ /* end of group Panchip_Device_Driver */
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/*** (C) COPYRIGHT 2016 Panchip Technology Corp. ***/
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