/*
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* Copyright (C) 2021 Panchip Technology Corp. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Panchip series phy driver header file
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* @version V1.00
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* $Revision: 3 $
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* $Date: 21/11/19 18:33 $
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*/
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#ifndef __PRI_RHY_H__
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#define __PRI_RHY_H__
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#include <stdint.h>
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/**
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* @brief Phy Interface
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* @defgroup phy_interface Phy Interface
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* @{
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*/
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/**@defgroup PHY_SELECT_FLAG Phy type select
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* @brief Phy type select definitions
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* @{ */
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enum tx_rx_phy
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{
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LE_NO_CHANGE = 0x00,
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LE_1M = 0x01,
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LE_2M = 0x02,
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LE_CODED_S8 = 0x03,
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LE_CODED = 0x04,
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LE_250K = 0x05,
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};
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/**@} */
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/**@defgroup PHY_ACTION_FLAG Phy action select
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* @brief Phy action select definitions
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* @{ */
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typedef enum llhw_phy_strt_stp_phy
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{
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LLHWC_PHY_START,
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LLHWC_PHY_STOP
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} llhw_phy_strt_stp_phy_e;
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/**@} */
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/**
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* @brief Reset phy.
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* @retval None
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*/
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void PHY_reset(void);
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/**
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* @brief Configures the channel.
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* @param chan: channel num
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* @retval None
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*/
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void PHY_SetChConfig(uint8_t chan);
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/**
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* @brief Phy init.
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* @retval None
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*/
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void PHY_init(void);
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/**
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* @brief Gonfigures the send and receive sequence.
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* @param phy: select phy
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* @retval None
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*/
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void PHY_SetTrxSeq_prf_LR(enum tx_rx_phy phy);
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void PHY_SetTrxSeq_prf_250K(enum tx_rx_phy phy);
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/**
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* @brief Gonfigures the send and receive time.
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* @param phy: select phy
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* @param tx1rx0: select tx or rx mode
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* @retval None
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*/
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uint8_t phy_time_cfg(uint8_t phy, uint8_t tx1rx0);
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/**
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* @brief Reset channel config.
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* @retval None
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*/
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void PHY_ResetChannel(void);
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/**
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* @brief Start or stop phy action.
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* @param phy_state: phy action select
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* @retval None
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*/
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void PHY_strt_stp(llhw_phy_strt_stp_phy_e phy_state);
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/**
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* @brief Write fifo batch config .
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* @param command: command select
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* @param cmd_len: command lenth
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* @param ptr_rsp_value: point to response value
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* @retval None
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*/
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uint32_t PHY_WriteCfgFifoBatch(const uint32_t *command, const uint32_t cmd_len, uint32_t *ptr_rsp_value);
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void PHY_set_tx_pwr(int8_t tx_pwr);
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uint32_t PHY_SeqRamInit(void);
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void panchip_prf_reduce_trx_time(bool reduce_flag);
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extern const uint32_t init_slp[];
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extern const uint32_t init_stdby[];
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extern const uint32_t init_slp_to_stdby[];
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extern const uint32_t reset[];
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extern const uint32_t phy_init[];
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extern const uint32_t pre_tx_interpacket[];
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extern const uint32_t pre_tx_interpacket_LR[];
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extern const uint32_t pre_tx_interpacket_2M[];
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extern const uint32_t pre_tx_interpacket_250K[];
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extern const uint32_t post_tx_interpacket[];
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extern const uint32_t pre_rx_interpacket[];
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extern const uint32_t pre_rx_interpacket_LR[];
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extern const uint32_t pre_rx_interpacket_2M[];
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extern const uint32_t pre_rx_interpacket_250K[];
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extern const uint32_t post_rx_interpacket[];
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extern const uint32_t pre_evnt[];
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extern const uint32_t post_evnt[];
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extern uint32_t channel_init[];
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extern const uint32_t init_constant_tone[];
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extern const uint32_t init_pll_bw_cal[];
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extern const uint32_t init_slp_size;
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extern const uint32_t init_stdby_size;
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extern const uint32_t init_slp_to_stdby_size;
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extern const uint32_t reset_size;
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extern uint32_t phy_init_size;
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extern uint32_t pre_tx_interpacket_size;
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extern uint32_t pre_tx_interpacket_LR_size;
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extern uint32_t pre_tx_interpacket_2M_size;
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extern uint32_t post_tx_interpacket_size;
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extern uint32_t pre_rx_interpacket_size;
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extern uint32_t pre_rx_interpacket_LR_size;
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extern uint32_t pre_rx_interpacket_2M_size;
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extern uint32_t post_rx_interpacket_size;
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extern uint32_t pre_evnt_size;
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extern uint32_t post_evnt_size;
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extern const uint32_t channel_init_size;
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extern uint32_t pre_tx_interpacket_250K_size;
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extern uint32_t pre_rx_interpacket_250K_size;
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extern uint32_t init_constant_tone_size;
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extern const uint32_t init_pll_bw_cal_size;
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extern const uint8_t phy_ch_cfg_reg;
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extern const uint8_t tx_pwr_cfg_reg;
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extern const uint8_t rssi_out_phy_reg_addrs;
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/**@} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __PRI_RHY_H__ */
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