/*
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* Copyright (c) 2020 Oticon A/S
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* Copyright (c) 2021 Codecoup
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* This header defines replacements for inline
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* ARM Cortex-M CMSIS intrinsics.
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*/
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#ifndef BOARDS_POSIX_NRF52_BSIM_CMSIS_H
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#define BOARDS_POSIX_NRF52_BSIM_CMSIS_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Implement the following ARM intrinsics as no-op:
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* - ARM Data Synchronization Barrier
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* - ARM Data Memory Synchronization Barrier
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* - ARM Instruction Synchronization Barrier
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* - ARM No Operation
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*/
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#ifndef __DMB
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#define __DMB()
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#endif
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#ifndef __DSB
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#define __DSB()
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#endif
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#ifndef __ISB
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#define __ISB()
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#endif
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#ifndef __NOP
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#define __NOP()
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#endif
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void NVIC_SystemReset(void);
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void __disable_irq(void);
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void __enable_irq(void);
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uint32_t __get_PRIMASK(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* BOARDS_POSIX_NRF52_BSIM_CMSIS_H */
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