/*
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* Licensed to the Apache Software Foundation (ASF) under one
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* or more contributor license agreements. See the NOTICE file
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* distributed with this work for additional information
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* regarding copyright ownership. The ASF licenses this file
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* to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance
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* with the License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing,
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* software distributed under the License is distributed on an
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* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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* KIND, either express or implied. See the License for the
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* specific language governing permissions and limitations
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* under the License.
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*/
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#include <assert.h>
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#include <string.h>
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#include <os/mynewt.h>
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#include <nimble/hci_common.h>
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#include <nimble/transport.h>
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#include <nimble/transport/hci_h4.h>
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#include "am_mcu_apollo.h"
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#define HCI_CMD_HDR_LEN (3) /*!< \brief Command packet header length */
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/* Tx power level in dBm. */
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typedef enum {
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TX_POWER_LEVEL_MINUS_10P0_dBm = 0x4,
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TX_POWER_LEVEL_MINUS_5P0_dBm = 0x5,
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TX_POWER_LEVEL_0P0_dBm = 0x8,
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TX_POWER_LEVEL_PLUS_3P0_dBm = 0xF,
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TX_POWER_LEVEL_INVALID = 0x10,
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} txPowerLevel_t;
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/* Structure for holding outgoing HCI packets. */
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typedef struct {
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uint32_t len;
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uint32_t data[MYNEWT_VAL(BLE_TRANSPORT_APOLLO3_MAX_TX_PACKET) / sizeof(uint32_t)];
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} hci_drv_write_t;
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uint32_t g_read_buf[MYNEWT_VAL(BLE_TRANSPORT_APOLLO3_MAX_RX_PACKET) / sizeof(uint32_t)];
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/* BLE module handle for Ambiq HAL functions */
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void *ble_handle;
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uint8_t g_ble_mac_address[6] = {0};
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static struct hci_h4_sm hci_apollo3_h4sm;
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static void
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apollo3_ble_hci_trans_rx_process(void)
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{
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uint32_t len;
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int rlen;
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uint8_t *buf = (uint8_t *)g_read_buf;
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am_hal_ble_blocking_hci_read(ble_handle, (uint32_t *)buf, &len);
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/* NOTE: Ambiq Apollo3 controller does not have local supported lmp features implemented
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* The command will always return 0 so we overwrite the buffer here
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*/
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if(buf[4] == 0x03 && buf[5] == 0x10 && len == 15) {
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memset(&buf[11], 0x60, sizeof(uint8_t));
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}
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rlen = hci_h4_sm_rx(&hci_apollo3_h4sm, buf, len);
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assert(rlen >= 0);
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}
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/* Interrupt handler that looks for BLECIRQ. This gets set by BLE core when there is something to read */
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static void
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apollo3_hci_int(void)
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{
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uint32_t int_status;
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/* Read and clear the interrupt status. */
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int_status = am_hal_ble_int_status(ble_handle, true);
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am_hal_ble_int_clear(ble_handle, int_status);
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/* Handle any DMA or Command Complete interrupts. */
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am_hal_ble_int_service(ble_handle, int_status);
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/* If this was a BLEIRQ interrupt, attempt to start a read operation. */
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if (int_status & AM_HAL_BLE_INT_BLECIRQ)
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{
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/* Lower WAKE */
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am_hal_ble_wakeup_set(ble_handle, 0);
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/* Call read function to pull in data from controller */
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apollo3_ble_hci_trans_rx_process();
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}
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else {
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assert(0);
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}
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}
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/* Boot the radio. */
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uint32_t
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apollo3_hci_radio_boot(bool is_cold_boot)
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{
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uint32_t xtal_retry_cnt = 0;
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uint32_t am_boot_status;
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am_hal_mcuctrl_device_t device_info;
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am_hal_ble_config_t ble_config =
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{
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/* Configure the HCI interface clock for 6 MHz */
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.ui32SpiClkCfg = AM_HAL_BLE_HCI_CLK_DIV8,
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/* Set HCI read and write thresholds to 32 bytes each. */
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.ui32ReadThreshold = 32,
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.ui32WriteThreshold = 32,
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/* The MCU will supply the clock to the BLE core. */
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.ui32BleClockConfig = AM_HAL_BLE_CORE_MCU_CLK,
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/* Note: These settings only apply to Apollo3 A1/A2 silicon, not B0 silicon.
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* Default settings for expected BLE clock drift (measured in PPM).
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*/
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.ui32ClockDrift = 0,
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.ui32SleepClockDrift = 50,
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/* Default setting - AGC Enabled */
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.bAgcEnabled = true,
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/* Default setting - Sleep Algo enabled */
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.bSleepEnabled = true,
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/* Apply the default patches when am_hal_ble_boot() is called. */
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.bUseDefaultPatches = true,
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};
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/* Configure and enable the BLE interface. */
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am_boot_status = AM_HAL_STATUS_FAIL;
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while (am_boot_status != AM_HAL_STATUS_SUCCESS) {
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am_hal_pwrctrl_low_power_init();
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am_hal_ble_initialize(0, &ble_handle);
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am_hal_ble_power_control(ble_handle, AM_HAL_BLE_POWER_ACTIVE);
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am_hal_ble_config(ble_handle, &ble_config);
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/*
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* Delay 1s for 32768Hz clock stability. This isn't required unless this is
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* our first run immediately after a power-up.
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*/
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if (is_cold_boot) {
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os_time_delay(OS_TICKS_PER_SEC);
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}
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/* Attempt to boot the radio. */
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am_boot_status = am_hal_ble_boot(ble_handle);
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/* Check our status, exit if radio is running */
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if (am_boot_status == AM_HAL_STATUS_SUCCESS) {
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break;
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}
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else if (am_boot_status == AM_HAL_BLE_32K_CLOCK_UNSTABLE) {
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/* If the radio is running, but the clock looks bad, we can try to restart. */
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am_hal_ble_power_control(ble_handle, AM_HAL_BLE_POWER_OFF);
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am_hal_ble_deinitialize(ble_handle);
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/* We won't restart forever. After we hit the maximum number of retries, we'll just return with failure. */
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if (xtal_retry_cnt++ < MYNEWT_VAL(BLE_TRANSPORT_APOLLO3_MAX_XTAL_RETRIES)) {
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os_time_delay(OS_TICKS_PER_SEC);
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}
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else {
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return SYS_EUNKNOWN;
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}
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}
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else {
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am_hal_ble_power_control(ble_handle, AM_HAL_BLE_POWER_OFF);
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am_hal_ble_deinitialize(ble_handle);
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/*
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* If the radio failed for some reason other than 32K Clock
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* instability, we should just report the failure and return.
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*/
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return SYS_EUNKNOWN;
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}
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}
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/* Set the BLE TX Output power to 0dBm. */
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am_hal_ble_tx_power_set(ble_handle, TX_POWER_LEVEL_0P0_dBm);
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/* Enable interrupts for the BLE module. */
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am_hal_ble_int_clear(ble_handle, (AM_HAL_BLE_INT_CMDCMP |
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AM_HAL_BLE_INT_DCMP |
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AM_HAL_BLE_INT_BLECIRQ));
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am_hal_ble_int_enable(ble_handle, (AM_HAL_BLE_INT_CMDCMP |
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AM_HAL_BLE_INT_DCMP |
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AM_HAL_BLE_INT_BLECIRQ));
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/* When it's is_cold_boot, it will use Apollo's Device ID to form Bluetooth address. */
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if (is_cold_boot) {
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am_hal_mcuctrl_info_get(AM_HAL_MCUCTRL_INFO_DEVICEID, &device_info);
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/* Bluetooth address formed by ChipID1 (32 bits) and ChipID0 (8-23 bits). */
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memcpy(g_ble_mac_address, &device_info.ui32ChipID1, sizeof(device_info.ui32ChipID1));
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/* ui32ChipID0 bit 8-31 is test time during chip manufacturing */
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g_ble_mac_address[4] = (device_info.ui32ChipID0 >> 8) & 0xFF;
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g_ble_mac_address[5] = (device_info.ui32ChipID0 >> 16) & 0xFF;
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}
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NVIC_EnableIRQ(BLE_IRQn);
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return 0;
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}
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/* Wake update helper function */
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static void
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apollo3_update_wake(void)
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{
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AM_CRITICAL_BEGIN;
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/* Set WAKE if there's something in the write queue, but not if SPISTATUS or IRQ is high. */
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if ((BLEIFn(0)->BSTATUS_b.SPISTATUS == 0) && (BLEIF->BSTATUS_b.BLEIRQ == false)) {
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am_hal_ble_wakeup_set(ble_handle, 1);
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/* If we've set wakeup, but IRQ came up at the same time, we should just lower WAKE again. */
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if (BLEIF->BSTATUS_b.BLEIRQ == true) {
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am_hal_ble_wakeup_set(ble_handle, 0);
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}
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}
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AM_CRITICAL_END;
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}
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/*
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* Function used by the BLE stack to send HCI messages to the BLE controller.
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* The payload is placed into a queue and the controller is turned on. When it is ready
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* an interrupt will fire to handle sending a message
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*/
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static uint8_t
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apollo3_hci_write(uint8_t type, uint16_t len, uint8_t *data)
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{
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uint8_t *write_ptr;
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hci_drv_write_t write_buf;
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/* comparison compensates for the type byte at index 0. */
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if (len > (MYNEWT_VAL(BLE_TRANSPORT_APOLLO3_MAX_TX_PACKET)-1)) {
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return 0;
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}
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/* Set all of the fields in the hci write structure. */
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write_buf.len = len + 1;
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write_ptr = (uint8_t *) write_buf.data;
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*write_ptr++ = type;
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for (uint32_t i = 0; i < len; i++) {
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write_ptr[i] = data[i];
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}
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/* Wake up the BLE controller. */
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apollo3_update_wake();
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/* Wait on SPI status before writing */
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while (BLEIFn(0)->BSTATUS_b.SPISTATUS) {
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os_time_delay(1);
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}
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am_hal_ble_blocking_hci_write(ble_handle, AM_HAL_BLE_RAW, write_buf.data, write_buf.len);
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return 0;
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}
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static int
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apollo3_ble_hci_acl_tx(struct os_mbuf *om)
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{
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struct os_mbuf *x;
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int rc = 0;
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x = om;
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while (x) {
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rc = apollo3_hci_write(HCI_H4_ACL, x->om_len, x->om_data);
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if (rc < 0) {
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break;
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}
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x = SLIST_NEXT(x, om_next);
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}
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os_mbuf_free_chain(om);
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return (rc < 0) ? BLE_ERR_MEM_CAPACITY : 0;
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}
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static int
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apollo3_ble_hci_frame_cb(uint8_t pkt_type, void *data)
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{
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int rc;
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switch (pkt_type) {
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case HCI_H4_ACL:
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rc = ble_transport_to_hs_acl(data);
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break;
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case HCI_H4_EVT:
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rc = ble_transport_to_hs_evt(data);
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break;
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default:
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assert(0);
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break;
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}
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return rc;
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}
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static void
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apollo3_ble_hci_init(void)
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{
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SYSINIT_ASSERT_ACTIVE();
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/* Enable interrupt to handle read based on BLECIRQ */
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NVIC_SetVector(BLE_IRQn, (uint32_t)apollo3_hci_int);
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/* Initial coldboot configuration */
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apollo3_hci_radio_boot(1);
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}
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int
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ble_transport_to_ll_cmd_impl(void *buf)
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{
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int rc;
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uint8_t *cmd = buf;
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int len = HCI_CMD_HDR_LEN + cmd[2];
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rc = apollo3_hci_write(HCI_H4_CMD, len, cmd);
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ble_transport_free(cmd);
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return (rc < 0) ? BLE_ERR_MEM_CAPACITY : 0;
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}
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int
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ble_transport_to_ll_acl_impl(struct os_mbuf *om)
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{
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return apollo3_ble_hci_acl_tx(om);
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}
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void
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ble_transport_ll_init(void)
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{
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hci_h4_sm_init(&hci_apollo3_h4sm, &hci_h4_allocs_from_ll,
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apollo3_ble_hci_frame_cb);
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apollo3_ble_hci_init();
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}
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