Ø 0í? ÀÙ^ R..\..\..\modules\hal\panchip\panplat\pan1070\bsp\radio\prf_lib\include\comm_prf.h ºÝµ öÙ` T..\..\..\modules\hal\panchip\panplat\pan1070\bsp\radio\prf_lib\include\pan_pri_rf.h ºÝµ %ÙX L..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\PanSeries.h ºÝµ ÄÙ8 ,C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h Ü Íò Ù9 -C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdlib.h Ü Íò 8Ù9 -C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h Ü Íò $Ù9 -C:\Keil_v5\ARM\ARMCC\Bin\..\include\string.h Ü Íò #ÙV J..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\core_cm0.h ºÝµ {Ù[ O..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\cmsis_version.h ºÝµ õÙ\ P..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\cmsis_compiler.h ºÝµ ÙY M..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\cmsis_armcc.h ºÝµ ùÙ_ S..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\system_PanSeries.h ºÝµ ²Ù: .C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdbool.h Ü Íò ÁÙZ N..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_sys_log.h ºÝµ ¬ÙV J..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_sys.h ºÝµ UÙV J..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_clk.h ºÝµ zÙV J..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_adc.h ºÝµ ZÙV J..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_fmc.h ºÝµ LÙW K..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_dmac.h ºÝµ ëÙW K..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_gpio.h ºÝµ ÑÙV J..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_spi.h ºÝµ 6ÙW K..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_uart.h ºÝµ ÄÙV J..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_i2c.h ºÝµ ÙX L..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_timer.h ºÝµ ]ÙV J..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_pwm.h ºÝµ .ÙV J..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_wdt.h ºÝµ 3ÙW K..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_wwdt.h ºÝµ ºÙU I..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_lp.h ºÝµ ÚÙX L..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_efuse.h ºÝµ Ù` T..\..\..\modules\hal\panchip\panplat\pan1070\bsp\radio\prf_lib\include\pan_pri_rf.h ºÝµ %ÙZ N..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_clktrim.h ºÝµ ¶ÙX L..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_power.h ºÝµ ÙX L..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\PanSeries.h ºÝµ ÄÙV J..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal.h ºÝµ MÙ[ O..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_gpio.h ºÝµ 5ÙZ N..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_def.h ºÝµ ·Ù[ O..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_uart.h ºÝµ (Ù[ O..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_dmac.h ºÝµ OÙZ N..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_spi.h ºÝµ ÙZ N..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_i2c.h ºÝµ èÙZ N..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_wdt.h ºÝµ Ù[ O..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_wwdt.h ºÝµ ÙZ N..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_pwm.h ºÝµ Ù\ P..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_timer.h ºÝµ ÁÙZ N..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_adc.h ºÝµ ¾Ù] Q..\..\..\modules\hal\panchip\panplat\pan1070\bsp\radio\prf_lib\include\pan_phy.h ºÝµ \ÙZ N..\..\..\modules\hal\panchip\panplat\pan1070\bsp\radio\prf_lib\include\info.h ºÝµ ¥ÙV J..\..\..\modules\hal\panchip\panplat\pan1070\bsp\radio\src\pan_prf_glue.c ºÝµ CÚ P __cplusplus
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Ú P COMM_PRF_H Ú P __PAN_PRI_RF_H__ hÚ P __PANSERIES_H__ àÚ P
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__stdio_h Ú P __ARMCLIB_VERSION lÚ P __int64 HÚ P __INT64_TYPE__ ;Ú P _ARMABI ²Ú P __STDIO_DECLS ¦Ú P __CLIBNS BÚ P __sizeof_ptr ®Ú size_t gÚ P NULL Ú P
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__clang__ 6Ú 8
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__va_list Ú
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__va_list ?Ú 8 __fpos_t_struct ZÚ (" __pos |Ú 8
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<unnamed> QÚ
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" __state1 Ú
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" __state2 Ú "
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__mbstate âÚ fpos_t jÚ P
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_SYS_OPEN ÊÚ 8 __FILE ÛÚ FILE ÙÚ __stdin ÿÚ __stdout |Ú __stderr Ú __aeabi_stdin ¢Ú __aeabi_stdout Ú __aeabi_stderr .Ú P stdin Ú P stdout Ú P stderr +Ú P _IOFBF úÚ P _IOLBF ôÚ P _IONBF òÚ P BUFSIZ ìÚ P
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FOPEN_MAX üÚ P FILENAME_MAX -Ú P L_tmpnam Ú P TMP_MAX Ú P EOF ëÚ P SEEK_SET HÚ P SEEK_CUR JÚ P SEEK_END ]Ú P _IOBIN ïÚ P __STDIN_BUFSIZ =Ú P __STDOUT_BUFSIZ ÚÚ P __STDERR_BUFSIZ éÚ remove NÚ rename dÚ tmpfile éÚ tmpnam OÚ fclose `Ú fflush TÚ fopen ÆÚ freopen ëÚ setbuf SÚ setvbuf ÛÚ fprintf áÚ _fprintf Ú printf IÚ _printf èÚ sprintf ÔÚ _sprintf sÚ __ARM_snprintf [Ú P __STDC_VERSION__ zÚ snprintf dÚ
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_snprintf Ú fscanf kÚ _fscanf
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Ú scanf ÓÚ _scanf rÚ sscanf ^Ú _sscanf ýÚ vfscanf óÚ vscanf [Ú vsscanf æÚ _vfscanf Ú _vscanf úÚ _vsscanf
Ú __ARM_vsscanf ÝÚ vprintf ÑÚ _vprintf pÚ vfprintf iÚ vsprintf \Ú __ARM_vsnprintf ãÚ
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vsnprintf ìÚ
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_vsprintf ûÚ
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_vfprintf Ú _vsnprintf Ú asprintf qÚ
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vasprintf ùÚ __ARM_asprintf hÚ __ARM_vasprintf ðÚ fgetc ÕÚ fgets ÅÚ fputc ¼Ú fputs ¬Ú getc =Ú P getchar ßÚ getchar üÚ gets -Ú putc $Ú P putchar ÆÚ putchar ãÚ puts Ú ungetc VÚ fread ÜÚ __fread_bytes_avail Ú fwrite KÚ fgetpos âÚ fseek ÐÚ fsetpos ÖÚ ftell ÇÚ rewind SÚ clearerr Ú feof @Ú ferror LÚ perror BÚ _fisatty uÚ! __use_no_semihosting_swi ¶Ú __use_no_semihosting pÚ P __stdlib_h °Ú P __ARMCC_VERSION Ú P __LONGLONG Ú P _ARMABI_PURE Ú P _ARMABI_NORETURN ÄÚ P _ARMABI_THROW ³Ú P __STDLIB_DECLS eÚ P __USE_C99_STDLIB ËÚ wchar_t Ú 8 div_t ¥Ú " quot qÚ " rem øÚ div_t áÚ 8 ldiv_t 7Ú " quot eÚ " rem ìÚ ldiv_t sÚ 8 lldiv_t ÉÚ &" quot GÚ &" rem ÎÚ lldiv_t Ú P __EXIT_FAILURE NÚ P EXIT_FAILURE Ú P EXIT_SUCCESS Ú P __USE_ANSI_EXAMPLE_RAND wÚ P RAND_MAX QÚ __aeabi_MB_CUR_MAX Ú P MB_CUR_MAX Ú atof 6Ú atoi 3Ú atol 0Ú atoll ÂÚ strtod <Ú strtof :Ú strtold ÎÚ strtol 4Ú strtoul ½Ú strtoll ÆÚ strtoull OÚ rand ;Ú srand ÆÚ 8 _rand_state +Ú <" ä¨__x ÐÚ _rand_r Ú _srand_r Ú 8 _ANSI_rand_state Ú <" ¬__x ®Ú _ANSI_rand_r qÚ _ANSI_srand_r üÚ calloc nÚ free >Ú malloc dÚ realloc øÚ posix_memalign ðÚ
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__heapprt =Ú __heapstats GÚ __heapvalid fÚ abort ÆÚ atexit MÚ P __EDG__ oÚ P __GNUC__ Ú exit &Ú _Exit åÚ getenv SÚ system 7Ú bsearch Ú qsort ¥Ú abs ¬Ú div Ú labs >Ú ldiv 1Ú llabs ÐÚ lldiv ÃÚ 8 __sdiv32by16 Ú " Èquot 1Ú " Èrem ¸Ú __sdiv32by16 ÎÚ 8 __udiv32by16 Ú
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" Ìquot +Ú
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" Ìrem ²Ú __udiv32by16 ÌÚ 8 __sdiv64by32 Ú " Ðrem °Ú " Ðquot )Ú __sdiv64by32 ËÚ __rt_sdiv32by16 jÚ __rt_udiv32by16 hÚ __rt_sdiv64by32 gÚ __fp_status ;Ú P __fpsr_IXE ùÚ P __fpsr_UFE ÿÚ P __fpsr_OFE Ú P __fpsr_DZE üÚ P __fpsr_IOE Ú P __fpsr_IXC ûÚ P __fpsr_UFC Ú P __fpsr_OFC Ú P __fpsr_DZC þÚ P __fpsr_IOC Ú mblen ÐÚ mbtowc PÚ wctomb PÚ mbstowcs fÚ wcstombs fÚ __use_realtime_heap Ú __use_realtime_division 9Ú __use_two_region_memory Ú __use_no_heap Ú __use_no_heap_region Ú# __C_library_version_string Ú# __C_library_version_number Ú P __stdint_h Ú P __INT64 ªÚ P __INT64_C_SUFFIX__ Ú P __PASTE2 NÚ P __PASTE Ú P
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__INT64_C Ú P __UINT64_C Ú P __STDINT_DECLS QÚ int8_t Ú int16_t nÚ int32_t pÚ int64_t kÚ uint8_t (Ú uint16_t ÷Ú uint32_t ùÚ uint64_t ôÚ int_least8_t Ú int_least16_t êÚ int_least32_t ìÚ int_least64_t çÚ uint_least8_t ¤Ú uint_least16_t sÚ uint_least32_t uÚ uint_least64_t pÚ int_fast8_t Ú int_fast16_t WÚ int_fast32_t YÚ int_fast64_t TÚ uint_fast8_t Ú uint_fast16_t àÚ uint_fast32_t âÚ uint_fast64_t ÝÚ intptr_t }Ú
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uintptr_t Ú intmax_t Ú
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uintmax_t Ú P INT8_MIN UÚ P
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UINT8_MAX üÚ P UINT16_MAX ËÚ P UINT32_MAX ÍÚ P UINT64_MAX ÈÚ P INT_LEAST8_MIN qÚ P INT_LEAST16_MIN @Ú P INT_LEAST32_MIN BÚ P INT_LEAST64_MIN =Ú P INT_LEAST8_MAX oÚ P INT_LEAST16_MAX >Ú P INT_LEAST32_MAX @Ú P INT_LEAST64_MAX ;Ú P UINT_LEAST8_MAX Ú P UINT_LEAST16_MAX çÚ P UINT_LEAST32_MAX éÚ P UINT_LEAST64_MAX äÚ P INT_FAST8_MIN ¾Ú P INT_FAST16_MIN Ú P INT_FAST32_MIN Ú P INT_FAST64_MIN Ú P INT_FAST8_MAX ¼Ú P INT_FAST16_MAX Ú P INT_FAST32_MAX Ú P INT_FAST64_MAX Ú P UINT_FAST8_MAX eÚ P UINT_FAST16_MAX 4Ú P UINT_FAST32_MAX 6Ú P UINT_FAST64_MAX 1Ú P INTPTR_MIN Ú P INTPTR_MAX Ú P UINTPTR_MAX :Ú P INTMAX_MIN £Ú P INTMAX_MAX ¡Ú P UINTMAX_MAX JÚ P PTRDIFF_MIN cÚ P PTRDIFF_MAX aÚ P SIG_ATOMIC_MIN mÚ P SIG_ATOMIC_MAX kÚ P SIZE_MAX ;Ú P
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WCHAR_MIN Ú P
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WCHAR_MAX ÿÚ P WINT_MIN 6Ú P WINT_MAX 4Ú P INT8_C úÚ P INT16_C ÉÚ P INT32_C ËÚ P INT64_C ÆÚ P UINT8_C £Ú P UINT16_C rÚ P UINT32_C tÚ P UINT64_C oÚ P INTMAX_C HÚ P
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UINTMAX_C ñÚ P __string_h Ú P __STRING_DECLS PÚ memcpy QÚ memmove äÚ strcpy 7Ú strncpy ÇÚ strcat KÚ strncat ÛÚ memcmp ]Ú strcmp CÚ strncmp ÓÚ strcasecmp Ú strncasecmp /Ú strcoll ×Ú strxfrm ÄÚ memchr `Ú strchr FÚ strcspn ÍÚ strpbrk ÒÚ strrchr ÒÚ strspn 2Ú strstr *Ú strtok 5Ú
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_strtok_r ÿÚ P __STRICT_ANSI__ ÌÚ strtok_r `Ú memset QÚ strerror UÚ strlen DÚ strlcpy ÉÚ strlcat ÝÚ _membitcpybl ÙÚ _membitcpybb ãÚ _membitcpyhl ÓÚ _membitcpyhb ÝÚ _membitcpywl ÄÚ _membitcpywb ÎÚ _membitmovebl lÚ _membitmovebb vÚ _membitmovehl fÚ _membitmovehb pÚ _membitmovewl WÚ _membitmovewb aÚ 8" IRQn ]Ú " úNonMaskableInt_IRQn Ú " úHardFault_IRQn Ú " ú SVCall_IRQn ëÚ " ú PendSV_IRQn àÚ " ú SysTick_IRQn DÚ " ú
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IRQn_Type Ú P
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__CM0_REV ïÚ P __MPU_PRESENT Ú P __NVIC_PRIO_BITS Ú P __Vendor_SysTickConfig ôÚ P __FPU_PRESENT Ú P __CORE_CM0_H_GENERIC Ú P __CMSIS_VERSION_H @Ú P __CM_CMSIS_VERSION_MAIN hÚ P __CM_CMSIS_VERSION_SUB ¥Ú P __CM_CMSIS_VERSION öÚ! P __CM0_CMSIS_VERSION_MAIN 6Ú P __CM0_CMSIS_VERSION_SUB sÚ P __CM0_CMSIS_VERSION ÄÚ P __CORTEX_M xÚ P __FPU_USED ~Ú P __CC_ARM 6Ú P __CMSIS_COMPILER_H Ú P __CMSIS_ARMCC_H Ú P __TARGET_ARCH_6S_M Ú P __ARM_ARCH_6M__ òÚ P __ASM "Ú P __INLINE >Ú P __STATIC_INLINE Ú P __STATIC_FORCEINLINE Ú P __NO_RETURN Ú P __USED ÐÚ P __WEAK ÙÚ P __PACKED UÚ P __PACKED_STRUCT Ú P __PACKED_UNION aÚ P __UNALIGNED_UINT32 NÚ! P __UNALIGNED_UINT16_WRITE VÚ P __UNALIGNED_UINT16_READ ÇÚ! P __UNALIGNED_UINT32_WRITE XÚ P __UNALIGNED_UINT32_READ ÉÚ P
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" Û __regPriMask 4Ú __get_FPSCR Ú __set_FPSCR ÷Ú ,
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" ßfpscr ³Ú P __NOP Ú P __WFI Ú P __WFE !Ú P __SEV Ú P __ISB %Ú P __DSB *Ú P __DMB 0Ú P __REV Ú P __NO_EMBEDDED_ASM Ú __REV16 ÔÚ ,
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" êvalue ©Ú __REVSH Ú , " ìvalue §Ú P __ROR Ú P __BKPT ÐÚ __RBIT ùÚ ,
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<unnamed> SÚ 8
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<unnamed> QÚ
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" _reserved0 ;Ú
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" V æÚ
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" C ùÚ
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APSR_Type ¸Ú P APSR_N_Pos CÚ P APSR_N_Msk JÚ P APSR_Z_Pos 7Ú P APSR_Z_Msk >Ú P APSR_C_Pos NÚ P APSR_C_Msk UÚ P APSR_V_Pos ;Ú P APSR_V_Msk BÚ 8
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<unnamed> SÚ 8
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<unnamed> QÚ
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" ISR 8Ú
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" _reserved0 )Ú " b ·Ú
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IPSR_Type °Ú P IPSR_ISR_Pos Ú P IPSR_ISR_Msk Ú 8
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<unnamed> SÚ 8
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<unnamed> QÚ
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" ¢ISR /Ú
|
" ¢ _reserved0 Ú
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" ¢T ÍÚ
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" ¡w «Ú
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xPSR_Type Ú P xPSR_N_Pos Ú P xPSR_N_Msk Ú P xPSR_Z_Pos Ú P xPSR_Z_Msk Ú P xPSR_C_Pos Ú P xPSR_C_Msk Ú P xPSR_V_Pos Ú P xPSR_V_Msk Ú P xPSR_T_Pos Ú P xPSR_T_Msk Ú P xPSR_ISR_Pos hÚ P xPSR_ISR_Msk oÚ 8
|
<unnamed> SÚ 8
|
<unnamed> QÚ
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" » _reserved0 Ú
|
" »SPSEL yÚ
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" » _reserved1 Ú " ºb Ú
|
" ºw Ú CONTROL_Type ÇÚ P CONTROL_SPSEL_Pos Ú P CONTROL_SPSEL_Msk Ú 8
|
<unnamed> QÚ <" ÄISER Ú <" |Ä
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RESERVED0 µÚ <" ÄICER ¤Ú <" |Ä
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RESERVED1 ´Ú <" ÄISPR Ú <" |Ä
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RESERVED2 ³Ú <" ÄICPR Ú <" |Ä
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RESERVED3 ²Ú <" Ä
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RESERVED4 ªÚ <" ÄIP Ú
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NVIC_Type ¾Ú 8
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<unnamed> QÚ
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" ÐCPUID vÚ
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" ÐICSR ¼Ú
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" Ð
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RESERVED0 SÚ
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" ÐCCR Ú
|
" Ð
|
RESERVED1 RÚ <" ÐSHP ÎÚ
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" ÐSHCSR hÚ SCB_Type Ú" P SCB_CPUID_IMPLEMENTER_Pos »Ú" P SCB_CPUID_IMPLEMENTER_Msk ÂÚ P SCB_CPUID_VARIANT_Pos ðÚ P SCB_CPUID_VARIANT_Msk ÷Ú# P SCB_CPUID_ARCHITECTURE_Pos xÚ# P SCB_CPUID_ARCHITECTURE_Msk Ú P SCB_CPUID_PARTNO_Pos 3Ú P SCB_CPUID_PARTNO_Msk :Ú P SCB_CPUID_REVISION_Pos Ú P SCB_CPUID_REVISION_Msk Ú P SCB_ICSR_NMIPENDSET_Pos NÚ P SCB_ICSR_NMIPENDSET_Msk UÚ P SCB_ICSR_PENDSVSET_Pos Ú P SCB_ICSR_PENDSVSET_Msk Ú P SCB_ICSR_PENDSVCLR_Pos Ú P SCB_ICSR_PENDSVCLR_Msk Ú P SCB_ICSR_PENDSTSET_Pos Ú P SCB_ICSR_PENDSTSET_Msk Ú P SCB_ICSR_PENDSTCLR_Pos Ú P SCB_ICSR_PENDSTCLR_Msk Ú P SCB_ICSR_ISRPREEMPT_Pos :Ú P SCB_ICSR_ISRPREEMPT_Msk AÚ P SCB_ICSR_ISRPENDING_Pos RÚ P SCB_ICSR_ISRPENDING_Msk YÚ! P SCB_ICSR_VECTPENDING_Pos Ú! P SCB_ICSR_VECTPENDING_Msk Ú P SCB_ICSR_VECTACTIVE_Pos WÚ P SCB_ICSR_VECTACTIVE_Msk ^Ú P SCB_AIRCR_VECTKEY_Pos îÚ P SCB_AIRCR_VECTKEY_Msk õÚ" P SCB_AIRCR_VECTKEYSTAT_Pos ªÚ" P SCB_AIRCR_VECTKEYSTAT_Msk ±Ú P SCB_AIRCR_ENDIANESS_Pos kÚ P SCB_AIRCR_ENDIANESS_Msk rÚ" P SCB_AIRCR_SYSRESETREQ_Pos Ú" P SCB_AIRCR_SYSRESETREQ_Msk Ú$ P SCB_AIRCR_VECTCLRACTIVE_Pos .Ú$ P SCB_AIRCR_VECTCLRACTIVE_Msk 5Ú P SCB_SCR_SEVONPEND_Pos àÚ P SCB_SCR_SEVONPEND_Msk çÚ P SCB_SCR_SLEEPDEEP_Pos ûÚ P SCB_SCR_SLEEPDEEP_Msk Ú P SCB_SCR_SLEEPONEXIT_Pos >Ú P SCB_SCR_SLEEPONEXIT_Msk EÚ P SCB_CCR_STKALIGN_Pos GÚ P SCB_CCR_STKALIGN_Msk NÚ P SCB_CCR_UNALIGN_TRP_Pos ;Ú P SCB_CCR_UNALIGN_TRP_Msk BÚ# P SCB_SHCSR_SVCALLPENDED_Pos xÚ# P SCB_SHCSR_SVCALLPENDED_Msk Ú 8
|
<unnamed> QÚ
|
" CTRL úÚ
|
" LOAD Ú
|
" VAL NÚ
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" CALIB ÒÚ SysTick_Type Ú# P SysTick_CTRL_COUNTFLAG_Pos ¦Ú# P SysTick_CTRL_COUNTFLAG_Msk Ú# P SysTick_CTRL_CLKSOURCE_Pos Ú# P SysTick_CTRL_CLKSOURCE_Msk ¥Ú! P SysTick_CTRL_TICKINT_Pos 7Ú! P SysTick_CTRL_TICKINT_Msk >Ú P SysTick_CTRL_ENABLE_Pos ¨Ú P SysTick_CTRL_ENABLE_Msk ¯Ú P SysTick_LOAD_RELOAD_Pos Ú P SysTick_LOAD_RELOAD_Msk ´Ú P SysTick_VAL_CURRENT_Pos ~Ú P SysTick_VAL_CURRENT_Msk
Ú P SysTick_CALIB_NOREF_Pos ¯Ú P SysTick_CALIB_NOREF_Msk ¶Ú P SysTick_CALIB_SKEW_Pos ñÚ P SysTick_CALIB_SKEW_Msk øÚ P SysTick_CALIB_TENMS_Pos ¢Ú P SysTick_CALIB_TENMS_Msk ©Ú P _VAL2FLD qÚ P _FLD2VAL qÚ P SCS_BASE XÚ P SysTick_BASE oÚ P
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NVIC_BASE Ú P SCB_BASE iÚ P SCB íÚ P SysTick óÚ P NVIC Ú P CMSIS_NVIC_VIRTUAL Ú! P NVIC_SetPriorityGrouping 3Ú! P NVIC_GetPriorityGrouping ?Ú P NVIC_EnableIRQ íÚ P NVIC_GetEnableIRQ ÇÚ P NVIC_DisableIRQ ~Ú P NVIC_GetPendingIRQ GÚ P NVIC_SetPendingIRQ ;Ú P NVIC_ClearPendingIRQ |Ú P NVIC_SetPriority Ú P NVIC_GetPriority Ú P NVIC_SystemReset Ú P CMSIS_VECTAB_VIRTUAL Ú P NVIC_SetVector Ú P NVIC_GetVector Ú P NVIC_USER_IRQ_OFFSET dÚ P EXC_RETURN_HANDLER +Ú P EXC_RETURN_THREAD_MSP Ú P EXC_RETURN_THREAD_PSP Ú P _BIT_SHIFT Ú P _SHP_IDX -Ú P _IP_IDX Ú# P __NVIC_SetPriorityGrouping qÚ# P __NVIC_GetPriorityGrouping }Ú __NVIC_EnableIRQ TÚ ,"" ÆIRQn {Ú __memory_changed HÚ __NVIC_GetEnableIRQ .Ú ,"" ÉIRQn xÚ __NVIC_DisableIRQ åÚ ,"" ËIRQn vÚ __schedule_barrier sÚ __dsb çÚ __isb âÚ __NVIC_GetPendingIRQ ®Ú ,"" ÐIRQn qÚ __NVIC_SetPendingIRQ ¢Ú ,"" ÒIRQn oÚ __NVIC_ClearPendingIRQ ãÚ ,"" ÔIRQn mÚ __NVIC_SetPriority õÚ ,"" ÖIRQn kÚ ,
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" Ö priority PÚ __NVIC_GetPriority Ú ,"" ÙIRQn hÚ NVIC_EncodePriority Ú ,
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" ÛPriorityGroup TÚ ,
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" ÛPreemptPriority Ú ,
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" Û SubPriority ;Ú
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" ÛPriorityGroupTmp AÚ
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" ÛPreemptPriorityBits
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Ú
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" ÛSubPriorityBits ÅÚ NVIC_DecodePriority Ú ,
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" â Priority dÚ ,
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" âPriorityGroup MÚ ," âpPreemptPriority ùÚ ," â pSubPriority ´Ú
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" âPriorityGroupTmp :Ú
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" âPreemptPriorityBits Ú
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" âSubPriorityBits ¾Ú __NVIC_SetVector èÚ ,"" êIRQn WÚ ,
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" êvector /Ú
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" êvectors ÞÚ __NVIC_GetVector ôÚ ,"" îIRQn SÚ
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" îvectors ÚÚ __NVIC_SystemReset ûÚ __nop ÓÚ SCB_GetFPUType ôÚ SysTick_Config YÚ ,
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" ôticks Ú P __SYSTEM_PANSERIES_H__ Ú& P __bool_true_false_are_defined ÙÚ P bool Ú P true Ú P false ¶Ú 8 _adc_vbg_kb ^Ú " û
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adc_vbg_k %Ú " û
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adc_vbg_b 0Ú ADC_VBG_KB_T DÚ 8 _otp_struct ûÚ <" ÿd8 tÚ 8
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<unnamed> QÚ <" rsvd0 ýÚ " pmu_vbg_trim &Ú " rsvd1 OÚ " pmu_vbg_volt_l NÚ " pmu_vbg_volt_h RÚ " hp_ldo_trim ¢Ú " hp_ldo_volt_l ÊÚ " hp_ldo_volt_h ÎÚ " lph_ldo_trim 4Ú " lph_ldo_volt_l \Ú " lph_ldo_volt_h `Ú " lpl_ldo_trim 0Ú " lpl_ldo_volt_l XÚ " lpl_ldo_volt_h \Ú " flash_ldo_trim fÚ " rsvd2 NÚ " flash_ldo_volt_l Ú " flash_ldo_volt_h Ú " ana_ldo_trim HÚ " rffe_ldo_trim ÓÚ " fsyn_ldo_trim ¶Ú " adc_ldo_trim PÚ " vco_ldo_trim 0Ú " ipoly_trim íÚ " rsvd3 MÚ " bod_vref_trim ÍÚ " rsvd4 LÚ " bod_vref_volt_l õÚ " bod_vref_volt_h ùÚ " adc_vbg_1v17_trim ØÚ " rsvd5 KÚ " adc_vbg_1v17_volt ÆÚ " adc_vbg_1v20_trim ÞÚ " rsvd6 JÚ " adc_vbg_1v20_volt ÌÚ " rch_trim áÚ
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" rch_freq èÚ " rcl_coarse_trim óÚ " rsvd7 IÚ " rcl_fine_trim ÒÚ " rcl_freq âÚ " xth_xocap_a Ú " xth_xocap_m Ú " xth_xocap_n Ú " xtl_xocap_a Ú " xtl_xocap_m Ú " xtl_xocap_n Ú " buck_imax_cal_trim ÈÚ " rsvd8 HÚ " buck_zero_cal_trim ·Ú " rsvd9 GÚ " buck_out_trim ¸Ú " rsvd10 Ú " buck_vout_volt .Ú "
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adc_vdd_k Ú "
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adc_vdd_b ³Ú "
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adc_vbg_k Ú "
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adc_vbg_b ©Ú " adc_temp_volt ÅÚ " current_temp_value Ú " battery_trim Ú# " pa_power_calib_trim_6dbm Ú# " pa_power_calib_trim_0dbm
Ú <" mac_addr ÓÚ <" uid ÃÚ "
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chip_info Ú " cp_version ýÚ " ft_version öÚ " cp_pass_flag OÚ " ft_pass_flag HÚ " cp_checksum ®Ú " ft_checksum §Ú <" user_rw_data øÚ " ÿm ÆÚ 8
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<unnamed> QÚ <" Ìrsvd0 ²Ú " Ì pmu_vbg_trim ÛÚ " Ìrsvd1 Ú " Ìpmu_vbg_volt_l Ú " Ìpmu_vbg_volt_h Ú " Ì hp_ldo_trim WÚ " Ìhp_ldo_volt_l Ú " Ìhp_ldo_volt_h Ú " Ì lph_ldo_trim éÚ " Ìlph_ldo_volt_l Ú " Ìlph_ldo_volt_h Ú " Ì lpl_ldo_trim åÚ " Ìlpl_ldo_volt_l Ú " Ìlpl_ldo_volt_h Ú " Ìflash_ldo_trim Ú " Ìrsvd2 Ú " Ìflash_ldo_volt_l CÚ " Ìflash_ldo_volt_h GÚ " Ì ana_ldo_trim ýÚ " Ìrffe_ldo_trim Ú " Ìfsyn_ldo_trim kÚ " Ì adc_ldo_trim Ú " Ì vco_ldo_trim åÚ " Ì ipoly_trim ¢Ú " Ìrsvd3 Ú " Ìbod_vref_trim Ú " Ìrsvd4 Ú " Ìbod_vref_volt_l ªÚ " Ìbod_vref_volt_h ®Ú " Ìrsvd5 Ú " Ì xtl_core Ú " Ì
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xth_icore 'Ú " Ì rch_bias ³Ú " Ìdpll_vco_freq_trim _Ú " Ìdpll_kvco_ctrl Ú " Ìdpll_icp_ctrl Ú " Ìdpll_icp_bias Ú " Ìrsvd6 ÿÚ " Ìadc_vbg_1v20_trim Ú " Ìptat_temp_trim ùÚ " Ìadc_vbg_1v20_volt Ú " Ì rch_trim Ú
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" Ì rch_freq Ú " Ìrcl_coarse_trim ¨Ú " Ìlph_ldo_vref_trim ÍÚ " Ìrsvd7 þÚ " Ìrcl_fine_trim Ú " Ì rcl_freq Ú " Ìanalog_temp_volt *Ú <"
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Ì
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rsvd_0x3e OÚ " Ìanalog_0p6v_volt Ú <"
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Ìrsvd8 ¾Ú " Ìbuck_imax_cal_trim }Ú " Ìrsvd9 üÚ " Ìbuck_zero_cal_trim lÚ " Ìrsvd10 ÒÚ " Ìbuck_out_trim mÚ " Ìrsvd11 ÑÚ " Ìbuck_vout_volt ãÚ " Ì
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adc_vdd_k TÚ " Ì
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adc_vdd_b hÚ " Ì
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adc_vbg_k SÚ " Ì
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adc_vbg_b ^Ú " Ìadc_temp_volt zÚ " Ìcurrent_temp_value ?Ú " Ì battery_trim ÐÚ <" Ìrsvd12 Ú <" Ìuid xÚ " Ì
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chip_info =Ú " Ì cp_version ²Ú " Ì ft_version «Ú " Ì cp_pass_flag Ú " Ì ft_pass_flag ýÚ " Ì cp_checksum cÚ " Ì ft_checksum \Ú <" Ì user_rw_data Ú <" Ì mac_addr Ú " Ì xth_xocap_a IÚ " Ì xth_xocap_m =Ú " Ì xth_xocap_n <Ú " Ìxth_xocap_trim ùÚ " Ì xtl_xocap_a EÚ " Ì xtl_xocap_m 9Ú " Ì xtl_xocap_n 8Ú " Ìxtl_xocap_trim õÚ <" Ì adc_vbg_kb §Ú " Ì adc_vbat_k ãÚ " Ì adc_vbat_b îÚ " Ìadc_vbat_dtemp_k `Ú " Ìadc_vbat_dtemp_b iÚ " Ì adc_temp_k ÒÚ
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" Ì
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adc_ctrl2 wÚ
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" Ì adc_extsmpt EÚ " Ìxth_fix_code1 ¿Ú " Ìxth_fix_code2 ¾Ú " Ìxtl_fix_code1 »Ú " Ìxtl_fix_code2 ºÚ <" +Ìrsvd13 oÚ " Ì ft_checksum2 (Ú " ÿm_v2 ¸Ú OTP_STRUCT_T ÿÚ isFtDataValid èÚ
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SystemCoreClock ãÚ
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vec_remap_adr Ú SystemCoreClockUpdate aÚ SystemInit »Ú , otp xÚ SystemHwParamLoader 6Ú RESET pÚ SET Ú FlagStatus ïÚ ITStatus ÐÚ DISABLE ûÚ ENABLE JÚ FunctionalState ÏÚ P IS_FUNCTIONAL_STATE ×Ú 8
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<unnamed> QÚ
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" ÁCTL Ú
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" ÁCMP Ú
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" ÁINTSTS Ú
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" ÁCNT Ú
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" ÁCAP 'Ú
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" ÁEXTCTL !Ú
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" ÁEINTSTS ÉÚ
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" ÁCMP1 èÚ
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" ÁCMP2 çÚ TIMER_T ¿Ú P TIMER_CTL_PSC_Pos Ú P TIMER_CTL_PSC_Msk Ú P TIMER_CTL_CAPSRC_Pos 4Ú P TIMER_CTL_CAPSRC_Msk ;Ú P TIMER_CTL_WKEN_Pos ¿Ú P TIMER_CTL_WKEN_Msk ÆÚ P TIMER_CTL_EXTCNTEN_Pos Ú P TIMER_CTL_EXTCNTEN_Msk Ú P TIMER_CTL_ACTSTS_Pos Ú P TIMER_CTL_ACTSTS_Msk %Ú P TIMER_CTL_RSTCNT_Pos Ú P TIMER_CTL_RSTCNT_Msk Ú P TIMER_CTL_OPMODE_Pos ,Ú P TIMER_CTL_OPMODE_Msk 3Ú P TIMER_CTL_INTEN_Pos tÚ P TIMER_CTL_INTEN_Msk {Ú P TIMER_CTL_CNTEN_Pos zÚ P TIMER_CTL_CNTEN_Msk Ú P TIMER_CTL_ICEDEBUG_Pos ´Ú P TIMER_CTL_ICEDEBUG_Msk »Ú P TIMER_CMP_CMPDAT_Pos :Ú P TIMER_CMP_CMPDAT_Msk AÚ P TIMER_INTSTS_TIF_Pos Ú P TIMER_INTSTS_TIF_Msk Ú P TIMER_INTSTS_TWKF0_Pos ~Ú P TIMER_INTSTS_TWKF0_Msk
Ú P TIMER_INTSTS_TWKF1_Pos }Ú P TIMER_INTSTS_TWKF1_Msk Ú P TIMER_INTSTS_TWKF2_Pos |Ú P TIMER_INTSTS_TWKF2_Msk Ú P TIMER_INTSTS_TF0_Pos $Ú P TIMER_INTSTS_TF0_Msk +Ú P TIMER_INTSTS_TF1_Pos #Ú P TIMER_INTSTS_TF1_Msk *Ú P TIMER_INTSTS_TF2_Pos "Ú P TIMER_INTSTS_TF2_Msk )Ú P TIMER_CNT_CNT_Pos Ú P TIMER_CNT_CNT_Msk Ú P TIMER_CAP_CAPDAT_Pos RÚ P TIMER_CAP_CAPDAT_Msk YÚ" P TIMER_EXTCTL_CNTPHASE_Pos Ú" P TIMER_EXTCTL_CNTPHASE_Msk ¦Ú! P TIMER_EXTCTL_CAPEDGE_Pos Ú! P TIMER_EXTCTL_CAPEDGE_Msk Ú P TIMER_EXTCTL_CAPEN_Pos Ú P TIMER_EXTCTL_CAPEN_Msk Ú" P TIMER_EXTCTL_CAPFUNCS_Pos ¢Ú" P TIMER_EXTCTL_CAPFUNCS_Msk ©Ú P TIMER_EXTCTL_CAPIEN_Pos IÚ P TIMER_EXTCTL_CAPIEN_Msk PÚ! P TIMER_EXTCTL_CAPDBEN_Pos
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Ú! P TIMER_EXTCTL_CAPDBEN_Msk Ú! P TIMER_EXTCTL_CNTDBEN_Pos ùÚ! P TIMER_EXTCTL_CNTDBEN_Msk Ú P TIMER_EXTCTL_CAPSEL_Pos AÚ P TIMER_EXTCTL_CAPSEL_Msk HÚ" P TIMER_EXTCTL_ACMPSSEL_Pos Ú" P TIMER_EXTCTL_ACMPSSEL_Msk ¤Ú P TIMER_EINTSTS_CAPIF_Pos @Ú P TIMER_EINTSTS_CAPIF_Msk GÚ P TIMER_EINTSTS_CAPF_Pos Ú P TIMER_EINTSTS_CAPF_Msk Ú 8
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<unnamed> QÚ
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" TRIM_EN ûÚ
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"
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TRIM_CODE oÚ
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"
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TRIM_CTRL UÚ
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" TRIM_INT ¡Ú
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" TRIM_CAL_CNT pÚ
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" TRIM_IDEAL_CNT ÝÚ
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" TRIM_REAL_CNT Ú TRIM_T Ú# P TRIM_MEASURE_TUNING_EN_Pos 3Ú# P TRIM_MEASURE_TUNING_EN_Msk :Ú" P TRIM_COARSE_TUNING_EN_Pos Ú" P TRIM_COARSE_TUNING_EN_Msk Ú P TRIM_FINE_TUNING_EN_Pos )Ú P TRIM_FINE_TUNING_EN_Msk 0Ú P TRIM_COARSE_CODE_Pos @Ú P TRIM_COARSE_CODE_Msk GÚ P TRIM_FINE_CODE_Pos ßÚ P TRIM_FINE_CODE_Msk æÚ P TRIM_BIT_WIDTH_Pos ½Ú P TRIM_BIT_WIDTH_Msk ÄÚ P TRIM_CLRL_RELATION_Pos Ú P TRIM_CLRL_RELATION_Msk Ú$ P TRIM_CLRL_EARLY_TERM_EN_Pos ×Ú$ P TRIM_CLRL_EARLY_TERM_EN_Msk ÞÚ% P TRIM_CLRL_FAIL_CLAC_FLAG_Pos ÔÚ% P TRIM_CLRL_FAIL_CLAC_FLAG_Msk ÛÚ P TRIM_CLRL_CODE_STEP_Pos /Ú P TRIM_CLRL_CODE_STEP_Msk 6Ú P TRIM_CLRL_ERR_RANGE_Pos 0Ú P TRIM_CLRL_ERR_RANGE_Msk 7Ú P TRIM_INT_EN_Pos ¤Ú P TRIM_INT_EN_Msk «Ú" P TRIM_INT_MEASURE_STOP_Pos lÚ" P TRIM_INT_MEASURE_STOP_Msk sÚ# P TRIM_FLAG_MEASURE_STOP_Pos ;Ú# P TRIM_FLAG_MEASURE_STOP_Msk BÚ P TRIM_INT_CTUNE_STOP_Pos Ú P TRIM_INT_CTUNE_STOP_Msk
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Ú! P TRIM_FLAG_CTUNE_STOP_Pos ÒÚ! P TRIM_FLAG_CTUNE_STOP_Msk ÙÚ P TRIM_INT_FTUNE_STOP_Pos Ú P TRIM_INT_FTUNE_STOP_Msk Ú! P TRIM_FLAG_FTUNE_STOP_Pos ÏÚ! P TRIM_FLAG_FTUNE_STOP_Msk ÖÚ P TRIM_INT_OVERFLOW_Pos ·Ú P TRIM_INT_OVERFLOW_Msk ¾Ú P TRIM_FLAG_OVERFLOW_Pos Ú P TRIM_FLAG_OVERFLOW_Msk Ú P TRIM_CALC_CNT_Pos &Ú P TRIM_CALC_CNT_Msk -Ú P TRIM_CALC_WATI_CNT_Pos Ú P TRIM_CALC_WATI_CNT_Msk Ú 8
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<unnamed> QÚ
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" ¿MODE ÕÚ
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" ¿DINOFF @Ú
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" ¿DOUT ¾Ú
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" ¿DATMSK 2Ú
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" ¿PIN Ú
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" ¿DBEN áÚ
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" ¿INTTYPE ÇÚ
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" ¿INTEN zÚ
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" ¿INTSRC #Ú GPIO_T Ú 8
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<unnamed> QÚ
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" ÊDBCTL Ú
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GPIO_DB_T (Ú P GP_MODE_MODE0_Pos IÚ P GP_MODE_MODE0_Msk PÚ P GP_MODE_MODE1_Pos HÚ P GP_MODE_MODE1_Msk OÚ P GP_MODE_MODE2_Pos GÚ P GP_MODE_MODE2_Msk NÚ P GP_MODE_MODE3_Pos FÚ P GP_MODE_MODE3_Msk MÚ P GP_MODE_MODE4_Pos EÚ P GP_MODE_MODE4_Msk LÚ P GP_MODE_MODE5_Pos DÚ P GP_MODE_MODE5_Msk KÚ P GP_DINOFF_DINOFF0_Pos Ú P GP_DINOFF_DINOFF0_Msk &Ú P GP_DINOFF_DINOFF1_Pos Ú P GP_DINOFF_DINOFF1_Msk %Ú P GP_DINOFF_DINOFF2_Pos Ú P GP_DINOFF_DINOFF2_Msk $Ú P GP_DINOFF_DINOFF3_Pos Ú P GP_DINOFF_DINOFF3_Msk #Ú P GP_DINOFF_DINOFF4_Pos Ú P GP_DINOFF_DINOFF4_Msk "Ú P GP_DINOFF_DINOFF5_Pos Ú P GP_DINOFF_DINOFF5_Msk !Ú P GP_DINOFF_DINOFF6_Pos Ú P GP_DINOFF_DINOFF6_Msk Ú P GP_DINOFF_DINOFF7_Pos Ú P GP_DINOFF_DINOFF7_Msk Ú P GP_DOUT_DOUT0_Pos Ú P GP_DOUT_DOUT0_Msk "Ú P GP_DOUT_DOUT1_Pos Ú P GP_DOUT_DOUT1_Msk !Ú P GP_DOUT_DOUT2_Pos Ú P GP_DOUT_DOUT2_Msk Ú P GP_DOUT_DOUT3_Pos Ú P GP_DOUT_DOUT3_Msk Ú P GP_DOUT_DOUT4_Pos Ú P GP_DOUT_DOUT4_Msk Ú P GP_DOUT_DOUT5_Pos Ú P GP_DOUT_DOUT5_Msk Ú P GP_DOUT_DOUT6_Pos Ú P GP_DOUT_DOUT6_Msk Ú P GP_DOUT_DOUT7_Pos Ú P GP_DOUT_DOUT7_Msk Ú P GP_DATMSK_DATMSK0_Pos Ú P GP_DATMSK_DATMSK0_Msk
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Ú P GP_DATMSK_DATMSK1_Pos Ú P GP_DATMSK_DATMSK1_Msk Ú P GP_DATMSK_DATMSK2_Pos Ú P GP_DATMSK_DATMSK2_Msk Ú P GP_DATMSK_DATMSK3_Pos Ú P GP_DATMSK_DATMSK3_Msk Ú P GP_DATMSK_DATMSK4_Pos ÿÚ P GP_DATMSK_DATMSK4_Msk Ú P GP_DATMSK_DATMSK5_Pos þÚ P GP_DATMSK_DATMSK5_Msk Ú P GP_DATMSK_DATMSK6_Pos ýÚ P GP_DATMSK_DATMSK6_Msk Ú P GP_DATMSK_DATMSK7_Pos üÚ P GP_DATMSK_DATMSK7_Msk Ú P GP_PIN_PIN0_Pos ÉÚ P GP_PIN_PIN0_Msk ÐÚ P GP_PIN_PIN1_Pos ÈÚ P GP_PIN_PIN1_Msk ÏÚ P GP_PIN_PIN2_Pos ÇÚ P GP_PIN_PIN2_Msk ÎÚ P GP_PIN_PIN3_Pos ÆÚ P GP_PIN_PIN3_Msk ÍÚ P GP_PIN_PIN4_Pos ÅÚ P GP_PIN_PIN4_Msk ÌÚ P GP_PIN_PIN5_Pos ÄÚ P GP_PIN_PIN5_Msk ËÚ P GP_PIN_PIN6_Pos ÃÚ P GP_PIN_PIN6_Msk ÊÚ P GP_PIN_PIN7_Pos ÂÚ P GP_PIN_PIN7_Msk ÉÚ P GP_DBEN_DBEN0_Pos aÚ P GP_DBEN_DBEN0_Msk hÚ P GP_DBEN_DBEN1_Pos `Ú P GP_DBEN_DBEN1_Msk gÚ P GP_DBEN_DBEN2_Pos _Ú P GP_DBEN_DBEN2_Msk fÚ P GP_DBEN_DBEN3_Pos ^Ú P GP_DBEN_DBEN3_Msk eÚ P GP_DBEN_DBEN4_Pos ]Ú P GP_DBEN_DBEN4_Msk dÚ P GP_DBEN_DBEN5_Pos \Ú P GP_DBEN_DBEN5_Msk cÚ P GP_DBEN_DBEN6_Pos [Ú P GP_DBEN_DBEN6_Msk bÚ P GP_DBEN_DBEN7_Pos ZÚ P GP_DBEN_DBEN7_Msk aÚ P GP_INTTYPE_TYPE0_Pos Ú P GP_INTTYPE_TYPE0_Msk %Ú P GP_INTTYPE_TYPE1_Pos Ú P GP_INTTYPE_TYPE1_Msk $Ú P GP_INTTYPE_TYPE2_Pos Ú P GP_INTTYPE_TYPE2_Msk #Ú P GP_INTTYPE_TYPE3_Pos Ú P GP_INTTYPE_TYPE3_Msk "Ú P GP_INTTYPE_TYPE4_Pos Ú P GP_INTTYPE_TYPE4_Msk !Ú P GP_INTTYPE_TYPE5_Pos Ú P GP_INTTYPE_TYPE5_Msk Ú P GP_INTTYPE_TYPE6_Pos Ú P GP_INTTYPE_TYPE6_Msk Ú P GP_INTTYPE_TYPE7_Pos Ú P GP_INTTYPE_TYPE7_Msk Ú P GP_INTEN_FLIEN0_Pos £Ú P GP_INTEN_FLIEN0_Msk ªÚ P GP_INTEN_FLIEN1_Pos ¢Ú P GP_INTEN_FLIEN1_Msk ©Ú P GP_INTEN_FLIEN2_Pos ¡Ú P GP_INTEN_FLIEN2_Msk ¨Ú P GP_INTEN_FLIEN3_Pos Ú P GP_INTEN_FLIEN3_Msk §Ú P GP_INTEN_FLIEN4_Pos Ú P GP_INTEN_FLIEN4_Msk ¦Ú P GP_INTEN_FLIEN5_Pos Ú P GP_INTEN_FLIEN5_Msk ¥Ú P GP_INTEN_FLIEN6_Pos Ú P GP_INTEN_FLIEN6_Msk ¤Ú P GP_INTEN_FLIEN7_Pos Ú P GP_INTEN_FLIEN7_Msk £Ú P GP_INTEN_RHIEN0_Pos Ú P GP_INTEN_RHIEN0_Msk ¢Ú P GP_INTEN_RHIEN1_Pos Ú P GP_INTEN_RHIEN1_Msk ¡Ú P GP_INTEN_RHIEN2_Pos Ú P GP_INTEN_RHIEN2_Msk Ú P GP_INTEN_RHIEN3_Pos Ú P GP_INTEN_RHIEN3_Msk Ú P GP_INTEN_RHIEN4_Pos Ú P GP_INTEN_RHIEN4_Msk Ú P GP_INTEN_RHIEN5_Pos Ú P GP_INTEN_RHIEN5_Msk Ú P GP_INTEN_RHIEN6_Pos Ú P GP_INTEN_RHIEN6_Msk Ú P GP_INTEN_RHIEN7_Pos Ú P GP_INTEN_RHIEN7_Msk Ú P GP_INTSRC_INTSRC0_Pos åÚ P GP_INTSRC_INTSRC0_Msk ìÚ P GP_INTSRC_INTSRC1_Pos äÚ P GP_INTSRC_INTSRC1_Msk ëÚ P GP_INTSRC_INTSRC2_Pos ãÚ P GP_INTSRC_INTSRC2_Msk êÚ P GP_INTSRC_INTSRC3_Pos âÚ P GP_INTSRC_INTSRC3_Msk éÚ P GP_INTSRC_INTSRC4_Pos áÚ P GP_INTSRC_INTSRC4_Msk èÚ P GP_INTSRC_INTSRC5_Pos àÚ P GP_INTSRC_INTSRC5_Msk çÚ P GP_INTSRC_INTSRC6_Pos ßÚ P GP_INTSRC_INTSRC6_Msk æÚ P GP_INTSRC_INTSRC7_Pos ÞÚ P GP_INTSRC_INTSRC7_Msk åÚ P GP_INTSRC_INTSRC8_Pos ÝÚ P GP_INTSRC_INTSRC8_Msk äÚ P GP_INTSRC_INTSRC9_Pos ÜÚ P GP_INTSRC_INTSRC9_Msk ãÚ P GP_INTSRC_INTSRC10_Pos ²Ú P GP_INTSRC_INTSRC10_Msk ¹Ú P GP_INTSRC_INTSRC11_Pos ±Ú P GP_INTSRC_INTSRC11_Msk ¸Ú P GP_INTSRC_INTSRC12_Pos °Ú P GP_INTSRC_INTSRC12_Msk ·Ú P GP_INTSRC_INTSRC13_Pos ¯Ú P GP_INTSRC_INTSRC13_Msk ¶Ú P GP_INTSRC_INTSRC14_Pos ®Ú P GP_INTSRC_INTSRC14_Msk µÚ P GP_INTSRC_INTSRC15_Pos Ú P GP_INTSRC_INTSRC15_Msk ´Ú P GP_DBCTL_DBCLKSEL_Pos Ú P GP_DBCTL_DBCLKSEL_Msk Ú P GP_DBCTL_DBCLKSRC_Pos
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Ú P GP_DBCTL_DBCLKSRC_Msk Ú P GP_DBCTL_ICLKON_Pos Ú P GP_DBCTL_ICLKON_Msk Ú 8
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<unnamed> QÚ
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" ÿ DAT âÚ <" ÿ
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RESERVED0 ÕÚ
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" ÿ CTL ØÚ
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" ÿ CHEN Ú
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" ÿ CMP0 ©Ú
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" ÿ CMP1 ¨Ú
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" ÿ STATUS ÑÚ <" ÿ
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RESERVED1 àÚ
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" ÿ TRGDLY ßÚ
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" ÿ EXTSMPT ~Ú
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" ÿ SEQCTL éÚ
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" ÿ SEQDAT1 ÀÚ
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" ÿ SEQDAT2 ¿Ú
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" ÿ CTL2 ¤Ú <" ÿ
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RESERVED2 ßÚ
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" ÿ BV_CTL ÛÚ ADC_T |Ú P ADC_DAT_RESULT_Pos ØÚ P ADC_DAT_RESULT_Msk ßÚ P ADC_DAT_OV_Pos Ú P ADC_DAT_OV_Msk !Ú P ADC_DAT_VALID_Pos IÚ P ADC_DAT_VALID_Msk PÚ P ADC_CTL_ADCEN_Pos TÚ P ADC_CTL_ADCEN_Msk [Ú P ADC_CTL_ADCIEN_Pos Ú P ADC_CTL_ADCIEN_Msk Ú P ADC_CTL_HWTRGSEL_Pos 9Ú P ADC_CTL_HWTRGSEL_Msk @Ú P ADC_CTL_HWTRGCOND_Pos ÷Ú P ADC_CTL_HWTRGCOND_Msk þÚ P ADC_CTL_HWTRGEN_Pos Ú P ADC_CTL_HWTRGEN_Msk Ú P ADC_CTL_FIFO_EN_Pos Ú P ADC_CTL_FIFO_EN_Msk Ú$ P ADC_CTL_FIFO_THRE_STATE_Pos Ú$ P ADC_CTL_FIFO_THRE_STATE_Msk Ú P ADC_CTL_SWTRG_Pos Ú P ADC_CTL_SWTRG_Msk Ú" P ADC_CTL_LEFT_SHIFT_EN_Pos ¥Ú" P ADC_CTL_LEFT_SHIFT_EN_Msk ¬Ú P ADC_CTL_SUB_BIAS_EN_Pos IÚ P ADC_CTL_SUB_BIAS_EN_Msk PÚ P ADC_CTL_BIAS_VALUE_Pos ªÚ P ADC_CTL_BIAS_VALUE_Msk ±Ú P ADC_CHEN_CHEN0_Pos $Ú P ADC_CHEN_CHEN0_Msk +Ú P ADC_CHEN_CHEN1_Pos #Ú P ADC_CHEN_CHEN1_Msk *Ú P ADC_CHEN_CHEN2_Pos "Ú P ADC_CHEN_CHEN2_Msk )Ú P ADC_CHEN_CHEN3_Pos !Ú P ADC_CHEN_CHEN3_Msk (Ú P ADC_CHEN_CHEN4_Pos Ú P ADC_CHEN_CHEN4_Msk 'Ú P ADC_CHEN_CHEN5_Pos Ú P ADC_CHEN_CHEN5_Msk &Ú P ADC_CHEN_CHEN6_Pos Ú P ADC_CHEN_CHEN6_Msk %Ú P ADC_CHEN_CHEN7_Pos Ú P ADC_CHEN_CHEN7_Msk $Ú P ADC_CHEN_CHEN8_VBG_Pos ÖÚ P ADC_CHEN_CHEN8_VBG_Msk ÝÚ P ADC_CHEN_CH9_TMP_Pos ZÚ P ADC_CHEN_CH9_TMP_Msk aÚ P ADC_CHEN_CH10_VDD_4_Pos ¬Ú P ADC_CHEN_CH10_VDD_4_Msk ³Ú P ADC_CHEN_CH11_VBG_2_Pos ¬Ú P ADC_CHEN_CH11_VBG_2_Msk ³Ú P ADC_CHEN_ALL_Msk ¤Ú P ADC_CMP0_ADCMPEN_Pos Ú P ADC_CMP0_ADCMPEN_Msk Ú P ADC_CMP0_ADCMPIE_Pos Ú P ADC_CMP0_ADCMPIE_Msk Ú P ADC_CMP0_CMPCOND_Pos xÚ P ADC_CMP0_CMPCOND_Msk Ú P ADC_CMP0_CMPCH_Pos Ú P ADC_CMP0_CMPCH_Msk Ú P ADC_CMP0_CMPMCNT_Pos jÚ P ADC_CMP0_CMPMCNT_Msk qÚ P ADC_CMP0_CMPDAT_Pos ÅÚ P ADC_CMP0_CMPDAT_Msk ÌÚ P ADC_CMP1_ADCMPEN_Pos Ú P ADC_CMP1_ADCMPEN_Msk Ú P ADC_CMP1_ADCMPIE_Pos Ú P ADC_CMP1_ADCMPIE_Msk Ú P ADC_CMP1_CMPCOND_Pos wÚ P ADC_CMP1_CMPCOND_Msk ~Ú P ADC_CMP1_CMPCH_Pos Ú P ADC_CMP1_CMPCH_Msk Ú P ADC_CMP1_CMPMCNT_Pos iÚ P ADC_CMP1_CMPMCNT_Msk pÚ P ADC_CMP1_CMPDAT_Pos ÄÚ P ADC_CMP1_CMPDAT_Msk ËÚ P ADC_STATUS_ADIF_Pos Ú P ADC_STATUS_ADIF_Msk Ú P ADC_STATUS_ADCMPIF0_Pos ~Ú P ADC_STATUS_ADCMPIF0_Msk
Ú P ADC_STATUS_ADCMPIF1_Pos }Ú P ADC_STATUS_ADCMPIF1_Msk Ú P ADC_STATUS_BUSY_Pos gÚ P ADC_STATUS_BUSY_Msk nÚ P ADC_STATUS_CHANNEL_Pos «Ú P ADC_STATUS_CHANNEL_Msk ²Ú P ADC_STATUS_VALID_Pos 8Ú P ADC_STATUS_VALID_Msk ?Ú# P ADC_STATUS_INTMSK_FULL_Pos 4Ú# P ADC_STATUS_INTMSK_FULL_Msk ;Ú$ P ADC_STATUS_INTMSK_EMPTY_Pos ÖÚ$ P ADC_STATUS_INTMSK_EMPTY_Msk ÝÚ# P ADC_STATUS_INTMSK_OVER_Pos +Ú# P ADC_STATUS_INTMSK_OVER_Msk 2Ú# P ADC_STATUS_INTMSK_HALF_Pos LÚ# P ADC_STATUS_INTMSK_HALF_Msk SÚ! P ADC_STATUS_INTMSK_AD_Pos æÚ! P ADC_STATUS_INTMSK_AD_Msk íÚ# P ADC_STATUS_INTMSK_CMP0_Pos WÚ# P ADC_STATUS_INTMSK_CMP0_Msk ^Ú# P ADC_STATUS_INTMSK_CMP1_Pos VÚ# P ADC_STATUS_INTMSK_CMP1_Msk ]Ú P ADC_STATUS_OV_Pos Ú P ADC_STATUS_OV_Msk Ú& P ADC_STATUS_ONE_CH_CLR_SEL_Pos GÚ& P ADC_STATUS_ONE_CH_CLR_SEL_Msk NÚ# P ADC_STATUS_ONE_CH_FLAG_Pos WÚ# P ADC_STATUS_ONE_CH_FLAG_Msk ^Ú# P ADC_STATUS_INTFLG_FULL_Pos FÚ# P ADC_STATUS_INTFLG_FULL_Msk MÚ$ P ADC_STATUS_INTFLG_EMPTY_Pos èÚ$ P ADC_STATUS_INTFLG_EMPTY_Msk ïÚ# P ADC_STATUS_INTFLG_OVER_Pos =Ú# P ADC_STATUS_INTFLG_OVER_Msk DÚ# P ADC_STATUS_INTFLG_HALF_Pos ^Ú# P ADC_STATUS_INTFLG_HALF_Msk eÚ P ADC_STATUS_ADCF_Pos Ú P ADC_STATUS_ADCF_Msk £Ú P ADC_STATUS_ADCMPF0_Pos ÉÚ P ADC_STATUS_ADCMPF0_Msk ÐÚ P ADC_STATUS_ADCMPF1_Pos ÈÚ P ADC_STATUS_ADCMPF1_Msk ÏÚ! P ADC_STATUS_FLAG_FULL_Pos ôÚ! P ADC_STATUS_FLAG_FULL_Msk ûÚ" P ADC_STATUS_FLAG_EMPTY_Pos Ú" P ADC_STATUS_FLAG_EMPTY_Msk Ú! P ADC_STATUS_FLAG_OVER_Pos ëÚ! P ADC_STATUS_FLAG_OVER_Msk òÚ! P ADC_STATUS_FLAG_HALF_Pos Ú! P ADC_STATUS_FLAG_HALF_Msk Ú P ADC_TRGDLY_DELAY_Pos GÚ P ADC_TRGDLY_DELAY_Msk NÚ P ADC_EXTSMPT_EXTSMPT_Pos Ú P ADC_EXTSMPT_EXTSMPT_Msk #Ú P ADC_SEQCTL_SEQEN_Pos DÚ P ADC_SEQCTL_SEQEN_Msk KÚ P ADC_SEQCTL_SEQTYPE_Pos Ú P ADC_SEQCTL_SEQTYPE_Msk Ú P ADC_SEQCTL_MODESEL_Pos ³Ú P ADC_SEQCTL_MODESEL_Msk ºÚ P ADC_SEQCTL_DELAY_EN_Pos YÚ P ADC_SEQCTL_DELAY_EN_Msk `Ú P ADC_SEQCTL_TRG_SEL_Pos Ú P ADC_SEQCTL_TRG_SEL_Msk Ú! P ADC_SEQCTL_ONE_CH_EN_Pos úÚ! P ADC_SEQCTL_ONE_CH_EN_Msk Ú P ADC_SEQCTL_TRG1CTL_Pos »Ú P ADC_SEQCTL_TRG1CTL_Msk ÂÚ P ADC_SEQCTL_TRG2CTL_Pos ºÚ P ADC_SEQCTL_TRG2CTL_Msk ÁÚ P ADC_SEQDAT1_RESULT_Pos ¶Ú P ADC_SEQDAT1_RESULT_Msk ½Ú P ADC_SEQDAT1_OV_Pos øÚ P ADC_SEQDAT1_OV_Msk ÿÚ P ADC_SEQDAT1_VALID_Pos 'Ú P ADC_SEQDAT1_VALID_Msk .Ú P ADC_SEQDAT2_RESULT_Pos µÚ P ADC_SEQDAT2_RESULT_Msk ¼Ú P ADC_SEQDAT2_OV_Pos ÷Ú P ADC_SEQDAT2_OV_Msk þÚ P ADC_SEQDAT2_VALID_Pos &Ú P ADC_SEQDAT2_VALID_Msk -Ú P ADC_CTL2_TESTMODE_Pos Ú P ADC_CTL2_TESTMODE_Msk Ú P ADC_CTL2_SHSEL_Pos üÚ P ADC_CTL2_SHSEL_Msk Ú P ADC_CTL2_DMA_EN_Pos µÚ P ADC_CTL2_DMA_EN_Msk ¼Ú P ADC_CTL2_CLKDIV_Pos ¼Ú P ADC_CTL2_CLKDIV_Msk ÃÚ P ADC_SEL_VREF_Pos }Ú P ADC_SEL_VREF_Msk Ú P ADC_CTL2_CMPCTL_Pos ¶Ú P ADC_CTL2_CMPCTL_Msk ½Ú P ADC_CTL2_DRVCTL_Pos ªÚ P ADC_CTL2_DRVCTL_Msk ±Ú 8
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<unnamed> QÚ
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" Â P0_MFP .Ú
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" Â P1_MFP -Ú
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" Â P2_MFP ,Ú
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" Â P3_MFP +Ú <" 0Â RESV VÚ
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" Â REGLCTL áÚ
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" Â STATUS Ú
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" Â CTRL0 Ú
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" Â CTRL1 Ú SYS_T EÚ P SYS_P0_MFP_MFP_Pos ´Ú P SYS_P0_MFP_MFP_Msk »Ú P SYS_P0_MFP_ALT0_Pos Ú P SYS_P0_MFP_ALT0_Msk Ú P SYS_P0_MFP_ALT1_Pos Ú P SYS_P0_MFP_ALT1_Msk Ú P SYS_P0_MFP_ALT2_Pos Ú P SYS_P0_MFP_ALT2_Msk Ú P SYS_P0_MFP_ALT3_Pos Ú P SYS_P0_MFP_ALT3_Msk Ú P SYS_P0_MFP_ALT4_Pos Ú P SYS_P0_MFP_ALT4_Msk Ú P SYS_P0_MFP_ALT5_Pos Ú P SYS_P0_MFP_ALT5_Msk Ú P SYS_P0_MFP_ALT6_Pos ~Ú P SYS_P0_MFP_ALT6_Msk
Ú P SYS_P0_MFP_ALT7_Pos }Ú P SYS_P0_MFP_ALT7_Msk Ú P SYS_P1_MFP_MFP_Pos ³Ú P SYS_P1_MFP_MFP_Msk ºÚ P SYS_P1_MFP_ALT0_Pos Ú P SYS_P1_MFP_ALT0_Msk Ú P SYS_P1_MFP_ALT1_Pos Ú P SYS_P1_MFP_ALT1_Msk Ú P SYS_P1_MFP_ALT2_Pos Ú P SYS_P1_MFP_ALT2_Msk Ú P SYS_P1_MFP_ALT3_Pos Ú P SYS_P1_MFP_ALT3_Msk Ú P SYS_P1_MFP_ALT4_Pos Ú P SYS_P1_MFP_ALT4_Msk Ú P SYS_P1_MFP_ALT5_Pos ~Ú P SYS_P1_MFP_ALT5_Msk
Ú P SYS_P1_MFP_ALT6_Pos }Ú P SYS_P1_MFP_ALT6_Msk Ú P SYS_P1_MFP_ALT7_Pos |Ú P SYS_P1_MFP_ALT7_Msk Ú P SYS_P1_MFP_TYPE_Pos RÚ P SYS_P1_MFP_TYPE_Msk YÚ P SYS_P1_MFP_P12EXT_Pos ìÚ P SYS_P1_MFP_P12EXT_Msk óÚ P SYS_P1_MFP_P13EXT_Pos ëÚ P SYS_P1_MFP_P13EXT_Msk òÚ P SYS_P1_MFP_P14EXT_Pos êÚ P SYS_P1_MFP_P14EXT_Msk ñÚ P SYS_P2_MFP_ALT0_Pos Ú P SYS_P2_MFP_ALT0_Msk Ú P SYS_P2_MFP_ALT1_Pos Ú P SYS_P2_MFP_ALT1_Msk Ú P SYS_P2_MFP_ALT2_Pos Ú P SYS_P2_MFP_ALT2_Msk Ú P SYS_P2_MFP_ALT3_Pos Ú P SYS_P2_MFP_ALT3_Msk Ú P SYS_P2_MFP_ALT4_Pos ~Ú P SYS_P2_MFP_ALT4_Msk
Ú P SYS_P2_MFP_ALT5_Pos }Ú P SYS_P2_MFP_ALT5_Msk Ú P SYS_P2_MFP_ALT6_Pos |Ú P SYS_P2_MFP_ALT6_Msk Ú P SYS_P2_MFP_ALT7_Pos {Ú P SYS_P2_MFP_ALT7_Msk Ú P SYS_P3_MFP_MFP_Pos ±Ú P SYS_P3_MFP_MFP_Msk ¸Ú P SYS_P3_MFP_ALT0_Pos Ú P SYS_P3_MFP_ALT0_Msk Ú P SYS_P3_MFP_ALT1_Pos Ú P SYS_P3_MFP_ALT1_Msk Ú P SYS_P3_MFP_ALT2_Pos Ú P SYS_P3_MFP_ALT2_Msk Ú P SYS_P3_MFP_ALT4_Pos }Ú P SYS_P3_MFP_ALT4_Msk Ú P SYS_P3_MFP_ALT5_Pos |Ú P SYS_P3_MFP_ALT5_Msk Ú P SYS_P3_MFP_ALT6_Pos {Ú P SYS_P3_MFP_ALT6_Msk Ú P SYS_P3_MFP_P32EXT_Pos èÚ P SYS_P3_MFP_P32EXT_Msk ïÚ P SYS_P4_MFP_MFP_Pos °Ú P SYS_P4_MFP_MFP_Msk ·Ú P SYS_P4_MFP_ALT6_Pos zÚ P SYS_P4_MFP_ALT6_Msk Ú P SYS_P4_MFP_ALT7_Pos yÚ P SYS_P4_MFP_ALT7_Msk Ú P SYS_P5_MFP_MFP_Pos ¯Ú P SYS_P5_MFP_MFP_Msk ¶Ú P SYS_P5_MFP_ALT0_Pos Ú P SYS_P5_MFP_ALT0_Msk Ú P SYS_P5_MFP_ALT1_Pos ~Ú P SYS_P5_MFP_ALT1_Msk
Ú P SYS_P5_MFP_ALT2_Pos }Ú P SYS_P5_MFP_ALT2_Msk Ú P SYS_P5_MFP_ALT3_Pos |Ú P SYS_P5_MFP_ALT3_Msk Ú P SYS_P5_MFP_ALT4_Pos {Ú P SYS_P5_MFP_ALT4_Msk Ú P SYS_P5_MFP_ALT5_Pos zÚ P SYS_P5_MFP_ALT5_Msk Ú P SYS_P5_MFP_ALT6_Pos yÚ P SYS_P5_MFP_ALT6_Msk Ú P SYS_P5_MFP_ALT7_Pos xÚ P SYS_P5_MFP_ALT7_Msk Ú P SYS_P5_MFP_P50EXT_Pos æÚ P SYS_P5_MFP_P50EXT_Msk íÚ P SYS_P5_MFP_P51EXT_Pos åÚ P SYS_P5_MFP_P51EXT_Msk ìÚ P SYS_REGLCTL_REGLCTL_Pos 5Ú P SYS_REGLCTL_REGLCTL_Msk <Ú 8
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<unnamed> QÚ
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" · RSTSTS Ú
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" · IPRST0 8Ú
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" · IPRST1 7Ú
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" ·
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BODCTL_3V TÚ
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" · BLDBCTL_3V Ú
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" · CLK_TOP_CTRL_3V @Ú
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" · RCL_CTRL_3V Ú
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" · RCH_CTRL
Ú
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" · XTL_CTRL_3V |Ú
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" · XTH_CTRL nÚ
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" ·
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DPLL_CTRL 4Ú
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" · AHB_CLK_CTRL VÚ
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" · APB1_CLK_CTRL Ú
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" · APB2_CLK_CTRL Ú
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" · MEAS_CLK_CTRL ùÚ CLK_T jÚ P CLK_RSTSTS_CHIPRF_Pos ÉÚ P CLK_RSTSTS_CHIPRF_Msk ÐÚ P CLK_RSTSTS_PINRF_Pos Ú P CLK_RSTSTS_PINRF_Msk Ú P CLK_RSTSTS_WDTRF_Pos Ú P CLK_RSTSTS_WDTRF_Msk Ú P CLK_RSTSTS_LVRRF_Pos ûÚ P CLK_RSTSTS_LVRRF_Msk Ú P CLK_RSTSTS_BODRF_Pos Ú P CLK_RSTSTS_BODRF_Msk !Ú P CLK_RSTSTS_SYSRF_Pos ðÚ P CLK_RSTSTS_SYSRF_Msk ÷Ú P CLK_RSTSTS_PORRF_Pos þÚ P CLK_RSTSTS_PORRF_Msk Ú P CLK_RSTSTS_CPURF_Pos Ú P CLK_RSTSTS_CPURF_Msk Ú P CLK_IPRST0_CHIPRST_Pos Ú P CLK_IPRST0_CHIPRST_Msk Ú P CLK_IPRST0_CPURST_Pos ÕÚ P CLK_IPRST0_CPURST_Msk ÜÚ P CLK_IPRST0_DMARST_Pos ëÚ P CLK_IPRST0_DMARST_Msk òÚ P CLK_IPRST0_RFRST_Pos 'Ú P CLK_IPRST0_RFRST_Msk .Ú P CLK_IPRST0_EFUSERST_Pos AÚ P CLK_IPRST0_EFUSERST_Msk HÚ P CLK_IPRST0_USBRST_Pos ÓÚ P CLK_IPRST0_USBRST_Msk ÚÚ# P CLK_IPRST0_MDMSTDBYRST_Pos OÚ# P CLK_IPRST0_MDMSTDBYRST_Msk VÚ P CLK_IPRST0_MDMRST_Pos ßÚ P CLK_IPRST0_MDMRST_Msk æÚ# P CLK_IPRST0_CHIPSCOPEEN_Pos {Ú# P CLK_IPRST0_CHIPSCOPEEN_Msk Ú P CLK_IPRST0_FTORRST_Pos Ú P CLK_IPRST0_FTORRST_Msk Ú P CLK_IPRST1_I2C0RST_Pos ÌÚ P CLK_IPRST1_I2C0RST_Msk ÓÚ P CLK_IPRST1_SPI0RST_Pos Ú P CLK_IPRST1_SPI0RST_Msk ¥Ú P CLK_IPRST1_SPI1RST_Pos Ú P CLK_IPRST1_SPI1RST_Msk ¤Ú P CLK_IPRST1_UART0RST_Pos LÚ P CLK_IPRST1_UART0RST_Msk SÚ P CLK_IPRST1_UART1RST_Pos KÚ P CLK_IPRST1_UART1RST_Msk RÚ P CLK_IPRST1_PWM0RST_Pos Ú P CLK_IPRST1_PWM0RST_Msk Ú P CLK_IPRST1_ADCRST_Pos ôÚ P CLK_IPRST1_ADCRST_Msk ûÚ P CLK_IPRST1_WDTRST_Pos ÍÚ P CLK_IPRST1_WDTRST_Msk ÔÚ P CLK_IPRST1_WWDTRST_Pos tÚ P CLK_IPRST1_WWDTRST_Msk {Ú P CLK_IPRST1_TMR0RST_Pos Ú P CLK_IPRST1_TMR0RST_Msk Ú P CLK_IPRST1_TMR1RST_Pos Ú P CLK_IPRST1_TMR1RST_Msk Ú P CLK_IPRST1_TMR2RST_Pos Ú P CLK_IPRST1_TMR2RST_Msk Ú P CLK_IPRST1_GPIORST_Pos Ú P CLK_IPRST1_GPIORST_Msk Ú P CLK_IPRST1_TRIMRST_Pos ~Ú P CLK_IPRST1_TRIMRST_Msk
Ú# P CLK_BODCTL_BODRSTEN_Pos_3v MÚ# P CLK_BODCTL_BODRSTEN_Msk_3v TÚ P CLK_BODCTL_BODIF_Pos ^Ú P CLK_BODCTL_BODIF_Msk eÚ P CLK_BODCTL_BODOUT_Pos óÚ P CLK_BODCTL_BODOUT_Msk úÚ P CLK_BODCTL_LVREN_Pos_3v -Ú P CLK_BODCTL_LVREN_Msk_3v 4Ú P CLK_BODCTL_BODEN_Pos_3v LÚ P CLK_BODCTL_BODEN_Msk_3v SÚ! P CLK_BODCTL_BODSEL_Pos_3v ùÚ! P CLK_BODCTL_BODSEL_Msk_3v Ú# P CLK_BODCTL_LVR_TEST_Pos_3v Ú# P CLK_BODCTL_LVR_TEST_Msk_3v "Ú# P CLK_BODCTL_BOD_TEST_Pos_3v :Ú# P CLK_BODCTL_BOD_TEST_Msk_3v AÚ% P CLK_BLDBCTL_LVRDB_SEL_Pos_3v ®Ú% P CLK_BLDBCTL_LVRDB_SEL_Msk_3v µÚ% P CLK_BLDBCTL_BODDB_SEL_Pos_3v ÍÚ% P CLK_BLDBCTL_BODDB_SEL_Msk_3v ÔÚ' P CLK_TOPCTL_RSICV_SYSCNT_EN_Pos ÔÚ' P CLK_TOPCTL_RSICV_SYSCNT_EN_Msk ÛÚ# P CLK_TOPCTL_SYS_CLK_SEL_Pos Ú# P CLK_TOPCTL_SYS_CLK_SEL_Msk $Ú& P CLK_TOPCTL_32K_CLK_SEL_Pos_3v ^Ú& P CLK_TOPCTL_32K_CLK_SEL_Msk_3v eÚ P CLK_TOPCTL_AHB_DIV_Pos Ú P CLK_TOPCTL_AHB_DIV_Msk Ú P CLK_TOPCTL_APB1_DIV_Pos XÚ P CLK_TOPCTL_APB1_DIV_Msk _Ú P CLK_TOPCTL_APB2_DIV_Pos WÚ P CLK_TOPCTL_APB2_DIV_Msk ^Ú# P CLK_RCLCTL_RC32K_EN_Pos_3v kÚ# P CLK_RCLCTL_RC32K_EN_Msk_3v rÚ$ P CLK_RCLCTL_RC32K_TST_EN_Pos Ú$ P CLK_RCLCTL_RC32K_TST_EN_Msk Ú" P CLK_RCLCTL_CLK_SEL_Pos_3v Ú" P CLK_RCLCTL_CLK_SEL_Msk_3v Ú' P CLK_RCLCTL_RC32K_COARSE_Pos_3v 9Ú' P CLK_RCLCTL_RC32K_COARSE_Msk_3v @Ú% P CLK_RCLCTL_RC32K_FINE_Pos_3v ØÚ% P CLK_RCLCTL_RC32K_FINE_Msk_3v ßÚ& P CLK_RCLCTL_RC32K_DELAY_Pos_3v Ú& P CLK_RCLCTL_RC32K_DELAY_Msk_3v Ú P CLK_RCLCTL_STABLE_Pos ùÚ P CLK_RCLCTL_STABLE_Msk Ú P CLK_RCHCTL_RCH_EN_Pos éÚ P CLK_RCHCTL_RCH_EN_Msk ðÚ" P CLK_RCHCTL_RCH_TST_EN_Pos Ú" P CLK_RCHCTL_RCH_TST_EN_Msk Ú P CLK_RCHCTL_CLK_SEL_Pos Ú P CLK_RCHCTL_CLK_SEL_Msk Ú P CLK_RCHCTL_BIAS_Pos Ú P CLK_RCHCTL_BIAS_Msk ¤Ú P CLK_RCHCTL_RCH_FREQ_Pos JÚ P CLK_RCHCTL_RCH_FREQ_Msk QÚ P CLK_RCHCTL_DELAY_Pos KÚ P CLK_RCHCTL_DELAY_Msk RÚ P CLK_RCHCTL_STABLE_Pos ýÚ P CLK_RCHCTL_STABLE_Msk Ú! P CLK_XTLCTL_XTL_EN_Pos_3v ¥Ú! P CLK_XTLCTL_XTL_EN_Msk_3v ¬Ú" P CLK_XTLCTL_XTL_TST_EN_Pos QÚ" P CLK_XTLCTL_XTL_TST_EN_Msk XÚ$ P CLK_XTLCTL_CORE_BIAS_Pos_3v âÚ$ P CLK_XTLCTL_CORE_BIAS_Msk_3v éÚ# P CLK_XTLCTL_XTL_TRIM_Pos_3v øÚ# P CLK_XTLCTL_XTL_TRIM_Msk_3v ÿÚ% P CLK_XTLCTL_XTL_CAP_EN_Pos_3v jÚ% P CLK_XTLCTL_XTL_CAP_EN_Msk_3v qÚ P CLK_XTLCTL_DELAY_Pos_3v "Ú P CLK_XTLCTL_DELAY_Msk_3v )Ú P CLK_XTLCTL_STABLE_Pos âÚ P CLK_XTLCTL_STABLE_Msk éÚ P CLK_XTHCTL_XTH_EN_Pos »Ú P CLK_XTHCTL_XTH_EN_Msk ÂÚ" P CLK_XTHCTL_XTH_TST_EN_Pos YÚ" P CLK_XTHCTL_XTH_TST_EN_Msk `Ú" P CLK_XTHCTL_START_FAST_Pos ~Ú" P CLK_XTHCTL_START_FAST_Msk
Ú# P CLK_XTHCTL_DEGLITCH_EN_Pos aÚ# P CLK_XTHCTL_DEGLITCH_EN_Msk hÚ" P CLK_XTHCTL_XO_CAP_SEL_Pos |Ú" P CLK_XTHCTL_XO_CAP_SEL_Msk Ú P CLK_XTHCTL_DELAY_Pos 4Ú P CLK_XTHCTL_DELAY_Msk ;Ú P CLK_XTHCTL_STABLE_Pos æÚ P CLK_XTHCTL_STABLE_Msk íÚ P CLK_DPLLCTL_DPLL_EN_Pos GÚ P CLK_DPLLCTL_DPLL_EN_Msk NÚ$ P CLK_DPLLCTL_DPLL_TST_EN_Pos åÚ$ P CLK_DPLLCTL_DPLL_TST_EN_Msk ìÚ! P CLK_DPLLCTL_FREQ_OUT_Pos ÞÚ! P CLK_DPLLCTL_FREQ_OUT_Msk åÚ! P CLK_DPLLCTL_RCLK_SEL_Pos ôÚ! P CLK_DPLLCTL_RCLK_SEL_Msk ûÚ! P CLK_DPLLCTL_ICP_BIAS_Pos Ú! P CLK_DPLLCTL_ICP_BIAS_Msk Ú! P CLK_DPLLCTL_ICP_CTRL_Pos óÚ! P CLK_DPLLCTL_ICP_CTRL_Msk úÚ" P CLK_DPLLCTL_KVCO_CTRL_Pos Ú" P CLK_DPLLCTL_KVCO_CTRL_Msk ¡Ú& P CLK_DPLLCTL_VCO_FREQ_TRIM_Pos IÚ& P CLK_DPLLCTL_VCO_FREQ_TRIM_Msk PÚ P CLK_DPLLCTL_DIV_SEL_Pos ?Ú P CLK_DPLLCTL_DIV_SEL_Msk FÚ P CLK_DPLLCTL_DELAY_Pos úÚ P CLK_DPLLCTL_DELAY_Msk Ú P CLK_DPLLCTL_STABLE_Pos ¬Ú P CLK_DPLLCTL_STABLE_Msk ³Ú P CLK_AHBCLK_DMAEN_Pos pÚ P CLK_AHBCLK_DMAEN_Msk wÚ P CLK_AHBCLK_GPIOEN_Pos Ú P CLK_AHBCLK_GPIOEN_Msk Ú" P CLK_AHBCLK_SYSTICK_EN_Pos ¯Ú" P CLK_AHBCLK_SYSTICK_EN_Msk ¶Ú P CLK_AHBCLK_APB1EN_Pos <Ú P CLK_AHBCLK_APB1EN_Msk CÚ P CLK_AHBCLK_APB2EN_Pos ;Ú P CLK_AHBCLK_APB2EN_Msk BÚ P CLK_AHBCLK_AHBEN_Pos wÚ P CLK_AHBCLK_AHBEN_Msk ~Ú! P CLK_AHBCLK_BLE32M_EN_Pos VÚ! P CLK_AHBCLK_BLE32M_EN_Msk ]Ú! P CLK_AHBCLK_BLE32K_EN_Pos XÚ! P CLK_AHBCLK_BLE32K_EN_Msk _Ú" P CLK_AHBCLK_BLE32M_SEL_Pos Ú" P CLK_AHBCLK_BLE32M_SEL_Msk
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Ú" P CLK_AHBCLK_ROM_CLK_EN_Pos ²Ú" P CLK_AHBCLK_ROM_CLK_EN_Msk ¹Ú$ P CLK_AHBCLK_EFUSE_CLK_EN_Pos $Ú$ P CLK_AHBCLK_EFUSE_CLK_EN_Msk +Ú& P CLK_AHBCLK_USB_AHB_CLK_EN_Pos Ú& P CLK_AHBCLK_USB_AHB_CLK_EN_Msk Ú& P CLK_AHBCLK_USB_48M_CLK_EN_Pos Ú& P CLK_AHBCLK_USB_48M_CLK_EN_Msk Ú% P CLK_AHBCLK_SPI_FLASH_DIV_Pos ÊÚ% P CLK_AHBCLK_SPI_FLASH_DIV_Msk ÑÚ) P !CLK_AHBCLK_SPI_FLASH_CLK_SEL_Pos Ú) P !CLK_AHBCLK_SPI_FLASH_CLK_SEL_Msk Ú' P CLK_AHBCLK_DPLL_CLK_TST_EN_Pos Ú' P CLK_AHBCLK_DPLL_CLK_TST_EN_Msk Ú( P CLK_AHBCLK_SPI_CLK_SEL_FPGA_Pos ÚÚ( P CLK_AHBCLK_SPI_CLK_SEL_FPGA_Msk áÚ# P CLK_APB1CLK_WDTSRC_SEL_Pos vÚ# P CLK_APB1CLK_WDTSRC_SEL_Msk }Ú$ P CLK_APB1CLK_WWDTSRC_SEL_Pos Ú$ P CLK_APB1CLK_WWDTSRC_SEL_Msk $Ú$ P CLK_APB1CLK_TMR0SRC_SEL_Pos @Ú$ P CLK_APB1CLK_TMR0SRC_SEL_Msk GÚ& P CLK_APB1CLK_PWM01_CLK_SEL_Pos ¹Ú& P CLK_APB1CLK_PWM01_CLK_SEL_Msk ÀÚ& P CLK_APB1CLK_PWM23_CLK_SEL_Pos µÚ& P CLK_APB1CLK_PWM23_CLK_SEL_Msk ¼Ú& P CLK_APB1CLK_PWM45_CLK_SEL_Pos ±Ú& P CLK_APB1CLK_PWM45_CLK_SEL_Msk ¸Ú& P CLK_APB1CLK_PWM67_CLK_SEL_Pos Ú& P CLK_APB1CLK_PWM67_CLK_SEL_Msk ´Ú$ P CLK_APB1CLK_ADC_CLK_SEL_Pos JÚ$ P CLK_APB1CLK_ADC_CLK_SEL_Msk QÚ$ P CLK_APB2CLK_TMR1SRC_SEL_Pos >Ú$ P CLK_APB2CLK_TMR1SRC_SEL_Msk EÚ$ P CLK_APB2CLK_TMR2SRC_SEL_Pos =Ú$ P CLK_APB2CLK_TMR2SRC_SEL_Msk DÚ$ P CLK_MEASCLK_TRIM_CLK_EN_Pos Ú$ P CLK_MEASCLK_TRIM_CLK_EN_Msk Ú% P CLK_MEASCLK_TRIM_CLK_SEL_Pos ²Ú% P CLK_MEASCLK_TRIM_CLK_SEL_Msk ¹Ú% P CLK_MEASCLK_TRIM_CLK_DIV_Pos ³Ú% P CLK_MEASCLK_TRIM_CLK_DIV_Msk ºÚ% P CLK_MEASCLK_XTL_QUICK_EN_Pos ¤Ú% P CLK_MEASCLK_XTL_QUICK_EN_Msk «Ú P CLK_MEASCLK_XTH_DIV_Pos >Ú P CLK_MEASCLK_XTH_DIV_Msk EÚ 8
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<unnamed> QÚ
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" ¶CTL Ú
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" ¶ALTCTL 5Ú WDT_T UÚ P WDT_CTL_RSTCNT_Pos ¨Ú P WDT_CTL_RSTCNT_Msk ¯Ú P WDT_CTL_RSTEN_Pos üÚ P WDT_CTL_RSTEN_Msk Ú P WDT_CTL_RSTF_Pos KÚ P WDT_CTL_RSTF_Msk RÚ P WDT_CTL_IF_Pos ÿÚ P WDT_CTL_IF_Msk Ú P WDT_CTL_WKEN_Pos UÚ P WDT_CTL_WKEN_Msk \Ú P WDT_CTL_WKF_Pos ¤Ú P WDT_CTL_WKF_Msk «Ú P WDT_CTL_INTEN_Pos
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Ú P WDT_CTL_INTEN_Msk Ú P WDT_CTL_WDTEN_Pos Ú P WDT_CTL_WDTEN_Msk Ú P WDT_CTL_TOUTSEL_Pos TÚ P WDT_CTL_TOUTSEL_Msk [Ú# P WDT_CTL_RST_REGION_SEL_Pos Ú# P WDT_CTL_RST_REGION_SEL_Msk Ú P WDT_CTL_TOF_Pos £Ú P WDT_CTL_TOF_Msk ªÚ P WDT_CTL_ICEDEBUG_Pos JÚ P WDT_CTL_ICEDEBUG_Msk QÚ P WDT_ALTCTL_RSTDSEL_Pos |Ú P WDT_ALTCTL_RSTDSEL_Msk Ú 8
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<unnamed> QÚ
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" ÔRLDCNT Ú
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" ÔCTL þÚ
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" ÔSTATUS ÷Ú
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" ÔCNT üÚ WWDT_T üÚ P WWDT_RLDCNT_RLDCNT_Pos |Ú P WWDT_RLDCNT_RLDCNT_Msk Ú P WWDT_CTL_WWDTEN_Pos TÚ P WWDT_CTL_WWDTEN_Msk [Ú P WWDT_CTL_INTEN_Pos ±Ú P WWDT_CTL_INTEN_Msk ¸Ú P WWDT_CTL_PSCSEL_Pos cÚ P WWDT_CTL_PSCSEL_Msk jÚ P WWDT_CTL_CMPDAT_Pos tÚ P WWDT_CTL_CMPDAT_Msk {Ú P WWDT_CTL_ICEDEBUG_Pos ñÚ P WWDT_CTL_ICEDEBUG_Msk øÚ P WWDT_STATUS_WWDTIF_Pos QÚ P WWDT_STATUS_WWDTIF_Msk XÚ P WWDT_STATUS_WWDTRF_Pos HÚ P WWDT_STATUS_WWDTRF_Msk OÚ P WWDT_STATUS_WWDTF_Pos Ú P WWDT_STATUS_WWDTF_Msk £Ú P WWDT_CNT_CNTDAT_Pos mÚ P WWDT_CNT_CNTDAT_Msk tÚ 8
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<unnamed> QÚ
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" îCLKPSC Ú
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" îCLKDIV Ú
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" îCTL äÚ
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" îPERIOD0 ÌÚ
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" îPERIOD1 ËÚ
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" îPERIOD2 ÊÚ
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" îPERIOD3 ÉÚ
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" îPERIOD4 ÈÚ
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" îPERIOD5 ÇÚ
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" îPERIOD6 ÆÚ
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" îPERIOD7 ÅÚ
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" îCMPDAT0 ÖÚ
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" îCMPDAT1 ÕÚ
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" îCMPDAT2 ÔÚ
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" îCMPDAT3 ÓÚ
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" îCMPDAT4 ÒÚ
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" îCMPDAT5 ÑÚ
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" îCMPDAT6 ÐÚ
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" îCMPDAT7 ÏÚ
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" îCTL2 °Ú
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" îFLAG «Ú
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" îINTEN EÚ
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" îINTSTS ÜÚ
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" îPOEN Ú <" î
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RESERVED0 ùÚ
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" îDTCTL HÚ
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" î ADCTCTL0 Ú
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" î ADCTCTL1 Ú
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" î ADCTSTS0 wÚ
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" î ADCTSTS1 vÚ <" î
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RESERVED1 ìÚ
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" îPCACTL
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Ú PWM_T PÚ P PWM_CLKPSC_CLKPSC01_Pos yÚ P PWM_CLKPSC_CLKPSC01_Msk Ú P PWM_CLKPSC_CLKPSC23_Pos uÚ P PWM_CLKPSC_CLKPSC23_Msk |Ú P PWM_CLKPSC_CLKPSC45_Pos qÚ P PWM_CLKPSC_CLKPSC45_Msk xÚ P PWM_CLKPSC_CLKPSC67_Pos mÚ P PWM_CLKPSC_CLKPSC67_Msk tÚ P PWM_CLKDIV_CLKDIV0_Pos ²Ú P PWM_CLKDIV_CLKDIV0_Msk ¹Ú P PWM_CLKDIV_CLKDIV1_Pos ±Ú P PWM_CLKDIV_CLKDIV1_Msk ¸Ú P PWM_CLKDIV_CLKDIV2_Pos °Ú P PWM_CLKDIV_CLKDIV2_Msk ·Ú P PWM_CLKDIV_CLKDIV3_Pos ¯Ú P PWM_CLKDIV_CLKDIV3_Msk ¶Ú P PWM_CLKDIV_CLKDIV4_Pos ®Ú P PWM_CLKDIV_CLKDIV4_Msk µÚ P PWM_CLKDIV_CLKDIV5_Pos Ú P PWM_CLKDIV_CLKDIV5_Msk ´Ú P PWM_CLKDIV_CLKDIV6_Pos ¬Ú P PWM_CLKDIV_CLKDIV6_Msk ³Ú P PWM_CLKDIV_CLKDIV7_Pos «Ú P PWM_CLKDIV_CLKDIV7_Msk ²Ú P PWM_CTL_CNTEN0_Pos ÙÚ P PWM_CTL_CNTEN0_Msk àÚ P PWM_CTL_PINV0_Pos Ú P PWM_CTL_PINV0_Msk Ú P PWM_CTL_CNTMODE0_Pos CÚ P PWM_CTL_CNTMODE0_Msk JÚ P PWM_CTL_CNTEN1_Pos ØÚ P PWM_CTL_CNTEN1_Msk ßÚ P PWM_CTL_HCUPDT_Pos ¹Ú P PWM_CTL_HCUPDT_Msk ÀÚ P PWM_CTL_PINV1_Pos Ú P PWM_CTL_PINV1_Msk Ú P PWM_CTL_CNTMODE1_Pos BÚ P PWM_CTL_CNTMODE1_Msk IÚ P PWM_CTL_CNTEN2_Pos ×Ú P PWM_CTL_CNTEN2_Msk ÞÚ P PWM_CTL_PINV2_Pos Ú P PWM_CTL_PINV2_Msk Ú P PWM_CTL_CNTMODE2_Pos AÚ P PWM_CTL_CNTMODE2_Msk HÚ P PWM_CTL_CNTEN3_Pos ÖÚ P PWM_CTL_CNTEN3_Msk ÝÚ P PWM_CTL_PINV3_Pos Ú P PWM_CTL_PINV3_Msk Ú P PWM_CTL_CNTMODE3_Pos @Ú P PWM_CTL_CNTMODE3_Msk GÚ P PWM_CTL_CNTEN4_Pos ÕÚ P PWM_CTL_CNTEN4_Msk ÜÚ P PWM_CTL_PINV4_Pos Ú P PWM_CTL_PINV4_Msk Ú P PWM_CTL_CNTMODE4_Pos ?Ú P PWM_CTL_CNTMODE4_Msk FÚ P PWM_CTL_CNTEN5_Pos ÔÚ P PWM_CTL_CNTEN5_Msk ÛÚ P PWM_CTL_ASYMEN_Pos ´Ú P PWM_CTL_ASYMEN_Msk »Ú P PWM_CTL_PINV5_Pos Ú P PWM_CTL_PINV5_Msk Ú P PWM_CTL_CNTMODE5_Pos >Ú P PWM_CTL_CNTMODE5_Msk EÚ P PWM_CTL_CNTEN6_Pos ÓÚ P PWM_CTL_CNTEN6_Msk ÚÚ P PWM_CTL_PINV6_Pos Ú P PWM_CTL_PINV6_Msk Ú P PWM_CTL_CNTMODE6_Pos =Ú P PWM_CTL_CNTMODE6_Msk DÚ P PWM_CTL_CNTEN7_Pos ÒÚ P PWM_CTL_CNTEN7_Msk ÙÚ P PWM_CTL_PINV7_Pos Ú P PWM_CTL_PINV7_Msk Ú P PWM_CTL_CNTMODE7_Pos <Ú P PWM_CTL_CNTMODE7_Msk CÚ P PWM_PERIOD0_PERIOD0_Pos tÚ P PWM_PERIOD0_PERIOD0_Msk {Ú P PWM_PERIOD0_PERIOD1_Pos sÚ P PWM_PERIOD0_PERIOD1_Msk zÚ P PWM_PERIOD0_PERIOD2_Pos rÚ P PWM_PERIOD0_PERIOD2_Msk yÚ P PWM_PERIOD0_PERIOD3_Pos qÚ P PWM_PERIOD0_PERIOD3_Msk xÚ P PWM_PERIOD0_PERIOD4_Pos pÚ P PWM_PERIOD0_PERIOD4_Msk wÚ P PWM_PERIOD0_PERIOD5_Pos oÚ P PWM_PERIOD0_PERIOD5_Msk vÚ P PWM_PERIOD0_PERIOD6_Pos nÚ P PWM_PERIOD0_PERIOD6_Msk uÚ P PWM_PERIOD0_PERIOD7_Pos mÚ P PWM_PERIOD0_PERIOD7_Msk tÚ P PWM_PERIOD1_PERIOD0_Pos sÚ P PWM_PERIOD1_PERIOD0_Msk zÚ P PWM_PERIOD1_PERIOD1_Pos rÚ P PWM_PERIOD1_PERIOD1_Msk yÚ P PWM_PERIOD1_PERIOD2_Pos qÚ P PWM_PERIOD1_PERIOD2_Msk xÚ P PWM_PERIOD1_PERIOD3_Pos pÚ P PWM_PERIOD1_PERIOD3_Msk wÚ P PWM_PERIOD1_PERIOD4_Pos oÚ P PWM_PERIOD1_PERIOD4_Msk vÚ P PWM_PERIOD1_PERIOD5_Pos nÚ P PWM_PERIOD1_PERIOD5_Msk uÚ P PWM_PERIOD1_PERIOD6_Pos mÚ P PWM_PERIOD1_PERIOD6_Msk tÚ P PWM_PERIOD1_PERIOD7_Pos lÚ P PWM_PERIOD1_PERIOD7_Msk sÚ P PWM_PERIOD2_PERIOD0_Pos rÚ P PWM_PERIOD2_PERIOD0_Msk yÚ P PWM_PERIOD2_PERIOD1_Pos qÚ P PWM_PERIOD2_PERIOD1_Msk xÚ P PWM_PERIOD2_PERIOD2_Pos pÚ P PWM_PERIOD2_PERIOD2_Msk wÚ P PWM_PERIOD2_PERIOD3_Pos oÚ P PWM_PERIOD2_PERIOD3_Msk vÚ P PWM_PERIOD2_PERIOD4_Pos nÚ P PWM_PERIOD2_PERIOD4_Msk uÚ P PWM_PERIOD2_PERIOD5_Pos mÚ P PWM_PERIOD2_PERIOD5_Msk tÚ P PWM_PERIOD2_PERIOD6_Pos lÚ P PWM_PERIOD2_PERIOD6_Msk sÚ P PWM_PERIOD2_PERIOD7_Pos kÚ P PWM_PERIOD2_PERIOD7_Msk rÚ P PWM_PERIOD3_PERIOD0_Pos qÚ P PWM_PERIOD3_PERIOD0_Msk xÚ P PWM_PERIOD3_PERIOD1_Pos pÚ P PWM_PERIOD3_PERIOD1_Msk wÚ P PWM_PERIOD3_PERIOD2_Pos oÚ P PWM_PERIOD3_PERIOD2_Msk vÚ P PWM_PERIOD3_PERIOD3_Pos nÚ P PWM_PERIOD3_PERIOD3_Msk uÚ P PWM_PERIOD3_PERIOD4_Pos mÚ P PWM_PERIOD3_PERIOD4_Msk tÚ P PWM_PERIOD3_PERIOD5_Pos lÚ P PWM_PERIOD3_PERIOD5_Msk sÚ P PWM_PERIOD3_PERIOD6_Pos kÚ P PWM_PERIOD3_PERIOD6_Msk rÚ P PWM_PERIOD3_PERIOD7_Pos jÚ P PWM_PERIOD3_PERIOD7_Msk qÚ P PWM_PERIOD4_PERIOD0_Pos pÚ P PWM_PERIOD4_PERIOD0_Msk wÚ P PWM_PERIOD4_PERIOD1_Pos oÚ P PWM_PERIOD4_PERIOD1_Msk vÚ P PWM_PERIOD4_PERIOD2_Pos nÚ P PWM_PERIOD4_PERIOD2_Msk uÚ P PWM_PERIOD4_PERIOD3_Pos mÚ P PWM_PERIOD4_PERIOD3_Msk tÚ P PWM_PERIOD4_PERIOD4_Pos lÚ P PWM_PERIOD4_PERIOD4_Msk sÚ P PWM_PERIOD4_PERIOD5_Pos kÚ P PWM_PERIOD4_PERIOD5_Msk rÚ P PWM_PERIOD4_PERIOD6_Pos jÚ P PWM_PERIOD4_PERIOD6_Msk qÚ P PWM_PERIOD4_PERIOD7_Pos iÚ P PWM_PERIOD4_PERIOD7_Msk pÚ P PWM_PERIOD5_PERIOD0_Pos oÚ P PWM_PERIOD5_PERIOD0_Msk vÚ P PWM_PERIOD5_PERIOD1_Pos nÚ P PWM_PERIOD5_PERIOD1_Msk uÚ P PWM_PERIOD5_PERIOD2_Pos mÚ P PWM_PERIOD5_PERIOD2_Msk tÚ P PWM_PERIOD5_PERIOD3_Pos lÚ P PWM_PERIOD5_PERIOD3_Msk sÚ P PWM_PERIOD5_PERIOD4_Pos kÚ P PWM_PERIOD5_PERIOD4_Msk rÚ P PWM_PERIOD5_PERIOD5_Pos jÚ P PWM_PERIOD5_PERIOD5_Msk qÚ P PWM_PERIOD5_PERIOD6_Pos iÚ P PWM_PERIOD5_PERIOD6_Msk pÚ P PWM_PERIOD5_PERIOD7_Pos hÚ P PWM_PERIOD5_PERIOD7_Msk oÚ P PWM_PERIOD6_PERIOD0_Pos nÚ P PWM_PERIOD6_PERIOD0_Msk uÚ P PWM_PERIOD6_PERIOD1_Pos mÚ P PWM_PERIOD6_PERIOD1_Msk tÚ P PWM_PERIOD6_PERIOD2_Pos lÚ P PWM_PERIOD6_PERIOD2_Msk sÚ P PWM_PERIOD6_PERIOD3_Pos kÚ P PWM_PERIOD6_PERIOD3_Msk rÚ P PWM_PERIOD6_PERIOD4_Pos jÚ P PWM_PERIOD6_PERIOD4_Msk qÚ P PWM_PERIOD6_PERIOD5_Pos iÚ P PWM_PERIOD6_PERIOD5_Msk pÚ P PWM_PERIOD6_PERIOD6_Pos hÚ P PWM_PERIOD6_PERIOD6_Msk oÚ P PWM_PERIOD6_PERIOD7_Pos gÚ P PWM_PERIOD6_PERIOD7_Msk nÚ P PWM_PERIOD7_PERIOD0_Pos mÚ P PWM_PERIOD7_PERIOD0_Msk tÚ P PWM_PERIOD7_PERIOD1_Pos lÚ P PWM_PERIOD7_PERIOD1_Msk sÚ P PWM_PERIOD7_PERIOD2_Pos kÚ P PWM_PERIOD7_PERIOD2_Msk rÚ P PWM_PERIOD7_PERIOD3_Pos jÚ P PWM_PERIOD7_PERIOD3_Msk qÚ P PWM_PERIOD7_PERIOD4_Pos iÚ P PWM_PERIOD7_PERIOD4_Msk pÚ P PWM_PERIOD7_PERIOD5_Pos hÚ P PWM_PERIOD7_PERIOD5_Msk oÚ P PWM_PERIOD7_PERIOD6_Pos gÚ P PWM_PERIOD7_PERIOD6_Msk nÚ P PWM_PERIOD7_PERIOD7_Pos fÚ P PWM_PERIOD7_PERIOD7_Msk mÚ P PWM_CMPDAT0_CMP0_Pos gÚ P PWM_CMPDAT0_CMP0_Msk nÚ P PWM_CMPDAT0_CMP1_Pos fÚ P PWM_CMPDAT0_CMP1_Msk mÚ P PWM_CMPDAT0_CMP2_Pos eÚ P PWM_CMPDAT0_CMP2_Msk lÚ P PWM_CMPDAT0_CMP3_Pos dÚ P PWM_CMPDAT0_CMP3_Msk kÚ P PWM_CMPDAT0_CMP4_Pos cÚ P PWM_CMPDAT0_CMP4_Msk jÚ P PWM_CMPDAT0_CMP5_Pos bÚ P PWM_CMPDAT0_CMP5_Msk iÚ P PWM_CMPDAT0_CMP6_Pos aÚ P PWM_CMPDAT0_CMP6_Msk hÚ P PWM_CMPDAT0_CMP7_Pos `Ú P PWM_CMPDAT0_CMP7_Msk gÚ P PWM_CMPDAT0_CMPD0_Pos !Ú P PWM_CMPDAT0_CMPD0_Msk (Ú P PWM_CMPDAT0_CMPD1_Pos Ú P PWM_CMPDAT0_CMPD1_Msk 'Ú P PWM_CMPDAT0_CMPD2_Pos Ú P PWM_CMPDAT0_CMPD2_Msk &Ú P PWM_CMPDAT0_CMPD3_Pos Ú P PWM_CMPDAT0_CMPD3_Msk %Ú P PWM_CMPDAT0_CMPD4_Pos Ú P PWM_CMPDAT0_CMPD4_Msk $Ú P PWM_CMPDAT0_CMPD5_Pos Ú P PWM_CMPDAT0_CMPD5_Msk #Ú P PWM_CMPDAT0_CMPD6_Pos Ú P PWM_CMPDAT0_CMPD6_Msk "Ú P PWM_CMPDAT0_CMPD7_Pos Ú P PWM_CMPDAT0_CMPD7_Msk !Ú P PWM_CMPDAT1_CMP0_Pos fÚ P PWM_CMPDAT1_CMP0_Msk mÚ P PWM_CMPDAT1_CMP1_Pos eÚ P PWM_CMPDAT1_CMP1_Msk lÚ P PWM_CMPDAT1_CMP2_Pos dÚ P PWM_CMPDAT1_CMP2_Msk kÚ P PWM_CMPDAT1_CMP3_Pos cÚ P PWM_CMPDAT1_CMP3_Msk jÚ P PWM_CMPDAT1_CMP4_Pos bÚ P PWM_CMPDAT1_CMP4_Msk iÚ P PWM_CMPDAT1_CMP5_Pos aÚ P PWM_CMPDAT1_CMP5_Msk hÚ P PWM_CMPDAT1_CMP6_Pos `Ú P PWM_CMPDAT1_CMP6_Msk gÚ P PWM_CMPDAT1_CMP7_Pos _Ú P PWM_CMPDAT1_CMP7_Msk fÚ P PWM_CMPDAT1_CMPD0_Pos Ú P PWM_CMPDAT1_CMPD0_Msk 'Ú P PWM_CMPDAT1_CMPD1_Pos Ú P PWM_CMPDAT1_CMPD1_Msk &Ú P PWM_CMPDAT1_CMPD2_Pos Ú P PWM_CMPDAT1_CMPD2_Msk %Ú P PWM_CMPDAT1_CMPD3_Pos Ú P PWM_CMPDAT1_CMPD3_Msk $Ú P PWM_CMPDAT1_CMPD4_Pos Ú P PWM_CMPDAT1_CMPD4_Msk #Ú P PWM_CMPDAT1_CMPD5_Pos Ú P PWM_CMPDAT1_CMPD5_Msk "Ú P PWM_CMPDAT1_CMPD6_Pos Ú P PWM_CMPDAT1_CMPD6_Msk !Ú P PWM_CMPDAT1_CMPD7_Pos Ú P PWM_CMPDAT1_CMPD7_Msk Ú P PWM_CMPDAT2_CMP0_Pos eÚ P PWM_CMPDAT2_CMP0_Msk lÚ P PWM_CMPDAT2_CMP1_Pos dÚ P PWM_CMPDAT2_CMP1_Msk kÚ P PWM_CMPDAT2_CMP2_Pos cÚ P PWM_CMPDAT2_CMP2_Msk jÚ P PWM_CMPDAT2_CMP3_Pos bÚ P PWM_CMPDAT2_CMP3_Msk iÚ P PWM_CMPDAT2_CMP4_Pos aÚ P PWM_CMPDAT2_CMP4_Msk hÚ P PWM_CMPDAT2_CMP5_Pos `Ú P PWM_CMPDAT2_CMP5_Msk gÚ P PWM_CMPDAT2_CMP6_Pos _Ú P PWM_CMPDAT2_CMP6_Msk fÚ P PWM_CMPDAT2_CMP7_Pos ^Ú P PWM_CMPDAT2_CMP7_Msk eÚ P PWM_CMPDAT2_CMPD0_Pos Ú P PWM_CMPDAT2_CMPD0_Msk &Ú P PWM_CMPDAT2_CMPD1_Pos Ú P PWM_CMPDAT2_CMPD1_Msk %Ú P PWM_CMPDAT2_CMPD2_Pos Ú P PWM_CMPDAT2_CMPD2_Msk $Ú P PWM_CMPDAT2_CMPD3_Pos Ú P PWM_CMPDAT2_CMPD3_Msk #Ú P PWM_CMPDAT2_CMPD4_Pos Ú P PWM_CMPDAT2_CMPD4_Msk "Ú P PWM_CMPDAT2_CMPD5_Pos Ú P PWM_CMPDAT2_CMPD5_Msk !Ú P PWM_CMPDAT2_CMPD6_Pos Ú P PWM_CMPDAT2_CMPD6_Msk Ú P PWM_CMPDAT2_CMPD7_Pos Ú P PWM_CMPDAT2_CMPD7_Msk Ú P PWM_CMPDAT3_CMP0_Pos dÚ P PWM_CMPDAT3_CMP0_Msk kÚ P PWM_CMPDAT3_CMP1_Pos cÚ P PWM_CMPDAT3_CMP1_Msk jÚ P PWM_CMPDAT3_CMP2_Pos bÚ P PWM_CMPDAT3_CMP2_Msk iÚ P PWM_CMPDAT3_CMP3_Pos aÚ P PWM_CMPDAT3_CMP3_Msk hÚ P PWM_CMPDAT3_CMP4_Pos `Ú P PWM_CMPDAT3_CMP4_Msk gÚ P PWM_CMPDAT3_CMP5_Pos _Ú P PWM_CMPDAT3_CMP5_Msk fÚ P PWM_CMPDAT3_CMP6_Pos ^Ú P PWM_CMPDAT3_CMP6_Msk eÚ P PWM_CMPDAT3_CMP7_Pos ]Ú P PWM_CMPDAT3_CMP7_Msk dÚ P PWM_CMPDAT3_CMPD0_Pos Ú P PWM_CMPDAT3_CMPD0_Msk %Ú P PWM_CMPDAT3_CMPD1_Pos Ú P PWM_CMPDAT3_CMPD1_Msk $Ú P PWM_CMPDAT3_CMPD2_Pos Ú P PWM_CMPDAT3_CMPD2_Msk #Ú P PWM_CMPDAT3_CMPD3_Pos Ú P PWM_CMPDAT3_CMPD3_Msk "Ú P PWM_CMPDAT3_CMPD4_Pos Ú P PWM_CMPDAT3_CMPD4_Msk !Ú P PWM_CMPDAT3_CMPD5_Pos Ú P PWM_CMPDAT3_CMPD5_Msk Ú P PWM_CMPDAT3_CMPD6_Pos Ú P PWM_CMPDAT3_CMPD6_Msk Ú P PWM_CMPDAT3_CMPD7_Pos Ú P PWM_CMPDAT3_CMPD7_Msk Ú P PWM_CMPDAT4_CMP0_Pos cÚ P PWM_CMPDAT4_CMP0_Msk jÚ P PWM_CMPDAT4_CMP1_Pos bÚ P PWM_CMPDAT4_CMP1_Msk iÚ P PWM_CMPDAT4_CMP2_Pos aÚ P PWM_CMPDAT4_CMP2_Msk hÚ P PWM_CMPDAT4_CMP3_Pos `Ú P PWM_CMPDAT4_CMP3_Msk gÚ P PWM_CMPDAT4_CMP4_Pos _Ú P PWM_CMPDAT4_CMP4_Msk fÚ P PWM_CMPDAT4_CMP5_Pos ^Ú P PWM_CMPDAT4_CMP5_Msk eÚ P PWM_CMPDAT4_CMP6_Pos ]Ú P PWM_CMPDAT4_CMP6_Msk dÚ P PWM_CMPDAT4_CMP7_Pos \Ú P PWM_CMPDAT4_CMP7_Msk cÚ P PWM_CMPDAT4_CMPD0_Pos Ú P PWM_CMPDAT4_CMPD0_Msk $Ú P PWM_CMPDAT4_CMPD1_Pos Ú P PWM_CMPDAT4_CMPD1_Msk #Ú P PWM_CMPDAT4_CMPD2_Pos Ú P PWM_CMPDAT4_CMPD2_Msk "Ú P PWM_CMPDAT4_CMPD3_Pos Ú P PWM_CMPDAT4_CMPD3_Msk !Ú P PWM_CMPDAT4_CMPD4_Pos Ú P PWM_CMPDAT4_CMPD4_Msk Ú P PWM_CMPDAT4_CMPD5_Pos Ú P PWM_CMPDAT4_CMPD5_Msk Ú P PWM_CMPDAT4_CMPD6_Pos Ú P PWM_CMPDAT4_CMPD6_Msk Ú P PWM_CMPDAT4_CMPD7_Pos Ú P PWM_CMPDAT4_CMPD7_Msk Ú P PWM_CMPDAT5_CMP0_Pos bÚ P PWM_CMPDAT5_CMP0_Msk iÚ P PWM_CMPDAT5_CMP1_Pos aÚ P PWM_CMPDAT5_CMP1_Msk hÚ P PWM_CMPDAT5_CMP2_Pos `Ú P PWM_CMPDAT5_CMP2_Msk gÚ P PWM_CMPDAT5_CMP3_Pos _Ú P PWM_CMPDAT5_CMP3_Msk fÚ P PWM_CMPDAT5_CMP4_Pos ^Ú P PWM_CMPDAT5_CMP4_Msk eÚ P PWM_CMPDAT5_CMP5_Pos ]Ú P PWM_CMPDAT5_CMP5_Msk dÚ P PWM_CMPDAT5_CMP6_Pos \Ú P PWM_CMPDAT5_CMP6_Msk cÚ P PWM_CMPDAT5_CMP7_Pos [Ú P PWM_CMPDAT5_CMP7_Msk bÚ P PWM_CMPDAT5_CMPD0_Pos Ú P PWM_CMPDAT5_CMPD0_Msk #Ú P PWM_CMPDAT5_CMPD1_Pos Ú P PWM_CMPDAT5_CMPD1_Msk "Ú P PWM_CMPDAT5_CMPD2_Pos Ú P PWM_CMPDAT5_CMPD2_Msk !Ú P PWM_CMPDAT5_CMPD3_Pos Ú P PWM_CMPDAT5_CMPD3_Msk Ú P PWM_CMPDAT5_CMPD4_Pos Ú P PWM_CMPDAT5_CMPD4_Msk Ú P PWM_CMPDAT5_CMPD5_Pos Ú P PWM_CMPDAT5_CMPD5_Msk Ú P PWM_CMPDAT5_CMPD6_Pos Ú P PWM_CMPDAT5_CMPD6_Msk Ú P PWM_CMPDAT5_CMPD7_Pos Ú P PWM_CMPDAT5_CMPD7_Msk Ú P PWM_CMPDAT6_CMP0_Pos aÚ P PWM_CMPDAT6_CMP0_Msk hÚ P PWM_CMPDAT6_CMP1_Pos `Ú P PWM_CMPDAT6_CMP1_Msk gÚ P PWM_CMPDAT6_CMP2_Pos _Ú P PWM_CMPDAT6_CMP2_Msk fÚ P PWM_CMPDAT6_CMP3_Pos ^Ú P PWM_CMPDAT6_CMP3_Msk eÚ P PWM_CMPDAT6_CMP4_Pos ]Ú P PWM_CMPDAT6_CMP4_Msk dÚ P PWM_CMPDAT6_CMP5_Pos \Ú P PWM_CMPDAT6_CMP5_Msk cÚ P PWM_CMPDAT6_CMP6_Pos [Ú P PWM_CMPDAT6_CMP6_Msk bÚ P PWM_CMPDAT6_CMP7_Pos ZÚ P PWM_CMPDAT6_CMP7_Msk aÚ P PWM_CMPDAT6_CMPD0_Pos Ú P PWM_CMPDAT6_CMPD0_Msk "Ú P PWM_CMPDAT6_CMPD1_Pos Ú P PWM_CMPDAT6_CMPD1_Msk !Ú P PWM_CMPDAT6_CMPD2_Pos Ú P PWM_CMPDAT6_CMPD2_Msk Ú P PWM_CMPDAT6_CMPD3_Pos Ú P PWM_CMPDAT6_CMPD3_Msk Ú P PWM_CMPDAT6_CMPD4_Pos Ú P PWM_CMPDAT6_CMPD4_Msk Ú P PWM_CMPDAT6_CMPD5_Pos Ú P PWM_CMPDAT6_CMPD5_Msk Ú P PWM_CMPDAT6_CMPD6_Pos Ú P PWM_CMPDAT6_CMPD6_Msk Ú P PWM_CMPDAT6_CMPD7_Pos Ú P PWM_CMPDAT6_CMPD7_Msk Ú P PWM_CMPDAT7_CMP0_Pos `Ú P PWM_CMPDAT7_CMP0_Msk gÚ P PWM_CMPDAT7_CMP1_Pos _Ú P PWM_CMPDAT7_CMP1_Msk fÚ P PWM_CMPDAT7_CMP2_Pos ^Ú P PWM_CMPDAT7_CMP2_Msk eÚ P PWM_CMPDAT7_CMP3_Pos ]Ú P PWM_CMPDAT7_CMP3_Msk dÚ P PWM_CMPDAT7_CMP4_Pos \Ú P PWM_CMPDAT7_CMP4_Msk cÚ P PWM_CMPDAT7_CMP5_Pos [Ú P PWM_CMPDAT7_CMP5_Msk bÚ P PWM_CMPDAT7_CMP6_Pos ZÚ P PWM_CMPDAT7_CMP6_Msk aÚ P PWM_CMPDAT7_CMP7_Pos YÚ P PWM_CMPDAT7_CMP7_Msk `Ú P PWM_CMPDAT7_CMPD0_Pos Ú P PWM_CMPDAT7_CMPD0_Msk !Ú P PWM_CMPDAT7_CMPD1_Pos Ú P PWM_CMPDAT7_CMPD1_Msk Ú P PWM_CMPDAT7_CMPD2_Pos Ú P PWM_CMPDAT7_CMPD2_Msk Ú P PWM_CMPDAT7_CMPD3_Pos Ú P PWM_CMPDAT7_CMPD3_Msk Ú P PWM_CMPDAT7_CMPD4_Pos Ú P PWM_CMPDAT7_CMPD4_Msk Ú P PWM_CMPDAT7_CMPD5_Pos Ú P PWM_CMPDAT7_CMPD5_Msk Ú P PWM_CMPDAT7_CMPD6_Pos Ú P PWM_CMPDAT7_CMPD6_Msk Ú P PWM_CMPDAT7_CMPD7_Pos Ú P PWM_CMPDAT7_CMPD7_Msk Ú P PWM_CTL2_BRKIEN_Pos Ú P PWM_CTL2_BRKIEN_Msk Ú P PWM_CTL2_PINTTYPE_Pos ÌÚ P PWM_CTL2_PINTTYPE_Msk ÓÚ P PWM_CTL2_DTCNT01_Pos mÚ P PWM_CTL2_DTCNT01_Msk tÚ P PWM_CTL2_DTCNT23_Pos iÚ P PWM_CTL2_DTCNT23_Msk pÚ P PWM_CTL2_DTCNT45_Pos eÚ P PWM_CTL2_DTCNT45_Msk lÚ P PWM_CTL2_DTCNT67_Pos aÚ P PWM_CTL2_DTCNT67_Msk hÚ P PWM_CTL2_CNTCLR_Pos Ú P PWM_CTL2_CNTCLR_Msk Ú P PWM_CTL2_MODE_Pos ,Ú P PWM_CTL2_MODE_Msk 3Ú P PWM_CTL2_GROUPEN_Pos +Ú P PWM_CTL2_GROUPEN_Msk 2Ú P PWM_CTL2_CNTTYPE_Pos $Ú P PWM_CTL2_CNTTYPE_Msk +Ú P PWM_FLAG_ZF0_Pos ~Ú P PWM_FLAG_ZF0_Msk
Ú P PWM_FLAG_ZF1_Pos }Ú P PWM_FLAG_ZF1_Msk Ú P PWM_FLAG_ZF2_Pos |Ú P PWM_FLAG_ZF2_Msk Ú P PWM_FLAG_ZF3_Pos {Ú P PWM_FLAG_ZF3_Msk Ú P PWM_FLAG_ZF4_Pos zÚ P PWM_FLAG_ZF4_Msk Ú P PWM_FLAG_ZF5_Pos yÚ P PWM_FLAG_ZF5_Msk Ú P PWM_FLAG_ZF6_Pos xÚ P PWM_FLAG_ZF6_Msk Ú P PWM_FLAG_ZF7_Pos wÚ P PWM_FLAG_ZF7_Msk ~Ú P PWM_FLAG_CMPDF0_Pos ®Ú P PWM_FLAG_CMPDF0_Msk µÚ P PWM_FLAG_CMPDF1_Pos Ú P PWM_FLAG_CMPDF1_Msk ´Ú P PWM_FLAG_CMPDF2_Pos ¬Ú P PWM_FLAG_CMPDF2_Msk ³Ú P PWM_FLAG_CMPDF3_Pos «Ú P PWM_FLAG_CMPDF3_Msk ²Ú P PWM_FLAG_CMPDF4_Pos ªÚ P PWM_FLAG_CMPDF4_Msk ±Ú P PWM_FLAG_CMPDF5_Pos ©Ú P PWM_FLAG_CMPDF5_Msk °Ú P PWM_FLAG_CMPDF6_Pos ¨Ú P PWM_FLAG_CMPDF6_Msk ¯Ú P PWM_FLAG_CMPDF7_Pos §Ú P PWM_FLAG_CMPDF7_Msk ®Ú P PWM_FLAG_PF0_Pos Ú P PWM_FLAG_PF0_Msk Ú P PWM_FLAG_PF1_Pos Ú P PWM_FLAG_PF1_Msk Ú P PWM_FLAG_PF2_Pos Ú P PWM_FLAG_PF2_Msk Ú P PWM_FLAG_PF3_Pos
Ú P PWM_FLAG_PF3_Msk Ú P PWM_FLAG_PF4_Pos Ú P PWM_FLAG_PF4_Msk Ú P PWM_FLAG_PF5_Pos Ú P PWM_FLAG_PF5_Msk Ú P PWM_FLAG_PF6_Pos Ú P PWM_FLAG_PF6_Msk Ú P PWM_FLAG_PF7_Pos Ú P PWM_FLAG_PF7_Msk Ú P PWM_FLAG_CMPUF0_Pos Ú P PWM_FLAG_CMPUF0_Msk ¤Ú P PWM_FLAG_CMPUF1_Pos Ú P PWM_FLAG_CMPUF1_Msk £Ú P PWM_FLAG_CMPUF2_Pos Ú P PWM_FLAG_CMPUF2_Msk ¢Ú P PWM_FLAG_CMPUF3_Pos Ú P PWM_FLAG_CMPUF3_Msk ¡Ú P PWM_FLAG_CMPUF4_Pos Ú P PWM_FLAG_CMPUF4_Msk Ú P PWM_FLAG_CMPUF5_Pos Ú P PWM_FLAG_CMPUF5_Msk Ú P PWM_FLAG_CMPUF6_Pos Ú P PWM_FLAG_CMPUF6_Msk Ú P PWM_FLAG_CMPUF7_Pos Ú P PWM_FLAG_CMPUF7_Msk Ú P PWM_INTEN_ZIEN0_Pos ~Ú P PWM_INTEN_ZIEN0_Msk
Ú P PWM_INTEN_ZIEN1_Pos }Ú P PWM_INTEN_ZIEN1_Msk Ú P PWM_INTEN_ZIEN2_Pos |Ú P PWM_INTEN_ZIEN2_Msk Ú P PWM_INTEN_ZIEN3_Pos {Ú P PWM_INTEN_ZIEN3_Msk Ú P PWM_INTEN_ZIEN4_Pos zÚ P PWM_INTEN_ZIEN4_Msk Ú P PWM_INTEN_ZIEN5_Pos yÚ P PWM_INTEN_ZIEN5_Msk Ú P PWM_INTEN_ZIEN6_Pos xÚ P PWM_INTEN_ZIEN6_Msk Ú P PWM_INTEN_ZIEN7_Pos wÚ P PWM_INTEN_ZIEN7_Msk ~Ú P PWM_INTEN_CMPDIEN0_Pos ®Ú P PWM_INTEN_CMPDIEN0_Msk µÚ P PWM_INTEN_CMPDIEN1_Pos Ú P PWM_INTEN_CMPDIEN1_Msk ´Ú P PWM_INTEN_CMPDIEN2_Pos ¬Ú P PWM_INTEN_CMPDIEN2_Msk ³Ú P PWM_INTEN_CMPDIEN3_Pos «Ú P PWM_INTEN_CMPDIEN3_Msk ²Ú P PWM_INTEN_CMPDIEN4_Pos ªÚ P PWM_INTEN_CMPDIEN4_Msk ±Ú P PWM_INTEN_CMPDIEN5_Pos ©Ú P PWM_INTEN_CMPDIEN5_Msk °Ú P PWM_INTEN_CMPDIEN6_Pos ¨Ú P PWM_INTEN_CMPDIEN6_Msk ¯Ú P PWM_INTEN_CMPDIEN7_Pos §Ú P PWM_INTEN_CMPDIEN7_Msk ®Ú P PWM_INTEN_PIEN0_Pos Ú P PWM_INTEN_PIEN0_Msk Ú P PWM_INTEN_PIEN1_Pos Ú P PWM_INTEN_PIEN1_Msk Ú P PWM_INTEN_PIEN2_Pos Ú P PWM_INTEN_PIEN2_Msk Ú P PWM_INTEN_PIEN3_Pos
Ú P PWM_INTEN_PIEN3_Msk Ú P PWM_INTEN_PIEN4_Pos Ú P PWM_INTEN_PIEN4_Msk Ú P PWM_INTEN_PIEN5_Pos Ú P PWM_INTEN_PIEN5_Msk Ú P PWM_INTEN_PIEN6_Pos Ú P PWM_INTEN_PIEN6_Msk Ú P PWM_INTEN_PIEN7_Pos Ú P PWM_INTEN_PIEN7_Msk Ú P PWM_INTEN_CMPUIEN0_Pos Ú P PWM_INTEN_CMPUIEN0_Msk ¤Ú P PWM_INTEN_CMPUIEN1_Pos Ú P PWM_INTEN_CMPUIEN1_Msk £Ú P PWM_INTEN_CMPUIEN2_Pos Ú P PWM_INTEN_CMPUIEN2_Msk ¢Ú P PWM_INTEN_CMPUIEN3_Pos Ú P PWM_INTEN_CMPUIEN3_Msk ¡Ú P PWM_INTEN_CMPUIEN4_Pos Ú P PWM_INTEN_CMPUIEN4_Msk Ú P PWM_INTEN_CMPUIEN5_Pos Ú P PWM_INTEN_CMPUIEN5_Msk Ú P PWM_INTEN_CMPUIEN6_Pos Ú P PWM_INTEN_CMPUIEN6_Msk Ú P PWM_INTEN_CMPUIEN7_Pos Ú P PWM_INTEN_CMPUIEN7_Msk Ú P PWM_INTSTS_ZIF0_Pos dÚ P PWM_INTSTS_ZIF0_Msk kÚ P PWM_INTSTS_ZIF1_Pos cÚ P PWM_INTSTS_ZIF1_Msk jÚ P PWM_INTSTS_ZIF2_Pos bÚ P PWM_INTSTS_ZIF2_Msk iÚ P PWM_INTSTS_ZIF3_Pos aÚ P PWM_INTSTS_ZIF3_Msk hÚ P PWM_INTSTS_ZIF4_Pos `Ú P PWM_INTSTS_ZIF4_Msk gÚ P PWM_INTSTS_ZIF5_Pos _Ú P PWM_INTSTS_ZIF5_Msk fÚ P PWM_INTSTS_ZIF6_Pos ^Ú P PWM_INTSTS_ZIF6_Msk eÚ P PWM_INTSTS_ZIF7_Pos ]Ú P PWM_INTSTS_ZIF7_Msk dÚ P PWM_INTSTS_CMPDIF0_Pos Ú P PWM_INTSTS_CMPDIF0_Msk Ú P PWM_INTSTS_CMPDIF1_Pos Ú P PWM_INTSTS_CMPDIF1_Msk Ú P PWM_INTSTS_CMPDIF2_Pos Ú P PWM_INTSTS_CMPDIF2_Msk Ú P PWM_INTSTS_CMPDIF3_Pos Ú P PWM_INTSTS_CMPDIF3_Msk Ú P PWM_INTSTS_CMPDIF4_Pos Ú P PWM_INTSTS_CMPDIF4_Msk Ú P PWM_INTSTS_CMPDIF5_Pos Ú P PWM_INTSTS_CMPDIF5_Msk Ú P PWM_INTSTS_CMPDIF6_Pos Ú P PWM_INTSTS_CMPDIF6_Msk Ú P PWM_INTSTS_CMPDIF7_Pos Ú P PWM_INTSTS_CMPDIF7_Msk Ú P PWM_INTSTS_PIF0_Pos nÚ P PWM_INTSTS_PIF0_Msk uÚ P PWM_INTSTS_PIF1_Pos mÚ P PWM_INTSTS_PIF1_Msk tÚ P PWM_INTSTS_PIF2_Pos lÚ P PWM_INTSTS_PIF2_Msk sÚ P PWM_INTSTS_PIF3_Pos kÚ P PWM_INTSTS_PIF3_Msk rÚ P PWM_INTSTS_PIF4_Pos jÚ P PWM_INTSTS_PIF4_Msk qÚ P PWM_INTSTS_PIF5_Pos iÚ P PWM_INTSTS_PIF5_Msk pÚ P PWM_INTSTS_PIF6_Pos hÚ P PWM_INTSTS_PIF6_Msk oÚ P PWM_INTSTS_PIF7_Pos gÚ P PWM_INTSTS_PIF7_Msk nÚ P PWM_INTSTS_CMPUIF0_Pos Ú P PWM_INTSTS_CMPUIF0_Msk Ú P PWM_INTSTS_CMPUIF1_Pos Ú P PWM_INTSTS_CMPUIF1_Msk Ú P PWM_INTSTS_CMPUIF2_Pos Ú P PWM_INTSTS_CMPUIF2_Msk Ú P PWM_INTSTS_CMPUIF3_Pos Ú P PWM_INTSTS_CMPUIF3_Msk Ú P PWM_INTSTS_CMPUIF4_Pos Ú P PWM_INTSTS_CMPUIF4_Msk Ú P PWM_INTSTS_CMPUIF5_Pos ~Ú P PWM_INTSTS_CMPUIF5_Msk
Ú P PWM_INTSTS_CMPUIF6_Pos }Ú P PWM_INTSTS_CMPUIF6_Msk Ú P PWM_INTSTS_CMPUIF7_Pos |Ú P PWM_INTSTS_CMPUIF7_Msk Ú P PWM_POEN_POEN0_Pos ÐÚ P PWM_POEN_POEN0_Msk ×Ú P PWM_POEN_POEN1_Pos ÏÚ P PWM_POEN_POEN1_Msk ÖÚ P PWM_POEN_POEN2_Pos ÎÚ P PWM_POEN_POEN2_Msk ÕÚ P PWM_POEN_POEN3_Pos ÍÚ P PWM_POEN_POEN3_Msk ÔÚ P PWM_POEN_POEN4_Pos ÌÚ P PWM_POEN_POEN4_Msk ÓÚ P PWM_POEN_POEN5_Pos ËÚ P PWM_POEN_POEN5_Msk ÒÚ P PWM_POEN_POEN6_Pos ÊÚ P PWM_POEN_POEN6_Msk ÑÚ P PWM_POEN_POEN7_Pos ÉÚ P PWM_POEN_POEN7_Msk ÐÚ P PWM_BRKCTL_BRK0EN_Pos úÚ P PWM_BRKCTL_BRK0EN_Msk Ú P PWM_BRKCTL_BRK1EN_Pos ùÚ P PWM_BRKCTL_BRK1EN_Msk Ú P PWM_BRKCTL_BRK0SEL_Pos §Ú P PWM_BRKCTL_BRK0SEL_Msk ®Ú P PWM_BRKCTL_BRK1SEL_Pos ¦Ú P PWM_BRKCTL_BRK1SEL_Msk Ú P PWM_BRKCTL_BRKSTS_Pos ÃÚ P PWM_BRKCTL_BRKSTS_Msk ÊÚ P PWM_BRKCTL_BRKACT_Pos åÚ P PWM_BRKCTL_BRKACT_Msk ìÚ P PWM_BRKCTL_SWBRK_Pos Ú P PWM_BRKCTL_SWBRK_Msk Ú P PWM_BRKCTL_BRKIF0_Pos þÚ P PWM_BRKCTL_BRKIF0_Msk Ú P PWM_BRKCTL_BRKIF1_Pos ýÚ P PWM_BRKCTL_BRKIF1_Msk Ú P PWM_BRKCTL_BRKF0_Pos IÚ P PWM_BRKCTL_BRKF0_Msk PÚ P PWM_BRKCTL_BRKF1_Pos HÚ P PWM_BRKCTL_BRKF1_Msk OÚ P PWM_BRKCTL_BKOD0_Pos NÚ P PWM_BRKCTL_BKOD0_Msk UÚ P PWM_BRKCTL_BKOD1_Pos MÚ P PWM_BRKCTL_BKOD1_Msk TÚ P PWM_BRKCTL_BKOD2_Pos LÚ P PWM_BRKCTL_BKOD2_Msk SÚ P PWM_BRKCTL_BKOD3_Pos KÚ P PWM_BRKCTL_BKOD3_Msk RÚ P PWM_BRKCTL_BKOD4_Pos JÚ P PWM_BRKCTL_BKOD4_Msk QÚ P PWM_BRKCTL_BKOD5_Pos IÚ P PWM_BRKCTL_BKOD5_Msk PÚ P PWM_BRKCTL_D6BKOD_Pos Ú P PWM_BRKCTL_D6BKOD_Msk Ú P PWM_BRKCTL_D7BKOD_Pos Ú P PWM_BRKCTL_D7BKOD_Msk Ú P PWM_DTCTL_DTI01_Pos ¥Ú P PWM_DTCTL_DTI01_Msk ¬Ú P PWM_DTCTL_DTI23_Pos ¡Ú P PWM_DTCTL_DTI23_Msk ¨Ú P PWM_DTCTL_DTI45_Pos Ú P PWM_DTCTL_DTI45_Msk ¤Ú P PWM_DTCTL_DTI67_Pos Ú P PWM_DTCTL_DTI67_Msk Ú" P PWM_ADCTCTL0_CUTRGEN0_Pos ßÚ" P PWM_ADCTCTL0_CUTRGEN0_Msk æÚ" P PWM_ADCTCTL0_CPTRGEN0_Pos äÚ" P PWM_ADCTCTL0_CPTRGEN0_Msk ëÚ" P PWM_ADCTCTL0_CDTRGEN0_Pos ðÚ" P PWM_ADCTCTL0_CDTRGEN0_Msk ÷Ú" P PWM_ADCTCTL0_ZPTRGEN0_Pos ÍÚ" P PWM_ADCTCTL0_ZPTRGEN0_Msk ÔÚ" P PWM_ADCTCTL0_CUTRGEN1_Pos ÞÚ" P PWM_ADCTCTL0_CUTRGEN1_Msk åÚ" P PWM_ADCTCTL0_CPTRGEN1_Pos ãÚ" P PWM_ADCTCTL0_CPTRGEN1_Msk êÚ" P PWM_ADCTCTL0_CDTRGEN1_Pos ïÚ" P PWM_ADCTCTL0_CDTRGEN1_Msk öÚ" P PWM_ADCTCTL0_ZPTRGEN1_Pos ÌÚ" P PWM_ADCTCTL0_ZPTRGEN1_Msk ÓÚ" P PWM_ADCTCTL0_CUTRGEN2_Pos ÝÚ" P PWM_ADCTCTL0_CUTRGEN2_Msk äÚ" P PWM_ADCTCTL0_CPTRGEN2_Pos âÚ" P PWM_ADCTCTL0_CPTRGEN2_Msk éÚ" P PWM_ADCTCTL0_CDTRGEN2_Pos îÚ" P PWM_ADCTCTL0_CDTRGEN2_Msk õÚ" P PWM_ADCTCTL0_ZPTRGEN2_Pos ËÚ" P PWM_ADCTCTL0_ZPTRGEN2_Msk ÒÚ" P PWM_ADCTCTL0_CUTRGEN3_Pos ÜÚ" P PWM_ADCTCTL0_CUTRGEN3_Msk ãÚ" P PWM_ADCTCTL0_CPTRGEN3_Pos áÚ" P PWM_ADCTCTL0_CPTRGEN3_Msk èÚ" P PWM_ADCTCTL0_CDTRGEN3_Pos íÚ" P PWM_ADCTCTL0_CDTRGEN3_Msk ôÚ" P PWM_ADCTCTL0_ZPTRGEN3_Pos ÊÚ" P PWM_ADCTCTL0_ZPTRGEN3_Msk ÑÚ" P PWM_ADCTCTL1_CUTRGEN4_Pos ÚÚ" P PWM_ADCTCTL1_CUTRGEN4_Msk áÚ" P PWM_ADCTCTL1_CPTRGEN4_Pos ßÚ" P PWM_ADCTCTL1_CPTRGEN4_Msk æÚ" P PWM_ADCTCTL1_CDTRGEN4_Pos ëÚ" P PWM_ADCTCTL1_CDTRGEN4_Msk òÚ" P PWM_ADCTCTL1_ZPTRGEN4_Pos ÈÚ" P PWM_ADCTCTL1_ZPTRGEN4_Msk ÏÚ" P PWM_ADCTCTL1_CUTRGEN5_Pos ÙÚ" P PWM_ADCTCTL1_CUTRGEN5_Msk àÚ" P PWM_ADCTCTL1_CPTRGEN5_Pos ÞÚ" P PWM_ADCTCTL1_CPTRGEN5_Msk åÚ" P PWM_ADCTCTL1_CDTRGEN5_Pos êÚ" P PWM_ADCTCTL1_CDTRGEN5_Msk ñÚ" P PWM_ADCTCTL1_ZPTRGEN5_Pos ÇÚ" P PWM_ADCTCTL1_ZPTRGEN5_Msk ÎÚ" P PWM_ADCTCTL1_CUTRGEN6_Pos ØÚ" P PWM_ADCTCTL1_CUTRGEN6_Msk ßÚ" P PWM_ADCTCTL1_CPTRGEN6_Pos ÝÚ" P PWM_ADCTCTL1_CPTRGEN6_Msk äÚ" P PWM_ADCTCTL1_CDTRGEN6_Pos éÚ" P PWM_ADCTCTL1_CDTRGEN6_Msk ðÚ" P PWM_ADCTCTL1_ZPTRGEN6_Pos ÆÚ" P PWM_ADCTCTL1_ZPTRGEN6_Msk ÍÚ" P PWM_ADCTCTL1_CUTRGEN7_Pos ×Ú" P PWM_ADCTCTL1_CUTRGEN7_Msk ÞÚ" P PWM_ADCTCTL1_CPTRGEN7_Pos ÜÚ" P PWM_ADCTCTL1_CPTRGEN7_Msk ãÚ" P PWM_ADCTCTL1_CDTRGEN7_Pos èÚ" P PWM_ADCTCTL1_CDTRGEN7_Msk ïÚ" P PWM_ADCTCTL1_ZPTRGEN7_Pos ÅÚ" P PWM_ADCTCTL1_ZPTRGEN7_Msk ÌÚ! P PWM_ADCTSTS0_CUTRGF0_Pos Ú! P PWM_ADCTSTS0_CUTRGF0_Msk Ú! P PWM_ADCTSTS0_CPTRGF0_Pos Ú! P PWM_ADCTSTS0_CPTRGF0_Msk #Ú! P PWM_ADCTSTS0_CDTRGF0_Pos (Ú! P PWM_ADCTSTS0_CDTRGF0_Msk /Ú! P PWM_ADCTSTS0_ZPTRGF0_Pos Ú! P PWM_ADCTSTS0_ZPTRGF0_Msk Ú! P PWM_ADCTSTS0_CUTRGF1_Pos Ú! P PWM_ADCTSTS0_CUTRGF1_Msk Ú! P PWM_ADCTSTS0_CPTRGF1_Pos Ú! P PWM_ADCTSTS0_CPTRGF1_Msk "Ú! P PWM_ADCTSTS0_CDTRGF1_Pos 'Ú! P PWM_ADCTSTS0_CDTRGF1_Msk .Ú! P PWM_ADCTSTS0_ZPTRGF1_Pos Ú! P PWM_ADCTSTS0_ZPTRGF1_Msk Ú! P PWM_ADCTSTS0_CUTRGF2_Pos Ú! P PWM_ADCTSTS0_CUTRGF2_Msk Ú! P PWM_ADCTSTS0_CPTRGF2_Pos Ú! P PWM_ADCTSTS0_CPTRGF2_Msk !Ú! P PWM_ADCTSTS0_CDTRGF2_Pos &Ú! P PWM_ADCTSTS0_CDTRGF2_Msk -Ú! P PWM_ADCTSTS0_ZPTRGF2_Pos Ú! P PWM_ADCTSTS0_ZPTRGF2_Msk
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Ú! P PWM_ADCTSTS0_CUTRGF3_Pos Ú! P PWM_ADCTSTS0_CUTRGF3_Msk Ú! P PWM_ADCTSTS0_CPTRGF3_Pos Ú! P PWM_ADCTSTS0_CPTRGF3_Msk Ú! P PWM_ADCTSTS0_CDTRGF3_Pos %Ú! P PWM_ADCTSTS0_CDTRGF3_Msk ,Ú! P PWM_ADCTSTS0_ZPTRGF3_Pos Ú! P PWM_ADCTSTS0_ZPTRGF3_Msk Ú! P PWM_ADCTSTS1_CUTRGF4_Pos Ú! P PWM_ADCTSTS1_CUTRGF4_Msk Ú! P PWM_ADCTSTS1_CPTRGF4_Pos Ú! P PWM_ADCTSTS1_CPTRGF4_Msk Ú! P PWM_ADCTSTS1_CDTRGF4_Pos #Ú! P PWM_ADCTSTS1_CDTRGF4_Msk *Ú! P PWM_ADCTSTS1_ZPTRGF4_Pos Ú! P PWM_ADCTSTS1_ZPTRGF4_Msk Ú! P PWM_ADCTSTS1_CUTRGF5_Pos Ú! P PWM_ADCTSTS1_CUTRGF5_Msk Ú! P PWM_ADCTSTS1_CPTRGF5_Pos Ú! P PWM_ADCTSTS1_CPTRGF5_Msk Ú! P PWM_ADCTSTS1_CDTRGF5_Pos "Ú! P PWM_ADCTSTS1_CDTRGF5_Msk )Ú! P PWM_ADCTSTS1_ZPTRGF5_Pos ÿÚ! P PWM_ADCTSTS1_ZPTRGF5_Msk Ú! P PWM_ADCTSTS1_CUTRGF6_Pos Ú! P PWM_ADCTSTS1_CUTRGF6_Msk Ú! P PWM_ADCTSTS1_CPTRGF6_Pos Ú! P PWM_ADCTSTS1_CPTRGF6_Msk Ú! P PWM_ADCTSTS1_CDTRGF6_Pos !Ú! P PWM_ADCTSTS1_CDTRGF6_Msk (Ú! P PWM_ADCTSTS1_ZPTRGF6_Pos þÚ! P PWM_ADCTSTS1_ZPTRGF6_Msk Ú! P PWM_ADCTSTS1_CUTRGF7_Pos Ú! P PWM_ADCTSTS1_CUTRGF7_Msk Ú! P PWM_ADCTSTS1_CPTRGF7_Pos Ú! P PWM_ADCTSTS1_CPTRGF7_Msk Ú! P PWM_ADCTSTS1_CDTRGF7_Pos Ú! P PWM_ADCTSTS1_CDTRGF7_Msk 'Ú! P PWM_ADCTSTS1_ZPTRGF7_Pos ýÚ! P PWM_ADCTSTS1_ZPTRGF7_Msk Ú P PWM_PCACTL_PCAEN_Pos BÚ P PWM_PCACTL_PCAEN_Msk IÚ 8
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<unnamed> QÚ
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" ð X_FL_CTL )Ú " ð
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X_FL_TRIG ÛÚ " ð X_FL_CONFIG WÚ <" ðX_FL_WD ?Ú
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" ð X_FL_X_MODE *Ú " ð X_FL_X2_CMD PÚ " ð X_FL_X4_CMD NÚ " ð X_FL_DP_CMD FÚ " ð X_FL_RDP_CMD òÚ
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" ðX_FL_REMAP_ADDR Ú
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" ð X_FL_DP_CTL 0Ú
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" ð X_FL_IRQ_CTL ÖÚ
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" ðX_FL_SUS_RESU_CMD .Ú FLCTL_T ËÚ 8
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<unnamed> QÚ <" ÿ X_FL_BUFFER Ú FLCTL_W_BUFF_T
Ú" P FLCTL_CTL_BYTES_NUM_R_Pos kÚ" P FLCTL_CTL_BYTES_NUM_R_Msk rÚ" P FLCTL_CTL_BYTES_NUM_W_Pos fÚ" P FLCTL_CTL_BYTES_NUM_W_Msk mÚ P FLCTL_TRIG_TRG_Pos ÀÚ P FLCTL_TRIG_TRG_Msk ÇÚ# P FLCTL_CONFIG_FLASH_CAP_Pos |Ú# P FLCTL_CONFIG_FLASH_CAP_Msk Ú' P FLCTL_CONFIG_TX_ADDR_TRANS_Pos Ú' P FLCTL_CONFIG_TX_ADDR_TRANS_Msk Ú! P FLCTL_CONFIG_INFO_EN_Pos Ú! P FLCTL_CONFIG_INFO_EN_Msk
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Ú# P FLCTL_CONFIG_PP_ACTIVE_Pos bÚ# P FLCTL_CONFIG_PP_ACTIVE_Msk iÚ P FLCTL_W_DATA_Pos vÚ P FLCTL_W_DATA_Msk }Ú% P FLCTL_X_MODE_TIMEOUT_CNT_Pos Ú% P FLCTL_X_MODE_TIMEOUT_CNT_Msk Ú# P FLCTL_X_MODE_RESUME_EN_Pos 4Ú# P FLCTL_X_MODE_RESUME_EN_Msk ;Ú% P FLCTL_X_MODE_SUS_SUCCESS_Pos Ú% P FLCTL_X_MODE_SUS_SUCCESS_Msk Ú! P FLCTL_X_MODE_CLK_DLY_Pos ÙÚ! P FLCTL_X_MODE_CLK_DLY_Msk àÚ P FLCTL_X_MODE_RX_NEG_Pos Ú P FLCTL_X_MODE_RX_NEG_Msk !Ú" P FLCTL_X_MODE_CRC32_EN_Pos ÊÚ" P FLCTL_X_MODE_CRC32_EN_Msk ÑÚ& P FLCTL_X_MODE_ENHANCE_MODE_Pos {Ú& P FLCTL_X_MODE_ENHANCE_MODE_Msk Ú& P FLCTL_X_MODE_LONG_TIME_OP_Pos 5Ú& P FLCTL_X_MODE_LONG_TIME_OP_Msk <Ú' P FLCTL_X_MODE_EN_BURST_WRAP_Pos ÔÚ' P FLCTL_X_MODE_EN_BURST_WRAP_Msk ÛÚ' P FLCTL_X_MODE_CS_IDLE_CYCLE_Pos Ú' P FLCTL_X_MODE_CS_IDLE_CYCLE_Msk Ú P FLCTL_X_MODE_X_MODE_Pos !Ú P FLCTL_X_MODE_X_MODE_Msk (Ú P FLCTL_X2_CMD_Pos Ú P FLCTL_X2_CMD_Msk Ú P FLCTL_X4_CMD_Pos Ú P FLCTL_X4_CMD_Msk Ú P FLCTL_DP_CMD_Pos Ú P FLCTL_DP_CMD_Msk Ú P FLCTL_RDP_CMD_Pos +Ú P FLCTL_RDP_CMD_Msk 2Ú P FLCTL_REMAP_ADDR_Pos OÚ P FLCTL_REMAP_ADDR_Msk VÚ$ P FLCTL_DP_CTL_RDP_WT_CNT_Pos ÇÚ$ P FLCTL_DP_CTL_RDP_WT_CNT_Msk ÎÚ# P FLCTL_DP_CTL_DP_WT_CNT_Pos Ú# P FLCTL_DP_CTL_DP_WT_CNT_Msk "Ú P FLCTL_DP_CTL_DP_EN_Pos Ú P FLCTL_DP_CTL_DP_EN_Msk Ú" P FLCTL_PROGRAM_SUS_CMD_Pos Ú" P FLCTL_PROGRAM_SUS_CMD_Msk Ú% P FLCTL_PROGRAM_RESUME_CMD_Pos ³Ú% P FLCTL_PROGRAM_RESUME_CMD_Msk ºÚ P FLCTL_ERASE_SUS_CMD_Pos ;Ú P FLCTL_ERASE_SUS_CMD_Msk BÚ# P FLCTL_ERASE_RESUME_CMD_Pos _Ú# P FLCTL_ERASE_RESUME_CMD_Msk fÚ 8
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<unnamed> QÚ
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" À X_CACHE_EN âÚ
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" ÀX_RESVR Ú
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" À X_CACHE_INI Ú CR_T ±Ú 8
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<unnamed> QÚ
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" ÅCR0 #Ú
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" ÅCR1 "Ú
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" ÅDR TÚ
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" ÅSR EÚ
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" ÅCPSR ®Ú
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" ÅIMSC ºÚ
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" ÅRIS úÚ
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" ÅMIS ÿÚ
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" ÅICR
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Ú
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" ÅDMACR }Ú SPI_T XÚ P SPI_CR0_SCR_Pos ÅÚ P SPI_CR0_SCR_Msk ÌÚ P SPI_CR0_SPH_Pos ÂÚ P SPI_CR0_SPH_Msk ÉÚ P SPI_CR0_SPO_Pos »Ú P SPI_CR0_SPO_Msk ÂÚ P SPI_CR0_FRF_Pos ÏÚ P SPI_CR0_FRF_Msk ÖÚ P SPI_CR0_DSS_Pos ÃÚ P SPI_CR0_DSS_Msk ÊÚ! P SPI_CR1_SPI_MODE_SEL_Pos çÚ! P SPI_CR1_SPI_MODE_SEL_Msk îÚ P SPI_CR1_CMD_DAT_EN_Pos Ú P SPI_CR1_CMD_DAT_EN_Msk §Ú! P SPI_CR1_CMD_DAT_CTRL_Pos úÚ! P SPI_CR1_CMD_DAT_CTRL_Msk Ú P SPI_CR1_WR_CTRL_Pos gÚ P SPI_CR1_WR_CTRL_Msk nÚ P SPI_CR1_RX_LSB_EN_Pos ÄÚ P SPI_CR1_RX_LSB_EN_Msk ËÚ P SPI_CR1_TX_LSB_EN_Pos ÂÚ P SPI_CR1_TX_LSB_EN_Msk ÉÚ P SPI_CR1_SOD_Pos ÆÚ P SPI_CR1_SOD_Msk ÍÚ P SPI_CR1_MS_Pos Ú P SPI_CR1_MS_Msk Ú P SPI_CR1_SSE_Pos ÁÚ P SPI_CR1_SSE_Msk ÈÚ P SPI_CR1_LBM_Pos ÑÚ P SPI_CR1_LBM_Msk ØÚ P SPI_DR_Pos EÚ P SPI_DR_Msk LÚ P SPI_SR_BUSY_Pos Ú P SPI_SR_BUSY_Msk Ú P SPI_SR_RFF_Pos ñÚ P SPI_SR_RFF_Msk øÚ P SPI_SR_RFNE_Pos ¢Ú P SPI_SR_RFNE_Msk ©Ú P SPI_SR_TFNF_Pos Ú P SPI_SR_TFNF_Msk ¦Ú P SPI_SR_TFE_Pos ðÚ P SPI_SR_TFE_Msk ÷Ú P SPI_CPSR_DIV_Pos UÚ P SPI_CPSR_DIV_Msk \Ú P SPI_IMSC_TXIM_Pos Ú P SPI_IMSC_TXIM_Msk Ú P SPI_IMSC_RXIM_Pos Ú P SPI_IMSC_RXIM_Msk Ú P SPI_IMSC_RTIM_Pos Ú P SPI_IMSC_RTIM_Msk Ú P SPI_RIS_TXIS_Pos :Ú P SPI_RIS_TXIS_Msk AÚ P SPI_RIS_RXIS_Pos <Ú P SPI_RIS_RXIS_Msk CÚ P SPI_RIS_RTIS_Pos @Ú P SPI_RIS_RTIS_Msk GÚ P SPI_RIS_RORIS_Pos ñÚ P SPI_RIS_RORIS_Msk øÚ P SPI_MIS_TXMIS_Pos ðÚ P SPI_MIS_TXMIS_Msk ÷Ú P SPI_MIS_RXMIS_Pos òÚ P SPI_MIS_RXMIS_Msk ùÚ P SPI_MIS_RTMIS_Pos öÚ P SPI_MIS_RTMIS_Msk ýÚ P SPI_MIS_RORMIS_Pos §Ú P SPI_MIS_RORMIS_Msk ®Ú P SPI_ICR_RTICR_Pos Ú P SPI_ICR_RTICR_Msk Ú P SPI_ICR_RORICR_Pos ½Ú P SPI_ICR_RORICR_Msk ÄÚ P SPI_DMACR_TDMAE_Pos Ú P SPI_DMACR_TDMAE_Msk Ú P SPI_DMACR_RDMAE_Pos Ú P SPI_DMACR_RDMAE_Msk ¡Ú 8
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<unnamed> QÚ
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" RBR_THR_DLL Ú
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" IER_DLH òÚ
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" IIR_FCR ëÚ
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" LCR 0Ú
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" MCR /Ú
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" LSR Ú
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" MSR Ú
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" SCR )Ú
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" LPDLL Ú
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" LPDLH Ú <" T
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RESERVED0 óÚ
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" USR Ú
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" TFL +Ú
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" RFL -Ú <"
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RESERVED1 *Ú
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" HTX Ú
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" DMASA §Ú <"
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RESERVED2 1Ú
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" DLF ;Ú
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" RAR ,Ú
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" TAR *Ú
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" LCR_EXT ØÚ UART_T Ú P UART_RBR_MSB9_Pos Ú P UART_RBR_MSB9_Msk $Ú P UART_RBR_DAT_Pos aÚ P UART_RBR_DAT_Msk hÚ P UART_THR_MSB9_Pos Ú P UART_THR_MSB9_Msk Ú P UART_THR_DAT_Pos YÚ P UART_THR_DAT_Msk `Ú P UART_DLH_Pos ¯Ú P UART_DLH_Msk ¶Ú P UART_DLL_Pos «Ú P UART_DLL_Msk ²Ú P UART_IER_EPTI_Pos Ú P UART_IER_EPTI_Msk Ú P UART_IER_EMSI_Pos Ú P UART_IER_EMSI_Msk Ú P UART_IER_ERLSI_Pos ½Ú P UART_IER_ERLSI_Msk ÄÚ P UART_IER_ETHREI_Pos yÚ P UART_IER_ETHREI_Msk Ú P UART_IER_ERDAI_Pos ×Ú P UART_IER_ERDAI_Msk ÞÚ P UART_IER_ALL_IRQ_Pos Ú P UART_IER_ALL_IRQ_Msk Ú P UART_IIR_FIFOSE_Pos zÚ P UART_IIR_FIFOSE_Msk Ú P UART_IIR_IID_Pos fÚ P UART_IIR_IID_Msk mÚ P UART_FCR_RT_Pos ¡Ú P UART_FCR_RT_Msk ¨Ú P UART_FCR_TET_Pos XÚ P UART_FCR_TET_Msk _Ú P UART_FCR_DMAM_Pos $Ú P UART_FCR_DMAM_Msk +Ú P UART_FCR_XFIFOR_Pos qÚ P UART_FCR_XFIFOR_Msk xÚ P UART_FCR_RFIFOR_Pos wÚ P UART_FCR_RFIFOR_Msk ~Ú P UART_FCR_FIFOE_Pos ØÚ P UART_FCR_FIFOE_Msk ßÚ P UART_LCR_DLAB_Pos *Ú P UART_LCR_DLAB_Msk 1Ú P UART_LCR_BC_Pos ¼Ú P UART_LCR_BC_Msk ÃÚ P UART_LCR_SP_Pos Ú P UART_LCR_SP_Msk ¥Ú P UART_LCR_EPS_Pos WÚ P UART_LCR_EPS_Msk ^Ú P UART_LCR_PEN_Pos \Ú P UART_LCR_PEN_Msk cÚ P UART_LCR_STOP_Pos ÷Ú P UART_LCR_STOP_Msk þÚ P UART_LCR_DLS_Pos \Ú P UART_LCR_DLS_Msk cÚ P UART_MCR_SIRE_Pos Ú P UART_MCR_SIRE_Msk Ú P UART_MCR_AFCE_Pos -Ú P UART_MCR_AFCE_Msk 4Ú P UART_MCR_LB_Pos ²Ú P UART_MCR_LB_Msk ¹Ú P UART_MCR_OUT2_Pos Ú P UART_MCR_OUT2_Msk Ú P UART_MCR_OUT1_Pos Ú P UART_MCR_OUT1_Msk Ú P UART_MCR_RTS_Pos EÚ P UART_MCR_RTS_Msk LÚ P UART_MCR_DTR_Pos TÚ P UART_MCR_DTR_Msk [Ú P UART_LSR_ADDR_RCVD_Pos zÚ P UART_LSR_ADDR_RCVD_Msk Ú P UART_LSR_RFE_Pos RÚ P UART_LSR_RFE_Msk YÚ P UART_LSR_TEMT_Pos óÚ P UART_LSR_TEMT_Msk úÚ P UART_LSR_THRE_Pos úÚ P UART_LSR_THRE_Msk Ú P UART_LSR_BI_Pos ¦Ú P UART_LSR_BI_Msk Ú P UART_LSR_FE_Pos ¦Ú P UART_LSR_FE_Msk Ú P UART_LSR_PE_Pos Ú P UART_LSR_PE_Msk £Ú P UART_LSR_OE_Pos Ú P UART_LSR_OE_Msk ¤Ú P UART_LSR_DR_Pos Ú P UART_LSR_DR_Msk ¢Ú! P UART_LSR_LINE_STATUS_Pos ´Ú! P UART_LSR_LINE_STATUS_Msk »Ú P UART_MSR_DCD_Pos cÚ P UART_MSR_DCD_Msk jÚ P UART_MSR_RI_Pos Ú P UART_MSR_RI_Msk Ú P UART_MSR_DSR_Pos EÚ P UART_MSR_DSR_Msk LÚ P UART_MSR_CTS_Pos DÚ P UART_MSR_CTS_Msk KÚ P UART_MSR_DDCD_Pos Ú P UART_MSR_DDCD_Msk $Ú P UART_MSR_TERI_Pos øÚ P UART_MSR_TERI_Msk ÿÚ P UART_MSR_DDSR_Pos ÿÚ P UART_MSR_DDSR_Msk Ú P UART_MSR_DCTS_Pos þÚ P UART_MSR_DCTS_Msk Ú" P UART_MSR_MODEM_STATUS_Pos gÚ" P UART_MSR_MODEM_STATUS_Msk nÚ P UART_SCR_Pos Ú P UART_SCR_Msk ¦Ú P UART_LPDLL_Pos Ú P UART_LPDLL_Msk Ú P UART_LPDLH_Pos Ú P UART_LPDLH_Msk Ú P UART_USR_RFF_Pos HÚ P UART_USR_RFF_Msk OÚ P UART_USR_RFNE_Pos ùÚ P UART_USR_RFNE_Msk Ú P UART_USR_TFE_Pos GÚ P UART_USR_TFE_Msk NÚ P UART_USR_TFNF_Pos öÚ P UART_USR_TFNF_Msk ýÚ P UART_TFL_Pos ¡Ú P UART_TFL_Msk ¨Ú P UART_RFL_Pos £Ú P UART_RFL_Msk ªÚ P UART_DMASA_Pos Ú P UART_DMASA_Msk $Ú P UART_DLF_Pos ±Ú P UART_DLF_Msk ¸Ú P UART_RAR_Pos ¢Ú P UART_RAR_Msk ©Ú P UART_TAR_Pos Ú P UART_TAR_Msk §Ú' P UART_LCR_EXT_TRANSMIT_MODE_Pos ÝÚ' P UART_LCR_EXT_TRANSMIT_MODE_Msk äÚ# P UART_LCR_EXT_SEND_ADDR_Pos 7Ú# P UART_LCR_EXT_SEND_ADDR_Msk >Ú$ P UART_LCR_EXT_ADDR_MATCH_Pos òÚ$ P UART_LCR_EXT_ADDR_MATCH_Msk ùÚ P UART_LCR_EXT_DLS_E_Pos \Ú P UART_LCR_EXT_DLS_E_Msk cÚ P UART_DR_OE Ú P UART_DR_BE Ú P UART_DR_PE Ú P UART_DR_FE Ú P UART_DR_DATA Ú P UART_RSCR_OE ëÚ P UART_RSCR_BE øÚ P UART_RSCR_PE êÚ P UART_RSCR_FE ôÚ P UART_RSCR_CLR_ERR LÚ P UART_STATUS_RI 6Ú P UART_STATUS_TXFE Ú P UART_STATUS_RXFF Ú P UART_STATUS_TXFF Ú P UART_STATUS_RXFE Ú P UART_STATUS_BUSY Ú P UART_STATUS_DCD Ú P UART_STATUS_DSR æÚ P UART_STATUS_CTS åÚ P UART_IRDA_LP_DIV ³Ú P UART_BRD_IBRD ¾Ú P UART_BRD_FBRD ÁÚ P UART_LC_CLEAR_MSK oÚ P UART_LC_SPS 6Ú P UART_LC_WLEN ôÚ P UART_LC_FEN SÚ P UART_LC_STP2 Ú P UART_LC_EPS DÚ P UART_LC_PEN IÚ P UART_LC_BRK MÚ P UART_CR_CLEAR_MSK iÚ P UART_CR_CTSEN ¥Ú P UART_CR_RTSEN Ú P UART_CR_OUT2 úÚ P UART_CR_OUT1 ûÚ P UART_CR_RTS -Ú P UART_CR_DTR <Ú P UART_CR_RXE 7Ú P UART_CR_TXE 5Ú P UART_CR_LBE SÚ P UART_CR_SIRLP Ú P UART_CR_SIREN ¡Ú P UART_CR_UARTEN QÚ P UART_INT_FIFO_RXIFLSEL ÎÚ P UART_INT_FIFO_TXIFLSEL ÌÚ P UART_INT_MSK_OEIM PÚ P UART_INT_MSK_BEIM ]Ú P UART_INT_MSK_PEIM OÚ P UART_INT_MSK_FEIM YÚ P UART_INT_MSK_RTIM >Ú P UART_INT_MSK_TXIM 8Ú P UART_INT_MSK_RXIM :Ú P UART_INT_MSK_DSRMIM ªÚ P UART_INT_MSK_DCDMIM ÈÚ P UART_INT_MSK_CTSMIM ©Ú P UART_INT_MSK_RIMIM úÚ P UART_RAW_INT_MSK_OEIM ÿÚ P UART_RAW_INT_MSK_BEIM Ú P UART_RAW_INT_MSK_PEIM þÚ P UART_RAW_INT_MSK_FEIM Ú P UART_RAW_INT_MSK_RTIM íÚ P UART_RAW_INT_MSK_TXIM çÚ P UART_RAW_INT_MSK_RXIM éÚ P UART_RAW_INT_MSK_DSRMIM YÚ P UART_RAW_INT_MSK_DCDMIM wÚ P UART_RAW_INT_MSK_CTSMIM XÚ P UART_RAW_INT_MSK_RIMIM ©Ú" P UART_MASKED_INT_STAT_OEIM ÛÚ" P UART_MASKED_INT_STAT_BEIM èÚ" P UART_MASKED_INT_STAT_PEIM ÚÚ" P UART_MASKED_INT_STAT_FEIM äÚ" P UART_MASKED_INT_STAT_RTIM ÉÚ" P UART_MASKED_INT_STAT_TXIM ÃÚ" P UART_MASKED_INT_STAT_RXIM ÅÚ$ P UART_MASKED_INT_STAT_DSRMIM 5Ú$ P UART_MASKED_INT_STAT_DCDMIM SÚ$ P UART_MASKED_INT_STAT_CTSMIM 4Ú# P UART_MASKED_INT_STAT_RIMIM
Ú P UART_CLR_INT_OEIM ZÚ P UART_CLR_INT_BEIM gÚ P UART_CLR_INT_PEIM YÚ P UART_CLR_INT_FEIM cÚ P UART_CLR_INT_RTIM HÚ P UART_CLR_INT_TXIM BÚ P UART_CLR_INT_RXIM DÚ P UART_CLR_INT_DSRMIM ´Ú P UART_CLR_INT_DCDMIM ÒÚ P UART_CLR_INT_CTSMIM ³Ú P UART_CLR_INT_RIMIM Ú P UART_DMA_CR_DMAONERR Ú P UART_DMA_CR_TXDMAE $Ú P UART_DMA_CR_RXDMAE &Ú 8
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<unnamed> QÚ 8
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<unnamed> QÚ
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" SAR_L yÚ
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" SAR_H }Ú
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" DAR_L Ú
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" DAR_H Ú <"
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RESERVED0 <Ú
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" CTL_L |Ú
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" CTL_H Ú <"
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RESERVED1 #Ú
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" CFG_L Ú
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" CFG_H Ú
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" SGR_L sÚ
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" SGR_H wÚ
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" DSR_L vÚ
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" DSR_H zÚ <" ÀCH Ú
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"
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RAW_TFR_L #Ú
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"
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RAW_TFR_H 'Ú
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" RAW_BLOCK_L Ú
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" RAW_BLOCK_H ¤Ú
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" RAW_SRCTRAN_L êÚ
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" RAW_SRCTRAN_H îÚ
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" RAW_DSTTRAN_L çÚ
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" RAW_DSTTRAN_H ëÚ
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"
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RAW_ERR_L &Ú
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"
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RAW_ERR_H *Ú
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" STATUS_TFR_L #Ú
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" STATUS_TFR_H 'Ú
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" STATUS_BLOCK_L Ú
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" STATUS_BLOCK_H ¤Ú
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" STATUS_SRCTRAN_L êÚ
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" STATUS_SRCTRAN_H îÚ
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" STATUS_DSTTRAN_L çÚ
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" STATUS_DSTTRAN_H ëÚ
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" STATUS_ERR_L &Ú
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" STATUS_ERR_H *Ú
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"
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MSK_TFR_L "Ú
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"
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MSK_TFR_H &Ú
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" MSK_BLOCK_L Ú
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" MSK_BLOCK_H £Ú
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" MSK_SRCTRAN_L éÚ
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" MSK_SRCTRAN_H íÚ
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" MSK_DSTTRAN_L æÚ
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" MSK_DSTTRAN_H êÚ
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"
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MSK_ERR_L %Ú
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"
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MSK_ERR_H )Ú
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" CLEAR_TFR_L ¢Ú
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" CLEAR_TFR_H ¦Ú
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" CLEAR_BLOCK_L Ú
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" CLEAR_BLOCK_H #Ú
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" CLEAR_SRCTRAN_L iÚ
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" CLEAR_SRCTRAN_H mÚ
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" CLEAR_DSTTRAN_L fÚ
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" CLEAR_DSTTRAN_H jÚ
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" CLEAR_ERR_L ¥Ú
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" CLEAR_ERR_H ©Ú
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" STATUS_INT_L $Ú
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" STATUS_INT_H (Ú <" 0
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RESERVED3 Ú
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" DMA_CFG_REG_L Ú
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" DMA_CFG_REG_H Ú
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" CH_EN_REG_L Ú
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" CH_EN_REG_H Ú DMA_T rÚ$ P DMAC_DMACFGREG_L_DMA_EN_Pos BÚ$ P DMAC_DMACFGREG_L_DMA_EN_Msk IÚ! P DMAC_CHENREG_L_CH_EN_Pos Ú! P DMAC_CHENREG_L_CH_EN_Msk Ú% P DMAC_CHENREG_L_CH_EN_ALL_Pos ÓÚ% P DMAC_CHENREG_L_CH_EN_ALL_Msk ÚÚ$ P DMAC_CHENREG_L_CH_EN_WE_Pos Ú$ P DMAC_CHENREG_L_CH_EN_WE_Msk Ú( P DMAC_CHENREG_L_CH_EN_WE_ALL_Pos ÒÚ( P DMAC_CHENREG_L_CH_EN_WE_ALL_Msk ÙÚ P DMAC_SAR_L_SAR_Pos ÌÚ P DMAC_SAR_L_SAR_Msk ÓÚ P DMAC_DAR_L_DAR_Pos êÚ P DMAC_DAR_L_DAR_Msk ñÚ P DMAC_CTL_L_INT_EN_Pos ÒÚ P DMAC_CTL_L_INT_EN_Msk ÙÚ$ P DMAC_CTL_L_DST_TR_WIDTH_Pos ÔÚ$ P DMAC_CTL_L_DST_TR_WIDTH_Msk ÛÚ$ P DMAC_CTL_L_SRC_TR_WIDTH_Pos ×Ú$ P DMAC_CTL_L_SRC_TR_WIDTH_Msk ÞÚ P DMAC_CTL_L_DINC_Pos Ú P DMAC_CTL_L_DINC_Msk Ú P DMAC_CTL_L_SINC_Pos Ú P DMAC_CTL_L_SINC_Msk Ú" P DMAC_CTL_L_DEST_MSIZE_Pos Ú" P DMAC_CTL_L_DEST_MSIZE_Msk Ú! P DMAC_CTL_L_SRC_MSIZE_Pos ÚÚ! P DMAC_CTL_L_SRC_MSIZE_Msk áÚ P DMAC_CTL_L_TT_FC_Pos !Ú P DMAC_CTL_L_TT_FC_Msk (Ú P DMAC_CTL_H_BLOCK_TS_Pos >Ú P DMAC_CTL_H_BLOCK_TS_Msk EÚ P DMAC_CTL_H_DONE_Pos Ú P DMAC_CTL_H_DONE_Msk Ú P DMAC_CFG_L_CH_PRIOR_Pos HÚ P DMAC_CFG_L_CH_PRIOR_Msk OÚ P DMAC_CFG_L_CH_SUSP_Pos Ú P DMAC_CFG_L_CH_SUSP_Msk Ú" P DMAC_CFG_L_FIFO_EMPTY_Pos ¨Ú" P DMAC_CFG_L_FIFO_EMPTY_Msk ¯Ú" P DMAC_CFG_L_HS_SEL_DST_Pos Ú" P DMAC_CFG_L_HS_SEL_DST_Msk Ú" P DMAC_CFG_L_HS_SEL_SRC_Pos Ú" P DMAC_CFG_L_HS_SEL_SRC_Msk Ú" P DMAC_CFG_L_DST_HS_POL_Pos Ú" P DMAC_CFG_L_DST_HS_POL_Msk Ú" P DMAC_CFG_L_SRC_HS_POL_Pos Ú" P DMAC_CFG_L_SRC_HS_POL_Msk Ú P DMAC_CFG_H_FCMODE_Pos Ú P DMAC_CFG_H_FCMODE_Msk Ú! P DMAC_CFG_H_FIFO_MODE_Pos Ú! P DMAC_CFG_H_FIFO_MODE_Msk Ú P DMAC_CFG_H_PROTCTL_Pos Ú P DMAC_CFG_H_PROTCTL_Msk £Ú P DMAC_CFG_H_SRC_PER_Pos Ú P DMAC_CFG_H_SRC_PER_Msk Ú P DMAC_CFG_H_DEST_PER_Pos LÚ P DMAC_CFG_H_DEST_PER_Msk SÚ" P DMAC_INT_RAW_STAT_CLR_Pos
Ú" P DMAC_INT_RAW_STAT_CLR_Msk Ú& P DMAC_INT_RAW_STAT_CLR_ALL_Pos EÚ& P DMAC_INT_RAW_STAT_CLR_ALL_Msk LÚ P DMAC_INT_MASK_L_Pos Ú P DMAC_INT_MASK_L_Msk Ú P DMAC_INT_MASK_L_ALL_Pos ?Ú P DMAC_INT_MASK_L_ALL_Msk FÚ P DMAC_INT_MASK_L_WE_Pos ~Ú P DMAC_INT_MASK_L_WE_Msk
Ú# P DMAC_INT_MASK_L_WE_ALL_Pos >Ú# P DMAC_INT_MASK_L_WE_ALL_Msk EÚ! P DMAC_STATUSINT_L_TFR_Pos ÑÚ! P DMAC_STATUSINT_L_TFR_Msk ØÚ# P DMAC_STATUSINT_L_BLOCK_Pos NÚ# P DMAC_STATUSINT_L_BLOCK_Msk UÚ% P DMAC_STATUSINT_L_SRCTRAN_Pos Ú% P DMAC_STATUSINT_L_SRCTRAN_Msk Ú% P DMAC_STATUSINT_L_DSTTRAN_Pos Ú% P DMAC_STATUSINT_L_DSTTRAN_Msk Ú! P DMAC_STATUSINT_L_ERR_Pos ÔÚ! P DMAC_STATUSINT_L_ERR_Msk ÛÚ 8
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<unnamed> QÚ
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" ¬CON Ú
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" ¬TAR Ú
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" ¬SAR Ú
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" ¬ HS_MADDR Ú
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" ¬DATACMD Ú
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" ¬ SS_SCL_HCNT zÚ
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" ¬ SS_SCL_LCNT vÚ
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" ¬ FS_SCL_HCNT Ú
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" ¬ FS_SCL_LCNT Ú
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" ¬ HS_SCL_HCNT
Ú
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" ¬ HS_SCL_LCNT Ú
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" ¬
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INTR_STAT Ú
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" ¬
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INTR_MASK )Ú
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" ¬RAW_INTR_STAT ÈÚ
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" ¬RX_TL PÚ
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" ¬TX_TL NÚ
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" ¬ CLR_INTR vÚ
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" ¬ CLR_RX_UND ¿Ú
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" ¬ CLR_RX_OVR ¯Ú
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" ¬ CLR_TX_OVR Ú
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" ¬ CLR_RD_REQ ÒÚ
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" ¬ CLR_TX_ABRT yÚ
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" ¬ CLR_RX_DONE ~Ú
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" ¬ CLR_ACTIVITY >Ú
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" ¬ CLR_STOP_DET )Ú
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" ¬CLR_START_DET ßÚ
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" ¬ CLR_GEN_CALL VÚ
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" ¬
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IC_ENABLE _Ú
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" ¬STATUS Ú
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" ¬TXFLR iÚ
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" ¬RXFLR kÚ
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" ¬ SDA_HOLD Ú
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" ¬ TX_ABRT_SRC rÚ
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" ¬SLV_DATA_NACK ÿÚ
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" ¬DMA_CR 1Ú
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" ¬ DMA_TDLR Ú
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" ¬ DMA_RDLR Ú
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" ¬
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SDA_SETUP )Ú
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" ¬ACK_GENERAL_CALL <Ú
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" ¬ENABLE_STATUS ÿÚ
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" ¬
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FS_SPKLEN ,Ú
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" ¬
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HS_SPKLEN *Ú
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" ¬CLR_RESTART_DET DÚ I2C_T Ú P I2C_CON_MASTER_MODE ùÚ P I2C_CON_SPEED äÚ P I2C_CON_SPEED_0 QÚ P I2C_CON_SPEED_1 PÚ# P I2C_CON_IC_10BITADDR_SLAVE Ú$ P I2C_CON_IC_10BITADDR_MASTER ÈÚ P I2C_CON_IC_RESTART_EN CÚ! P I2C_CON_IC_SLAVE_DISABLE Ú% P I2C_CON_STOP_DET_IFADDRESSED 8Ú P I2C_CON_TX_EMPTY_CTRL Ú P I2C_TAR_TAR kÚ P I2C_TAR_IC_TAR_0 çÚ P I2C_TAR_IC_TAR_1 æÚ P I2C_TAR_IC_TAR_2 åÚ P I2C_TAR_IC_TAR_3 äÚ P I2C_TAR_IC_TAR_4 ãÚ P I2C_TAR_IC_TAR_5 âÚ P I2C_TAR_IC_TAR_6 áÚ P I2C_TAR_IC_TAR_7 àÚ P I2C_TAR_IC_TAR_8 ßÚ P I2C_TAR_IC_TAR_9 ÞÚ P I2C_TAR_GC_OR_START ËÚ P I2C_TAR_SPECIAL IÚ$ P I2C_TAR_IC_10BITADDR_MASTER ÁÚ P I2C_SAR_IC_SAR |Ú P I2C_HS_MADDR_IC_HS_MAR üÚ P I2C_DATA_CMD_DAT Ú P I2C_DATA_CMD_CMD_R YÚ P I2C_DATA_CMD_STOP Ú P I2C_DATA_CMD_RESTART µÚ P I2C_SS_SCL_HCNT Ú P I2C_SS_SCL_LCNT Ú P I2C_FS_SCL_HCNT *Ú P I2C_FS_SCL_LCNT &Ú P I2C_HS_SCL_HCNT (Ú P I2C_HS_SCL_LCNT $Ú! P I2C_INTR_STAT_R_RX_UNDER Ú P I2C_INTR_STAT_R_RX_OVER SÚ P I2C_INTR_STAT_R_RX_FULL \Ú P I2C_INTR_STAT_R_TX_OVER QÚ! P I2C_INTR_STAT_R_TX_EMPTY üÚ P I2C_INTR_STAT_R_RD_REQ ½Ú P I2C_INTR_STAT_R_TX_ABRT dÚ P I2C_INTR_STAT_R_RX_DONE iÚ! P I2C_INTR_STAT_R_ACTIVITY )Ú! P I2C_INTR_STAT_R_STOP_DET Ú" P I2C_INTR_STAT_R_START_DET ÊÚ! P I2C_INTR_STAT_R_GEN_CALL AÚ$ P I2C_INTR_STAT_R_RESTART_DET /Ú$ P I2C_INTR_STAT_R_MST_ON_HOLD Ú! P I2C_INTR_MASK_M_RX_UNDER $Ú P I2C_INTR_MASK_M_RX_OVER hÚ P I2C_INTR_MASK_M_RX_FULL qÚ P I2C_INTR_MASK_M_TX_OVER fÚ! P I2C_INTR_MASK_M_TX_EMPTY Ú P I2C_INTR_MASK_M_RD_REQ ÒÚ P I2C_INTR_MASK_M_TX_ABRT yÚ P I2C_INTR_MASK_M_RX_DONE ~Ú! P I2C_INTR_MASK_M_ACTIVITY >Ú! P I2C_INTR_MASK_M_STOP_DET )Ú" P I2C_INTR_MASK_M_START_DET ßÚ! P I2C_INTR_MASK_M_GEN_CALL VÚ$ P I2C_INTR_MASK_M_RESTART_DET DÚ$ P I2C_INTR_MASK_M_MST_ON_HOLD /Ú# P I2C_RAW_INTR_STAT_RX_UNDER sÚ" P I2C_RAW_INTR_STAT_RX_OVER ·Ú" P I2C_RAW_INTR_STAT_RX_FULL ÀÚ" P I2C_RAW_INTR_STAT_TX_OVER µÚ# P I2C_RAW_INTR_STAT_TX_EMPTY `Ú! P I2C_RAW_INTR_STAT_RD_REQ !Ú" P I2C_RAW_INTR_STAT_TX_ABRT ÈÚ" P I2C_RAW_INTR_STAT_RX_DONE ÍÚ# P I2C_RAW_INTR_STAT_ACTIVITY Ú# P I2C_RAW_INTR_STAT_STOP_DET xÚ$ P I2C_RAW_INTR_STAT_START_DET .Ú# P I2C_RAW_INTR_STAT_GEN_CALL ¥Ú& P I2C_RAW_INTR_STAT_RESTART_DET Ú& P I2C_RAW_INTR_STAT_MST_ON_HOLD ~Ú P
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I2C_RX_TL óÚ P
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I2C_TX_TL ñÚ P I2C_CLR_INTR Ú P I2C_CLR_RX_UNDER ÇÚ P I2C_CLR_TX_OVER Ú P I2C_CLR_RD_REQ uÚ P I2C_CLR_TX_ABORT ËÚ P I2C_CLR_RX_DONE !Ú P I2C_CLR_ACTIVITY áÚ P I2C_CLR_STOP_DET ÌÚ P I2C_CLR_START_DET Ú P I2C_CLR_GEN_CALL ùÚ P I2C_CLR_RESTART_DET çÚ P I2C_CLR_MST_ON_HOLD ÒÚ P I2C_ENABLE_ENABLE ßÚ P I2C_ENABLE_ABORT Ú P I2C_STATUS_ACTIVITY ØÚ P I2C_STATUS_TFNF Ú P I2C_STATUS_TFE pÚ P I2C_STATUS_RFNE "Ú P I2C_STATUS_RFE rÚ P I2C_STATUS_MST_ACTIVITY }Ú P I2C_STATUS_SLV_ACTIVITY |Ú P
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I2C_TXFLR Ú P
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I2C_RXFLR Ú P I2C_SDA_HOLD 8Ú) P !I2C_TX_ABRT_SOURCE_7B_ADDR_NOACK íÚ) P !I2C_TX_ABRT_SOURCE_10ADDR1_NOACK 3Ú) P !I2C_TX_ABRT_SOURCE_10ADDR2_NOACK 2Ú( P I2C_TX_ABRT_SOURCE_TXDATA_NOACK Ú' P I2C_TX_ABRT_SOURCE_GCALL_NOACK Ú& P I2C_TX_ABRT_SOURCE_GCALL_READ ÓÚ% P I2C_TX_ABRT_SOURCE_HS_ACKDET Ú( P I2C_TX_ABRT_SOURCE_SBYTE_ACKDET Ú& P I2C_TX_ABRT_SOURCE_HS_NORSTRT {Ú) P !I2C_TX_ABRT_SOURCE_SBYTE_NORSTRT Ú* P "I2C_TX_ABRT_SOURCE_10B_RD_NORSTRT vÚ& P I2C_TX_ABRT_SOURCE_MASTER_DIS ¦Ú$ P I2C_TX_ABRT_SOURCE_ARB_LOST ?Ú+ P #I2C_TX_ABRT_SOURCE_SLVFLUSH_TXFIFO Ú' P I2C_TX_ABRT_SOURCE_SLV_ARBLOST DÚ& P I2C_TX_ABRT_SOURCE_SLVRD_INTX Ú% P I2C_TX_ABRT_SOURCE_USER_ABRT ìÚ( P I2C_TX_ABRT_SOURCE_TX_FLUSH_CNT ÜÚ P I2C_SLV_DATA_NACK_ONLY ÷Ú P I2C_DMA_CR_RDMAE Ú P I2C_DMA_CR_TDMAE þÚ P I2C_DMA_TDLR /Ú P I2C_DMA_RDLR 1Ú P I2C_SDA_SETUP ÌÚ P I2C_ACK_GENERAL_CALL ßÚ P I2C_ENABLE_STATUS_IC_EN ¹Ú) P !I2C_ENABLE_STATUS_SLV_RX_ABORTED ÇÚ6 P .I2C_ENABLE_STATUS_SLV_FIFO_FILLED_AND_FLUSHED èÚ P I2C_FS_SPKLEN ÏÚ P I2C_HS_SPKLEN ÍÚ' P I2C_COMP_PARAM1_APB_DATA_WIDTH ¸Ú' P I2C_COMP_PARAM1_MAX_SPEED_MODE ©Ú( P I2C_COMP_PARAM1_HC_COUNT_VALUES ?Ú P I2C_COMP_PARAM1_INTR_IO ½Ú P I2C_COMP_PARAM1_HAS_DMA äÚ+ P #I2C_COMP_PARAM1_ADD_ENCODED_PARAMS Ú( P I2C_COMP_PARAM1_RX_BUFFER_DEPTH JÚ( P I2C_COMP_PARAM1_TX_BUFFER_DEPTH HÚ P I2C_COMP_VERSION ÚÚ P I2C_COMP_TYPE ÄÚ 8
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<unnamed> QÚ
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" é LP_REG_SYNC :Ú
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" éLP_FL_CTRL_3V ¢Ú
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" éLP_SPACING_TIME0 çÚ
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" éLP_SPACING_TIME1 æÚ
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" éLP_SPACING_TIME2 åÚ
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" é
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LP_SLPTMR ÖÚ
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" é LP_INT_CTRL 5Ú
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" éLP_DLY_CTRL_3V IÚ
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" é LP_PTAT_POLY ÖÚ
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" é
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LP_HP_LDO âÚ
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" é LP_LP_LDO_3V ðÚ
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" é LP_ANA_LDO ¨Ú
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" é LP_FSYN_LDO 6Ú
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" éLP_SW Ú
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" é LP_BUCK_3V ©Ú
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" é ANA_ADC_LDO zÚ
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" é ANA_RFFE_LDO Ú
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" é ANA_VCO_LDO ZÚ
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" éANA_DFT ªÚ
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" é ANA_MISC_3V lÚ
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" éANA_RESERVED_3V 0Ú
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" é ACT_32K_CTRL 2Ú
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" éACT_32K_BASECORR Ú
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" éCPU_ADDR_REMAP_CTRL ÕÚ
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" éRCL_HW_CAL_CTRL Ú ANA_T tÚ P ANAC_LP_REG_SYNC_3V_Pos =Ú P ANAC_LP_REG_SYNC_3V_Msk DÚ$ P ANAC_LP_REG_SYNC_3V_TRG_Pos éÚ$ P ANAC_LP_REG_SYNC_3V_TRG_Msk ðÚ# P ANAC_FL_SLEEP_MODE_SEL_Pos cÚ# P ANAC_FL_SLEEP_MODE_SEL_Msk jÚ& P ANAC_FL_EXT_WAKEUP_SEL_Pos_3v 5Ú& P ANAC_FL_EXT_WAKEUP_SEL_Msk_3v <Ú! P ANAC_FL_SLEEP_CNT_EN_Pos øÚ! P ANAC_FL_SLEEP_CNT_EN_Msk ÿÚ% P ANAC_FL_CPU_RETENTION_EN_Pos ®Ú% P ANAC_FL_CPU_RETENTION_EN_Msk µÚ# P ANAC_FL_LDO_ISOLATE_EN_Pos bÚ# P ANAC_FL_LDO_ISOLATE_EN_Msk iÚ P ANAC_FL_RCL_GATE_EN_Pos VÚ P ANAC_FL_RCL_GATE_EN_Msk ]Ú P ANAC_FL_PWR_CTL_EN_Pos ~Ú P ANAC_FL_PWR_CTL_EN_Msk
Ú P ANAC_FL_FLASH_BP_EN_Pos XÚ P ANAC_FL_FLASH_BP_EN_Msk _Ú P ANAC_FL_FLASH_LP_EN_Pos NÚ P ANAC_FL_FLASH_LP_EN_Msk UÚ P ANAC_FL_BUCK_BP_EN_Pos £Ú P ANAC_FL_BUCK_BP_EN_Msk ªÚ P ANAC_FL_BUCK_EN_Pos Ú P ANAC_FL_BUCK_EN_Msk ¡Ú P ANAC_FL_DPLL_EN_Pos Ú P ANAC_FL_DPLL_EN_Msk Ú P ANAC_FL_RCH_EN_Pos äÚ P ANAC_FL_RCH_EN_Msk ëÚ P ANAC_FL_XTH_EN_Pos ÍÚ P ANAC_FL_XTH_EN_Msk ÔÚ" P ANAC_FL_XTAL32K_EN_Pos_3v ÂÚ" P ANAC_FL_XTAL32K_EN_Msk_3v ÉÚ P ANAC_FL_RC32K_EN_Pos_3v jÚ P ANAC_FL_RC32K_EN_Msk_3v qÚ P ANAC_FL_LDO_HP_EN_Pos åÚ P ANAC_FL_LDO_HP_EN_Msk ìÚ P ANAC_FL_PMU_EN_Pos ÏÚ P ANAC_FL_PMU_EN_Msk ÖÚ! P ANAC_SRAM0_POWER_CTL_Pos Ú! P ANAC_SRAM0_POWER_CTL_Msk Ú! P ANAC_SRAM1_POWER_CTL_Pos Ú! P ANAC_SRAM1_POWER_CTL_Msk Ú P ANAC_CPU_POWER_CTL_Pos Ú P ANAC_CPU_POWER_CTL_Msk Ú P ANAC_PHY_POWER_CTL_Pos }Ú P ANAC_PHY_POWER_CTL_Msk Ú# P ANAC_LL_SRAM_POWER_CTL_Pos <Ú# P ANAC_LL_SRAM_POWER_CTL_Msk CÚ! P ANAC_FLASH_POWER_CTL_Pos üÚ! P ANAC_FLASH_POWER_CTL_Msk Ú P ANAC_LDO_POWER_CTL_Pos Ú P ANAC_LDO_POWER_CTL_Msk Ú P ANAC_LDOL_POWER_CTL_Pos AÚ P ANAC_LDOL_POWER_CTL_Msk HÚ P ANAC_INT_LP_INT_EN_Pos zÚ P ANAC_INT_LP_INT_EN_Msk Ú P ANAC_INT_DP_FLAG_Pos IÚ P ANAC_INT_DP_FLAG_Msk PÚ% P ANAC_INT_STANDBY_M1_FLAG_Pos ÛÚ% P ANAC_INT_STANDBY_M1_FLAG_Msk âÚ% P ANAC_INT_STANDBY_M0_FLAG_Pos ÜÚ% P ANAC_INT_STANDBY_M0_FLAG_Msk ãÚ# P ANAC_INT_SRAM_RET_FLAG_Pos TÚ# P ANAC_INT_SRAM_RET_FLAG_Msk [Ú& P ANAC_INT_SLEEP_TMR_INT_EN_Pos =Ú& P ANAC_INT_SLEEP_TMR_INT_EN_Msk DÚ P ANAC_INT_SLEEP_TMR0_Pos UÚ P ANAC_INT_SLEEP_TMR0_Msk \Ú P ANAC_INT_SLEEP_TMR1_Pos TÚ P ANAC_INT_SLEEP_TMR1_Msk [Ú P ANAC_INT_SLEEP_TMR2_Pos SÚ P ANAC_INT_SLEEP_TMR2_Msk ZÚ% P ANAC_INT_SLEEP_TMR_WK_EN_Pos Ú% P ANAC_INT_SLEEP_TMR_WK_EN_Msk Ú! P ANAC_32KCLK_DLY_TIME_Pos 8Ú! P ANAC_32KCLK_DLY_TIME_Msk ?Ú P ANAC_32KCLK_DLY_EN_Pos ØÚ P ANAC_32KCLK_DLY_EN_Msk ßÚ" P ANAC_HPLDO_RDY_BYPASS_Pos Ú" P ANAC_HPLDO_RDY_BYPASS_Msk §Ú$ P ANAC_LPLDOH_DLY_TIME_Pos_3v ñÚ$ P ANAC_LPLDOH_DLY_TIME_Msk_3v øÚ P ANAC_PTAT_CORE_EN_Pos ëÚ P ANAC_PTAT_CORE_EN_Msk òÚ P ANAC_PTAT_TMP_TRIM_Pos xÚ P ANAC_PTAT_TMP_TRIM_Msk Ú P ANAC_PTAT_TRIM_Pos ÐÚ P ANAC_PTAT_TRIM_Msk ×Ú# P ANAC_PTAT_FLT_SHIFT_EN_Pos GÚ# P ANAC_PTAT_FLT_SHIFT_EN_Msk NÚ! P ANAC_PTAT_FLT_ACT_EN_Pos ñÚ! P ANAC_PTAT_FLT_ACT_EN_Msk øÚ P ANAC_POLY_EN_Pos rÚ P ANAC_POLY_EN_Msk yÚ P ANAC_IPOLY_TRIM_Pos zÚ P ANAC_IPOLY_TRIM_Msk Ú P ANAC_HPLDO_EN_Pos =Ú P ANAC_HPLDO_EN_Msk DÚ P ANAC_HPLDO_BYPASS_Pos öÚ P ANAC_HPLDO_BYPASS_Msk ýÚ P ANAC_HPLDO_TRIM_Pos Ú P ANAC_HPLDO_TRIM_Msk Ú P ANAC_HPLDO_SEL_Pos êÚ P ANAC_HPLDO_SEL_Msk ñÚ& P ANAC_HPLDO_FLASHLDO_BP_Pos_3v rÚ& P ANAC_HPLDO_FLASHLDO_BP_Msk_3v yÚ& P ANAC_HPLDO_FLASHLDO_EN_Pos_3v qÚ& P ANAC_HPLDO_FLASHLDO_EN_Msk_3v xÚ& P ANAC_HPLDO_FLASHLDO_LP_EN_Pos ~Ú& P ANAC_HPLDO_FLASHLDO_LP_EN_Msk
Ú( P ANAC_HPLDO_FLASHLDO_CAP_SEL_Pos ñÚ( P ANAC_HPLDO_FLASHLDO_CAP_SEL_Msk øÚ% P ANAC_HPLDO_FLASHLDO_TRIM_Pos ÒÚ% P ANAC_HPLDO_FLASHLDO_TRIM_Msk ÙÚ P ANAC_LPLDO_L_EN_Pos Ú P ANAC_LPLDO_L_EN_Msk Ú" P ANAC_LPLDO_L_DVDD_SEL_Pos ¬Ú" P ANAC_LPLDO_L_DVDD_SEL_Msk ³Ú P ANAC_LPLDO_H_EN_Pos_3v Ú P ANAC_LPLDO_H_EN_Msk_3v Ú% P ANAC_LPLDO_H_DVDD_SEL_Pos_3v ¢Ú% P ANAC_LPLDO_H_DVDD_SEL_Msk_3v ©Ú% P ANAC_LPLDO_H_REF_TRIM_Pos_3v Ú% P ANAC_LPLDO_H_REF_TRIM_Msk_3v Ú% P ANAC_LPLDO_H_MODE_SEL_Pos_3v Ú% P ANAC_LPLDO_H_MODE_SEL_Msk_3v ¦Ú P ANAC_ANA_LDO_EN_Pos ¢Ú P ANAC_ANA_LDO_EN_Msk ©Ú P ANAC_ANA_LDO_TRIM_Pos õÚ P ANAC_ANA_LDO_TRIM_Msk üÚ P ANAC_FSYN_LDO_EN_Pos 0Ú P ANAC_FSYN_LDO_EN_Msk 7Ú P ANAC_FSYN_LDO_TRIM_Pos Ú P ANAC_FSYN_LDO_TRIM_Msk Ú P ANAC_HP_DVDD_PD_Pos Ú P ANAC_HP_DVDD_PD_Msk Ú P ANAC_HP_DVDD_EN_Pos Ú P ANAC_HP_DVDD_EN_Msk Ú P ANAC_DVDD_SRAM0_EN_Pos ÆÚ P ANAC_DVDD_SRAM0_EN_Msk ÍÚ P ANAC_DVDD_SRAM1_EN_Pos ÅÚ P ANAC_DVDD_SRAM1_EN_Msk ÌÚ P ANAC_DVDD_LPLDO_EN_Pos ®Ú P ANAC_DVDD_LPLDO_EN_Msk µÚ P ANAC_VDD_FLASH_EN_Pos Ú P ANAC_VDD_FLASH_EN_Msk Ú P ANAC_DVDD_DLL_EN_Pos QÚ P ANAC_DVDD_DLL_EN_Msk XÚ P ANAC_DVDD_PHY_EN_Pos <Ú P ANAC_DVDD_PHY_EN_Msk CÚ P ANAC_DVDD_CPU_EN_Pos EÚ P ANAC_DVDD_CPU_EN_Msk LÚ# P ANAC_BUCK_BYPASS_EN_Pos_3v DÚ# P ANAC_BUCK_BYPASS_EN_Msk_3v KÚ P ANAC_BUCK_EN_Pos_3v Ú P ANAC_BUCK_EN_Msk_3v Ú P ANAC_BUCK_VOUT_Pos_3v ÄÚ P ANAC_BUCK_VOUT_Msk_3v ËÚ P ANAC_BUCK_IMAX_Pos_3v ãÚ P ANAC_BUCK_IMAX_Msk_3v êÚ" P ANAC_BUCK_IMAX_CAL_Pos_3v ¬Ú" P ANAC_BUCK_IMAX_CAL_Msk_3v ³Ú" P ANAC_BUCK_ZERO_CAL_Pos_3v Ú" P ANAC_BUCK_ZERO_CAL_Msk_3v ¢Ú% P ANAC_BUCK_DLY_MODE_EN_Pos_3v ¥Ú% P ANAC_BUCK_DLY_MODE_EN_Msk_3v ¬Ú P ANAC_BUCK_TEST_EN_Pos èÚ P ANAC_BUCK_TEST_EN_Msk ïÚ% P ANAC_BUCK_DEBOUNCE_EN_Pos_3v ÍÚ% P ANAC_BUCK_DEBOUNCE_EN_Msk_3v ÔÚ P ANAC_BUCK_CAL_EN_Pos_3v LÚ P ANAC_BUCK_CAL_EN_Msk_3v SÚ P ANAC_BUCK_CAL_OUT_Pos óÚ P ANAC_BUCK_CAL_OUT_Msk úÚ& P ANAC_BUCK_VOL_LIMIT_EN_Pos_3v AÚ& P ANAC_BUCK_VOL_LIMIT_EN_Msk_3v HÚ P ANAC_ADC_LDO_EN_Pos ªÚ P ANAC_ADC_LDO_EN_Msk ±Ú P ANAC_ADC_LDO_TRIM_Pos ýÚ P ANAC_ADC_LDO_TRIM_Msk Ú P ANAC_RFFE_LDO_EN_Pos MÚ P ANAC_RFFE_LDO_EN_Msk TÚ P ANAC_RFFE_LDO_TRIM_Pos Ú P ANAC_RFFE_LDO_TRIM_Msk §Ú P ANAC_VCO_LDO_EN_Pos Ú P ANAC_VCO_LDO_EN_Msk Ú P ANAC_VCO_LDO_TRIM_Pos ÝÚ P ANAC_VCO_LDO_TRIM_Msk äÚ P ANAC_DFT_BUF_BYPASS_Pos OÚ P ANAC_DFT_BUF_BYPASS_Msk VÚ P ANAC_DFT_FLAG_SEL_Pos Ú P ANAC_DFT_FLAG_SEL_Msk Ú P ANAC_DFT_CLK_SEL_Pos FÚ P ANAC_DFT_CLK_SEL_Msk MÚ P ANAC_DFT_I_SEL_Pos ÛÚ P ANAC_DFT_I_SEL_Msk âÚ P ANAC_DFT_V_SEL_Pos ÎÚ P ANAC_DFT_V_SEL_Msk ÕÚ$ P ANAC_DFT_FLAG_OUTPUT_EN_Pos ùÚ$ P ANAC_DFT_FLAG_OUTPUT_EN_Msk Ú# P ANAC_DFT_CLK_OUTPUT_EN_Pos ;Ú# P ANAC_DFT_CLK_OUTPUT_EN_Msk BÚ! P ANAC_DFT_I_OUTPUT_EN_Pos ÐÚ! P ANAC_DFT_I_OUTPUT_EN_Msk ×Ú! P ANAC_DFT_V_OUTPUT_EN_Pos ÃÚ! P ANAC_DFT_V_OUTPUT_EN_Msk ÊÚ" P ANAC_DFT_PAD_TEST_SEL_Pos ¢Ú" P ANAC_DFT_PAD_TEST_SEL_Msk ©Ú% P ANAC_DFT_BATTERY_TEST_EN_Pos §Ú% P ANAC_DFT_BATTERY_TEST_EN_Msk ®Ú& P ANAC_DFT_BATTERY_TEST_SEL_Pos TÚ& P ANAC_DFT_BATTERY_TEST_SEL_Msk [Ú' P ANAC_DFT_BATTERY_TEST_TRIM_Pos úÚ' P ANAC_DFT_BATTERY_TEST_TRIM_Msk Ú' P ANAC_MISC_RST_VREF_TRIM_Pos_3v ÓÚ' P ANAC_MISC_RST_VREF_TRIM_Msk_3v ÚÚ" P ANAC_MISC_PMU_LDO_TST_Pos Ú" P ANAC_MISC_PMU_LDO_TST_Msk Ú% P ANAC_MISC_PMU_VBG_BUF_EN_Pos §Ú% P ANAC_MISC_PMU_VBG_BUF_EN_Msk ®Ú. P &ANAC_MISC_LPLDO_LEVEL_SHIFT_EN_Pos_3v ÊÚ. P &ANAC_MISC_LPLDO_LEVEL_SHIFT_EN_Msk_3v ÑÚ+ P #ANAC_MISC_HPLDO_LEVEL_SHIFT_EN_Pos ÜÚ+ P #ANAC_MISC_HPLDO_LEVEL_SHIFT_EN_Msk ãÚ% P ANAC_MISC_FLASH_PAD_PUEN_Pos ÌÚ% P ANAC_MISC_FLASH_PAD_PUEN_Msk ÓÚ% P ANAC_MISC_FLASH_PAD_PDEN_Pos ÝÚ% P ANAC_MISC_FLASH_PAD_PDEN_Msk äÚ P ANAC_MISC_USB_EN_Pos 9Ú P ANAC_MISC_USB_EN_Msk @Ú P ANAC_MISC_USB_DP_PU_Pos .Ú P ANAC_MISC_USB_DP_PU_Msk 5Ú P ANAC_MISC_USB_DM_PU_Pos 1Ú P ANAC_MISC_USB_DM_PU_Msk 8Ú P ANAC_ACT_32K_EN_Pos ÉÚ P ANAC_ACT_32K_EN_Msk ÐÚ P ANAC_ACT_32K_SEL_Pos vÚ P ANAC_ACT_32K_SEL_Msk }Ú! P ANAC_ACT_32K_UP_DONE_Pos (Ú! P ANAC_ACT_32K_UP_DONE_Msk /Ú% P ANAC_ACT_32K_FINE_OFFSET_Pos Ú% P ANAC_ACT_32K_FINE_OFFSET_Msk Ú& P ANAC_ACT_32K_FINE_CORRECT_Pos µÚ& P ANAC_ACT_32K_FINE_CORRECT_Msk ¼Ú P ANAC_CPU_REMAP_ADR_Pos ªÚ P ANAC_CPU_REMAP_ADR_Msk ±Ú" P ANAC_CPU_ADR_REMAP_EN_Pos ²Ú" P ANAC_CPU_ADR_REMAP_EN_Msk ¹Ú! P ANAC_RCL_HW_CAL_TIME_Pos üÚ! P ANAC_RCL_HW_CAL_TIME_Msk Ú P ANAC_RCL_HW_CAL_EN_Pos Ú P ANAC_RCL_HW_CAL_EN_Msk £Ú! P ANAC_RCL_HW_CAL_BUSY_Pos èÚ! P ANAC_RCL_HW_CAL_BUSY_Msk ïÚ 8
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<unnamed> QÚ
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" EF_CTL NÚ
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" EF_ADDR Ú
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" EF_DAT XÚ
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" EF_RSV0 Ú
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" EF_VDD SÚ
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" EF_RSV1 Ú
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" EF_CMD ]Ú
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" EF_TRG DÚ
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" EF_PROG_TIMING1 Ú
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" EF_PROG_TIMING2 Ú
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" EF_PROG_TIMING3 Ú
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" EF_READ_TIMING4 ¨Ú
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" EF_READ_TIMING5 §Ú <" 0 EF_RSV2 ¤Ú
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" EF_OP_ERROR Ú
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" EF_VERIFY_DEBUG1 QÚ
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" EF_VERIFY_DEBUG2 PÚ
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" EF_VERIFY_DEBUG3 OÚ
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" EF_VERIFY_DEBUG4 NÚ
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" EF_FLASH_PERMISSION AÚ EFUSE_T ÈÚ P EFUSE_CTL_EFUSE_EN_Pos Ú P EFUSE_CTL_EFUSE_EN_Msk Ú P EFUSE_CTL_THR_DVDD_Pos Ú P EFUSE_CTL_THR_DVDD_Msk Ú" P EFUSE_CTL_TAEN_RD_CTL_Pos Ú" P EFUSE_CTL_TAEN_RD_CTL_Msk Ú! P EFUSE_CTL_THR_RD_CTL_Pos ÌÚ! P EFUSE_CTL_THR_RD_CTL_Msk ÓÚ P EFUSE_CTL_TRD_CTL_Pos ËÚ P EFUSE_CTL_TRD_CTL_Msk ÒÚ! P EFUSE_CTL_TSR_RD_CTL_Pos ÁÚ! P EFUSE_CTL_TSR_RD_CTL_Msk ÈÚ# P EFUSE_CTL_TSR_DVDD_CTL_Pos 1Ú# P EFUSE_CTL_TSR_DVDD_CTL_Msk 8Ú! P EFUSE_CTL_THP_RD_CTL_Pos ÎÚ! P EFUSE_CTL_THP_RD_CTL_Msk ÕÚ& P EFUSE_CTL_THP_PG_AVDD_CTL_Pos EÚ& P EFUSE_CTL_THP_PG_AVDD_CTL_Msk LÚ# P EFUSE_CTL_TAEN_PGM_CTL_Pos @Ú# P EFUSE_CTL_TAEN_PGM_CTL_Msk GÚ" P EFUSE_CTL_THP_PGM_CTL_Pos ~Ú" P EFUSE_CTL_THP_PGM_CTL_Msk
Ú P EFUSE_CTL_TPGM_CTL_Pos {Ú P EFUSE_CTL_TPGM_CTL_Msk Ú" P EFUSE_CTL_TSP_PGM_CTL_Pos sÚ" P EFUSE_CTL_TSP_PGM_CTL_Msk zÚ& P EFUSE_CTL_TSP_PG_AVDD_CTL_Pos :Ú& P EFUSE_CTL_TSP_PG_AVDD_CTL_Msk AÚ! P EFUSE_CTL_TSP_RD_CTL_Pos ÃÚ% P EFUSE_CTL_TSP_TSP_RD_CTL_Msk lÚ% P EFUSE_ADDR_EFUSEADDR_ADR_Pos èÚ% P EFUSE_ADDR_EFUSEADDR_ADR_Msk ïÚ# P EFUSE_DAT_EFUSEDAT_DAT_Pos nÚ# P EFUSE_DAT_EFUSEDAT_DAT_Msk uÚ+ P #EFUSE_DAT_EFUSEDAT_DAT_CONFIRM_Pos ñÚ+ P #EFUSE_DAT_EFUSEDAT_DAT_CONFIRM_Msk øÚ P EFUSE_VDD_DVDD_REG_Pos Ú P EFUSE_VDD_DVDD_REG_Msk ¢Ú P EFUSE_VDD_AVDD_REG_Pos Ú P EFUSE_VDD_AVDD_REG_Msk ¥Ú# P EFUSE_CMD_EFUSECMD_CMD_Pos }Ú# P EFUSE_CMD_EFUSECMD_CMD_Msk Ú" P EFUSE_TRG_EFUSETRG_GO_Pos Ú" P EFUSE_TRG_EFUSETRG_GO_Msk Ú* P "EFUSE_PROG_TIMING1_TSP_RD_SET_Pos ûÚ* P "EFUSE_PROG_TIMING1_TSP_RD_SET_Msk Ú/ P 'EFUSE_PROG_TIMING1_TSP_PG_AVDD_SET_Pos rÚ/ P 'EFUSE_PROG_TIMING1_TSP_PG_AVDD_SET_Msk yÚ+ P #EFUSE_PROG_TIMING1_TSP_PGM_SET_Pos «Ú+ P #EFUSE_PROG_TIMING1_TSP_PGM_SET_Msk ²Ú( P EFUSE_PROG_TIMING2_TPGM_SET_Pos ²Ú( P EFUSE_PROG_TIMING2_TPGM_SET_Msk ¹Ú+ P #EFUSE_PROG_TIMING2_THP_PGM_SET_Pos µÚ+ P #EFUSE_PROG_TIMING2_THP_PGM_SET_Msk ¼Ú, P $EFUSE_PROG_TIMING2_TAEN_PGM_SET_Pos wÚ, P $EFUSE_PROG_TIMING2_TAEN_PGM_SET_Msk ~Ú/ P 'EFUSE_PROG_TIMING3_THP_PG_AVDD_SET_Pos {Ú/ P 'EFUSE_PROG_TIMING3_THP_PG_AVDD_SET_Msk Ú* P "EFUSE_PROG_TIMING3_THP_RD_SET_Pos Ú* P "EFUSE_PROG_TIMING3_THP_RD_SET_Msk Ú, P $EFUSE_READ_TIMING4_TSR_DVDD_SET_Pos Ú, P $EFUSE_READ_TIMING4_TSR_DVDD_SET_Msk Ú* P "EFUSE_READ_TIMING4_TSR_RD_SET_Pos Ú* P "EFUSE_READ_TIMING4_TSR_RD_SET_Msk Ú' P EFUSE_READ_TIMING4_TRD_SET_Pos Ú' P EFUSE_READ_TIMING4_TRD_SET_Msk #Ú* P "EFUSE_READ_TIMING5_THR_RD_SET_Pos Ú* P "EFUSE_READ_TIMING5_THR_RD_SET_Msk #Ú+ P #EFUSE_READ_TIMING5_TAEN_RD_SET_Pos àÚ+ P #EFUSE_READ_TIMING5_TAEN_RD_SET_Msk çÚ, P $EFUSE_READ_TIMING5_THR_DVDD_SET_Pos Ú, P $EFUSE_READ_TIMING5_THR_DVDD_SET_Msk Ú$ P EFUSE_OP_ERROR_OP_ERROR_Pos ¾Ú$ P EFUSE_OP_ERROR_OP_ERROR_Msk ÅÚ0 P (EFUSE_VERIFY_DEBUG1_VERIFY_DBG_KEY1_Pos pÚ0 P (EFUSE_VERIFY_DEBUG1_VERIFY_DBG_KEY1_Msk wÚ0 P (EFUSE_VERIFY_DEBUG2_VERIFY_DBG_KEY2_Pos nÚ0 P (EFUSE_VERIFY_DEBUG2_VERIFY_DBG_KEY2_Msk uÚ0 P (EFUSE_VERIFY_DEBUG3_VERIFY_DBG_KEY3_Pos lÚ0 P (EFUSE_VERIFY_DEBUG3_VERIFY_DBG_KEY3_Msk sÚ0 P (EFUSE_VERIFY_DEBUG4_VERIFY_DBG_KEY4_Pos jÚ0 P (EFUSE_VERIFY_DEBUG4_VERIFY_DBG_KEY4_Msk qÚ( P EFUSE_FLASH_PERMISSION_CTRL_Pos »Ú( P EFUSE_FLASH_PERMISSION_CTRL_Msk ÂÚ 8
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<unnamed> QÚ " î FADDR YÚ " î POWER -Ú " î INT_IN1 ¤Ú " î INT_IN2 £Ú " î INT_OUT1 AÚ " î INT_OUT2 @Ú " î INT_USB Ú " î INT_IN1E ]Ú " î INT_IN2E \Ú " î
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INT_OUT1E úÚ " î
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INT_OUT2E ùÚ " î INT_USBE ;Ú " î FRAME1 Ú " î FRAME2 Ú " î INDEX BÚ " î REV ÑÚ " î MAX_PKT_IN Ú " î CSR0_INCSR1 Ú " î IN_CSR2 ¦Ú " î MAX_PKT_OUT #Ú " î OUT_CSR1 DÚ " î OUT_CSR2 CÚ " î OUT_COUNT1 Ú " î OUT_COUNT2 Ú <" î REV0 bÚ " î FIFO_EP0 lÚ <" î REV1 fÚ " î FIFO_EP1 kÚ <" î REV2 eÚ " î FIFO_EP2 jÚ <" î REV3 dÚ " î FIFO_EP3 iÚ USB_T ZÚ 8
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<unnamed> QÚ
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" DMA_INTR Ú
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" CNTL1 ®Ú
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" ADDR1 ÄÚ
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" COUNT1 TÚ USBDMA_T Ú P USB_DMA_REQUEST_Pos qÚ P USB_DMA_REQUEST_Msk xÚ P USB_DMA_DIRECTION_Pos õÚ P USB_DMA_DIRECTION_Msk üÚ P USB_DMA_MODE_SEL_Pos 0Ú P USB_DMA_MODE_SEL_Msk 7Ú P USB_DMA_EP_NUM_Pos ¸Ú P USB_DMA_EP_NUM_Msk ¿Ú 8
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<unnamed> QÚ
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" revs0 Ú
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" FSM5 éÚ
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" FSM6 èÚ
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" FSM13 ¸Ú
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" FSM14 ·Ú
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" FSM15 ¶Ú
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" FSM16 µÚ
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" FSM17 ´Ú
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" FSM18 ³Ú
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" FSM19 ²Ú
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" PHY1 âÚ
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" PHY2 áÚ
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" PHY3 àÚ
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" PHY4 ßÚ
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" PHY5 ÞÚ <" revs1 ÛÚ
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" INTR1 Ú
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" INTCLR 4Ú
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" INTMSK *Ú
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" INTR4 Ú
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" revs2 Ú
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" ACTTMR1 Ú
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" ACTTMR2 Ú
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" ACTTMR6 ýÚ
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" ACTTMR7 üÚ
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" revs3 Ú
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" SECURE1 Ú
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" SECURE2 Ú
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" SECURE3 Ú
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" SECURE4 Ú
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" SECURE5 Ú
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" SECURE6 Ú
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" SECURE7 Ú
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" SECURE8 ÿÚ
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" SECURE9 þÚ
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" SECURE10 ÔÚ
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" revs4 Ú
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" TEST_MUX00 ÿÚ
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" RNG1 ìÚ
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" RNG2 ëÚ
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" revs5 Ú
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" LL_MAC_CTRL Ú
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" TEST_MUX01 þÚ
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" TEST_MUX02 ýÚ
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" TEST_MUX03 üÚ <" revs6 ÖÚ
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" R00_CTL
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Ú
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" R01_INT Ú
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" R02_TMR_CTL ®Ú
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" R03_RX_ADDR_L Ú
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" R04_RX_CTL ÷Ú
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" R05_TX_ADDR_L Ú
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" R06_TX_CTL óÚ
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" R07_SRAM_CTL gÚ
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" R08_RX_ADDR1_L ×Ú
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" R09_RX_ADDR2_L ÕÚ
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" R0A_RX_ADDR3_L ÌÚ
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" R0B_RX_ADDR4_L ÊÚ
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" R0C_RX_ADDR5_L ÈÚ
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" R0D_RX_ADDR6_L ÆÚ
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" R0E_RX_ADDR7_L ÄÚ
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" R0F_RX_ADDR_H Ú
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" R10_RX_ADDR_EN ÈÚ
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" R11_CFG Ú PRI_RF_T \Ú P FSM5_SM_STP_Pos ¬Ú P FSM5_SM_STP_Msk ³Ú P FSM5_SM_TX_LATENCY_Pos zÚ P FSM5_SM_TX_LATENCY_Msk Ú P FSM6_SM_RX_LATENCY_Pos {Ú P FSM6_SM_RX_LATENCY_Msk Ú& P FSM13_SM_RX_PACKET_ADDR_1_Pos Ú& P FSM13_SM_RX_PACKET_ADDR_1_Msk Ú& P FSM13_SM_TX_PACKET_ADDR_1_Pos Ú& P FSM13_SM_TX_PACKET_ADDR_1_Msk Ú& P FSM14_SM_RX_PACKET_ADDR_2_Pos Ú& P FSM14_SM_RX_PACKET_ADDR_2_Msk Ú& P FSM14_SM_TX_PACKET_ADDR_2_Pos Ú& P FSM14_SM_TX_PACKET_ADDR_2_Msk Ú& P FSM15_SM_RX_PACKET_ADDR_3_Pos Ú& P FSM15_SM_RX_PACKET_ADDR_3_Msk Ú& P FSM15_SM_TX_PACKET_ADDR_3_Pos Ú& P FSM15_SM_TX_PACKET_ADDR_3_Msk Ú& P FSM16_SM_RX_PACKET_ADDR_4_Pos Ú& P FSM16_SM_RX_PACKET_ADDR_4_Msk Ú& P FSM16_SM_TX_PACKET_ADDR_4_Pos
Ú& P FSM16_SM_TX_PACKET_ADDR_4_Msk Ú& P FSM17_SM_RX_PACKET_ADDR_5_Pos
Ú& P FSM17_SM_RX_PACKET_ADDR_5_Msk Ú& P FSM17_SM_TX_PACKET_ADDR_5_Pos Ú& P FSM17_SM_TX_PACKET_ADDR_5_Msk Ú& P FSM18_SM_RX_PACKET_ADDR_6_Pos Ú& P FSM18_SM_RX_PACKET_ADDR_6_Msk Ú& P FSM18_SM_TX_PACKET_ADDR_6_Pos Ú& P FSM18_SM_TX_PACKET_ADDR_6_Msk Ú& P FSM19_SM_RX_PACKET_ADDR_7_Pos Ú& P FSM19_SM_RX_PACKET_ADDR_7_Msk Ú& P FSM19_SM_TX_PACKET_ADDR_7_Pos Ú& P FSM19_SM_TX_PACKET_ADDR_7_Msk Ú& P PHY1_PHY_DRV_RSP_BUF_FULL_Pos !Ú& P PHY1_PHY_DRV_RSP_BUF_FULL_Msk (Ú' P PHY1_PHY_DRV_RSP_BUF_EMPTY_Pos ÃÚ' P PHY1_PHY_DRV_RSP_BUF_EMPTY_Msk ÊÚ' P PHY1_PHY_DRV_CFG_BUF_ERROR_Pos íÚ' P PHY1_PHY_DRV_CFG_BUF_ERROR_Msk ôÚ& P PHY1_PHY_DRV_CFG_BUF_FULL_Pos FÚ& P PHY1_PHY_DRV_CFG_BUF_FULL_Msk MÚ' P PHY1_PHY_DRV_CFG_BUF_EMPTY_Pos èÚ' P PHY1_PHY_DRV_CFG_BUF_EMPTY_Msk ïÚ! P PHY1_IF_CLK_PRESCALE_Pos Ú! P PHY1_IF_CLK_PRESCALE_Msk Ú' P PHY1_PHY_DRV_RSSI_REG_ADDR_Pos êÚ' P PHY1_PHY_DRV_RSSI_REG_ADDR_Msk ñÚ! P PHY1_PHY_DRV_CFG_TRG_Pos ÒÚ! P PHY1_PHY_DRV_CFG_TRG_Msk ÙÚ! P PHY1_PHY_DRV_CFG_REG_Pos áÚ! P PHY1_PHY_DRV_CFG_REG_Msk èÚ' P PHY1_PHY_DRV_RSP_BUF_FLUSH_Pos ÐÚ' P PHY1_PHY_DRV_RSP_BUF_FLUSH_Msk ×Ú' P PHY1_PHY_DRV_CFG_BUF_FLUSH_Pos õÚ' P PHY1_PHY_DRV_CFG_BUF_FLUSH_Msk üÚ' P PHY2_PHY_DRV_RSP_BUF_ERROR_Pos ÇÚ' P PHY2_PHY_DRV_RSP_BUF_ERROR_Msk ÎÚ) P !PHY2_PHY_DRV_SEQ_RX_END_ADDR_Pos ;Ú) P !PHY2_PHY_DRV_SEQ_RX_END_ADDR_Msk BÚ) P !PHY2_PHY_DRV_SEQ_TX_END_ADDR_Pos 9Ú) P !PHY2_PHY_DRV_SEQ_TX_END_ADDR_Msk @Ú* P "PHY2_PHY_DRV_SEQ_RX_STRT_ADDR_Pos ÃÚ* P "PHY2_PHY_DRV_SEQ_RX_STRT_ADDR_Msk ÊÚ* P "PHY2_PHY_DRV_SEQ_TX_STRT_ADDR_Pos ÁÚ* P "PHY2_PHY_DRV_SEQ_TX_STRT_ADDR_Msk ÈÚ% P PHY3_PHY_DRV_CFG_BUF_DIN_Pos Ú% P PHY3_PHY_DRV_CFG_BUF_DIN_Msk ¥Ú& P PHY4_PHY_DRV_RSP_BUF_DOUT_Pos Ú& P PHY4_PHY_DRV_RSP_BUF_DOUT_Msk Ú+ P #PHY5_PHY_DRV_SET_CHAN_REG_ADDR_Pos ºÚ+ P #PHY5_PHY_DRV_SET_CHAN_REG_ADDR_Msk ÁÚ P INTR1_IC_RNG_DONE_Pos ìÚ P INTR1_IC_RNG_DONE_Msk óÚ P INTR1_IC_SEC_DONE_Pos øÚ P INTR1_IC_SEC_DONE_Msk ÿÚ0 P (INTR1_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_Pos Ú0 P (INTR1_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_Msk Ú& P INTR1_IC_PHY_DRV_CFG_DONE_Pos XÚ& P INTR1_IC_PHY_DRV_CFG_DONE_Msk _Ú# P INTCLR_IC_RNG_DONE_CLR_Pos DÚ# P INTCLR_IC_RNG_DONE_CLR_Msk KÚ# P INTCLR_IC_SEC_DONE_CLR_Pos PÚ# P INTCLR_IC_SEC_DONE_CLR_Msk WÚ5 P -INTCLR_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_CLR_Pos XÚ5 P -INTCLR_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_CLR_Msk _Ú+ P #INTCLR_IC_PHY_DRV_CFG_DONE_CLR_Pos °Ú+ P #INTCLR_IC_PHY_DRV_CFG_DONE_CLR_Msk ·Ú$ P INTMSK_IC_RNG_DONE_MASK_Pos íÚ$ P INTMSK_IC_RNG_DONE_MASK_Msk ôÚ$ P INTMSK_IC_SEC_DONE_MASK_Pos ùÚ$ P INTMSK_IC_SEC_DONE_MASK_Msk Ú6 P .INTMSK_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_MASK_Pos Ú6 P .INTMSK_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_MASK_Msk Ú, P $INTMSK_IC_PHY_DRV_CFG_DONE_MASK_Pos YÚ, P $INTMSK_IC_PHY_DRV_CFG_DONE_MASK_Msk `Ú P INTR4_IC_CLR_IRQ_Pos +Ú P INTR4_IC_CLR_IRQ_Msk 2Ú( P INTR4_IC_ONE_PULSE_FLAG_IRQ_Pos ³Ú( P INTR4_IC_ONE_PULSE_FLAG_IRQ_Msk ºÚ P INTR4_IC_MODE_IRQ_Pos åÚ P INTR4_IC_MODE_IRQ_Msk ìÚ P INTR4_IC_PULSE_CNT_Pos Ú P INTR4_IC_PULSE_CNT_Msk Ú. P &ACTTMR1_ACTTMR_CMPR_MAX_EVENT_DIN_Pos ÙÚ. P &ACTTMR1_ACTTMR_CMPR_MAX_EVENT_DIN_Msk àÚ' P ACTTMR2_ACTTMR_DISABLE_FLG_Pos LÚ' P ACTTMR2_ACTTMR_DISABLE_FLG_Msk SÚ& P ACTTMR2_ACT_CLK_ACCUR_FLG_Pos Ú& P ACTTMR2_ACT_CLK_ACCUR_FLG_Msk Ú- P %ACTTMR2_ACTTMR_CMPR_MAX_EVENT_EN_Pos "Ú- P %ACTTMR2_ACTTMR_CMPR_MAX_EVENT_EN_Msk )Ú/ P 'ACTTMR6_ACTTMR_CMPR_STRT_EVENT_DIN_Pos kÚ/ P 'ACTTMR6_ACTTMR_CMPR_STRT_EVENT_DIN_Msk rÚ* P "ACTTMR7_ACTTMR_CPTUR_BUS_DOUT_Pos ûÚ* P "ACTTMR7_ACTTMR_CPTUR_BUS_DOUT_Msk Ú# P SECURE1_SEC_DECRYPT_EN_Pos hÚ# P SECURE1_SEC_DECRYPT_EN_Msk oÚ P SECURE1_SEC_AD_LEN_Pos ºÚ P SECURE1_SEC_AD_LEN_Msk ÁÚ P SECURE1_SEC_MIC_LEN_Pos dÚ P SECURE1_SEC_MIC_LEN_Msk kÚ P SECURE1_SEC_VLD_MAC_Pos eÚ P SECURE1_SEC_VLD_MAC_Msk lÚ$ P SECURE1_SEC_PKT_ENABLES_Pos +Ú$ P SECURE1_SEC_PKT_ENABLES_Msk 2Ú P SECURE1_SEC_MODE_Pos \Ú P SECURE1_SEC_MODE_Msk cÚ P SECURE1_SEC_ENABLE_Pos ÖÚ P SECURE1_SEC_ENABLE_Msk ÝÚ P SECURE2_SEC_IV3_Pos °Ú P SECURE2_SEC_IV3_Msk ·Ú P SECURE2_SEC_IV2_Pos ±Ú P SECURE2_SEC_IV2_Msk ¸Ú P SECURE2_SEC_IV1_Pos ²Ú P SECURE2_SEC_IV1_Msk ¹Ú P SECURE2_SEC_IV0_Pos ³Ú P SECURE2_SEC_IV0_Msk ºÚ P SECURE3_SEC_IV7_Pos «Ú P SECURE3_SEC_IV7_Msk ²Ú P SECURE3_SEC_IV6_Pos ¬Ú P SECURE3_SEC_IV6_Msk ³Ú P SECURE3_SEC_IV5_Pos Ú P SECURE3_SEC_IV5_Msk ´Ú P SECURE3_SEC_IV4_Pos ®Ú P SECURE3_SEC_IV4_Msk µÚ% P SECURE4_SEC_KEY2_RX_ADDR_Pos ÐÚ% P SECURE4_SEC_KEY2_RX_ADDR_Msk ×Ú% P SECURE4_SEC_KEY1_RX_ADDR_Pos ÑÚ% P SECURE4_SEC_KEY1_RX_ADDR_Msk ØÚ% P SECURE5_SEC_KEY4_RX_ADDR_Pos ÍÚ% P SECURE5_SEC_KEY4_RX_ADDR_Msk ÔÚ% P SECURE5_SEC_KEY3_RX_ADDR_Pos ÎÚ% P SECURE5_SEC_KEY3_RX_ADDR_Msk ÕÚ% P SECURE6_SEC_KEY6_RX_ADDR_Pos ÊÚ% P SECURE6_SEC_KEY6_RX_ADDR_Msk ÑÚ% P SECURE6_SEC_KEY5_RX_ADDR_Pos ËÚ% P SECURE6_SEC_KEY5_RX_ADDR_Msk ÒÚ P SECURE7_SEC_MD_LEN_Pos ¨Ú P SECURE7_SEC_MD_LEN_Msk ¯Ú% P SECURE7_SEC_KEY7_RX_ADDR_Pos ÈÚ% P SECURE7_SEC_KEY7_RX_ADDR_Msk ÏÚ' P SECURE7_SEC_PKT_CNT_TX_MSB_Pos èÚ' P SECURE7_SEC_PKT_CNT_TX_MSB_Msk ïÚ' P SECURE8_SEC_PKT_CNT_TX_LSB_Pos èÚ' P SECURE8_SEC_PKT_CNT_TX_LSB_Msk ïÚ' P SECURE9_SEC_PKT_CNT_RX_MSB_Pos èÚ' P SECURE9_SEC_PKT_CNT_RX_MSB_Msk ïÚ( P SECURE10_SEC_PKT_CNT_RX_LSB_Pos ¿Ú( P SECURE10_SEC_PKT_CNT_RX_LSB_Msk ÆÚ) P !TEST_MUX00_TST_MUX_SELECT_03_Pos mÚ) P !TEST_MUX00_TST_MUX_SELECT_03_Msk tÚ) P !TEST_MUX00_TST_MUX_SELECT_02_Pos nÚ) P !TEST_MUX00_TST_MUX_SELECT_02_Msk uÚ) P !TEST_MUX00_TST_MUX_SELECT_01_Pos oÚ) P !TEST_MUX00_TST_MUX_SELECT_01_Msk vÚ) P !TEST_MUX00_TST_MUX_SELECT_00_Pos pÚ) P !TEST_MUX00_TST_MUX_SELECT_00_Msk wÚ$ P RNG1_RNG_RING_SCRMB_SEL_Pos þÚ$ P RNG1_RNG_RING_SCRMB_SEL_Msk Ú P RNG1_RNG_EN_Pos ÌÚ P RNG1_RNG_EN_Msk ÓÚ P RNG2_RNG_DATA_Pos @Ú P RNG2_RNG_DATA_Msk GÚ# P LL_MAC_CTRL_CTRL_LL_EN_Pos -Ú# P LL_MAC_CTRL_CTRL_LL_EN_Msk 4Ú) P !TEST_MUX01_TST_MUX_SELECT_07_Pos hÚ) P !TEST_MUX01_TST_MUX_SELECT_07_Msk oÚ) P !TEST_MUX01_TST_MUX_SELECT_06_Pos iÚ) P !TEST_MUX01_TST_MUX_SELECT_06_Msk pÚ) P !TEST_MUX01_TST_MUX_SELECT_05_Pos jÚ) P !TEST_MUX01_TST_MUX_SELECT_05_Msk qÚ) P !TEST_MUX01_TST_MUX_SELECT_04_Pos kÚ) P !TEST_MUX01_TST_MUX_SELECT_04_Msk rÚ) P !TEST_MUX02_TST_MUX_SELECT_11_Pos lÚ) P !TEST_MUX02_TST_MUX_SELECT_11_Msk sÚ) P !TEST_MUX02_TST_MUX_SELECT_10_Pos mÚ) P !TEST_MUX02_TST_MUX_SELECT_10_Msk tÚ) P !TEST_MUX02_TST_MUX_SELECT_09_Pos eÚ) P !TEST_MUX02_TST_MUX_SELECT_09_Msk lÚ) P !TEST_MUX02_TST_MUX_SELECT_08_Pos fÚ) P !TEST_MUX02_TST_MUX_SELECT_08_Msk mÚ) P !TEST_MUX03_TST_MUX_SELECT_15_Pos gÚ) P !TEST_MUX03_TST_MUX_SELECT_15_Msk nÚ) P !TEST_MUX03_TST_MUX_SELECT_14_Pos hÚ) P !TEST_MUX03_TST_MUX_SELECT_14_Msk oÚ) P !TEST_MUX03_TST_MUX_SELECT_13_Pos iÚ) P !TEST_MUX03_TST_MUX_SELECT_13_Msk pÚ) P !TEST_MUX03_TST_MUX_SELECT_12_Pos jÚ) P !TEST_MUX03_TST_MUX_SELECT_12_Msk qÚ# P R00_CTL_TX_PAYLOAD_LEN_Pos `Ú# P R00_CTL_TX_PAYLOAD_LEN_Msk gÚ# P R00_CTL_RX_PAYLOAD_LEN_Pos bÚ# P R00_CTL_RX_PAYLOAD_LEN_Msk iÚ# P R00_CTL_CRC_ACCESS_ADR_Pos Ú# P R00_CTL_CRC_ACCESS_ADR_Msk Ú P R00_CTL_CRC24_EN_Pos Ú P R00_CTL_CRC24_EN_Msk Ú" P R00_CTL_ADDR_BYTE_LEN_Pos ÉÚ" P R00_CTL_ADDR_BYTE_LEN_Msk ÐÚ P R00_CTL_DPY_EN_Pos äÚ P R00_CTL_DPY_EN_Msk ëÚ P R00_CTL_CRC_EN_Pos ùÚ P R00_CTL_CRC_EN_Msk Ú P R00_CTL_CRC_SEL16_Pos ;Ú P R00_CTL_CRC_SEL16_Msk BÚ P R00_CTL_SCR_EN_Pos éÚ P R00_CTL_SCR_EN_Msk ðÚ P R00_CTL_NRF_ENHANCE_Pos Ú P R00_CTL_NRF_ENHANCE_Msk Ú P R00_CTL_ENHANCE_Pos ÏÚ P R00_CTL_ENHANCE_Msk ÖÚ P R00_CTL_BW_MODE_Pos ¤Ú P R00_CTL_BW_MODE_Msk «Ú P R00_CTL_CHIP_MODE_Pos Ú P R00_CTL_CHIP_MODE_Msk Ú& P R00_CTL_RX_ACK_PAYLOAD_EN_Pos zÚ& P R00_CTL_RX_ACK_PAYLOAD_EN_Msk Ú P R00_CTL_TX_NOACK_EN_Pos PÚ P R00_CTL_TX_NOACK_EN_Msk WÚ P R00_CTL_PRI_RX_Pos ÏÚ P R00_CTL_PRI_RX_Msk ÖÚ P R01_INT_PRI_RX_PID_Pos Ú P R01_INT_PRI_RX_PID_Msk Ú P R01_INT_PRI_TX_PID_Pos Ú P R01_INT_PRI_TX_PID_Msk Ú" P R01_INT_RX_LENGTH_ERR_Pos Ú" P R01_INT_RX_LENGTH_ERR_Msk Ú# P R01_INT_RX_ACCADDR_ERR_Pos wÚ# P R01_INT_RX_ACCADDR_ERR_Msk ~Ú( P R01_INT_RX_ACCADDR_ERR_MASK_Pos âÚ( P R01_INT_RX_ACCADDR_ERR_MASK_Msk éÚ' P R01_INT_RX_LENGTH_ERR_MASK_Pos Ú' P R01_INT_RX_LENGTH_ERR_MASK_Msk Ú P R01_INT_PRI_ENDIAN_Pos ¹Ú P R01_INT_PRI_ENDIAN_Msk ÀÚ' P R01_INT_PRI_TX_DONE_IRQ_EN_Pos êÚ' P R01_INT_PRI_TX_DONE_IRQ_EN_Msk ñÚ' P R01_INT_PRI_RX_DONE_IRQ_EN_Pos ìÚ' P R01_INT_PRI_RX_DONE_IRQ_EN_Msk óÚ P R01_INT_PRI_RX_GOON_Pos *Ú P R01_INT_PRI_RX_GOON_Msk 1Ú P R01_INT_PRI_RST_Pos uÚ P R01_INT_PRI_RST_Msk |Ú P R01_INT_EXIT_RX_Pos uÚ P R01_INT_EXIT_RX_Msk |Ú% P R01_INT_TX_DONE_IRQ_FLAG_Pos ±Ú% P R01_INT_TX_DONE_IRQ_FLAG_Msk ¸Ú% P R01_INT_RX_DONE_IRQ_FLAG_Pos ³Ú% P R01_INT_RX_DONE_IRQ_FLAG_Msk ºÚ( P R01_INT_RX_PID_ERR_IRQ_FLAG_Pos ®Ú( P R01_INT_RX_PID_ERR_IRQ_FLAG_Msk µÚ P R01_INT_RX_CRC_ERR_Pos Ú P R01_INT_RX_CRC_ERR_Msk Ú# P R01_INT_TX_TIMEOUT_IRQ_Pos -Ú# P R01_INT_TX_TIMEOUT_IRQ_Msk 4Ú P R01_INT_TX_IRQ_Pos ÃÚ P R01_INT_TX_IRQ_Msk ÊÚ P R01_INT_RX_IRQ_Pos ÅÚ P R01_INT_RX_IRQ_Msk ÌÚ P R01_INT_IRQ_CLR_EN_Pos Ú P R01_INT_IRQ_CLR_EN_Msk Ú$ P R01_INT_RX_CRC_ERR_MASK_Pos ôÚ$ P R01_INT_RX_CRC_ERR_MASK_Msk ûÚ! P R01_INT_PID_ERR_MASK_Pos þÚ! P R01_INT_PID_ERR_MASK_Msk Ú( P R01_INT_TX_TIMEOUT_IRQ_MASK_Pos Ú( P R01_INT_TX_TIMEOUT_IRQ_MASK_Msk Ú P R01_INT_TX_IRQ_MASK_Pos .Ú P R01_INT_TX_IRQ_MASK_Msk 5Ú P R01_INT_RX_IRQ_MASK_Pos 0Ú P R01_INT_RX_IRQ_MASK_Msk 7Ú% P R01_INT_MULTI_RX_ACC_ADR_Pos ¶Ú% P R01_INT_MULTI_RX_ACC_ADR_Msk ½Ú% P R02_TMR_CTL_RX_WAIT_TIME_Pos Ú% P R02_TMR_CTL_RX_WAIT_TIME_Msk Ú( P R02_TMR_CTL_RX_WAIT_TIME_EN_Pos Ú( P R02_TMR_CTL_RX_WAIT_TIME_EN_Msk Ú, P $R02_TMR_CTL_TRX_TRANS_WAIT_TIME_Pos FÚ, P $R02_TMR_CTL_TRX_TRANS_WAIT_TIME_Msk MÚ P R03_RX_ADDR_L_L32B_Pos ÙÚ P R03_RX_ADDR_L_L32B_Msk àÚ" P R04_RX_CTL_RX_HEADER1_Pos ÅÚ" P R04_RX_CTL_RX_HEADER1_Msk ÌÚ! P R04_RX_CTL_RX_HEADER_Pos øÚ! P R04_RX_CTL_RX_HEADER_Msk ÿÚ P R04_RX_CTL_RX_FEC_Pos ÙÚ P R04_RX_CTL_RX_FEC_Msk àÚ P R04_RX_CTL_TX_FEC_Pos ×Ú P R04_RX_CTL_TX_FEC_Msk ÞÚ P R04_RX_CTL_CI_MODE_Pos Ú P R04_RX_CTL_CI_MODE_Msk ¥Ú! P R04_RX_CTL_NORMAL_M1_Pos Ú! P R04_RX_CTL_NORMAL_M1_Msk Ú$ P R04_RX_CTL_HDR_LEN_NUMB_Pos ÷Ú$ P R04_RX_CTL_HDR_LEN_NUMB_Msk þÚ% P R04_RX_CTL_HDR_LEN_EXIST_Pos Ú% P R04_RX_CTL_HDR_LEN_EXIST_Msk ¡Ú P R04_RX_CTL_M8B_Pos ïÚ P R04_RX_CTL_M8B_Msk öÚ P R05_TX_ADDR_L_L32B_Pos ÕÚ P R05_TX_ADDR_L_L32B_Msk ÜÚ" P R06_TX_CTL_RX_HEADER1_Pos ÁÚ" P R06_TX_CTL_RX_HEADER1_Msk ÈÚ! P R06_TX_CTL_RX_HEADER_Pos ôÚ! P R06_TX_CTL_RX_HEADER_Msk ûÚ% P R06_TX_CTL_MAX_LENGTH_EN_Pos ¥Ú% P R06_TX_CTL_MAX_LENGTH_EN_Msk ¬Ú& P R06_TX_CTL_WHITENING_INIT_Pos \Ú& P R06_TX_CTL_WHITENING_INIT_Msk cÚ P R06_TX_CTL_M8B_Pos ëÚ P R06_TX_CTL_M8B_Msk òÚ' P R07_SRAM_CTL_RX_START_ADDR_Pos Ú' P R07_SRAM_CTL_RX_START_ADDR_Msk Ú" P R07_SRAM_CTL_RX_READY_Pos Ú" P R07_SRAM_CTL_RX_READY_Msk ¥Ú' P R07_SRAM_CTL_TX_START_ADDR_Pos ÿÚ' P R07_SRAM_CTL_TX_START_ADDR_Msk Ú" P R07_SRAM_CTL_TX_READY_Pos Ú" P R07_SRAM_CTL_TX_READY_Msk £Ú P R0F_RX_ADDR4_M8B_Pos mÚ P R0F_RX_ADDR4_M8B_Msk tÚ P R0F_RX_ADDR3_M8B_Pos nÚ P R0F_RX_ADDR3_M8B_Msk uÚ P R0F_RX_ADDR2_M8B_Pos oÚ P R0F_RX_ADDR2_M8B_Msk vÚ P R0F_RX_ADDR1_M8B_Pos pÚ P R0F_RX_ADDR1_M8B_Msk wÚ P R10_RX_ADDR7_EN_Pos µÚ P R10_RX_ADDR7_EN_Msk ¼Ú P R10_RX_ADDR6_EN_Pos ¶Ú P R10_RX_ADDR6_EN_Msk ½Ú P R10_RX_ADDR5_EN_Pos ·Ú P R10_RX_ADDR5_EN_Msk ¾Ú P R10_RX_ADDR4_EN_Pos ¸Ú P R10_RX_ADDR4_EN_Msk ¿Ú P R10_RX_ADDR3_EN_Pos ¹Ú P R10_RX_ADDR3_EN_Msk ÀÚ P R10_RX_ADDR2_EN_Pos ºÚ P R10_RX_ADDR2_EN_Msk ÁÚ P R10_RX_ADDR1_EN_Pos »Ú P R10_RX_ADDR1_EN_Msk ÂÚ P R10_RX_ADDR0_EN_Pos ¼Ú P R10_RX_ADDR0_EN_Msk ÃÚ P R10_RX_ADDR7_M8B_Pos Ú P R10_RX_ADDR7_M8B_Msk Ú P R10_RX_ADDR6_M8B_Pos Ú P R10_RX_ADDR6_M8B_Msk Ú P R10_RX_ADDR5_M8B_Pos Ú P R10_RX_ADDR5_M8B_Msk Ú P R11_CFG_NRF_PRE_SEL_Pos [Ú P R11_CFG_NRF_PRE_SEL_Msk bÚ# P R11_CFG_RX_DATA_REV_EN_Pos cÚ# P R11_CFG_RX_DATA_REV_EN_Msk jÚ$ P R11_CFG_PRE_SYNC_12B_EN_Pos IÚ$ P R11_CFG_PRE_SYNC_12B_EN_Msk PÚ# P R11_CFG_PRE_SYNC_8B_EN_Pos vÚ# P R11_CFG_PRE_SYNC_8B_EN_Msk }Ú# P R11_CFG_PRE_SYNC_4B_EN_Pos zÚ# P R11_CFG_PRE_SYNC_4B_EN_Msk Ú P R11_CFG_PRE_SYNC_EN_Pos UÚ P R11_CFG_PRE_SYNC_EN_Msk \Ú! P R11_CFG_250K_MODE_EN_Pos pÚ! P R11_CFG_250K_MODE_EN_Msk wÚ" P R11_CFG_B250K_PRE_SEL_Pos Ú" P R11_CFG_B250K_PRE_SEL_Msk Ú P R11_CFG_LQI_EN_Pos üÚ P R11_CFG_LQI_EN_Msk Ú" P R11_CFG_RX_PID_MANUAL_Pos ÃÚ" P R11_CFG_RX_PID_MANUAL_Msk ÊÚ" P R11_CFG_TX_PID_MANUAL_Pos ÁÚ" P R11_CFG_TX_PID_MANUAL_Msk ÈÚ# P R11_CFG_PREAM_2BYTE_EN_Pos Ú# P R11_CFG_PREAM_2BYTE_EN_Msk Ú$ P R11_CFG_B250K_INVERT_EN_Pos uÚ$ P R11_CFG_B250K_INVERT_EN_Msk |Ú) P !R11_CFG_B250K_SCR_INIT_VALUE_Pos ÞÚ) P !R11_CFG_B250K_SCR_INIT_VALUE_Msk åÚ P R11_CFG_B250K_PREAM_Pos ÒÚ P R11_CFG_B250K_PREAM_Msk ÙÚ P R11_CFG_B250K_MODE_Pos $Ú P R11_CFG_B250K_MODE_Msk +Ú! P R11_CFG_ADDR_ERR_THR_Pos Ú! P R11_CFG_ADDR_ERR_THR_Msk Ú" P R11_CFG_PID_MANUAL_EN_Pos ÚÚ" P R11_CFG_PID_MANUAL_EN_Msk áÚ! P R11_CFG_ADDR_SCR_DIS_Pos 'Ú! P R11_CFG_ADDR_SCR_DIS_Msk .Ú P CR_BASE ®Ú P
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SRAM_BASE Ú P AHB1_PERIPH_BASE Ú P APB1_PERIPH_BASE Ú P APB2_PERIPH_BASE Ú P BLE_PERIPH_BASE 9Ú P
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I2C0_BASE QÚ P
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SPI0_BASE #Ú P UART0_BASE ÑÚ P PWM_BASE MÚ P ADC_BASE yÚ P WDT_BASE RÚ P
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WWDT_BASE ùÚ P TIMER0_BASE Ú P
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SPI1_BASE "Ú P UART1_BASE ÐÚ P TIMER1_BASE Ú P TIMER2_BASE Ú P
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TRIM_BASE Ú P
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GPIO_BASE Ú P P0_BASE ÃÚ P P1_BASE ÂÚ P P2_BASE ÁÚ P P3_BASE ÀÚ P GPIO_DBNCECON_BASE cÚ P GPIOBIT0_BASE ùÚ P GPIOBIT1_BASE øÚ P GPIOBIT2_BASE ÷Ú P GPIOBIT3_BASE öÚ P SYS_BASE BÚ P CLK_BASE gÚ P FLCTL_BASE ÈÚ P FLCTL_BASE1 Ú P DMA_BASE oÚ P ANA_BASE qÚ P EFUSE_BASE ÅÚ P USB_BASE WÚ P USBDMA_BASE Ú P PRI_RF_BASE YÚ P CR 2Ú P I2C0 ÕÚ P SPI0 §Ú P UART0 UÚ P PWM ÑÚ P ADC ýÚ P WDT ÖÚ P WWDT }Ú P TIMER0 Ú P SPI1 ¦Ú P UART1 TÚ P TIMER1 Ú P TIMER2 Ú P TRIM Ú P GPIO Ú P P0 GÚ P P1 FÚ P P2 EÚ P P3 DÚ P GPIO_DB ©Ú P SYS ÆÚ P CLK ëÚ P FLCTL LÚ P FLCTL_BUFF ÀÚ P DMA óÚ P ANA õÚ P EFUSE IÚ P USB ÛÚ P USBDMA Ú P PRI_RF ÝÚ P __ZEPHYR__ WÚ P TRUE Ú P FALSE VÚ P BIT0 ´Ú P BIT1 ³Ú P BIT2 ²Ú P BIT3 ±Ú P BIT4 °Ú P BIT5 ¯Ú P BIT6 ®Ú P BIT7 Ú P BIT8 ¬Ú P BIT9 «Ú P BIT10 Ú P BIT11 Ú P BIT12 Ú P BIT13 ~Ú P BIT14 }Ú P BIT15 |Ú P BIT16 {Ú P BIT17 zÚ P BIT18 yÚ P BIT19 xÚ P BIT20 Ú P BIT21 Ú P BIT22 ~Ú P BIT23 }Ú P BIT24 |Ú P BIT25 {Ú P BIT26 zÚ P BIT27 yÚ P BIT28 xÚ P BIT29 wÚ P BIT30 Ú P BIT31 ~Ú P BIT æÚ P
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BYTE0_Msk ËÚ P
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BYTE1_Msk ÊÚ P
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BYTE2_Msk ÉÚ P
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BYTE3_Msk ÈÚ P
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GET_BYTE0 Ú P
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GET_BYTE1 Ú P
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GET_BYTE2 Ú P
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GET_BYTE3 Ú P SET_BIT Ú P
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CLEAR_BIT Ú P READ_BIT aÚ P
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CLEAR_REG Ú P
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WRITE_REG ñÚ P READ_REG bÚ P MODIFY_REG ²Ú P USE_FULL_ASSERT ûÚ P assert_param ±Ú P FREQ_RCL MÚ P FREQ_XTL 6Ú NVIC_SystemReset ½Ú P __PAN_SYS_LOG_H__ Ú P DBG_ON öÚ P INFO_ON Ú P WARN_ON Ú P ERR_ON ÚÚ P TEST_ON Ú P
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ASSERT_ON ëÚ P
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SYS_ABORT ãÚ P LOG ãÚ P SYS_DBG Ú P SYS_INFO 1Ú P SYS_WARN %Ú P SYS_TEST Ú P SYS_ERR vÚ P SYS_ASSERT Ú , file )Ú ,
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line /Ú SYS_AssertError ðÚ P __PAN_SYS_H__ QÚ P SYS_MFP_TYPE_Msk ?Ú P SYS_MFP_ALT_Msk ¢Ú P SYS_MFP_MFP_Msk Ú P SYS_MFP_GPIO äÚ P SYS_MFP_P00_GPIO ÍÚ P SYS_MFP_P00_SWD_CLK ÏÚ P SYS_MFP_P00_UART1_RX ~Ú P SYS_MFP_P00_I2C0_SCL ÅÚ P SYS_MFP_P00_SPI0_CLK Ú P SYS_MFP_P00_LL_DBG_14 jÚ P SYS_MFP_P00_MDM_DBG_11 %Ú P SYS_MFP_P00_RESERVED Ú P SYS_MFP_P00_Msk ÓÚ P SYS_MFP_P01_GPIO ÌÚ P SYS_MFP_P01_SWD_DAT ÏÚ P SYS_MFP_P01_UART1_TX {Ú P SYS_MFP_P01_I2C0_SDA ÎÚ P SYS_MFP_P01_SPI0_CS äÚ P SYS_MFP_P01_LL_DBG_15 hÚ P SYS_MFP_P01_MDM_DBG_12 #Ú P SYS_MFP_P01_RESERVED Ú P SYS_MFP_P01_Msk ÒÚ P SYS_MFP_P02_GPIO ËÚ P SYS_MFP_P02_UART0_CTS ;Ú P SYS_MFP_P02_SPI1_MISO <Ú P SYS_MFP_P02_PWM_CH3 ãÚ P SYS_MFP_P02_UART1_CTS :Ú P SYS_MFP_P02_LL_DBG_8 Ú P SYS_MFP_P02_MDM_DBG_19 Ú P SYS_MFP_P02_RESERVED Ú P SYS_MFP_P02_Msk ÑÚ P SYS_MFP_P03_GPIO ÊÚ P SYS_MFP_P03_UART0_CTS :Ú P SYS_MFP_P03_SPI0_CS âÚ P SYS_MFP_P03_PWM_CH2 ãÚ# P SYS_MFP_P03_TIMER0_CNT_OUT Ú P SYS_MFP_P03_LL_DBG_8 Ú P SYS_MFP_P03_MDM_DBG_5 QÚ P SYS_MFP_P03_RESERVED Ú P SYS_MFP_P03_Msk ÐÚ P SYS_MFP_P04_GPIO ÉÚ P SYS_MFP_P04_UART0_RTS *Ú P SYS_MFP_P04_SPI0_CLK Ú P SYS_MFP_P04_PWM_CH3 áÚ P SYS_MFP_P04_TIMER0_EXT ëÚ P SYS_MFP_P04_LL_DBG_9 Ú P SYS_MFP_P04_MDM_DBG_6 OÚ P SYS_MFP_P04_RESERVED Ú P SYS_MFP_P04_Msk ÏÚ P SYS_MFP_P05_GPIO ÈÚ P SYS_MFP_P05_UART0_TX xÚ P SYS_MFP_P05_SPI0_MISO :Ú P SYS_MFP_P05_PWM_CH4 ßÚ P SYS_MFP_P05_EXT_STADC .Ú P SYS_MFP_P05_LL_DBG_12 gÚ P SYS_MFP_P05_MDM_DBG_9 KÚ P SYS_MFP_P05_RESERVED Ú P SYS_MFP_P05_Msk ÎÚ P SYS_MFP_P06_GPIO ÇÚ P SYS_MFP_P06_UART0_RX yÚ P SYS_MFP_P06_SPI0_MISO 9Ú P SYS_MFP_P06_PWM_CH5 ÝÚ P SYS_MFP_P06_TIMER1_EXT èÚ P SYS_MFP_P06_LL_DBG_13 eÚ P SYS_MFP_P06_MDM_DBG_3 PÚ P SYS_MFP_P06_AHB_CLK ìÚ P SYS_MFP_P06_Msk ÍÚ P SYS_MFP_P07_GPIO ÆÚ P SYS_MFP_P07_UART1_RX wÚ P SYS_MFP_P07_I2C0_SCL ¾Ú P SYS_MFP_P07_SPI0_MOSI 8Ú P SYS_MFP_P07_PWM_CH0 áÚ P SYS_MFP_P07_LL_DBG_10 gÚ P SYS_MFP_P07_MDM_DBG_7 KÚ P SYS_MFP_P07_RESERVED Ú P SYS_MFP_P07_Msk ÌÚ P SYS_MFP_P10_GPIO ÌÚ P SYS_MFP_P10_UART1_TX {Ú P SYS_MFP_P10_I2C0_SDA ÎÚ P SYS_MFP_P10_SPI0_MISO >Ú P SYS_MFP_P10_PWM_CH5 âÚ P SYS_MFP_P10_LL_DBG_11 lÚ P SYS_MFP_P10_MDM_DBG_8 PÚ P SYS_MFP_P10_RESERVED Ú P SYS_MFP_P10_Msk ÒÚ P SYS_MFP_P11_GPIO ËÚ P SYS_MFP_P11_UART1_RTS +Ú P SYS_MFP_P11_SPI0_MOSI =Ú P SYS_MFP_P11_PWM_CH7 ßÚ P SYS_MFP_P11_CLK_32K Ú P SYS_MFP_P11_LL_DBG_9 Ú P SYS_MFP_P11_MDM_DBG_0 WÚ P SYS_MFP_P11_UART0_TX {Ú P SYS_MFP_P11_Msk ÑÚ P SYS_MFP_P12_GPIO ÊÚ P SYS_MFP_P12_UART0_RX |Ú P SYS_MFP_P12_PWM_CH4 áÚ# P SYS_MFP_P12_TIMER0_CNT_OUT Ú P SYS_MFP_P12_UART1_TX yÚ P SYS_MFP_P12_LL_DBG_4 Ú P SYS_MFP_P12_MDM_DBG_17 Ú P SYS_MFP_P12_SPI0_MISO <Ú P SYS_MFP_P12_Msk ÐÚ P SYS_MFP_P13_GPIO ÉÚ P SYS_MFP_P13_UART0_RTS *Ú P SYS_MFP_P13_I2C0_SDA ËÚ P SYS_MFP_P13_PWM_CH3 áÚ P SYS_MFP_P13_LL_DBG_3 Ú P SYS_MFP_P13_MDM_DBG_16 Ú P SYS_MFP_P13_SPI1_CS àÚ P SYS_MFP_P13_SPI0_CS áÚ P SYS_MFP_P13_Msk ÏÚ P SYS_MFP_P14_GPIO ÈÚ P SYS_MFP_P14_UART0_CTS 8Ú P SYS_MFP_P14_I2C0_SCL ÀÚ P SYS_MFP_P14_PWM_CH2 áÚ P SYS_MFP_P14_LL_DEBUG_2 üÚ P SYS_MFP_P14_MDM_DBG_15 Ú P SYS_MFP_P14_SPI0_CLK Ú P SYS_MFP_P14_RESERVED Ú P SYS_MFP_P14_Msk ÎÚ P SYS_MFP_P15_GPIO ÇÚ P SYS_MFP_P15_SPI0_CS ßÚ P SYS_MFP_P15_PWM_CH5 ÝÚ P SYS_MFP_P15_TIMER0_EXT éÚ P SYS_MFP_P15_UART0_RX yÚ P SYS_MFP_P15_LL_DBG_5 Ú P SYS_MFP_P15_MDM_DBG_18 Ú P SYS_MFP_P15_RESERVED Ú P SYS_MFP_P15_Msk ÍÚ P SYS_MFP_P16_GPIO ÆÚ P SYS_MFP_P16_UART0_TX vÚ# P SYS_MFP_P16_TIMER2_CNT_OUT Ú P SYS_MFP_P16_PWM_CH0 áÚ P SYS_MFP_P16_LL_DBG_0 Ú P SYS_MFP_P16_MDM_DBG_13 Ú P SYS_MFP_P16_SPI1_CLK Ú P SYS_MFP_P16_I2C0_SCL ¾Ú P SYS_MFP_P16_Msk ÌÚ P SYS_MFP_P17_GPIO ÅÚ P SYS_MFP_P17_UART0_RX wÚ P SYS_MFP_P17_TIMER2_EXT åÚ P SYS_MFP_P17_PWM_CH1 ßÚ P SYS_MFP_P17_LL_DBG_1 Ú P SYS_MFP_P17_MDM_DBG_14 Ú P SYS_MFP_P17_RCH Ú P SYS_MFP_P17_RESERVED Ú P SYS_MFP_P17_Msk ËÚ P SYS_MFP_P20_GPIO ËÚ P SYS_MFP_P20_SPI1_MISO <Ú P SYS_MFP_P20_PWM_CH6 àÚ P SYS_MFP_P20_TADC_CLK Ú P SYS_MFP_P20_LL_DBG_6 Ú P SYS_MFP_P20_MDM_DBG_2 UÚ P SYS_MFP_P20_XTL_C1_CLK êÚ P SYS_MFP_P20_RESERVED Ú P SYS_MFP_P20_Msk ÑÚ P SYS_MFP_P21_GPIO ÊÚ P SYS_MFP_P21_SPI1_MOSI ;Ú P SYS_MFP_P21_PWM_CH7 ÞÚ P SYS_MFP_P21_TADC_VLD Ú P SYS_MFP_P21_LL_DBG_7 Ú P SYS_MFP_P21_MDM_DBG_1 UÚ P SYS_MFP_P21_XTL_C2_CLK èÚ P SYS_MFP_P21_RESERVED Ú P SYS_MFP_P21_Msk ÐÚ P SYS_MFP_P22_GPIO ÉÚ P SYS_MFP_P22_SPI1_CLK Ú P SYS_MFP_P22_PWM_CH0 äÚ P SYS_MFP_P22_RESERVED Ú P SYS_MFP_P22_TADC_DATl .Ú P SYS_MFP_P22_MDM_DBG_0 UÚ P SYS_MFP_P22_SPI0_MOSI ;Ú P SYS_MFP_P22_RESERVED1 ]Ú P SYS_MFP_P22_Msk ÏÚ P SYS_MFP_P23_GPIO ÈÚ P SYS_MFP_P23_SPI1_CS ßÚ P SYS_MFP_P23_PWM_CH1 âÚ P SYS_MFP_P23_DPLL_DIV8 GÚ P SYS_MFP_P23_TADC_DATH QÚ P SYS_MFP_P23_MDM_DBG_10 !Ú P SYS_MFP_P23_I2C0_SCL ÀÚ P SYS_MFP_P23_RESERVED Ú P SYS_MFP_P23_Msk ÎÚ P SYS_MFP_P24_GPIO ÇÚ P SYS_MFP_P24_SPI1_MISO 8Ú P SYS_MFP_P24_UART1_RX xÚ P SYS_MFP_P24_PWM_CH2 àÚ# P SYS_MFP_P24_TIMER1_CNT_OUT Ú P SYS_MFP_P24_MDM_DBG_4 OÚ P SYS_MFP_P24_RESERVED Ú P SYS_MFP_P24_RESERVED1 [Ú P SYS_MFP_P24_Msk ÍÚ P SYS_MFP_P25_GPIO ÆÚ P SYS_MFP_P25_SPI1_MOSI 7Ú P SYS_MFP_P25_UART1_TX uÚ P SYS_MFP_P25_PWM_CH3 ÞÚ P SYS_MFP_P25_MDM_DBG_5 MÚ P SYS_MFP_P25_RESERVED Ú P SYS_MFP_P25_I2C0_SDA ÈÚ P SYS_MFP_P25_RESERVED1 ZÚ P SYS_MFP_P25_Msk ÌÚ P SYS_MFP_P26_GPIO ÅÚ P SYS_MFP_P26_UART1_RTS %Ú P SYS_MFP_P26_PWM_CH4 ÜÚ P SYS_MFP_P26_SPI1_CS ÜÚ P SYS_MFP_P26_MDM_DBG_4 MÚ P SYS_MFP_P26_MDM_DBG_10 Ú P SYS_MFP_P26_RESERVED Ú P SYS_MFP_P26_RESERVED1 YÚ P SYS_MFP_P26_Msk ËÚ P SYS_MFP_P27_GPIO ÄÚ P SYS_MFP_P27_UART1_CTS 3Ú P SYS_MFP_P27_PWM_CH5 ÚÚ P SYS_MFP_P27_SPI1_CLK Ú P SYS_MFP_P27_RESERVED Ú P SYS_MFP_P27_MDM_DBG_20 Ú P SYS_MFP_P27_XTH Ú P SYS_MFP_P27_RESERVED1 XÚ P SYS_MFP_P27_Msk ÊÚ P SYS_MFP_P30_GPIO ÊÚ P SYS_MFP_P30_UART1_RX {Ú P SYS_MFP_P30_PWM_CH6 ßÚ P SYS_MFP_P30_SPI1_MISO ;Ú P SYS_MFP_P30_MDM_DBG_10 #Ú P SYS_MFP_P30_RESERVED Ú P SYS_MFP_P30_RESERVED1 ^Ú P SYS_MFP_P30_RESERVED2 ]Ú P SYS_MFP_P30_Msk ÐÚ P SYS_MFP_P31_GPIO ÉÚ P SYS_MFP_P31_UART1_TX xÚ P SYS_MFP_P31_PWM_CH7 ÝÚ P SYS_MFP_P31_SPI1_MOSI :Ú P SYS_MFP_P31_RESERVED Ú P SYS_MFP_P31_RESERVED1 ]Ú P SYS_MFP_P31_RESERVED2 \Ú P SYS_MFP_P31_RESERVED3 [Ú P SYS_MFP_P31_Msk ÏÚ P SYS_SET_MFP )Ú SYS_UnlockReg òÚ SYS_LockReg ÙÚ SYS_IsRegLocked @Ú ,
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u32NopCnt ¡Ú SYS_delay_10nop PÚ P __PAN_CLK_H__ vÚ$ P CLK_APB1_WDTSEL_MILLI_PULSE hÚ P CLK_APB1_WDTSEL_RCL32K @Ú% P CLK_APB1_WWDTSEL_MILLI_PULSE Ú P CLK_APB1_WWDTSEL_RCL32K çÚ! P CLK_APB1_TMR0SEL_APB1CLK »Ú P CLK_APB1_TMR0SEL_RCL32K
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Ú P CLK_APB1_TMR0SEL_TM0 ÐÚ! P CLK_APB2_TMR1SEL_APB2CLK ¸Ú P CLK_APB2_TMR1SEL_RCL32K Ú P CLK_APB2_TMR1SEL_TM1 ÍÚ! P CLK_APB2_TMR2SEL_APB2CLK ·Ú P CLK_APB2_TMR2SEL_RCL32K Ú P CLK_APB2_TMR2SEL_TM2 ËÚ" P CLK_APB1_PWM_CH01_SEL_APB IÚ% P CLK_APB1_PWM_CH01_SEL_CLK32K Ú" P CLK_APB1_PWM_CH23_SEL_APB EÚ% P CLK_APB1_PWM_CH23_SEL_CLK32K Ú" P CLK_APB1_PWM_CH45_SEL_APB AÚ% P CLK_APB1_PWM_CH45_SEL_CLK32K Ú" P CLK_APB1_PWM_CH67_SEL_APB =Ú% P CLK_APB1_PWM_CH67_SEL_CLK32K Ú P
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FREQ_1MHZ Ú P
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FREQ_8MHZ Ú P FREQ_16MHZ ÔÚ P FREQ_25MHZ ÔÚ P FREQ_32MHZ ÖÚ P FREQ_48MHZ ÏÚ P FREQ_64MHZ ÑÚ P FREQ_96MHZ ÌÚ P FREQ_50MHZ ÖÚ P FREQ_72MHZ ÒÚ P FREQ_100MHZ ¨Ú P CLK_SYS_SRCSEL_RCH Ú P CLK_SYS_SRCSEL_XTH ñÚ P CLK_SYS_SRCSEL_DPLL ·Ú P CLK_DPLL_REF_CLKSEL_RCH £Ú P CLK_DPLL_REF_CLKSEL_XTH Ú P CLK_DPLL_OUT_48M ×Ú P CLK_DPLL_OUT_64M ÙÚ P CLK_APB1Periph_I2C0 ³Ú P CLK_APB1Periph_SPI0
Ú P CLK_APB1Periph_UART0 3Ú! P CLK_APB1Periph_PWM0_CH01 (Ú! P CLK_APB1Periph_PWM0_CH23 $Ú! P CLK_APB1Periph_PWM0_CH45 Ú! P CLK_APB1Periph_PWM0_CH67 Ú P CLK_APB1Periph_PWM0_EN
Ú P CLK_APB1Periph_ADC ÛÚ P CLK_APB1Periph_WDT ´Ú P CLK_APB1Periph_WWDT [Ú P CLK_APB1Periph_TMR0 ~Ú P CLK_APB1Periph_MILI_CLK 5Ú P CLK_APB1Periph_All Ú P CLK_APB2Periph_SPI1 Ú P CLK_APB2Periph_UART1 1Ú P CLK_APB2Periph_TMR1 |Ú P CLK_APB2Periph_TMR2 {Ú P CLK_APB2Periph_All Ú P CLK_AHBPeriph_DMAC ÇÚ P CLK_AHBPeriph_GPIO Ú P CLK_AHBPeriph_SYSTICK ¬Ú P CLK_AHBPeriph_APB1 ØÚ P CLK_AHBPeriph_APB2 ×Ú P CLK_AHBPeriph_AHB Ú P CLK_AHBPeriph_BLE_32M òÚ P CLK_AHBPeriph_BLE_32K ôÚ P CLK_AHBPeriph_ROM ðÚ P CLK_AHBPeriph_EFUSE bÚ P CLK_AHBPeriph_USB_AHB ÂÚ P CLK_AHBPeriph_USB_48M ÔÚ P CLK_AHBPeriph_All ÅÚ P CLK_DivideSource_Ahb :Ú P CLK_DivideSource_Apb1 ÿÚ P CLK_DivideSource_Apb2 þÚ P CLK_RCL_SELECT vÚ P CLK_RCH_SELECT zÚ P CLK_XTL_SELECT _Ú P CLK_XTH_SELECT cÚ P CLK_DPLL_SELECT )Ú P CLK_STABLE_STATUS_Pos ÙÚ P CLK_STABLE_STATUS_Msk àÚ! P CLKTRIM_CALC_CLK_SEL_32K Ú! P CLKTRIM_CALC_CLK_SEL_32M Ú! P CLKTRIM_QDEC_CLK_SEL_APB [Ú! P CLKTRIM_QDEC_CLK_SEL_32K ~Ú" P CLKTRIM_KSCAN_CLK_SEL_APB Ú" P CLKTRIM_KSCAN_CLK_SEL_32K )Ú P DMA_RST Ú P LL_RST ÏÚ P
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EFUSE_RST éÚ P USB_RST {Ú P MDMSTB_RST Ú P MDM_RST Ú P I2C0_RST uÚ P SPI0_RST GÚ P SPI1_RST FÚ P
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UART0_RST õÚ P
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UART1_RST ôÚ P PWM0_RST ?Ú P ADC_RST Ú P WDT_RST vÚ P WWDT_RST Ú P TMR0_RST @Ú P TMR1_RST ?Ú P TMR2_RST >Ú P GPIO_RST 4Ú P CLKTRIM_RST GÚ P CLK_BODCTL_BOD_INT_EN @Ú P CLK_BODCTL_BOD_RST_EN 2Ú P CLK_BODCTL_BODSEL_1_75V ãÚ P CLK_BODCTL_BODSEL_1_95V áÚ P CLK_BODCTL_BODSEL_2_15V èÚ P CLK_BODCTL_BODSEL_2_35V æÚ P CLK_BODCTL_BODSEL_2_55V äÚ P CLK_BODCTL_BODSEL_2_75V âÚ P CLK_BODCTL_BODSEL_2_95V àÚ# P CLK_BLDBCTL_BODDBSEL_2POW0 Ú# P CLK_BLDBCTL_BODDBSEL_2POW1 Ú# P CLK_BLDBCTL_BODDBSEL_2POW2 Ú# P CLK_BLDBCTL_BODDBSEL_2POW3 Ú# P CLK_BLDBCTL_BODDBSEL_2POW4 Ú# P CLK_BLDBCTL_BODDBSEL_2POW5 Ú# P CLK_BLDBCTL_LVRDBSEL_2POW0 óÚ# P CLK_BLDBCTL_LVRDBSEL_2POW1 òÚ# P CLK_BLDBCTL_LVRDBSEL_2POW2 ñÚ# P CLK_BLDBCTL_LVRDBSEL_2POW3 ðÚ# P CLK_BLDBCTL_LVRDBSEL_2POW4 ïÚ# P CLK_BLDBCTL_LVRDBSEL_2POW5 îÚ CLK_XthStartupConfig Ú CLK_HCLKConfig 'Ú ,
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" þ&
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u32ClkDiv pÚ CLK_PCLK1Config ìÚ ,
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" '
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u32ClkDiv íÚ CLK_PCLK2Config ëÚ ,
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" '
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u32ClkDiv ëÚ CLK_SetDpllOutputFreq ºÚ ,
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" 'freq \Ú CLK_EnableClkTrim Ú ,"" ' NewState ÀÚ CLK_SelectClkTrimSrc UÚ ,
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" 'src ÀÚ CLK_SetClkTrimCalClkDiv ^Ú ," 'div ÁÚ
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" 'reg ìÚ CLK_FLASH_CLKDIV_1 Ú CLK_FLASH_CLKDIV_2
Ú CLK_FLASH_CLKDIV_4 Ú CLK_FLASH_CLKDIV_8 Ú CLK_FLASH_CLKDIV_16 NÚ CLK_FLASH_CLKDIV_32 PÚ CLK_SetFlashClkDiv @Ú ," 'div ÁÚ
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" 'reg ãÚ CLK_GetHCLKFreq ÁÚ CLK_GetCPUFreq ýÚ CLK_GetPCLK1Freq Ú CLK_GetPCLK2Freq
Ú ,
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u32ClkSrc ±Ú CLK_RefClkSrcConfig ÔÚ ,
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u32ClkSrc ±Ú ,
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freq_out jÚ CLK_SYSCLKConfig `Ú ,
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u32ClkDiv ¶Ú ,
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u32ClkDiv ¶Ú ,
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u32ClkDiv ¶Ú ,
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CLK_AHBPeriph YÚ ," NewState Ú CLK_AHBPeriphClockCmd RÚ ,
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CLK_APB1Periph Ú ," NewState Ú CLK_APB1PeriphClockCmd Ú ,
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CLK_APB2Periph Ú ," NewState Ú CLK_APB2PeriphClockCmd Ú ,
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u32ClkMask KÚ CLK_WaitClockReady Ú CLK_Wait3vSyncReady ¹Ú CLK_Set3vSyncAuto Ú ,
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u32clksel uÚ CLK_SetWdtClkSrc òÚ ,
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u32clksel uÚ CLK_SetWwdtClkSrc yÚ , timer ¦Ú ,
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u32clksel uÚ CLK_SetTmrClkSrc îÚ ,
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u32ChNum Ú ,
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u32clksel uÚ CLK_SetPwmClkSrc íÚ , Peripheral ±Ú CLK_GetPeripheralFreq ËÚ CLK_ResetChip Ú! CLK_ResetSystemToRomMode Ú ,
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u32ModuleIndex Ú CLK_ResetModule (Ú , i32Mode Ú ,
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u32BODLevel "Ú CLK_ConfigureBOD Ú CLK_EnableBOD yÚ CLK_DisableBOD
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Ú CLK_GetBODStatus Ú CLK_GetBODIntFlag óÚ CLK_ClearBODIntFlag (Ú ,
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u32BodDBTime ÃÚ CLK_SetBODDebounceTime ÎÚ CLK_EnableLVR ZÚ CLK_DisableLVR ëÚ ,
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u32LvrDBTime ¤Ú CLK_SetLVRDebounceTime ¯Ú P __PAN_ADC_H__ Ú P ADC_INPUTRANGE_HIGH Ú P ADC_INPUTRANGE_LOW 2Ú P ADC_CH8_EXT {Ú P ADC_CH8_BGP Ú P ADC_CMP0_LESS_THAN PÚ P ADC_CMP1_LESS_THAN OÚ% P ADC_CMP0_GREATER_OR_EQUAL_TO Ú% P ADC_CMP1_GREATER_OR_EQUAL_TO Ú P ADC_TRIGGER_BY_EXT_PIN ÔÚ P ADC_TRIGGER_BY_PWM Ú! P ADC_FALLING_EDGE_TRIGGER Ú P ADC_RISING_EDGE_TRIGGER ÃÚ P ADC_ADIF_INT .Ú P ADC_CMP0_INT 2Ú P ADC_CMP1_INT 1Ú P ADC_FIFO_FULL_INT Ú P ADC_FIFO_EMPTY_INT $Ú P ADC_FIFO_OVER_INT yÚ P ADC_FIFO_HALF_INT Ú P ADC_SAMPLE_CLOCK_0 dÚ P ADC_SAMPLE_CLOCK_1 cÚ P ADC_SAMPLE_CLOCK_2 bÚ P ADC_SAMPLE_CLOCK_4 `Ú P ADC_SAMPLE_CLOCK_8 \Ú P ADC_SAMPLE_CLOCK_16 +Ú P ADC_SAMPLE_CLOCK_32 -Ú P ADC_SAMPLE_CLOCK_64 (Ú P ADC_SAMPLE_CLOCK_128 õÚ P ADC_SAMPLE_CLOCK_256 óÚ P ADC_SAMPLE_CLOCK_512 øÚ P ADC_SAMPLE_CLOCK_1024 ÇÚ! P ADC_SEQMODE_TYPE_23SHUNT oÚ P ADC_SEQMODE_TYPE_1SHUNT ¥Ú$ P ADC_SEQMODE_MODESELECT_CH01 ÑÚ$ P ADC_SEQMODE_MODESELECT_CH12 ÏÚ$ P ADC_SEQMODE_MODESELECT_CH02 ÐÚ# P ADC_SEQMODE_MODESELECT_ONE ÝÚ P ADC_SEQMODE_PWM0_RISING ºÚ P ADC_SEQMODE_PWM0_CENTER ÅÚ! P ADC_SEQMODE_PWM0_FALLING Ú P ADC_SEQMODE_PWM0_PERIOD ÃÚ P ADC_SEQMODE_PWM2_RISING ¸Ú P ADC_SEQMODE_PWM2_CENTER ÃÚ! P ADC_SEQMODE_PWM2_FALLING
Ú P ADC_SEQMODE_PWM2_PERIOD ÁÚ P ADC_SEQMODE_PWM4_RISING ¶Ú P ADC_SEQMODE_PWM4_CENTER ÁÚ! P ADC_SEQMODE_PWM4_FALLING Ú P ADC_SEQMODE_PWM4_PERIOD ¿Ú P ADC_SEQMODE_PWM6_RISING ´Ú P ADC_SEQMODE_PWM6_CENTER ¿Ú! P ADC_SEQMODE_PWM6_FALLING Ú P ADC_SEQMODE_PWM6_PERIOD ½Ú P ADC_COMPARATOR_0 ýÚ P ADC_COMPARATOR_1 üÚ! P ADC_FIFO_TRIG_LEVEL_HALF jÚ! P ADC_FIFO_TRIG_LEVEL_FULL RÚ 8
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<unnamed> QÚ " (
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chip_info `Ú " ( ft_version ÎÚ " (
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adc_vdd_b Ú " (
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adc_vdd_k wÚ " (
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adc_vbg_k vÚ " (
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adc_vbg_b Ú " (adc_temp_volt Ú " (current_temp_value bÚ " (adc_vbg_1v20_trim ¶Ú " (
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rsvd_0x30 æÚ <" ( adc_vbg_kb ÊÚ " ( adc_vbat_k Ú " ( adc_vbat_b Ú " (adc_vbat_dtemp_k Ú " (adc_vbat_dtemp_b Ú " ( adc_temp_k õÚ
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" (
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adc_ctrl2 Ú
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" ( adc_extsmpt hÚ
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ADC_OPT_T "Ú @
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m_adc_opt õÚ
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global_calc_vbat_mv $Ú , opt xÚ ADC_SetCalirationParams ýÚ ADC_GetConversionData ãÚ ," (ADCx Ú ADC_StatusFlag ³Ú ," ¡(ADCx Ú ,
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" ¡(IntMask /Ú ADC_ClearStatusFlag ÂÚ ," ¤(ADCx Ú ,
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" ¤(IntMask ,Ú ADC_IntMask Ú ," §(ADCx Ú ,
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" §(IntMask )Ú ,"" §( NewState Ú ADC_IsIntOccured Ú ," «(ADCx Ú ,
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" «(IntMask %Ú ADC_ClearIntFlag !Ú ," ®(ADCx Ú ,
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" ®(IntMask "Ú ADC_IsBusy ZÚ ," ±(ADCx Ú ADC_IsDataOverrun Ú ," ³(ADCx Ú ADC_IsDataValid Ú ," µ(ADCx Ú ADC_PowerDown Ú ," ·(ADCx Ú ADC_PowerOn íÚ ," ¹(ADCx Ú" ADC_SequentialModeDisable GÚ ," »(ADCx Ú ADC_Trigger2Select CÚ ," ½(ADCx Ú ,"" ½( NewState Ú ADC_DisableCompare0 üÚ ," À(ADCx Ú ADC_DisableCompare1 ûÚ ," Â(ADCx }Ú ADC_StartConvert ¾Ú ," Ä(ADCx {Ú ADC_StopConvert (Ú ," Æ(ADCx yÚ ADC_TestModeEnable =Ú ," È(ADCx wÚ ADC_TestModeDisable ÎÚ ," Ê(ADCx uÚ ADC_DmaModeEnable ÍÚ ," Ì(ADCx sÚ ,"" Ì( NewState yÚ ADC_SetClockDivider ÈÚ ," Ï(ADCx pÚ ,
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" Ï(Divider ñÚ ADC_Open +Ú ," Ò(ADCx mÚ ,
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" Ò(ChMask Ú ADC_SelInputRange Ú ," Õ(ADCx jÚ ,
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" Õ( EnableHigh åÚ ADC_TriggerDelay êÚ ," Ø(ADCx gÚ ,
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" Ø(Data ;Ú ADC_SetExtraSampleTime Ú ," Û(ADCx dÚ ,
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" Û( SampleTime µÚ ADC_IsOneChConvertEnd "Ú ," Þ(ADCx aÚ ADC_ClearByHw RÚ ," à(ADCx _Ú ,"" à( NewState eÚ ADC_LeftShiftEn sÚ ," ã(ADCx \Ú ,"" ã( NewState bÚ ADC_SubtractBiasEn /Ú ," æ(ADCx YÚ ,"" æ( NewState _Ú ADC_SetBiasData Ú ," é(ADCx VÚ ,
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" é( BiasData £Ú ADC_SetFifoTrigLevel gÚ ," ì(ADCx SÚ ," ì(Level ®Ú ADC_SeqModeOneChEn {Ú ," ï(ADCx PÚ ,"" ï( NewState VÚ , ADCx Ú , buf_en kÚ ADC_Init Ú , ADCx Ú ADC_PrepareVbgCalibData PÚ , ADCx Ú ,
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adc_code Ú ADC_OutputVoltage <Ú , ADCx Ú , sample_buf Ú ,
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sample_cnt ¥Ú ,
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trim_cnt oÚ! ADC_SamplingCodeTrimMean ¾Ú , ADCx Ú" ADC_MeasureSocTemperature
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Ú , ADCx Ú& ADC_MeasureSocTemperatureFast tÚ , ADCx Ú ADC_MeasureSocVbat Ú , ADCx Ú ADC_Disable ÷Ú
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ADC_Close ¹Ú , ADCx Ú ,
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Source bÚ ,
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Param äÚ ADC_EnableHWTrigger áÚ , ADCx Ú ADC_DisableHWTrigger rÚ , ADCx Ú ,
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Mask KÚ ADC_EnableInt 5Ú , ADCx Ú ,
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Mask KÚ ADC_DisableInt ÆÚ , ADCx Ú ,
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SeqTYPE fÚ ,
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ModeSel (Ú ADC_SeqModeEnable ªÚ , ADCx Ú ,
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SeqModeTriSrc ÀÚ ADC_SeqModeTriggerSrc íÚ , ADCx Ú ,
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ChNum úÚ ,
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CmpCondition Ú ,
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CmpData 7Ú ,
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MatchCnt ½Ú ,
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CmpSelect MÚ ADC_CompareEnable Ú , ADCx Ú ,
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Trig AÚ , Level äÚ , DmaEn Ú , HwClrEN eÚ ADC_SeqOneChModeConfig ÄÚ P __PAN_FMC_H__ zÚ P M32 Ú P CMD_ERASE_PAGE Ú P CMD_ERASE_SECTOR ÙÚ P CMD_ERASE_32K ÿÚ P CMD_ERASE_64K úÚ P CMD_ERASE_CHIP Ú P CMD_READ_STATUS_L lÚ P CMD_READ_STATUS_H pÚ P CMD_WRITE_STATUS ªÚ P OPS_WR_STU_REG_NOR ÇÚ P OPS_WR_STU_REG_ALL ÝÚ P CMD_FAST_READ ÕÚ P CMD_NORM_READ ÇÚ P
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CMD_DREAD &Ú P
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CMD_2READ 8Ú P
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CMD_QREAD Ú P
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CMD_4READ 6Ú P CMD_BURST_READ qÚ P BURST_READ_MODE_8 Ú P BURST_READ_MODE_16 RÚ P BURST_READ_MODE_32 TÚ P BURST_READ_MODE_64 OÚ P CMD_TRIG RÚ P CMD_WRITE_ENABLE çÚ P CMD_WRITE_DISABLE Ú P FLASH_X1_MODE ×Ú P FLASH_X2_MODE ÖÚ P FLASH_X4_MODE ÔÚ P QUAD_ENABLE_Pos ëÚ P QUAD_ENABLE_Msk òÚ P Write_Enable_Latch_Pos Ú P Write_Enable_Latch_Msk Ú P Write_In_Process_Pos ³Ú P Write_In_Process_Msk ºÚ P Long_Time_Op_Pos ~Ú P
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PAGE_SIZE Ú P SECTOR_SIZE KÚ 8 _flash_ids ¥Ú " Î)manufacturer_id Ú 8
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<unnamed> SÚ <" Ð)d :Ú 8
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<unnamed> QÚ " Ò)memory_type_id ÓÚ " Ò)memory_density_id Ú <" Î)uid LÚ FLASH_IDS_T Ú
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flash_ids Ú# FMC_EnterDeepPowerDownMode åÚ ," Ø)fmc rÚ" FMC_ExitDeepPowerDownMode KÚ ," Ú)fmc pÚ , fmc Ú FMC_GetFlashUniqueId YÚ , fmc Ú FMC_GetFlashJedecId ÷Ú , fmc Ú FMC_SetFlashCapacity CÚ , fmc Ú! FMC_GetFlashCodeAreaSize æÚ , fmc Ú , adr Ú FMC_EraseSector 5Ú , fmc Ú , addr 4Ú FMC_EraseBlock32k æÚ , fmc Ú , addr 4Ú FMC_EraseBlock64k áÚ , fmc Ú FMC_EraseChip %Ú , fmc Ú ,
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addr <Ú ,
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len Ú FMC_EraseCodeArea Ú , fmc Ú ,
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mode 2Ú InitIcache Ú , fmc Ú ,
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addr <Ú ,
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count ¬Ú , chksum :Ú FMC_GetCrc32Sum ÃÚ , fmc Ú , adr Ú , sz æÚ BlankCheck Ú , fmc Ú , adr Ú , sz æÚ , buf Ú Verify gÚ , fmc Ú , adr Ú , sz æÚ , buf Ú ProgramPage }Ú , fmc Ú , cmd ¬Ú FMC_ReadStatusReg sÚ , fmc Ú FMC_WriteEnable CÚ , fmc Ú FMC_WriteDisable ÔÚ , fmc Ú , ops Ú ,
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buf Ú FMC_WriteStatusReg âÚ , fmc Ú ,
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Addr \Ú , cmd ¬Ú FMC_ReadByte Ú , fmc Ú ,
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addr <Ú , data DÚ FMC_WriteByte úÚ , fmc Ú ,
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addr <Ú , data ;Ú FMC_WriteHalfWord oÚ , fmc Ú ,
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Addr \Ú , cmd ¬Ú FMC_ReadWord Ú , fmc Ú ,
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Addr \Ú , cmd ¬Ú FMC_ReadPage ¢Ú , fmc Ú ,
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Addr \Ú , cmd ¬Ú , buf Ú ,
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len Ú FMC_ReadStream ¯Ú , fmc Ú ,
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Addr \Ú , buf Ú ,
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len Ú FMC_WriteStream Ú , fmc Ú ,
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Addr \Ú , cmd ¬Ú , buf Ú ,
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len Ú FMC_ReadInfoArea Ú , fmc Ú ,
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Addr \Ú , buf Ú ,
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len Ú FMC_WriteInfoArea Ú , fmc Ú FMC_EraseInfoArea Ú , fmc Ú ,
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mode 2Ú , enhance Ú FMC_SetFlashMode ôÚ , fmc Ú FMC_ExitEnhanceMode ¼Ú , fmc Ú ,
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mode 2Ú FMC_EnterEnhanceMode VÚ , fmc Ú FMC_EnableAutoDp ÿÚ , fmc Ú FMC_DisableAutoDp Ú , fmc Ú ,
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cnt Ú FMC_SetRdpWaitCount Ú , fmc Ú ,
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cnt Ú FMC_SetDpWaitCount Ú , fmc Ú ," IRQn hÚ ," NewState Ú FMC_SetSuspendIrq WÚ , fmc Ú ,
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timeout ÊÚ FMC_SetSuspendTimeout Ú P __PAN_DMAC_H__ 9Ú P DMAC_CHANNEL_NUMBER Ú P DMA_INVLID_CHANNEL XÚ" P DMAC_TransferType_Mem2Mem oÚ" P DMAC_TransferType_Mem2Per gÚ" P DMAC_TransferType_Per2Mem gÚ" P DMAC_TransferType_Per2Per _Ú P DMAC_FlowControl_DMA
Ú$ P DMAC_FlowControl_Peripheral =Ú P DMAC_BurstLen_1 zÚ P DMAC_BurstLen_4 wÚ P DMAC_BurstLen_8 sÚ P DMAC_BurstLen_16 BÚ P DMAC_BurstLen_32 DÚ P DMAC_BurstLen_64 ?Ú P DMAC_BurstLen_128 Ú P DMAC_BurstLen_256
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Ú" P DMAC_AddrChange_Increment `Ú" P DMAC_AddrChange_Decrement nÚ! P DMAC_AddrChange_NoChange Ú P DMAC_DataWidth_8 &Ú P DMAC_DataWidth_16 õÚ P DMAC_DataWidth_32 ÷Ú P DMAC_DataWidth_64 òÚ P DMAC_DataWidth_128 ¿Ú P DMAC_DataWidth_256 ½Ú P DMAC_Peripheral_I2C0_Tx ¥Ú P DMAC_Peripheral_I2C0_Rx §Ú P DMAC_Peripheral_SPI0_Tx wÚ P DMAC_Peripheral_SPI0_Rx yÚ! P DMAC_Peripheral_UART0_Tx %Ú! P DMAC_Peripheral_UART0_Rx 'Ú P DMAC_Peripheral_SPI1_Tx vÚ P DMAC_Peripheral_SPI1_Rx xÚ! P DMAC_Peripheral_UART1_Tx $Ú! P DMAC_Peripheral_UART1_Rx &Ú P DMAC_Peripheral_ADC þÚ P DMAC_Peripheral_USB_Rx Ú P DMAC_Peripheral_USB_Tx «Ú# P DMAC_HandshakePolarity_Low ·Ú$ P DMAC_HandshakePolarity_High gÚ P DMAC_Handshake_Default Ú P DMAC_Handshake_Software øÚ P DMAC_Handshake_Hardware Ú$ P DMAC_LockLevel_Tfr_Complete }Ú& P DMAC_LockLevel_Block_Complete ºÚ, P $DMAC_LockLevel_Transaction_Complete Ú P DMAC_ChannelPriority_0 Ú P DMAC_ChannelPriority_1 Ú P DMAC_ChannelPriority_2 Ú P DMAC_ChannelPriority_3 ~Ú P DMAC_ChannelPriority_4 }Ú P DMAC_ChannelPriority_5 |Ú P DMAC_ChannelPriority_6 {Ú P DMAC_ChannelPriority_7 zÚ P DMAC_CHANNELALL_MASK ÒÚ P DMAC_FLAG_INDEX_TFR õÚ P DMAC_FLAG_INDEX_BLK Ú P DMAC_FLAG_INDEX_SRCTFR Ú P DMAC_FLAG_INDEX_DSTTFR Ú P DMAC_FLAG_INDEX_ERR øÚ P DMAC_FLAG_MASK_TFR CÚ P DMAC_FLAG_MASK_BLK VÚ P DMAC_FLAG_MASK_SRCTFR UÚ P DMAC_FLAG_MASK_DSTTFR RÚ P DMAC_FLAG_MASK_ERR FÚ P DMAC_FLAG_MASK_ALL VÚ$ 8 __DMAC_ChannelConfigTypeDef Ú
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" +CTL_L iÚ
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" +CTL_H mÚ
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" +CFG_L |Ú
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" +CFG_H Ú$ __DMAC_ChannelConfigTypeDef ÙÚ" 8 DMAC_ChannelConfigTypeDef _Ú
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" £+
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IntEnable wÚ
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" £+ DataWidthDst >Ú
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" £+ DataWidthSrc AÚ
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" £+AddrChangeDst õÚ
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" £+AddrChangeSrc øÚ
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" £+ BurstLenDst Ú
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" £+ BurstLenSrc Ú
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" £+ GatherEnSrc ¯Ú
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" £+ ScatterEnDst /Ú
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" £+__Rev0 ÔÚ
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" £+ TransferType üÚ
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" £+ FlowControl lÚ
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" £+__Rev1 ÓÚ
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" £+
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BlockSize cÚ
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" £+Done mÚ
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" £+__Rev3 ÑÚ
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" £+__Rev4 ÐÚ
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" £+ChannelPriority ÂÚ
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" £+ChannelSuspend DÚ
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" £+
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FifoEmpty VÚ
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" £+ HandshakeDst 1Ú
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" £+ HandshakeSrc 4Ú
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" £+LockBus :Ú
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" £+ LockChannel £Ú
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" £+ LockBusLevel 8Ú
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" £+LockChannelLevel ¡Ú
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" £+HandshakePolarityDst ÍÚ
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" £+HandshakePolaritySrc ÐÚ
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" £+__Rev6 ÎÚ
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" £+AutoReloadSrc ÉÚ
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" £+AutoReloadDst ÆÚ
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" £+FlowControlMode ßÚ
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" £+ FifoMode âÚ
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" £+ProtectControl Ú
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" £+__Rev7 ÍÚ
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" £+PeripheralSrc Ú
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" £+PeripheralDst ªÚ
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" £+__Rev8 ÌÚ" DMAC_ChannelConfigTypeDef Ú DMAC_IsChannelValid õÚ ," Ë+dma Ú ,
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" Ë+ChIdx íÚ P DMAC_ChannelMask òÚ DMAC_CombinedIntStatus Ú ," Ï+dma }Ú ,
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" Ï+FlgMsk sÚ DMAC_StatusFlag dÚ ," Ò+dma zÚ ,
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" Ò+ChIdx æÚ ,
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" Ò+FlgIdx vÚ DMAC_IntFlag ÃÚ ," Ö+dma vÚ ,
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" Ö+ChIdx âÚ ,
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" Ö+FlgIdx rÚ DMAC_IntFlagMsk Ú ," Ú+dma rÚ ,
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" Ú+ChIdx ÞÚ ,
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" Ú+FlgIdx nÚ DMAC_ClrIntFlag Ú ," Þ+dma nÚ ,
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" Þ+ChIdx ÚÚ ,
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" Þ+FlgIdx jÚ , dma Ú
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DMAC_Init ÎÚ , dma Ú DMAC_DeInit !Ú , dma Ú ,
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ChIdx Ú ,
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FlgIdx Ú DMAC_ClrIntFlagMsk _Ú , dma Ú ,
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ChIdx Ú ,
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FlgIdx Ú DMAC_SetIntFlagMsk TÚ , dma Ú ,
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ChIdx Ú , Config oÚ DMAC_SetChannelConfig Ú , dma Ú ,
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ChIdx Ú , Config oÚ DMAC_GetChannelConfig Ú , dma Ú ,
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ChIdx Ú , Src £Ú , Dst Ú ,
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Len ºÚ DMAC_StartChannel Ú , dma Ú ,
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ChIdx Ú DMAC_StopChannel õÚ , dma Ú DMAC_AcquireChannel ËÚ , dma Ú ,
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ChIdx Ú DMAC_ReleaseChannel ÔÚ , dma Ú" DMAC_IsAllChannelReleased Ú P __PAN_GPIO_H__ Ú P GPIO_PIN_MAX ùÚ 8" _GPIO_ModeDef $Ú " ,GPIO_MODE_INPUT gÚ " ,GPIO_MODE_OUTPUT Ú " ,GPIO_MODE_OPEN_DRAIN îÚ " ,GPIO_MODE_QUASI tÚ GPIO_ModeDef ÇÚ 8" _GPIO_IntAttrDef ÝÚ " ,GPIO_INT_RISING _Ú " ,GPIO_INT_FALLING ,Ú " ,GPIO_INT_BOTH_EDGE Ú " ,GPIO_INT_HIGH Ú " , GPIO_INT_LOW ?Ú GPIO_IntAttrDef Ú 8" _GPIO_ClkSrcDef cÚ" " ,GPIO_DBCTL_DBCLKSRC_RCL Ú# " ,GPIO_DBCTL_DBCLKSRC_HCLK ËÚ GPIO_ClkSrcDef Ú 8" _GPIO_ClkSelDef gÚ " ,GPIO_DBCTL_DBCLKSEL_1 ÂÚ " ,GPIO_DBCTL_DBCLKSEL_2 ÁÚ " ,GPIO_DBCTL_DBCLKSEL_4 ¿Ú " ,GPIO_DBCTL_DBCLKSEL_8 »Ú! " ,GPIO_DBCTL_DBCLKSEL_16 Ú! " ,GPIO_DBCTL_DBCLKSEL_32 Ú! " ,GPIO_DBCTL_DBCLKSEL_64 Ú" " ,GPIO_DBCTL_DBCLKSEL_128 TÚ" " ,GPIO_DBCTL_DBCLKSEL_256 RÚ" " ,GPIO_DBCTL_DBCLKSEL_512 WÚ# " ,GPIO_DBCTL_DBCLKSEL_1024 &Ú# " ,GPIO_DBCTL_DBCLKSEL_2048 Ú# " ,GPIO_DBCTL_DBCLKSEL_4096 Ú# " ,GPIO_DBCTL_DBCLKSEL_8192 Ú$ " ,GPIO_DBCTL_DBCLKSEL_16384 åÚ$ " ,GPIO_DBCTL_DBCLKSEL_32768 áÚ GPIO_ClkSelDef
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Ú P GPIO_PIN_ADDR ÂÚ P P00 Ú P P01 Ú P P02 Ú P P03 Ú P P04 Ú P P05 Ú P P06 Ú P P07 Ú P P10 Ú P P11 Ú P P12 Ú P P13 Ú P P14 Ú P P15 Ú P P16 Ú P P17 Ú P P20 Ú P P21 Ú P P22 Ú P P23 Ú P P24 Ú P P25 Ú P P26 Ú P P27 Ú P P30 Ú P P31 Ú GPIO_ClrIntFlag Ú ," Æ,gpio Ú ,
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" Æ, u32PinMask *Ú GPIO_ClrAllIntFlag cÚ ," É,gpio Ú GPIO_DisableDebounce eÚ ," Ë,gpio Ú ,
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" Ë, u32PinMask %Ú GPIO_EnableDebounce ÔÚ ," Î,gpio þÚ ,
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" Î, u32PinMask "Ú GPIO_DisableDigitalPath 9Ú ," Ñ,gpio ûÚ ,
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" Ñ, u32PinMask Ú GPIO_EnableDigitalPath ¨Ú ," Ô,gpio øÚ ,
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" Ô, u32PinMask Ú GPIO_DisablePullupPath wÚ ," ×,gpio õÚ ,
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" ×, u32PinMask Ú GPIO_EnablePullupPath æÚ ," Ú,gpio òÚ ,
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" Ú, u32PinMask Ú! GPIO_DisablePulldownPath Ú ," Ý,gpio ïÚ ,
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" Ý, u32PinMask Ú GPIO_EnablePulldownPath Ú ," à,gpio ìÚ ,
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" à, u32PinMask Ú GPIO_DisableDoutMask bÚ ," ã,gpio éÚ ,
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" ã, u32PinMask Ú GPIO_EnableDoutMask ÑÚ ," æ,gpio æÚ ,
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" æ, u32PinMask
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Ú GPIO_GetIntFlag Ú ," é,gpio ãÚ ,
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" é, u32PinMask Ú GPIO_SetDebounceTime ^Ú ,"" ì,clksrc Ú ,"" ì,clksel Ú GPIO_GetInData ùÚ ," ï,gpio ÝÚ GPIO_SetOutData jÚ ," ñ,gpio ÛÚ ,
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" ñ,data þÚ GPIO_GetOutData vÚ ," ô,gpio ØÚ GPIO_Toggle îÚ ," ö,gpio ÖÚ ,
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" ö, u32PinMask úÚ GPIO_EnableInt ØÚ ," ù,gpio ÓÚ ,
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" ù,u32Pin Ú ,"" ù, IntAttribs hÚ GPIO_DisableInt iÚ ," ý,gpio ÏÚ ,
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" ý,u32Pin Ú P GPIO_EnableEINT0 vÚ P GPIO_DisableEINT0 Ú P GPIO_EnableEINT1 uÚ P GPIO_DisableEINT1 Ú , gpio Ú ,
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PinMask Ú ," Mode =Ú GPIO_SetMode Ú P __PAN_SPI_H__ dÚ 8" SPI_Irq :Ú " -SPI_IRQ_TX_HALF_EMPTY QÚ " -SPI_IRQ_RX_HALF_FULL ±Ú " -SPI_IRQ_RX_TIMEOUT ;Ú " -SPI_IRQ_RX_OVERRUN 1Ú " - SPI_IRQ_ALL Ú SPI_IrqDef gÚ 8" SPI_Role ÒÚ " -SPI_RoleMaster ¹Ú " -SPI_RoleSlave ,Ú SPI_RoleDef ÿÚ 8" SPI_DataFrameSize RÚ " -SPI_DataFrame_4b UÚ " -SPI_DataFrame_5b TÚ " -SPI_DataFrame_6b SÚ " -SPI_DataFrame_7b RÚ " -SPI_DataFrame_8b QÚ " -SPI_DataFrame_9b PÚ " -SPI_DataFrame_10b &Ú " -SPI_DataFrame_11b %Ú " -SPI_DataFrame_12b $Ú " -SPI_DataFrame_13b #Ú " -SPI_DataFrame_14b "Ú " -SPI_DataFrame_15b !Ú " -SPI_DataFrame_16b Ú SPI_DataFrameSizeDef Ú 8" SPI_BaudRateDiv +Ú " £-SPI_BaudRateDiv_2 âÚ " £-SPI_BaudRateDiv_4 àÚ " £-SPI_BaudRateDiv_6 ÞÚ " £-SPI_BaudRateDiv_8 ÜÚ " £-SPI_BaudRateDiv_16 «Ú " £-SPI_BaudRateDiv_32 Ú " £-SPI_BaudRateDiv_48 ¦Ú " £-SPI_BaudRateDiv_64 ¨Ú " £-SPI_BaudRateDiv_96 £Ú " £-SPI_BaudRateDiv_128 uÚ " £-SPI_BaudRateDiv_160 yÚ " £-SPI_BaudRateDiv_192 tÚ " £-SPI_BaudRateDiv_224 xÚ " £-SPI_BaudRateDiv_240 zÚ " £-SPI_BaudRateDiv_250 yÚ SPI_BaudRateDivDef XÚ P SPI_BAUD_RATE_DIV uÚ 8" SPI_ClockPol EÚ " µ-SPI_ClockPolarityLow Ú " µ-SPI_ClockPolarityHigh ÄÚ SPI_ClockPolDef rÚ 8" SPI_ClockPhase {Ú" " ¹-SPI_ClockPhaseFirstEdge "Ú# " ¹-SPI_ClockPhaseSecondEdge ÌÚ SPI_ClockPhaseDef ¨Ú 8" SPI_FrameFormat Ú " ½-SPI_FormatMotorola ÌÚ " ½- SPI_FormatTi hÚ " ½-SPI_FormatMicrowire fÚ SPI_FrameFormatDef /Ú 8" SPI_WireNum Ú " Â-SPI_WireNumThree ÂÚ " Â-SPI_WireNumFour Ú SPI_WireNumDef ÄÚ 8" SPI_CmdDat 3Ú " Æ-SPI_CommandSelect \Ú " Æ-SPI_DataSelect §Ú SPI_CmdDatDef `Ú 8" SPI_WriteReadSel ©Ú " Ê-SPI_3WireRead 9Ú " Ê-SPI_3WireWrite ¨Ú SPI_WriteReadSelDef ÖÚ 8
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<unnamed> QÚ "" Î- SPI_role ¬Ú "" Î-SPI_dataFrameSize ,Ú "" Î- SPI_CPOL 0Ú "" Î- SPI_CPHA BÚ " Î-SPI_baudRateDiv Ú "" Î- SPI_format ÑÚ SPI_InitTypeDef SÚ SPI_EnableSpi Ú ," Ö-SPIx @Ú
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" Ö-tmpreg CÚ SPI_DisableSpi Ú ," Ù-SPIx =Ú
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" Ù-tmpreg @Ú SPI_IsSpiEnabled öÚ ," Ü-SPIx :Ú
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" Ü-tmpreg =Ú SPI_EnableDmaTx fÚ ," ß-SPIx 7Ú
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" ß-tmpreg :Ú SPI_DisableDmaTx ÷Ú ," â-SPIx 4Ú
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" â-tmpreg 7Ú SPI_IsDmaTxEnabled @Ú ," å-SPIx 1Ú
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" å-tmpreg 4Ú SPI_EnableDmaRx hÚ ," è-SPIx .Ú
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" è-tmpreg 1Ú SPI_DisableDmaRx ùÚ ," ë-SPIx +Ú
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" ë-tmpreg .Ú SPI_IsDmaRxEnabled BÚ ," î-SPIx (Ú
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" î-tmpreg +Ú SPI_SendData Ú ," ñ-SPIx %Ú ,
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" ñ-Data Ú SPI_ReceiveData NÚ ," ô-SPIx "Ú SPI_EnableIrq Ú ," ö-SPIx Ú ,"" ö-irq 3Ú
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" ö-tmpreg #Ú SPI_DisableIrq Ú ," ú-SPIx Ú ,"" ú-irq /Ú
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" ú-tmpreg Ú SPI_IsIrqEnabled öÚ ," þ-SPIx Ú ,"" þ-irq +Ú
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" þ-tmpreg Ú SPI_GetMskedActiveIrq ãÚ ," .SPIx Ú
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" .tmpreg Ú SPI_IsIrqActive GÚ ,"
.SPIx Ú ,""
.irq £Ú
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"
.tmpreg Ú SPI_IsRawIrqActive Ú ," .SPIx Ú ,"" .irq Ú
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" .tmpreg Ú SPI_ClearIrq ~Ú ," .SPIx Ú ,"" .irq Ú
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" .tmpreg Ú SPI_GetRawActiveIrq ±Ú ," .SPIx Ú
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" .tmpreg Ú SPI_IsTxFifoEmpty lÚ ," .SPIx Ú
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" .tmpreg Ú SPI_IsTxFifoFull êÚ ," .SPIx ~Ú
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" .tmpreg Ú SPI_IsRxFifoEmpty nÚ ," .SPIx {Ú
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" .tmpreg ~Ú SPI_IsRxFifoFull ìÚ ," .SPIx xÚ
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" .tmpreg {Ú SPI_IsBusy 6Ú ," .SPIx uÚ
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" .tmpreg xÚ SPI_TxLsbEnable WÚ ," £.SPIx rÚ ," £.enable Ú SPI_RxLsbEnable YÚ ," ¦.SPIx oÚ ," ¦.enable }Ú SPI_SetWireNum Ú ," ©.SPIx lÚ ,"" ©.num {Ú SPI_DataCmdLineEnable "Ú ," ¬.SPIx iÚ ,"" ¬. NewState Ú SPI_DataCmdSelCmdDat ¢Ú ," ¯.SPIx fÚ ,"" ¯.cmdDat rÚ SPI_WriteReadCtrl kÚ ," ².SPIx cÚ ,"" ².wr ÛÚ , SPIx eÚ , SPI_InitStruct QÚ SPI_Init ùÚ P __PAN_UART_H__ Ú 8" UART_TxTrigger hÚ " ¹.UART_TX_FIFO_EMPTY Ú! " ¹.UART_TX_FIFO_TWO_CHARS ÕÚ$ " ¹.UART_TX_FIFO_QUARTER_FULL ãÚ! " ¹.UART_TX_FIFO_HALF_FULL òÚ UART_TxTriggerDef Ú 8" UART_RxTrigger jÚ " ¿.UART_RX_FIFO_ONE_CHAR >Ú$ " ¿.UART_RX_FIFO_QUARTER_FULL ßÚ! " ¿.UART_RX_FIFO_HALF_FULL îÚ* " ¿. UART_RX_FIFO_TWO_LESS_THAN_FULL ÝÚ UART_RxTriggerDef Ú 8" UART_LineCtrl íÚ " Å.Uart_Line_5n1 Ú " Å.Uart_Line_5n1_5 Ú " Å.Uart_Line_5e1 !Ú " Å.Uart_Line_5e1_5 Ú " Å.Uart_Line_5o1 Ú " Å.Uart_Line_5o1_5 Ú " Å.Uart_Line_5s1 Ú " Å.Uart_Line_5s1_5 {Ú " Å.Uart_Line_5m1 Ú " Å.Uart_Line_5m1_5 Ú " Å.Uart_Line_6n1 Ú " Å.Uart_Line_6n2 Ú " Å.Uart_Line_6e1 Ú " Å.Uart_Line_6e2 Ú " Å.Uart_Line_6o1 Ú " Å.Uart_Line_6o2 Ú " Å.Uart_Line_6s1 Ú " Å.Uart_Line_6s2 Ú " Å.Uart_Line_6m1 Ú " Å.Uart_Line_6m2 Ú " Å.Uart_Line_7n1 Ú " Å.Uart_Line_7n2 Ú " Å.Uart_Line_7e1 Ú " Å.Uart_Line_7e2 Ú " Å.Uart_Line_7o1 Ú " Å.Uart_Line_7o2 Ú " Å.Uart_Line_7s1 Ú " Å.Uart_Line_7s2 Ú " Å.Uart_Line_7m1 Ú " Å.Uart_Line_7m2 Ú " Å.Uart_Line_8n1 Ú " Å.Uart_Line_8n2 Ú " Å.Uart_Line_8e1 Ú " Å.Uart_Line_8e2 Ú " Å.Uart_Line_8o1 Ú " Å.Uart_Line_8o2 Ú " Å.Uart_Line_8s1 Ú " Å.Uart_Line_8s2 Ú " Å.Uart_Line_8m1 Ú " Å.Uart_Line_8m2 Ú UART_LineCtrlDef Ú 8" UART_Irq èÚ! " ï.UART_IRQ_RECV_DATA_AVL ÁÚ " ï.UART_IRQ_THR_EMPTY ØÚ " ï.UART_IRQ_LINE_STATUS EÚ " ï.UART_IRQ_MODEM_STATUS ùÚ " ï. UART_IRQ_ALL çÚ UART_IrqDef Ú 8" UART_Event Ú " ö.UART_EVENT_MODEM ©Ú " ö.UART_EVENT_NONE íÚ " ö.UART_EVENT_THR_EMPTY 7Ú " ö.UART_EVENT_DATA Ú " ö.UART_EVENT_LINE õÚ " ö.UART_EVENT_TIMEOUT ðÚ UART_EventDef ;Ú 8" UART_LineStatus úÚ " þ.UART_LINE_DATA_RDY Ú " þ.UART_LINE_OVERRUN_ERR êÚ " þ.UART_LINE_PARITY_ERR DÚ " þ.UART_LINE_FRAME_ERR ´Ú " þ.UART_LINE_BREAK_INT ¸Ú " þ.UART_LINE_THRE >Ú " þ.UART_LINE_TXSR_EMPTY &Ú$ " þ.UART_LINE_RECV_FIFO_EMPTY ºÚ " þ.UART_LINE_ADDR_RCVD ¾Ú UART_LineStatusDef 'Ú 8" UART_ModemStatus Ú " /UART_MODEM_DCTS kÚ " /UART_MODEM_DDSR lÚ " /UART_MODEM_TERI eÚ " /UART_MODEM_DDCD Ú " /UART_MODEM_CTS ±Ú " /UART_MODEM_DSR ²Ú " /UART_MODEM_RI Ú " /UART_MODEM_DCD ÐÚ UART_ModemStatusDef »Ú 8
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<unnamed> QÚ
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" /UART_BaudRate JÚ "" /UART_LineCtrl Ú UART_InitTypeDef Ú UART_EnableStickParity oÚ ," /UARTx +Ú UART_DisableStickParity Ú ," /UARTx )Ú UART_GetLineStatus Ú ," /UARTx 'Ú UART_GetModemStatus Ú ," /UARTx %Ú UART_EnableFifo pÚ ," /UARTx #Ú UART_DisableFifo Ú ," ¡/UARTx !Ú UART_IsFifoEnabled JÚ ," £/UARTx Ú UART_ResetRxFifo èÚ ," ¥/UARTx Ú
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" ¥/val ÄÚ UART_ResetTxFifo æÚ ," ¨/UARTx Ú UART_SetTxTrigger kÚ ," ª/UARTx Ú ,"" ª/level Ú UART_SetRxTrigger mÚ ," /UARTx Ú ,"" /level ªÚ UART_GetTxFifoLevel ËÚ ," °/UARTx Ú UART_GetRxFifoLevel ÍÚ ," ²/UARTx Ú UART_EnableAfc ìÚ ," ´/UARTx Ú UART_DisableAfc }Ú ," ¶/UARTx Ú UART_IsAfcEnabled ÆÚ ," ¸/UARTx
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Ú UART_SendData ;Ú ," º/UARTx Ú ," º/Data YÚ UART_ReceiveData üÚ ," ½/UARTx Ú UART_EnablePtime óÚ ," ¿/UARTx Ú UART_DisablePtime Ú ," Á/UARTx Ú UART_IsPtimeEnabled ÍÚ ," Ã/UARTx ÿÚ UART_EnableIrq ÊÚ ," Å/UARTx ýÚ ,"" Å/irq bÚ UART_DisableIrq [Ú ," È/UARTx úÚ ,"" È/irq _Ú UART_IsIrqEnabled ¤Ú ," Ë/UARTx ÷Ú ,"" Ë/irq \Ú UART_GetIrqMasked Ú ," Î/UARTx ôÚ UART_GetActiveEvent µÚ ," Ð/UARTx òÚ UART_IsTxFifoEmpty Ú ," Ò/UARTx ðÚ UART_IsTxFifoFull Ú ," Ô/UARTx îÚ UART_IsRxFifoEmpty Ú ," Ö/UARTx ìÚ UART_IsRxFifoFull Ú ," Ø/UARTx êÚ UART_EnableHaltTX »Ú ," Ú/UARTx èÚ UART_DisableHaltTX LÚ ," Ü/UARTx æÚ UART_EnableRts ½Ú ," Þ/UARTx äÚ UART_DisableRts NÚ ," à/UARTx âÚ UART_Enable9BitData Ú ," â/UARTx àÚ UART_Disable9BitData «Ú ," ä/UARTx ÞÚ! UART_EnableAddrMatchMode õÚ ," æ/UARTx ÜÚ" UART_DisableAddrMatchMode Ú ," è/UARTx ÚÚ UART_SendAddr :Ú ," ê/UARTx ØÚ UART_SetReceiveAddress xÚ ," ì/UARTx ÖÚ ,
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" ì/addr ÿÚ UART_SetTransmitAddress çÚ ," ï/UARTx ÓÚ ,
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" ï/addr üÚ , UARTx Ú , UART_InitStruct ÿÚ
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UART_Init §Ú , UARTx Ú UART_DeInit úÚ , UARTx Ú , Buf ®Ú ,
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BufSize Ú ,
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SendSize ªÚ UART_SendMultipleData ÓÚ , UARTx Ú , Buf ®Ú ,
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BufSize Ú ,
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ExpectSize ÇÚ! UART_ReceiveMultipleData Ú P __PAN_I2C_H__ Ú 8
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<unnamed> QÚ
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" 0I2C_ClockSpeed Ú " 0 I2C_Mode cÚ " 0I2C_DutyCycle HÚ " 0I2C_OwnAddress1 ¯Ú" " 0I2C_AcknowledgedAddress <Ú I2C_InitTypeDef Ú P I2C_DYNAMIC_TAR_UPDATE Ú P I2C_MODE_MASTER @Ú P I2C_MODE_SLAVE Ú P IS_I2C_MODE xÚ P I2C_SPEED_STANDARD_MODE ÛÚ P I2C_SPEED_FAST_MODE Ú P I2C_SPEED_HIGH_MODE Ú P I2C_DutyCycle_16_9 Ú P I2C_DutyCycle_2 iÚ P I2C_DutyCycle_1_1 ÖÚ P I2C_DutyCycle_1_2 ÕÚ P IS_I2C_DUTY_CYCLE |Ú" P I2C_Direction_Transmitter ßÚ P I2C_Direction_Receiver MÚ P IS_I2C_DIRECTION òÚ% P I2C_AcknowledgedAddress_7bit Ú& P I2C_AcknowledgedAddress_10bit çÚ# P IS_I2C_ACKNOWLEDGE_ADDRESS öÚ P I2C_CMD_WR ¾Ú P I2C_CMD_RD ÑÚ P I2C_CMD_STOP Ú P I2C_CMD_RESTART 8Ú P I2C_RX_TL_0 `Ú P I2C_RX_TL_1 _Ú P I2C_RX_TL_2 ^Ú P I2C_RX_TL_3 ]Ú P I2C_RX_TL_4 \Ú P I2C_RX_TL_5 [Ú P I2C_RX_TL_6 ZÚ P I2C_RX_TL_7 YÚ P I2C_RX_TL_8 XÚ P I2C_TX_TL_0 ^Ú P I2C_TX_TL_1 ]Ú P I2C_TX_TL_2 \Ú P I2C_TX_TL_3 [Ú P I2C_TX_TL_4 ZÚ P I2C_TX_TL_5 YÚ P I2C_TX_TL_6 XÚ P I2C_TX_TL_7 WÚ P I2C_TX_TL_8 VÚ P I2C_IT_RX_UNDER Ú P I2C_IT_RX_OVER QÚ P I2C_IT_RX_FULL ZÚ P I2C_IT_TX_OVER OÚ P I2C_IT_TX_EMPTY úÚ P I2C_IT_RD_REQ »Ú P I2C_IT_TX_ABORT Ú P I2C_IT_RX_DONE gÚ P I2C_IT_ACTIVITY 'Ú P I2C_IT_STOP_DET Ú P I2C_IT_START_DET ÈÚ P I2C_IT_GEN_CALL ?Ú P I2C_IT_MST_ON_HOLD Ú P I2C_IT_ALL ÅÚ P IS_I2C_CLEAR_IT 2Ú P IS_I2C_GET_IT ½Ú P I2C_FLAG_SLV_ACTIVITY JÚ P I2C_FLAG_MST_ACTIVITY KÚ P I2C_FLAG_RFF ?Ú P I2C_FLAG_RFNE ðÚ P I2C_FLAG_TFE >Ú P I2C_FLAG_TFNF íÚ P I2C_FLAG_ACTIVITY ¦Ú P IS_I2C_CLEAR_FLAG ±Ú P IS_I2C_GET_FLAG <Ú P
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FLAG_MASK Ú P
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ITEN_MASK þÚ P IT_FLAG_MASK Ú I2C_SetMode Ú ," Í0I2Cx tÚ ," Í0Mode 1Ú I2C_SetTxTirggerLevel éÚ ," Ð0I2Cx qÚ ," Ð0ThresholdValue þÚ I2C_SetRxTirggerLevel ëÚ ," Ó0I2Cx nÚ ," Ó0ThresholdValue ûÚ I2C_Cmd µÚ ," Ö0I2Cx kÚ ,"" Ö0 NewState gÚ I2C_GeneralCallCmd eÚ ," Ù0I2Cx hÚ ,"" Ù0 NewState dÚ I2C_SendDataCmd ¡Ú ," Ü0I2Cx eÚ ," Ü0Data 6Ú ," Ü0Cmd Ú I2C_SendCmd #Ú ," à0I2Cx aÚ ," à0Cmd Ú I2C_ReceiveData |Ú ," ã0I2Cx ^Ú I2C_AbortTransfer xÚ ," å0I2Cx \Ú I2C_DMACmd ÝÚ ," ç0I2Cx ZÚ ,"" ç0 NewState VÚ! I2C_DMATransferDataLevel Ú ," ê0I2Cx WÚ ," ê0Level ¨Ú I2C_DMAReceiveDataLevel ¢Ú ," í0I2Cx TÚ ," í0Level ¥Ú I2C_GetITStatus xÚ ," ð0I2Cx QÚ ," ð0I2C_IT ÕÚ I2C_GetRawITStatus HÚ ," ó0I2Cx NÚ ," ó0I2C_IT ÒÚ I2C_ITConfig ÌÚ ," ö0I2Cx KÚ ," ö0I2C_IT ÏÚ ,"" ö0 NewState GÚ I2C_DisableAllIT MÚ ," ú0I2Cx GÚ! I2C_ClearAllITPendingBit &Ú ," ü0I2Cx EÚ I2C_AbortSrcCheck ·Ú ," þ0I2Cx CÚ ,
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" þ0IC_MSK Ú I2C_SetSlaveAddr Ú ," 1I2Cx ¿Ú ,
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" 1addr hÚ , I2Cx Ú , I2C_InitStruct Ú I2C_Init 'Ú , I2Cx Ú , Address Ú I2C_Set7bitAddress ?Ú , I2Cx Ú , Address Ú I2C_Set10bitAddress Ú , I2Cx Ú ,
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I2C_FLAG Ú I2C_GetFlagStatus Ú , I2Cx Ú , I2C_IT Ú I2C_ClearITPendingBit 9Ú , I2Cx Ú , WriteBuf Ú ,
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Size <Ú
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I2C_Write ®Ú , I2Cx Ú , ReadBuf *Ú ,
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Size <Ú I2C_Read ?Ú P __PAN_TIMER_H__ ËÚ 8" _TIMER_CntModeDef ¥Ú " 1TIMER_ONESHOT_MODE fÚ " 1TIMER_PERIODIC_MODE 5Ú " 1TIMER_TOGGLE_MODE ÆÚ " 1TIMER_CONTINUOUS_MODE iÚ TIMER_CntModeDef HÚ 8" _TIMER_CapModeDef ¶Ú+ " ¢1!TIMER_CAPTURE_FREE_COUNTING_MODE Ú. " ¢1$TIMER_CAPTURE_TRIGGER_COUNTING_MODE Ú+ " ¢1!TIMER_CAPTURE_COUNTER_RESET_MODE ïÚ TIMER_CapModeDef YÚ 8" _TIMER_CapEdgeDef ÆÚ% " §1TIMER_CAPTURE_FALLING_EDGE Ú$ " §1TIMER_CAPTURE_RISING_EDGE >Ú" " §1TIMER_CAPTURE_BOTH_EDGE áÚ1 " §1'TIMER_CAPTURE_FALLING_THEN_RISING_EDGE :Ú1 " §1'TIMER_CAPTURE_RISING_THEN_FALLING_EDGE :Ú TIMER_CapEdgeDef iÚ 8" _TIMER_EvtCntEdgeDef Ú% " ®1TIMER_COUNTER_FALLING_EDGE øÚ$ " ®1TIMER_COUNTER_RISING_EDGE +Ú TIMER_EvtCntEdgeDef #Ú 8" _TIMER_CapSrcDef Ú' " ²1 TIMER_CAPTURE_SOURCE_EXT_PIN Ú* " ²1 TIMER_CAPTURE_SOURCE_32K_OUTPUT 7Ú TIMER_CapSrcDef ¸Ú 8" _TIMER0_CmpSelDef ÛÚ" " ¶1TMR0_COMPARATOR_SEL_CMP ÊÚ# " ¶1TMR0_COMPARATOR_SEL_CMP1 Ú# " ¶1TMR0_COMPARATOR_SEL_CMP2 Ú TIMER0_CmpSelDef ~Ú P FIXED_DEVIATION ;Ú TIMER_EnableCapture ÓÚ ," ¼1timer Ú ,"" ¼1capMode óÚ ,"" ¼1capEdge Ú TIMER_DisableCapture dÚ ," À1timer Ú! TIMER_EnableEventCounter »Ú ," Â1timer Ú ,"" Â1 evtCntEdge ¸Ú" TIMER_DisableEventCounter LÚ ," Å1timer Ú TIMER_SetPrescaleValue Ú ," Ç1timer Ú ,
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" Ç1 u32Value ÞÚ TIMER_SetCountingMode òÚ ," Ê1timer Ú ,"" Ê1cntMode ÒÚ TIMER_IsActive àÚ ," Í1timer Ú TIMER_Start ðÚ ," Ï1timer Ú TIMER_Stop ZÚ ," Ñ1timer Ú TIMER_Reset ûÚ ," Ó1timer Ú TIMER_EnableWakeup <Ú ," Õ1timer ~Ú TIMER_DisableWakeup ÍÚ ," ×1timer |Ú$ TIMER_EnableCaptureDebounce Ú ," Ù1timer zÚ% TIMER_DisableCaptureDebounce /Ú ," Û1timer xÚ) !TIMER_EnableEventCounterDebounce Ú ," Ý1timer vÚ* "TIMER_DisableEventCounterDebounce Ú ," ß1timer tÚ TIMER_EnableInt Ú ," á1timer rÚ TIMER_DisableInt Ú ," ã1timer pÚ TIMER_EnableCaptureInt ¢Ú ," å1timer nÚ TIMER_DisableCaptureInt 3Ú ," ç1timer lÚ TIMER_GetIntFlag /Ú ," é1timer jÚ TIMER_ClearIntFlag dÚ ," ë1timer hÚ TIMER_GetTFFlag ÂÚ ," í1timer fÚ TIMER_ClearTFFlag ÷Ú ," ï1timer dÚ ,
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" ï1 timer_flag oÚ TIMER_GetWakeupFlag çÚ ," ò1timer aÚ TIMER_ClearWakeupFlag Ú ," ô1timer _Ú ,
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" ô1
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wake_flag åÚ TIMER_GetCaptureIntFlag MÚ ," ÷1timer \Ú" TIMER_ClearCaptureIntFlag Ú ," ù1timer ZÚ TIMER_GetCaptureFlag ~Ú ," û1timer XÚ TIMER_ClearCaptureFlag ³Ú ," ý1timer VÚ TIMER_SetCaptureSource wÚ ," ÿ1timer TÚ ,"" ÿ1capSrc Ú TIMER_GetCaptureData ~Ú ," 2timer ÐÚ TIMER_GetCounter ôÚ ," 2timer ÎÚ TIMER_SetTmrCounterMode "Ú ," 2timer ÌÚ ,
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" 2 u32CntMode mÚ , timer ¦Ú ," cntMode ïÚ ,
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u32Freq iÚ TIMER_Open bÚ , timer ¦Ú TIMER_Close üÚ , timer ¦Ú ,
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u32Usec gÚ TIMER_Delay Ú , timer ¦Ú ," cmp_seq ÔÚ ,
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u32Value øÚ TIMER_SetCmpValue Ú P __PAN_PWM_H__ \Ú P PWM_CHANNEL_NUM Ú P PWM_CH0 ¯Ú P PWM_CH1 ®Ú P PWM_CH2 Ú P PWM_CH3 ¬Ú P PWM_CH4 «Ú P PWM_CH5 ªÚ P PWM_CH6 ©Ú P PWM_CH7 ¨Ú 8" _PWM_ClkSrcSelDef vÚ " 2PWM_CLK_SRC_APB EÚ " 2PWM_CLK_SRC_RCL 7Ú " 2PWM_CLK_SRC_XTL Ú PWM_ClkSrcSelDef Ú 8" _PWM_ClkDivDef ¥Ú " ¥2PWM_CLK_DIV_1 ëÚ " ¥2PWM_CLK_DIV_2 êÚ " ¥2PWM_CLK_DIV_4 èÚ " ¥2PWM_CLK_DIV_8 äÚ " ¥2PWM_CLK_DIV_16 ³Ú " ¥2PWM_CLK_DIRECT ¡Ú PWM_ClkDivDef HÚ 8" _PWM_AlignedTypeDef Ú " 2PWM_EDGE_ALIGNED !Ú " 2PWM_CENTER_ALIGNED qÚ PWM_AlignedTypeDef %Ú 8" _PWM_IntPeriodTypeDef ¤Ú# " ±2PWM_PERIOD_INT_UNDERFLOW SÚ# " ±2PWM_PERIOD_INT_MATCH_CNR ZÚ PWM_IntPeriodTypeDef GÚ 8" _PWM_OperateTypeDef fÚ! " µ2OPERATION_EDGE_ALIGNED PÚ# " µ2OPERATION_CENTER_ALIGNED Ú+ " µ2!OPERATION_PRECISE_CENTER_ALIGNED &Ú PWM_OperateTypeDef Ú 8" _PWM_CntModeDef 6Ú " º2PWM_CNTMODE_ONE_SHOT Ú" " º2PWM_CNTMODE_AUTO_RELOAD ¶Ú PWM_CntModeDef ÙÚ PWM_EnableOutput ©Ú ," ¾2pwm eÚ ,
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" ¾2u32ChannelMask Ú PWM_DisableOutput :Ú ," Á2pwm bÚ ,
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" Á2u32ChannelMask Ú PWM_StartChannel ºÚ ," Ä2pwm _Ú ,
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" Ä2u32ChannelNum êÚ PWM_StopChannel $Ú ," Ç2pwm \Ú ,
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" Ç2u32ChannelNum çÚ PWM_EnableDeadZone ,Ú ," Ê2pwm YÚ ,
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" Ê2u32ChannelNum äÚ ,
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" Ê2 u32Duration Ú PWM_DisableDeadZone ½Ú ," Î2pwm UÚ ,
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" Î2u32ChannelNum àÚ PWM_EnableCMPDInt éÚ ," Ñ2pwm RÚ ,
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" Ñ2u32ChannelNum ÝÚ PWM_DisableCMPDInt zÚ ," Ô2pwm OÚ ,
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" Ô2u32ChannelNum ÚÚ PWM_ClearCMPDIntFlag ÉÚ ," ×2pwm LÚ ,
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" ×2u32ChannelNum ×Ú PWM_GetCMPDIntFlag Ú ," Ú2pwm IÚ ,
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" Ú2u32ChannelNum ÔÚ PWM_EnablePeriodInt ¦Ú ," Ý2pwm FÚ ,
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" Ý2u32ChannelNum ÑÚ PWM_DisablePeriodInt 7Ú ," à2pwm CÚ ,
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" à2u32ChannelNum ÎÚ PWM_ClearPeriodIntFlag Ú ," ã2pwm @Ú ,
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" ã2u32ChannelNum ËÚ PWM_GetPeriodIntFlag QÚ ," æ2pwm =Ú ,
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" æ2u32ChannelNum ÈÚ PWM_EnableZeroInt mÚ ," é2pwm :Ú ,
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" é2u32ChannelNum ÅÚ PWM_DisableZeroInt þÚ ," ì2pwm 7Ú ,
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" ì2u32ChannelNum ÂÚ PWM_ClearZeroIntFlag MÚ ," ï2pwm 4Ú ,
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" ï2u32ChannelNum ¿Ú PWM_GetZeroIntFlag Ú ," ò2pwm 1Ú ,
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" ò2u32ChannelNum ¼Ú PWM_EnableCMPUInt ØÚ ," õ2pwm .Ú ,
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" õ2u32ChannelNum ¹Ú PWM_DisableCMPUInt iÚ ," ø2pwm +Ú ,
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" ø2u32ChannelNum ¶Ú PWM_ClearCMPUIntFlag ¸Ú ," û2pwm (Ú ,
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" û2u32ChannelNum ³Ú PWM_GetCMPUIntFlag Ú ," þ2pwm %Ú ,
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" þ2u32ChannelNum °Ú PWM_EnableCenterInt ¨Ú ," 3pwm ¡Ú ,
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" 3u32ChannelNum ,Ú ,"" 3IntPeriodType ªÚ PWM_DisableCenterInt 9Ú ,"
3pwm Ú ,
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"
3u32ChannelNum (Ú PWM_ClearCenterIntFlag Ú ," 3pwm Ú ,
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" 3u32ChannelNum %Ú PWM_GetCenterIntFlag SÚ ," 3pwm Ú ,
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" 3u32ChannelNum "Ú" PWM_EnableIndependentMode 5Ú ," 3pwm Ú$ PWM_EnableComplementaryMode ?Ú ," 3pwm Ú% PWM_DisableComplementaryMode ÐÚ ," 3pwm Ú PWM_EnableGroupMode ¢Ú ," 3pwm Ú PWM_DisableGroupMode 3Ú ," 3pwm Ú PWM_EnableSyncMode Ú ," 3pwm Ú PWM_DisableSyncMode ¥Ú ," 3pwm Ú PWM_SetPrescaler ´Ú ," 3pwm Ú ,
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" 3u32ChannelNum Ú ,
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" 3 u32Prescaler [Ú PWM_ResetPrescaler ÙÚ ," 3pwm Ú ,
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" 3u32ChannelNum Ú PWM_SetDivider Ú ," £3pwm Ú ,
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" £3u32ChannelNum
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Ú ,"" £3Divider ýÚ PWM_SetCMR Ú ," §3pwm {Ú ,
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" §3u32ChannelNum Ú ,
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" §3u32CMR Ú PWM_SetCNR ~Ú ," «3pwm wÚ ,
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" «3u32ChannelNum Ú ,
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" «3u32CNR Ú PWM_SetCMRD 9Ú ," ¯3pwm sÚ ,
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" ¯3u32ChannelNum þÚ ,
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" ¯3u32CMRD ÍÚ PWM_SetAlignedType ûÚ ," ³3pwm oÚ ,
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" ³3u32ChannelMask Ú ,"" ³3 AlignedType VÚ! PWM_EnableAsymmetricMode Ú ," ·3pwm kÚ" PWM_DisableAsymmetricMode Ú ," ¹3pwm iÚ PWM_EnablePCA lÚ ," »3pwm gÚ PWM_DisablePCA ýÚ ," ½3pwm eÚ , pwm wÚ ,
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u32ChannelNum Ú ,
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u32Frequency ;Ú ,
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u32DutyCycle WÚ ," OperateType BÚ PWM_ConfigOutputChannel ÇÚ , pwm wÚ ,
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u32ChannelNum Ú , u16PeriodCycle Ú , u16PulseCycle îÚ PWM_SetPeriodAndDuty %Ú , pwm wÚ ,
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u32ChannelMask ¤Ú
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PWM_Start uÚ , pwm wÚ ,
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u32ChannelMask ¤Ú PWM_Stop ßÚ , pwm wÚ ,
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u32ChannelMask ¤Ú PWM_ForceStop æÚ , pwm wÚ ,
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u32ChannelMask ¤Ú! PWM_EnableOutputInverter >Ú , pwm wÚ ,
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u32ChannelMask ¤Ú" PWM_DisableOutputInverter ÏÚ P __PAN_WDT_H__ aÚ 8" _WDT_Timeout Ú " Ú3WDT_TIMEOUT_2POW4 |Ú " Ú3WDT_TIMEOUT_2POW6 zÚ " Ú3WDT_TIMEOUT_2POW8 xÚ " Ú3WDT_TIMEOUT_2POW10 MÚ " Ú3WDT_TIMEOUT_2POW12 KÚ " Ú3WDT_TIMEOUT_2POW14 IÚ " Ú3WDT_TIMEOUT_2POW15 HÚ " Ú3WDT_TIMEOUT_2POW16 GÚ " Ú3WDT_TIMEOUT_2POW17 FÚ " Ú3WDT_TIMEOUT_2POW18 EÚ " Ú3WDT_TIMEOUT_2POW19 DÚ " Ú3WDT_TIMEOUT_2POW20 LÚ " Ú3WDT_TIMEOUT_2POW21 KÚ " Ú3WDT_TIMEOUT_2POW22 JÚ " Ú3WDT_TIMEOUT_2POW23 IÚ " Ú3WDT_TIMEOUT_2POW24 HÚ WDT_TimeoutDef ¡Ú 8" _WDT_ResetDelay Ú " ì3WDT_RESET_DELAY_2CLK Ú " ì3WDT_RESET_DELAY_17CLK RÚ! " ì3WDT_RESET_DELAY_129CLK Ú" " ì3WDT_RESET_DELAY_1025CLK îÚ WDT_ResetDelayDef Ú WDT_ClearResetFlag Ú WDT_ClearTimeoutFlag 6Ú WDT_ClearTimeoutIntFlag Ú# WDT_ClearTimeoutWakeupFlag ½Ú WDT_GetResetFlag éÚ WDT_GetTimeoutFlag Ú WDT_GetTimeoutIntFlag ÐÚ! WDT_GetTimeoutWakeupFlag Ú WDT_ResetCounter £Ú ," u32TimeoutInterval Ú ," u32ResetDelay äÚ ,
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u32EnableReset Ú ,
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u32EnableWakeup 3Ú WDT_Open øÚ
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WDT_Close Ú WDT_EnableInt Ú WDT_DisableInt Ú P __PAN_WWDT_H__ Ú 8" _WWDT_Prescale pÚ " 4WWDT_PRESCALER_1 -Ú " 4WWDT_PRESCALER_2 ,Ú " 4WWDT_PRESCALER_4 *Ú " 4WWDT_PRESCALER_8 &Ú " 4WWDT_PRESCALER_16 õÚ " 4WWDT_PRESCALER_32 ÷Ú " 4WWDT_PRESCALER_64 òÚ " 4WWDT_PRESCALER_128 ¿Ú " 4WWDT_PRESCALER_192 ¾Ú " 4WWDT_PRESCALER_256 ½Ú " 4WWDT_PRESCALER_384 »Ú " 4WWDT_PRESCALER_512 ÂÚ " 4WWDT_PRESCALER_768 µÚ " 4WWDT_PRESCALER_1024 Ú " 4WWDT_PRESCALER_1536 Ú " 4WWDT_PRESCALER_2048 Ú WWDT_PrescaleDef þÚ P WWDT_RELOAD_WORD ´Ú WWDT_ClearResetFlag ÅÚ WWDT_ClearIntFlag ¡Ú WWDT_ClearWWDTFFlag <Ú WWDT_GetResetFlag Ú WWDT_GetIntFlag lÚ WWDT_GetWWDTFFlag Ú WWDT_GetCounter 1Ú WWDT_GetCompareValue CÚ WWDT_ReloadCounter ôÚ ," preScale Ú ,
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u32CmpValue ÒÚ ,
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u32EnableInt {Ú
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WWDT_Open Ú WWDT_Close 9Ú P __PAN_LP_H__ ¶Ú P LP_EXT_P56_WK_EN ²Ú P LP_EXT_P56_WK_DISABLE GÚ P LP_EXT_P56_WK_EDGE_LOW ÓÚ P LP_EXT_P56_WK_EDGE_HIGH £Ú" P LP_WKUP_MODE_SEL_EXT_GPIO ²Ú P LP_WKUP_MODE_SEL_32K Ú P LP_WKUP_MODE_SEL_GPIO
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Ú P LP_WKUP_MODE_SEL_WDT LÚ P LP_WKUP_MODE_SEL_TIMER ¶Ú P LP_WKUP_MODE_SEL_BOD fÚ P LP_WKUP_MODE_SEL_LVR GÚ P LP_MODE_SEL_SLEEP_MODE àÚ# P LP_MODE_SEL_DEEPSLEEP_MODE ºÚ$ P LP_MODE_SEL_STANDBY_M1_MODE ]Ú$ P LP_MODE_SEL_STANDBY_M0_MODE ^Ú P LP_DEEPSLEEP_MODE_SEL HÚ P LP_DEEPSLEEP_MODE1 `Ú P LP_DEEPSLEEP_MODE2 _Ú P LP_DEEPSLEEP_MODE3 ^Ú P LP_STANDBY_M1_MODE_SEL ëÚ P LP_STANDBY_M1_MODE1 Ú P LP_STANDBY_M1_MODE2 Ú P LP_STANDBY_M1_MODE3 Ú LP_EnableInt oÚ ," ½4ana Ú ,"" ½4 NewState |Ú LP_ClearWakeFlag ðÚ ," À4ana
Ú ,
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" À4u32Mask UÚ LP_HpldoRdyBypassEn Ú ," Ã4ana Ú ,"" Ã4 NewState vÚ LP_FastClkDelayEn Ú ," Æ4ana Ú ,"" Æ4 NewState sÚ , ana Ú , WkEdge £Ú LP_SetExternalWake ÒÚ , ana Ú ,
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u32ClkCnt ´Ú , idx Ú LP_SetSleepTime Ú , ana Ú , u16Clk32Cnt GÚ LP_SetLpldohDelay MÚ , ana Ú , u16Clk32Cnt GÚ LP_SetWakeDelay ,Ú , ana Ú , mode 9Ú LP_SetSleepMode %Ú , ana Ú ,
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wkMode lÚ , enterCyclically ¡Ú LP_SetSleepModeConfig ÃÚ , ana Ú ,
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wkMode lÚ , enterCyclically ¡Ú ,
|
PowerCtrl 2Ú , dp_mode Ú LP_SetDeepSleepConfig ÊÚ! LP_SetStandbyMode0Config ±Ú' LP_SetStandbyMode0BodLvrConfig \Ú , ana Ú ,
|
wkMode lÚ ,
|
PowerCtrl 2Ú ,
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slpTimer Ú , spaceIdx ¥Ú ,
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stdy_mode Ú! LP_SetStandbyMode1Config °Ú P __PAN_EFUSE_H__ ÔÚ P EFUSE_CMD_READ Ú P EFUSE_CMD_PROGRAM Ú P EFUSE_CMD_INACTIVE JÚ P EFUSE_STATUS_OK ùÚ P EFUSE_STATUS_FAIL sÚ EFUSE_Init uÚ ," ò4efuse gÚ EFUSE_UnInit ®Ú ," ô4efuse eÚ EFUSE_GetErrorStatus GÚ ," ö4efuse cÚ EFUSE_ClrErrorStatus FÚ ," ø4efuse aÚ , efuse ¯Ú ,
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addr <Ú EFUSE_ReadByte åÚ , efuse ¯Ú ,
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addr <Ú , data DÚ EFUSE_WriteByte TÚ , efuse ¯Ú ,
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addr <Ú , data /Ú , len Ú EFUSE_Read Ú , efuse ¯Ú ,
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addr <Ú , data /Ú , len Ú EFUSE_Write ðÚ , efuse ¯Ú ,
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addr <Ú , data /Ú , len Ú EFUSE_UserRead ÚÚ , efuse ¯Ú ,
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addr <Ú , data /Ú , len Ú EFUSE_UserWrite IÚ P _PAN_CLKTRIM_H_ ôÚ TRIM_SetIdealCnt Ú ," 5trim Ú ,
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" 5cnt §Ú TRIM_GetIdealCnt Ú ," 5trim Ú TRIM_GetRealCnt rÚ ," 5trim Ú TRIM_IsIntStatusOccured ûÚ ," 5trim Ú ,
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" 5msk Ú TRIM_ClearIntStatusMsk lÚ ," 5trim Ú ,
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" 5msk Ú TRIM_EnableInt ËÚ ," £5trim Ú ,"" £5 NewState Ú! TRIM_SetRelationIncrease Ú ," ¦5trim Ú ,"" ¦5 NewState Ú" TRIM_SetEarlyTerminatinEn 0Ú ," ©5trim Ú ,"" ©5 NewState Ú TRIM_SetCoarseCode 1Ú ," ¬5trim
|
Ú ,
|
" ¬5code 9Ú TRIM_GetCoarseCode =Ú ," ¯5trim Ú TRIM_SetFineCode Ú ," ±5trim Ú ,
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" ±5code 4Ú TRIM_GetFineCode Ú ," ´5trim Ú TRIM_SetBitWidth îÚ ," ¶5trim Ú ,
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" ¶5width ¨Ú TRIM_GetBitWidth úÚ ," ¹5trim ýÚ TRIM_StartTuning ¶Ú ," »5trim ûÚ ,
|
" »5 function WÚ , trim Ú ,
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cnt Ú TRIM_SetCalWaitCnt 3Ú , trim Ú ,
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cnt Ú TRIM_SetCalCnt ÐÚ , trim Ú TRIM_GetCalCnt ÜÚ , trim Ú ,
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|
deviation
|
Ú TRIM_SetErrRange ëÚ P PAN_POWER__H_ Ú 8
|
<unnamed> QÚ " Ê5buck_out_trim @Ú " Ê5lph_ldo_vref_trim Ú " Ê5 lpl_ldo_trim ¸Ú " Ê5 hp_ldo_trim *Ú power_param_t wÚ PW_ParamIsHas ÿÚ , p_otp ¥Ú PW_ParamsSet :Ú , temp !Ú PW_AutoOptimizeParams jÚ P __PAN_HAL_H__ {Ú P __PAN_HAL_GPIO_H__ ãÚ P __PAN_HAL_DEF_H__ EÚ DMAC_CallbackFunc ÒÚ UART_CB_FLAG_TX_FINISH Ú UART_CB_FLAG_RX_FINISH Ú UART_CB_FLAG_RX_TIMEOUT §Ú! UART_CB_FLAG_RX_BUFFFULL vÚ UART_CB_FLAG_DMA Ú UART_Cb_Flag_Opt 6Ú I2C_CB_FLAG_STOP Ú I2C_CB_FLAG_DMA Ú I2C_Cb_Flag_Opt ¶Ú ADC_CB_FLAG_DMA Ú ADC_Cb_Flag_Opt ¬Ú SPI_CB_FLAG_INT LÚ SPI_CB_FLAG_DMA eÚ SPI_CbFlagOpt JÚ UART_CallbackFunc «Ú I2C_CallbackFunc +Ú SPI_CallbackFunc ýÚ ADC_CallbackFunc !Ú P GPIO_P0_PIN_NUM
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Ú P GPIO_P1_PIN_NUM Ú P GPIO_P2_PIN_NUM Ú P GPIO_P3_PIN_NUM Ú P GPIO_INTEN_MASK_BASE Ú P GPIO_INTTYPE_MASK_BASE ßÚ P0_0 æÚ P0_1 åÚ P0_2 äÚ P0_3 ãÚ P0_4 âÚ P0_5 áÚ P0_6 àÚ P0_7 ßÚ P1_0 åÚ P1_1 äÚ P1_2 ãÚ P1_3 âÚ P1_4 áÚ P1_5 àÚ P1_6 ßÚ P1_7 ÞÚ P2_0 äÚ P2_1 ãÚ P2_2 âÚ P2_3 áÚ P2_4 àÚ P2_5 ßÚ P2_6 ÞÚ P2_7 ÝÚ P3_0 ãÚ P3_1 âÚ HAL_GPIO_PinId OÚ$ HAL_GPIO_MODE_INPUT_DIGITAL Ú# HAL_GPIO_MODE_INPUT_ANALOG âÚ& HAL_GPIO_MODE_OUTPUT_PUSHPULL °Ú' HAL_GPIO_MODE_OUTPUT_OPENDRAIN Ú* "HAL_GPIO_MODE_QUASI_BIDIRECTIONAL ÚÚ HAL_GPIO_Mode Ú HAL_GPIO_PULL_DISABLE Ú HAL_GPIO_PULL_UP ÚÚ HAL_GPIO_PULL_DOWN CÚ HAL_GPIO_Pull Ú HAL_GPIO_LEVEL_LOW NÚ HAL_GPIO_LEVEL_HIGH Ú HAL_GPIO_Level +Ú HAL_GPIO_INT_RISING ÿÚ HAL_GPIO_INT_FALLING ÌÚ HAL_GPIO_INT_BOTH_EDGE $Ú HAL_GPIO_INT_HIGH ¯Ú HAL_GPIO_INT_LOW ßÚ HAL_GPIO_INT_DISABLE ÕÚ HAL_GPIO_IntMode oÚ HAL_GPIO_CallbackFunc |Ú < hHAL_GPIO_CallbackArray kÚ 8
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<unnamed> QÚ "" ¢6mode ,Ú "" ¢6pull Ú "" ¢6level ºÚ HAL_GPIO_InitTypeDef ÒÚ 8
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<unnamed> QÚ "" §6intMode öÚ " §6 callbackFunc Ú "" §6 debounce Ú HAL_GPIO_IntInitTypeDef ¡Ú ," pinID ìÚ , initStruct Ú HAL_GPIO_Init xÚ ," pinID ìÚ ," level ¨Ú HAL_GPIO_WritePin ÒÚ ," pinID ìÚ HAL_GPIO_ReadPin cÚ ," pinID ìÚ HAL_GPIO_TogglePin yÚ ," pinID ìÚ ," pull Ú HAL_GPIO_SetPull =Ú ," pinID ìÚ HAL_GPIO_DeInit ËÚ ," pinID ìÚ , intInitStruct SÚ HAL_GPIO_InterruptInit Ú ,
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pinID Ú ," intMode éÚ HAL_GPIO_SetIntMode $Ú ,
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pinID Ú ," debounce uÚ HAL_GPIO_SetIntDebounce |Ú P __PAN_HAL_UART_H__ ÖÚ HAL_UART_CB_TX_EMPTY Ú HAL_UART_CB_TX_FULL æÚ HAL_UART_CB_LINE_ERROR Ú HAL_UART_CB_TX_FINISH TÚ HAL_UART_CB_MODEM ¶Ú HAL_UART_CB_MAX FÚ UART_Callback_Type_Opt Ú# HAL_UART_INT_RECV_DATA_AVL ÅÚ HAL_UART_INT_THR_EMPTY ÜÚ! HAL_UART_INT_LINE_STATUS IÚ" HAL_UART_INT_MODEM_STATUS ýÚ HAL_UART_INT_ALL ëÚ HAL_UART_INT_DISABLE ÈÚ UART_Interrupt_Mode_Opt õÚ P UART_RX_BUF_SIZE Ú P UART_TX_BUF_SIZE Ú < uartRxBuffer RÚ < uartTxBuffer PÚ
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uartRxBufIdx Ú
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uartTxBufIdx Ú uartTxDone àÚ uartAddrRcvd $Ú uartRxIntFlag ½Ú HAL_UART_FMT_5_N_1 RÚ HAL_UART_FMT_5_N_1_5 ºÚ HAL_UART_FMT_5_E_1 [Ú HAL_UART_FMT_5_E_1_5 ÃÚ HAL_UART_FMT_5_O_1 QÚ HAL_UART_FMT_5_O_1_5 ¹Ú HAL_UART_FMT_5_S_1 MÚ HAL_UART_FMT_5_S_1_5 µÚ HAL_UART_FMT_5_M_1 SÚ HAL_UART_FMT_5_M_1_5 »Ú HAL_UART_FMT_6_N_1 QÚ HAL_UART_FMT_6_N_2 PÚ HAL_UART_FMT_6_E_1 ZÚ HAL_UART_FMT_6_E_2 YÚ HAL_UART_FMT_6_O_1 PÚ HAL_UART_FMT_6_O_2 OÚ HAL_UART_FMT_6_S_1 LÚ HAL_UART_FMT_6_S_2 KÚ HAL_UART_FMT_6_M_1 RÚ HAL_UART_FMT_6_M_2 QÚ HAL_UART_FMT_7_N_1 PÚ HAL_UART_FMT_7_N_2 OÚ HAL_UART_FMT_7_E_1 YÚ HAL_UART_FMT_7_E_2 XÚ HAL_UART_FMT_7_O_1 OÚ HAL_UART_FMT_7_O_2 NÚ HAL_UART_FMT_7_S_1 KÚ HAL_UART_FMT_7_S_2 JÚ HAL_UART_FMT_7_M_1 QÚ HAL_UART_FMT_7_M_2 PÚ HAL_UART_FMT_8_N_1 OÚ HAL_UART_FMT_8_N_2 NÚ HAL_UART_FMT_8_E_1 XÚ HAL_UART_FMT_8_E_2 WÚ HAL_UART_FMT_8_O_1 NÚ HAL_UART_FMT_8_O_2 MÚ HAL_UART_FMT_8_S_1 JÚ HAL_UART_FMT_8_S_2 IÚ HAL_UART_FMT_8_M_1 PÚ HAL_UART_FMT_8_M_2 OÚ UART_Format_Opt MÚ 8
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<unnamed> QÚ
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"
7 baudRate ÕÚ ""
7format cÚ UART_Init_Opt &Ú 8
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<unnamed> QÚ " 7 switchFlag ðÚ " 7interruptMode Ú "" 7 callbackTyp tÚ " 7 callbackFunc *Ú UART_Interrupt_Opt ãÚ 8
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<unnamed> QÚ " 7pUartx eÚ " 7initObj Ú " 7 interruptObj ÍÚ " 7 pTxBuffPtr ìÚ " 7 txXferSize ÑÚ " 7 txXferCount aÚ " 7 pRxBuffPtr îÚ " 7 rxXferSize ÓÚ " 7 rxXferCount cÚ "" 7IRQn Ú " 7rxIntCallback ¹Ú " 7txIntCallback ·Ú
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" 7dmaSrc Ú
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" 7dmaDst Ú
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" 7
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errorCode LÚ UART_HandleTypeDef EÚ P
|
UART0_OBJ Ú P
|
UART1_OBJ Ú < xUART_Handle_Array îÚ , pUart »Ú HAL_UART_Init kÚ , pUart »Ú , pBuf <Ú ,
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size Ú HAL_UART_SendData óÚ , pUart »Ú , pBuf <Ú ,
|
size Ú ,
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timeout ÊÚ HAL_UART_ReceiveData ´Ú , pUart »Ú , pBuf <Ú ,
|
size Ú , callback Ú HAL_UART_SendData_INT ¡Ú , pUart »Ú , pBuf <Ú ,
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size Ú ,
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timeout ÊÚ , callback Ú! HAL_UART_ReceiveData_INT bÚ , pUart »Ú , pBuf <Ú ,
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size Ú , callback Ú HAL_UART_SendData_DMA ºÚ , pUart »Ú , pBuf <Ú ,
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size Ú ,
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timeout ÊÚ , callback Ú! HAL_UART_ReceiveData_DMA {Ú , pUart »Ú HAL_UART_Init_INT Ú UART0_IRQHandler SÚ UART1_IRQHandler RÚ
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,
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t iÚ HAL_DelayMs ïÚ P __PAN_HAL_DMAC_H__ ýÚ DMAC_Peri_UART BÚ DMAC_Peri_I2C ÂÚ DMAC_Peri_SPI Ú DMAC_Peri_ADC ¸Ú DMAC_Peri_Mode_Opt cÚ 8
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<unnamed> QÚ " Ð7dma |Ú " Ð7
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ConfigTmp Ú " Ð7 Callback Ú " Ð7 XferFlag ªÚ " Ð7 CallbackUart óÚ " Ð7 CallbackI2c ³Ú " Ð7 CallbackSpi eÚ " Ð7 CallbackAdc Ú "" Ð7 PeriMode Ú " Ð7 pBuffPtr {Ú " Ð7 XferSize Ú DMAC_HandleTypeDef lÚ P DMAC_CHANNEL_NUMS Ú < pDMAC_Channel_Array ®Ú P DMAC_Channel_1 òÚ P DMAC_Channel_2 ñÚ P DMAC_Channel_3 ðÚ dma_uart2mem_config $Ú dma_mem2uart_config $Ú dma_spi2mem_config Ú dma_mem2spi_config Ú dma_mem2i2c_config äÚ dma_i2c2mem_config äÚ dma_adc2mem_config ºÚ dma_mem2i2c_u16_config ¡Ú HAL_DMA_Init ×Ú DMA_IRQHandler ñÚ P _PAN_HAL_SPI_H_ êÚ P SPI_RX_BUF_SIZE âÚ P SPI_TX_BUF_SIZE àÚ 8
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<unnamed> QÚ "" ï7Mode Ú SPI_InterruptOptDef Ú BAUDRATE_100K `Ú BAUDRATE_500K \Ú BAUDRATE_1M ÂÚ BAUDRATE_2M ÁÚ BAUDRATE_5M ¾Ú BAUDRATE_10M Ú SPI_BaudRate Ú 8
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<unnamed> QÚ "" ù7role ÊÚ "" ù7 dataSize ?Ú "" ù7 clkPolarity àÚ "" ù7 clkPhase IÚ "" ù7 baudrateDiv Ú "" ù7format ïÚ SPI_InitOptDef ÄÚ SPI_STAT_NULL ÂÚ SPI_STAT_RX WÚ SPI_STAT_TX UÚ SPI_STAT_RXTX §Ú SPI_XferStatOpt 4Ú 8
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<unnamed> QÚ " 8pSpix ßÚ " 8initObj Ú "" 8 xferStat Ú " 8 interruptObj ÜÚ " 8 pTxBuffPtr ôÚ " 8 txXferSize ÙÚ " 8 txXferCount iÚ " 8 pRxBuffPtr öÚ " 8 rxXferSize ÛÚ " 8 rxXferCount kÚ "" 8IRQn Ú " 8rxIntCallback ÁÚ " 8txIntCallback ¿Ú
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" 8dmaSrc ¥Ú
|
" 8dmaDst ¢Ú
|
" 8
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errorCode TÚ SPI_HandleTypeDef Ú < hspiHandleArray ²Ú P SPI0_OBJ eÚ P SPI1_OBJ dÚ , pSpi -Ú HAL_SPI_Init ½Ú , pSpi -Ú HAL_SPI_DeInit Ú , pSpi -Ú HAL_SPI_Init_INT kÚ , pSpi -Ú HAL_SPI_DeInit_INT ¾Ú , pSpi -Ú , pBuf <Ú ,
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size Ú ,
|
timeout ÊÚ HAL_SPI_SendData EÚ , pSpi -Ú , pBuf <Ú ,
|
size Ú ,
|
timeout ÊÚ HAL_SPI_ReceiveData Ú , pSpi -Ú , pSendBuf ªÚ ,
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sendBufSize gÚ , pRecvBuf ¤Ú ,
|
recvBufSize aÚ HAL_SPI_SendReceiveData tÚ , pSpi -Ú , pBuf <Ú ,
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size Ú , callback Ú HAL_SPI_SendData_INT óÚ , pSpi -Ú , pBuf <Ú ,
|
size Ú , callback Ú HAL_SPI_ReceiveData_INT ´Ú , pSpi -Ú , pSendBuf ªÚ ,
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sendBufSize gÚ , sendCallback Ú , pRecvBuf ¤Ú ,
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recvBufSize aÚ , recvCallback üÚ$ HAL_SPI_SendReceiveData_INT "Ú , pSpi -Ú , pBuf <Ú ,
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size Ú , callback Ú HAL_SPI_SendData_DMA Ú , pSpi -Ú , pBuf <Ú ,
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size Ú , callback Ú HAL_SPI_ReceiveData_DMA ÍÚ , pSpi -Ú , pSendBuf ªÚ ,
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sendBufSize gÚ , sendCallback Ú , pRecvBuf ¤Ú ,
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recvBufSize aÚ , recvCallback üÚ$ HAL_SPI_SendReceiveData_DMA ;Ú P __PAN_HAL_I2C_H Ú I2C_ADDR_7BIT 6Ú I2C_ADDR_10BIT
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Ú I2C_AddressMode_Opt áÚ I2C_ROLE_MASTER eÚ I2C_ROLE_SLAVE ¸Ú I2C_Role_Opt ¨Ú I2C_DUTYCYCLE_16_9 ¨Ú I2C_DUTYCYCLE_2 {Ú I2C_DutyCycle_Opt Ú I2C_DIR_TX âÚ I2C_DIR_RX äÚ I2C_Direction_Opt Ú I2C_ACK_ADDR_7BIT Ú I2C_ACK_ADDR_10BIT ÔÚ I2C_AckAddr_Opt ªÚ I2C_SPEED_100K Ú I2C_SPEED_200K Ú I2C_SPEED_400K Ú I2C_SPEED_500K Ú I2C_SPEED_1M zÚ I2C_SPEED_2M yÚ I2C_ClockSpeed_Opt QÚ 8
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<unnamed> QÚ "" î8 ClockSpeed Ú "" î8Role ôÚ "" î8
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DutyCycle åÚ " î8 OwnAddress Ú "" î8 AckAddress ¤Ú "" î8 AddressMode -Ú I2C_Init_Opt ¦Ú I2C_Tx_Dir Ú I2C_Rx_Dir Ú I2C_Xfer_Dir_Opt Ú 8
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<unnamed> QÚ " ù8pass àÚ I2C_Interrupt_Opt cÚ 8
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<unnamed> QÚ " ü8I2Cx IÚ " ü8 I2C_InitObj Ú " ü8 InterruptObj Ú " ü8 pTxBuffPtr ~Ú " ü8 TxXferSize Ú " ü8 TxXferCount Ú " ü8 pRxBuffPtr Ú " ü8 RxXferSize
Ú " ü8 RxXferCount Ú "" ü8IRQn Ú " ü8RxIntCallback kÚ " ü8TxIntCallback iÚ
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" ü8DMA_SRC nÚ
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" ü8DMA_DST kÚ " ü8 StopFlag lÚ I2C_HandleTypeDef ÅÚ , i2c ÍÚ HAL_I2C_Init ëÚ , i2c ÍÚ HAL_I2C_DeInit >Ú , i2c ÍÚ HAL_I2C_Init_INT Ú , i2c ÍÚ HAL_I2C_DeInit_INT ìÚ , i2c ÍÚ , DevAddress äÚ , Buf ®Ú ,
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Size <Ú ,
|
Timeout êÚ HAL_I2C_Master_SendData Ú , i2c ÍÚ , DevAddress äÚ , Buf ®Ú ,
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Size <Ú ,
|
Timeout êÚ# HAL_I2C_Master_ReceiveData [Ú , i2c ÍÚ , DevAddress äÚ , Buf ®Ú ,
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Size <Ú , Callback ´Ú$ HAL_I2C_Master_SendData_INT HÚ , i2c ÍÚ , DevAddress äÚ , Buf ®Ú ,
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Size <Ú , Callback ´Ú' HAL_I2C_Master_ReceiveData_INT Ú , i2c ÍÚ , DevAddress äÚ , Buf ®Ú ,
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Size <Ú , Callback ´Ú$ HAL_I2C_Master_SendData_DMA aÚ , i2c ÍÚ , DevAddress äÚ , Buf ®Ú ,
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Size <Ú , Callback ´Ú' HAL_I2C_Master_ReceiveData_DMA "Ú , i2c ÍÚ , Buf ®Ú ,
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Size <Ú ,
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Timeout êÚ HAL_I2C_Slave_SendData Ú , i2c ÍÚ , Buf ®Ú ,
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Size <Ú ,
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Timeout êÚ" HAL_I2C_Slave_ReceiveData ÎÚ , i2c ÍÚ , Buf ®Ú ,
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Size <Ú , Callback ´Ú# HAL_I2C_Slave_SendData_INT »Ú , i2c ÍÚ , Buf ®Ú ,
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Size <Ú , Callback ´Ú& HAL_I2C_Slave_ReceiveData_INT |Ú , i2c ÍÚ , Buf ®Ú ,
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Size <Ú , Callback ´Ú# HAL_I2C_Slave_SendData_DMA ÔÚ , i2c ÍÚ , Buf ®Ú ,
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Size <Ú , Callback ´Ú& HAL_I2C_Slave_ReceiveData_DMA Ú P __PAN_HAL_WDT_H çÚ 8
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<unnamed> QÚ "" Ø9Timeout Ú "" Ø9 ResetDelay Ú
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" Ø9 ClockSource EÚ
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" Ø9 ResetSwitch -Ú
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" Ø9 WakeupSwitch ÁÚ WDT_Init_Opt uÚ WDT_CallbackFunc úÚ 8
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<unnamed> QÚ " à9 CallbackFunc ñÚ WDT_Interrupt_Opt 2Ú , wdt |Ú HAL_WDT_Init ºÚ HAL_WDT_DeInit Ú , wdt |Ú HAL_WDT_Feed ÚÚ , opt xÚ HAL_WDT_Init_INT hÚ HAL_WDT_DeInit_INT »Ú WDT_IRQHandler ÔÚ P __PAN_HAL_WWDT_H Ú WWDT_CallbackFunc ¡Ú 8
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<unnamed> QÚ "" î9
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Prescaler ÙÚ
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" î9 ClockSource /Ú
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" î9 CmpValue uÚ WWDT_Init_Opt Ú 8
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<unnamed> QÚ " ó9 CallbackFunc ÞÚ WWDT_Interrupt_Opt ÙÚ , wwdt Ú HAL_WWDT_Init aÚ HAL_WWDT_DeInit ´Ú , wwdt Ú HAL_WWDT_Feed Ú , wwdt Ú HAL_WWDT_Init_INT Ú HAL_WWDT_DeInit_INT bÚ WWDT_IRQHandler {Ú P __PAN_HAL_PWM_H âÚ PWM0_CH0 ¯Ú PWM0_CH1 ®Ú PWM0_CH2 Ú PWM0_CH3 ¬Ú PWM0_CH4 «Ú PWM0_CH5 ªÚ PWM0_CH6 ©Ú PWM0_CH7 ¨Ú PWM_ChId FÚ PWM_MODE_INDEPENDENT ÐÚ PWM_MODE_COMPLEMENTARY Ú PWM_MODE_SYNCHRONIZED \Ú PWM_MODE_GROUP }Ú PWM_ModeOpt àÚ 8
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<unnamed> QÚ
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" :
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frequency Ú
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" :
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dutyCycle 9Ú "" : operateType DÚ "" :mode >Ú " : inverter Ú " : lowPowerEn âÚ PWM_InitOpt ÑÚ! P HAL_PWM_PinConfiguration Ú ," chId JÚ , pInitObj ¢Ú HAL_PWM_Init µÚ ,
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handle gÚ HAL_PWM_DeInit Ú ,
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handle gÚ HAL_PWM_Start 9Ú ,
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handle gÚ , force ÍÚ HAL_PWM_Stop £Ú ,
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handle gÚ ,
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frequency ûÚ ,
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dutyCycle Ú HAL_PWM_SetFreqAndDuty ÂÚ P __PAN_HAL_TIMER_H QÚ TIMER_CB_FLAG_CNT ¹Ú TIMER_CB_FLAG_CAP ÊÚ TIMER_CB_FLAG_WK þÚ TIMER_Cb_Flag_Opt ïÚ TIMER_CallbackFunc dÚ TIMER_MODE_BASECNT uÚ TIMER_MODE_EVENTCNT Ú TIMER_MODE_INCAP Ú TIMER_MODE_WAKEUP ªÚ TIMER_Mode_Opt îÚ 8
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<unnamed> QÚ " °:pass 'Ú TIMER_Interrupt_Opt Ú 8
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<unnamed> QÚ
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" ³:freq &Ú "" ³:mode Ú "" ³:cntMode ìÚ "" ³:capMode ÿÚ
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" ³: cmpValue Ú "" ³:capEdge Ú "" ³: evtCntEdge ÊÚ "" ³:capSrc \Ú
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" ³: prescale }Ú "" ³: tmr0CmpSel ìÚ TIMER_Init_Opt ßÚ 8
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<unnamed> QÚ " ¿:TIMERx ½Ú " $¿:initObj ÁÚ " ¿: interruptObj ¡Ú "" ¿:IRQn YÚ " ¿: callback
Ú TIMER_HandleTypeDef þÚ P TIMER0_OBJ ÌÚ P TIMER1_OBJ ËÚ P TIMER2_OBJ ÊÚ < TIMER_Handle_Array Ú HAL_TIMER_US_TO_CNT ÌÚ ,
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" Ê:timeUs 6Ú ,(" Ê:
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frequency ³Ú (" Ê:cnt pÚ HAL_TIMER_MS_TO_CNT ÔÚ ,
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" Î:timeMs :Ú ,(" Î:
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frequency ¯Ú (" Î:cnt lÚ , pTimer TÚ HAL_TIMER_Init $Ú , pTimer TÚ HAL_TIMER_DeInit wÚ , pTimer TÚ HAL_TIMER_Init_INT ÒÚ , pTimer TÚ HAL_TIMER_DeInit_INT %Ú , pTimer TÚ HAL_TIMER_Start ¨Ú , pTimer TÚ HAL_TIMER_Stop Ú , pTimer TÚ HAL_TIMER_GetRealFreq xÚ P __PAN_HAL_ADC_H Ú ADC_MODE_CONV Ú ADC_MODE_EXTRIG aÚ ADC_MODE_COMPARE +Ú ADC_MODE_PWMSEQ WÚ ADC_MODE_SGLCONVSEQ 'Ú ADC_ModeOpt Ú ADC_CONV_MODE_BASE ~Ú ADC_CONV_MODE_TEMP cÚ ADC_CONV_MODE_VBG ¼Ú ADC_CONV_MODE_VDD4 Ú ADC_ConvertModeOpt Ú ADC_CH0 Ú ADC_CH1 Ú ADC_CH2 Ú ADC_CH3
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Ú ADC_CH4 Ú ADC_CH5 Ú ADC_CH6 Ú ADC_CH7 Ú ADC_CH_TEMP Ú ADC_CH_BATTERY µÚ ADC_IDLE ¨Ú ADC_ChId rÚ ADC_INPUT_RANGE_LOW Ú ADC_INPUT_RANGE_HIGH ÓÚ ADC_InputRangeOpt Ú 8
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<unnamed> QÚ "" û: InputRange nÚ "" û:Mode òÚ ADC_InitOpt ýÚ 8
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<unnamed> QÚ " ÿ:initOpt Ú "" ÿ:id ªÚ ADC_HandleTypeDef »Ú , pADC Ú HAL_ADC_Init áÚ , pADC Ú HAL_ADC_DeInit 4Ú , pADC Ú , value ªÚ HAL_ADC_GetValue PÚ PAN_HAL_SUCCESS TÚ PAN_HAL_INVALID_PARAMS 5Ú PAN_HAL_IO_ERROR êÚ PAN_HAL_DEVICE_BUSY Ú PAN_HAL_NO_MEM Ú# PAN_HAL_NO_HARDWARE_SOURCE ÝÚ PAN_HAL_UNKNOWN =Ú PanHalError Ú P PRI_RF_MODE_SEL_TX óÚ P PRI_RF_MODE_SEL_RX õÚ P PRI_RF_MODE_SEL_TRX Ú P PRI_RF_ADDR_BYTE_LEN_2 áÚ P PRI_RF_ADDR_BYTE_LEN_3 àÚ P PRI_RF_ADDR_BYTE_LEN_4 ßÚ P PRI_RF_ADDR_BYTE_LEN_5 ÞÚ! P PRI_RF_CHIP_MODE_INVALID LÚ P PRI_RF_CHIP_MODE_BLE Ú P PRI_RF_CHIP_MODE_297 ¹Ú P PRI_RF_CHIP_MODE_NORDIC Ú P REG_FILE_OFST ¹Ú P SEQ_RAM_OFST ðÚ P LIST_RAM_OFST Ú P TX_RX_RAM_OFST Ú P CTE_IQ_RAM_OFST þÚ P LLHWC_READ32_REG Ú P LLHWC_WRITE32_REG £Ú P READ_4_BYTES Ú P PRI_RF_WRITE_REG_VALUE ºÚ P PRI_RF_READ_REG_VALUE +Ú P PRI_RF_SET_FUNC_ENABLE áÚ! PRI_RF_AutoAnlsPayloadEn ßÚ ," ¨;rf ðÚ ,"" ¨; NewState Ú PRI_RF_CrcCheckEn èÚ ," «;rf íÚ ,"" «; NewState Ú PRI_RF_Crc16Select °Ú ," ®;rf êÚ ,"" ®; NewState Ú PRI_RF_ScambleEn )Ú ," ±;rf çÚ ,"" ±; NewState Ú PRI_RF_NordicEnhanceEn ÃÚ ," ´;rf äÚ ,"" ´; NewState ~Ú PRI_RF_IsNordicEnhance ºÚ ," ·;rf áÚ PRI_RF_EnhanceEn .Ú ," ¹;rf ßÚ ,"" ¹; NewState yÚ PRI_RF_IsEnhance %Ú ," ¼;rf ÜÚ PRI_RF_BandWidth2mSel QÚ ," ¾;rf ÚÚ ,"" ¾; NewState tÚ PRI_RF_ChipModeSel bÚ ," Á;rf ×Ú ," Á;modeSel ñÚ PRI_RF_GetChipMode fÚ ," Ä;rf ÔÚ PRI_RF_RxAckEn Ú ," Æ;rf ÒÚ ,"" Æ; NewState lÚ PRI_RF_IsRxAckEn KÚ ," É;rf ÏÚ PRI_RF_TxNoAckEn HÚ ," Ë;rf ÍÚ ,"" Ë; NewState gÚ PRI_RF_IsTxNoAckEn Ú ," Î;rf ÊÚ PRI_RF_TrxFuncSel £Ú ," Ð;rf ÈÚ ,"" Ð; NewState bÚ PRI_RF_IsRxSel íÚ ," Ó;rf ÅÚ PRI_RF_ClearAllIrqEn ¬Ú ," Õ;rf ÃÚ ,"" Õ; NewState ]Ú PRI_RF_IntMask àÚ ," Ø;rf ÀÚ ,
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" Ø;msk YÚ ,"" Ø; NewState ZÚ PRI_RF_IntFlag òÚ ," Ü;rf ¼Ú ,
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" Ü;msk UÚ PRI_RF_ForceExitRx <Ú ," ß;rf ¹Ú ,"" ß; NewState SÚ# PRI_RF_SetTrxTransWaitTime éÚ ," â;rf ¶Ú ," â;time çÚ PRI_RF_EnableRxPipeAdr ÑÚ ," å;rf ³Ú ," å;pipe åÚ ,"" å; NewState MÚ PRI_RF_SetRxGoon
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Ú ," é;rf ¯Ú ," é;en_flag ÆÚ PRI_RF_SetAddrMatchBit ÔÚ ," ì;rf ¬Ú ," ì;value vÚ PRI_RF_SetPayloadEndian @Ú ," ï;rf ©Ú ," ï;endian Ú PRI_RF_MultiPreamble XÚ ," ò;rf ¦Ú ," ò; pre_length [Ú PRI_RF_StopRx )Ú ," õ;rf £Ú ," õ;en_flag ºÚ PRI_RF_RandomNumGenInit FÚ ," ø;rf Ú" PRI_RF_RandomNumGenReinit kÚ ," ú;rf Ú PRI_RF_GetRandomNum ÜÚ ," ü;rf Ú ana_prf_ldo_en %Ú ana_prf_ldo_dis ¶Ú , rf õÚ , mode 9Ú , len ¡Ú PRI_RF_SetTrxPayloadLen &Ú , rf õÚ , len ¡Ú PRI_RF_SetAddrByteLen #Ú , rf õÚ , mode 9Ú , pid £Ú PRI_RF_SetPidManual ÚÚ , rf õÚ , time &Ú PRI_RF_SetRxWaitTime eÚ , rf õÚ , mode 9Ú , pipe 0Ú , addr .Ú PRI_RF_SetTrxAddr Ú , rf õÚ , mode 9Ú ,
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addr <Ú" PRI_RF_SetTrxRamStartAddr bÚ , rf õÚ , mode 9Ú PRI_RF_IsTrxRamReady pÚ , rf õÚ , mode 9Ú , ready ÇÚ PRI_RF_SetTrxRamReady þÚ P __PRI_RHY_H__ QÚ 8"
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tx_rx_phy ÈÚ " < LE_NO_CHANGE VÚ " <LE_1M Ú " <LE_2M Ú " < LE_CODED_S8 ±Ú " < LE_CODED ¡Ú " <LE_250K Ú 8" llhw_phy_strt_stp_phy Ú " ¦<LLHWC_PHY_START $Ú " ¦<LLHWC_PHY_STOP nÚ llhw_phy_strt_stp_phy_e Ú
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PHY_reset cÚ , chan DÚ PHY_SetChConfig MÚ PHY_init ÔÚ ," phy sÚ PHY_SetTrxSeq_prf_LR 9Ú ," phy sÚ PHY_SetTrxSeq_prf_250K ñÚ , phy Ú , tx1rx0 £Ú phy_time_cfg âÚ PHY_ResetChannel ¼Ú ,"
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phy_state çÚ PHY_strt_stp ýÚ , command äÚ ,
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cmd_len ÿÚ , ptr_rsp_value 1Ú PHY_WriteCfgFifoBatch íÚ , tx_pwr 8Ú PHY_set_tx_pwr -Ú PHY_SeqRamInit Ú , reduce_flag _Ú$ panchip_prf_reduce_trx_time Ú < init_slp [Ú < init_stdby Ú < init_slp_to_stdby Ú < reset Ú < phy_init YÚ < pre_tx_interpacket Ú < pre_tx_interpacket_LR Ú < pre_tx_interpacket_2M :Ú < pre_tx_interpacket_250K ÓÚ < post_tx_interpacket Ú < pre_rx_interpacket Ú < pre_rx_interpacket_LR Ú < pre_rx_interpacket_2M <Ú < pre_rx_interpacket_250K ÕÚ < post_rx_interpacket Ú < pre_evnt ZÚ <
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post_evnt ÙÚ < channel_init ÉÚ < init_constant_tone Ú < init_pll_bw_cal Ú
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init_slp_size eÚ
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init_stdby_size Ú
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init_slp_to_stdby_size Ú
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reset_size ªÚ
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phy_init_size cÚ
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pre_tx_interpacket_size (Ú#
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pre_tx_interpacket_LR_size %Ú#
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pre_tx_interpacket_2M_size DÚ!
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post_tx_interpacket_size §Ú
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pre_rx_interpacket_size *Ú#
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pre_rx_interpacket_LR_size 'Ú#
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pre_rx_interpacket_2M_size FÚ!
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post_rx_interpacket_size ©Ú
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pre_evnt_size dÚ
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post_evnt_size ãÚ
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channel_init_size ÓÚ%
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pre_tx_interpacket_250K_size ÝÚ%
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pre_rx_interpacket_250K_size ßÚ
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init_constant_tone_size !Ú
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init_pll_bw_cal_size Ú phy_ch_cfg_reg ?Ú tx_pwr_cfg_reg Ú rssi_out_phy_reg_addrs ¤Ú P
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__ramfunc Ú P PRF_LL_IRQ_PRIORITY Ú P PRF_DATA_MAX_SIZE iÚ PRF_CHIP_MODE_SEL_BLE oÚ PRF_CHIP_MODE_SEL_XN297 öÚ PRF_CHIP_MODE_SEL_NRF \Ú prf_chip_mode_sel_t Ú 8" PRF_ADDR_LENGTH_SEL ÓÚ " ó<PRF_ADDR_LENGTH_SEL_3 *Ú " ó<PRF_ADDR_LENGTH_SEL_4 )Ú " ó<PRF_ADDR_LENGTH_SEL_5 (Ú prf_addr_length_sel_t >Ú 8" PRF_CRC_SEL GÚ " ø<PRF_CRC_SEL_NOCRC OÚ " ø<PRF_CRC_SEL_CRC8 ¶Ú " ø<PRF_CRC_SEL_CRC16
Ú " ø<PRF_CRC_SEL_CRC24 Ú prf_crc_sel_t Ú 8" PRF_SCRAMBLE_SEL ÌÚ " þ<PRF_SRC_SEL_NOSRC )Ú " þ<PRF_SRC_SEL_EN !Ú prf_scramble_sel_t wÚ 8" PRF_MODE CÚ " =PRF_MODE_NORMAL jÚ " =PRF_MODE_ENHANCE ?Ú " =PRF_MODE_NORMAL_M1 Ú prf_mode_t ÎÚ 8" PRF_PHY yÚ " = PRF_PHY_1M îÚ " = PRF_PHY_2M íÚ " =PRF_PHY_CODED_S8 Ú " =PRF_PHY_CODED Ú " = PRF_PHY_250K Ú
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prf_phy_t $Ú 8" PRF_TRX_MODE ÞÚ " = PRF_TX_MODE Ú " = PRF_RX_MODE
Ú prf_trx_mode_t Ú 8" PRF_MODE_CONF_SEL iÚ " = PRF_BLE_CONF UÚ " = PRF_NRF_CONF BÚ " =PRF_G_250k_CONF zÚ " =PRF_B_250K_CONF Ú prf_mode_conf_sel_t Ú 8" PRF_PIPE :Ú " =
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PRF_PIPE0 OÚ " =
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PRF_PIPE1 NÚ " =
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PRF_PIPE2 MÚ " =
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PRF_PIPE3 LÚ " =
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PRF_PIPE4 KÚ " =
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PRF_PIPE5 JÚ " =
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PRF_PIPE6 IÚ " =
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PRF_PIPE7 HÚ prf_pipe_t ÅÚ 8" PRF_TRANSFER_TYPE PÚ " ¢=PRF_TRF_NORMAL
Ú " ¢=PRF_TRF_NRF52 Ú " ¢=PRF_TRF_B250K ,Ú
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prf_trf_t )Ú 8" PRF_ENC_DEC_MODE ÓÚ " §=PRF_ENCRYPT_MODE çÚ " §=PRF_DECRYPT_MODE ñÚ prf_enc_dec_mode_t Ú 8
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<unnamed> QÚ
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" «= data_length PÚ <" ÿ«=data Ú panchip_prf_payload_t 1Ú 8
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<unnamed> QÚ "" ¯=
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work_mode ïÚ "" ¯=
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chip_mode Ú "" ¯= trx_mode VÚ "" ¯=phy qÚ "" ¯=crc Ú "" ¯=src zÚ "" ¯=
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mode_conf Ú " ¯= rx_timeout wÚ " ¯= rf_channel ·Ú " ¯=
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tx_no_ack Ú "" ¯= trf_type KÚ " ¯=
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rx_length Ú " ¯= sync_length 0Ú <" ¯=sync åÚ " ¯= tx_power ^Ú " ¯=pid_manual_flag ³Ú " ¯=crc_include_sync -Ú " ¯=src_include_sync Ú "" ¯=pipe Ú pan_prf_config_t SÚ RRF_CallbackFunc ÿÚ 8
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<unnamed> QÚ " Å=tx_cb Ú " Å=rx_timeout_cb +Ú " Å=rx_cb ¡Ú " Å=rx_crc_err_cb RÚ " Å=rx_len_err_cb KÚ " Å=rx_acc_adr_err_cb ÅÚ " Å=rx_pid_err_cb MÚ pan_prf_callback_t Ú 8
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<unnamed> QÚ
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" Î=major Ú
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" Î=minor Ú
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" Î=patch ¤Ú
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" Î=
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commit_id ÷Ú pan_prf_version_t ÁÚ$ P SLPTMR1_SLPTMR_CMPR_BUS_ENA 4Ú( P SLPTMR1_SLPTMR_CMPR_BUS_ENA_MSK âÚ) P !SLPTMR1_SLPTMR_CMPR_BUS_ENA_SHFT Ú+ P #SLPTMR2_SLPTMR_CMPR_STRT_EVENT_DIN ÚÚ$ P SLPTMR4_SLPTMR_CMPR_BUS_DIN *Ú P CTRL_PM_PWR_STATE @Ú P CTRL_PM_PWR_STATE_MSK îÚ P CTRL_PM_PWR_STATE_SHFT ¢Ú P CTRL_PWR_MOD çÚ P CTRL_PWR_MOD_MSK Ú P CTRL_PWR_MOD_SHFT IÚ P CTRL_MEM_SOFT_RST_N Ú P CTRL_MEM_SOFT_RST_N_MSK @Ú! P CTRL_MEM_SOFT_RST_N_SHFT ôÚ P SLPTMR1_SLPTMR_REST_N Ú" P SLPTMR1_SLPTMR_REST_N_MSK ±Ú# P SLPTMR1_SLPTMR_REST_N_SHFT eÚ P SLPTMR1_SLPTMR_ENA Ú P SLPTMR1_SLPTMR_ENA_MSK ÎÚ P SLPTMR1_SLPTMR_ENA_SHFT Ú! P DSLP1_LL_PHY_DRIVER_NRST Ú% P DSLP1_LL_PHY_DRIVER_NRST_MSK ÍÚ& P DSLP1_LL_PHY_DRIVER_NRST_SHFT Ú+ P #SLPTMR1_SLPTMR_CMPR_STRT_EVENT_ENA âÚ/ P 'SLPTMR1_SLPTMR_CMPR_STRT_EVENT_ENA_MSK Ú0 P (SLPTMR1_SLPTMR_CMPR_STRT_EVENT_ENA_SHFT DÚ/ P 'SLPTMR2_SLPTMR_CMPR_STRT_EVENT_DIN_MSK Ú0 P (SLPTMR2_SLPTMR_CMPR_STRT_EVENT_DIN_SHFT <Ú P SLPTMR3_SLPTMR_CURRENT ÇÚ# P SLPTMR3_SLPTMR_CURRENT_MSK uÚ$ P SLPTMR3_SLPTMR_CURRENT_SHFT )Ú P LLHWC_WRITE_MASK32_REG Ú P LLHWC_READ_MASK32_REG Ú" P LLHWC_READ_MASK32_REG_EXT 'Ú ,
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p_payload Ú panchip_prf_data_rec ¤Ú ,
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p_payload Ú panchip_prf_set_data Ú ,
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p_payload Ú! panchip_prf_set_ack_data üÚ , p_config |Ú panchip_prf_init +Ú panchip_prf_trx_start êÚ panchip_prf_module_init 8Ú panchip_prf_ble_resume °Ú , p_config |Ú panchip_switch_prf IÚ , rf_channel ¹Ú panchip_prf_set_chn õÚ , p_config |Ú# panchip_prf_trx_trans_time ØÚ& panchip_prf_isr_resume_ble_cb ÑÚ , prf_config Ú$ panchip_prf_dual_mode_start Ú panchip_prf_ble_handler aÚ panchip_prf_isr_proc vÚ panchip_prf_irq_enable ÁÚ , tx_pwr 8Ú panchip_prf_set_tx_pwr Ú , p_config |Ú" panchip_prf_module_enable Ú panchip_prf_get_version ,Ú ," conf Ú" panchip_prf_mode_conf_set xÚ ," phy sÚ panchip_prf_set_phy ÝÚ , value ¿Ú& panchip_prf_rx_length_irq_cfg ÀÚ ," trx_mode XÚ! panchip_prf_set_trx_mode ÂÚ ,"
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work_mode ñÚ" panchip_prf_set_work_mode [Ú , addr .Ú , len ¡Ú ," pipe Ú panchip_prf_set_addr Ú , flag DÚ! panchip_prf_set_tx_noack ÍÚ , time &Ú panchip_prf_rx_timeout Ú panchip_prf_rx_stop ÊÚ panchip_prf_reset ºÚ , prf_config Ú , pid £Ú panchip_prf_pid_cfg Ú , value ¿Ú! panchip_white_init_value ÆÚ , tx_channel ¥Ú" panchip_prf_carrier_start XÚ! panchip_prf_carrier_stop ÂÚ panchip_prf_enable_rssi JÚ! panchip_prf_disable_rssi ÛÚ panchip_prf_read_rssi Ú( panchip_prf_enable_carrier_rssi óÚ) !panchip_prf_disable_carrier_rssi Ú& panchip_prf_read_carrier_rssi ÂÚ panchip_prf_b250k_init \Ú panchip_prf_isr_init vÚ , idx Ú& panchip_prf_b250k_set_channel ~Ú , plain_text
Ú , plain_text_len ëÚ , key Ú , iv îÚ , encry_data £Ú ," enc_mode Ú$ panchip_prf_encrypt_decrypt jÚ% panchip_prf_rx_patch_handler 1Ú& panchip_prf_get_current_stamp Ú
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data_addr_tx Ú
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data_addr_rx Ú prf_rssi Ú
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rf_config Ú isr_cb SÚ wake_from_lp_mode æÚ P __INFO_H__ hÚ# P CONFIG_SIMULATE_WRITE_INFO ©Ú P CONFIG_UART_OUTPUT_INFO qÚ P INFO_VERSION_16_BITS Ú P INFO_TYPE_TX_PWR {Ú P INFO_TYPE_PHY_INIT ÷Ú! P INFO_TYPE_POST_TX_CONFIG Ú! P INFO_TYPE_POST_RX_CONFIG Ú$ P INFO_TYPE_PRE_TX_CONFIG_PRF Ú$ P INFO_TYPE_PRE_RX_CONFIG_PRF Ú' P INFO_TYPE_PRE_TX_CONFIG_2M_PRF 7Ú' P INFO_TYPE_PRE_RX_CONFIG_2M_PRF 9Ú# P INFO_TYPE_PRE_TX_CONFIG_LR gÚ# P INFO_TYPE_PRE_RX_CONFIG_LR iÚ) P !INFO_TYPE_PRE_TX_CONFIG_250K_PRF ÐÚ) P !INFO_TYPE_PRE_RX_CONFIG_250K_PRF ÒÚ" P INFO_TYPE_PRE_EVNT_CONFIG ÕÚ# P INFO_TYPE_POST_EVNT_CONFIG tÚ P INFO_TYPE_DCOC_LIMIT Ú P INFO_TYPE_CONSTANT_TONE rÚ P INFO_TYPE_MAX Ú P INFO_HEADER_LEN ;Ú P TLV_HEAD_LEN Ú P TLV_TYPE_LEN ÞÚ P TLV_LEN_LEN CÚ P INFO_TOTAL_LEN_MAX Ú P INFO_READ_BUFFER_LEN ¥Ú" P INFO_ITER_READ_BUFFER_LEN Ú P CRC_LEN §Ú P INFO_READ_OFFSET ÞÚ P INFO_READ_SIZE nÚ info_value_size Ú$ info_value_tlv_value_output IÚ , ptr uÚ ,
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len Ú send_raw_value ýÚ get_info_crc îÚ total_tlv_data_output ÜÚ , ptr uÚ ,
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len Ú send_uart_raw_value ØÚ) !info_value_tlv_value_uart_output $Ú# total_tlv_uart_data_output ·Ú check_info_tlv_data Ú start_overwrite_info AÚ start_read_info Ú start_read_1k_info Ú , type Ú , data /Ú , len Ú , offset JÚ info_read_from_type çÚ info_data_is_valid uÚ check_info_is_empyt ðÚ! phy_value_init_from_code ËÚ! phy_value_init_from_info ºÚ 8 tlv_item QÚ " ÿ>addr çÚ " ÿ>len EÚ < dcoc_init_limit_prf ÖÚ < @
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tlv_items ¤Ú g_phy_pre_tx_1M_ptr -Ú g_phy_pre_tx_2M_ptr ,Ú g_phy_pre_tx_LR_ptr Ú g_phy_pre_tx_250K_ptr ÅÚ g_phy_pre_rx_1M_ptr /Ú g_phy_pre_rx_2M_ptr .Ú g_phy_pre_rx_LR_ptr Ú g_phy_pre_rx_250K_ptr ÇÚ g_phy_post_tx_ptr Ú g_phy_post_rx_ptr Ú g_phy_pre_event_ptr ÔÚ g_phy_post_event_ptr SÚ g_phy_constant_tone_ptr Ú P CONFIG_USE_PRF_ISR_CB %Ú P XN297_RX_TO_TX_TIME ¹Ú! P XN297_RX_TO_TX_TIME_VICE )Ú P PRTX_SPI_TRANS_TIME Ú P PRTX_LEGENCY ÿÚ P PRTX_TRANS_TIME êÚ P XN297_TX_TO_RX_TIME ¹Ú! P XN297_TX_TO_RX_TIME_VICE )Ú P PTRX_SPI_TRANS_TIME Ú P PTRX_TRANS_TIME êÚ P NRF_RX_TO_TX_TIME Ú P NRF_TX_TO_RX_TIME Ú P REG_WRITE_BITS VÚ P __nop ¶Ú prf_delay_nop lÚ ,
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" ?times ³Ú prf_init_flag Ú buck_vout_trim Ú " >ptxprx ]Ú " >enhc yÚ " >
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normal_m1 Ú " >noack Ú P PRF_BLE_DUAL_MODE Ú LL_IRQHandler -Ú ," > p_config Ú ," > rf_channel ÕÚ
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" > channel_map Ú <" > cmd_channel oÚ __disable_irq Ú " > tmp_int_part ýÚ " >divider_ratio §Ú " >tmp_frac_part ¥Ú
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" >offset Ú <" > init_channel íÚ <" > init_vco_cal ïÚ <" >init_pll_bw_cal ±Ú " >idx ÛÚ <" > init_channel íÚ __enable_irq Ú ," ·>idx Ú <" ,·> channel_map Ú <" ·> cmd_channel <Ú " ·> tmp_int_part ÁÚ " ·>divider_ratio kÚ " ·>tmp_frac_part rÚ
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" ·>offset YÚ <" ·> init_channel ºÚ data_convert ÖÚ ," À?src bÚ ," À?dst _Ú ," À?iv ÍÚ " À?i ~Ú% panchip_prf_refresh_phy_page ,Ú ," Å?idx uÚ <" Å?cmd uÚ phy_page1_reg62_val ·Ú' panchip_set_phy_reg_before_wfi ZÚ
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" É? response ZÚ
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" É?value ²Ú <" É?ed_cmd CÚ <" É?cmd qÚ panchip_reload_phy_reg ¶Ú <" Î?cmd lÚ
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data_swap "Ú ," Ð?src RÚ " Ð?i nÚ " Ð? swap_var fÚ ," ¾> plain_text gÚ ," ¾>plain_text_len ÍÚ ," ¾>key dÚ ," ¾>iv ÐÚ ," ¾> encry_data
Ú ,"" ¾> enc_mode bÚ
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" ¾>plain_txt_ofst ÛÚ
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" ¾> key_ofst qÚ
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