/*
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* Copyright (c) 2020-2024 Shanghai Panchip Microelectronics Co.,Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _OS_LP_H_
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#define _OS_LP_H_
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#include <stdint.h>
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#include <Panseries.h>
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enum {
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SOC_RST_REASON_CHIP_RESET = 0,
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SOC_RST_REASON_PIN_RESET = 1,
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SOC_RST_REASON_WDT_RESET = 2,
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SOC_RST_REASON_LVR_RESET = 3,
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SOC_RST_REASON_BOD_RESET = 4,
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SOC_RST_REASON_SYS_RESET = 5,
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SOC_RST_REASON_POR_RESET = 6,
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SOC_RST_REASON_STBM0_EXTIO_WAKEUP = 10, /* P00/P01/P02 */
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SOC_RST_REASON_STBM1_SLPTMR0_WAKEUP = 11,
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SOC_RST_REASON_STBM1_SLPTMR1_WAKEUP = 12,
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SOC_RST_REASON_STBM1_SLPTMR2_WAKEUP = 13,
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SOC_RST_REASON_STBM1_GPIO_WAKEUP = 14, /* All GPIOs */
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SOC_RST_REASON_UNKNOWN_RESET = 255
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};
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enum {
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STBM1_WAKEUP_SRC_GPIO = BIT0,
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STBM1_WAKEUP_SRC_SLPTMR = BIT1,
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};
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enum {
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STBM1_RETENTION_SRAM_NONE = 0,
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STBM1_RETENTION_SRAM_BLOCK0 = BIT0, /* 32 KB */
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STBM1_RETENTION_SRAM_BLOCK1 = BIT1, /* 16 KB */
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STBM1_RETENTION_SRAM_DECRYPT = BIT2, /* 256 B */
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STBM1_RETENTION_SRAM_PHY_REGS = BIT3, /* 256 B PHY SEQ RAM + PHY Registers */
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STBM1_RETENTION_SRAM_LL = BIT4, /* 8 KB */
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STBM1_RETENTION_SRAM_ALL = (BIT0 | BIT1 | BIT2 | BIT3 | BIT4),
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};
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/**
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* @brief Read the current counter of LP Timer.
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*
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* This routine returns the current cycle count, as measured by the SoC's
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* hardware LP TImer.
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*
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* @return Current hardware LP Timer clock up-counter (in cycles).
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*/
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__STATIC_FORCEINLINE uint32_t soc_lptmr_cycle_get(void)
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{
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return (*(volatile uint32_t *)(0x50020014));
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}
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/**
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* @brief Get current 32K low speed clock freqency.
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*
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* @return Current 32K low speed clock freqency in Hz.
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*/
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__STATIC_FORCEINLINE uint32_t soc_32k_clock_freq_get(void)
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{
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return (CLK->CLK_TOP_CTRL_3V & CLK_TOPCTL_32K_CLK_SEL_Msk_3v ? 32768 : 32000);
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}
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/**
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* @brief Read the current counter of LP Timer.
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*
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* This routine returns the current cycle count, as measured by the SoC's
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* hardware LP TImer.
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*
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* @return Current hardware LP Timer clock up-counter (in cycles).
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*/
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__STATIC_FORCEINLINE uint32_t soc_lptmr_uptime_get_ms(void)
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{
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return soc_lptmr_cycle_get() * 1000ull / soc_32k_clock_freq_get();
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}
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extern void soc_busy_wait(uint32_t us);
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extern uint8_t soc_reset_reason_get(void);
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extern uint32_t soc_stbm1_gpio_wakeup_src_get(void);
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extern void soc_enter_standby_mode_0(void);
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extern void soc_enter_standby_mode_1(uint32_t wakeup_src, uint32_t retention_sram);
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#endif /* _OS_LP_H_ */
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