#include "FreeRTOS.h"
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#include "task.h"
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#ifdef NIMBLE_SPARK_SUP
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#include "app_config_spark.h"
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#endif
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#include "pan_clktrim.h"
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#include "nimble/nimble_port.h"
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#include "pan_svc_call.h"
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#ifdef NIMBLE_SPARK_SUP
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#include "nimble/pan107x/nimble_glue_spark.h"
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#endif
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#include "pan_power.h"
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/* For RCL Clock test */
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//#define PRINT_RCL_FREQ_BEFORE_AND_AFTER_CALIBRATE
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#define CLK_ACT32K_TMR_EN_Pos (0)
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#define CLK_ACT32K_TMR_EN_Msk (0x1ul << CLK_ACT32K_TMR_EN_Pos)
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#define CLK_ACT32K_LL_32KCLK_SEL_Pos (1)
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#define CLK_ACT32K_LL_32KCLK_SEL_Msk (0x1ul << CLK_ACT32K_LL_32KCLK_SEL_Pos)
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/* Do not modify this definition */
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#define LPTMR_CURR_CNT_ENA_REG (0x5002000C)
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extern uint32_t lp_int_ctrl_reg;
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extern uint32_t rst_status_reg;
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extern void app_main(void);
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static uint8_t m_chip_mac[6];
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#if (CONFIG_LOW_SPEED_CLOCK_SRC == 1)
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uint32_t clk_32k_count = 32768;
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#else
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uint32_t clk_32k_count = 32000;
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#endif
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#if CONFIG_AUTO_OPTIMIZE_POWER_PARAM
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#define TEMP_CHECK_INTERVAL_MS (CONFIG_TEMP_SAMPLE_INTERVAL_S*1000)
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#ifdef NIMBLE_SPARK_SUP
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static struct ble_npl_callout temp_check_timer;
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static ADC_HandleTypeDef adc_temperature = {
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.id = ADC_CH_TEMP,
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};
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#endif
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void temp_check_start(uint32_t ms)
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{
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#ifdef NIMBLE_SPARK_SUP
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ble_npl_callout_reset(&temp_check_timer, pdMS_TO_TICKS(ms));
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#endif
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}
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void temp_check_cb(struct ble_npl_event *e)
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{
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#ifdef NIMBLE_SPARK_SUP
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float temp;
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temp_check_start(TEMP_CHECK_INTERVAL_MS);
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if (HAL_ADC_GetValue(&adc_temperature, &temp) == PAN_HAL_SUCCESS)
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PW_AutoOptimizeParams((int)temp);
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#endif
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}
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void temp_check_init(void)
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{
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#ifdef NIMBLE_SPARK_SUP
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//register timer
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ble_npl_callout_init(&temp_check_timer, (struct ble_npl_eventq *)nimble_port_get_dflt_eventq(), temp_check_cb, NULL);
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//start timer
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temp_check_start(1000);
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#endif
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}
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void temp_check_stop(void)
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{
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#ifdef NIMBLE_SPARK_SUP
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ble_npl_callout_stop(&temp_check_timer);
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#endif
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}
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#endif /* CONFIG_AUTO_OPTIMIZE_POWER_PARAM */
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#define DST_CLK_CNT 100 /* measure 100 rcl clock period, time spend about 50ms+ */
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#if ((CONFIG_LOW_SPEED_CLOCK_SRC == 0) || (CONFIG_LOW_SPEED_CLOCK_SRC == 1))
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static uint32_t clktrim_measure_32k_clk(uint32_t dst_clk_cnt)
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{
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uint32_t counter_result;
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uint32_t calib_freq;
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CLK_EnableClkTrim(ENABLE);
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CLK_SelectClkTrimSrc(CLKTRIM_CALC_CLK_SEL_32K);
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TRIM_SetCalCnt(TRIM, dst_clk_cnt);
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TRIM_StartTuning(TRIM, TRIM_MEASURE_TUNING_EN_Msk);
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while (!TRIM_IsIntStatusOccured(TRIM, TRIM_FLAG_MEASURE_STOP_Msk)) {
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/* busy-wait */
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}
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TRIM_ClearIntStatusMsk(TRIM, TRIM_FLAG_MEASURE_STOP_Msk);
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counter_result = TRIM_GetRealCnt(TRIM);
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calib_freq = ((uint64_t)FREQ_32MHZ * (uint64_t)dst_clk_cnt) / counter_result;
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clk_32k_count = calib_freq;
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CLK_EnableClkTrim(DISABLE);
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return calib_freq;
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}
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#endif
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#if (CONFIG_FORCE_CALIB_RCL_CLK && (CONFIG_LOW_SPEED_CLOCK_SRC == 0))
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static void calibrate_rcl_clk(uint32_t expected_freq)
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{
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uint32_t AHB_clk_reg;
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const uint8_t coarse_tune_bitwidth = 3;
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const uint8_t fine_tune_bitwidth = 7;
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AHB_clk_reg = CLK->AHB_CLK_CTRL;
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CLK->AHB_CLK_CTRL |= CLK_AHBPeriph_APB2;
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TRIM_EnableInt(TRIM, ENABLE);
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/* Start calibration */
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/* Disable hardware calculate. */
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ANA->RCL_HW_CAL_CTRL &= ~ANAC_RCL_HW_CAL_EN_Msk;
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/* Enable Clktrim */
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CLK_SelectClkTrimSrc(CLKTRIM_CALC_CLK_SEL_32K);
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CLK_EnableClkTrim(ENABLE);
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TRIM_SetCalCnt(TRIM, DST_CLK_CNT);
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TRIM_SetIdealCnt(TRIM, FREQ_32MHZ / expected_freq * DST_CLK_CNT - 1);
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/* a. Coarse tuning proc */
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TRIM_SetBitWidth(TRIM, coarse_tune_bitwidth);
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TRIM_SetCoarseCode(TRIM, 1 << coarse_tune_bitwidth);
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TRIM_StartTuning(TRIM, TRIM_COARSE_TUNING_EN_Msk);
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while (!TRIM_IsIntStatusOccured(TRIM, TRIM_FLAG_CTUNE_STOP_Msk)) {
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/* busy-wait */
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}
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TRIM_ClearIntStatusMsk(TRIM, TRIM_FLAG_CTUNE_STOP_Msk);
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/* b. Fine tuning proc */
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TRIM_SetBitWidth(TRIM, fine_tune_bitwidth);
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TRIM_SetFineCode(TRIM, 1 << fine_tune_bitwidth);
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TRIM_StartTuning(TRIM, TRIM_FINE_TUNING_EN_Msk);
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while (!TRIM_IsIntStatusOccured(TRIM, TRIM_FLAG_FTUNE_STOP_Msk)) {
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/* busy-wait */
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}
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TRIM_ClearIntStatusMsk(TRIM, TRIM_FLAG_FTUNE_STOP_Msk);
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/* Disable Clktrim */
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CLK_EnableClkTrim(DISABLE);
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CLK->AHB_CLK_CTRL = AHB_clk_reg;
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}
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#endif /* CONFIG_FORCE_CALIB_RCL_CLK */
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#if CONFIG_LOG_ENABLE
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void debug_uart_init(void)
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{
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/* Unlock protected registers */
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SYS_UnlockReg();
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CLK_APB1PeriphClockCmd(CLK_APB1Periph_UART0, ENABLE);
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#ifdef IP_101x
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/* Init I/O Multi-function */
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SYS_SET_MFP(P1, 1, UART0_TX);
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SYS_SET_MFP(P1, 2, UART0_RX);
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GPIO_EnableDigitalPath(P1, BIT2);
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#else
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/* Init I/O Multi-function */
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SYS_SET_MFP(P1, 6, UART0_TX);
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SYS_SET_MFP(P1, 7, UART0_RX);
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GPIO_EnableDigitalPath(P1, BIT7);
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#endif
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/* Relock protected registers */
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// SYS_LockReg();
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UART_InitTypeDef Init_Struct;
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Init_Struct.UART_BaudRate = 921600;
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#ifdef CONFIG_APP_REDEFINE_BAUDRATE
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Init_Struct.UART_BaudRate = CONFIG_APP_REDEFINE_BAUDRATE;
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#endif
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Init_Struct.UART_LineCtrl = Uart_Line_8n1;
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/* Init UART0 for printf */
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UART_Init(UART0, &Init_Struct);
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UART_EnableFifo(UART0);
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}
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#endif //CONFIG_LOG_ENABLE
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void track_pin_init(void)
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{
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#ifdef NIMBLE_SPARK_SUP
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CLK_AHBPeriphClockCmd(CLK_AHBPeriph_GPIO, ENABLE);
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debug_io_map debug_io;
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#if 1 //32 pin
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GPIO_SetMode(P1, BIT5, GPIO_MODE_OUTPUT); P15 = 0;
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GPIO_SetMode(P1, BIT3, GPIO_MODE_OUTPUT); P13 = 0;
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GPIO_SetMode(P1, BIT4, GPIO_MODE_OUTPUT); P14 = 0;
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GPIO_SetMode(P1, BIT2, GPIO_MODE_OUTPUT); P12 = 0;
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GPIO_SetMode(P0, BIT5, GPIO_MODE_OUTPUT); P05 = 0;
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GPIO_SetMode(P0, BIT3, GPIO_MODE_OUTPUT); P03 = 0;
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GPIO_SetMode(P2, BIT3, GPIO_MODE_OUTPUT); P23 = 0;
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debug_io.scan_pin = (uint32_t)&P15;
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debug_io.adv_pin = (uint32_t)&P13;
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debug_io.timer_irq_pin = (uint32_t)&P14;
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debug_io.ll_irq_pin = (uint32_t)&P12;
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debug_io.conn_pin[0] = (uint32_t)&P05;
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debug_io.conn_pin[1] = (uint32_t)&P03;
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debug_io.sch_pin = (uint32_t)&P23;
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#else
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GPIO_SetMode(P2, BIT2, GPIO_MODE_OUTPUT); P22 = 0;
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GPIO_SetMode(P2, BIT4, GPIO_MODE_OUTPUT); P24 = 0;
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GPIO_SetMode(P2, BIT5, GPIO_MODE_OUTPUT); P25 = 0;
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GPIO_SetMode(P0, BIT3, GPIO_MODE_OUTPUT); P03 = 0;
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GPIO_SetMode(P2, BIT6, GPIO_MODE_OUTPUT); P26 = 0;
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GPIO_SetMode(P1, BIT2, GPIO_MODE_OUTPUT); P12 = 0;
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GPIO_SetMode(P1, BIT1, GPIO_MODE_OUTPUT); P11 = 0;
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GPIO_SetMode(P1, BIT5, GPIO_MODE_OUTPUT); P15 = 0;
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debug_io.scan_pin = (uint32_t)&P22;
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debug_io.adv_pin = (uint32_t)&P24;
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debug_io.timer_irq_pin = (uint32_t)&P25;
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debug_io.ll_irq_pin = (uint32_t)&P03;
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debug_io.conn_pin[0] = (uint32_t)&P26;
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debug_io.conn_pin[1] = (uint32_t)&P12;
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debug_io.sch_pin = (uint32_t)&P15;
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#endif
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pan_svc_interface(SVC_LL_DEBUG, &debug_io);
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#endif
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}
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__weak void vPortSystemClockEnable()
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{
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/* User overload, self - realization clock enable and disable */
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}
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void sys_clock_Init(void)
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{
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/* Unlock protected registers */
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SYS_UnlockReg();
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ANA->LP_FSYN_LDO |= 0X1;
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CLK_XthStartupConfig();
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CLK->XTH_CTRL |= CLK_XTHCTL_XTH_EN_Msk;
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CLK_WaitClockReady(CLK_SYS_SRCSEL_XTH);
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#if (CONFIG_SYSTEM_CLOCK == 32)
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CLK_HCLKConfig(1);
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CLK_SYSCLKConfig(CLK_DPLL_REF_CLKSEL_XTH, CLK_DPLL_OUT_64M);
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#elif (CONFIG_SYSTEM_CLOCK == 48)
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CLK_HCLKConfig(0);
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CLK_SYSCLKConfig(CLK_DPLL_REF_CLKSEL_XTH, CLK_DPLL_OUT_48M);
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#endif
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CLK_RefClkSrcConfig(CLK_SYS_SRCSEL_DPLL);
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CLK->RCH_CTRL &= ~BIT(0);
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CLK_PCLK1Config(CONFIG_PERIPH_DIVIDE / 2);
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CLK_PCLK2Config(CONFIG_PERIPH_DIVIDE / 2);
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/*
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* Note that all clocks on APB are disabled by default after SoC power up, and
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* the default AHB clocks enabled after SoC power up are:
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* ACC/eFuse/ROM/RCC_AHB/Systick/GPIO.
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* Here we disable ACC, eFuse and ROM clock as these modules are not commonly
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* used. We should re-enabled them once we use later.
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* Here We also enable APB1 and APB2 clock path to make sure modules on APB can
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* be easily enabled by each peripheral driver by enabling their clock enable
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* bits on APB bus.
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*/
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CLK_AHBPeriphClockCmd(CLK_AHBPeriph_ROM, DISABLE);
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CLK_AHBPeriphClockCmd(CLK_AHBPeriph_APB1 | CLK_AHBPeriph_APB2, ENABLE);
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/*Basic clock for BLE*/
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CLK_AHBPeriphClockCmd(CLK_AHBPeriph_BLE_32M | CLK_AHBPeriph_BLE_32K, ENABLE);
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CLK_AHBPeriphClockCmd(CLK_AHBPeriph_USB_AHB|CLK_AHBPeriph_USB_48M, DISABLE);
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vPortSystemClockEnable();
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}
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void ble_misc_init(void)
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{
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#ifdef NIMBLE_SPARK_SUP
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NVIC_EnableIRQ(LL_IRQn);
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NVIC_SetPriority(LL_IRQn, 0);
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NVIC_EnableIRQ(BLE_EVENT_PROC_IRQn);
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NVIC_SetPriority(BLE_EVENT_PROC_IRQn, 1);
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#endif
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}
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static int pan10xx_hw_calib_init(void)
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{
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OTP_STRUCT_T otp;
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printf("Try to load HW calibration data..");
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if (!SystemHwParamLoader(&otp)) {
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printf("\nWARNING: Cannot find valid calib data in current chip!\n");
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} else {
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printf(" DONE.\n");
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printf("- Chip Info : 0x%x\n", otp.m.chip_info);
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printf("- Chip CP Version : %d\n", otp.m.cp_version);
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printf("- Chip FT Version : %d\n", otp.m.ft_version);
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if (otp.m.ft_version >= 2) {
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memcpy(m_chip_mac, otp.m_v2.mac_addr, 6);
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printf("- Chip MAC Address : %02X%02X%02X%02X%02X%02X\n", otp.m_v2.mac_addr[0], otp.m_v2.mac_addr[1],
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otp.m_v2.mac_addr[2], otp.m_v2.mac_addr[3], otp.m_v2.mac_addr[4], otp.m_v2.mac_addr[5]);
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} else {
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memcpy(m_chip_mac, otp.m.mac_addr, 6);
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printf("- Chip MAC Address : %02X%02X%02X%02X%02X%02X\n", otp.m.mac_addr[0], otp.m.mac_addr[1],
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otp.m.mac_addr[2], otp.m.mac_addr[3], otp.m.mac_addr[4], otp.m.mac_addr[5]);
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}
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printf("- Chip UID : %02X%02X%02X%02X%02X%02X%02X%02X%02X\n", otp.m.uid[0], otp.m.uid[1],
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otp.m.uid[2], otp.m.uid[3], otp.m.uid[4], otp.m.uid[5], otp.m.uid[6], otp.m.uid[7], otp.m.uid[8]);
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//buck out(DCDC):default - 2; default:8
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uint32_t tmp = ANA->LP_BUCK_3V;
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tmp &= ~(0xFul<<2);
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tmp |= (((otp.m.buck_out_trim >> 1) - 2) << 2);
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ANA->LP_BUCK_3V = tmp;
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#if CONFIG_DVDD_VOL_OPTIMIZE_EN
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//HPLDO(DVDD) default - 1/2; default:8
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tmp = ANA->LP_HP_LDO;
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tmp &= ~(0xFul <<3);
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tmp |= ((otp.m.hp_ldo_trim - 2)<<3); //~1.12V
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ANA->LP_HP_LDO = tmp;
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#else
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//HPLDO(DVDD) default - 1/2; default:8
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tmp = ANA->LP_HP_LDO;
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tmp &= ~(0xFul <<3);
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tmp |= ((otp.m.hp_ldo_trim - 1)<<3); //~1.16V
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ANA->LP_HP_LDO = tmp;
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#endif
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}
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printf("- Chip Flash UID : ");
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for (uint32_t i = 0; i < 16; i++) {
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printf("%02X", flash_ids.uid[i]);
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}
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printf("\n- Chip Flash Size : %ld KB\n", BIT(flash_ids.memory_density_id) >> 10);
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#if CONFIG_SOC_INCREASE_LPLDOH_CALIB_CODE
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/* Temporarily get and increase LPLDOH calibrate code */
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uint32_t i = ((ANA->LP_LP_LDO_3V & (0xFu << 17)) >> 17) + CONFIG_SOC_INCREASE_LPLDOH_CALIB_CODE;
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/* Handle code overflow */
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if (i > 15) {
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i = 15;
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}
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ANA->LP_LP_LDO_3V = (ANA->LP_LP_LDO_3V & ~(0xFu << 17)) | (i << 17);
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#endif /* CONFIG_SOC_INCREASE_LPLDOH_CALIB_CODE */
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return 0;
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}
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uint8_t pan10x_mac_addr_get(uint8_t *mac)
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{
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uint8_t addr_null[6] = {0, 0, 0, 0, 0, 0};
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if (memcmp(m_chip_mac, addr_null, 6) == 0) {
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return 1;
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} else {
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memcpy(mac, m_chip_mac, 6);
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return 0;
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}
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}
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void pan10x_init()
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{
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#if CONFIG_RF_CALIB
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CLK->XTH_CTRL = (CLK->XTH_CTRL & ~CLK_XTHCTL_XO_CAP_SEL_Msk) | (0x16 << CLK_XTHCTL_XO_CAP_SEL_Pos);
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#endif
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#if CONFIG_VECTOR_REMAP_TO_RAM
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static ALIGN(256) uint32_t ram_vector[64] = {0};
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extern uint32_t __Vectors;
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memcpy((void*)ram_vector, &__Vectors, 256);
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ANA->CPU_ADDR_REMAP_CTRL = ((uint32_t)ram_vector >> 8) | BIT(31);
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#endif /* CONFIG_VECTOR_REMAP_TO_RAM */
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pan10xx_hw_calib_init();
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#if CONFIG_FLASH_LDO_EN
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#if CONFIG_FLASH_LDO_VOL < 8
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ANA->LP_HP_LDO &= ~(BIT(22)|BIT(21)|BIT(20));
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ANA->LP_HP_LDO |= (CONFIG_FLASH_LDO_VOL<<20);
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#endif /* CONFIG_FLASH_LDO_VOL */
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ANA->LP_HP_LDO &= ~ANAC_HPLDO_FLASHLDO_BP_Msk_3v;
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#else
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ANA->LP_HP_LDO |= ANAC_HPLDO_FLASHLDO_BP_Msk_3v;
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#endif /* CONFIG_FLASH_LDO_EN */
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// Ensure SoC LP configure is sleep mode (default state)
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SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
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LP_SetSleepMode(ANA, LP_MODE_SEL_SLEEP_MODE);
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#if (CONFIG_LOW_SPEED_CLOCK_SRC == 0) /*LP Clock from RCL, 32000 HZ default*/
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/* Enable RCL */
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CLK->RCL_CTRL_3V |= CLK_RCLCTL_RC32K_EN_Msk_3v;
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/* Wait for stable */
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while (!(CLK->RCL_CTRL_3V & CLK_STABLE_STATUS_Msk));
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/* Select RCL as SoC 32K clock source */
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CLK->CLK_TOP_CTRL_3V &= ~CLK_TOPCTL_32K_CLK_SEL_Msk_3v;
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/* Disable lp xtl src */
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ANA->LP_FL_CTRL_3V &= ~ANAC_FL_XTAL32K_EN_Msk_3v;
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ANA->LP_FL_CTRL_3V |= ANAC_FL_RC32K_EN_Msk_3v;
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/* Delay more than two 32K clock cycles */
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SYS_delay_10nop(250);
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/* Disable XTL */
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CLK->XTL_CTRL_3V &= ~CLK_XTLCTL_XTL_EN_Msk_3v;
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#if CONFIG_FORCE_CALIB_RCL_CLK
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#ifdef PRINT_RCL_FREQ_BEFORE_AND_AFTER_CALIBRATE
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printf("RCL Freq before calib: %d Hz\n", clktrim_measure_32k_clk(DST_CLK_CNT));
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#endif
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/* Calibrate RCL to 32K Hz */
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calibrate_rcl_clk(32000);
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#ifdef PRINT_RCL_FREQ_BEFORE_AND_AFTER_CALIBRATE
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printf("RCL Freq after calib: %d Hz\n", clktrim_measure_32k_clk(DST_CLK_CNT));
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#endif
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#endif /* CONFIG_FORCE_CALIB_RCL_CLK */
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#elif ( CONFIG_LOW_SPEED_CLOCK_SRC == 2) /*LP Clock from ACT32K,32000 HZ default*/
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ANA->ACT_32K_CTRL |= (CLK_ACT32K_TMR_EN_Msk | CLK_ACT32K_LL_32KCLK_SEL_Msk); /*LP Clock from XTL,32768 HZ default*/
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#else /*LP Clock from XTL, 32768 HZ */
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#ifdef XTL_SLOW_SETUP
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/* Enable XTL clock */
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CLK->XTL_CTRL_3V |= CLK_XTLCTL_XTL_EN_Msk_3v;
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while(!(CLK->XTL_CTRL_3V & CLK_XTLCTL_STABLE_Msk));
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#else // Quick Setup
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CLK->MEAS_CLK_CTRL = (CLK->MEAS_CLK_CTRL & ~(CLK_MEASCLK_XTH_DIV_Msk)) | (0x1e8 << CLK_MEASCLK_XTH_DIV_Pos);
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CLK->XTL_CTRL_3V = (CLK->XTL_CTRL_3V & ~(CLK_XTLCTL_DELAY_Msk_3v)) | (3 << CLK_XTLCTL_DELAY_Pos_3v);
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/* Enable quick startup */
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CLK->MEAS_CLK_CTRL |= CLK_MEASCLK_XTL_QUICK_EN_Msk;
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SYS_SET_MFP(P2, 0, XTL_C1_CLK);
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SYS_SET_MFP(P2, 1, XTL_C2_CLK);
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/* Enable XTL clock */
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CLK->XTL_CTRL_3V |= CLK_XTLCTL_XTL_EN_Msk_3v;
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/* Delay a while */
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SYS_delay_10nop(5000);
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/* Disable quick startup */
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CLK->MEAS_CLK_CTRL &= ~CLK_MEASCLK_XTL_QUICK_EN_Msk;
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SYS_SET_MFP(P2, 0, GPIO);
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SYS_SET_MFP(P2, 1, GPIO);
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/* Wait for stable */
|
while (!(CLK->XTL_CTRL_3V & CLK_STABLE_STATUS_Msk)) {
|
/* Busy wait */
|
__NOP();
|
}
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#endif /* XTL_SLOW_SETUP */
|
/* Select XTL as current 32K clock */
|
CLK->CLK_TOP_CTRL_3V |= CLK_TOPCTL_32K_CLK_SEL_Msk_3v;
|
/* Delay more than two 32K clock cycles */
|
SYS_delay_10nop(250);
|
/* Disable lp rcl src */
|
ANA->LP_FL_CTRL_3V |= ANAC_FL_XTAL32K_EN_Msk_3v;
|
ANA->LP_FL_CTRL_3V &= ~ANAC_FL_RC32K_EN_Msk_3v;
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/* Disable RCL clock */
|
CLK->RCL_CTRL_3V &= ~BIT(0);
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#endif /* CONFIG_LOW_SPEED_CLOCK_SRC */
|
|
/* Store value in rst status reg and lp int ctrl reg for later possible soc_reset_reason_get() use */
|
rst_status_reg = CLK->RSTSTS;
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lp_int_ctrl_reg = ANA->LP_INT_CTRL;
|
/* Clear status registers for next time detecting */
|
CLK->RSTSTS = CLK->RSTSTS;
|
ANA->LP_INT_CTRL = ANA->LP_INT_CTRL;
|
|
/* Enable lp timer counter */
|
ANA->LP_FL_CTRL_3V |= ANAC_FL_SLEEP_CNT_EN_Msk;
|
(*(volatile uint32_t *)LPTMR_CURR_CNT_ENA_REG) |= BIT1;
|
|
/* Enable ble related irqs, etc. */
|
ble_misc_init();
|
}
|
|
void setup_thread(void *param)
|
{
|
app_main();
|
}
|
|
CONFIG_RAM_CODE void soc_busy_wait(uint32_t us)
|
{
|
while (us--) {
|
for (int32_t cnt = SystemCoreClock; cnt > 0; cnt-= 16000000u) {
|
__NOP();
|
}
|
}
|
}
|
|
void __WEAK app_init_early(void)
|
{
|
return;
|
}
|
|
int main()
|
{
|
/* system clock initialize */
|
sys_clock_Init();
|
|
/* add a weak function for application initializing early */
|
extern void app_init_early(void);
|
app_init_early();
|
|
#if CONFIG_LOG_ENABLE
|
/* log uart initialize */
|
debug_uart_init();
|
#endif /* CONFIG_LOG_ENABLE */
|
|
/* Track Init */
|
#if CONFIG_BT_CTLR_LINK_LAYER_DEBUG
|
track_pin_init();
|
pan_misc_register_print(vprintf);
|
#endif
|
|
/* system configure */
|
pan10x_init();
|
|
#if CONFIG_PM
|
/* Init low power flow */
|
extern void deepsleep_init(void);
|
deepsleep_init();
|
|
#endif
|
|
#ifdef NIMBLE_SPARK_SUP
|
/* ble stack init*/
|
nimble_port_init();
|
#endif
|
|
#if CONFIG_AUTO_OPTIMIZE_POWER_PARAM
|
#ifdef NIMBLE_SPARK_SUP
|
if(PW_ParamIsHas()){
|
HAL_ADC_Init(&adc_temperature);
|
temp_check_init();
|
}
|
#endif
|
#endif
|
|
#if ((CONFIG_LOW_SPEED_CLOCK_SRC == 0) || (CONFIG_LOW_SPEED_CLOCK_SRC == 1))
|
/* get clock frequence, no matter rcl or xtl */
|
clktrim_measure_32k_clk(1000);
|
#endif
|
|
#if CONFIG_SYSTEM_WATCH_DOG_ENABLE
|
extern void system_watch_dog_init(void);
|
system_watch_dog_init();
|
#endif
|
|
setup_thread(NULL);
|
|
/* The operating system starts scheduling. */
|
vTaskStartScheduler();
|
|
printf("\033[31;1m[ERR] This is not where the program should go\n\033[0m");
|
while(1);
|
}
|
|
#if configUSE_MALLOC_FAILED_HOOK
|
void vApplicationMallocFailedHook(void)
|
{
|
printf("pvPortMalloc failed\n");
|
}
|
#endif
|
|
#if (CONFIG_LOG_ENABLE == 0)
|
void SendChar(int ch)
|
{
|
}
|
|
char GetChar(void)
|
{
|
return (char)0;
|
}
|
#endif
|
|
__attribute__((weak,noreturn))
|
void __aeabi_assert (const char *expr, const char *file, int line) {
|
char str[12], *p;
|
|
fputs("*** assertion failed: ", stderr);
|
fputs(expr, stderr);
|
fputs(", file ", stderr);
|
fputs(file, stderr);
|
fputs(", line ", stderr);
|
|
p = str + sizeof(str);
|
*--p = '\0';
|
*--p = '\n';
|
while (line > 0) {
|
*--p = '0' + (line % 10);
|
line /= 10;
|
}
|
fputs(p, stderr);
|
|
abort();
|
}
|
|
__attribute__((weak))
|
void abort(void) {
|
for (;;);
|
}
|
