#include "PanSeries.h"
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#include "pan_lp.h"
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#include "pan_clk.h"
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extern const uint32_t PanFlashLineMode;
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extern const bool PanFlashEnhanceEnable;
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/**
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* @brief This function enable gpio p56 wake up
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* @param[in] ana: where ana is analog module
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* @param[in] WkEdge: wake up edge select,0-->low,1-->high
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* @return none
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*/
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void LP_SetExternalWake(ANA_T *ana,uint8_t WkEdge)
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{
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if(WkEdge){
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ana->LP_FL_CTRL_3V |= ANAC_FL_EXT_WAKEUP_SEL_Msk_3v;
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}else{
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ana->LP_FL_CTRL_3V &= ~ANAC_FL_EXT_WAKEUP_SEL_Msk_3v;
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}
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}
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/**
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* @brief This function set sleep time
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* @param[in] ana: where ana is analog module
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* @param[in] u32ClkCnt: where u32ClkCnt is 32k clock cnt num
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* @param[in] idx: channel index of sleeptimer, can be 0, 1, 2
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* @return none
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*/
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void LP_SetSleepTime(ANA_T *ana,uint32_t u32ClkCnt,uint8_t idx)
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{
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((__IO uint32_t *)(&(ana)->LP_SPACING_TIME0))[idx] = u32ClkCnt;
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}
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/**
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* @brief This function get current 32K timer counter
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* @param[in] ana: where ana is analog module
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* @return Current 32K timer counter
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*/
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uint32_t LP_GetSlptmrCurrCount(ANA_T *ana)
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{
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return ana->LP_SLPTMR;
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}
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/**
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* @brief This function set delay time used for standby_m0 mode for wait LPLDOH ready
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* @param[in] ana: where ana is analog module
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* @param[in] u8Clk32Cnt: where u8Clk32Cnt is 32k clock period cnt
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* @return none
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*/
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void LP_SetLpldohDelay(ANA_T *ana,uint16_t u16Clk32Cnt)
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{
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uint32_t tmp_reg;
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tmp_reg = ana->LP_DLY_CTRL_3V;
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tmp_reg &= ~(ANAC_LPLDOH_DLY_TIME_Msk_3v);
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tmp_reg |= (u16Clk32Cnt << ANAC_LPLDOH_DLY_TIME_Pos_3v);
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ana->LP_DLY_CTRL_3V = tmp_reg;
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}
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/**
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* @brief This function set delay time used for fast clock ready
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* @param[in] ana: where ana is analog module
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* @param[in] u8Clk32Cnt: where u8Clk32Cnt is 32k clock period cnt
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* @return none
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*/
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void LP_SetWakeDelay(ANA_T *ana,uint16_t u16Clk32Cnt)
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{
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uint32_t tmp_reg;
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tmp_reg = ana->LP_DLY_CTRL_3V;
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tmp_reg &= ~(ANAC_32KCLK_DLY_TIME_Msk);
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tmp_reg |= (u16Clk32Cnt << ANAC_32KCLK_DLY_TIME_Pos);
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ana->LP_DLY_CTRL_3V = tmp_reg;
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}
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/**
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* @brief This function set delay time used for fast clock ready
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* @param[in] ana: where ana is analog module
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* @param[in] mode: where mode is sleep mode select
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* LP_MODE_SEL_SLEEP_MODE
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* LP_MODE_SEL_DEEPSLEEP_MODE
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* LP_MODE_SEL_STANDBY_M1_MODE
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* LP_MODE_SEL_STANDBY_M0_MODE
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*
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* @return none
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*/
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void LP_SetSleepMode(ANA_T *ana,uint8_t mode)
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{
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uint32_t tmp_reg;
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tmp_reg = ana->LP_FL_CTRL_3V;
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tmp_reg &= ~(ANAC_FL_SLEEP_MODE_SEL_Msk);
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tmp_reg |= (mode << ANAC_FL_SLEEP_MODE_SEL_Pos);
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ana->LP_FL_CTRL_3V = tmp_reg;
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}
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/**
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* @brief This function set sleep mode config
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* @param[in] ana: Select analog module
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* @param[in] enterCyclically: Enable ARM Sleep-On-Exit Feature or not
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* @return none
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*/
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void LP_EnterSleepMode(ANA_T *ana, bool enterCyclically)
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{
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LP_EnableInt(ana, ENABLE);
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/* Enable proper 32k clock in low power mode */
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if (CLK->CLK_TOP_CTRL_3V & CLK_TOPCTL_32K_CLK_SEL_Msk_3v) {
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ana->LP_FL_CTRL_3V |= ANAC_FL_XTAL32K_EN_Msk_3v;
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ana->LP_FL_CTRL_3V &= ~ANAC_FL_RC32K_EN_Msk_3v;
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} else {
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ana->LP_FL_CTRL_3V &= ~ANAC_FL_XTAL32K_EN_Msk_3v;
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ana->LP_FL_CTRL_3V |= ANAC_FL_RC32K_EN_Msk_3v;
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}
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LP_SetSleepMode(ana, LP_MODE_SEL_SLEEP_MODE);
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SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
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if (enterCyclically) {
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SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk;
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} else {
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SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk;
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}
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__WFI();
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}
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void LP_EnterDeepSleepMode(ANA_T *ana, bool enterCyclically, uint8_t powerCtrl, uint8_t dpMode)
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{
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uint32_t nvicInt;
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ana->LP_INT_CTRL |= ANAC_INT_LP_INT_EN_Msk | ANAC_INT_SLEEP_TMR_INT_EN_Msk | ANAC_INT_SLEEP_TMR_WK_EN_Msk;
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if (dpMode == LP_DEEPSLEEP_MODE1) {
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ana->LP_LP_LDO_3V |= ANAC_LPLDO_H_EN_Msk_3v;
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ana->LP_LP_LDO_3V |= ANAC_LPLDO_L_EN_Msk;
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ana->LP_FL_CTRL_3V |= ANAC_LDO_POWER_CTL_Msk | ANAC_FL_LDO_ISOLATE_EN_Msk;
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ana->LP_FL_CTRL_3V &= ~ANAC_LDOL_POWER_CTL_Msk;
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} else if (dpMode == LP_DEEPSLEEP_MODE2) {
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ana->LP_LP_LDO_3V |= ANAC_LPLDO_H_EN_Msk_3v;
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ana->LP_LP_LDO_3V &= ~ANAC_LPLDO_L_EN_Msk;
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ana->LP_FL_CTRL_3V |= ANAC_LDOL_POWER_CTL_Msk | ANAC_LDO_POWER_CTL_Msk;
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ana->LP_FL_CTRL_3V &= ~ANAC_FL_LDO_ISOLATE_EN_Msk;
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} else if (dpMode == LP_DEEPSLEEP_MODE3) {
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ana->LP_LP_LDO_3V &= ~ANAC_LPLDO_H_EN_Msk_3v;
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ana->LP_LP_LDO_3V |= ANAC_LPLDO_L_EN_Msk;
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ana->LP_FL_CTRL_3V |= ANAC_LDOL_POWER_CTL_Msk | ANAC_LDO_POWER_CTL_Msk;
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ana->LP_FL_CTRL_3V &= ~ANAC_FL_LDO_ISOLATE_EN_Msk;
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}
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// Enable LPDOH mode 2 to save power
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// NOTE: This option is now configured in SystemHwParamLoader() flow due to ft version.
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#if 0
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ana->LP_LP_LDO_3V |= ANAC_LPLDO_H_MODE_SEL_Msk_3v;
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#endif
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#if CONFIG_KEEP_FLASH_POWER_IN_LP_MODE
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// Keep flash power in Deepsleep mode
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#if CONFIG_FLASH_LDO_EN
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ana->LP_FL_CTRL_3V |= ANAC_FL_FLASH_LP_EN_Msk;
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ana->LP_FL_CTRL_3V &= ~ANAC_FL_FLASH_BP_EN_Msk;
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#else
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ana->LP_FL_CTRL_3V &= ~ANAC_FL_FLASH_LP_EN_Msk;
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ana->LP_FL_CTRL_3V |= ANAC_FL_FLASH_BP_EN_Msk;
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#endif /* CONFIG_FLASH_LDO_EN */
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// Configure rdp wait cnt for auto dp use
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FMC_SetRdpWaitCount(FLCTL, 0x400);
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#else
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// Power down flash in Deepsleep mode
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ana->LP_FL_CTRL_3V &= ~ANAC_FL_FLASH_LP_EN_Msk;
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ana->LP_FL_CTRL_3V &= ~ANAC_FL_FLASH_BP_EN_Msk;
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#endif /* CONFIG_KEEP_FLASH_POWER_IN_LP_MODE */
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/* Enable flash auto-dp no matter flash power-down or not in deepsleep mode */
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FMC_EnableAutoDp(FLCTL);
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/* Enable proper 32k clock in low power mode */
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if (CLK->CLK_TOP_CTRL_3V & CLK_TOPCTL_32K_CLK_SEL_Msk_3v) {
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ana->LP_FL_CTRL_3V |= ANAC_FL_XTAL32K_EN_Msk_3v;
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ana->LP_FL_CTRL_3V &= ~ANAC_FL_RC32K_EN_Msk_3v;
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} else {
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ana->LP_FL_CTRL_3V &= ~ANAC_FL_XTAL32K_EN_Msk_3v;
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ana->LP_FL_CTRL_3V |= ANAC_FL_RC32K_EN_Msk_3v;
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}
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// Configure power of SRAM
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ana->LP_FL_CTRL_3V = ((powerCtrl & 0x1f) << 24u) | (ana->LP_FL_CTRL_3V & 0xe0FFFFFF);
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// Configure LP delay
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ana->LP_DLY_CTRL_3V &= ~0x3ff;
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ana->LP_DLY_CTRL_3V |= 0x5;
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// Mask all interrupts
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__disable_irq();
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// Set LP irq to lowest priority
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NVIC_SetPriority(LP_IRQn, 3);
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/* Store and Clear NVIC Interrupt Enable Register */
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nvicInt = NVIC->ISER[0U];
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NVIC->ICER[0U] = 0xFFFFFFFF;
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/* Enable LP IRQ to make sure related ISR would trigger after wake up */
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NVIC_EnableIRQ(LP_IRQn);
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// Ensure next wfi enter deepsleep mode
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LP_SetSleepMode(ana, LP_MODE_SEL_DEEPSLEEP_MODE);
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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// Wait 3v sync ready manually
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ana->LP_REG_SYNC |= ANAC_LP_REG_SYNC_3V_Msk | ANAC_LP_REG_SYNC_3V_TRG_Msk;
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while (ana->LP_REG_SYNC & (ANAC_LP_REG_SYNC_3V_TRG_Msk)) {}
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if (enterCyclically) {
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SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk;
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} else {
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SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk;
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}
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__WFI();
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// Ensure next wfi enter sleep mode
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SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
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LP_SetSleepMode(ana, LP_MODE_SEL_SLEEP_MODE);
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/* Disable flash auto-dp after deepsleep wakeup */
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FMC_DisableAutoDp(FLCTL);
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#if ((!CONFIG_KEEP_FLASH_POWER_IN_LP_MODE) && (CONFIG_FLASH_LINE_MODE == FLASH_X4_MODE))
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/* Set en_burst_wrap in FMC */
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FLCTL->X_FL_X_MODE |= (0x1 << 16);
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/* Re-issue burst_wrap command to flash if is X4 mode */
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FLCTL->X_FL_CTL = (0 << 8) | (0x05 << 0);
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FLCTL->X_FL_WD[0] = CMD_BURST_READ;
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FLCTL->X_FL_WD[4] = BURST_READ_MODE_32 << 5;
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FLCTL->X_FL_TRIG = CMD_TRIG;
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while (FLCTL->X_FL_TRIG) {
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__NOP();
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}
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#endif
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/* Restore NVIC Interrupt Enable Register [xxx:107 must]*/
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NVIC->ISER[0U] = nvicInt;
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}
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__ASM static void LP_WfiWithCoreRegsBackupAndResume(void)
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{
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push {r0-r7} /* Backup r0 ~ r7 */
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mov r0, r8
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mov r1, r9
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mov r2, r10
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mov r3, r11
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mov r4, r12
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mov r5, lr
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push {r0-r5} /* Backup r8 ~ r12 and lr */
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wfi /* Trigger hw to enter low power mode */
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pop {r0-r5} /* Restore r8 ~ r12 and lr */
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mov r8, r0
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mov r9, r1
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mov r10, r2
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mov r11, r3
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mov r12, r4
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mov lr, r5
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pop {r0-r7} /* Restore r0 ~ r7 */
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bx lr /* Function return */
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}
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void LP_EnterStandbyMode1(ANA_T *ana, uint8_t powerCtrl, bool wakeupWithoutReset)
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{
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ana->LP_INT_CTRL |= ANAC_INT_LP_INT_EN_Msk | ANAC_INT_SLEEP_TMR_INT_EN_Msk | ANAC_INT_SLEEP_TMR_WK_EN_Msk;
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/* StandbyM1 Power Mode 1, use both LPLDOH and LPLDOL */
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ana->LP_LP_LDO_3V |= ANAC_LPLDO_H_EN_Msk_3v;
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ana->LP_LP_LDO_3V |= ANAC_LPLDO_L_EN_Msk;
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ana->LP_FL_CTRL_3V |= ANAC_FL_LDO_ISOLATE_EN_Msk;
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ana->LP_FL_CTRL_3V &= ~(ANAC_LDOL_POWER_CTL_Msk | ANAC_LDO_POWER_CTL_Msk);
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/* LPDOH switch to mode 2 for better power consumption performance */
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ana->LP_LP_LDO_3V |= ANAC_LPLDO_H_MODE_SEL_Msk_3v;
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/* Power down Flash in lp mode discard the dedicated Flash LDO enabled or not */
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ana->LP_FL_CTRL_3V = (ana->LP_FL_CTRL_3V & ~(0x3 << 12u)) | (0x0 << 12u);
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/* Enable proper 32k clock in low power mode */
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if (CLK->CLK_TOP_CTRL_3V & CLK_TOPCTL_32K_CLK_SEL_Msk_3v) {
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ana->LP_FL_CTRL_3V |= ANAC_FL_XTAL32K_EN_Msk_3v;
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ana->LP_FL_CTRL_3V &= ~ANAC_FL_RC32K_EN_Msk_3v;
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} else {
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ana->LP_FL_CTRL_3V &= ~ANAC_FL_XTAL32K_EN_Msk_3v;
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ana->LP_FL_CTRL_3V |= ANAC_FL_RC32K_EN_Msk_3v;
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}
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/* Configure retention SRAM modules in low power mode */
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ana->LP_FL_CTRL_3V = ((powerCtrl & 0x1f) << 24u) | (ana->LP_FL_CTRL_3V & 0xe0FFFFFF);
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/* Set digital delay with 32k tick unit */
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ana->LP_DLY_CTRL_3V &= ~0x3ff;
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ana->LP_DLY_CTRL_3V |= 5;
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/* Insure we are going to enter hw standby mode 1 */
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LP_SetSleepMode(ana, LP_MODE_SEL_STANDBY_M1_MODE);
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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// Mask all interrupts
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__disable_irq();
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/* Trigger 3v sync */
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ana->LP_REG_SYNC |= ANAC_LP_REG_SYNC_3V_Msk | ANAC_LP_REG_SYNC_3V_TRG_Msk;
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/* Clear all lowpower related int flags if any */
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ana->LP_INT_CTRL = ana->LP_INT_CTRL;
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#if 0
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/* Reset all hw peripheral modules except eFuse and GPIO */
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CLK->IPRST0 = 0x1CC;
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CLK->IPRST0 = 0x0;
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CLK->IPRST1 = 0x17FFF;
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CLK->IPRST1 = 0x0;
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#endif
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/* Disable all IRQs and clear all pending IRQs on NVIC */
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NVIC->ICER[0U] = 0xFFFFFFFF;
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NVIC->ICPR[0U] = 0xFFFFFFFF;
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/* Wait until 3v sync done */
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while (ana->LP_REG_SYNC & (ANAC_LP_REG_SYNC_3V_TRG_Msk)) {
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__NOP();
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}
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if (!wakeupWithoutReset) {
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/* Reset CPU Vector Remap register to avoid issue after waking up */
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ana->CPU_ADDR_REMAP_CTRL = 0;
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/* Trigger hw to enter low power mode */
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__WFI();
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/*
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* ======== (Now SoC is expected in HW Standby Mode 1 and would never return back here) =========
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*/
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} else {
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/*
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* Enable CPU core regs retention in standby mode 1
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* The CPU core registers PC, MSP, PSP and CONTROL would automatically
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* be saved and restored by hardware in SoC standby mode 1.
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*/
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ana->LP_FL_CTRL_3V |= ANAC_FL_CPU_RETENTION_EN_Msk;
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/* Backup the FMC remap register in case we configure it in bootloader */
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uint32_t fmc_remap_bkp = FLCTL->X_FL_REMAP_ADDR;
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/*
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* 1. Backup CPU core registers which are not auto-saved by hardware
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* 2. Enter SoC Standby Mode 1 (WFI)
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* 3. Restore previous backup CPU core registers
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*/
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LP_WfiWithCoreRegsBackupAndResume();
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/* Restore FMC remap register after waking up */
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FLCTL->X_FL_REMAP_ADDR = fmc_remap_bkp;
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// Disable CPU core regs retention after wakeup
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ANA->LP_FL_CTRL_3V &= ~ANAC_FL_CPU_RETENTION_EN_Msk;
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/* Reset SoC lp mode to sleep mode (1.2v area, do not need 3v sync) */
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ana->LP_FL_CTRL_3V = (ana->LP_FL_CTRL_3V & ~ANAC_FL_SLEEP_MODE_SEL_Msk)
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| (LP_MODE_SEL_SLEEP_MODE << ANAC_FL_SLEEP_MODE_SEL_Pos);
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/* Restore fmc and flash status */
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FMC_SetFlashMode(FLCTL, PanFlashEnhanceEnable, PanFlashEnhanceEnable);
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/* Reinit I-Cache */
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InitIcache(FLCTL, PanFlashEnhanceEnable);
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/*
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* Clear StandbyM1 int flag (write 1 to clear) in this register, but still
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* retain all other ctrl/status flags.
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*/
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ana->LP_INT_CTRL = (ana->LP_INT_CTRL | ANAC_INT_STANDBY_M1_FLAG_Msk)
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& ~(ANAC_INT_SLEEP_TMR0_Msk | ANAC_INT_SLEEP_TMR1_Msk | ANAC_INT_SLEEP_TMR2_Msk
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| ANAC_INT_DP_FLAG_Msk | ANAC_INT_STANDBY_M0_FLAG_Msk | ANAC_INT_SRAM_RET_FLAG_Msk);
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}
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}
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void LP_EnterStandbyMode0(ANA_T *ana, bool enableClk32k)
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{
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/* Mask all IRQs when we are on the way to enter standby mode */
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__disable_irq();
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if (enableClk32k) {
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/* Enable proper 32k clock in low power mode */
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if (CLK->CLK_TOP_CTRL_3V & CLK_TOPCTL_32K_CLK_SEL_Msk_3v) {
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ANA->LP_FL_CTRL_3V |= ANAC_FL_XTAL32K_EN_Msk_3v;
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ANA->LP_FL_CTRL_3V &= ~ANAC_FL_RC32K_EN_Msk_3v;
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} else {
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ANA->LP_FL_CTRL_3V &= ~ANAC_FL_XTAL32K_EN_Msk_3v;
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ANA->LP_FL_CTRL_3V |= ANAC_FL_RC32K_EN_Msk_3v;
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}
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} else {
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// Disable 32K Clock Source to save power
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ANA->LP_FL_CTRL_3V &= ~ANAC_FL_RC32K_EN_Msk_3v;
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ANA->LP_FL_CTRL_3V &= ~ANAC_FL_XTAL32K_EN_Msk_3v;
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}
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/* Set digital delay with 32k tick unit */
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ANA->LP_DLY_CTRL_3V &= ~0x3ff;
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ANA->LP_DLY_CTRL_3V |= 5;
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/* Insure we are going to enter hw standby mode 1 */
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LP_SetSleepMode(ANA, LP_MODE_SEL_STANDBY_M0_MODE);
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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/* Trigger 3v sync */
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ANA->LP_REG_SYNC |= ANAC_LP_REG_SYNC_3V_Msk | ANAC_LP_REG_SYNC_3V_TRG_Msk;
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/* Disable SLPTMR interrupt and wakeup in lp mode (Only enable LP interrupt) */
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ANA->LP_INT_CTRL = ANAC_INT_LP_INT_EN_Msk;
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// Clear configured time of sleep timers
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ANA->LP_SPACING_TIME0 = 0;
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ANA->LP_SPACING_TIME1 = 0;
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ANA->LP_SPACING_TIME2 = 0;
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/* Clear all lowpower related int flags if any */
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ANA->LP_INT_CTRL = ANA->LP_INT_CTRL;
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#if 0
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/* Reset all hw peripheral modules except eFuse and GPIO */
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CLK->IPRST0 = 0x1CC;
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CLK->IPRST0 = 0x0;
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CLK->IPRST1 = 0x17FFF;
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CLK->IPRST1 = 0x0;
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#endif
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/* Disable all IRQs and clear all pending IRQs on NVIC */
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NVIC->ICER[0U] = 0xFFFFFFFF;
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NVIC->ICPR[0U] = 0xFFFFFFFF;
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/* Wait until 3v sync done */
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while (ANA->LP_REG_SYNC & (ANAC_LP_REG_SYNC_3V_TRG_Msk)) {
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__NOP();
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}
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/* Trigger hw to enter low power mode */
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__WFI();
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/*
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* ======== (Now SoC is expected in HW Standby Mode 0 and would never return back here) =========
|
*/
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}
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