#ifndef SDK_CONFIG_H
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#define SDK_CONFIG_H
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//*** <<< Use Configuration Wizard in Context Menu >>> ***
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// ==========================================================
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// <h> SoC Platform
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// <o> Chip Power Mode
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// <0=> LDO
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// <1=> DCDC
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#define CONFIG_SOC_DCDC_PAN1070 1
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// <o> System Clock
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// <48=> 48 MHz (DPLL)
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// <32=> 32 MHz (DPLL)
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// <i> System main frequency, Unit MHz
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#define CONFIG_SYSTEM_CLOCK 32
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// <o> APB1 Clock Divisor
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// <0=> No Divider
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// <2=> 2
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// <4=> 4
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// <6=> 6
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// <8=> 8
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// <10=> 10
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// <12=> 12
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// <14=> 14
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// <16=> 16
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// <i> Divisor of peripheral clocks on APB1, It can only be even numbers.
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#define CONFIG_APB1_CLOCK_DIVISOR 2
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// <o> APB2 Clock Divisor
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// <0=> No Divider
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// <2=> 2
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// <4=> 4
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// <6=> 6
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// <8=> 8
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// <10=> 10
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// <12=> 12
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// <14=> 14
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// <16=> 16
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// <i> Divisor of peripheral clocks on APB2, It can only be even numbers.
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#define CONFIG_APB2_CLOCK_DIVISOR 2
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// <o> 32K Low-Speed Clock Source
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// <0=> RCL (32000 Hz)
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// <1=> XTL (32768 Hz)
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// <2=> ACT32K (32000 Hz)
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// <i> Select a low-speed clock source
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#define CONFIG_LOW_SPEED_CLOCK_SRC 1
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// <q> Force Calib RCL Clock
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// <i> Force calibrate the 32K RCL clock at system init stage.
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// <i> NOTE this only take effect when the Low-Speed Clock Source is seleted to RCL.
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#define CONFIG_FORCE_CALIB_RCL_CLK 0
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// <e> Enable UART Log
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#define CONFIG_UART_LOG_ENABLE 1
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// <o> Log UART Tx Pin
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// <0=> P05 (UART0)
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// <1=> P11 (UART0)
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// <2=> P16 (UART0)
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// <3=> P01 (UART1)
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// <4=> P10 (UART1)
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// <5=> P12 (UART1)
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// <6=> P25 (UART1)
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// <7=> P31 (UART1)
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// <i> Select a UART Tx pin for logging output.
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#define CONFIG_LOG_UART_PIN 2
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// <o> Log UART Baudrate
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// <115200=> 115200
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// <230400=> 230400
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// <460800=> 460800
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// <921600=> 921600
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// <1000000=> 1M
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// <2000000=> 2M
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#define CONFIG_LOG_UART_BAUDRATE 921600
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// </e>
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// <e> Enable RTT Log
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// <i> Note that the Low Power Mode (CONFIG_PM) should be disabled
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// <i> while using RTT log, since the Jlink SWD connnection would be lost
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// <i> at SoC DeepSleep or Standby Mode.
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#define CONFIG_RTT_LOG_ENABLE 0
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// <o> RTT Log Buffer Size (Bytes)
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// <i> Configure Log RTT Up Buffer Size in Bytes (Channel 0).
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#define CONFIG_LOG_RTT_UP_BUFFER_SIZE 512
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// </e>
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// <q> Enable RAM Function
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// <i> Adding essential code to SRAM could improve running performance.
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#define CONFIG_RAM_FUNCTION 1
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// <q> Enable Flash LDO
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// <i> Enable the internal 1.8v flash LDO for flash power supply
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// <i> instead of the default flash power from SoC VBAT.
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#define CONFIG_FLASH_LDO_EN 1
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// <q> Remap Vector Table to SRAM
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#define CONFIG_VECTOR_REMAP_TO_RAM 1
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// <e> Enable Auto Power Optimization
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// <i> Several power configurations could be updated due to temperature change.
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#define CONFIG_AUTO_OPTIMIZE_POWER_PARAM 0
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// <o> Temperature Sample Interval (in Seconds)
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#define CONFIG_TEMP_SAMPLE_INTERVAL_S 300
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// <q> Enable DVDD Voltage Optimization
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#define CONFIG_DVDD_VOL_OPTIMIZE_EN 1
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// </e>
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// <e> Enable Low Power Mode
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#define CONFIG_PM 0
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// <q> Enable System Watchdog
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#define CONFIG_SYSTEM_WATCH_DOG_ENABLE 0
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// <q> Keep Flash Power in Low Power Mode
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// <i> Select this means flash power would be retained in Low Power Mode, and
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// <i> there would be a little avg-current increase (about 1uA). The benefit is that
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// <i> the large peak current (>15mA) would not occur.
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#define CONFIG_KEEP_FLASH_POWER_IN_LP_MODE 1
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// <q> Enable DeepSleep Mode 2
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// <i> Enable DeepSleep Mode 2 (Only LPLDOH in use), and the HW APB Timer Wakeup
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// <i> and PWM waveform output can be use in this mode.
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#define CONFIG_DEEPSLEEP_MODE_2 0
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// <o> Increase LPLDOH trim value
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// <0=> +0
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// <1=> +1
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// <2=> +2
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// <3=> +3
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// <4=> +4
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// <5=> +5
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// <6=> +6
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// <7=> +7
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// <8=> +8
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// <i> Increase LPLDOH voltage for specific LowPower scenario use.
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#define CONFIG_SOC_INCREASE_LPLDOH_CALIB_CODE 0
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// <q> Continue Run After Standby M1 Wakeup
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// <i> Check this configuration to let CPU continue run after standby M1 waking up,
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// <i> or CPU would reset after waking up from standby M1.
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#define CONFIG_PM_STANDBY_M1_WAKEUP_WITHOUT_RESET 0
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// <q> Enable AHB Clock Optimization
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#define CONFIG_HCLK_OPTIMIZE_EN 1
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// </e>
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// </h>
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// ========================================================== SoC Platform
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// ==========================================================
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// <h> RTOS
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// ******************************
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// <h> Timer Thread
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// <q> Use freeretos software timer
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#define configUSE_TIMERS 1
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// <o> Timer thread priority
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#define configTIMER_TASK_PRIORITY 2
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// <o> Support maximun number of timer queue length
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#define configTIMER_QUEUE_LENGTH 12
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// <o> Timer thread stack size
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#define configTIMER_TASK_STACK_DEPTH 128
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// </h>
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// ****************************** Timer Thread
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// ******************************
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// <h> BLE Host Thread
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// <o> Host thread stack size
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#define MYNEWT_VAL_BLE_HOST_THREAD_STACK_SIZE 256
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// <o> Host thread prioirty
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#define MYNEWT_VAL_BLE_HOST_THREAD_PRIORITY 6
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// </h>
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// ****************************** BLE Host Thread
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// <o> Total Heap Size
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#define configTOTAL_HEAP_SIZE 7000
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// <q> Print Current Heap Usage
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#define CONFIG_FREERTOS_HEAP_PRINT 0
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// <q> Enable OS Idle Hook
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#define configUSE_IDLE_HOOK 0
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// <q> Enable OS Tick Hook
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#define configUSE_TICK_HOOK 0
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// <q> Enable OS Malloc Fail Hook
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#define configUSE_MALLOC_FAILED_HOOK 1
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// </h>
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// ========================================================== RTOS
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// ==========================================================
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// <h> BLE Resource
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// <o> Support maximun number of BLE Master Link
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#define CONFIG_BT_MAX_NUM_OF_CENTRAL 1
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// <o> Support maximun number of BLE Slave Link
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#define CONFIG_BT_MAX_NUM_OF_PERIPHERAL 0
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// <q> Support gap broadcaster role
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#define MYNEWT_VAL_BLE_ROLE_BROADCASTER 0
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// <q> Support gap central role
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#define MYNEWT_VAL_BLE_ROLE_CENTRAL 1
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// <q> Support gap observser role
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#define MYNEWT_VAL_BLE_ROLE_OBSERVER 1
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// <q> Support gap peripheral role
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#define MYNEWT_VAL_BLE_ROLE_PERIPHERAL 0
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// <o> Support acl buffer counts receiving data from controller
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#define MYNEWT_VAL_BLE_TRANSPORT_ACL_FROM_LL_COUNT 5
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// <o> Support acl buffer receiving data from controller
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#define MYNEWT_VAL_BLE_TRANSPORT_ACL_SIZE 27
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// <o> Support hci events counts
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#define MYNEWT_VAL_BLE_TRANSPORT_EVT_COUNT 4
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// <o> Support hci discardable events counts
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#define MYNEWT_VAL_BLE_TRANSPORT_EVT_DISCARDABLE_COUNT 6
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// <o> Support l2cap buffer counts
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#define MYNEWT_VAL_MSYS_1_BLOCK_COUNT 4
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// <o> Support l2cap buffer size
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#define MYNEWT_VAL_MSYS_1_BLOCK_SIZE 120
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// <o> BLE Controller RF RX Buffer Number (must be a power of 2)
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#define CONFIG_BLE_CONTROLLER_RF_RX_BUF_NUM 16
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// <o> BLE Controller RF TX Buffer Number (must be a power of 2)
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#define CONFIG_BLE_CONTROLLER_RF_TX_BUF_NUM 16
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// <o> BLE Controller Packet Encrypt Time (unit:us)
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#define CONFIG_BLE_CONTROLLER_LL_ENC_TIME 100
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// <o> BLE Controller More Data Number
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#define CONFIG_BLE_CONTROLLER_MORE_DATA_NUM 6
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// <o> BLE Controller WhiteList Number
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#define CONFIG_BLE_CONTROLLER_WIHTELIST_NUM 1
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// <o> BLE Controller Resolving List Number
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#define CONFIG_BLE_CONTROLLER_RESOLVELIST_NUM 0
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// <o> BLE Controller Master Link Margin (unit:0.625ms)
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#define CONFIG_BLE_CONTROLLER_MASTER_LINK_MARGIN 6
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// <q> Use Chip unique Mac Address
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#define CONFIG_USER_CHIP_MAC_ADDR 1
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// <o> TX power
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// <0=> 0dBm
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// <1=> 1dBm
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// <2=> 2dBm
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// <3=> 3dBm
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// <4=> 4dBm
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// <5=> 5dBm
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// <6=> 6dBm
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// <7=> 7dBm
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// <8=> 8dBm
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// <9=> 9dBm
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#define CONFIG_BT_CTLR_TX_POWER_DFT 0
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// <q> BLE Timing Debug
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#define CONFIG_BT_CTLR_LINK_LAYER_DEBUG 0
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// </h>
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// ========================================================== BLE Resource
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// ==========================================================
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// <h> BLE Security Manager
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// <o> Security level selection
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#define MYNEWT_VAL_BLE_SM_SC_LVL 0
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// <q> Support SM legacy pair
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#define MYNEWT_VAL_BLE_SM_LEGACY 0
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// <q> Support SM security pair
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#define MYNEWT_VAL_BLE_SM_SC 0
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// <o> IO capability
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// <0=> DisplayOnly
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// <1=> DisplayYesN
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// <2=> KeyboardOnly
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// <3=> NoInputNoOutput
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// <4=> KeyboardDisplay Only
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#define CONFIG_HS_IO_CAPABILITY 3
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// <q> Support SM Bonding
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#define MYNEWT_VAL_BLE_SM_BONDING 0
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// <q> Support SM MITM
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#define MYNEWT_VAL_BLE_SM_MITM 0
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// <q> Support SM oob
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#define MYNEWT_VAL_BLE_SM_OOB_DATA_FLAG 0
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// <q> Support persist store key
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#define MYNEWT_VAL_BLE_STORE_CONFIG_PERSIST 0
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// <o> Support maximun store bonded devices
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#define MYNEWT_VAL_BLE_STORE_MAX_BONDS 1
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// <o> Support maximun store bonded device's cccd
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#define MYNEWT_VAL_BLE_STORE_MAX_CCCDS 8
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// <q> Support host software rpa feature
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#define MYNEWT_VAL_HOST_SOFTWARE_RPA 0
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// </h>
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// ========================================================== BLE Security Manager
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// ==========================================================
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// <h> BLE Services
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// </h>
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// ========================================================== BLE Services
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// <h> Flash KVStore Area
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// ==========================================================
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// <i> Configure Key-Value-Store (kvstore) Area on Flash
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// <o> Start Address
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#define CONFIG_SETTINGS_START_ADDR 0x78000
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// <o> Number of Flash Sectors (>=2)
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// <i> 1 flash sector means 4096 Bytes
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#define CONFIG_SETTINGS_SECTOR_NUM 4
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// </h>
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// ========================================================== Flash KVStore Area
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// <h> Flash Map
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// ==========================================================
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// <q> Support BootLoader
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#define CONFIG_BOOT_ENABLE 0
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// <o> Flash Image Size
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// <0xFF000=> 1M
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// <0x7F000=> 512K
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// <0x3F000=> 256K
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#define CONFIG_FLASH_MAP_SIZE 520192
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// <q> Support Back-up area in OTA model
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#define CONFIG_OTA_IN_APP 0
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// </h>
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// ========================================================== Flash Map
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//*** <<< end of configuration section >>> ***
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#endif /* SDK_CONFIG_H */
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