国产蓝牙芯片的仓库
blame | 历史 | 原始文档
WXK
2024-12-20 51135221cd73a2b3a6ce4b5ec906396d5a33b4c7 
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Ø    ËqaÙ/#.\configuration\app_config_spark.h‡ä”»‰Ù9-C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdlib.hÜ Íò8Ù9-C:\Keil_v5\ARM\ARMCC\Bin\..\include\string.hÜ Íò#Ù8,C:\Keil_v5\ARM\ARMCC\Bin\..\include\errno.hÜ Íò–Ù9-C:\Keil_v5\ARM\ARMCC\Bin\..\include\assert.hÚ Íò*ÙK?..\..\..\..\host\nimble\porting\nimble\include\os/os_mempool.hºÝµgÙ:.C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdbool.hÜ ÍòÁÙC7..\..\..\..\host\nimble\porting\nimble\include\os/os.hºÝµÏÙ9-C:\Keil_v5\ARM\ARMCC\Bin\..\include\assert.hÚ Íò*Ù, .\configuration\nimble_syscfg.hºÝµlÙ.".\configuration\pan_host_config.hºÝµœÙG;..\..\..\..\host\nimble\nimble\include\nimble/nimble_npl.hºÝµSÙ9-C:\Keil_v5\ARM\ARMCC\Bin\..\include\stddef.hÜ Íò@Ù9-C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.hÜ Íò$ÙXL..\..\..\..\host\nimble\porting\npl\freertos\include\nimble/nimble_npl_os.hºÝµøÙ9-C:\Keil_v5\ARM\ARMCC\Bin\..\include\assert.hÚ Íò*Ù7+..\..\..\..\os\freertos\include\FreeRTOS.hºÝµ+Ù-!.\configuration\FreeRTOSConfig.hºÝµ¯Ù^R..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\PanSeries.hºÝµHÙ8,C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.hÜ Íò™Ù\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\core_cm0.hºÝµÿÙaU..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\cmsis_version.hºÝµyÙbV..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\cmsis_compiler.hºÝµ"Ù_S..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\cmsis_armcc.hºÝµ}ÙeY..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\system_PanSeries.hºÝµ6Ù`T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_sys_log.hºÝµ0Ù\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_sys.hºÝµÙÙ\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_clk.hºÝµþÙ\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_adc.hºÝµÞÙ\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_fmc.hºÝµÐÙ]Q..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_dmac.hºÝµoÙ]Q..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_gpio.hºÝµUÙ\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_spi.hºÝµºÙ]Q..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_uart.hºÝµHÙ\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_i2c.hºÝµÙ^R..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_timer.hºÝµáÙ\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_pwm.hºÝµ²Ù\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_wdt.hºÝµ·Ù]Q..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_wwdt.hºÝµ>Ù[O..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_lp.hºÝµ^Ù^R..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_efuse.hºÝµÙfZ..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\radio\prf_lib\include\pan_pri_rf.hºÝµ©Ù^R..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\PanSeries.hºÝµHÙ`T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_clktrim.hºÝµ:Ù^R..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_power.hºÝµÙ\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal.hºÝµÑÙaU..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_gpio.hºÝµ¹Ù`T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_def.hºÝµ;ÙaU..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_uart.hºÝµ¬ÙaU..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_dmac.hºÝµÓÙ`T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_spi.hºÝµÙ`T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_i2c.hºÝµlÙ`T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_wdt.hºÝµÙaU..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_wwdt.hºÝµ¢Ù`T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_pwm.hºÝµÙbV..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_timer.hºÝµEÙ`T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_adc.hºÝµBÙ7+..\..\..\..\os\freertos\include\projdefs.hºÝµ˜Ù7+..\..\..\..\os\freertos\include\portable.hºÝµœÙE9..\..\..\..\os\freertos\include\deprecated_definitions.hºÝµÍÙF:..\..\..\..\os\freertos\portable\RVDS\ARM_CM0\portmacro.hºÝµ•Ù;/..\..\..\..\os\freertos\include\mpu_wrappers.hºÝµÈÙ4(..\..\..\..\os\freertos\include\queue.hºÝµÖÙ3'..\..\..\..\os\freertos\include\task.hºÝµJÙ3'..\..\..\..\os\freertos\include\list.hºÝµAÙ5)..\..\..\..\os\freertos\include\semphr.hºÝµjÙ5)..\..\..\..\os\freertos\include\timers.hºÝµeÙWK..\..\..\..\host\nimble\porting\npl\freertos\include\nimble/npl_freertos.hºÝµHÙG;..\..\..\..\host\nimble\portin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ÙC7..\..\..\..\host\nimble\nimble\host\src\ble_att_priv.hºÝµ¨ÙI=..\..\..\..\host\nimble\porting\nimble\include\stats/stats.hºÝµ)ÙG;..\..\..\..\host\nimble\nimble\host\include\host/ble_att.hºÝµ7ÙC7..\..\..\..\host\nimble\nimble\host\src\ble_gap_priv.hºÝµ¹ÙG;..\..\..\..\host\nimble\nimble\host\include\host/ble_gap.hºÝµHÙF:..\..\..\..\host\nimble\nimble\host\include\host/ble_hs.hºÝµ§ÙG;..\..\..\..\host\nimble\nimble\include\nimble/hci_common.hºÝµWÙPD..\..\..\..\host\nimble\nimble\transport\include\nimble/transport.hºÝµ+ÙUI..\..\..\..\host\nimble\nimble\transport\include\nimble/transport_impl.hºÝµÙXL..\..\..\..\host\nimble\nimble\transport\include\nimble/transport/monitor.hºÝµäÙMA..\..\..\..\host\nimble\nimble\host\include\host/ble_eddystone.hºÝµ¥ÙG;..\..\..\..\host\nimble\nimble\host\include\host/ble_gap.hºÝµHÙH<..\..\..\..\host\nimble\nimble\host\include\host/ble_gatt.hºÝµÎÙJ>..\..\..\..\host\nimble\nimble\host\include\host/ble_hs_adv.hºÝµÙI=..\..\..\..\host\nimble\nimble\host\include\host/ble_hs_id.hºÝµuÙJ>..\..\..\..\host\nimble\nimble\host\include\host/ble_hs_hci.hºÝµÙJ>..\..\..\..\host\nimble\nimble\host\include\host/ble_hs_log.hºÝµþÙK?..\..\..\..\host\nimble\porting\nimble\include\modlog/modlog.hºÝµÙSG..\..\..\..\host\nimble\porting\nimble\include\log_common/log_common.hºÝµÙOC..\..\..\..\host\nimble\porting\nimble\include\log_common/ignore.hºÝµÍÙE9..\..\..\..\host\nimble\porting\nimble\include\log/log.hºÝµÙK?..\..\..\..\host\nimble\porting\nimble\include\logcfg/logcfg.hºÝµŸÙK?..\..\..\..\host\nimble\nimble\host\include\host/ble_hs_mbuf.hºÝµ”ÙK?..\..\..\..\host\nimble\nimble\host\include\host/ble_hs_stop.hºÝµxÙK?..\..\..\..\host\nimble\nimble\host\include\host/ble_ibeacon.hºÝµ§ÙI=..\..\..\..\host\nimble\nimble\host\include\host/ble_l2cap.hºÝµªÙG;..\..\..\..\host\nimble\nimble\include\nimble/nimble_opt.hºÝµJÙL@..\..\..\..\host\nimble\nimble\include\nimble/nimble_opt_auto.hºÝµ(ÙF:..\..\..\..\host\nimble\nimble\host\include\host/ble_sm.hºÝµ¢ÙI=..\..\..\..\host\nimble\nimble\host\include\host/ble_store.hºÝµOÙD8..\..\..\..\host\nimble\nimble\host\src\ble_gatt_priv.hºÝµ?ÙF:..\..\..\..\host\nimble\nimble\host\src\ble_hs_hci_priv.hºÝµ}ÙI=..\..\..\..\host\nimble\nimble\host\src\ble_hs_atomic_priv.hºÝµ.ÙG;..\..\..\..\host\nimble\nimble\host\src\ble_hs_conn_priv.hºÝµÙE9..\..\..\..\host\nimble\nimble\host\src\ble_l2cap_priv.hºÝµÙI=..\..\..\..\host\nimble\nimble\host\src\ble_l2cap_coc_priv.hºÝµÙI=..\..\..\..\host\nimble\nimble\host\src\ble_l2cap_sig_priv.hºÝµqÙG;..\..\..\..\host\nimble\nimble\host\src\ble_hs_mbuf_priv.hºÝµÙJ>..\..\..\..\host\nimble\nimble\host\src\ble_hs_startup_priv.hºÝµ–ÙB6..\..\..\..\host\nimble\nimble\host\src\ble_sm_priv.hºÝµÙF:..\..\..\..\host\nimble\nimble\host\src\ble_hs_adv_priv.hºÝµvÙG;..\..\..\..\host\nimble\nimble\host\src\ble_hs_flow_priv.hºÝµ÷ÙG;..\..\..\..\host\nimble\nimble\host\src\ble_hs_pvcy_priv.hºÝµíÙE9..\..\..\..\host\nimble\nimble\host\src\ble_hs_id_priv.hºÝµæÙPD..\..\..\..\host\nimble\nimble\host\src\ble_hs_periodic_sync_priv.hºÝµ2ÙD8..\..\..\..\host\nimble\nimble\host\src\ble_uuid_priv.hºÝµ8ÙB6..\..\..\..\host\nimble\nimble\host\src\ble_att_clt.cºÝµ.ÚPSAMPLE_CONFIG_H/ÚPCONFIG_SYSTEM_CLOCKàÚPCONFIG_PERIPH_DIVIDE²Ú PCONFIG_SOC_DCDC_PAN10700Ú#PCONFIG_FREERTOS_HEAP_PRINT¯Ú#PCONFIG_VECTOR_REMAP_TO_RAMšÚ'PCONFIG_SYSTEM_WATCH_DOG_ENABLE€ÚPCONFIG_RAM_FUNCTIONëÚPCONFIG_RAM_CODE>ÚPCONFIG_LOG_ENABLE¬ÚPCONFIG_FLASH_LDO_ENòÚPCONFIG_FLASH_LDO_VOL’Ú"PCONFIG_USER_CHIP_MAC_ADDRÚ#PCONFIG_LOW_SPEED_CLOCK_SRC®Ú%PCONFIG_BT_MAX_NUM_OF_CENTRALøÚ(P CONFIG_BT_MAX_NUM_OF_PERIPHERALÚ$PCONFIG_BT_CTLR_TX_POWER_DFT"Ú#PCONFIG_FORCE_CALIB_RCL_CLKàÚ$PCONFIG_CNTRL_MEM_POOL_PRINT:Ú PCONFIG_BT_CTLR_AGC_MODE°Ú(P CONFIG_BT_CTLR_LINK_LAYER_DEBUGÚPCONFIG_RF_CALIBFÚP


CONFIG_PMÚ+P#CONFIG_KEEP_FLASH_POWER_IN_LP_MODEÚ PCONFIG_DEEPSLEEP_MODE_2ÜÚ.P&CONFIG_SOC_INCREASE_LPLDOH_CALIB_CODEˆÚ2P*CONFIG_PM_STANDBY_M1_WAKEUP_WITHOUT_RESETÕÚ)P!CONFIG_AUTO_OPTIMIZE_POWER_PARAM±Ú&PCONFIG_TEMP_SAMPLE_INTERVAL_S¯Ú$PCONFIG_DVDD_VOL_OPTIMIZE_ENLÚ PCONFIG_HCLK_OPTIMIZE_EN¤Ú#PCONFIG_SETTINGS_START_ADDRªÚ#PCONFIG_SETTINGS_SECTOR_NUM“ÚP__stdlib_h°ÚP__ARMCLIB_VERSIONlÚP__ARMCC_VERSIONÚP__LONGLONG™ÚP_ARMABI²ÚP _ARMABI_PURE ÚP_ARMABI_NORETURNÄÚP_ARMABI_THROW³ÚP__STDLIB_DECLSeÚP__USE_C99_STDLIBËÚP__STDC_VERSION__zÚP    __CLIBNSBÚP__cplusplus


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"‘ TRIM_CAL_CNTfÚ 


"‘TRIM_IDEAL_CNTÓÚ 


"‘TRIM_REAL_CNTÚTRIM_TÚ#PTRIM_MEASURE_TUNING_EN_Pos3Ú#PTRIM_MEASURE_TUNING_EN_Msk:Ú"PTRIM_COARSE_TUNING_EN_PosŠÚ"PTRIM_COARSE_TUNING_EN_Msk‘Ú PTRIM_FINE_TUNING_EN_Pos)Ú PTRIM_FINE_TUNING_EN_Msk0ÚPTRIM_COARSE_CODE_Pos@ÚPTRIM_COARSE_CODE_MskGÚPTRIM_FINE_CODE_PosßÚPTRIM_FINE_CODE_MskæÚPTRIM_BIT_WIDTH_Pos½ÚPTRIM_BIT_WIDTH_MskÄÚPTRIM_CLRL_RELATION_Pos‰ÚPTRIM_CLRL_RELATION_MskÚ$PTRIM_CLRL_EARLY_TERM_EN_Pos×Ú$PTRIM_CLRL_EARLY_TERM_EN_MskÞÚ%PTRIM_CLRL_FAIL_CLAC_FLAG_PosÔÚ%PTRIM_CLRL_FAIL_CLAC_FLAG_MskÛÚ PTRIM_CLRL_CODE_STEP_Pos/Ú PTRIM_CLRL_CODE_STEP_Msk6Ú PTRIM_CLRL_ERR_RANGE_Pos0Ú PTRIM_CLRL_ERR_RANGE_Msk7ÚPTRIM_INT_EN_Pos¤ÚPTRIM_INT_EN_Msk«Ú"PTRIM_INT_MEASURE_STOP_PoslÚ"PTRIM_INT_MEASURE_STOP_MsksÚ#PTRIM_FLAG_MEASURE_STOP_Pos;Ú#PTRIM_FLAG_MEASURE_STOP_MskBÚ PTRIM_INT_CTUNE_STOP_PosÚ PTRIM_INT_CTUNE_STOP_Msk


Ú!PTRIM_FLAG_CTUNE_STOP_PosÒÚ!PTRIM_FLAG_CTUNE_STOP_MskÙÚ PTRIM_INT_FTUNE_STOP_PosÚ PTRIM_INT_FTUNE_STOP_MskÚ!PTRIM_FLAG_FTUNE_STOP_PosÏÚ!PTRIM_FLAG_FTUNE_STOP_MskÖÚPTRIM_INT_OVERFLOW_Pos·ÚPTRIM_INT_OVERFLOW_Msk¾ÚPTRIM_FLAG_OVERFLOW_Pos†ÚPTRIM_FLAG_OVERFLOW_MskÚPTRIM_CALC_CNT_Pos&ÚPTRIM_CALC_CNT_Msk-ÚPTRIM_CALC_WATI_CNT_PosˆÚPTRIM_CALC_WATI_CNT_MskÚ8


<unnamed>QÚ 


"ÆMODEËÚ 


"ÆDINOFF6Ú 


"ÆDOUT´Ú 


"ÆDATMSK(Ú 


"ÆPINÚ 


"ÆDBEN×Ú 


"ÆINTTYPE½Ú 


"ÆINTENpÚ 


"ÆINTSRCÚGPIO_TÚ8


<unnamed>QÚ 


"ÑDBCTLzÚ


GPIO_DB_T(ÚPGP_MODE_MODE0_PosIÚPGP_MODE_MODE0_MskPÚPGP_MODE_MODE1_PosHÚPGP_MODE_MODE1_MskOÚPGP_MODE_MODE2_PosGÚPGP_MODE_MODE2_MskNÚPGP_MODE_MODE3_PosFÚPGP_MODE_MODE3_MskMÚPGP_MODE_MODE4_PosEÚPGP_MODE_MODE4_MskLÚPGP_MODE_MODE5_PosDÚPGP_MODE_MODE5_MskKÚPGP_DINOFF_DINOFF0_PosÚPGP_DINOFF_DINOFF0_Msk&ÚPGP_DINOFF_DINOFF1_PosÚPGP_DINOFF_DINOFF1_Msk%ÚPGP_DINOFF_DINOFF2_PosÚPGP_DINOFF_DINOFF2_Msk$ÚPGP_DINOFF_DINOFF3_PosÚPGP_DINOFF_DINOFF3_Msk#ÚPGP_DINOFF_DINOFF4_PosÚPGP_DINOFF_DINOFF4_Msk"ÚPGP_DINOFF_DINOFF5_PosÚPGP_DINOFF_DINOFF5_Msk!ÚPGP_DINOFF_DINOFF6_PosÚPGP_DINOFF_DINOFF6_Msk ÚPGP_DINOFF_DINOFF7_PosÚPGP_DINOFF_DINOFF7_MskÚPGP_DOUT_DOUT0_PosÚPGP_DOUT_DOUT0_Msk"ÚPGP_DOUT_DOUT1_PosÚPGP_DOUT_DOUT1_Msk!ÚPGP_DOUT_DOUT2_PosÚPGP_DOUT_DOUT2_Msk ÚPGP_DOUT_DOUT3_PosÚPGP_DOUT_DOUT3_MskÚPGP_DOUT_DOUT4_PosÚPGP_DOUT_DOUT4_MskÚPGP_DOUT_DOUT5_PosÚPGP_DOUT_DOUT5_MskÚPGP_DOUT_DOUT6_PosÚPGP_DOUT_DOUT6_MskÚPGP_DOUT_DOUT7_PosÚPGP_DOUT_DOUT7_MskÚPGP_DATMSK_DATMSK0_PosÚPGP_DATMSK_DATMSK0_Msk


ÚPGP_DATMSK_DATMSK1_PosÚPGP_DATMSK_DATMSK1_Msk    ÚPGP_DATMSK_DATMSK2_PosÚPGP_DATMSK_DATMSK2_MskÚPGP_DATMSK_DATMSK3_PosÚPGP_DATMSK_DATMSK3_MskÚPGP_DATMSK_DATMSK4_PosÿÚPGP_DATMSK_DATMSK4_MskÚPGP_DATMSK_DATMSK5_PosþÚPGP_DATMSK_DATMSK5_MskÚPGP_DATMSK_DATMSK6_PosýÚPGP_DATMSK_DATMSK6_MskÚPGP_DATMSK_DATMSK7_PosüÚPGP_DATMSK_DATMSK7_MskÚPGP_PIN_PIN0_PosÉÚPGP_PIN_PIN0_MskÐÚPGP_PIN_PIN1_PosÈÚPGP_PIN_PIN1_MskÏÚPGP_PIN_PIN2_PosÇÚPGP_PIN_PIN2_MskÎÚPGP_PIN_PIN3_PosÆÚPGP_PIN_PIN3_MskÍÚPGP_PIN_PIN4_PosÅÚPGP_PIN_PIN4_MskÌÚPGP_PIN_PIN5_PosÄÚPGP_PIN_PIN5_MskËÚPGP_PIN_PIN6_PosÃÚPGP_PIN_PIN6_MskÊÚPGP_PIN_PIN7_PosÂÚPGP_PIN_PIN7_MskÉÚPGP_DBEN_DBEN0_PosaÚPGP_DBEN_DBEN0_MskhÚPGP_DBEN_DBEN1_Pos`ÚPGP_DBEN_DBEN1_MskgÚPGP_DBEN_DBEN2_Pos_ÚPGP_DBEN_DBEN2_MskfÚPGP_DBEN_DBEN3_Pos^ÚPGP_DBEN_DBEN3_MskeÚPGP_DBEN_DBEN4_Pos]ÚPGP_DBEN_DBEN4_MskdÚPGP_DBEN_DBEN5_Pos\ÚPGP_DBEN_DBEN5_MskcÚPGP_DBEN_DBEN6_Pos[ÚPGP_DBEN_DBEN6_MskbÚPGP_DBEN_DBEN7_PosZÚPGP_DBEN_DBEN7_MskaÚPGP_INTTYPE_TYPE0_PosÚPGP_INTTYPE_TYPE0_Msk%ÚPGP_INTTYPE_TYPE1_PosÚPGP_INTTYPE_TYPE1_Msk$ÚPGP_INTTYPE_TYPE2_PosÚPGP_INTTYPE_TYPE2_Msk#ÚPGP_INTTYPE_TYPE3_PosÚPGP_INTTYPE_TYPE3_Msk"ÚPGP_INTTYPE_TYPE4_PosÚPGP_INTTYPE_TYPE4_Msk!ÚPGP_INTTYPE_TYPE5_PosÚPGP_INTTYPE_TYPE5_Msk ÚPGP_INTTYPE_TYPE6_PosÚPGP_INTTYPE_TYPE6_MskÚPGP_INTTYPE_TYPE7_PosÚPGP_INTTYPE_TYPE7_MskÚPGP_INTEN_FLIEN0_Pos£ÚPGP_INTEN_FLIEN0_MskªÚPGP_INTEN_FLIEN1_Pos¢ÚPGP_INTEN_FLIEN1_Msk©ÚPGP_INTEN_FLIEN2_Pos¡ÚPGP_INTEN_FLIEN2_Msk¨ÚPGP_INTEN_FLIEN3_Pos ÚPGP_INTEN_FLIEN3_Msk§ÚPGP_INTEN_FLIEN4_PosŸÚPGP_INTEN_FLIEN4_Msk¦ÚPGP_INTEN_FLIEN5_PosžÚPGP_INTEN_FLIEN5_Msk¥ÚPGP_INTEN_FLIEN6_PosÚPGP_INTEN_FLIEN6_Msk¤ÚPGP_INTEN_FLIEN7_PosœÚPGP_INTEN_FLIEN7_Msk£ÚPGP_INTEN_RHIEN0_Pos›ÚPGP_INTEN_RHIEN0_Msk¢ÚPGP_INTEN_RHIEN1_PosšÚPGP_INTEN_RHIEN1_Msk¡ÚPGP_INTEN_RHIEN2_Pos™ÚPGP_INTEN_RHIEN2_Msk ÚPGP_INTEN_RHIEN3_Pos˜ÚPGP_INTEN_RHIEN3_MskŸÚPGP_INTEN_RHIEN4_Pos—ÚPGP_INTEN_RHIEN4_MskžÚPGP_INTEN_RHIEN5_Pos–ÚPGP_INTEN_RHIEN5_MskÚPGP_INTEN_RHIEN6_Pos•ÚPGP_INTEN_RHIEN6_MskœÚPGP_INTEN_RHIEN7_Pos”ÚPGP_INTEN_RHIEN7_Msk›ÚPGP_INTSRC_INTSRC0_PosåÚPGP_INTSRC_INTSRC0_MskìÚPGP_INTSRC_INTSRC1_PosäÚPGP_INTSRC_INTSRC1_MskëÚPGP_INTSRC_INTSRC2_PosãÚPGP_INTSRC_INTSRC2_MskêÚPGP_INTSRC_INTSRC3_PosâÚPGP_INTSRC_INTSRC3_MskéÚPGP_INTSRC_INTSRC4_PosáÚPGP_INTSRC_INTSRC4_MskèÚPGP_INTSRC_INTSRC5_PosàÚPGP_INTSRC_INTSRC5_MskçÚPGP_INTSRC_INTSRC6_PosßÚPGP_INTSRC_INTSRC6_MskæÚPGP_INTSRC_INTSRC7_PosÞÚPGP_INTSRC_INTSRC7_MskåÚPGP_INTSRC_INTSRC8_PosÝÚPGP_INTSRC_INTSRC8_MskäÚPGP_INTSRC_INTSRC9_PosÜÚPGP_INTSRC_INTSRC9_MskãÚPGP_INTSRC_INTSRC10_Pos²ÚPGP_INTSRC_INTSRC10_Msk¹ÚPGP_INTSRC_INTSRC11_Pos±ÚPGP_INTSRC_INTSRC11_Msk¸ÚPGP_INTSRC_INTSRC12_Pos°ÚPGP_INTSRC_INTSRC12_Msk·ÚPGP_INTSRC_INTSRC13_Pos¯ÚPGP_INTSRC_INTSRC13_Msk¶ÚPGP_INTSRC_INTSRC14_Pos®ÚPGP_INTSRC_INTSRC14_MskµÚPGP_INTSRC_INTSRC15_Pos­ÚPGP_INTSRC_INTSRC15_Msk´ÚPGP_DBCTL_DBCLKSEL_PosÚPGP_DBCTL_DBCLKSEL_MskÚPGP_DBCTL_DBCLKSRC_Pos


ÚPGP_DBCTL_DBCLKSRC_MskÚPGP_DBCTL_ICLKON_Pos–ÚPGP_DBCTL_ICLKON_MskÚ8


<unnamed>QÚ 


"† DATWÚ <"† 


RESERVED0JÚ 


"† CTLMÚ 


"† CHENÚ 


"† CMP0Ú 


"† CMP1Ú 


"† STATUSFÚ <"† 


RESERVED1UÚ 


"† TRGDLYTÚ 


"† EXTSMPTóÚ 


"† SEQCTL^Ú 


"† SEQDAT15Ú 


"† SEQDAT24Ú 


"† CTL2Ú <"† 


RESERVED2TÚ 


"† BV_CTLPÚADC_T|ÚPADC_DAT_RESULT_PosØÚPADC_DAT_RESULT_MskßÚPADC_DAT_OV_PosÚPADC_DAT_OV_Msk!ÚPADC_DAT_VALID_PosIÚPADC_DAT_VALID_MskPÚPADC_CTL_ADCEN_PosTÚPADC_CTL_ADCEN_Msk[ÚPADC_CTL_ADCIEN_Pos    ÚPADC_CTL_ADCIEN_MskÚPADC_CTL_HWTRGSEL_Pos9ÚPADC_CTL_HWTRGSEL_Msk@ÚPADC_CTL_HWTRGCOND_Pos÷ÚPADC_CTL_HWTRGCOND_MskþÚPADC_CTL_HWTRGEN_PosŒÚPADC_CTL_HWTRGEN_Msk“ÚPADC_CTL_FIFO_EN_Pos•ÚPADC_CTL_FIFO_EN_MskœÚ$PADC_CTL_FIFO_THRE_STATE_PosÚ$PADC_CTL_FIFO_THRE_STATE_MskÚPADC_CTL_SWTRG_PosÚPADC_CTL_SWTRG_MskÚ"PADC_CTL_LEFT_SHIFT_EN_Pos¥Ú"PADC_CTL_LEFT_SHIFT_EN_Msk¬Ú PADC_CTL_SUB_BIAS_EN_PosIÚ PADC_CTL_SUB_BIAS_EN_MskPÚPADC_CTL_BIAS_VALUE_PosªÚPADC_CTL_BIAS_VALUE_Msk±ÚPADC_CHEN_CHEN0_Pos$ÚPADC_CHEN_CHEN0_Msk+ÚPADC_CHEN_CHEN1_Pos#ÚPADC_CHEN_CHEN1_Msk*ÚPADC_CHEN_CHEN2_Pos"ÚPADC_CHEN_CHEN2_Msk)ÚPADC_CHEN_CHEN3_Pos!ÚPADC_CHEN_CHEN3_Msk(ÚPADC_CHEN_CHEN4_Pos ÚPADC_CHEN_CHEN4_Msk'ÚPADC_CHEN_CHEN5_PosÚPADC_CHEN_CHEN5_Msk&ÚPADC_CHEN_CHEN6_PosÚPADC_CHEN_CHEN6_Msk%ÚPADC_CHEN_CHEN7_PosÚPADC_CHEN_CHEN7_Msk$ÚPADC_CHEN_CHEN8_VBG_PosÖÚPADC_CHEN_CHEN8_VBG_MskÝÚPADC_CHEN_CH9_TMP_PosZÚPADC_CHEN_CH9_TMP_MskaÚ PADC_CHEN_CH10_VDD_4_Pos¬Ú PADC_CHEN_CH10_VDD_4_Msk³Ú PADC_CHEN_CH11_VBG_2_Pos¬Ú PADC_CHEN_CH11_VBG_2_Msk³ÚPADC_CHEN_ALL_Msk¤ÚPADC_CMP0_ADCMPEN_Pos„ÚPADC_CMP0_ADCMPEN_Msk‹ÚPADC_CMP0_ADCMPIE_Pos‰ÚPADC_CMP0_ADCMPIE_MskÚPADC_CMP0_CMPCOND_PosxÚPADC_CMP0_CMPCOND_MskÚPADC_CMP0_CMPCH_PosÚPADC_CMP0_CMPCH_MskÚPADC_CMP0_CMPMCNT_PosjÚPADC_CMP0_CMPMCNT_MskqÚPADC_CMP0_CMPDAT_PosÅÚPADC_CMP0_CMPDAT_MskÌÚPADC_CMP1_ADCMPEN_PosƒÚPADC_CMP1_ADCMPEN_MskŠÚPADC_CMP1_ADCMPIE_PosˆÚPADC_CMP1_ADCMPIE_MskÚPADC_CMP1_CMPCOND_PoswÚPADC_CMP1_CMPCOND_Msk~ÚPADC_CMP1_CMPCH_PosÚPADC_CMP1_CMPCH_MskÚPADC_CMP1_CMPMCNT_PosiÚPADC_CMP1_CMPMCNT_MskpÚPADC_CMP1_CMPDAT_PosÄÚPADC_CMP1_CMPDAT_MskËÚPADC_STATUS_ADIF_Pos–ÚPADC_STATUS_ADIF_MskÚ PADC_STATUS_ADCMPIF0_Pos~Ú PADC_STATUS_ADCMPIF0_Msk…Ú PADC_STATUS_ADCMPIF1_Pos}Ú PADC_STATUS_ADCMPIF1_Msk„ÚPADC_STATUS_BUSY_PosgÚPADC_STATUS_BUSY_MsknÚPADC_STATUS_CHANNEL_Pos«ÚPADC_STATUS_CHANNEL_Msk²ÚPADC_STATUS_VALID_Pos8ÚPADC_STATUS_VALID_Msk?Ú#PADC_STATUS_INTMSK_FULL_Pos4Ú#PADC_STATUS_INTMSK_FULL_Msk;Ú$PADC_STATUS_INTMSK_EMPTY_PosÖÚ$PADC_STATUS_INTMSK_EMPTY_MskÝÚ#PADC_STATUS_INTMSK_OVER_Pos+Ú#PADC_STATUS_INTMSK_OVER_Msk2Ú#PADC_STATUS_INTMSK_HALF_PosLÚ#PADC_STATUS_INTMSK_HALF_MskSÚ!PADC_STATUS_INTMSK_AD_PosæÚ!PADC_STATUS_INTMSK_AD_MskíÚ#PADC_STATUS_INTMSK_CMP0_PosWÚ#PADC_STATUS_INTMSK_CMP0_Msk^Ú#PADC_STATUS_INTMSK_CMP1_PosVÚ#PADC_STATUS_INTMSK_CMP1_Msk]ÚPADC_STATUS_OV_Pos    ÚPADC_STATUS_OV_MskÚ&PADC_STATUS_ONE_CH_CLR_SEL_PosGÚ&PADC_STATUS_ONE_CH_CLR_SEL_MskNÚ#PADC_STATUS_ONE_CH_FLAG_PosWÚ#PADC_STATUS_ONE_CH_FLAG_Msk^Ú#PADC_STATUS_INTFLG_FULL_PosFÚ#PADC_STATUS_INTFLG_FULL_MskMÚ$PADC_STATUS_INTFLG_EMPTY_PosèÚ$PADC_STATUS_INTFLG_EMPTY_MskïÚ#PADC_STATUS_INTFLG_OVER_Pos=Ú#PADC_STATUS_INTFLG_OVER_MskDÚ#PADC_STATUS_INTFLG_HALF_Pos^Ú#PADC_STATUS_INTFLG_HALF_MskeÚPADC_STATUS_ADCF_PosœÚPADC_STATUS_ADCF_Msk£ÚPADC_STATUS_ADCMPF0_PosÉÚPADC_STATUS_ADCMPF0_MskÐÚPADC_STATUS_ADCMPF1_PosÈÚPADC_STATUS_ADCMPF1_MskÏÚ!PADC_STATUS_FLAG_FULL_PosôÚ!PADC_STATUS_FLAG_FULL_MskûÚ"PADC_STATUS_FLAG_EMPTY_Pos–Ú"PADC_STATUS_FLAG_EMPTY_MskÚ!PADC_STATUS_FLAG_OVER_PosëÚ!PADC_STATUS_FLAG_OVER_MskòÚ!PADC_STATUS_FLAG_HALF_PosÚ!PADC_STATUS_FLAG_HALF_MskÚPADC_TRGDLY_DELAY_PosGÚPADC_TRGDLY_DELAY_MskNÚ PADC_EXTSMPT_EXTSMPT_PosÚ PADC_EXTSMPT_EXTSMPT_Msk#ÚPADC_SEQCTL_SEQEN_PosDÚPADC_SEQCTL_SEQEN_MskKÚPADC_SEQCTL_SEQTYPE_Pos‘ÚPADC_SEQCTL_SEQTYPE_Msk˜ÚPADC_SEQCTL_MODESEL_Pos³ÚPADC_SEQCTL_MODESEL_MskºÚ PADC_SEQCTL_DELAY_EN_PosYÚ PADC_SEQCTL_DELAY_EN_Msk`ÚPADC_SEQCTL_TRG_SEL_PosŒÚPADC_SEQCTL_TRG_SEL_Msk“Ú!PADC_SEQCTL_ONE_CH_EN_PosúÚ!PADC_SEQCTL_ONE_CH_EN_MskÚPADC_SEQCTL_TRG1CTL_Pos»ÚPADC_SEQCTL_TRG1CTL_MskÂÚPADC_SEQCTL_TRG2CTL_PosºÚPADC_SEQCTL_TRG2CTL_MskÁÚPADC_SEQDAT1_RESULT_Pos¶ÚPADC_SEQDAT1_RESULT_Msk½ÚPADC_SEQDAT1_OV_PosøÚPADC_SEQDAT1_OV_MskÿÚPADC_SEQDAT1_VALID_Pos'ÚPADC_SEQDAT1_VALID_Msk.ÚPADC_SEQDAT2_RESULT_PosµÚPADC_SEQDAT2_RESULT_Msk¼ÚPADC_SEQDAT2_OV_Pos÷ÚPADC_SEQDAT2_OV_MskþÚPADC_SEQDAT2_VALID_Pos&ÚPADC_SEQDAT2_VALID_Msk-ÚPADC_CTL2_TESTMODE_PosÚPADC_CTL2_TESTMODE_MskÚPADC_CTL2_SHSEL_PosüÚPADC_CTL2_SHSEL_MskÚPADC_CTL2_DMA_EN_PosµÚPADC_CTL2_DMA_EN_Msk¼ÚPADC_CTL2_CLKDIV_Pos¼ÚPADC_CTL2_CLKDIV_MskÃÚPADC_SEL_VREF_Pos}ÚPADC_SEL_VREF_Msk„ÚPADC_CTL2_CMPCTL_Pos¶ÚPADC_CTL2_CMPCTL_Msk½ÚPADC_CTL2_DRVCTL_PosªÚPADC_CTL2_DRVCTL_Msk±Ú8


<unnamed>QÚ 


"ÉP0_MFP$Ú 


"ÉP1_MFP#Ú 


"ÉP2_MFP"Ú 


"ÉP3_MFP!Ú <"0ÉRESVLÚ 


"ÉREGLCTL×Ú 


"ÉSTATUSÚ 


"ÉCTRL0ƒÚ 


"ÉCTRL1‚ÚSYS_TEÚPSYS_P0_MFP_MFP_Pos´ÚPSYS_P0_MFP_MFP_Msk»ÚPSYS_P0_MFP_ALT0_Pos„ÚPSYS_P0_MFP_ALT0_Msk‹ÚPSYS_P0_MFP_ALT1_PosƒÚPSYS_P0_MFP_ALT1_MskŠÚPSYS_P0_MFP_ALT2_Pos‚ÚPSYS_P0_MFP_ALT2_Msk‰ÚPSYS_P0_MFP_ALT3_PosÚPSYS_P0_MFP_ALT3_MskˆÚPSYS_P0_MFP_ALT4_Pos€ÚPSYS_P0_MFP_ALT4_Msk‡ÚPSYS_P0_MFP_ALT5_PosÚPSYS_P0_MFP_ALT5_Msk†ÚPSYS_P0_MFP_ALT6_Pos~ÚPSYS_P0_MFP_ALT6_Msk…ÚPSYS_P0_MFP_ALT7_Pos}ÚPSYS_P0_MFP_ALT7_Msk„ÚPSYS_P1_MFP_MFP_Pos³ÚPSYS_P1_MFP_MFP_MskºÚPSYS_P1_MFP_ALT0_PosƒÚPSYS_P1_MFP_ALT0_MskŠÚPSYS_P1_MFP_ALT1_Pos‚ÚPSYS_P1_MFP_ALT1_Msk‰ÚPSYS_P1_MFP_ALT2_PosÚPSYS_P1_MFP_ALT2_MskˆÚPSYS_P1_MFP_ALT3_Pos€ÚPSYS_P1_MFP_ALT3_Msk‡ÚPSYS_P1_MFP_ALT4_PosÚPSYS_P1_MFP_ALT4_Msk†ÚPSYS_P1_MFP_ALT5_Pos~ÚPSYS_P1_MFP_ALT5_Msk…ÚPSYS_P1_MFP_ALT6_Pos}ÚPSYS_P1_MFP_ALT6_Msk„ÚPSYS_P1_MFP_ALT7_Pos|ÚPSYS_P1_MFP_ALT7_MskƒÚPSYS_P1_MFP_TYPE_PosRÚPSYS_P1_MFP_TYPE_MskYÚPSYS_P1_MFP_P12EXT_PosìÚPSYS_P1_MFP_P12EXT_MskóÚPSYS_P1_MFP_P13EXT_PosëÚPSYS_P1_MFP_P13EXT_MskòÚPSYS_P1_MFP_P14EXT_PosêÚPSYS_P1_MFP_P14EXT_MskñÚPSYS_P2_MFP_ALT0_Pos‚ÚPSYS_P2_MFP_ALT0_Msk‰ÚPSYS_P2_MFP_ALT1_PosÚPSYS_P2_MFP_ALT1_MskˆÚPSYS_P2_MFP_ALT2_Pos€ÚPSYS_P2_MFP_ALT2_Msk‡ÚPSYS_P2_MFP_ALT3_PosÚPSYS_P2_MFP_ALT3_Msk†ÚPSYS_P2_MFP_ALT4_Pos~ÚPSYS_P2_MFP_ALT4_Msk…ÚPSYS_P2_MFP_ALT5_Pos}ÚPSYS_P2_MFP_ALT5_Msk„ÚPSYS_P2_MFP_ALT6_Pos|ÚPSYS_P2_MFP_ALT6_MskƒÚPSYS_P2_MFP_ALT7_Pos{ÚPSYS_P2_MFP_ALT7_Msk‚ÚPSYS_P3_MFP_MFP_Pos±ÚPSYS_P3_MFP_MFP_Msk¸ÚPSYS_P3_MFP_ALT0_PosÚPSYS_P3_MFP_ALT0_MskˆÚPSYS_P3_MFP_ALT1_Pos€ÚPSYS_P3_MFP_ALT1_Msk‡ÚPSYS_P3_MFP_ALT2_PosÚPSYS_P3_MFP_ALT2_Msk†ÚPSYS_P3_MFP_ALT4_Pos}ÚPSYS_P3_MFP_ALT4_Msk„ÚPSYS_P3_MFP_ALT5_Pos|ÚPSYS_P3_MFP_ALT5_MskƒÚPSYS_P3_MFP_ALT6_Pos{ÚPSYS_P3_MFP_ALT6_Msk‚ÚPSYS_P3_MFP_P32EXT_PosèÚPSYS_P3_MFP_P32EXT_MskïÚPSYS_P4_MFP_MFP_Pos°ÚPSYS_P4_MFP_MFP_Msk·ÚPSYS_P4_MFP_ALT6_PoszÚPSYS_P4_MFP_ALT6_MskÚPSYS_P4_MFP_ALT7_PosyÚPSYS_P4_MFP_ALT7_Msk€ÚPSYS_P5_MFP_MFP_Pos¯ÚPSYS_P5_MFP_MFP_Msk¶ÚPSYS_P5_MFP_ALT0_PosÚPSYS_P5_MFP_ALT0_Msk†ÚPSYS_P5_MFP_ALT1_Pos~ÚPSYS_P5_MFP_ALT1_Msk…ÚPSYS_P5_MFP_ALT2_Pos}ÚPSYS_P5_MFP_ALT2_Msk„ÚPSYS_P5_MFP_ALT3_Pos|ÚPSYS_P5_MFP_ALT3_MskƒÚPSYS_P5_MFP_ALT4_Pos{ÚPSYS_P5_MFP_ALT4_Msk‚ÚPSYS_P5_MFP_ALT5_PoszÚPSYS_P5_MFP_ALT5_MskÚPSYS_P5_MFP_ALT6_PosyÚPSYS_P5_MFP_ALT6_Msk€ÚPSYS_P5_MFP_ALT7_PosxÚPSYS_P5_MFP_ALT7_MskÚPSYS_P5_MFP_P50EXT_PosæÚPSYS_P5_MFP_P50EXT_MskíÚPSYS_P5_MFP_P51EXT_PosåÚPSYS_P5_MFP_P51EXT_MskìÚ PSYS_REGLCTL_REGLCTL_Pos5Ú PSYS_REGLCTL_REGLCTL_Msk<Ú8


<unnamed>QÚ 


"¾RSTSTSýÚ 


"¾IPRST0.Ú 


"¾IPRST1-Ú 


"¾


BODCTL_3VJÚ 


"¾BLDBCTL_3V    Ú 


"¾CLK_TOP_CTRL_3V6Ú 


"¾RCL_CTRL_3V‰Ú 


"¾    RCH_CTRL{Ú 


"¾XTL_CTRL_3VrÚ 


"¾    XTH_CTRLdÚ 


"¾


DPLL_CTRL*Ú 


"¾ AHB_CLK_CTRLLÚ 


"¾APB1_CLK_CTRLÚ 


"¾APB2_CLK_CTRLÚ 


"¾MEAS_CLK_CTRLïÚCLK_TjÚPCLK_RSTSTS_CHIPRF_PosÉÚPCLK_RSTSTS_CHIPRF_MskÐÚPCLK_RSTSTS_PINRF_PosÚPCLK_RSTSTS_PINRF_MskÚPCLK_RSTSTS_WDTRF_PosÚPCLK_RSTSTS_WDTRF_MskÚPCLK_RSTSTS_LVRRF_PosûÚPCLK_RSTSTS_LVRRF_MskÚPCLK_RSTSTS_BODRF_PosÚPCLK_RSTSTS_BODRF_Msk!ÚPCLK_RSTSTS_SYSRF_PosðÚPCLK_RSTSTS_SYSRF_Msk÷ÚPCLK_RSTSTS_PORRF_PosþÚPCLK_RSTSTS_PORRF_MskÚPCLK_RSTSTS_CPURF_PosÚPCLK_RSTSTS_CPURF_MskÚPCLK_IPRST0_CHIPRST_Pos—ÚPCLK_IPRST0_CHIPRST_MskžÚPCLK_IPRST0_CPURST_PosÕÚPCLK_IPRST0_CPURST_MskÜÚPCLK_IPRST0_DMARST_PosëÚPCLK_IPRST0_DMARST_MskòÚPCLK_IPRST0_RFRST_Pos'ÚPCLK_IPRST0_RFRST_Msk.Ú PCLK_IPRST0_EFUSERST_PosAÚ PCLK_IPRST0_EFUSERST_MskHÚPCLK_IPRST0_USBRST_PosÓÚPCLK_IPRST0_USBRST_MskÚÚ#PCLK_IPRST0_MDMSTDBYRST_PosOÚ#PCLK_IPRST0_MDMSTDBYRST_MskVÚPCLK_IPRST0_MDMRST_PosßÚPCLK_IPRST0_MDMRST_MskæÚ#PCLK_IPRST0_CHIPSCOPEEN_Pos{Ú#PCLK_IPRST0_CHIPSCOPEEN_Msk‚ÚPCLK_IPRST0_FTORRST_Pos€ÚPCLK_IPRST0_FTORRST_Msk‡ÚPCLK_IPRST1_I2C0RST_PosÌÚPCLK_IPRST1_I2C0RST_MskÓÚPCLK_IPRST1_SPI0RST_PosžÚPCLK_IPRST1_SPI0RST_Msk¥ÚPCLK_IPRST1_SPI1RST_PosÚPCLK_IPRST1_SPI1RST_Msk¤Ú PCLK_IPRST1_UART0RST_PosLÚ PCLK_IPRST1_UART0RST_MskSÚ PCLK_IPRST1_UART1RST_PosKÚ PCLK_IPRST1_UART1RST_MskRÚPCLK_IPRST1_PWM0RST_Pos–ÚPCLK_IPRST1_PWM0RST_MskÚPCLK_IPRST1_ADCRST_PosôÚPCLK_IPRST1_ADCRST_MskûÚPCLK_IPRST1_WDTRST_PosÍÚPCLK_IPRST1_WDTRST_MskÔÚPCLK_IPRST1_WWDTRST_PostÚPCLK_IPRST1_WWDTRST_Msk{ÚPCLK_IPRST1_TMR0RST_Pos—ÚPCLK_IPRST1_TMR0RST_MskžÚPCLK_IPRST1_TMR1RST_Pos–ÚPCLK_IPRST1_TMR1RST_MskÚPCLK_IPRST1_TMR2RST_Pos•ÚPCLK_IPRST1_TMR2RST_MskœÚPCLK_IPRST1_GPIORST_Pos‹ÚPCLK_IPRST1_GPIORST_Msk’ÚPCLK_IPRST1_TRIMRST_Pos~ÚPCLK_IPRST1_TRIMRST_Msk…Ú#PCLK_BODCTL_BODRSTEN_Pos_3vMÚ#PCLK_BODCTL_BODRSTEN_Msk_3vTÚPCLK_BODCTL_BODIF_Pos^ÚPCLK_BODCTL_BODIF_MskeÚPCLK_BODCTL_BODOUT_PosóÚPCLK_BODCTL_BODOUT_MskúÚ PCLK_BODCTL_LVREN_Pos_3v-Ú PCLK_BODCTL_LVREN_Msk_3v4Ú PCLK_BODCTL_BODEN_Pos_3vLÚ PCLK_BODCTL_BODEN_Msk_3vSÚ!PCLK_BODCTL_BODSEL_Pos_3vùÚ!PCLK_BODCTL_BODSEL_Msk_3vÚ#PCLK_BODCTL_LVR_TEST_Pos_3vÚ#PCLK_BODCTL_LVR_TEST_Msk_3v"Ú#PCLK_BODCTL_BOD_TEST_Pos_3v:Ú#PCLK_BODCTL_BOD_TEST_Msk_3vAÚ%PCLK_BLDBCTL_LVRDB_SEL_Pos_3v®Ú%PCLK_BLDBCTL_LVRDB_SEL_Msk_3vµÚ%PCLK_BLDBCTL_BODDB_SEL_Pos_3vÍÚ%PCLK_BLDBCTL_BODDB_SEL_Msk_3vÔÚ'PCLK_TOPCTL_RSICV_SYSCNT_EN_PosÔÚ'PCLK_TOPCTL_RSICV_SYSCNT_EN_MskÛÚ#PCLK_TOPCTL_SYS_CLK_SEL_PosÚ#PCLK_TOPCTL_SYS_CLK_SEL_Msk$Ú&PCLK_TOPCTL_32K_CLK_SEL_Pos_3v^Ú&PCLK_TOPCTL_32K_CLK_SEL_Msk_3veÚPCLK_TOPCTL_AHB_DIV_Pos“ÚPCLK_TOPCTL_AHB_DIV_MskšÚ PCLK_TOPCTL_APB1_DIV_PosXÚ PCLK_TOPCTL_APB1_DIV_Msk_Ú PCLK_TOPCTL_APB2_DIV_PosWÚ PCLK_TOPCTL_APB2_DIV_Msk^Ú#PCLK_RCLCTL_RC32K_EN_Pos_3vkÚ#PCLK_RCLCTL_RC32K_EN_Msk_3vrÚ$PCLK_RCLCTL_RC32K_TST_EN_PosÚ$PCLK_RCLCTL_RC32K_TST_EN_MskÚ"PCLK_RCLCTL_CLK_SEL_Pos_3v‡Ú"PCLK_RCLCTL_CLK_SEL_Msk_3vŽÚ'PCLK_RCLCTL_RC32K_COARSE_Pos_3v9Ú'PCLK_RCLCTL_RC32K_COARSE_Msk_3v@Ú%PCLK_RCLCTL_RC32K_FINE_Pos_3vØÚ%PCLK_RCLCTL_RC32K_FINE_Msk_3vßÚ&PCLK_RCLCTL_RC32K_DELAY_Pos_3v‰Ú&PCLK_RCLCTL_RC32K_DELAY_Msk_3vÚPCLK_RCLCTL_STABLE_PosùÚPCLK_RCLCTL_STABLE_MskÚPCLK_RCHCTL_RCH_EN_PoséÚPCLK_RCHCTL_RCH_EN_MskðÚ"PCLK_RCHCTL_RCH_TST_EN_Pos‡Ú"PCLK_RCHCTL_RCH_TST_EN_MskŽÚPCLK_RCHCTL_CLK_SEL_Pos™ÚPCLK_RCHCTL_CLK_SEL_Msk ÚPCLK_RCHCTL_BIAS_PosÚPCLK_RCHCTL_BIAS_Msk¤Ú PCLK_RCHCTL_RCH_FREQ_PosJÚ PCLK_RCHCTL_RCH_FREQ_MskQÚPCLK_RCHCTL_DELAY_PosKÚPCLK_RCHCTL_DELAY_MskRÚPCLK_RCHCTL_STABLE_PosýÚPCLK_RCHCTL_STABLE_MskÚ!PCLK_XTLCTL_XTL_EN_Pos_3v¥Ú!PCLK_XTLCTL_XTL_EN_Msk_3v¬Ú"PCLK_XTLCTL_XTL_TST_EN_PosQÚ"PCLK_XTLCTL_XTL_TST_EN_MskXÚ$PCLK_XTLCTL_CORE_BIAS_Pos_3vâÚ$PCLK_XTLCTL_CORE_BIAS_Msk_3véÚ#PCLK_XTLCTL_XTL_TRIM_Pos_3vøÚ#PCLK_XTLCTL_XTL_TRIM_Msk_3vÿÚ%PCLK_XTLCTL_XTL_CAP_EN_Pos_3vjÚ%PCLK_XTLCTL_XTL_CAP_EN_Msk_3vqÚ PCLK_XTLCTL_DELAY_Pos_3v"Ú PCLK_XTLCTL_DELAY_Msk_3v)ÚPCLK_XTLCTL_STABLE_PosâÚPCLK_XTLCTL_STABLE_MskéÚPCLK_XTHCTL_XTH_EN_Pos»ÚPCLK_XTHCTL_XTH_EN_MskÂÚ"PCLK_XTHCTL_XTH_TST_EN_PosYÚ"PCLK_XTHCTL_XTH_TST_EN_Msk`Ú"PCLK_XTHCTL_START_FAST_Pos~Ú"PCLK_XTHCTL_START_FAST_Msk…Ú#PCLK_XTHCTL_DEGLITCH_EN_PosaÚ#PCLK_XTHCTL_DEGLITCH_EN_MskhÚ"PCLK_XTHCTL_XO_CAP_SEL_Pos|Ú"PCLK_XTHCTL_XO_CAP_SEL_MskƒÚPCLK_XTHCTL_DELAY_Pos4ÚPCLK_XTHCTL_DELAY_Msk;ÚPCLK_XTHCTL_STABLE_PosæÚPCLK_XTHCTL_STABLE_MskíÚ PCLK_DPLLCTL_DPLL_EN_PosGÚ PCLK_DPLLCTL_DPLL_EN_MskNÚ$PCLK_DPLLCTL_DPLL_TST_EN_PosåÚ$PCLK_DPLLCTL_DPLL_TST_EN_MskìÚ!PCLK_DPLLCTL_FREQ_OUT_PosÞÚ!PCLK_DPLLCTL_FREQ_OUT_MskåÚ!PCLK_DPLLCTL_RCLK_SEL_PosôÚ!PCLK_DPLLCTL_RCLK_SEL_MskûÚ!PCLK_DPLLCTL_ICP_BIAS_Pos    Ú!PCLK_DPLLCTL_ICP_BIAS_MskÚ!PCLK_DPLLCTL_ICP_CTRL_PosóÚ!PCLK_DPLLCTL_ICP_CTRL_MskúÚ"PCLK_DPLLCTL_KVCO_CTRL_PosšÚ"PCLK_DPLLCTL_KVCO_CTRL_Msk¡Ú&PCLK_DPLLCTL_VCO_FREQ_TRIM_PosIÚ&PCLK_DPLLCTL_VCO_FREQ_TRIM_MskPÚ PCLK_DPLLCTL_DIV_SEL_Pos?Ú PCLK_DPLLCTL_DIV_SEL_MskFÚPCLK_DPLLCTL_DELAY_PosúÚPCLK_DPLLCTL_DELAY_MskÚPCLK_DPLLCTL_STABLE_Pos¬ÚPCLK_DPLLCTL_STABLE_Msk³ÚPCLK_AHBCLK_DMAEN_PospÚPCLK_AHBCLK_DMAEN_MskwÚPCLK_AHBCLK_GPIOEN_PosÚPCLK_AHBCLK_GPIOEN_MskÚ"PCLK_AHBCLK_SYSTICK_EN_Pos¯Ú"PCLK_AHBCLK_SYSTICK_EN_Msk¶ÚPCLK_AHBCLK_APB1EN_Pos<ÚPCLK_AHBCLK_APB1EN_MskCÚPCLK_AHBCLK_APB2EN_Pos;ÚPCLK_AHBCLK_APB2EN_MskBÚPCLK_AHBCLK_AHBEN_PoswÚPCLK_AHBCLK_AHBEN_Msk~Ú!PCLK_AHBCLK_BLE32M_EN_PosVÚ!PCLK_AHBCLK_BLE32M_EN_Msk]Ú!PCLK_AHBCLK_BLE32K_EN_PosXÚ!PCLK_AHBCLK_BLE32K_EN_Msk_Ú"PCLK_AHBCLK_BLE32M_SEL_PosÚ"PCLK_AHBCLK_BLE32M_SEL_Msk


Ú"PCLK_AHBCLK_ROM_CLK_EN_Pos²Ú"PCLK_AHBCLK_ROM_CLK_EN_Msk¹Ú$PCLK_AHBCLK_EFUSE_CLK_EN_Pos$Ú$PCLK_AHBCLK_EFUSE_CLK_EN_Msk+Ú&PCLK_AHBCLK_USB_AHB_CLK_EN_Pos„Ú&PCLK_AHBCLK_USB_AHB_CLK_EN_Msk‹Ú&PCLK_AHBCLK_USB_48M_CLK_EN_Pos–Ú&PCLK_AHBCLK_USB_48M_CLK_EN_MskÚ%PCLK_AHBCLK_SPI_FLASH_DIV_PosÊÚ%PCLK_AHBCLK_SPI_FLASH_DIV_MskÑÚ)P!CLK_AHBCLK_SPI_FLASH_CLK_SEL_PosˆÚ)P!CLK_AHBCLK_SPI_FLASH_CLK_SEL_MskÚ'PCLK_AHBCLK_DPLL_CLK_TST_EN_PosÚ'PCLK_AHBCLK_DPLL_CLK_TST_EN_MskÚ(P CLK_AHBCLK_SPI_CLK_SEL_FPGA_PosÚÚ(P CLK_AHBCLK_SPI_CLK_SEL_FPGA_MskáÚ#PCLK_APB1CLK_WDTSRC_SEL_PosvÚ#PCLK_APB1CLK_WDTSRC_SEL_Msk}Ú$PCLK_APB1CLK_WWDTSRC_SEL_PosÚ$PCLK_APB1CLK_WWDTSRC_SEL_Msk$Ú$PCLK_APB1CLK_TMR0SRC_SEL_Pos@Ú$PCLK_APB1CLK_TMR0SRC_SEL_MskGÚ&PCLK_APB1CLK_PWM01_CLK_SEL_Pos¹Ú&PCLK_APB1CLK_PWM01_CLK_SEL_MskÀÚ&PCLK_APB1CLK_PWM23_CLK_SEL_PosµÚ&PCLK_APB1CLK_PWM23_CLK_SEL_Msk¼Ú&PCLK_APB1CLK_PWM45_CLK_SEL_Pos±Ú&PCLK_APB1CLK_PWM45_CLK_SEL_Msk¸Ú&PCLK_APB1CLK_PWM67_CLK_SEL_Pos­Ú&PCLK_APB1CLK_PWM67_CLK_SEL_Msk´Ú$PCLK_APB1CLK_ADC_CLK_SEL_PosJÚ$PCLK_APB1CLK_ADC_CLK_SEL_MskQÚ$PCLK_APB2CLK_TMR1SRC_SEL_Pos>Ú$PCLK_APB2CLK_TMR1SRC_SEL_MskEÚ$PCLK_APB2CLK_TMR2SRC_SEL_Pos=Ú$PCLK_APB2CLK_TMR2SRC_SEL_MskDÚ$PCLK_MEASCLK_TRIM_CLK_EN_PosÚ$PCLK_MEASCLK_TRIM_CLK_EN_MskÚ%PCLK_MEASCLK_TRIM_CLK_SEL_Pos²Ú%PCLK_MEASCLK_TRIM_CLK_SEL_Msk¹Ú%PCLK_MEASCLK_TRIM_CLK_DIV_Pos³Ú%PCLK_MEASCLK_TRIM_CLK_DIV_MskºÚ%PCLK_MEASCLK_XTL_QUICK_EN_Pos¤Ú%PCLK_MEASCLK_XTL_QUICK_EN_Msk«Ú PCLK_MEASCLK_XTH_DIV_Pos>Ú PCLK_MEASCLK_XTH_DIV_MskEÚ8


<unnamed>QÚ 


"½CTLÚ 


"½ALTCTL+ÚWDT_TUÚPWDT_CTL_RSTCNT_Pos¨ÚPWDT_CTL_RSTCNT_Msk¯ÚPWDT_CTL_RSTEN_PosüÚPWDT_CTL_RSTEN_MskÚPWDT_CTL_RSTF_PosKÚPWDT_CTL_RSTF_MskRÚPWDT_CTL_IF_PosÿÚPWDT_CTL_IF_MskÚPWDT_CTL_WKEN_PosUÚPWDT_CTL_WKEN_Msk\ÚPWDT_CTL_WKF_Pos¤ÚPWDT_CTL_WKF_Msk«ÚPWDT_CTL_INTEN_Pos


ÚPWDT_CTL_INTEN_MskÚPWDT_CTL_WDTEN_PosÚPWDT_CTL_WDTEN_Msk ÚPWDT_CTL_TOUTSEL_PosTÚPWDT_CTL_TOUTSEL_Msk[Ú#PWDT_CTL_RST_REGION_SEL_PosÚ#PWDT_CTL_RST_REGION_SEL_MskÚPWDT_CTL_TOF_Pos£ÚPWDT_CTL_TOF_MskªÚPWDT_CTL_ICEDEBUG_PosJÚPWDT_CTL_ICEDEBUG_MskQÚPWDT_ALTCTL_RSTDSEL_Pos|ÚPWDT_ALTCTL_RSTDSEL_MskƒÚ8


<unnamed>QÚ 


"ÛRLDCNT


Ú 


"ÛCTLôÚ 


"ÛSTATUSíÚ 


"ÛCNTòÚWWDT_TüÚPWWDT_RLDCNT_RLDCNT_Pos|ÚPWWDT_RLDCNT_RLDCNT_MskƒÚPWWDT_CTL_WWDTEN_PosTÚPWWDT_CTL_WWDTEN_Msk[ÚPWWDT_CTL_INTEN_Pos±ÚPWWDT_CTL_INTEN_Msk¸ÚPWWDT_CTL_PSCSEL_PoscÚPWWDT_CTL_PSCSEL_MskjÚPWWDT_CTL_CMPDAT_PostÚPWWDT_CTL_CMPDAT_Msk{ÚPWWDT_CTL_ICEDEBUG_PosñÚPWWDT_CTL_ICEDEBUG_MskøÚPWWDT_STATUS_WWDTIF_PosQÚPWWDT_STATUS_WWDTIF_MskXÚPWWDT_STATUS_WWDTRF_PosHÚPWWDT_STATUS_WWDTRF_MskOÚPWWDT_STATUS_WWDTF_PosœÚPWWDT_STATUS_WWDTF_Msk£ÚPWWDT_CNT_CNTDAT_PosmÚPWWDT_CNT_CNTDAT_MsktÚ8


<unnamed>QÚ 


"õCLKPSC÷Ú 


"õCLKDIVúÚ 


"õCTLÚÚ 


"õPERIOD0ÂÚ 


"õPERIOD1ÁÚ 


"õPERIOD2ÀÚ 


"õPERIOD3¿Ú 


"õPERIOD4¾Ú 


"õPERIOD5½Ú 


"õPERIOD6¼Ú 


"õPERIOD7»Ú 


"õCMPDAT0ÌÚ 


"õCMPDAT1ËÚ 


"õCMPDAT2ÊÚ 


"õCMPDAT3ÉÚ 


"õCMPDAT4ÈÚ 


"õCMPDAT5ÇÚ 


"õCMPDAT6ÆÚ 


"õCMPDAT7ÅÚ 


"õCTL2¦Ú 


"õFLAG¡Ú 


"õINTEN;Ú 


"õINTSTSÒÚ 


"õPOEN‰Ú <"õ


RESERVED0ïÚ 


"õDTCTL>Ú 


"õ    ADCTCTL0„Ú 


"õ    ADCTCTL1ƒÚ 


"õ    ADCTSTS0mÚ 


"õ    ADCTSTS1lÚ <"õ


RESERVED1âÚ 


"õPCACTLÚPWM_TPÚ PPWM_CLKPSC_CLKPSC01_PosyÚ PPWM_CLKPSC_CLKPSC01_Msk€Ú PPWM_CLKPSC_CLKPSC23_PosuÚ PPWM_CLKPSC_CLKPSC23_Msk|Ú PPWM_CLKPSC_CLKPSC45_PosqÚ PPWM_CLKPSC_CLKPSC45_MskxÚ PPWM_CLKPSC_CLKPSC67_PosmÚ PPWM_CLKPSC_CLKPSC67_MsktÚPPWM_CLKDIV_CLKDIV0_Pos²ÚPPWM_CLKDIV_CLKDIV0_Msk¹ÚPPWM_CLKDIV_CLKDIV1_Pos±ÚPPWM_CLKDIV_CLKDIV1_Msk¸ÚPPWM_CLKDIV_CLKDIV2_Pos°ÚPPWM_CLKDIV_CLKDIV2_Msk·ÚPPWM_CLKDIV_CLKDIV3_Pos¯ÚPPWM_CLKDIV_CLKDIV3_Msk¶ÚPPWM_CLKDIV_CLKDIV4_Pos®ÚPPWM_CLKDIV_CLKDIV4_MskµÚPPWM_CLKDIV_CLKDIV5_Pos­ÚPPWM_CLKDIV_CLKDIV5_Msk´ÚPPWM_CLKDIV_CLKDIV6_Pos¬ÚPPWM_CLKDIV_CLKDIV6_Msk³ÚPPWM_CLKDIV_CLKDIV7_Pos«ÚPPWM_CLKDIV_CLKDIV7_Msk²ÚPPWM_CTL_CNTEN0_PosÙÚPPWM_CTL_CNTEN0_MskàÚPPWM_CTL_PINV0_PosÚPPWM_CTL_PINV0_MskÚPPWM_CTL_CNTMODE0_PosCÚPPWM_CTL_CNTMODE0_MskJÚPPWM_CTL_CNTEN1_PosØÚPPWM_CTL_CNTEN1_MskßÚPPWM_CTL_HCUPDT_Pos¹ÚPPWM_CTL_HCUPDT_MskÀÚPPWM_CTL_PINV1_PosÚPPWM_CTL_PINV1_MskÚPPWM_CTL_CNTMODE1_PosBÚPPWM_CTL_CNTMODE1_MskIÚPPWM_CTL_CNTEN2_Pos×ÚPPWM_CTL_CNTEN2_MskÞÚPPWM_CTL_PINV2_PosÚPPWM_CTL_PINV2_MskÚPPWM_CTL_CNTMODE2_PosAÚPPWM_CTL_CNTMODE2_MskHÚPPWM_CTL_CNTEN3_PosÖÚPPWM_CTL_CNTEN3_MskÝÚPPWM_CTL_PINV3_PosÚPPWM_CTL_PINV3_MskÚPPWM_CTL_CNTMODE3_Pos@ÚPPWM_CTL_CNTMODE3_MskGÚPPWM_CTL_CNTEN4_PosÕÚPPWM_CTL_CNTEN4_MskÜÚPPWM_CTL_PINV4_PosÚPPWM_CTL_PINV4_MskÚPPWM_CTL_CNTMODE4_Pos?ÚPPWM_CTL_CNTMODE4_MskFÚPPWM_CTL_CNTEN5_PosÔÚPPWM_CTL_CNTEN5_MskÛÚPPWM_CTL_ASYMEN_Pos´ÚPPWM_CTL_ASYMEN_Msk»ÚPPWM_CTL_PINV5_PosÚPPWM_CTL_PINV5_MskÚPPWM_CTL_CNTMODE5_Pos>ÚPPWM_CTL_CNTMODE5_MskEÚPPWM_CTL_CNTEN6_PosÓÚPPWM_CTL_CNTEN6_MskÚÚPPWM_CTL_PINV6_PosÚPPWM_CTL_PINV6_MskÚPPWM_CTL_CNTMODE6_Pos=ÚPPWM_CTL_CNTMODE6_MskDÚPPWM_CTL_CNTEN7_PosÒÚPPWM_CTL_CNTEN7_MskÙÚPPWM_CTL_PINV7_PosÚPPWM_CTL_PINV7_MskÚPPWM_CTL_CNTMODE7_Pos<ÚPPWM_CTL_CNTMODE7_MskCÚ PPWM_PERIOD0_PERIOD0_PostÚ PPWM_PERIOD0_PERIOD0_Msk{Ú PPWM_PERIOD0_PERIOD1_PossÚ PPWM_PERIOD0_PERIOD1_MskzÚ PPWM_PERIOD0_PERIOD2_PosrÚ PPWM_PERIOD0_PERIOD2_MskyÚ PPWM_PERIOD0_PERIOD3_PosqÚ PPWM_PERIOD0_PERIOD3_MskxÚ PPWM_PERIOD0_PERIOD4_PospÚ PPWM_PERIOD0_PERIOD4_MskwÚ PPWM_PERIOD0_PERIOD5_PosoÚ PPWM_PERIOD0_PERIOD5_MskvÚ PPWM_PERIOD0_PERIOD6_PosnÚ PPWM_PERIOD0_PERIOD6_MskuÚ PPWM_PERIOD0_PERIOD7_PosmÚ PPWM_PERIOD0_PERIOD7_MsktÚ PPWM_PERIOD1_PERIOD0_PossÚ PPWM_PERIOD1_PERIOD0_MskzÚ PPWM_PERIOD1_PERIOD1_PosrÚ PPWM_PERIOD1_PERIOD1_MskyÚ PPWM_PERIOD1_PERIOD2_PosqÚ PPWM_PERIOD1_PERIOD2_MskxÚ PPWM_PERIOD1_PERIOD3_PospÚ PPWM_PERIOD1_PERIOD3_MskwÚ PPWM_PERIOD1_PERIOD4_PosoÚ PPWM_PERIOD1_PERIOD4_MskvÚ PPWM_PERIOD1_PERIOD5_PosnÚ PPWM_PERIOD1_PERIOD5_MskuÚ PPWM_PERIOD1_PERIOD6_PosmÚ PPWM_PERIOD1_PERIOD6_MsktÚ PPWM_PERIOD1_PERIOD7_PoslÚ PPWM_PERIOD1_PERIOD7_MsksÚ PPWM_PERIOD2_PERIOD0_PosrÚ PPWM_PERIOD2_PERIOD0_MskyÚ PPWM_PERIOD2_PERIOD1_PosqÚ PPWM_PERIOD2_PERIOD1_MskxÚ PPWM_PERIOD2_PERIOD2_PospÚ PPWM_PERIOD2_PERIOD2_MskwÚ PPWM_PERIOD2_PERIOD3_PosoÚ PPWM_PERIOD2_PERIOD3_MskvÚ PPWM_PERIOD2_PERIOD4_PosnÚ PPWM_PERIOD2_PERIOD4_MskuÚ PPWM_PERIOD2_PERIOD5_PosmÚ PPWM_PERIOD2_PERIOD5_MsktÚ PPWM_PERIOD2_PERIOD6_PoslÚ PPWM_PERIOD2_PERIOD6_MsksÚ PPWM_PERIOD2_PERIOD7_PoskÚ PPWM_PERIOD2_PERIOD7_MskrÚ PPWM_PERIOD3_PERIOD0_PosqÚ PPWM_PERIOD3_PERIOD0_MskxÚ PPWM_PERIOD3_PERIOD1_PospÚ PPWM_PERIOD3_PERIOD1_MskwÚ PPWM_PERIOD3_PERIOD2_PosoÚ PPWM_PERIOD3_PERIOD2_MskvÚ PPWM_PERIOD3_PERIOD3_PosnÚ PPWM_PERIOD3_PERIOD3_MskuÚ PPWM_PERIOD3_PERIOD4_PosmÚ PPWM_PERIOD3_PERIOD4_MsktÚ PPWM_PERIOD3_PERIOD5_PoslÚ PPWM_PERIOD3_PERIOD5_MsksÚ PPWM_PERIOD3_PERIOD6_PoskÚ PPWM_PERIOD3_PERIOD6_MskrÚ PPWM_PERIOD3_PERIOD7_PosjÚ PPWM_PERIOD3_PERIOD7_MskqÚ PPWM_PERIOD4_PERIOD0_PospÚ PPWM_PERIOD4_PERIOD0_MskwÚ PPWM_PERIOD4_PERIOD1_PosoÚ PPWM_PERIOD4_PERIOD1_MskvÚ PPWM_PERIOD4_PERIOD2_PosnÚ PPWM_PERIOD4_PERIOD2_MskuÚ PPWM_PERIOD4_PERIOD3_PosmÚ PPWM_PERIOD4_PERIOD3_MsktÚ PPWM_PERIOD4_PERIOD4_PoslÚ PPWM_PERIOD4_PERIOD4_MsksÚ PPWM_PERIOD4_PERIOD5_PoskÚ PPWM_PERIOD4_PERIOD5_MskrÚ PPWM_PERIOD4_PERIOD6_PosjÚ PPWM_PERIOD4_PERIOD6_MskqÚ PPWM_PERIOD4_PERIOD7_PosiÚ PPWM_PERIOD4_PERIOD7_MskpÚ PPWM_PERIOD5_PERIOD0_PosoÚ PPWM_PERIOD5_PERIOD0_MskvÚ PPWM_PERIOD5_PERIOD1_PosnÚ PPWM_PERIOD5_PERIOD1_MskuÚ PPWM_PERIOD5_PERIOD2_PosmÚ PPWM_PERIOD5_PERIOD2_MsktÚ PPWM_PERIOD5_PERIOD3_PoslÚ PPWM_PERIOD5_PERIOD3_MsksÚ PPWM_PERIOD5_PERIOD4_PoskÚ PPWM_PERIOD5_PERIOD4_MskrÚ PPWM_PERIOD5_PERIOD5_PosjÚ PPWM_PERIOD5_PERIOD5_MskqÚ PPWM_PERIOD5_PERIOD6_PosiÚ PPWM_PERIOD5_PERIOD6_MskpÚ PPWM_PERIOD5_PERIOD7_PoshÚ PPWM_PERIOD5_PERIOD7_MskoÚ PPWM_PERIOD6_PERIOD0_PosnÚ PPWM_PERIOD6_PERIOD0_MskuÚ PPWM_PERIOD6_PERIOD1_PosmÚ PPWM_PERIOD6_PERIOD1_MsktÚ PPWM_PERIOD6_PERIOD2_PoslÚ PPWM_PERIOD6_PERIOD2_MsksÚ PPWM_PERIOD6_PERIOD3_PoskÚ PPWM_PERIOD6_PERIOD3_MskrÚ PPWM_PERIOD6_PERIOD4_PosjÚ PPWM_PERIOD6_PERIOD4_MskqÚ PPWM_PERIOD6_PERIOD5_PosiÚ PPWM_PERIOD6_PERIOD5_MskpÚ PPWM_PERIOD6_PERIOD6_PoshÚ PPWM_PERIOD6_PERIOD6_MskoÚ PPWM_PERIOD6_PERIOD7_PosgÚ PPWM_PERIOD6_PERIOD7_MsknÚ PPWM_PERIOD7_PERIOD0_PosmÚ PPWM_PERIOD7_PERIOD0_MsktÚ PPWM_PERIOD7_PERIOD1_PoslÚ PPWM_PERIOD7_PERIOD1_MsksÚ PPWM_PERIOD7_PERIOD2_PoskÚ PPWM_PERIOD7_PERIOD2_MskrÚ PPWM_PERIOD7_PERIOD3_PosjÚ PPWM_PERIOD7_PERIOD3_MskqÚ PPWM_PERIOD7_PERIOD4_PosiÚ PPWM_PERIOD7_PERIOD4_MskpÚ PPWM_PERIOD7_PERIOD5_PoshÚ PPWM_PERIOD7_PERIOD5_MskoÚ PPWM_PERIOD7_PERIOD6_PosgÚ PPWM_PERIOD7_PERIOD6_MsknÚ PPWM_PERIOD7_PERIOD7_PosfÚ PPWM_PERIOD7_PERIOD7_MskmÚPPWM_CMPDAT0_CMP0_PosgÚPPWM_CMPDAT0_CMP0_MsknÚPPWM_CMPDAT0_CMP1_PosfÚPPWM_CMPDAT0_CMP1_MskmÚPPWM_CMPDAT0_CMP2_PoseÚPPWM_CMPDAT0_CMP2_MsklÚPPWM_CMPDAT0_CMP3_PosdÚPPWM_CMPDAT0_CMP3_MskkÚPPWM_CMPDAT0_CMP4_PoscÚPPWM_CMPDAT0_CMP4_MskjÚPPWM_CMPDAT0_CMP5_PosbÚPPWM_CMPDAT0_CMP5_MskiÚPPWM_CMPDAT0_CMP6_PosaÚPPWM_CMPDAT0_CMP6_MskhÚPPWM_CMPDAT0_CMP7_Pos`ÚPPWM_CMPDAT0_CMP7_MskgÚPPWM_CMPDAT0_CMPD0_Pos!ÚPPWM_CMPDAT0_CMPD0_Msk(ÚPPWM_CMPDAT0_CMPD1_Pos ÚPPWM_CMPDAT0_CMPD1_Msk'ÚPPWM_CMPDAT0_CMPD2_PosÚPPWM_CMPDAT0_CMPD2_Msk&ÚPPWM_CMPDAT0_CMPD3_PosÚPPWM_CMPDAT0_CMPD3_Msk%ÚPPWM_CMPDAT0_CMPD4_PosÚPPWM_CMPDAT0_CMPD4_Msk$ÚPPWM_CMPDAT0_CMPD5_PosÚPPWM_CMPDAT0_CMPD5_Msk#ÚPPWM_CMPDAT0_CMPD6_PosÚPPWM_CMPDAT0_CMPD6_Msk"ÚPPWM_CMPDAT0_CMPD7_PosÚPPWM_CMPDAT0_CMPD7_Msk!ÚPPWM_CMPDAT1_CMP0_PosfÚPPWM_CMPDAT1_CMP0_MskmÚPPWM_CMPDAT1_CMP1_PoseÚPPWM_CMPDAT1_CMP1_MsklÚPPWM_CMPDAT1_CMP2_PosdÚPPWM_CMPDAT1_CMP2_MskkÚPPWM_CMPDAT1_CMP3_PoscÚPPWM_CMPDAT1_CMP3_MskjÚPPWM_CMPDAT1_CMP4_PosbÚPPWM_CMPDAT1_CMP4_MskiÚPPWM_CMPDAT1_CMP5_PosaÚPPWM_CMPDAT1_CMP5_MskhÚPPWM_CMPDAT1_CMP6_Pos`ÚPPWM_CMPDAT1_CMP6_MskgÚPPWM_CMPDAT1_CMP7_Pos_ÚPPWM_CMPDAT1_CMP7_MskfÚPPWM_CMPDAT1_CMPD0_Pos ÚPPWM_CMPDAT1_CMPD0_Msk'ÚPPWM_CMPDAT1_CMPD1_PosÚPPWM_CMPDAT1_CMPD1_Msk&ÚPPWM_CMPDAT1_CMPD2_PosÚPPWM_CMPDAT1_CMPD2_Msk%ÚPPWM_CMPDAT1_CMPD3_PosÚPPWM_CMPDAT1_CMPD3_Msk$ÚPPWM_CMPDAT1_CMPD4_PosÚPPWM_CMPDAT1_CMPD4_Msk#ÚPPWM_CMPDAT1_CMPD5_PosÚPPWM_CMPDAT1_CMPD5_Msk"ÚPPWM_CMPDAT1_CMPD6_PosÚPPWM_CMPDAT1_CMPD6_Msk!ÚPPWM_CMPDAT1_CMPD7_PosÚPPWM_CMPDAT1_CMPD7_Msk ÚPPWM_CMPDAT2_CMP0_PoseÚPPWM_CMPDAT2_CMP0_MsklÚPPWM_CMPDAT2_CMP1_PosdÚPPWM_CMPDAT2_CMP1_MskkÚPPWM_CMPDAT2_CMP2_PoscÚPPWM_CMPDAT2_CMP2_MskjÚPPWM_CMPDAT2_CMP3_PosbÚPPWM_CMPDAT2_CMP3_MskiÚPPWM_CMPDAT2_CMP4_PosaÚPPWM_CMPDAT2_CMP4_MskhÚPPWM_CMPDAT2_CMP5_Pos`ÚPPWM_CMPDAT2_CMP5_MskgÚPPWM_CMPDAT2_CMP6_Pos_ÚPPWM_CMPDAT2_CMP6_MskfÚPPWM_CMPDAT2_CMP7_Pos^ÚPPWM_CMPDAT2_CMP7_MskeÚPPWM_CMPDAT2_CMPD0_PosÚPPWM_CMPDAT2_CMPD0_Msk&ÚPPWM_CMPDAT2_CMPD1_PosÚPPWM_CMPDAT2_CMPD1_Msk%ÚPPWM_CMPDAT2_CMPD2_PosÚPPWM_CMPDAT2_CMPD2_Msk$ÚPPWM_CMPDAT2_CMPD3_PosÚPPWM_CMPDAT2_CMPD3_Msk#ÚPPWM_CMPDAT2_CMPD4_PosÚPPWM_CMPDAT2_CMPD4_Msk"ÚPPWM_CMPDAT2_CMPD5_PosÚPPWM_CMPDAT2_CMPD5_Msk!ÚPPWM_CMPDAT2_CMPD6_PosÚPPWM_CMPDAT2_CMPD6_Msk ÚPPWM_CMPDAT2_CMPD7_PosÚPPWM_CMPDAT2_CMPD7_MskÚPPWM_CMPDAT3_CMP0_PosdÚPPWM_CMPDAT3_CMP0_MskkÚPPWM_CMPDAT3_CMP1_PoscÚPPWM_CMPDAT3_CMP1_MskjÚPPWM_CMPDAT3_CMP2_PosbÚPPWM_CMPDAT3_CMP2_MskiÚPPWM_CMPDAT3_CMP3_PosaÚPPWM_CMPDAT3_CMP3_MskhÚPPWM_CMPDAT3_CMP4_Pos`ÚPPWM_CMPDAT3_CMP4_MskgÚPPWM_CMPDAT3_CMP5_Pos_ÚPPWM_CMPDAT3_CMP5_MskfÚPPWM_CMPDAT3_CMP6_Pos^ÚPPWM_CMPDAT3_CMP6_MskeÚPPWM_CMPDAT3_CMP7_Pos]ÚPPWM_CMPDAT3_CMP7_MskdÚPPWM_CMPDAT3_CMPD0_PosÚPPWM_CMPDAT3_CMPD0_Msk%ÚPPWM_CMPDAT3_CMPD1_PosÚPPWM_CMPDAT3_CMPD1_Msk$ÚPPWM_CMPDAT3_CMPD2_PosÚPPWM_CMPDAT3_CMPD2_Msk#ÚPPWM_CMPDAT3_CMPD3_PosÚPPWM_CMPDAT3_CMPD3_Msk"ÚPPWM_CMPDAT3_CMPD4_PosÚPPWM_CMPDAT3_CMPD4_Msk!ÚPPWM_CMPDAT3_CMPD5_PosÚPPWM_CMPDAT3_CMPD5_Msk ÚPPWM_CMPDAT3_CMPD6_PosÚPPWM_CMPDAT3_CMPD6_MskÚPPWM_CMPDAT3_CMPD7_PosÚPPWM_CMPDAT3_CMPD7_MskÚPPWM_CMPDAT4_CMP0_PoscÚPPWM_CMPDAT4_CMP0_MskjÚPPWM_CMPDAT4_CMP1_PosbÚPPWM_CMPDAT4_CMP1_MskiÚPPWM_CMPDAT4_CMP2_PosaÚPPWM_CMPDAT4_CMP2_MskhÚPPWM_CMPDAT4_CMP3_Pos`ÚPPWM_CMPDAT4_CMP3_MskgÚPPWM_CMPDAT4_CMP4_Pos_ÚPPWM_CMPDAT4_CMP4_MskfÚPPWM_CMPDAT4_CMP5_Pos^ÚPPWM_CMPDAT4_CMP5_MskeÚPPWM_CMPDAT4_CMP6_Pos]ÚPPWM_CMPDAT4_CMP6_MskdÚPPWM_CMPDAT4_CMP7_Pos\ÚPPWM_CMPDAT4_CMP7_MskcÚPPWM_CMPDAT4_CMPD0_PosÚPPWM_CMPDAT4_CMPD0_Msk$ÚPPWM_CMPDAT4_CMPD1_PosÚPPWM_CMPDAT4_CMPD1_Msk#ÚPPWM_CMPDAT4_CMPD2_PosÚPPWM_CMPDAT4_CMPD2_Msk"ÚPPWM_CMPDAT4_CMPD3_PosÚPPWM_CMPDAT4_CMPD3_Msk!ÚPPWM_CMPDAT4_CMPD4_PosÚPPWM_CMPDAT4_CMPD4_Msk ÚPPWM_CMPDAT4_CMPD5_PosÚPPWM_CMPDAT4_CMPD5_MskÚPPWM_CMPDAT4_CMPD6_PosÚPPWM_CMPDAT4_CMPD6_MskÚPPWM_CMPDAT4_CMPD7_PosÚPPWM_CMPDAT4_CMPD7_MskÚPPWM_CMPDAT5_CMP0_PosbÚPPWM_CMPDAT5_CMP0_MskiÚPPWM_CMPDAT5_CMP1_PosaÚPPWM_CMPDAT5_CMP1_MskhÚPPWM_CMPDAT5_CMP2_Pos`ÚPPWM_CMPDAT5_CMP2_MskgÚPPWM_CMPDAT5_CMP3_Pos_ÚPPWM_CMPDAT5_CMP3_MskfÚPPWM_CMPDAT5_CMP4_Pos^ÚPPWM_CMPDAT5_CMP4_MskeÚPPWM_CMPDAT5_CMP5_Pos]ÚPPWM_CMPDAT5_CMP5_MskdÚPPWM_CMPDAT5_CMP6_Pos\ÚPPWM_CMPDAT5_CMP6_MskcÚPPWM_CMPDAT5_CMP7_Pos[ÚPPWM_CMPDAT5_CMP7_MskbÚPPWM_CMPDAT5_CMPD0_PosÚPPWM_CMPDAT5_CMPD0_Msk#ÚPPWM_CMPDAT5_CMPD1_PosÚPPWM_CMPDAT5_CMPD1_Msk"ÚPPWM_CMPDAT5_CMPD2_PosÚPPWM_CMPDAT5_CMPD2_Msk!ÚPPWM_CMPDAT5_CMPD3_PosÚPPWM_CMPDAT5_CMPD3_Msk ÚPPWM_CMPDAT5_CMPD4_PosÚPPWM_CMPDAT5_CMPD4_MskÚPPWM_CMPDAT5_CMPD5_PosÚPPWM_CMPDAT5_CMPD5_MskÚPPWM_CMPDAT5_CMPD6_PosÚPPWM_CMPDAT5_CMPD6_MskÚPPWM_CMPDAT5_CMPD7_PosÚPPWM_CMPDAT5_CMPD7_MskÚPPWM_CMPDAT6_CMP0_PosaÚPPWM_CMPDAT6_CMP0_MskhÚPPWM_CMPDAT6_CMP1_Pos`ÚPPWM_CMPDAT6_CMP1_MskgÚPPWM_CMPDAT6_CMP2_Pos_ÚPPWM_CMPDAT6_CMP2_MskfÚPPWM_CMPDAT6_CMP3_Pos^ÚPPWM_CMPDAT6_CMP3_MskeÚPPWM_CMPDAT6_CMP4_Pos]ÚPPWM_CMPDAT6_CMP4_MskdÚPPWM_CMPDAT6_CMP5_Pos\ÚPPWM_CMPDAT6_CMP5_MskcÚPPWM_CMPDAT6_CMP6_Pos[ÚPPWM_CMPDAT6_CMP6_MskbÚPPWM_CMPDAT6_CMP7_PosZÚPPWM_CMPDAT6_CMP7_MskaÚPPWM_CMPDAT6_CMPD0_PosÚPPWM_CMPDAT6_CMPD0_Msk"ÚPPWM_CMPDAT6_CMPD1_PosÚPPWM_CMPDAT6_CMPD1_Msk!ÚPPWM_CMPDAT6_CMPD2_PosÚPPWM_CMPDAT6_CMPD2_Msk ÚPPWM_CMPDAT6_CMPD3_PosÚPPWM_CMPDAT6_CMPD3_MskÚPPWM_CMPDAT6_CMPD4_PosÚPPWM_CMPDAT6_CMPD4_MskÚPPWM_CMPDAT6_CMPD5_PosÚPPWM_CMPDAT6_CMPD5_MskÚPPWM_CMPDAT6_CMPD6_PosÚPPWM_CMPDAT6_CMPD6_MskÚPPWM_CMPDAT6_CMPD7_PosÚPPWM_CMPDAT6_CMPD7_MskÚPPWM_CMPDAT7_CMP0_Pos`ÚPPWM_CMPDAT7_CMP0_MskgÚPPWM_CMPDAT7_CMP1_Pos_ÚPPWM_CMPDAT7_CMP1_MskfÚPPWM_CMPDAT7_CMP2_Pos^ÚPPWM_CMPDAT7_CMP2_MskeÚPPWM_CMPDAT7_CMP3_Pos]ÚPPWM_CMPDAT7_CMP3_MskdÚPPWM_CMPDAT7_CMP4_Pos\ÚPPWM_CMPDAT7_CMP4_MskcÚPPWM_CMPDAT7_CMP5_Pos[ÚPPWM_CMPDAT7_CMP5_MskbÚPPWM_CMPDAT7_CMP6_PosZÚPPWM_CMPDAT7_CMP6_MskaÚPPWM_CMPDAT7_CMP7_PosYÚPPWM_CMPDAT7_CMP7_Msk`ÚPPWM_CMPDAT7_CMPD0_PosÚPPWM_CMPDAT7_CMPD0_Msk!ÚPPWM_CMPDAT7_CMPD1_PosÚPPWM_CMPDAT7_CMPD1_Msk ÚPPWM_CMPDAT7_CMPD2_PosÚPPWM_CMPDAT7_CMPD2_MskÚPPWM_CMPDAT7_CMPD3_PosÚPPWM_CMPDAT7_CMPD3_MskÚPPWM_CMPDAT7_CMPD4_PosÚPPWM_CMPDAT7_CMPD4_MskÚPPWM_CMPDAT7_CMPD5_PosÚPPWM_CMPDAT7_CMPD5_MskÚPPWM_CMPDAT7_CMPD6_PosÚPPWM_CMPDAT7_CMPD6_MskÚPPWM_CMPDAT7_CMPD7_PosÚPPWM_CMPDAT7_CMPD7_MskÚPPWM_CTL2_BRKIEN_Pos’ÚPPWM_CTL2_BRKIEN_Msk™ÚPPWM_CTL2_PINTTYPE_PosÌÚPPWM_CTL2_PINTTYPE_MskÓÚPPWM_CTL2_DTCNT01_PosmÚPPWM_CTL2_DTCNT01_MsktÚPPWM_CTL2_DTCNT23_PosiÚPPWM_CTL2_DTCNT23_MskpÚPPWM_CTL2_DTCNT45_PoseÚPPWM_CTL2_DTCNT45_MsklÚPPWM_CTL2_DTCNT67_PosaÚPPWM_CTL2_DTCNT67_MskhÚPPWM_CTL2_CNTCLR_Pos‡ÚPPWM_CTL2_CNTCLR_MskŽÚPPWM_CTL2_MODE_Pos,ÚPPWM_CTL2_MODE_Msk3ÚPPWM_CTL2_GROUPEN_Pos+ÚPPWM_CTL2_GROUPEN_Msk2ÚPPWM_CTL2_CNTTYPE_Pos$ÚPPWM_CTL2_CNTTYPE_Msk+ÚPPWM_FLAG_ZF0_Pos~ÚPPWM_FLAG_ZF0_Msk…ÚPPWM_FLAG_ZF1_Pos}ÚPPWM_FLAG_ZF1_Msk„ÚPPWM_FLAG_ZF2_Pos|ÚPPWM_FLAG_ZF2_MskƒÚPPWM_FLAG_ZF3_Pos{ÚPPWM_FLAG_ZF3_Msk‚ÚPPWM_FLAG_ZF4_PoszÚPPWM_FLAG_ZF4_MskÚPPWM_FLAG_ZF5_PosyÚPPWM_FLAG_ZF5_Msk€ÚPPWM_FLAG_ZF6_PosxÚPPWM_FLAG_ZF6_MskÚPPWM_FLAG_ZF7_PoswÚPPWM_FLAG_ZF7_Msk~ÚPPWM_FLAG_CMPDF0_Pos®ÚPPWM_FLAG_CMPDF0_MskµÚPPWM_FLAG_CMPDF1_Pos­ÚPPWM_FLAG_CMPDF1_Msk´ÚPPWM_FLAG_CMPDF2_Pos¬ÚPPWM_FLAG_CMPDF2_Msk³ÚPPWM_FLAG_CMPDF3_Pos«ÚPPWM_FLAG_CMPDF3_Msk²ÚPPWM_FLAG_CMPDF4_PosªÚPPWM_FLAG_CMPDF4_Msk±ÚPPWM_FLAG_CMPDF5_Pos©ÚPPWM_FLAG_CMPDF5_Msk°ÚPPWM_FLAG_CMPDF6_Pos¨ÚPPWM_FLAG_CMPDF6_Msk¯ÚPPWM_FLAG_CMPDF7_Pos§ÚPPWM_FLAG_CMPDF7_Msk®ÚPPWM_FLAG_PF0_PosˆÚPPWM_FLAG_PF0_MskÚPPWM_FLAG_PF1_Pos‡ÚPPWM_FLAG_PF1_MskŽÚPPWM_FLAG_PF2_Pos†ÚPPWM_FLAG_PF2_MskÚPPWM_FLAG_PF3_Pos…ÚPPWM_FLAG_PF3_MskŒÚPPWM_FLAG_PF4_Pos„ÚPPWM_FLAG_PF4_Msk‹ÚPPWM_FLAG_PF5_PosƒÚPPWM_FLAG_PF5_MskŠÚPPWM_FLAG_PF6_Pos‚ÚPPWM_FLAG_PF6_Msk‰ÚPPWM_FLAG_PF7_PosÚPPWM_FLAG_PF7_MskˆÚPPWM_FLAG_CMPUF0_PosÚPPWM_FLAG_CMPUF0_Msk¤ÚPPWM_FLAG_CMPUF1_PosœÚPPWM_FLAG_CMPUF1_Msk£ÚPPWM_FLAG_CMPUF2_Pos›ÚPPWM_FLAG_CMPUF2_Msk¢ÚPPWM_FLAG_CMPUF3_PosšÚPPWM_FLAG_CMPUF3_Msk¡ÚPPWM_FLAG_CMPUF4_Pos™ÚPPWM_FLAG_CMPUF4_Msk ÚPPWM_FLAG_CMPUF5_Pos˜ÚPPWM_FLAG_CMPUF5_MskŸÚPPWM_FLAG_CMPUF6_Pos—ÚPPWM_FLAG_CMPUF6_MskžÚPPWM_FLAG_CMPUF7_Pos–ÚPPWM_FLAG_CMPUF7_MskÚPPWM_INTEN_ZIEN0_Pos~ÚPPWM_INTEN_ZIEN0_Msk…ÚPPWM_INTEN_ZIEN1_Pos}ÚPPWM_INTEN_ZIEN1_Msk„ÚPPWM_INTEN_ZIEN2_Pos|ÚPPWM_INTEN_ZIEN2_MskƒÚPPWM_INTEN_ZIEN3_Pos{ÚPPWM_INTEN_ZIEN3_Msk‚ÚPPWM_INTEN_ZIEN4_PoszÚPPWM_INTEN_ZIEN4_MskÚPPWM_INTEN_ZIEN5_PosyÚPPWM_INTEN_ZIEN5_Msk€ÚPPWM_INTEN_ZIEN6_PosxÚPPWM_INTEN_ZIEN6_MskÚPPWM_INTEN_ZIEN7_PoswÚPPWM_INTEN_ZIEN7_Msk~ÚPPWM_INTEN_CMPDIEN0_Pos®ÚPPWM_INTEN_CMPDIEN0_MskµÚPPWM_INTEN_CMPDIEN1_Pos­ÚPPWM_INTEN_CMPDIEN1_Msk´ÚPPWM_INTEN_CMPDIEN2_Pos¬ÚPPWM_INTEN_CMPDIEN2_Msk³ÚPPWM_INTEN_CMPDIEN3_Pos«ÚPPWM_INTEN_CMPDIEN3_Msk²ÚPPWM_INTEN_CMPDIEN4_PosªÚPPWM_INTEN_CMPDIEN4_Msk±ÚPPWM_INTEN_CMPDIEN5_Pos©ÚPPWM_INTEN_CMPDIEN5_Msk°ÚPPWM_INTEN_CMPDIEN6_Pos¨ÚPPWM_INTEN_CMPDIEN6_Msk¯ÚPPWM_INTEN_CMPDIEN7_Pos§ÚPPWM_INTEN_CMPDIEN7_Msk®ÚPPWM_INTEN_PIEN0_PosˆÚPPWM_INTEN_PIEN0_MskÚPPWM_INTEN_PIEN1_Pos‡ÚPPWM_INTEN_PIEN1_MskŽÚPPWM_INTEN_PIEN2_Pos†ÚPPWM_INTEN_PIEN2_MskÚPPWM_INTEN_PIEN3_Pos…ÚPPWM_INTEN_PIEN3_MskŒÚPPWM_INTEN_PIEN4_Pos„ÚPPWM_INTEN_PIEN4_Msk‹ÚPPWM_INTEN_PIEN5_PosƒÚPPWM_INTEN_PIEN5_MskŠÚPPWM_INTEN_PIEN6_Pos‚ÚPPWM_INTEN_PIEN6_Msk‰ÚPPWM_INTEN_PIEN7_PosÚPPWM_INTEN_PIEN7_MskˆÚPPWM_INTEN_CMPUIEN0_PosÚPPWM_INTEN_CMPUIEN0_Msk¤ÚPPWM_INTEN_CMPUIEN1_PosœÚPPWM_INTEN_CMPUIEN1_Msk£ÚPPWM_INTEN_CMPUIEN2_Pos›ÚPPWM_INTEN_CMPUIEN2_Msk¢ÚPPWM_INTEN_CMPUIEN3_PosšÚPPWM_INTEN_CMPUIEN3_Msk¡ÚPPWM_INTEN_CMPUIEN4_Pos™ÚPPWM_INTEN_CMPUIEN4_Msk ÚPPWM_INTEN_CMPUIEN5_Pos˜ÚPPWM_INTEN_CMPUIEN5_MskŸÚPPWM_INTEN_CMPUIEN6_Pos—ÚPPWM_INTEN_CMPUIEN6_MskžÚPPWM_INTEN_CMPUIEN7_Pos–ÚPPWM_INTEN_CMPUIEN7_MskÚPPWM_INTSTS_ZIF0_PosdÚPPWM_INTSTS_ZIF0_MskkÚPPWM_INTSTS_ZIF1_PoscÚPPWM_INTSTS_ZIF1_MskjÚPPWM_INTSTS_ZIF2_PosbÚPPWM_INTSTS_ZIF2_MskiÚPPWM_INTSTS_ZIF3_PosaÚPPWM_INTSTS_ZIF3_MskhÚPPWM_INTSTS_ZIF4_Pos`ÚPPWM_INTSTS_ZIF4_MskgÚPPWM_INTSTS_ZIF5_Pos_ÚPPWM_INTSTS_ZIF5_MskfÚPPWM_INTSTS_ZIF6_Pos^ÚPPWM_INTSTS_ZIF6_MskeÚPPWM_INTSTS_ZIF7_Pos]ÚPPWM_INTSTS_ZIF7_MskdÚPPWM_INTSTS_CMPDIF0_Pos”ÚPPWM_INTSTS_CMPDIF0_Msk›ÚPPWM_INTSTS_CMPDIF1_Pos“ÚPPWM_INTSTS_CMPDIF1_MskšÚPPWM_INTSTS_CMPDIF2_Pos’ÚPPWM_INTSTS_CMPDIF2_Msk™ÚPPWM_INTSTS_CMPDIF3_Pos‘ÚPPWM_INTSTS_CMPDIF3_Msk˜ÚPPWM_INTSTS_CMPDIF4_PosÚPPWM_INTSTS_CMPDIF4_Msk—ÚPPWM_INTSTS_CMPDIF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<unnamed>QÚ 


"÷    X_FL_CTLÚ "÷


X_FL_TRIGÑÚ "÷X_FL_CONFIGMÚ <"÷X_FL_WD5Ú 


"÷X_FL_X_MODE Ú "÷X_FL_X2_CMDFÚ "÷X_FL_X4_CMDDÚ "÷X_FL_DP_CMD<Ú "÷ X_FL_RDP_CMDèÚ 


"÷X_FL_REMAP_ADDRÚ 


"÷X_FL_DP_CTL&Ú 


"÷ X_FL_IRQ_CTLÌÚ 


"÷X_FL_SUS_RESU_CMD$ÚFLCTL_TËÚ8


<unnamed>QÚ <"€†X_FL_BUFFERÚFLCTL_W_BUFF_T…Ú"PFLCTL_CTL_BYTES_NUM_R_PoskÚ"PFLCTL_CTL_BYTES_NUM_R_MskrÚ"PFLCTL_CTL_BYTES_NUM_W_PosfÚ"PFLCTL_CTL_BYTES_NUM_W_MskmÚPFLCTL_TRIG_TRG_PosÀÚPFLCTL_TRIG_TRG_MskÇÚ#PFLCTL_CONFIG_FLASH_CAP_Pos|Ú#PFLCTL_CONFIG_FLASH_CAP_MskƒÚ'PFLCTL_CONFIG_TX_ADDR_TRANS_PosÚ'PFLCTL_CONFIG_TX_ADDR_TRANS_MskÚ!PFLCTL_CONFIG_INFO_EN_PosÚ!PFLCTL_CONFIG_INFO_EN_Msk


Ú#PFLCTL_CONFIG_PP_ACTIVE_PosbÚ#PFLCTL_CONFIG_PP_ACTIVE_MskiÚPFLCTL_W_DATA_PosvÚPFLCTL_W_DATA_Msk}Ú%PFLCTL_X_MODE_TIMEOUT_CNT_PosˆÚ%PFLCTL_X_MODE_TIMEOUT_CNT_MskÚ#PFLCTL_X_MODE_RESUME_EN_Pos4Ú#PFLCTL_X_MODE_RESUME_EN_Msk;Ú%PFLCTL_X_MODE_SUS_SUCCESS_Pos€Ú%PFLCTL_X_MODE_SUS_SUCCESS_Msk‡Ú!PFLCTL_X_MODE_CLK_DLY_PosÙÚ!PFLCTL_X_MODE_CLK_DLY_MskàÚ PFLCTL_X_MODE_RX_NEG_PosÚ PFLCTL_X_MODE_RX_NEG_Msk!Ú"PFLCTL_X_MODE_CRC32_EN_PosÊÚ"PFLCTL_X_MODE_CRC32_EN_MskÑÚ&PFLCTL_X_MODE_ENHANCE_MODE_Pos{Ú&PFLCTL_X_MODE_ENHANCE_MODE_Msk‚Ú&PFLCTL_X_MODE_LONG_TIME_OP_Pos5Ú&PFLCTL_X_MODE_LONG_TIME_OP_Msk<Ú'PFLCTL_X_MODE_EN_BURST_WRAP_PosÔÚ'PFLCTL_X_MODE_EN_BURST_WRAP_MskÛÚ'PFLCTL_X_MODE_CS_IDLE_CYCLE_Pos Ú'PFLCTL_X_MODE_CS_IDLE_CYCLE_MskÚ PFLCTL_X_MODE_X_MODE_Pos!Ú PFLCTL_X_MODE_X_MODE_Msk(ÚPFLCTL_X2_CMD_Pos‰ÚPFLCTL_X2_CMD_MskÚPFLCTL_X4_CMD_Pos‡ÚPFLCTL_X4_CMD_MskŽÚPFLCTL_DP_CMD_PosÚPFLCTL_DP_CMD_Msk†ÚPFLCTL_RDP_CMD_Pos+ÚPFLCTL_RDP_CMD_Msk2ÚPFLCTL_REMAP_ADDR_PosOÚPFLCTL_REMAP_ADDR_MskVÚ$PFLCTL_DP_CTL_RDP_WT_CNT_PosÇÚ$PFLCTL_DP_CTL_RDP_WT_CNT_MskÎÚ#PFLCTL_DP_CTL_DP_WT_CNT_PosÚ#PFLCTL_DP_CTL_DP_WT_CNT_Msk"ÚPFLCTL_DP_CTL_DP_EN_PosÚPFLCTL_DP_CTL_DP_EN_Msk†Ú"PFLCTL_PROGRAM_SUS_CMD_PosÚ"PFLCTL_PROGRAM_SUS_CMD_Msk–Ú%PFLCTL_PROGRAM_RESUME_CMD_Pos³Ú%PFLCTL_PROGRAM_RESUME_CMD_MskºÚ PFLCTL_ERASE_SUS_CMD_Pos;Ú PFLCTL_ERASE_SUS_CMD_MskBÚ#PFLCTL_ERASE_RESUME_CMD_Pos_Ú#PFLCTL_ERASE_RESUME_CMD_MskfÚ8


<unnamed>QÚ 


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HS_SPKLEN Ú 


"³CLR_RESTART_DET:ÚI2C_T†ÚPI2C_CON_MASTER_MODEùÚPI2C_CON_SPEEDäÚPI2C_CON_SPEED_0QÚPI2C_CON_SPEED_1PÚ#PI2C_CON_IC_10BITADDR_SLAVEÚ$PI2C_CON_IC_10BITADDR_MASTERÈÚPI2C_CON_IC_RESTART_ENCÚ!PI2C_CON_IC_SLAVE_DISABLE†Ú%PI2C_CON_STOP_DET_IFADDRESSED8ÚPI2C_CON_TX_EMPTY_CTRLÚPI2C_TAR_TARkÚPI2C_TAR_IC_TAR_0çÚPI2C_TAR_IC_TAR_1æÚPI2C_TAR_IC_TAR_2åÚPI2C_TAR_IC_TAR_3äÚPI2C_TAR_IC_TAR_4ãÚPI2C_TAR_IC_TAR_5âÚPI2C_TAR_IC_TAR_6áÚPI2C_TAR_IC_TAR_7àÚPI2C_TAR_IC_TAR_8ßÚPI2C_TAR_IC_TAR_9ÞÚPI2C_TAR_GC_OR_STARTËÚPI2C_TAR_SPECIALIÚ$PI2C_TAR_IC_10BITADDR_MASTERÁÚPI2C_SAR_IC_SAR|ÚPI2C_HS_MADDR_IC_HS_MARüÚPI2C_DATA_CMD_DAT    ÚPI2C_DATA_CMD_CMD_RYÚPI2C_DATA_CMD_STOPšÚPI2C_DATA_CMD_RESTARTµÚPI2C_SS_SCL_HCNTÚPI2C_SS_SCL_LCNTÚPI2C_FS_SCL_HCNT*ÚPI2C_FS_SCL_LCNT&ÚPI2C_HS_SCL_HCNT(ÚPI2C_HS_SCL_LCNT$Ú!PI2C_INTR_STAT_R_RX_UNDERÚ PI2C_INTR_STAT_R_RX_OVERSÚ PI2C_INTR_STAT_R_RX_FULL\Ú PI2C_INTR_STAT_R_TX_OVERQÚ!PI2C_INTR_STAT_R_TX_EMPTYüÚPI2C_INTR_STAT_R_RD_REQ½Ú PI2C_INTR_STAT_R_TX_ABRTdÚ PI2C_INTR_STAT_R_RX_DONEiÚ!PI2C_INTR_STAT_R_ACTIVITY)Ú!PI2C_INTR_STAT_R_STOP_DETÚ"PI2C_INTR_STAT_R_START_DETÊÚ!PI2C_INTR_STAT_R_GEN_CALLAÚ$PI2C_INTR_STAT_R_RESTART_DET/Ú$PI2C_INTR_STAT_R_MST_ON_HOLDÚ!PI2C_INTR_MASK_M_RX_UNDER$Ú PI2C_INTR_MASK_M_RX_OVERhÚ PI2C_INTR_MASK_M_RX_FULLqÚ PI2C_INTR_MASK_M_TX_OVERfÚ!PI2C_INTR_MASK_M_TX_EMPTYÚPI2C_INTR_MASK_M_RD_REQÒÚ PI2C_INTR_MASK_M_TX_ABRTyÚ PI2C_INTR_MASK_M_RX_DONE~Ú!PI2C_INTR_MASK_M_ACTIVITY>Ú!PI2C_INTR_MASK_M_STOP_DET)Ú"PI2C_INTR_MASK_M_START_DETßÚ!PI2C_INTR_MASK_M_GEN_CALLVÚ$PI2C_INTR_MASK_M_RESTART_DETDÚ$PI2C_INTR_MASK_M_MST_ON_HOLD/Ú#PI2C_RAW_INTR_STAT_RX_UNDERsÚ"PI2C_RAW_INTR_STAT_RX_OVER·Ú"PI2C_RAW_INTR_STAT_RX_FULLÀÚ"PI2C_RAW_INTR_STAT_TX_OVERµÚ#PI2C_RAW_INTR_STAT_TX_EMPTY`Ú!PI2C_RAW_INTR_STAT_RD_REQ!Ú"PI2C_RAW_INTR_STAT_TX_ABRTÈÚ"PI2C_RAW_INTR_STAT_RX_DONEÍÚ#PI2C_RAW_INTR_STAT_ACTIVITYÚ#PI2C_RAW_INTR_STAT_STOP_DETxÚ$PI2C_RAW_INTR_STAT_START_DET.Ú#PI2C_RAW_INTR_STAT_GEN_CALL¥Ú&PI2C_RAW_INTR_STAT_RESTART_DET“Ú&PI2C_RAW_INTR_STAT_MST_ON_HOLD~ÚP


I2C_RX_TLóÚP


I2C_TX_TLñÚP I2C_CLR_INTRÚPI2C_CLR_RX_UNDERÇÚPI2C_CLR_TX_OVER    ÚPI2C_CLR_RD_REQuÚPI2C_CLR_TX_ABORTËÚPI2C_CLR_RX_DONE!ÚPI2C_CLR_ACTIVITYáÚPI2C_CLR_STOP_DETÌÚPI2C_CLR_START_DET‚ÚPI2C_CLR_GEN_CALLùÚPI2C_CLR_RESTART_DETçÚPI2C_CLR_MST_ON_HOLDÒÚPI2C_ENABLE_ENABLEßÚPI2C_ENABLE_ABORTÚPI2C_STATUS_ACTIVITYØÚPI2C_STATUS_TFNFÚPI2C_STATUS_TFEpÚPI2C_STATUS_RFNE"ÚPI2C_STATUS_RFErÚ PI2C_STATUS_MST_ACTIVITY}Ú PI2C_STATUS_SLV_ACTIVITY|ÚP


I2C_TXFLRÚP


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<unnamed>QÚ 


"ðLP_REG_SYNC0Ú 


"ðLP_FL_CTRL_3V˜Ú 


"ðLP_SPACING_TIME0ÝÚ 


"ðLP_SPACING_TIME1ÜÚ 


"ðLP_SPACING_TIME2ÛÚ 


"ð


LP_SLPTMRÌÚ 


"ðLP_INT_CTRL+Ú 


"ðLP_DLY_CTRL_3V?Ú 


"ð LP_PTAT_POLYÌÚ 


"ð


LP_HP_LDOØÚ 


"ð LP_LP_LDO_3VæÚ 


"ðLP_ANA_LDOžÚ 


"ðLP_FSYN_LDO,Ú 


"ðLP_SWÚ 


"ðLP_BUCK_3VŸÚ 


"ðANA_ADC_LDOpÚ 


"ð ANA_RFFE_LDOÚ 


"ðANA_VCO_LDOPÚ 


"ðANA_DFT Ú 


"ðANA_MISC_3VbÚ 


"ðANA_RESERVED_3V&Ú 


"ð ACT_32K_CTRL(Ú 


"ðACT_32K_BASECORRÚ 


"ðCPU_ADDR_REMAP_CTRLËÚ 


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<unnamed>QÚ 


"‹!EF_CTLDÚ 


"‹!EF_ADDR


Ú 


"‹!EF_DATNÚ 


"‹!EF_RSV0úÚ 


"‹!EF_VDDIÚ 


"‹!EF_RSV1ùÚ 


"‹!EF_CMDSÚ 


"‹!EF_TRG:Ú 


"‹!EF_PROG_TIMING1…Ú 


"‹!EF_PROG_TIMING2„Ú 


"‹!EF_PROG_TIMING3ƒÚ 


"‹!EF_READ_TIMING4žÚ 


"‹!EF_READ_TIMING5Ú <"0‹!EF_RSV2šÚ 


"‹!EF_OP_ERROR•Ú 


"‹!EF_VERIFY_DEBUG1GÚ 


"‹!EF_VERIFY_DEBUG2FÚ 


"‹!EF_VERIFY_DEBUG3EÚ 


"‹!EF_VERIFY_DEBUG4DÚ 


"‹!EF_FLASH_PERMISSION7ÚEFUSE_TÈÚPEFUSE_CTL_EFUSE_EN_Pos‹ÚPEFUSE_CTL_EFUSE_EN_Msk’ÚPEFUSE_CTL_THR_DVDD_Pos†ÚPEFUSE_CTL_THR_DVDD_MskÚ"PEFUSE_CTL_TAEN_RD_CTL_PosÚ"PEFUSE_CTL_TAEN_RD_CTL_Msk—Ú!PEFUSE_CTL_THR_RD_CTL_PosÌÚ!PEFUSE_CTL_THR_RD_CTL_MskÓÚPEFUSE_CTL_TRD_CTL_PosËÚPEFUSE_CTL_TRD_CTL_MskÒÚ!PEFUSE_CTL_TSR_RD_CTL_PosÁÚ!PEFUSE_CTL_TSR_RD_CTL_MskÈÚ#PEFUSE_CTL_TSR_DVDD_CTL_Pos1Ú#PEFUSE_CTL_TSR_DVDD_CTL_Msk8Ú!PEFUSE_CTL_THP_RD_CTL_PosÎÚ!PEFUSE_CTL_THP_RD_CTL_MskÕÚ&PEFUSE_CTL_THP_PG_AVDD_CTL_PosEÚ&PEFUSE_CTL_THP_PG_AVDD_CTL_MskLÚ#PEFUSE_CTL_TAEN_PGM_CTL_Pos@Ú#PEFUSE_CTL_TAEN_PGM_CTL_MskGÚ"PEFUSE_CTL_THP_PGM_CTL_Pos~Ú"PEFUSE_CTL_THP_PGM_CTL_Msk…ÚPEFUSE_CTL_TPGM_CTL_Pos{ÚPEFUSE_CTL_TPGM_CTL_Msk‚Ú"PEFUSE_CTL_TSP_PGM_CTL_PossÚ"PEFUSE_CTL_TSP_PGM_CTL_MskzÚ&PEFUSE_CTL_TSP_PG_AVDD_CTL_Pos:Ú&PEFUSE_CTL_TSP_PG_AVDD_CTL_MskAÚ!PEFUSE_CTL_TSP_RD_CTL_PosÃÚ%PEFUSE_CTL_TSP_TSP_RD_CTL_MsklÚ%PEFUSE_ADDR_EFUSEADDR_ADR_PosèÚ%PEFUSE_ADDR_EFUSEADDR_ADR_MskïÚ#PEFUSE_DAT_EFUSEDAT_DAT_PosnÚ#PEFUSE_DAT_EFUSEDAT_DAT_MskuÚ+P#EFUSE_DAT_EFUSEDAT_DAT_CONFIRM_PosñÚ+P#EFUSE_DAT_EFUSEDAT_DAT_CONFIRM_MskøÚPEFUSE_VDD_DVDD_REG_Pos›ÚPEFUSE_VDD_DVDD_REG_Msk¢ÚPEFUSE_VDD_AVDD_REG_PosžÚPEFUSE_VDD_AVDD_REG_Msk¥Ú#PEFUSE_CMD_EFUSECMD_CMD_Pos}Ú#PEFUSE_CMD_EFUSECMD_CMD_Msk„Ú"PEFUSE_TRG_EFUSETRG_GO_Pos‹Ú"PEFUSE_TRG_EFUSETRG_GO_Msk’Ú*P"EFUSE_PROG_TIMING1_TSP_RD_SET_PosûÚ*P"EFUSE_PROG_TIMING1_TSP_RD_SET_MskÚ/P'EFUSE_PROG_TIMING1_TSP_PG_AVDD_SET_PosrÚ/P'EFUSE_PROG_TIMING1_TSP_PG_AVDD_SET_MskyÚ+P#EFUSE_PROG_TIMING1_TSP_PGM_SET_Pos«Ú+P#EFUSE_PROG_TIMING1_TSP_PGM_SET_Msk²Ú(P EFUSE_PROG_TIMING2_TPGM_SET_Pos²Ú(P EFUSE_PROG_TIMING2_TPGM_SET_Msk¹Ú+P#EFUSE_PROG_TIMING2_THP_PGM_SET_PosµÚ+P#EFUSE_PROG_TIMING2_THP_PGM_SET_Msk¼Ú,P$EFUSE_PROG_TIMING2_TAEN_PGM_SET_PoswÚ,P$EFUSE_PROG_TIMING2_TAEN_PGM_SET_Msk~Ú/P'EFUSE_PROG_TIMING3_THP_PG_AVDD_SET_Pos{Ú/P'EFUSE_PROG_TIMING3_THP_PG_AVDD_SET_Msk‚Ú*P"EFUSE_PROG_TIMING3_THP_RD_SET_PosÚ*P"EFUSE_PROG_TIMING3_THP_RD_SET_MskÚ,P$EFUSE_READ_TIMING4_TSR_DVDD_SET_Pos‚Ú,P$EFUSE_READ_TIMING4_TSR_DVDD_SET_Msk‰Ú*P"EFUSE_READ_TIMING4_TSR_RD_SET_PosÚ*P"EFUSE_READ_TIMING4_TSR_RD_SET_MskÚ'PEFUSE_READ_TIMING4_TRD_SET_PosÚ'PEFUSE_READ_TIMING4_TRD_SET_Msk#Ú*P"EFUSE_READ_TIMING5_THR_RD_SET_PosÚ*P"EFUSE_READ_TIMING5_THR_RD_SET_Msk#Ú+P#EFUSE_READ_TIMING5_TAEN_RD_SET_PosàÚ+P#EFUSE_READ_TIMING5_TAEN_RD_SET_MskçÚ,P$EFUSE_READ_TIMING5_THR_DVDD_SET_PosŒÚ,P$EFUSE_READ_TIMING5_THR_DVDD_SET_Msk“Ú$PEFUSE_OP_ERROR_OP_ERROR_Pos¾Ú$PEFUSE_OP_ERROR_OP_ERROR_MskÅÚ0P(EFUSE_VERIFY_DEBUG1_VERIFY_DBG_KEY1_PospÚ0P(EFUSE_VERIFY_DEBUG1_VERIFY_DBG_KEY1_MskwÚ0P(EFUSE_VERIFY_DEBUG2_VERIFY_DBG_KEY2_PosnÚ0P(EFUSE_VERIFY_DEBUG2_VERIFY_DBG_KEY2_MskuÚ0P(EFUSE_VERIFY_DEBUG3_VERIFY_DBG_KEY3_PoslÚ0P(EFUSE_VERIFY_DEBUG3_VERIFY_DBG_KEY3_MsksÚ0P(EFUSE_VERIFY_DEBUG4_VERIFY_DBG_KEY4_PosjÚ0P(EFUSE_VERIFY_DEBUG4_VERIFY_DBG_KEY4_MskqÚ(P EFUSE_FLASH_PERMISSION_CTRL_Pos»Ú(P EFUSE_FLASH_PERMISSION_CTRL_MskÂÚ8


<unnamed>QÚ "õ!FADDROÚ "õ!POWER#Ú "õ!INT_IN1šÚ "õ!INT_IN2™Ú "õ!    INT_OUT17Ú "õ!    INT_OUT26Ú "õ!INT_USBxÚ "õ!    INT_IN1ESÚ "õ!    INT_IN2ERÚ "õ!


INT_OUT1EðÚ "õ!


INT_OUT2EïÚ "õ!    INT_USBE1Ú "õ!FRAME1Ú "õ!FRAME2Ú "õ!INDEX8Ú "õ!REVÇÚ "õ!MAX_PKT_IN|Ú "õ!CSR0_INCSR1}Ú "õ!IN_CSR2œÚ "õ!MAX_PKT_OUTÚ "õ!    OUT_CSR1:Ú "õ!    OUT_CSR29Ú "õ!OUT_COUNT1•Ú "õ!OUT_COUNT2”Ú <"õ!REV0XÚ "õ!    FIFO_EP0bÚ <"õ!REV1\Ú "õ!    FIFO_EP1aÚ <"õ!REV2[Ú "õ!    FIFO_EP2`Ú <"õ!REV3ZÚ "õ!    FIFO_EP3_ÚUSB_TZÚ8


<unnamed>QÚ 


"—"    DMA_INTR’Ú 


"—"CNTL1¤Ú 


"—"ADDR1ºÚ 


"—"COUNT1JÚ    USBDMA_T‚ÚPUSB_DMA_REQUEST_PosqÚPUSB_DMA_REQUEST_MskxÚPUSB_DMA_DIRECTION_PosõÚPUSB_DMA_DIRECTION_MsküÚPUSB_DMA_MODE_SEL_Pos0ÚPUSB_DMA_MODE_SEL_Msk7ÚPUSB_DMA_EP_NUM_Pos¸ÚPUSB_DMA_EP_NUM_Msk¿Ú8


<unnamed>QÚ 


"¥"revs0Ú 


"¥"FSM5ßÚ 


"¥"FSM6ÞÚ 


"¥"FSM13®Ú 


"¥"FSM14­Ú 


"¥"FSM15¬Ú 


"¥"FSM16«Ú 


"¥"FSM17ªÚ 


"¥"FSM18©Ú 


"¥"FSM19¨Ú 


"¥"PHY1ØÚ 


"¥"PHY2×Ú 


"¥"PHY3ÖÚ 


"¥"PHY4ÕÚ 


"¥"PHY5ÔÚ <"¥"revs1ÑÚ 


"¥"INTR1ŠÚ 


"¥"INTCLR*Ú 


"¥"INTMSK Ú 


"¥"INTR4‡Ú 


"¥"revs2Ú 


"¥"ACTTMR1øÚ 


"¥"ACTTMR2÷Ú 


"¥"ACTTMR6óÚ 


"¥"ACTTMR7òÚ 


"¥"revs3Ú 


"¥"SECURE1üÚ 


"¥"SECURE2ûÚ 


"¥"SECURE3úÚ 


"¥"SECURE4ùÚ 


"¥"SECURE5øÚ 


"¥"SECURE6÷Ú 


"¥"SECURE7öÚ 


"¥"SECURE8õÚ 


"¥"SECURE9ôÚ 


"¥"    SECURE10ÊÚ 


"¥"revs4Ú 


"¥"TEST_MUX00õÚ 


"¥"RNG1âÚ 


"¥"RNG2áÚ 


"¥"revs5Ú 


"¥"LL_MAC_CTRLÚ 


"¥"TEST_MUX01ôÚ 


"¥"TEST_MUX02óÚ 


"¥"TEST_MUX03òÚ <"¥"revs6ÌÚ 


"¥"R00_CTLÚ 


"¥"R01_INT÷Ú 


"¥"R02_TMR_CTL¤Ú 


"¥"R03_RX_ADDR_LÚ 


"¥"R04_RX_CTLíÚ 


"¥"R05_TX_ADDR_LÚ 


"¥"R06_TX_CTLéÚ 


"¥" R07_SRAM_CTL]Ú 


"¥"R08_RX_ADDR1_LÍÚ 


"¥"R09_RX_ADDR2_LËÚ 


"¥"R0A_RX_ADDR3_LÂÚ 


"¥"R0B_RX_ADDR4_LÀÚ 


"¥"R0C_RX_ADDR5_L¾Ú 


"¥"R0D_RX_ADDR6_L¼Ú 


"¥"R0E_RX_ADDR7_LºÚ 


"¥"R0F_RX_ADDR_HöÚ 


"¥"R10_RX_ADDR_EN¾Ú 


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CLEAR_BITÚP    READ_BITaÚP


CLEAR_REGÚP


WRITE_REGñÚP    READ_REGbÚPMODIFY_REG²ÚPUSE_FULL_ASSERTûÚP assert_param±ÚP    FREQ_RCLMÚP    FREQ_XTL6ÚNVIC_SystemReset½ÚP__PAN_SYS_LOG_H__ÚPDBG_ONöÚPINFO_ON•ÚPWARN_ON‰ÚPERR_ONÚÚPTEST_ONÚP


ASSERT_ONëÚP


SYS_ABORTãÚPLOGãÚPSYS_DBG’ÚP    SYS_INFO1ÚP    SYS_WARN%ÚP    SYS_TESTÚPSYS_ERRvÚPSYS_ASSERT‡Ú ,file)Ú ,


line/ÚSYS_AssertErrorðÚP__PAN_SYS_H__QÚPSYS_MFP_TYPE_Msk?ÚPSYS_MFP_ALT_Msk¢ÚPSYS_MFP_MFP_Msk ÚP SYS_MFP_GPIOäÚPSYS_MFP_P00_GPIOÍÚPSYS_MFP_P00_SWD_CLKÏÚPSYS_MFP_P00_UART1_RX~ÚPSYS_MFP_P00_I2C0_SCLÅÚPSYS_MFP_P00_SPI0_CLKŸÚPSYS_MFP_P00_LL_DBG_14jÚPSYS_MFP_P00_MDM_DBG_11%ÚPSYS_MFP_P00_RESERVED”ÚPSYS_MFP_P00_MskÓÚPSYS_MFP_P01_GPIOÌÚPSYS_MFP_P01_SWD_DATÏÚPSYS_MFP_P01_UART1_TX{ÚPSYS_MFP_P01_I2C0_SDAÎÚPSYS_MFP_P01_SPI0_CSäÚPSYS_MFP_P01_LL_DBG_15hÚPSYS_MFP_P01_MDM_DBG_12#ÚPSYS_MFP_P01_RESERVED“ÚPSYS_MFP_P01_MskÒÚPSYS_MFP_P02_GPIOËÚPSYS_MFP_P02_UART0_CTS;ÚPSYS_MFP_P02_SPI1_MISO<ÚPSYS_MFP_P02_PWM_CH3ãÚPSYS_MFP_P02_UART1_CTS:ÚPSYS_MFP_P02_LL_DBG_8—ÚPSYS_MFP_P02_MDM_DBG_19ÚPSYS_MFP_P02_RESERVED’ÚPSYS_MFP_P02_MskÑÚPSYS_MFP_P03_GPIOÊÚPSYS_MFP_P03_UART0_CTS:ÚPSYS_MFP_P03_SPI0_CSâÚPSYS_MFP_P03_PWM_CH2ãÚ#PSYS_MFP_P03_TIMER0_CNT_OUT™ÚPSYS_MFP_P03_LL_DBG_8–ÚPSYS_MFP_P03_MDM_DBG_5QÚPSYS_MFP_P03_RESERVED‘ÚPSYS_MFP_P03_MskÐÚPSYS_MFP_P04_GPIOÉÚPSYS_MFP_P04_UART0_RTS*ÚPSYS_MFP_P04_SPI0_CLK›ÚPSYS_MFP_P04_PWM_CH3áÚPSYS_MFP_P04_TIMER0_EXTëÚPSYS_MFP_P04_LL_DBG_9”ÚPSYS_MFP_P04_MDM_DBG_6OÚPSYS_MFP_P04_RESERVEDÚPSYS_MFP_P04_MskÏÚPSYS_MFP_P05_GPIOÈÚPSYS_MFP_P05_UART0_TXxÚPSYS_MFP_P05_SPI0_MISO:ÚPSYS_MFP_P05_PWM_CH4ßÚPSYS_MFP_P05_EXT_STADC.ÚPSYS_MFP_P05_LL_DBG_12gÚPSYS_MFP_P05_MDM_DBG_9KÚPSYS_MFP_P05_RESERVEDÚPSYS_MFP_P05_MskÎÚPSYS_MFP_P06_GPIOÇÚPSYS_MFP_P06_UART0_RXyÚPSYS_MFP_P06_SPI0_MISO9ÚPSYS_MFP_P06_PWM_CH5ÝÚPSYS_MFP_P06_TIMER1_EXTèÚPSYS_MFP_P06_LL_DBG_13eÚPSYS_MFP_P06_MDM_DBG_3PÚPSYS_MFP_P06_AHB_CLKìÚPSYS_MFP_P06_MskÍÚPSYS_MFP_P07_GPIOÆÚPSYS_MFP_P07_UART1_RXwÚPSYS_MFP_P07_I2C0_SCL¾ÚPSYS_MFP_P07_SPI0_MOSI8ÚPSYS_MFP_P07_PWM_CH0áÚPSYS_MFP_P07_LL_DBG_10gÚPSYS_MFP_P07_MDM_DBG_7KÚPSYS_MFP_P07_RESERVEDÚPSYS_MFP_P07_MskÌÚPSYS_MFP_P10_GPIOÌÚPSYS_MFP_P10_UART1_TX{ÚPSYS_MFP_P10_I2C0_SDAÎÚPSYS_MFP_P10_SPI0_MISO>ÚPSYS_MFP_P10_PWM_CH5âÚPSYS_MFP_P10_LL_DBG_11lÚPSYS_MFP_P10_MDM_DBG_8PÚPSYS_MFP_P10_RESERVED“ÚPSYS_MFP_P10_MskÒÚPSYS_MFP_P11_GPIOËÚPSYS_MFP_P11_UART1_RTS+ÚPSYS_MFP_P11_SPI0_MOSI=ÚPSYS_MFP_P11_PWM_CH7ßÚPSYS_MFP_P11_CLK_32KÚPSYS_MFP_P11_LL_DBG_9–ÚPSYS_MFP_P11_MDM_DBG_0WÚPSYS_MFP_P11_UART0_TX{ÚPSYS_MFP_P11_MskÑÚPSYS_MFP_P12_GPIOÊÚPSYS_MFP_P12_UART0_RX|ÚPSYS_MFP_P12_PWM_CH4áÚ#PSYS_MFP_P12_TIMER0_CNT_OUT™ÚPSYS_MFP_P12_UART1_TXyÚPSYS_MFP_P12_LL_DBG_4šÚPSYS_MFP_P12_MDM_DBG_17ÚPSYS_MFP_P12_SPI0_MISO<ÚPSYS_MFP_P12_MskÐÚPSYS_MFP_P13_GPIOÉÚPSYS_MFP_P13_UART0_RTS*ÚPSYS_MFP_P13_I2C0_SDAËÚPSYS_MFP_P13_PWM_CH3áÚPSYS_MFP_P13_LL_DBG_3šÚPSYS_MFP_P13_MDM_DBG_16ÚPSYS_MFP_P13_SPI1_CSàÚPSYS_MFP_P13_SPI0_CSáÚPSYS_MFP_P13_MskÏÚPSYS_MFP_P14_GPIOÈÚPSYS_MFP_P14_UART0_CTS8ÚPSYS_MFP_P14_I2C0_SCLÀÚPSYS_MFP_P14_PWM_CH2áÚPSYS_MFP_P14_LL_DEBUG_2üÚPSYS_MFP_P14_MDM_DBG_15ÚPSYS_MFP_P14_SPI0_CLKšÚPSYS_MFP_P14_RESERVEDÚPSYS_MFP_P14_MskÎÚPSYS_MFP_P15_GPIOÇÚPSYS_MFP_P15_SPI0_CSßÚPSYS_MFP_P15_PWM_CH5ÝÚPSYS_MFP_P15_TIMER0_EXTéÚPSYS_MFP_P15_UART0_RXyÚPSYS_MFP_P15_LL_DBG_5–ÚPSYS_MFP_P15_MDM_DBG_18ÚPSYS_MFP_P15_RESERVEDŽÚPSYS_MFP_P15_MskÍÚPSYS_MFP_P16_GPIOÆÚPSYS_MFP_P16_UART0_TXvÚ#PSYS_MFP_P16_TIMER2_CNT_OUT“ÚPSYS_MFP_P16_PWM_CH0áÚPSYS_MFP_P16_LL_DBG_0šÚPSYS_MFP_P16_MDM_DBG_13ÚPSYS_MFP_P16_SPI1_CLK—ÚPSYS_MFP_P16_I2C0_SCL¾ÚPSYS_MFP_P16_MskÌÚPSYS_MFP_P17_GPIOÅÚPSYS_MFP_P17_UART0_RXwÚPSYS_MFP_P17_TIMER2_EXTåÚPSYS_MFP_P17_PWM_CH1ßÚPSYS_MFP_P17_LL_DBG_1˜ÚPSYS_MFP_P17_MDM_DBG_14ÚPSYS_MFP_P17_RCHÚPSYS_MFP_P17_RESERVEDŒÚPSYS_MFP_P17_MskËÚPSYS_MFP_P20_GPIOËÚPSYS_MFP_P20_SPI1_MISO<ÚPSYS_MFP_P20_PWM_CH6àÚPSYS_MFP_P20_TADC_CLKÚPSYS_MFP_P20_LL_DBG_6™ÚPSYS_MFP_P20_MDM_DBG_2UÚPSYS_MFP_P20_XTL_C1_CLKêÚPSYS_MFP_P20_RESERVED’ÚPSYS_MFP_P20_MskÑÚPSYS_MFP_P21_GPIOÊÚPSYS_MFP_P21_SPI1_MOSI;ÚPSYS_MFP_P21_PWM_CH7ÞÚPSYS_MFP_P21_TADC_VLDÚPSYS_MFP_P21_LL_DBG_7—ÚPSYS_MFP_P21_MDM_DBG_1UÚPSYS_MFP_P21_XTL_C2_CLKèÚPSYS_MFP_P21_RESERVED‘ÚPSYS_MFP_P21_MskÐÚPSYS_MFP_P22_GPIOÉÚPSYS_MFP_P22_SPI1_CLKšÚPSYS_MFP_P22_PWM_CH0äÚPSYS_MFP_P22_RESERVEDÚPSYS_MFP_P22_TADC_DATl.ÚPSYS_MFP_P22_MDM_DBG_0UÚPSYS_MFP_P22_SPI0_MOSI;ÚPSYS_MFP_P22_RESERVED1]ÚPSYS_MFP_P22_MskÏÚPSYS_MFP_P23_GPIOÈÚPSYS_MFP_P23_SPI1_CSßÚPSYS_MFP_P23_PWM_CH1âÚPSYS_MFP_P23_DPLL_DIV8GÚPSYS_MFP_P23_TADC_DATHQÚPSYS_MFP_P23_MDM_DBG_10!ÚPSYS_MFP_P23_I2C0_SCLÀÚPSYS_MFP_P23_RESERVEDÚPSYS_MFP_P23_MskÎÚPSYS_MFP_P24_GPIOÇÚPSYS_MFP_P24_SPI1_MISO8ÚPSYS_MFP_P24_UART1_RXxÚPSYS_MFP_P24_PWM_CH2àÚ#PSYS_MFP_P24_TIMER1_CNT_OUT•ÚPSYS_MFP_P24_MDM_DBG_4OÚPSYS_MFP_P24_RESERVEDŽÚPSYS_MFP_P24_RESERVED1[ÚPSYS_MFP_P24_MskÍÚPSYS_MFP_P25_GPIOÆÚPSYS_MFP_P25_SPI1_MOSI7ÚPSYS_MFP_P25_UART1_TXuÚPSYS_MFP_P25_PWM_CH3ÞÚPSYS_MFP_P25_MDM_DBG_5MÚPSYS_MFP_P25_RESERVEDÚPSYS_MFP_P25_I2C0_SDAÈÚPSYS_MFP_P25_RESERVED1ZÚPSYS_MFP_P25_MskÌÚPSYS_MFP_P26_GPIOÅÚPSYS_MFP_P26_UART1_RTS%ÚPSYS_MFP_P26_PWM_CH4ÜÚPSYS_MFP_P26_SPI1_CSÜÚPSYS_MFP_P26_MDM_DBG_4MÚPSYS_MFP_P26_MDM_DBG_10ÚPSYS_MFP_P26_RESERVEDŒÚPSYS_MFP_P26_RESERVED1YÚPSYS_MFP_P26_MskËÚPSYS_MFP_P27_GPIOÄÚPSYS_MFP_P27_UART1_CTS3ÚPSYS_MFP_P27_PWM_CH5ÚÚPSYS_MFP_P27_SPI1_CLK•ÚPSYS_MFP_P27_RESERVED‹ÚPSYS_MFP_P27_MDM_DBG_20ÚPSYS_MFP_P27_XTHÚPSYS_MFP_P27_RESERVED1XÚPSYS_MFP_P27_MskÊÚPSYS_MFP_P30_GPIOÊÚPSYS_MFP_P30_UART1_RX{ÚPSYS_MFP_P30_PWM_CH6ßÚPSYS_MFP_P30_SPI1_MISO;ÚPSYS_MFP_P30_MDM_DBG_10#ÚPSYS_MFP_P30_RESERVED‘ÚPSYS_MFP_P30_RESERVED1^ÚPSYS_MFP_P30_RESERVED2]ÚPSYS_MFP_P30_MskÐÚPSYS_MFP_P31_GPIOÉÚPSYS_MFP_P31_UART1_TXxÚPSYS_MFP_P31_PWM_CH7ÝÚPSYS_MFP_P31_SPI1_MOSI:ÚPSYS_MFP_P31_RESERVEDÚPSYS_MFP_P31_RESERVED1]ÚPSYS_MFP_P31_RESERVED2\ÚPSYS_MFP_P31_RESERVED3[ÚPSYS_MFP_P31_MskÏÚPSYS_SET_MFP)ÚSYS_UnlockRegòÚSYS_LockRegÙÚSYS_IsRegLocked@Ú,


 


u32NopCnt¡ÚSYS_delay_10nopPÚP__PAN_CLK_H__vÚ$PCLK_APB1_WDTSEL_MILLI_PULSEhÚPCLK_APB1_WDTSEL_RCL32K@Ú%PCLK_APB1_WWDTSEL_MILLI_PULSEÚ PCLK_APB1_WWDTSEL_RCL32KçÚ!PCLK_APB1_TMR0SEL_APB1CLK»Ú PCLK_APB1_TMR0SEL_RCL32K


ÚPCLK_APB1_TMR0SEL_TM0ÐÚ!PCLK_APB2_TMR1SEL_APB2CLK¸Ú PCLK_APB2_TMR1SEL_RCL32KÚPCLK_APB2_TMR1SEL_TM1ÍÚ!PCLK_APB2_TMR2SEL_APB2CLK·Ú PCLK_APB2_TMR2SEL_RCL32KÚPCLK_APB2_TMR2SEL_TM2ËÚ"PCLK_APB1_PWM_CH01_SEL_APBIÚ%PCLK_APB1_PWM_CH01_SEL_CLK32KŒÚ"PCLK_APB1_PWM_CH23_SEL_APBEÚ%PCLK_APB1_PWM_CH23_SEL_CLK32KˆÚ"PCLK_APB1_PWM_CH45_SEL_APBAÚ%PCLK_APB1_PWM_CH45_SEL_CLK32K„Ú"PCLK_APB1_PWM_CH67_SEL_APB=Ú%PCLK_APB1_PWM_CH67_SEL_CLK32K€ÚP


FREQ_1MHZÚP


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EFUSE_RSTéÚPUSB_RST{ÚPMDMSTB_RST˜ÚPMDM_RST‡ÚP    I2C0_RSTuÚP    SPI0_RSTGÚP    SPI1_RSTFÚP


UART0_RSTõÚP


UART1_RSTôÚP    PWM0_RST?ÚPADC_RSTÚPWDT_RSTvÚP    WWDT_RSTÚP    TMR0_RST@ÚP    TMR1_RST?ÚP    TMR2_RST>ÚP    GPIO_RST4ÚPCLKTRIM_RSTGÚPCLK_BODCTL_BOD_INT_EN@ÚPCLK_BODCTL_BOD_RST_EN2Ú PCLK_BODCTL_BODSEL_1_75VãÚ PCLK_BODCTL_BODSEL_1_95VáÚ PCLK_BODCTL_BODSEL_2_15VèÚ PCLK_BODCTL_BODSEL_2_35VæÚ PCLK_BODCTL_BODSEL_2_55VäÚ PCLK_BODCTL_BODSEL_2_75VâÚ PCLK_BODCTL_BODSEL_2_95VàÚ#PCLK_BLDBCTL_BODDBSEL_2POW0Ú#PCLK_BLDBCTL_BODDBSEL_2POW1Ú#PCLK_BLDBCTL_BODDBSEL_2POW2Ú#PCLK_BLDBCTL_BODDBSEL_2POW3Ú#PCLK_BLDBCTL_BODDBSEL_2POW4Ú#PCLK_BLDBCTL_BODDBSEL_2POW5 Ú#PCLK_BLDBCTL_LVRDBSEL_2POW0óÚ#PCLK_BLDBCTL_LVRDBSEL_2POW1òÚ#PCLK_BLDBCTL_LVRDBSEL_2POW2ñÚ#PCLK_BLDBCTL_LVRDBSEL_2POW3ðÚ#PCLK_BLDBCTL_LVRDBSEL_2POW4ïÚ#PCLK_BLDBCTL_LVRDBSEL_2POW5îÚCLK_XthStartupConfigÚCLK_HCLKConfig'Ú,


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u32ClkDivåÚCLK_PCLK1ConfigìÚ,


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u32ClkDivãÚCLK_PCLK2ConfigëÚ,


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"‘*regâÚCLK_FLASH_CLKDIV_1†ÚCLK_FLASH_CLKDIV_2…ÚCLK_FLASH_CLKDIV_4ƒÚCLK_FLASH_CLKDIV_8ÚCLK_FLASH_CLKDIV_16NÚCLK_FLASH_CLKDIV_32PÚCLK_SetFlashClkDiv@Ú,"š*div·Ú


"š*regÙÚCLK_GetHCLKFreqÁÚCLK_GetCPUFreqýÚCLK_GetPCLK1Freq†ÚCLK_GetPCLK2Freq…Ú,


 


u32ClkSrc±ÚCLK_RefClkSrcConfigÔÚ,


 


u32ClkSrc±Ú,


    freq_outjÚCLK_SYSCLKConfig`Ú,


 


u32ClkDiv¶Ú,


 


u32ClkDiv¶Ú,


 


u32ClkDiv¶Ú,


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CLK_APB1PeriphÚ,"    NewStateÚCLK_APB1PeriphClockCmdÚ,


CLK_APB2PeriphÚ,"    NewStateÚCLK_APB2PeriphClockCmdÚ,


u32ClkMaskKÚCLK_WaitClockReadyÚCLK_Wait3vSyncReady¹ÚCLK_Set3vSyncAuto‚Ú,


 


u32clkseluÚCLK_SetWdtClkSrcòÚ,


 


u32clkseluÚCLK_SetWwdtClkSrcyÚ,timer¦Ú,


 


u32clkseluÚCLK_SetTmrClkSrcîÚ,


    u32ChNumÚ,


 


u32clkseluÚCLK_SetPwmClkSrcíÚ,Peripheral±ÚCLK_GetPeripheralFreqËÚCLK_ResetChipÚ!CLK_ResetSystemToRomModeÚ,


u32ModuleIndex‹ÚCLK_ResetModule(Ú,i32Mode€Ú,


u32BODLevel"ÚCLK_ConfigureBODÚCLK_EnableBODyÚCLK_DisableBOD


ÚCLK_GetBODStatusÚCLK_GetBODIntFlagóÚCLK_ClearBODIntFlag(Ú,


 u32BodDBTimeÃÚCLK_SetBODDebounceTimeÎÚCLK_EnableLVRZÚCLK_DisableLVRëÚ,


 u32LvrDBTime¤ÚCLK_SetLVRDebounceTime¯ÚP__PAN_ADC_H__ˆÚPADC_INPUTRANGE_HIGHÚPADC_INPUTRANGE_LOW2ÚPADC_CH8_EXT{ÚPADC_CH8_BGP“ÚPADC_CMP0_LESS_THANPÚPADC_CMP1_LESS_THANOÚ%PADC_CMP0_GREATER_OR_EQUAL_TOÚ%PADC_CMP1_GREATER_OR_EQUAL_TOÚPADC_TRIGGER_BY_EXT_PINÔÚPADC_TRIGGER_BY_PWMÚ!PADC_FALLING_EDGE_TRIGGERÚ PADC_RISING_EDGE_TRIGGERÃÚP ADC_ADIF_INT.ÚP ADC_CMP0_INT2ÚP ADC_CMP1_INT1ÚPADC_FIFO_FULL_INT‚ÚPADC_FIFO_EMPTY_INT$ÚPADC_FIFO_OVER_INTyÚPADC_FIFO_HALF_INTšÚPADC_SAMPLE_CLOCK_0dÚPADC_SAMPLE_CLOCK_1cÚPADC_SAMPLE_CLOCK_2bÚPADC_SAMPLE_CLOCK_4`ÚPADC_SAMPLE_CLOCK_8\ÚPADC_SAMPLE_CLOCK_16+ÚPADC_SAMPLE_CLOCK_32-ÚPADC_SAMPLE_CLOCK_64(ÚPADC_SAMPLE_CLOCK_128õÚPADC_SAMPLE_CLOCK_256óÚPADC_SAMPLE_CLOCK_512øÚPADC_SAMPLE_CLOCK_1024ÇÚ!PADC_SEQMODE_TYPE_23SHUNToÚ PADC_SEQMODE_TYPE_1SHUNT¥Ú$PADC_SEQMODE_MODESELECT_CH01ÑÚ$PADC_SEQMODE_MODESELECT_CH12ÏÚ$PADC_SEQMODE_MODESELECT_CH02ÐÚ#PADC_SEQMODE_MODESELECT_ONEÝÚ PADC_SEQMODE_PWM0_RISINGºÚ PADC_SEQMODE_PWM0_CENTERÅÚ!PADC_SEQMODE_PWM0_FALLING‡Ú PADC_SEQMODE_PWM0_PERIODÃÚ PADC_SEQMODE_PWM2_RISING¸Ú PADC_SEQMODE_PWM2_CENTERÃÚ!PADC_SEQMODE_PWM2_FALLING…Ú PADC_SEQMODE_PWM2_PERIODÁÚ PADC_SEQMODE_PWM4_RISING¶Ú PADC_SEQMODE_PWM4_CENTERÁÚ!PADC_SEQMODE_PWM4_FALLINGƒÚ PADC_SEQMODE_PWM4_PERIOD¿Ú PADC_SEQMODE_PWM6_RISING´Ú PADC_SEQMODE_PWM6_CENTER¿Ú!PADC_SEQMODE_PWM6_FALLINGÚ PADC_SEQMODE_PWM6_PERIOD½ÚPADC_COMPARATOR_0ýÚPADC_COMPARATOR_1üÚ!PADC_FIFO_TRIG_LEVEL_HALFjÚ!PADC_FIFO_TRIG_LEVEL_FULLRÚ8


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chip_infoVÚ "Ž+ft_versionÄÚ "Ž+


adc_vdd_bÚ "Ž+


adc_vdd_kmÚ "Ž+


adc_vbg_klÚ "Ž+


adc_vbg_bwÚ "Ž+adc_temp_volt“Ú "Ž+current_temp_valueXÚ "Ž+adc_vbg_1v20_trim¬Ú "Ž+


rsvd_0x30ÜÚ <"Ž+adc_vbg_kbÀÚ "Ž+adc_vbat_küÚ "Ž+adc_vbat_bÚ "Ž+adc_vbat_dtemp_kyÚ "Ž+adc_vbat_dtemp_b‚Ú "Ž+adc_temp_këÚ 


"Ž+


adc_ctrl2Ú 


"Ž+adc_extsmpt^Ú


ADC_OPT_T"Ú@


m_adc_optõÚ


global_calc_vbat_mv$Ú,optxÚ ADC_SetCalirationParamsýÚADC_GetConversionDataãÚ,"¦+ADCx–ÚADC_StatusFlag³Ú,"¨+ADCx”Ú,


"¨+IntMask%ÚADC_ClearStatusFlagÂÚ,"«+ADCx‘Ú,


"«+IntMask"ÚADC_IntMaskÚ,"®+ADCxŽÚ,


"®+IntMaskÚ,""®+    NewState”ÚADC_IsIntOccuredÚ,"²+ADCxŠÚ,


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"µ+IntMaskÚADC_IsBusyZÚ,"¸+ADCx„ÚADC_IsDataOverrun„Ú,"º+ADCx‚ÚADC_IsDataValid‰Ú,"¼+ADCx€ÚADC_PowerDownÚ,"¾+ADCx~ÚADC_PowerOníÚ,"À+ADCx|Ú"ADC_SequentialModeDisableGÚ,"Â+ADCxzÚADC_Trigger2SelectCÚ,"Ä+ADCxxÚ,""Ä+    NewState~ÚADC_DisableCompare0üÚ,"Ç+ADCxuÚADC_DisableCompare1ûÚ,"É+ADCxsÚADC_StartConvert¾Ú,"Ë+ADCxqÚADC_StopConvert(Ú,"Í+ADCxoÚADC_TestModeEnable=Ú,"Ï+ADCxmÚADC_TestModeDisableÎÚ,"Ñ+ADCxkÚADC_DmaModeEnableÍÚ,"Ó+ADCxiÚ,""Ó+    NewStateoÚADC_SetClockDividerÈÚ,"Ö+ADCxfÚ,


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"ß+Data1ÚADC_SetExtraSampleTime€Ú,"â+ADCxZÚ,


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Ú ,ADCx‰Ú&ADC_MeasureSocTemperatureFasttÚ ,ADCx‰ÚADC_MeasureSocVbatÚ ,ADCx‰ÚADC_Disable÷Ú


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MaskKÚADC_DisableIntÆÚ ,ADCx‰Ú,


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ModeSel(ÚADC_SeqModeEnableªÚ ,ADCx‰Ú,


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 CmpConditionÚ,


CmpData7Ú,


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CmpSelectMÚADC_CompareEnable‘Ú ,ADCx‰Ú ,


TrigAÚ,LeveläÚ,DmaEnÚ,HwClrENeÚADC_SeqOneChModeConfigÄÚP__PAN_FMC_H__zÚPM32ÚPCMD_ERASE_PAGEÚPCMD_ERASE_SECTORÙÚPCMD_ERASE_32KÿÚPCMD_ERASE_64KúÚPCMD_ERASE_CHIP‰ÚPCMD_READ_STATUS_LlÚPCMD_READ_STATUS_HpÚPCMD_WRITE_STATUSªÚPOPS_WR_STU_REG_NORÇÚPOPS_WR_STU_REG_ALLÝÚPCMD_FAST_READÕÚPCMD_NORM_READÇÚP


CMD_DREAD&ÚP


CMD_2READ8ÚP


CMD_QREADÚP


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PAGE_SIZEÚPSECTOR_SIZEKÚ8_flash_ids¥Ú "Õ,manufacturer_idxÚ8


<unnamed>SÚ <"×,d0Ú8


<unnamed>QÚ "Ù,memory_type_idÉÚ "Ù,memory_density_id…Ú <"Õ,uidBÚFLASH_IDS_T‹Ú


flash_idsÚ#FMC_EnterDeepPowerDownModeåÚ,"ß,fmchÚ"FMC_ExitDeepPowerDownModeKÚ,"á,fmcfÚ,fmc•ÚFMC_GetFlashUniqueIdYÚ,fmc•ÚFMC_GetFlashJedecId÷Ú,fmc•ÚFMC_SetFlashCapacityCÚ,fmc•Ú!FMC_GetFlashCodeAreaSizeæÚ,fmc•Ú,adršÚFMC_EraseSector5Ú,fmc•Ú ,addr4ÚFMC_EraseBlock32kæÚ,fmc•Ú ,addr4ÚFMC_EraseBlock64káÚ,fmc•ÚFMC_EraseChip%Ú,fmc•Ú ,


addr<Ú,


lenšÚFMC_EraseCodeArea­Ú,fmc•Ú ,


mode2ÚInitIcacheÚ,fmc•Ú ,


addr<Ú,


count¬Ú,chksum:ÚFMC_GetCrc32SumÃÚ,fmc•Ú,adršÚ,szæÚBlankCheckÚ,fmc•Ú,adršÚ,szæÚ,bufŽÚVerifygÚ,fmc•Ú,adršÚ,szæÚ,bufŽÚProgramPage}Ú,fmc•Ú,cmd¬ÚFMC_ReadStatusRegsÚ,fmc•ÚFMC_WriteEnableCÚ,fmc•ÚFMC_WriteDisableÔÚ,fmc•Ú,opsŽÚ,


bufœÚFMC_WriteStatusRegâÚ,fmc•Ú ,


Addr\Ú,cmd¬Ú FMC_ReadByte‹Ú,fmc•Ú ,


addr<Ú ,dataDÚFMC_WriteByteúÚ,fmc•Ú ,


addr<Ú ,data;ÚFMC_WriteHalfWordoÚ,fmc•Ú ,


Addr\Ú,cmd¬Ú FMC_ReadWordƒÚ,fmc•Ú ,


Addr\Ú,cmd¬Ú FMC_ReadPage¢Ú,fmc•Ú ,


Addr\Ú,cmd¬Ú,bufŽÚ,


lenšÚFMC_ReadStream¯Ú,fmc•Ú ,


Addr\Ú,bufŽÚ,


lenšÚFMC_WriteStreamÚ,fmc•Ú ,


Addr\Ú,cmd¬Ú,bufŽÚ,


lenšÚFMC_ReadInfoAreaÚ,fmc•Ú ,


Addr\Ú,bufŽÚ,


lenšÚFMC_WriteInfoAreaÚ,fmc•ÚFMC_EraseInfoAreaœÚ,fmc•Ú ,


mode2Ú,enhanceÚFMC_SetFlashModeôÚ,fmc•ÚFMC_ExitEnhanceMode¼Ú,fmc•Ú ,


mode2ÚFMC_EnterEnhanceModeVÚ,fmc•ÚFMC_EnableAutoDpÿÚ,fmc•ÚFMC_DisableAutoDpÚ,fmc•Ú,


cnt”ÚFMC_SetRdpWaitCountÚ,fmc•Ú,


cnt”ÚFMC_SetDpWaitCountÚ,fmc•Ú ,"IRQnhÚ,"    NewStateÚFMC_SetSuspendIrqWÚ,fmc•Ú,


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Ú"PDMAC_AddrChange_Increment`Ú"PDMAC_AddrChange_DecrementnÚ!PDMAC_AddrChange_NoChangeÚPDMAC_DataWidth_8&ÚPDMAC_DataWidth_16õÚPDMAC_DataWidth_32÷ÚPDMAC_DataWidth_64òÚPDMAC_DataWidth_128¿ÚPDMAC_DataWidth_256½Ú PDMAC_Peripheral_I2C0_Tx¥Ú PDMAC_Peripheral_I2C0_Rx§Ú PDMAC_Peripheral_SPI0_TxwÚ PDMAC_Peripheral_SPI0_RxyÚ!PDMAC_Peripheral_UART0_Tx%Ú!PDMAC_Peripheral_UART0_Rx'Ú PDMAC_Peripheral_SPI1_TxvÚ PDMAC_Peripheral_SPI1_RxxÚ!PDMAC_Peripheral_UART1_Tx$Ú!PDMAC_Peripheral_UART1_Rx&ÚPDMAC_Peripheral_ADCþÚPDMAC_Peripheral_USB_Rx­ÚPDMAC_Peripheral_USB_Tx«Ú#PDMAC_HandshakePolarity_Low·Ú$PDMAC_HandshakePolarity_HighgÚPDMAC_Handshake_Default€Ú PDMAC_Handshake_SoftwareøÚ PDMAC_Handshake_HardwareÚ$PDMAC_LockLevel_Tfr_Complete}Ú&PDMAC_LockLevel_Block_CompleteºÚ,P$DMAC_LockLevel_Transaction_CompleteÚPDMAC_ChannelPriority_0ÚPDMAC_ChannelPriority_1€ÚPDMAC_ChannelPriority_2ÚPDMAC_ChannelPriority_3~ÚPDMAC_ChannelPriority_4}ÚPDMAC_ChannelPriority_5|ÚPDMAC_ChannelPriority_6{ÚPDMAC_ChannelPriority_7zÚPDMAC_CHANNELALL_MASKÒÚPDMAC_FLAG_INDEX_TFRõÚPDMAC_FLAG_INDEX_BLKÚPDMAC_FLAG_INDEX_SRCTFRÚPDMAC_FLAG_INDEX_DSTTFRÚPDMAC_FLAG_INDEX_ERRøÚPDMAC_FLAG_MASK_TFRCÚPDMAC_FLAG_MASK_BLKVÚPDMAC_FLAG_MASK_SRCTFRUÚPDMAC_FLAG_MASK_DSTTFRRÚPDMAC_FLAG_MASK_ERRFÚPDMAC_FLAG_MASK_ALLVÚ$8__DMAC_ChannelConfigTypeDefÚ 


"¤.CTL_L_Ú 


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"¤.CFG_HvÚ$__DMAC_ChannelConfigTypeDefÙÚ"8DMAC_ChannelConfigTypeDef_Ú 


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IntEnablemÚ 


"ª. DataWidthDst4Ú 


"ª. DataWidthSrc7Ú 


"ª.AddrChangeDstëÚ 


"ª.AddrChangeSrcîÚ 


"ª.BurstLenDstÚ 


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"ª.__Rev0ÊÚ 


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FifoEmptyLÚ 


"ª. HandshakeDst'Ú 


"ª. HandshakeSrc*Ú 


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"ª.HandshakePolaritySrcÆÚ 


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"ª.    FifoModeØÚ 


"ª.ProtectControlÚ 


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"ª.PeripheralDst Ú 


"ª.__Rev8ÂÚ"DMAC_ChannelConfigTypeDef›ÚDMAC_IsChannelValidõÚ,"Ò.dmawÚ,


"Ò.ChIdxãÚPDMAC_ChannelMaskòÚDMAC_CombinedIntStatus„Ú,"Ö.dmasÚ,


"Ö.FlgMskiÚDMAC_StatusFlagdÚ,"Ù.dmapÚ,


"Ù.ChIdxÜÚ,


"Ù.FlgIdxlÚ DMAC_IntFlagÃÚ,"Ý.dmalÚ,


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"á.FlgIdxdÚDMAC_ClrIntFlagœÚ,"å.dmadÚ,


"å.ChIdxÐÚ,


"å.FlgIdx`Ú,dma™Ú


DMAC_InitÎÚ,dma™ÚDMAC_DeInit!Ú,dma™Ú,


ChIdxÚ,


FlgIdx•ÚDMAC_ClrIntFlagMsk_Ú,dma™Ú,


ChIdxÚ,


FlgIdx•ÚDMAC_SetIntFlagMskTÚ,dma™Ú,


ChIdxÚ,ConfigoÚDMAC_SetChannelConfigÚ,dma™Ú,


ChIdxÚ,ConfigoÚDMAC_GetChannelConfigÚ,dma™Ú,


ChIdxÚ,Src£Ú,Dst Ú,


LenºÚDMAC_StartChannel‹Ú,dma™Ú,


ChIdxÚDMAC_StopChannelõÚ,dma™ÚDMAC_AcquireChannelËÚ,dma™Ú,


ChIdxÚDMAC_ReleaseChannelÔÚ,dma™Ú"DMAC_IsAllChannelReleasedÚP__PAN_GPIO_H__ÚP GPIO_PIN_MAXùÚ8"_GPIO_ModeDef$Ú"/GPIO_MODE_INPUT]Ú"/GPIO_MODE_OUTPUTúÚ"/GPIO_MODE_OPEN_DRAINäÚ"/GPIO_MODE_QUASIjÚ GPIO_ModeDefÇÚ8"_GPIO_IntAttrDefÝÚ"•/GPIO_INT_RISINGUÚ"•/GPIO_INT_FALLING"Ú"•/GPIO_INT_BOTH_EDGEzÚ"•/GPIO_INT_HIGHÚ"•/ GPIO_INT_LOW5ÚGPIO_IntAttrDef€Ú8"_GPIO_ClkSrcDefcÚ""œ/GPIO_DBCTL_DBCLKSRC_RCLÚ#"œ/GPIO_DBCTL_DBCLKSRC_HCLKÁÚGPIO_ClkSrcDefÚ8"_GPIO_ClkSelDefgÚ " /GPIO_DBCTL_DBCLKSEL_1¸Ú " /GPIO_DBCTL_DBCLKSEL_2·Ú " /GPIO_DBCTL_DBCLKSEL_4µÚ " /GPIO_DBCTL_DBCLKSEL_8±Ú!" /GPIO_DBCTL_DBCLKSEL_16€Ú!" /GPIO_DBCTL_DBCLKSEL_32‚Ú!" /GPIO_DBCTL_DBCLKSEL_64}Ú"" /GPIO_DBCTL_DBCLKSEL_128JÚ"" /GPIO_DBCTL_DBCLKSEL_256HÚ"" /GPIO_DBCTL_DBCLKSEL_512MÚ#" /GPIO_DBCTL_DBCLKSEL_1024Ú#" /GPIO_DBCTL_DBCLKSEL_2048Ú#" /GPIO_DBCTL_DBCLKSEL_4096Ú#" /GPIO_DBCTL_DBCLKSEL_8192Ú$" /GPIO_DBCTL_DBCLKSEL_16384ÛÚ$" /GPIO_DBCTL_DBCLKSEL_32768×ÚGPIO_ClkSelDef


ÚPGPIO_PIN_ADDRÂÚPP00ÚPP01ÚPP02ÚPP03ÚPP04ÚPP05ÚPP06ÚPP07ÚPP10ÚPP11ÚPP12ÚPP13ÚPP14ÚPP15ÚPP16ÚPP17 ÚPP20ÚPP21ÚPP22ÚPP23ÚPP24ÚPP25ÚPP26 ÚPP27ÚPP30ÚPP31ÚGPIO_ClrIntFlag‚Ú,"Í/gpioüÚ,


"Í/u32PinMask ÚGPIO_ClrAllIntFlagcÚ,"Ð/gpioùÚGPIO_DisableDebounceeÚ,"Ò/gpio÷Ú,


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"á/u32PinMaskÚ!GPIO_DisablePulldownPath Ú,"ä/gpioåÚ,


"ä/u32PinMask    Ú GPIO_EnablePulldownPathÚ,"ç/gpioâÚ,


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"í5u32ChannelNum¾ÚPWM_EnableZeroIntmÚ,"ð5pwm0Ú,


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"ó5u32ChannelNum¸ÚPWM_ClearZeroIntFlagMÚ,"ö5pwm*Ú,


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slh_first¸Ú "ÄKnameÚPOS_MEMPOOL_F_EXTœÚ8os_mempool_ext¿Úos_mempool_put_fnºÚ "ÛLmpe_mpîÚ "ÛLmpe_put_cbbÚ "ÛLmpe_put_argëÚ!POS_MEMPOOL_INFO_NAME_LEN8Ú8os_mempool_infobÚ "áLomi_block_size¹Ú "áLomi_num_blocks±Ú "áL omi_num_free‘Ú "áL omi_min_freeÚ <" áL    omi_nameùÚ!os_mempool_info_get_next¶ÚPOS_MEMPOOL_BLOCK_SZµÚos_membuf_t[ÚPOS_MEMPOOL_SIZEùÚPOS_MEMPOOL_BYTES«Ú,mpðÚ,blocksSÚ,


block_size¦Ú,membufIÚ ,name(Úos_mempool_init}Ú,mpe‰Ú,blocksSÚ,


block_size¦Ú,membufIÚ ,name(Úos_mempool_ext_initÅÚ,mpðÚos_mempool_unregisterÝÚ,mpðÚos_mempool_clear(Ú,mpðÚos_mempool_is_saneIÚ,mpðÚ,block_addr¸Úos_memblock_from*Ú,mpðÚos_memblock_get Ú,mpðÚ,block_addr¸Ú os_memblock_put_from_cb@Ú,mpðÚ,block_addr¸Úos_memblock_put‡ÚPH_BLE_æÚPBLE_ADV_INSTANCES•ÚPBLE_ENC_BLOCK_SIZE;ÚPBLE_ACL_MAX_PKT_SIZEtÚ8ble_encryption_blockVÚ <"MkeybÚ <"Mplain_texteÚ <"Mcipher_textüÚ8ble_mbuf_hdr_rxinfoÑÚ "‘MflagsÒÚ "‘MchannelÚ "‘MhandlezÚ "‘Mrssi+Ú "‘MphyÚ "‘M    phy_modeÚ'PBLE_MBUF_HDR_F_CONNECT_IND_TXD_Ú'PBLE_MBUF_HDR_F_CONNECT_REQ_TXDRÚ'PBLE_MBUF_HDR_F_CONNECT_RSP_RXDGÚ#PBLE_MBUF_HDR_F_CONN_CREDIT²ÚPBLE_MBUF_HDR_F_IGNOREDúÚ'PBLE_MBUF_HDR_F_CONN_CREDIT_INT`Ú$PBLE_MBUF_HDR_F_SCAN_REQ_TXD=Ú&PBLE_MBUF_HDR_F_INITA_RESOLVED¼Ú(P BLE_MBUF_HDR_F_TARGETA_RESOLVED%Ú#PBLE_MBUF_HDR_F_EXT_ADV_SEC•ÚPBLE_MBUF_HDR_F_EXT_ADV×Ú PBLE_MBUF_HDR_F_RESOLVEDœÚ$PBLE_MBUF_HDR_F_AUX_PTR_WAIT!Ú#PBLE_MBUF_HDR_F_AUX_INVALID¦ÚPBLE_MBUF_HDR_F_CRC_OK3Ú PBLE_MBUF_HDR_F_DEVMATCH´Ú#PBLE_MBUF_HDR_F_MIC_FAILUREºÚ$PBLE_MBUF_HDR_F_SCAN_RSP_TXD0Ú$PBLE_MBUF_HDR_F_SCAN_RSP_RXD2Ú$PBLE_MBUF_HDR_F_RXSTATE_MASKBÚ8ble_mbuf_hdr_txinfoÏÚ "¬MflagsÀÚ "¬M    hdr_bytevÚ "¬Moffset;Ú "¬M    pyld_lengÚ8 ble_mbuf_hdrÔÚ8


<unnamed>SÚ "²MrxinfoÚ "²MtxinfoÚ 


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rem_usecsóÚPBLE_MBUF_HDR_IGNORED£Ú"PBLE_MBUF_HDR_SCAN_REQ_TXDæÚ!PBLE_MBUF_HDR_EXT_ADV_SEC>ÚPBLE_MBUF_HDR_EXT_ADV€ÚPBLE_MBUF_HDR_DEVMATCH]Ú"PBLE_MBUF_HDR_SCAN_RSP_RXDÛÚ!PBLE_MBUF_HDR_AUX_INVALIDOÚPBLE_MBUF_HDR_WAIT_AUX'ÚPBLE_MBUF_HDR_CRC_OKÜÚ!PBLE_MBUF_HDR_MIC_FAILUREcÚPBLE_MBUF_HDR_RESOLVEDEÚ$PBLE_MBUF_HDR_INITA_RESOLVEDeÚ&PBLE_MBUF_HDR_TARGETA_RESOLVEDÎÚPBLE_MBUF_HDR_RX_STATEÚPBLE_MBUF_HDR_PTR½Ú!PBLE_MBUF_PKTHDR_OVERHEADfÚ#PBLE_MBUF_MEMBLOCK_OVERHEADåÚPBLE_MBUF_HS_HDR_LENÔÚPBLE_DEV_ADDR_LENâÚ<g_dev_addr´Ú<g_random_addrlÚ8"ble_error_codesxÚ"ÌMBLE_ERR_SUCCESSÚ""ÌMBLE_ERR_UNKNOWN_HCI_CMD„Ú"ÌMBLE_ERR_UNK_CONN_ID»Ú"ÌMBLE_ERR_HW_FAILÚ"ÌMBLE_ERR_PAGE_TMO¼Ú"ÌMBLE_ERR_AUTH_FAILyÚ!"ÌMBLE_ERR_PINKEY_MISSINGÓÚ"ÌMBLE_ERR_MEM_CAPACITY”Ú "ÌMBLE_ERR_CONN_SPVN_TMOûÚ"ÌMBLE_ERR_CONN_LIMITÚ#"ÌMBLE_ERR_SYNCH_CONN_LIMIT(Ú""ÌMBLE_ERR_ACL_CONN_EXISTS~Ú!"ÌMBLE_ERR_CMD_DISALLOWEDÚ%"ÌMBLE_ERR_CONN_REJ_RESOURCESŒÚ$"ÌMBLE_ERR_CONN_REJ_SECURITYÑÚ#"ÌMBLE_ERR_CONN_REJ_BD_ADDRKÚ""ÌMBLE_ERR_CONN_ACCEPT_TMOŽÚ"ÌMBLE_ERR_UNSUPPORTED¹Ú$"ÌMBLE_ERR_INV_HCI_CMD_PARMSáÚ%"ÌMBLE_ERR_REM_USER_CONN_TERMnÚ&"ÌMBLE_ERR_RD_CONN_TERM_RESRCS'Ú&"ÌMBLE_ERR_RD_CONN_TERM_PWROFF%Ú""ÌMBLE_ERR_CONN_TERM_LOCAL‹Ú$"ÌMBLE_ERR_REPEATED_ATTEMPTSûÚ"ÌMBLE_ERR_NO_PAIRINGÚ"ÌMBLE_ERR_UNK_LMPôÚ%"ÌMBLE_ERR_UNSUPP_REM_FEATURE{Ú"ÌMBLE_ERR_SCO_OFFSETÚ"ÌMBLE_ERR_SCO_ITVL¥Ú"ÌMBLE_ERR_SCO_AIR_MODE|Ú""ÌMBLE_ERR_INV_LMP_LL_PARM_Ú"ÌMBLE_ERR_UNSPECIFIEDóÚ%"ÌMBLE_ERR_UNSUPP_LMP_LL_PARM[Ú!"ÌMBLE_ERR_NO_ROLE_CHANGEéÚ!"ÌMBLE_ERR_LMP_LL_RSP_TMO™Ú "ÌMBLE_ERR_LMP_COLLISION*Ú"ÌMBLE_ERR_LMP_PDUùÚ""ÌMBLE_ERR_ENCRYPTION_MODE‹Ú""ÌMBLE_ERR_LINK_KEY_CHANGEŸÚ"ÌMBLE_ERR_UNSUPP_QOSçÚ!"ÌMBLE_ERR_INSTANT_PASSEDÜÚ#"ÌMBLE_ERR_UNIT_KEY_PAIRING'Ú""ÌMBLE_ERR_DIFF_TRANS_COLL‘Ú"ÌMBLE_ERR_QOS_PARM¦Ú"ÌMBLE_ERR_QOS_REJECTEDˆÚ"ÌMBLE_ERR_CHAN_CLASS5Ú#"ÌMBLE_ERR_INSUFFICIENT_SECWÚ$"ÌMBLE_ERR_PARM_OUT_OF_RANGEÏÚ""ÌMBLE_ERR_PENDING_ROLE_SW{Ú "ÌMBLE_ERR_RESERVED_SLOTÚ"ÌMBLE_ERR_ROLE_SW_FAILjÚ""ÌMBLE_ERR_INQ_RSP_TOO_BIG\Ú""ÌMBLE_ERR_SEC_SIMPLE_PAIR‹Ú!"ÌMBLE_ERR_HOST_BUSY_PAIR±Ú#"ÌMBLE_ERR_CONN_REJ_CHANNELRÚ"ÌMBLE_ERR_CTLR_BUSYOÚ"ÌMBLE_ERR_CONN_PARMSÚ"ÌMBLE_ERR_DIR_ADV_TMOºÚ "ÌMBLE_ERR_CONN_TERM_MIC!Ú%"ÌMBLE_ERR_CONN_ESTABLISHMENT´Ú "ÌMBLE_ERR_MAC_CONN_FAILEÚ!"ÌMBLE_ERR_COARSE_CLK_ADJøÚ$"ÌMBLE_ERR_TYPE0_SUBMAP_NDEFÚ!"ÌMBLE_ERR_UNK_ADV_INDENTÓÚ "ÌMBLE_ERR_LIMIT_REACHEDTÚ&"ÌMBLE_ERR_OPERATION_CANCELLED‡Ú""ÌMBLE_ERR_PACKET_TOO_LONG‚Ú"ÌMBLE_ERR_MAXLÚPBLE_HW_ERR_DO_NOT_USEúÚ!PBLE_HW_ERR_HCI_SYNC_LOSSÚPBLE_OWN_ADDR_PUBLICçÚPBLE_OWN_ADDR_RANDOMåÚ(P BLE_OWN_ADDR_RPA_PUBLIC_DEFAULT)Ú(P BLE_OWN_ADDR_RPA_RANDOM_DEFAULT'ÚPBLE_ADDR_PUBLICBÚPBLE_ADDR_RANDOM@ÚPBLE_ADDR_PUBLIC_IDPÚPBLE_ADDR_RANDOM_IDNÚP BLE_ADDR_ANYÚPBLE_ADDR_IS_RPA#ÚPBLE_ADDR_IS_NRPAÓÚPBLE_ADDR_IS_STATIC8Ú8


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type_diff&ÚPH_BLE_UUID_FÚBLE_UUID_TYPE_16 ÚBLE_UUID_TYPE_32ÚBLE_UUID_TYPE_128×Ú8


<unnamed>QÚ "«Ntype Úble_uuid_tÑÚ8


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<unnamed>SÚ "ºNu;Ú "ºNu16ÍÚ "ºNu32ËÚ "ºNu128ŠÚble_uuid_any_t"ÚPBLE_UUID16_INITJÚPBLE_UUID32_INITLÚPBLE_UUID128_INITÚPBLE_UUID16_DECLAREˆÚPBLE_UUID32_DECLAREŠÚPBLE_UUID128_DECLARERÚPBLE_UUID16çÚPBLE_UUID32éÚPBLE_UUID128±ÚPBLE_UUID_STR_LEN¬Ú ,uuidÚ,bufŽÚ,


lenšÚble_uuid_init_from_buf±Ú,uuid1ßÚ,uuid2ÞÚ ble_uuid_cmpèÚ,dst€Ú,srcƒÚble_uuid_copykÚ ,uuidÚ,dst€Úble_uuid_to_str‡Ú ,uuidÚ ble_uuid_u16LÚPH_BLE_HS_PRIV_<ÚPH_BLE_ATT_CMD_[Ú8ble_att_hdr7Ú "ÛNopcode!Ú <"ÛNdataÐÚPBLE_ATT_ERROR_RSP_SZ?Ú8ble_att_error_rsp‹Ú "ßNbaep_req_opÚ "ßNbaep_handle!Ú "ßNbaep_error_codejÚPBLE_ATT_MTU_CMD_SZøÚ8ble_att_mtu_cmd„Ú "äN    bamc_mtu=Ú!PBLE_ATT_FIND_INFO_REQ_SZ"Ú8ble_att_find_info_reqÚ "çNbafq_start_handle~Ú "çNbafq_end_handleyÚ&PBLE_ATT_FIND_INFO_RSP_BASE_SZ‘Ú8ble_att_find_info_rspÚ "ëNbafp_formatÚ+P#BLE_ATT_FIND_INFO_RSP_FORMAT_16BIT@Ú,P$BLE_ATT_FIND_INFO_RSP_FORMAT_128BIT


Ú&PBLE_ATT_FIND_INFO_IDATA_16_SZ×Ú'PBLE_ATT_FIND_INFO_IDATA_128_SZ¡Ú,P$BLE_ATT_FIND_TYPE_VALUE_REQ_BASE_SZ Ú$8ble_att_find_type_value_reqpÚ "òNbavq_start_handlecÚ "òNbavq_end_handle^Ú "òNbavq_attr_type†Ú <"òNbavq_value!Ú,P$BLE_ATT_FIND_TYPE_VALUE_RSP_BASE_SZ“Ú.P&BLE_ATT_FIND_TYPE_VALUE_HINFO_BASE_SZÚ8ble_att_handle_groupkÚ "ùNattr_handleäÚ "ùNgroup_end_handleÒÚ$8ble_att_find_type_value_rspcÚ <"üNlistÚ&PBLE_ATT_READ_TYPE_REQ_BASE_SZÚ$PBLE_ATT_READ_TYPE_REQ_SZ_16EÚ%PBLE_ATT_READ_TYPE_REQ_SZ_128Ú8ble_att_read_type_reqýÚ "Obatq_start_handleÕÚ "Obatq_end_handleÐÚ <"OuuidÚ&PBLE_ATT_READ_TYPE_RSP_BASE_SZ€Ú8ble_att_attr_data_listÚ "†OhandlezÚ <"†OvalueŸÚ8ble_att_read_type_rspðÚ "‰Obatp_lengthZÚ <"‰O


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H_BLE_HS_æÚPH_BLE_HCI_COMMON_uÚPH_NIMBLE_TRANSPORT_¼Ú!PH_NIMBLE_TRANSPORT_IMPL_!Úhs_thread_initÚble_transport_hs_initòÚll_initïÚ,bufŽÚ%ble_transport_to_ll_cmd_implÚ,omñÚ%ble_transport_to_ll_acl_implÚ,bufŽÚ%ble_transport_to_hs_evt_implöÚ,omñÚ%ble_transport_to_hs_acl_implÚPH_BLE_MONITOR_OÚPBLE_MONITOR[Úble_monitor_log›Ú,"òSlevelXÚ,"òSfmtÚ ble_transport_to_ll_cmd;Ú,"õSbuf$Ú ble_transport_to_ll_acl?Ú ,"÷Som…Ú ble_transport_to_hs_evtÚ,"ùSbuf Ú ble_transport_to_hs_acl<Ú ,"ûSomÚ ble_transport_alloc_cmd>Ú,discardable]Ú ble_transport_alloc_evt#Ú( ble_transport_alloc_acl_from_hsåÚ( ble_transport_alloc_acl_from_llèÚ,bufŽÚble_transport_freeDÚ,cbÚ2*ble_transport_register_put_acl_from_ll_cbžÚ,bufŽÚ,omñÚ,bufŽÚ,omñÚble_transport_init2ÚPBLE_HCI_MAX_DATA_LEN¡Ú8ble_hci_cmdVÚ "ŒTopcodeaÚ "ŒTlengthbÚ <"ŒTdataÚ8ble_hci_ev±Ú "TopcodefÚ "Tlength^Ú <"TdataÚPBLE_HCI_OPCODE_NOP<ÚPBLE_HCI_OP³ÚPBLE_HCI_OGFtÚPBLE_HCI_OCFxÚPBLE_HCI_OGF_LINK_CTRL?Ú PBLE_HCI_OGF_LINK_POLICY Ú"PBLE_HCI_OGF_CTLR_BASEBAND5Ú PBLE_HCI_OGF_INFO_PARAMS®Ú"PBLE_HCI_OGF_STATUS_PARAMSòÚPBLE_HCI_OGF_TESTINGçÚPBLE_HCI_OGF_LE~ÚPBLE_HCI_OGF_VENDOR9ÚPBLE_HCI_NUM_LE_CMDSÚÚ#PBLE_HCI_OCF_DISCONNECT_CMDÞÚ!8ble_hci_lc_disconnect_cpæÚ "¢Tconn_handleBÚ "¢TreasonFÚ$PBLE_HCI_OCF_RD_REM_VER_INFOIÚ#8ble_hci_rd_rem_ver_info_cp


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