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2024-12-20 51135221cd73a2b3a6ce4b5ec906396d5a33b4c7

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4117
Ø    
nÙfoÙ/#.\configuration\app_config_spark.h‡ä”»‰Ù;/C:\Keil_v5\ARM\ARMCC\Bin\..\include\inttypes.hÜ Íò6Ù9-C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.hÜ Íò$Ù9-C:\Keil_v5\ARM\ARMCC\Bin\..\include\string.hÜ Íò#ÙMA..\..\..\..\host\nimble\porting\nimble\include\sysinit/sysinit.hºÝµYÙ9-C:\Keil_v5\ARM\ARMCC\Bin\..\include\assert.hÚ Íò*Ù, .\configuration\nimble_syscfg.hºÝµlÙ.".\configuration\pan_host_config.hºÝµœÙF:..\..\..\..\host\nimble\nimble\host\include\host/ble_hs.hºÝµ§ÙG;..\..\..\..\host\nimble\nimble\include\nimble/hci_common.hºÝµWÙ@4..\..\..\..\host\nimble\nimble\include\nimble/ble.hºÝµNÙC7..\..\..\..\host\nimble\porting\nimble\include\os/os.hºÝµÏÙ9-C:\Keil_v5\ARM\ARMCC\Bin\..\include\assert.hÚ Íò*ÙG;..\..\..\..\host\nimble\nimble\include\nimble/nimble_npl.hºÝµSÙ:.C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdbool.hÜ ÍòÁÙ9-C:\Keil_v5\ARM\ARMCC\Bin\..\include\stddef.hÜ Íò@ÙXL..\..\..\..\host\nimble\porting\npl\freertos\include\nimble/nimble_npl_os.hºÝµøÙ9-C:\Keil_v5\ARM\ARMCC\Bin\..\include\assert.hÚ Íò*Ù7+..\..\..\..\os\freertos\include\FreeRTOS.hºÝµ+Ù-!.\configuration\FreeRTOSConfig.hºÝµ¯Ù^R..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\PanSeries.hºÝµHÙ8,C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.hÜ Íò™Ù9-C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdlib.hÜ Íò8Ù\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\core_cm0.hºÝµÿÙaU..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\cmsis_version.hºÝµyÙbV..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\cmsis_compiler.hºÝµ"Ù_S..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\cmsis_armcc.hºÝµ}ÙeY..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\system_PanSeries.hºÝµ6Ù`T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_sys_log.hºÝµ0Ù\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_sys.hºÝµÙÙ\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_clk.hºÝµþÙ\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_adc.hºÝµÞÙ\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_fmc.hºÝµÐÙ]Q..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_dmac.hºÝµoÙ]Q..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_gpio.hºÝµUÙ\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_spi.hºÝµºÙ]Q..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_uart.hºÝµHÙ\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_i2c.hºÝµÙ^R..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_timer.hºÝµáÙ\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_pwm.hºÝµ²Ù\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_wdt.hºÝµ·Ù]Q..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_wwdt.hºÝµ>Ù[O..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_lp.hºÝµ^Ù^R..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_efuse.hºÝµÙfZ..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\radio\prf_lib\include\pan_pri_rf.hºÝµ©Ù^R..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\PanSeries.hºÝµHÙ`T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_clktrim.hºÝµ:Ù^R..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_power.hºÝµÙ\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal.hºÝµÑÙaU..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_gpio.hºÝµ¹Ù`T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_def.hºÝµ;ÙaU..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_uart.hºÝµ¬ÙaU..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_dmac.hºÝµÓÙ`T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_spi.hºÝµÙ`T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_i2c.hºÝµlÙ`T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_wdt.hºÝµÙaU..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_wwdt.hºÝµ¢Ù`T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_pwm.hºÝµÙbV..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_timer.hºÝµEÙ`T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_adc.hºÝµBÙ7+..\..\..\..\os\freertos\include\projdefs.hºÝµ˜Ù7+..\..\..\..\os\freertos\include\portable.hºÝµœÙE9..\..\..\..\os\freertos\include\deprecated_definitions.hºÝµÍÙF:..\..\..\..\os\freertos\portable\RVDS\ARM_CM0\portmacro.hºÝµ•Ù;/..\..\..\..\os\freertos\include\mpu_wrappers.hºÝµÈÙ4(..\..\..\..\os\freertos\include\queue.hºÝµÖÙ3'..\..\..\..\os\freertos\include\task.hºÝµJÙ3'..\..\..\..\os\freertos\include\list.hºÝµAÙ5)..\..\..\..\os\fr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TIMER_CTL_PSC_MskÚP
TIMER_CTL_CAPSRC_Pos4ÚP
TIMER_CTL_CAPSRC_Msk;ÚP
TIMER_CTL_WKEN_Pos¿ÚP
TIMER_CTL_WKEN_MskÆÚP
TIMER_CTL_EXTCNTEN_PosƒÚP
TIMER_CTL_EXTCNTEN_MskŠÚP
TIMER_CTL_ACTSTS_PosÚP
TIMER_CTL_ACTSTS_Msk%ÚP
TIMER_CTL_RSTCNT_PosÚP
TIMER_CTL_RSTCNT_MskÚP
TIMER_CTL_OPMODE_Pos,ÚP
TIMER_CTL_OPMODE_Msk3ÚP
TIMER_CTL_INTEN_PostÚP
TIMER_CTL_INTEN_Msk{ÚP
TIMER_CTL_CNTEN_PoszÚP
TIMER_CTL_CNTEN_MskÚP
TIMER_CTL_ICEDEBUG_Pos´ÚP
TIMER_CTL_ICEDEBUG_Msk»ÚP
TIMER_CMP_CMPDAT_Pos:ÚP
TIMER_CMP_CMPDAT_MskAÚP
TIMER_INTSTS_TIF_PosÚP
TIMER_INTSTS_TIF_MskÚP
TIMER_INTSTS_TWKF0_Pos~ÚP
TIMER_INTSTS_TWKF0_Msk…ÚP
TIMER_INTSTS_TWKF1_Pos}ÚP
TIMER_INTSTS_TWKF1_Msk„ÚP
TIMER_INTSTS_TWKF2_Pos|ÚP
TIMER_INTSTS_TWKF2_MskƒÚP
TIMER_INTSTS_TF0_Pos$ÚP
TIMER_INTSTS_TF0_Msk+ÚP
TIMER_INTSTS_TF1_Pos#ÚP
TIMER_INTSTS_TF1_Msk*ÚP
TIMER_INTSTS_TF2_Pos"ÚP
TIMER_INTSTS_TF2_Msk)ÚP
TIMER_CNT_CNT_PosÚP
TIMER_CNT_CNT_MskÚP
TIMER_CAP_CAPDAT_PosRÚP
TIMER_CAP_CAPDAT_MskYÚ"P
TIMER_EXTCTL_CNTPHASE_PosŸÚ"P
TIMER_EXTCTL_CNTPHASE_Msk¦Ú!P
TIMER_EXTCTL_CAPEDGE_PosÚ!P
TIMER_EXTCTL_CAPEDGE_MskÚP
TIMER_EXTCTL_CAPEN_Pos”ÚP
TIMER_EXTCTL_CAPEN_Msk›Ú"P
TIMER_EXTCTL_CAPFUNCS_Pos¢Ú"P
TIMER_EXTCTL_CAPFUNCS_Msk©Ú P
TIMER_EXTCTL_CAPIEN_PosIÚ P
TIMER_EXTCTL_CAPIEN_MskPÚ!P
TIMER_EXTCTL_CAPDBEN_Pos
Ú!P
TIMER_EXTCTL_CAPDBEN_MskÚ!P
TIMER_EXTCTL_CNTDBEN_PosùÚ!P
TIMER_EXTCTL_CNTDBEN_MskÚ P
TIMER_EXTCTL_CAPSEL_PosAÚ P
TIMER_EXTCTL_CAPSEL_MskHÚ"P
TIMER_EXTCTL_ACMPSSEL_PosÚ"P
TIMER_EXTCTL_ACMPSSEL_Msk¤Ú P
TIMER_EINTSTS_CAPIF_Pos@Ú P
TIMER_EINTSTS_CAPIF_MskGÚP
TIMER_EINTSTS_CAPF_Pos‹ÚP
TIMER_EINTSTS_CAPF_Msk’Ú8

<unnamed>QÚ 
"
µTRIM_ENÌÚ 
"
µ
TRIM_CODE@Ú 
"
µ
TRIM_CTRL&Ú 
"
µ    TRIM_INTrÚ 
"
µ TRIM_CAL_CNTAÚ 
"
µTRIM_IDEAL_CNT®Ú 
"
µTRIM_REAL_CNTëÚ
TRIM_TÚ#P
TRIM_MEASURE_TUNING_EN_Pos3Ú#P
TRIM_MEASURE_TUNING_EN_Msk:Ú"P
TRIM_COARSE_TUNING_EN_PosŠÚ"P
TRIM_COARSE_TUNING_EN_Msk‘Ú P
TRIM_FINE_TUNING_EN_Pos)Ú P
TRIM_FINE_TUNING_EN_Msk0ÚP
TRIM_COARSE_CODE_Pos@ÚP
TRIM_COARSE_CODE_MskGÚP
TRIM_FINE_CODE_PosßÚP
TRIM_FINE_CODE_MskæÚP
TRIM_BIT_WIDTH_Pos½ÚP
TRIM_BIT_WIDTH_MskÄÚP
TRIM_CLRL_RELATION_Pos‰ÚP
TRIM_CLRL_RELATION_MskÚ$P
TRIM_CLRL_EARLY_TERM_EN_Pos×Ú$P
TRIM_CLRL_EARLY_TERM_EN_MskÞÚ%P
TRIM_CLRL_FAIL_CLAC_FLAG_PosÔÚ%P
TRIM_CLRL_FAIL_CLAC_FLAG_MskÛÚ P
TRIM_CLRL_CODE_STEP_Pos/Ú P
TRIM_CLRL_CODE_STEP_Msk6Ú P
TRIM_CLRL_ERR_RANGE_Pos0Ú P
TRIM_CLRL_ERR_RANGE_Msk7ÚP
TRIM_INT_EN_Pos¤ÚP
TRIM_INT_EN_Msk«Ú"P
TRIM_INT_MEASURE_STOP_PoslÚ"P
TRIM_INT_MEASURE_STOP_MsksÚ#P
TRIM_FLAG_MEASURE_STOP_Pos;Ú#P
TRIM_FLAG_MEASURE_STOP_MskBÚ P
TRIM_INT_CTUNE_STOP_PosÚ P
TRIM_INT_CTUNE_STOP_Msk
Ú!P
TRIM_FLAG_CTUNE_STOP_PosÒÚ!P
TRIM_FLAG_CTUNE_STOP_MskÙÚ P
TRIM_INT_FTUNE_STOP_PosÚ P
TRIM_INT_FTUNE_STOP_MskÚ!P
TRIM_FLAG_FTUNE_STOP_PosÏÚ!P
TRIM_FLAG_FTUNE_STOP_MskÖÚP
TRIM_INT_OVERFLOW_Pos·ÚP
TRIM_INT_OVERFLOW_Msk¾ÚP
TRIM_FLAG_OVERFLOW_Pos†ÚP
TRIM_FLAG_OVERFLOW_MskÚP
TRIM_CALC_CNT_Pos&ÚP
TRIM_CALC_CNT_Msk-ÚP
TRIM_CALC_WATI_CNT_PosˆÚP
TRIM_CALC_WATI_CNT_MskÚ8

<unnamed>QÚ 
"
êMODE¦Ú 
"
êDINOFFÚ 
"
êDOUTÚ 
"
êDATMSKÚ 
"
êPINæÚ 
"
êDBEN²Ú 
"
êINTTYPE˜Ú 
"
êINTENKÚ 
"
êINTSRCôÚ
GPIO_TÚ8

<unnamed>QÚ 
"
õDBCTLUÚ

GPIO_DB_T(ÚP
GP_MODE_MODE0_PosIÚP
GP_MODE_MODE0_MskPÚP
GP_MODE_MODE1_PosHÚP
GP_MODE_MODE1_MskOÚP
GP_MODE_MODE2_PosGÚP
GP_MODE_MODE2_MskNÚP
GP_MODE_MODE3_PosFÚP
GP_MODE_MODE3_MskMÚP
GP_MODE_MODE4_PosEÚP
GP_MODE_MODE4_MskLÚP
GP_MODE_MODE5_PosDÚP
GP_MODE_MODE5_MskKÚP
GP_DINOFF_DINOFF0_PosÚP
GP_DINOFF_DINOFF0_Msk&ÚP
GP_DINOFF_DINOFF1_PosÚP
GP_DINOFF_DINOFF1_Msk%ÚP
GP_DINOFF_DINOFF2_PosÚP
GP_DINOFF_DINOFF2_Msk$ÚP
GP_DINOFF_DINOFF3_PosÚP
GP_DINOFF_DINOFF3_Msk#ÚP
GP_DINOFF_DINOFF4_PosÚP
GP_DINOFF_DINOFF4_Msk"ÚP
GP_DINOFF_DINOFF5_PosÚP
GP_DINOFF_DINOFF5_Msk!ÚP
GP_DINOFF_DINOFF6_PosÚP
GP_DINOFF_DINOFF6_Msk ÚP
GP_DINOFF_DINOFF7_PosÚP
GP_DINOFF_DINOFF7_MskÚP
GP_DOUT_DOUT0_PosÚP
GP_DOUT_DOUT0_Msk"ÚP
GP_DOUT_DOUT1_PosÚP
GP_DOUT_DOUT1_Msk!ÚP
GP_DOUT_DOUT2_PosÚP
GP_DOUT_DOUT2_Msk ÚP
GP_DOUT_DOUT3_PosÚP
GP_DOUT_DOUT3_MskÚP
GP_DOUT_DOUT4_PosÚP
GP_DOUT_DOUT4_MskÚP
GP_DOUT_DOUT5_PosÚP
GP_DOUT_DOUT5_MskÚP
GP_DOUT_DOUT6_PosÚP
GP_DOUT_DOUT6_MskÚP
GP_DOUT_DOUT7_PosÚP
GP_DOUT_DOUT7_MskÚP
GP_DATMSK_DATMSK0_PosÚP
GP_DATMSK_DATMSK0_Msk
ÚP
GP_DATMSK_DATMSK1_PosÚP
GP_DATMSK_DATMSK1_Msk    ÚP
GP_DATMSK_DATMSK2_Pos
ÚP
GP_DATMSK_DATMSK2_MskÚP
GP_DATMSK_DATMSK3_PosÚP
GP_DATMSK_DATMSK3_MskÚP
GP_DATMSK_DATMSK4_PosÿÚP
GP_DATMSK_DATMSK4_MskÚP
GP_DATMSK_DATMSK5_PosþÚP
GP_DATMSK_DATMSK5_MskÚP
GP_DATMSK_DATMSK6_PosýÚP
GP_DATMSK_DATMSK6_MskÚP
GP_DATMSK_DATMSK7_PosüÚP
GP_DATMSK_DATMSK7_MskÚP
GP_PIN_PIN0_PosÉÚP
GP_PIN_PIN0_MskÐÚP
GP_PIN_PIN1_PosÈÚP
GP_PIN_PIN1_MskÏÚP
GP_PIN_PIN2_PosÇÚP
GP_PIN_PIN2_MskÎÚP
GP_PIN_PIN3_PosÆÚP
GP_PIN_PIN3_MskÍÚP
GP_PIN_PIN4_PosÅÚP
GP_PIN_PIN4_MskÌÚP
GP_PIN_PIN5_PosÄÚP
GP_PIN_PIN5_MskËÚP
GP_PIN_PIN6_PosÃÚP
GP_PIN_PIN6_MskÊÚP
GP_PIN_PIN7_PosÂÚP
GP_PIN_PIN7_MskÉÚP
GP_DBEN_DBEN0_PosaÚP
GP_DBEN_DBEN0_MskhÚP
GP_DBEN_DBEN1_Pos`ÚP
GP_DBEN_DBEN1_MskgÚP
GP_DBEN_DBEN2_Pos_ÚP
GP_DBEN_DBEN2_MskfÚP
GP_DBEN_DBEN3_Pos^ÚP
GP_DBEN_DBEN3_MskeÚP
GP_DBEN_DBEN4_Pos]ÚP
GP_DBEN_DBEN4_MskdÚP
GP_DBEN_DBEN5_Pos\ÚP
GP_DBEN_DBEN5_MskcÚP
GP_DBEN_DBEN6_Pos[ÚP
GP_DBEN_DBEN6_MskbÚP
GP_DBEN_DBEN7_PosZÚP
GP_DBEN_DBEN7_MskaÚP
GP_INTTYPE_TYPE0_PosÚP
GP_INTTYPE_TYPE0_Msk%ÚP
GP_INTTYPE_TYPE1_PosÚP
GP_INTTYPE_TYPE1_Msk$ÚP
GP_INTTYPE_TYPE2_PosÚP
GP_INTTYPE_TYPE2_Msk#ÚP
GP_INTTYPE_TYPE3_PosÚP
GP_INTTYPE_TYPE3_Msk"ÚP
GP_INTTYPE_TYPE4_PosÚP
GP_INTTYPE_TYPE4_Msk!ÚP
GP_INTTYPE_TYPE5_PosÚP
GP_INTTYPE_TYPE5_Msk ÚP
GP_INTTYPE_TYPE6_PosÚP
GP_INTTYPE_TYPE6_MskÚP
GP_INTTYPE_TYPE7_PosÚP
GP_INTTYPE_TYPE7_MskÚP
GP_INTEN_FLIEN0_Pos£ÚP
GP_INTEN_FLIEN0_MskªÚP
GP_INTEN_FLIEN1_Pos¢ÚP
GP_INTEN_FLIEN1_Msk©ÚP
GP_INTEN_FLIEN2_Pos¡ÚP
GP_INTEN_FLIEN2_Msk¨ÚP
GP_INTEN_FLIEN3_Pos ÚP
GP_INTEN_FLIEN3_Msk§ÚP
GP_INTEN_FLIEN4_PosŸÚP
GP_INTEN_FLIEN4_Msk¦ÚP
GP_INTEN_FLIEN5_PosžÚP
GP_INTEN_FLIEN5_Msk¥ÚP
GP_INTEN_FLIEN6_PosÚP
GP_INTEN_FLIEN6_Msk¤ÚP
GP_INTEN_FLIEN7_PosœÚP
GP_INTEN_FLIEN7_Msk£ÚP
GP_INTEN_RHIEN0_Pos›ÚP
GP_INTEN_RHIEN0_Msk¢ÚP
GP_INTEN_RHIEN1_PosšÚP
GP_INTEN_RHIEN1_Msk¡ÚP
GP_INTEN_RHIEN2_Pos™ÚP
GP_INTEN_RHIEN2_Msk ÚP
GP_INTEN_RHIEN3_Pos˜ÚP
GP_INTEN_RHIEN3_MskŸÚP
GP_INTEN_RHIEN4_Pos—ÚP
GP_INTEN_RHIEN4_MskžÚP
GP_INTEN_RHIEN5_Pos–ÚP
GP_INTEN_RHIEN5_MskÚP
GP_INTEN_RHIEN6_Pos•ÚP
GP_INTEN_RHIEN6_MskœÚP
GP_INTEN_RHIEN7_Pos”ÚP
GP_INTEN_RHIEN7_Msk›ÚP
GP_INTSRC_INTSRC0_PosåÚP
GP_INTSRC_INTSRC0_MskìÚP
GP_INTSRC_INTSRC1_PosäÚP
GP_INTSRC_INTSRC1_MskëÚP
GP_INTSRC_INTSRC2_PosãÚP
GP_INTSRC_INTSRC2_MskêÚP
GP_INTSRC_INTSRC3_PosâÚP
GP_INTSRC_INTSRC3_MskéÚP
GP_INTSRC_INTSRC4_PosáÚP
GP_INTSRC_INTSRC4_MskèÚP
GP_INTSRC_INTSRC5_PosàÚP
GP_INTSRC_INTSRC5_MskçÚP
GP_INTSRC_INTSRC6_PosßÚP
GP_INTSRC_INTSRC6_MskæÚP
GP_INTSRC_INTSRC7_PosÞÚP
GP_INTSRC_INTSRC7_MskåÚP
GP_INTSRC_INTSRC8_PosÝÚP
GP_INTSRC_INTSRC8_MskäÚP
GP_INTSRC_INTSRC9_PosÜÚP
GP_INTSRC_INTSRC9_MskãÚP
GP_INTSRC_INTSRC10_Pos²ÚP
GP_INTSRC_INTSRC10_Msk¹ÚP
GP_INTSRC_INTSRC11_Pos±ÚP
GP_INTSRC_INTSRC11_Msk¸ÚP
GP_INTSRC_INTSRC12_Pos°ÚP
GP_INTSRC_INTSRC12_Msk·ÚP
GP_INTSRC_INTSRC13_Pos¯ÚP
GP_INTSRC_INTSRC13_Msk¶ÚP
GP_INTSRC_INTSRC14_Pos®ÚP
GP_INTSRC_INTSRC14_MskµÚP
GP_INTSRC_INTSRC15_Pos­ÚP
GP_INTSRC_INTSRC15_Msk´ÚP
GP_DBCTL_DBCLKSEL_PosÚP
GP_DBCTL_DBCLKSEL_MskÚP
GP_DBCTL_DBCLKSRC_Pos
ÚP
GP_DBCTL_DBCLKSRC_MskÚP
GP_DBCTL_ICLKON_Pos–ÚP
GP_DBCTL_ICLKON_MskÚ8

<unnamed>QÚ 
"
ªDAT2Ú <"
ª
RESERVED0%Ú 
"
ªCTL(Ú 
"
ªCHENëÚ 
"
ªCMP0ùÚ 
"
ªCMP1øÚ 
"
ªSTATUS!Ú <"
ª
RESERVED10Ú 
"
ªTRGDLY/Ú 
"
ªEXTSMPTÎÚ 
"
ªSEQCTL9Ú 
"
ªSEQDAT1Ú 
"
ªSEQDAT2Ú 
"
ªCTL2ôÚ <"
ª
RESERVED2/Ú 
"
ªBV_CTL+Ú
ADC_T|ÚP
ADC_DAT_RESULT_PosØÚP
ADC_DAT_RESULT_MskßÚP
ADC_DAT_OV_PosÚP
ADC_DAT_OV_Msk!ÚP
ADC_DAT_VALID_PosIÚP
ADC_DAT_VALID_MskPÚP
ADC_CTL_ADCEN_PosTÚP
ADC_CTL_ADCEN_Msk[ÚP
ADC_CTL_ADCIEN_Pos    ÚP
ADC_CTL_ADCIEN_MskÚP
ADC_CTL_HWTRGSEL_Pos9ÚP
ADC_CTL_HWTRGSEL_Msk@ÚP
ADC_CTL_HWTRGCOND_Pos÷ÚP
ADC_CTL_HWTRGCOND_MskþÚP
ADC_CTL_HWTRGEN_PosŒÚP
ADC_CTL_HWTRGEN_Msk“ÚP
ADC_CTL_FIFO_EN_Pos•ÚP
ADC_CTL_FIFO_EN_MskœÚ$P
ADC_CTL_FIFO_THRE_STATE_PosÚ$P
ADC_CTL_FIFO_THRE_STATE_MskÚP
ADC_CTL_SWTRG_PosÚP
ADC_CTL_SWTRG_MskÚ"P
ADC_CTL_LEFT_SHIFT_EN_Pos¥Ú"P
ADC_CTL_LEFT_SHIFT_EN_Msk¬Ú P
ADC_CTL_SUB_BIAS_EN_PosIÚ P
ADC_CTL_SUB_BIAS_EN_MskPÚP
ADC_CTL_BIAS_VALUE_PosªÚP
ADC_CTL_BIAS_VALUE_Msk±ÚP
ADC_CHEN_CHEN0_Pos$ÚP
ADC_CHEN_CHEN0_Msk+ÚP
ADC_CHEN_CHEN1_Pos#ÚP
ADC_CHEN_CHEN1_Msk*ÚP
ADC_CHEN_CHEN2_Pos"ÚP
ADC_CHEN_CHEN2_Msk)ÚP
ADC_CHEN_CHEN3_Pos!ÚP
ADC_CHEN_CHEN3_Msk(ÚP
ADC_CHEN_CHEN4_Pos ÚP
ADC_CHEN_CHEN4_Msk'ÚP
ADC_CHEN_CHEN5_PosÚP
ADC_CHEN_CHEN5_Msk&ÚP
ADC_CHEN_CHEN6_PosÚP
ADC_CHEN_CHEN6_Msk%ÚP
ADC_CHEN_CHEN7_PosÚP
ADC_CHEN_CHEN7_Msk$ÚP
ADC_CHEN_CHEN8_VBG_PosÖÚP
ADC_CHEN_CHEN8_VBG_MskÝÚP
ADC_CHEN_CH9_TMP_PosZÚP
ADC_CHEN_CH9_TMP_MskaÚ P
ADC_CHEN_CH10_VDD_4_Pos¬Ú P
ADC_CHEN_CH10_VDD_4_Msk³Ú P
ADC_CHEN_CH11_VBG_2_Pos¬Ú P
ADC_CHEN_CH11_VBG_2_Msk³ÚP
ADC_CHEN_ALL_Msk¤ÚP
ADC_CMP0_ADCMPEN_Pos„ÚP
ADC_CMP0_ADCMPEN_Msk‹ÚP
ADC_CMP0_ADCMPIE_Pos‰ÚP
ADC_CMP0_ADCMPIE_MskÚP
ADC_CMP0_CMPCOND_PosxÚP
ADC_CMP0_CMPCOND_MskÚP
ADC_CMP0_CMPCH_PosÚP
ADC_CMP0_CMPCH_MskÚP
ADC_CMP0_CMPMCNT_PosjÚP
ADC_CMP0_CMPMCNT_MskqÚP
ADC_CMP0_CMPDAT_PosÅÚP
ADC_CMP0_CMPDAT_MskÌÚP
ADC_CMP1_ADCMPEN_PosƒÚP
ADC_CMP1_ADCMPEN_MskŠÚP
ADC_CMP1_ADCMPIE_PosˆÚP
ADC_CMP1_ADCMPIE_MskÚP
ADC_CMP1_CMPCOND_PoswÚP
ADC_CMP1_CMPCOND_Msk~ÚP
ADC_CMP1_CMPCH_PosÚP
ADC_CMP1_CMPCH_MskÚP
ADC_CMP1_CMPMCNT_PosiÚP
ADC_CMP1_CMPMCNT_MskpÚP
ADC_CMP1_CMPDAT_PosÄÚP
ADC_CMP1_CMPDAT_MskËÚP
ADC_STATUS_ADIF_Pos–ÚP
ADC_STATUS_ADIF_MskÚ P
ADC_STATUS_ADCMPIF0_Pos~Ú P
ADC_STATUS_ADCMPIF0_Msk…Ú P
ADC_STATUS_ADCMPIF1_Pos}Ú P
ADC_STATUS_ADCMPIF1_Msk„ÚP
ADC_STATUS_BUSY_PosgÚP
ADC_STATUS_BUSY_MsknÚP
ADC_STATUS_CHANNEL_Pos«ÚP
ADC_STATUS_CHANNEL_Msk²ÚP
ADC_STATUS_VALID_Pos8ÚP
ADC_STATUS_VALID_Msk?Ú#P
ADC_STATUS_INTMSK_FULL_Pos4Ú#P
ADC_STATUS_INTMSK_FULL_Msk;Ú$P
ADC_STATUS_INTMSK_EMPTY_PosÖÚ$P
ADC_STATUS_INTMSK_EMPTY_MskÝÚ#P
ADC_STATUS_INTMSK_OVER_Pos+Ú#P
ADC_STATUS_INTMSK_OVER_Msk2Ú#P
ADC_STATUS_INTMSK_HALF_PosLÚ#P
ADC_STATUS_INTMSK_HALF_MskSÚ!P
ADC_STATUS_INTMSK_AD_PosæÚ!P
ADC_STATUS_INTMSK_AD_MskíÚ#P
ADC_STATUS_INTMSK_CMP0_PosWÚ#P
ADC_STATUS_INTMSK_CMP0_Msk^Ú#P
ADC_STATUS_INTMSK_CMP1_PosVÚ#P
ADC_STATUS_INTMSK_CMP1_Msk]ÚP
ADC_STATUS_OV_Pos    ÚP
ADC_STATUS_OV_MskÚ&P
ADC_STATUS_ONE_CH_CLR_SEL_PosGÚ&P
ADC_STATUS_ONE_CH_CLR_SEL_MskNÚ#P
ADC_STATUS_ONE_CH_FLAG_PosWÚ#P
ADC_STATUS_ONE_CH_FLAG_Msk^Ú#P
ADC_STATUS_INTFLG_FULL_PosFÚ#P
ADC_STATUS_INTFLG_FULL_MskMÚ$P
ADC_STATUS_INTFLG_EMPTY_PosèÚ$P
ADC_STATUS_INTFLG_EMPTY_MskïÚ#P
ADC_STATUS_INTFLG_OVER_Pos=Ú#P
ADC_STATUS_INTFLG_OVER_MskDÚ#P
ADC_STATUS_INTFLG_HALF_Pos^Ú#P
ADC_STATUS_INTFLG_HALF_MskeÚP
ADC_STATUS_ADCF_PosœÚP
ADC_STATUS_ADCF_Msk£ÚP
ADC_STATUS_ADCMPF0_PosÉÚP
ADC_STATUS_ADCMPF0_MskÐÚP
ADC_STATUS_ADCMPF1_PosÈÚP
ADC_STATUS_ADCMPF1_MskÏÚ!P
ADC_STATUS_FLAG_FULL_PosôÚ!P
ADC_STATUS_FLAG_FULL_MskûÚ"P
ADC_STATUS_FLAG_EMPTY_Pos–Ú"P
ADC_STATUS_FLAG_EMPTY_MskÚ!P
ADC_STATUS_FLAG_OVER_PosëÚ!P
ADC_STATUS_FLAG_OVER_MskòÚ!P
ADC_STATUS_FLAG_HALF_PosÚ!P
ADC_STATUS_FLAG_HALF_MskÚP
ADC_TRGDLY_DELAY_PosGÚP
ADC_TRGDLY_DELAY_MskNÚ P
ADC_EXTSMPT_EXTSMPT_PosÚ P
ADC_EXTSMPT_EXTSMPT_Msk#ÚP
ADC_SEQCTL_SEQEN_PosDÚP
ADC_SEQCTL_SEQEN_MskKÚP
ADC_SEQCTL_SEQTYPE_Pos‘ÚP
ADC_SEQCTL_SEQTYPE_Msk˜ÚP
ADC_SEQCTL_MODESEL_Pos³ÚP
ADC_SEQCTL_MODESEL_MskºÚ P
ADC_SEQCTL_DELAY_EN_PosYÚ P
ADC_SEQCTL_DELAY_EN_Msk`ÚP
ADC_SEQCTL_TRG_SEL_PosŒÚP
ADC_SEQCTL_TRG_SEL_Msk“Ú!P
ADC_SEQCTL_ONE_CH_EN_PosúÚ!P
ADC_SEQCTL_ONE_CH_EN_Msk
ÚP
ADC_SEQCTL_TRG1CTL_Pos»ÚP
ADC_SEQCTL_TRG1CTL_MskÂÚP
ADC_SEQCTL_TRG2CTL_PosºÚP
ADC_SEQCTL_TRG2CTL_MskÁÚP
ADC_SEQDAT1_RESULT_Pos¶ÚP
ADC_SEQDAT1_RESULT_Msk½ÚP
ADC_SEQDAT1_OV_PosøÚP
ADC_SEQDAT1_OV_MskÿÚP
ADC_SEQDAT1_VALID_Pos'ÚP
ADC_SEQDAT1_VALID_Msk.ÚP
ADC_SEQDAT2_RESULT_PosµÚP
ADC_SEQDAT2_RESULT_Msk¼ÚP
ADC_SEQDAT2_OV_Pos÷ÚP
ADC_SEQDAT2_OV_MskþÚP
ADC_SEQDAT2_VALID_Pos&ÚP
ADC_SEQDAT2_VALID_Msk-ÚP
ADC_CTL2_TESTMODE_PosÚP
ADC_CTL2_TESTMODE_MskÚP
ADC_CTL2_SHSEL_PosüÚP
ADC_CTL2_SHSEL_MskÚP
ADC_CTL2_DMA_EN_PosµÚP
ADC_CTL2_DMA_EN_Msk¼ÚP
ADC_CTL2_CLKDIV_Pos¼ÚP
ADC_CTL2_CLKDIV_MskÃÚP
ADC_SEL_VREF_Pos}ÚP
ADC_SEL_VREF_Msk„ÚP
ADC_CTL2_CMPCTL_Pos¶ÚP
ADC_CTL2_CMPCTL_Msk½ÚP
ADC_CTL2_DRVCTL_PosªÚP
ADC_CTL2_DRVCTL_Msk±Ú8

<unnamed>QÚ 
"
íP0_MFPÿÚ 
"
íP1_MFPþÚ 
"
íP2_MFPýÚ 
"
íP3_MFPüÚ <"
0íRESV'Ú 
"
íREGLCTL²Ú 
"
íSTATUSÝÚ 
"
íCTRL0^Ú 
"
íCTRL1]Ú
SYS_TEÚP
SYS_P0_MFP_MFP_Pos´ÚP
SYS_P0_MFP_MFP_Msk»ÚP
SYS_P0_MFP_ALT0_Pos„ÚP
SYS_P0_MFP_ALT0_Msk‹ÚP
SYS_P0_MFP_ALT1_PosƒÚP
SYS_P0_MFP_ALT1_MskŠÚP
SYS_P0_MFP_ALT2_Pos‚ÚP
SYS_P0_MFP_ALT2_Msk‰ÚP
SYS_P0_MFP_ALT3_PosÚP
SYS_P0_MFP_ALT3_MskˆÚP
SYS_P0_MFP_ALT4_Pos€ÚP
SYS_P0_MFP_ALT4_Msk‡ÚP
SYS_P0_MFP_ALT5_PosÚP
SYS_P0_MFP_ALT5_Msk†ÚP
SYS_P0_MFP_ALT6_Pos~ÚP
SYS_P0_MFP_ALT6_Msk…ÚP
SYS_P0_MFP_ALT7_Pos}ÚP
SYS_P0_MFP_ALT7_Msk„ÚP
SYS_P1_MFP_MFP_Pos³ÚP
SYS_P1_MFP_MFP_MskºÚP
SYS_P1_MFP_ALT0_PosƒÚP
SYS_P1_MFP_ALT0_MskŠÚP
SYS_P1_MFP_ALT1_Pos‚ÚP
SYS_P1_MFP_ALT1_Msk‰ÚP
SYS_P1_MFP_ALT2_PosÚP
SYS_P1_MFP_ALT2_MskˆÚP
SYS_P1_MFP_ALT3_Pos€ÚP
SYS_P1_MFP_ALT3_Msk‡ÚP
SYS_P1_MFP_ALT4_PosÚP
SYS_P1_MFP_ALT4_Msk†ÚP
SYS_P1_MFP_ALT5_Pos~ÚP
SYS_P1_MFP_ALT5_Msk…ÚP
SYS_P1_MFP_ALT6_Pos}ÚP
SYS_P1_MFP_ALT6_Msk„ÚP
SYS_P1_MFP_ALT7_Pos|ÚP
SYS_P1_MFP_ALT7_MskƒÚP
SYS_P1_MFP_TYPE_PosRÚP
SYS_P1_MFP_TYPE_MskYÚP
SYS_P1_MFP_P12EXT_PosìÚP
SYS_P1_MFP_P12EXT_MskóÚP
SYS_P1_MFP_P13EXT_PosëÚP
SYS_P1_MFP_P13EXT_MskòÚP
SYS_P1_MFP_P14EXT_PosêÚP
SYS_P1_MFP_P14EXT_MskñÚP
SYS_P2_MFP_ALT0_Pos‚ÚP
SYS_P2_MFP_ALT0_Msk‰ÚP
SYS_P2_MFP_ALT1_PosÚP
SYS_P2_MFP_ALT1_MskˆÚP
SYS_P2_MFP_ALT2_Pos€ÚP
SYS_P2_MFP_ALT2_Msk‡ÚP
SYS_P2_MFP_ALT3_PosÚP
SYS_P2_MFP_ALT3_Msk†ÚP
SYS_P2_MFP_ALT4_Pos~ÚP
SYS_P2_MFP_ALT4_Msk…ÚP
SYS_P2_MFP_ALT5_Pos}ÚP
SYS_P2_MFP_ALT5_Msk„ÚP
SYS_P2_MFP_ALT6_Pos|ÚP
SYS_P2_MFP_ALT6_MskƒÚP
SYS_P2_MFP_ALT7_Pos{ÚP
SYS_P2_MFP_ALT7_Msk‚ÚP
SYS_P3_MFP_MFP_Pos±ÚP
SYS_P3_MFP_MFP_Msk¸ÚP
SYS_P3_MFP_ALT0_PosÚP
SYS_P3_MFP_ALT0_MskˆÚP
SYS_P3_MFP_ALT1_Pos€ÚP
SYS_P3_MFP_ALT1_Msk‡ÚP
SYS_P3_MFP_ALT2_PosÚP
SYS_P3_MFP_ALT2_Msk†ÚP
SYS_P3_MFP_ALT4_Pos}ÚP
SYS_P3_MFP_ALT4_Msk„ÚP
SYS_P3_MFP_ALT5_Pos|ÚP
SYS_P3_MFP_ALT5_MskƒÚP
SYS_P3_MFP_ALT6_Pos{ÚP
SYS_P3_MFP_ALT6_Msk‚ÚP
SYS_P3_MFP_P32EXT_PosèÚP
SYS_P3_MFP_P32EXT_MskïÚP
SYS_P4_MFP_MFP_Pos°ÚP
SYS_P4_MFP_MFP_Msk·ÚP
SYS_P4_MFP_ALT6_PoszÚP
SYS_P4_MFP_ALT6_MskÚP
SYS_P4_MFP_ALT7_PosyÚP
SYS_P4_MFP_ALT7_Msk€ÚP
SYS_P5_MFP_MFP_Pos¯ÚP
SYS_P5_MFP_MFP_Msk¶ÚP
SYS_P5_MFP_ALT0_PosÚP
SYS_P5_MFP_ALT0_Msk†ÚP
SYS_P5_MFP_ALT1_Pos~ÚP
SYS_P5_MFP_ALT1_Msk…ÚP
SYS_P5_MFP_ALT2_Pos}ÚP
SYS_P5_MFP_ALT2_Msk„ÚP
SYS_P5_MFP_ALT3_Pos|ÚP
SYS_P5_MFP_ALT3_MskƒÚP
SYS_P5_MFP_ALT4_Pos{ÚP
SYS_P5_MFP_ALT4_Msk‚ÚP
SYS_P5_MFP_ALT5_PoszÚP
SYS_P5_MFP_ALT5_MskÚP
SYS_P5_MFP_ALT6_PosyÚP
SYS_P5_MFP_ALT6_Msk€ÚP
SYS_P5_MFP_ALT7_PosxÚP
SYS_P5_MFP_ALT7_MskÚP
SYS_P5_MFP_P50EXT_PosæÚP
SYS_P5_MFP_P50EXT_MskíÚP
SYS_P5_MFP_P51EXT_PosåÚP
SYS_P5_MFP_P51EXT_MskìÚ P
SYS_REGLCTL_REGLCTL_Pos5Ú P
SYS_REGLCTL_REGLCTL_Msk<Ú8

<unnamed>QÚ 
"
âRSTSTSØÚ 
"
âIPRST0    Ú 
"
âIPRST1Ú 
"
â
BODCTL_3V%Ú 
"
âBLDBCTL_3VäÚ 
"
âCLK_TOP_CTRL_3VÚ 
"
âRCL_CTRL_3VdÚ 
"
â    RCH_CTRLVÚ 
"
âXTL_CTRL_3VMÚ 
"
â    XTH_CTRL?Ú 
"
â
DPLL_CTRLÚ 
"
â AHB_CLK_CTRL'Ú 
"
âAPB1_CLK_CTRLìÚ 
"
âAPB2_CLK_CTRLëÚ 
"
âMEAS_CLK_CTRLÊÚ
CLK_TjÚP
CLK_RSTSTS_CHIPRF_PosÉÚP
CLK_RSTSTS_CHIPRF_MskÐÚP
CLK_RSTSTS_PINRF_PosÚP
CLK_RSTSTS_PINRF_MskÚP
CLK_RSTSTS_WDTRF_PosÚP
CLK_RSTSTS_WDTRF_MskÚP
CLK_RSTSTS_LVRRF_PosûÚP
CLK_RSTSTS_LVRRF_MskÚP
CLK_RSTSTS_BODRF_PosÚP
CLK_RSTSTS_BODRF_Msk!ÚP
CLK_RSTSTS_SYSRF_PosðÚP
CLK_RSTSTS_SYSRF_Msk÷ÚP
CLK_RSTSTS_PORRF_PosþÚP
CLK_RSTSTS_PORRF_MskÚP
CLK_RSTSTS_CPURF_PosÚP
CLK_RSTSTS_CPURF_MskÚP
CLK_IPRST0_CHIPRST_Pos—ÚP
CLK_IPRST0_CHIPRST_MskžÚP
CLK_IPRST0_CPURST_PosÕÚP
CLK_IPRST0_CPURST_MskÜÚP
CLK_IPRST0_DMARST_PosëÚP
CLK_IPRST0_DMARST_MskòÚP
CLK_IPRST0_RFRST_Pos'ÚP
CLK_IPRST0_RFRST_Msk.Ú P
CLK_IPRST0_EFUSERST_PosAÚ P
CLK_IPRST0_EFUSERST_MskHÚP
CLK_IPRST0_USBRST_PosÓÚP
CLK_IPRST0_USBRST_MskÚÚ#P
CLK_IPRST0_MDMSTDBYRST_PosOÚ#P
CLK_IPRST0_MDMSTDBYRST_MskVÚP
CLK_IPRST0_MDMRST_PosßÚP
CLK_IPRST0_MDMRST_MskæÚ#P
CLK_IPRST0_CHIPSCOPEEN_Pos{Ú#P
CLK_IPRST0_CHIPSCOPEEN_Msk‚ÚP
CLK_IPRST0_FTORRST_Pos€ÚP
CLK_IPRST0_FTORRST_Msk‡ÚP
CLK_IPRST1_I2C0RST_PosÌÚP
CLK_IPRST1_I2C0RST_MskÓÚP
CLK_IPRST1_SPI0RST_PosžÚP
CLK_IPRST1_SPI0RST_Msk¥ÚP
CLK_IPRST1_SPI1RST_PosÚP
CLK_IPRST1_SPI1RST_Msk¤Ú P
CLK_IPRST1_UART0RST_PosLÚ P
CLK_IPRST1_UART0RST_MskSÚ P
CLK_IPRST1_UART1RST_PosKÚ P
CLK_IPRST1_UART1RST_MskRÚP
CLK_IPRST1_PWM0RST_Pos–ÚP
CLK_IPRST1_PWM0RST_MskÚP
CLK_IPRST1_ADCRST_PosôÚP
CLK_IPRST1_ADCRST_MskûÚP
CLK_IPRST1_WDTRST_PosÍÚP
CLK_IPRST1_WDTRST_MskÔÚP
CLK_IPRST1_WWDTRST_PostÚP
CLK_IPRST1_WWDTRST_Msk{ÚP
CLK_IPRST1_TMR0RST_Pos—ÚP
CLK_IPRST1_TMR0RST_MskžÚP
CLK_IPRST1_TMR1RST_Pos–ÚP
CLK_IPRST1_TMR1RST_MskÚP
CLK_IPRST1_TMR2RST_Pos•ÚP
CLK_IPRST1_TMR2RST_MskœÚP
CLK_IPRST1_GPIORST_Pos‹ÚP
CLK_IPRST1_GPIORST_Msk’ÚP
CLK_IPRST1_TRIMRST_Pos~ÚP
CLK_IPRST1_TRIMRST_Msk…Ú#P
CLK_BODCTL_BODRSTEN_Pos_3vMÚ#P
CLK_BODCTL_BODRSTEN_Msk_3vTÚP
CLK_BODCTL_BODIF_Pos^ÚP
CLK_BODCTL_BODIF_MskeÚP
CLK_BODCTL_BODOUT_PosóÚP
CLK_BODCTL_BODOUT_MskúÚ P
CLK_BODCTL_LVREN_Pos_3v-Ú P
CLK_BODCTL_LVREN_Msk_3v4Ú P
CLK_BODCTL_BODEN_Pos_3vLÚ P
CLK_BODCTL_BODEN_Msk_3vSÚ!P
CLK_BODCTL_BODSEL_Pos_3vùÚ!P
CLK_BODCTL_BODSEL_Msk_3vÚ#P
CLK_BODCTL_LVR_TEST_Pos_3vÚ#P
CLK_BODCTL_LVR_TEST_Msk_3v"Ú#P
CLK_BODCTL_BOD_TEST_Pos_3v:Ú#P
CLK_BODCTL_BOD_TEST_Msk_3vAÚ%P
CLK_BLDBCTL_LVRDB_SEL_Pos_3v®Ú%P
CLK_BLDBCTL_LVRDB_SEL_Msk_3vµÚ%P
CLK_BLDBCTL_BODDB_SEL_Pos_3vÍÚ%P
CLK_BLDBCTL_BODDB_SEL_Msk_3vÔÚ'P
CLK_TOPCTL_RSICV_SYSCNT_EN_PosÔÚ'P
CLK_TOPCTL_RSICV_SYSCNT_EN_MskÛÚ#P
CLK_TOPCTL_SYS_CLK_SEL_PosÚ#P
CLK_TOPCTL_SYS_CLK_SEL_Msk$Ú&P
CLK_TOPCTL_32K_CLK_SEL_Pos_3v^Ú&P
CLK_TOPCTL_32K_CLK_SEL_Msk_3veÚP
CLK_TOPCTL_AHB_DIV_Pos“ÚP
CLK_TOPCTL_AHB_DIV_MskšÚ P
CLK_TOPCTL_APB1_DIV_PosXÚ P
CLK_TOPCTL_APB1_DIV_Msk_Ú P
CLK_TOPCTL_APB2_DIV_PosWÚ P
CLK_TOPCTL_APB2_DIV_Msk^Ú#P
CLK_RCLCTL_RC32K_EN_Pos_3vkÚ#P
CLK_RCLCTL_RC32K_EN_Msk_3vrÚ$P
CLK_RCLCTL_RC32K_TST_EN_PosÚ$P
CLK_RCLCTL_RC32K_TST_EN_MskÚ"P
CLK_RCLCTL_CLK_SEL_Pos_3v‡Ú"P
CLK_RCLCTL_CLK_SEL_Msk_3vŽÚ'P
CLK_RCLCTL_RC32K_COARSE_Pos_3v9Ú'P
CLK_RCLCTL_RC32K_COARSE_Msk_3v@Ú%P
CLK_RCLCTL_RC32K_FINE_Pos_3vØÚ%P
CLK_RCLCTL_RC32K_FINE_Msk_3vßÚ&P
CLK_RCLCTL_RC32K_DELAY_Pos_3v‰Ú&P
CLK_RCLCTL_RC32K_DELAY_Msk_3vÚP
CLK_RCLCTL_STABLE_PosùÚP
CLK_RCLCTL_STABLE_MskÚP
CLK_RCHCTL_RCH_EN_PoséÚP
CLK_RCHCTL_RCH_EN_MskðÚ"P
CLK_RCHCTL_RCH_TST_EN_Pos‡Ú"P
CLK_RCHCTL_RCH_TST_EN_MskŽÚP
CLK_RCHCTL_CLK_SEL_Pos™ÚP
CLK_RCHCTL_CLK_SEL_Msk ÚP
CLK_RCHCTL_BIAS_PosÚP
CLK_RCHCTL_BIAS_Msk¤Ú P
CLK_RCHCTL_RCH_FREQ_PosJÚ P
CLK_RCHCTL_RCH_FREQ_MskQÚP
CLK_RCHCTL_DELAY_PosKÚP
CLK_RCHCTL_DELAY_MskRÚP
CLK_RCHCTL_STABLE_PosýÚP
CLK_RCHCTL_STABLE_MskÚ!P
CLK_XTLCTL_XTL_EN_Pos_3v¥Ú!P
CLK_XTLCTL_XTL_EN_Msk_3v¬Ú"P
CLK_XTLCTL_XTL_TST_EN_PosQÚ"P
CLK_XTLCTL_XTL_TST_EN_MskXÚ$P
CLK_XTLCTL_CORE_BIAS_Pos_3vâÚ$P
CLK_XTLCTL_CORE_BIAS_Msk_3véÚ#P
CLK_XTLCTL_XTL_TRIM_Pos_3vøÚ#P
CLK_XTLCTL_XTL_TRIM_Msk_3vÿÚ%P
CLK_XTLCTL_XTL_CAP_EN_Pos_3vjÚ%P
CLK_XTLCTL_XTL_CAP_EN_Msk_3vqÚ P
CLK_XTLCTL_DELAY_Pos_3v"Ú P
CLK_XTLCTL_DELAY_Msk_3v)ÚP
CLK_XTLCTL_STABLE_PosâÚP
CLK_XTLCTL_STABLE_MskéÚP
CLK_XTHCTL_XTH_EN_Pos»ÚP
CLK_XTHCTL_XTH_EN_MskÂÚ"P
CLK_XTHCTL_XTH_TST_EN_PosYÚ"P
CLK_XTHCTL_XTH_TST_EN_Msk`Ú"P
CLK_XTHCTL_START_FAST_Pos~Ú"P
CLK_XTHCTL_START_FAST_Msk…Ú#P
CLK_XTHCTL_DEGLITCH_EN_PosaÚ#P
CLK_XTHCTL_DEGLITCH_EN_MskhÚ"P
CLK_XTHCTL_XO_CAP_SEL_Pos|Ú"P
CLK_XTHCTL_XO_CAP_SEL_MskƒÚP
CLK_XTHCTL_DELAY_Pos4ÚP
CLK_XTHCTL_DELAY_Msk;ÚP
CLK_XTHCTL_STABLE_PosæÚP
CLK_XTHCTL_STABLE_MskíÚ P
CLK_DPLLCTL_DPLL_EN_PosGÚ P
CLK_DPLLCTL_DPLL_EN_MskNÚ$P
CLK_DPLLCTL_DPLL_TST_EN_PosåÚ$P
CLK_DPLLCTL_DPLL_TST_EN_MskìÚ!P
CLK_DPLLCTL_FREQ_OUT_PosÞÚ!P
CLK_DPLLCTL_FREQ_OUT_MskåÚ!P
CLK_DPLLCTL_RCLK_SEL_PosôÚ!P
CLK_DPLLCTL_RCLK_SEL_MskûÚ!P
CLK_DPLLCTL_ICP_BIAS_Pos    Ú!P
CLK_DPLLCTL_ICP_BIAS_MskÚ!P
CLK_DPLLCTL_ICP_CTRL_PosóÚ!P
CLK_DPLLCTL_ICP_CTRL_MskúÚ"P
CLK_DPLLCTL_KVCO_CTRL_PosšÚ"P
CLK_DPLLCTL_KVCO_CTRL_Msk¡Ú&P
CLK_DPLLCTL_VCO_FREQ_TRIM_PosIÚ&P
CLK_DPLLCTL_VCO_FREQ_TRIM_MskPÚ P
CLK_DPLLCTL_DIV_SEL_Pos?Ú P
CLK_DPLLCTL_DIV_SEL_MskFÚP
CLK_DPLLCTL_DELAY_PosúÚP
CLK_DPLLCTL_DELAY_Msk
ÚP
CLK_DPLLCTL_STABLE_Pos¬ÚP
CLK_DPLLCTL_STABLE_Msk³ÚP
CLK_AHBCLK_DMAEN_PospÚP
CLK_AHBCLK_DMAEN_MskwÚP
CLK_AHBCLK_GPIOEN_PosÚP
CLK_AHBCLK_GPIOEN_MskÚ"P
CLK_AHBCLK_SYSTICK_EN_Pos¯Ú"P
CLK_AHBCLK_SYSTICK_EN_Msk¶ÚP
CLK_AHBCLK_APB1EN_Pos<ÚP
CLK_AHBCLK_APB1EN_MskCÚP
CLK_AHBCLK_APB2EN_Pos;ÚP
CLK_AHBCLK_APB2EN_MskBÚP
CLK_AHBCLK_AHBEN_PoswÚP
CLK_AHBCLK_AHBEN_Msk~Ú!P
CLK_AHBCLK_BLE32M_EN_PosVÚ!P
CLK_AHBCLK_BLE32M_EN_Msk]Ú!P
CLK_AHBCLK_BLE32K_EN_PosXÚ!P
CLK_AHBCLK_BLE32K_EN_Msk_Ú"P
CLK_AHBCLK_BLE32M_SEL_PosÚ"P
CLK_AHBCLK_BLE32M_SEL_Msk
Ú"P
CLK_AHBCLK_ROM_CLK_EN_Pos²Ú"P
CLK_AHBCLK_ROM_CLK_EN_Msk¹Ú$P
CLK_AHBCLK_EFUSE_CLK_EN_Pos$Ú$P
CLK_AHBCLK_EFUSE_CLK_EN_Msk+Ú&P
CLK_AHBCLK_USB_AHB_CLK_EN_Pos„Ú&P
CLK_AHBCLK_USB_AHB_CLK_EN_Msk‹Ú&P
CLK_AHBCLK_USB_48M_CLK_EN_Pos–Ú&P
CLK_AHBCLK_USB_48M_CLK_EN_MskÚ%P
CLK_AHBCLK_SPI_FLASH_DIV_PosÊÚ%P
CLK_AHBCLK_SPI_FLASH_DIV_MskÑÚ)P
!CLK_AHBCLK_SPI_FLASH_CLK_SEL_PosˆÚ)P
!CLK_AHBCLK_SPI_FLASH_CLK_SEL_MskÚ'P
CLK_AHBCLK_DPLL_CLK_TST_EN_PosÚ'P
CLK_AHBCLK_DPLL_CLK_TST_EN_MskÚ(P
 CLK_AHBCLK_SPI_CLK_SEL_FPGA_PosÚÚ(P
 CLK_AHBCLK_SPI_CLK_SEL_FPGA_MskáÚ#P
CLK_APB1CLK_WDTSRC_SEL_PosvÚ#P
CLK_APB1CLK_WDTSRC_SEL_Msk}Ú$P
CLK_APB1CLK_WWDTSRC_SEL_PosÚ$P
CLK_APB1CLK_WWDTSRC_SEL_Msk$Ú$P
CLK_APB1CLK_TMR0SRC_SEL_Pos@Ú$P
CLK_APB1CLK_TMR0SRC_SEL_MskGÚ&P
CLK_APB1CLK_PWM01_CLK_SEL_Pos¹Ú&P
CLK_APB1CLK_PWM01_CLK_SEL_MskÀÚ&P
CLK_APB1CLK_PWM23_CLK_SEL_PosµÚ&P
CLK_APB1CLK_PWM23_CLK_SEL_Msk¼Ú&P
CLK_APB1CLK_PWM45_CLK_SEL_Pos±Ú&P
CLK_APB1CLK_PWM45_CLK_SEL_Msk¸Ú&P
CLK_APB1CLK_PWM67_CLK_SEL_Pos­Ú&P
CLK_APB1CLK_PWM67_CLK_SEL_Msk´Ú$P
CLK_APB1CLK_ADC_CLK_SEL_PosJÚ$P
CLK_APB1CLK_ADC_CLK_SEL_MskQÚ$P
CLK_APB2CLK_TMR1SRC_SEL_Pos>Ú$P
CLK_APB2CLK_TMR1SRC_SEL_MskEÚ$P
CLK_APB2CLK_TMR2SRC_SEL_Pos=Ú$P
CLK_APB2CLK_TMR2SRC_SEL_MskDÚ$P
CLK_MEASCLK_TRIM_CLK_EN_PosÚ$P
CLK_MEASCLK_TRIM_CLK_EN_MskÚ%P
CLK_MEASCLK_TRIM_CLK_SEL_Pos²Ú%P
CLK_MEASCLK_TRIM_CLK_SEL_Msk¹Ú%P
CLK_MEASCLK_TRIM_CLK_DIV_Pos³Ú%P
CLK_MEASCLK_TRIM_CLK_DIV_MskºÚ%P
CLK_MEASCLK_XTL_QUICK_EN_Pos¤Ú%P
CLK_MEASCLK_XTL_QUICK_EN_Msk«Ú P
CLK_MEASCLK_XTH_DIV_Pos>Ú P
CLK_MEASCLK_XTH_DIV_MskEÚ8

<unnamed>QÚ 
"
áCTLíÚ 
"
áALTCTLÚ
WDT_TUÚP
WDT_CTL_RSTCNT_Pos¨ÚP
WDT_CTL_RSTCNT_Msk¯ÚP
WDT_CTL_RSTEN_PosüÚP
WDT_CTL_RSTEN_MskÚP
WDT_CTL_RSTF_PosKÚP
WDT_CTL_RSTF_MskRÚP
WDT_CTL_IF_PosÿÚP
WDT_CTL_IF_MskÚP
WDT_CTL_WKEN_PosUÚP
WDT_CTL_WKEN_Msk\ÚP
WDT_CTL_WKF_Pos¤ÚP
WDT_CTL_WKF_Msk«ÚP
WDT_CTL_INTEN_Pos
ÚP
WDT_CTL_INTEN_MskÚP
WDT_CTL_WDTEN_PosÚP
WDT_CTL_WDTEN_Msk ÚP
WDT_CTL_TOUTSEL_PosTÚP
WDT_CTL_TOUTSEL_Msk[Ú#P
WDT_CTL_RST_REGION_SEL_PosÚ#P
WDT_CTL_RST_REGION_SEL_MskÚP
WDT_CTL_TOF_Pos£ÚP
WDT_CTL_TOF_MskªÚP
WDT_CTL_ICEDEBUG_PosJÚP
WDT_CTL_ICEDEBUG_MskQÚP
WDT_ALTCTL_RSTDSEL_Pos|ÚP
WDT_ALTCTL_RSTDSEL_MskƒÚ8

<unnamed>QÚ 
"
ÿRLDCNTåÚ 
"
ÿCTLÏÚ 
"
ÿSTATUSÈÚ 
"
ÿCNTÍÚ
WWDT_TüÚP
WWDT_RLDCNT_RLDCNT_Pos|ÚP
WWDT_RLDCNT_RLDCNT_MskƒÚP
WWDT_CTL_WWDTEN_PosTÚP
WWDT_CTL_WWDTEN_Msk[ÚP
WWDT_CTL_INTEN_Pos±ÚP
WWDT_CTL_INTEN_Msk¸ÚP
WWDT_CTL_PSCSEL_PoscÚP
WWDT_CTL_PSCSEL_MskjÚP
WWDT_CTL_CMPDAT_PostÚP
WWDT_CTL_CMPDAT_Msk{ÚP
WWDT_CTL_ICEDEBUG_PosñÚP
WWDT_CTL_ICEDEBUG_MskøÚP
WWDT_STATUS_WWDTIF_PosQÚP
WWDT_STATUS_WWDTIF_MskXÚP
WWDT_STATUS_WWDTRF_PosHÚP
WWDT_STATUS_WWDTRF_MskOÚP
WWDT_STATUS_WWDTF_PosœÚP
WWDT_STATUS_WWDTF_Msk£ÚP
WWDT_CNT_CNTDAT_PosmÚP
WWDT_CNT_CNTDAT_MsktÚ8

<unnamed>QÚ 
"
™CLKPSCQÚ 
"
™CLKDIVTÚ 
"
™CTL4Ú 
"
™PERIOD0Ú 
"
™PERIOD1Ú 
"
™PERIOD2Ú 
"
™PERIOD3Ú 
"
™PERIOD4Ú 
"
™PERIOD5Ú 
"
™PERIOD6Ú 
"
™PERIOD7Ú 
"
™CMPDAT0&Ú 
"
™CMPDAT1%Ú 
"
™CMPDAT2$Ú 
"
™CMPDAT3#Ú 
"
™CMPDAT4"Ú 
"
™CMPDAT5!Ú 
"
™CMPDAT6 Ú 
"
™CMPDAT7Ú 
"
™CTL2Ú 
"
™FLAGûÚ 
"
™INTEN•Ú 
"
™INTSTS,Ú 
"
™POENãÚ <"
™
RESERVED0IÚ 
"
™DTCTL˜Ú 
"
™    ADCTCTL0ÞÚ 
"
™    ADCTCTL1ÝÚ 
"
™    ADCTSTS0ÇÚ 
"
™    ADCTSTS1ÆÚ <"
™
RESERVED1<Ú 
"
™PCACTLZÚ
PWM_TPÚ P
PWM_CLKPSC_CLKPSC01_PosyÚ P
PWM_CLKPSC_CLKPSC01_Msk€Ú P
PWM_CLKPSC_CLKPSC23_PosuÚ P
PWM_CLKPSC_CLKPSC23_Msk|Ú P
PWM_CLKPSC_CLKPSC45_PosqÚ P
PWM_CLKPSC_CLKPSC45_MskxÚ P
PWM_CLKPSC_CLKPSC67_PosmÚ P
PWM_CLKPSC_CLKPSC67_MsktÚP
PWM_CLKDIV_CLKDIV0_Pos²ÚP
PWM_CLKDIV_CLKDIV0_Msk¹ÚP
PWM_CLKDIV_CLKDIV1_Pos±ÚP
PWM_CLKDIV_CLKDIV1_Msk¸ÚP
PWM_CLKDIV_CLKDIV2_Pos°ÚP
PWM_CLKDIV_CLKDIV2_Msk·ÚP
PWM_CLKDIV_CLKDIV3_Pos¯ÚP
PWM_CLKDIV_CLKDIV3_Msk¶ÚP
PWM_CLKDIV_CLKDIV4_Pos®ÚP
PWM_CLKDIV_CLKDIV4_MskµÚP
PWM_CLKDIV_CLKDIV5_Pos­ÚP
PWM_CLKDIV_CLKDIV5_Msk´ÚP
PWM_CLKDIV_CLKDIV6_Pos¬ÚP
PWM_CLKDIV_CLKDIV6_Msk³ÚP
PWM_CLKDIV_CLKDIV7_Pos«ÚP
PWM_CLKDIV_CLKDIV7_Msk²ÚP
PWM_CTL_CNTEN0_PosÙÚP
PWM_CTL_CNTEN0_MskàÚP
PWM_CTL_PINV0_PosÚP
PWM_CTL_PINV0_MskÚP
PWM_CTL_CNTMODE0_PosCÚP
PWM_CTL_CNTMODE0_MskJÚP
PWM_CTL_CNTEN1_PosØÚP
PWM_CTL_CNTEN1_MskßÚP
PWM_CTL_HCUPDT_Pos¹ÚP
PWM_CTL_HCUPDT_MskÀÚP
PWM_CTL_PINV1_PosÚP
PWM_CTL_PINV1_MskÚP
PWM_CTL_CNTMODE1_PosBÚP
PWM_CTL_CNTMODE1_MskIÚP
PWM_CTL_CNTEN2_Pos×ÚP
PWM_CTL_CNTEN2_MskÞÚP
PWM_CTL_PINV2_PosÚP
PWM_CTL_PINV2_MskÚP
PWM_CTL_CNTMODE2_PosAÚP
PWM_CTL_CNTMODE2_MskHÚP
PWM_CTL_CNTEN3_PosÖÚP
PWM_CTL_CNTEN3_MskÝÚP
PWM_CTL_PINV3_PosÚP
PWM_CTL_PINV3_MskÚP
PWM_CTL_CNTMODE3_Pos@ÚP
PWM_CTL_CNTMODE3_MskGÚP
PWM_CTL_CNTEN4_PosÕÚP
PWM_CTL_CNTEN4_MskÜÚP
PWM_CTL_PINV4_PosÚP
PWM_CTL_PINV4_MskÚP
PWM_CTL_CNTMODE4_Pos?ÚP
PWM_CTL_CNTMODE4_MskFÚP
PWM_CTL_CNTEN5_PosÔÚP
PWM_CTL_CNTEN5_MskÛÚP
PWM_CTL_ASYMEN_Pos´ÚP
PWM_CTL_ASYMEN_Msk»ÚP
PWM_CTL_PINV5_PosÚP
PWM_CTL_PINV5_MskÚP
PWM_CTL_CNTMODE5_Pos>ÚP
PWM_CTL_CNTMODE5_MskEÚP
PWM_CTL_CNTEN6_PosÓÚP
PWM_CTL_CNTEN6_MskÚÚP
PWM_CTL_PINV6_PosÚP
PWM_CTL_PINV6_MskÚP
PWM_CTL_CNTMODE6_Pos=ÚP
PWM_CTL_CNTMODE6_MskDÚP
PWM_CTL_CNTEN7_PosÒÚP
PWM_CTL_CNTEN7_MskÙÚP
PWM_CTL_PINV7_PosÚP
PWM_CTL_PINV7_MskÚP
PWM_CTL_CNTMODE7_Pos<ÚP
PWM_CTL_CNTMODE7_MskCÚ P
PWM_PERIOD0_PERIOD0_PostÚ P
PWM_PERIOD0_PERIOD0_Msk{Ú P
PWM_PERIOD0_PERIOD1_PossÚ P
PWM_PERIOD0_PERIOD1_MskzÚ P
PWM_PERIOD0_PERIOD2_PosrÚ P
PWM_PERIOD0_PERIOD2_MskyÚ P
PWM_PERIOD0_PERIOD3_PosqÚ P
PWM_PERIOD0_PERIOD3_MskxÚ P
PWM_PERIOD0_PERIOD4_PospÚ P
PWM_PERIOD0_PERIOD4_MskwÚ P
PWM_PERIOD0_PERIOD5_PosoÚ P
PWM_PERIOD0_PERIOD5_MskvÚ P
PWM_PERIOD0_PERIOD6_PosnÚ P
PWM_PERIOD0_PERIOD6_MskuÚ P
PWM_PERIOD0_PERIOD7_PosmÚ P
PWM_PERIOD0_PERIOD7_MsktÚ P
PWM_PERIOD1_PERIOD0_PossÚ P
PWM_PERIOD1_PERIOD0_MskzÚ P
PWM_PERIOD1_PERIOD1_PosrÚ P
PWM_PERIOD1_PERIOD1_MskyÚ P
PWM_PERIOD1_PERIOD2_PosqÚ P
PWM_PERIOD1_PERIOD2_MskxÚ P
PWM_PERIOD1_PERIOD3_PospÚ P
PWM_PERIOD1_PERIOD3_MskwÚ P
PWM_PERIOD1_PERIOD4_PosoÚ P
PWM_PERIOD1_PERIOD4_MskvÚ P
PWM_PERIOD1_PERIOD5_PosnÚ P
PWM_PERIOD1_PERIOD5_MskuÚ P
PWM_PERIOD1_PERIOD6_PosmÚ P
PWM_PERIOD1_PERIOD6_MsktÚ P
PWM_PERIOD1_PERIOD7_PoslÚ P
PWM_PERIOD1_PERIOD7_MsksÚ P
PWM_PERIOD2_PERIOD0_PosrÚ P
PWM_PERIOD2_PERIOD0_MskyÚ P
PWM_PERIOD2_PERIOD1_PosqÚ P
PWM_PERIOD2_PERIOD1_MskxÚ P
PWM_PERIOD2_PERIOD2_PospÚ P
PWM_PERIOD2_PERIOD2_MskwÚ P
PWM_PERIOD2_PERIOD3_PosoÚ P
PWM_PERIOD2_PERIOD3_MskvÚ P
PWM_PERIOD2_PERIOD4_PosnÚ P
PWM_PERIOD2_PERIOD4_MskuÚ P
PWM_PERIOD2_PERIOD5_PosmÚ P
PWM_PERIOD2_PERIOD5_MsktÚ P
PWM_PERIOD2_PERIOD6_PoslÚ P
PWM_PERIOD2_PERIOD6_MsksÚ P
PWM_PERIOD2_PERIOD7_PoskÚ P
PWM_PERIOD2_PERIOD7_MskrÚ P
PWM_PERIOD3_PERIOD0_PosqÚ P
PWM_PERIOD3_PERIOD0_MskxÚ P
PWM_PERIOD3_PERIOD1_PospÚ P
PWM_PERIOD3_PERIOD1_MskwÚ P
PWM_PERIOD3_PERIOD2_PosoÚ P
PWM_PERIOD3_PERIOD2_MskvÚ P
PWM_PERIOD3_PERIOD3_PosnÚ P
PWM_PERIOD3_PERIOD3_MskuÚ P
PWM_PERIOD3_PERIOD4_PosmÚ P
PWM_PERIOD3_PERIOD4_MsktÚ P
PWM_PERIOD3_PERIOD5_PoslÚ P
PWM_PERIOD3_PERIOD5_MsksÚ P
PWM_PERIOD3_PERIOD6_PoskÚ P
PWM_PERIOD3_PERIOD6_MskrÚ P
PWM_PERIOD3_PERIOD7_PosjÚ P
PWM_PERIOD3_PERIOD7_MskqÚ P
PWM_PERIOD4_PERIOD0_PospÚ P
PWM_PERIOD4_PERIOD0_MskwÚ P
PWM_PERIOD4_PERIOD1_PosoÚ P
PWM_PERIOD4_PERIOD1_MskvÚ P
PWM_PERIOD4_PERIOD2_PosnÚ P
PWM_PERIOD4_PERIOD2_MskuÚ P
PWM_PERIOD4_PERIOD3_PosmÚ P
PWM_PERIOD4_PERIOD3_MsktÚ P
PWM_PERIOD4_PERIOD4_PoslÚ P
PWM_PERIOD4_PERIOD4_MsksÚ P
PWM_PERIOD4_PERIOD5_PoskÚ P
PWM_PERIOD4_PERIOD5_MskrÚ P
PWM_PERIOD4_PERIOD6_PosjÚ P
PWM_PERIOD4_PERIOD6_MskqÚ P
PWM_PERIOD4_PERIOD7_PosiÚ P
PWM_PERIOD4_PERIOD7_MskpÚ P
PWM_PERIOD5_PERIOD0_PosoÚ P
PWM_PERIOD5_PERIOD0_MskvÚ P
PWM_PERIOD5_PERIOD1_PosnÚ P
PWM_PERIOD5_PERIOD1_MskuÚ P
PWM_PERIOD5_PERIOD2_PosmÚ P
PWM_PERIOD5_PERIOD2_MsktÚ P
PWM_PERIOD5_PERIOD3_PoslÚ P
PWM_PERIOD5_PERIOD3_MsksÚ P
PWM_PERIOD5_PERIOD4_PoskÚ P
PWM_PERIOD5_PERIOD4_MskrÚ P
PWM_PERIOD5_PERIOD5_PosjÚ P
PWM_PERIOD5_PERIOD5_MskqÚ P
PWM_PERIOD5_PERIOD6_PosiÚ P
PWM_PERIOD5_PERIOD6_MskpÚ P
PWM_PERIOD5_PERIOD7_PoshÚ P
PWM_PERIOD5_PERIOD7_MskoÚ P
PWM_PERIOD6_PERIOD0_PosnÚ P
PWM_PERIOD6_PERIOD0_MskuÚ P
PWM_PERIOD6_PERIOD1_PosmÚ P
PWM_PERIOD6_PERIOD1_MsktÚ P
PWM_PERIOD6_PERIOD2_PoslÚ P
PWM_PERIOD6_PERIOD2_MsksÚ P
PWM_PERIOD6_PERIOD3_PoskÚ P
PWM_PERIOD6_PERIOD3_MskrÚ P
PWM_PERIOD6_PERIOD4_PosjÚ P
PWM_PERIOD6_PERIOD4_MskqÚ P
PWM_PERIOD6_PERIOD5_PosiÚ P
PWM_PERIOD6_PERIOD5_MskpÚ P
PWM_PERIOD6_PERIOD6_PoshÚ P
PWM_PERIOD6_PERIOD6_MskoÚ P
PWM_PERIOD6_PERIOD7_PosgÚ P
PWM_PERIOD6_PERIOD7_MsknÚ P
PWM_PERIOD7_PERIOD0_PosmÚ P
PWM_PERIOD7_PERIOD0_MsktÚ P
PWM_PERIOD7_PERIOD1_PoslÚ P
PWM_PERIOD7_PERIOD1_MsksÚ P
PWM_PERIOD7_PERIOD2_PoskÚ P
PWM_PERIOD7_PERIOD2_MskrÚ P
PWM_PERIOD7_PERIOD3_PosjÚ P
PWM_PERIOD7_PERIOD3_MskqÚ P
PWM_PERIOD7_PERIOD4_PosiÚ P
PWM_PERIOD7_PERIOD4_MskpÚ P
PWM_PERIOD7_PERIOD5_PoshÚ P
PWM_PERIOD7_PERIOD5_MskoÚ P
PWM_PERIOD7_PERIOD6_PosgÚ P
PWM_PERIOD7_PERIOD6_MsknÚ P
PWM_PERIOD7_PERIOD7_PosfÚ P
PWM_PERIOD7_PERIOD7_MskmÚP
PWM_CMPDAT0_CMP0_PosgÚP
PWM_CMPDAT0_CMP0_MsknÚP
PWM_CMPDAT0_CMP1_PosfÚP
PWM_CMPDAT0_CMP1_MskmÚP
PWM_CMPDAT0_CMP2_PoseÚP
PWM_CMPDAT0_CMP2_MsklÚP
PWM_CMPDAT0_CMP3_PosdÚP
PWM_CMPDAT0_CMP3_MskkÚP
PWM_CMPDAT0_CMP4_PoscÚP
PWM_CMPDAT0_CMP4_MskjÚP
PWM_CMPDAT0_CMP5_PosbÚP
PWM_CMPDAT0_CMP5_MskiÚP
PWM_CMPDAT0_CMP6_PosaÚP
PWM_CMPDAT0_CMP6_MskhÚP
PWM_CMPDAT0_CMP7_Pos`ÚP
PWM_CMPDAT0_CMP7_MskgÚP
PWM_CMPDAT0_CMPD0_Pos!ÚP
PWM_CMPDAT0_CMPD0_Msk(ÚP
PWM_CMPDAT0_CMPD1_Pos ÚP
PWM_CMPDAT0_CMPD1_Msk'ÚP
PWM_CMPDAT0_CMPD2_PosÚP
PWM_CMPDAT0_CMPD2_Msk&ÚP
PWM_CMPDAT0_CMPD3_PosÚP
PWM_CMPDAT0_CMPD3_Msk%ÚP
PWM_CMPDAT0_CMPD4_PosÚP
PWM_CMPDAT0_CMPD4_Msk$ÚP
PWM_CMPDAT0_CMPD5_PosÚP
PWM_CMPDAT0_CMPD5_Msk#ÚP
PWM_CMPDAT0_CMPD6_PosÚP
PWM_CMPDAT0_CMPD6_Msk"ÚP
PWM_CMPDAT0_CMPD7_PosÚP
PWM_CMPDAT0_CMPD7_Msk!ÚP
PWM_CMPDAT1_CMP0_PosfÚP
PWM_CMPDAT1_CMP0_MskmÚP
PWM_CMPDAT1_CMP1_PoseÚP
PWM_CMPDAT1_CMP1_MsklÚP
PWM_CMPDAT1_CMP2_PosdÚP
PWM_CMPDAT1_CMP2_MskkÚP
PWM_CMPDAT1_CMP3_PoscÚP
PWM_CMPDAT1_CMP3_MskjÚP
PWM_CMPDAT1_CMP4_PosbÚP
PWM_CMPDAT1_CMP4_MskiÚP
PWM_CMPDAT1_CMP5_PosaÚP
PWM_CMPDAT1_CMP5_MskhÚP
PWM_CMPDAT1_CMP6_Pos`ÚP
PWM_CMPDAT1_CMP6_MskgÚP
PWM_CMPDAT1_CMP7_Pos_ÚP
PWM_CMPDAT1_CMP7_MskfÚP
PWM_CMPDAT1_CMPD0_Pos ÚP
PWM_CMPDAT1_CMPD0_Msk'ÚP
PWM_CMPDAT1_CMPD1_PosÚP
PWM_CMPDAT1_CMPD1_Msk&ÚP
PWM_CMPDAT1_CMPD2_PosÚP
PWM_CMPDAT1_CMPD2_Msk%ÚP
PWM_CMPDAT1_CMPD3_PosÚP
PWM_CMPDAT1_CMPD3_Msk$ÚP
PWM_CMPDAT1_CMPD4_PosÚP
PWM_CMPDAT1_CMPD4_Msk#ÚP
PWM_CMPDAT1_CMPD5_PosÚP
PWM_CMPDAT1_CMPD5_Msk"ÚP
PWM_CMPDAT1_CMPD6_PosÚP
PWM_CMPDAT1_CMPD6_Msk!ÚP
PWM_CMPDAT1_CMPD7_PosÚP
PWM_CMPDAT1_CMPD7_Msk ÚP
PWM_CMPDAT2_CMP0_PoseÚP
PWM_CMPDAT2_CMP0_MsklÚP
PWM_CMPDAT2_CMP1_PosdÚP
PWM_CMPDAT2_CMP1_MskkÚP
PWM_CMPDAT2_CMP2_PoscÚP
PWM_CMPDAT2_CMP2_MskjÚP
PWM_CMPDAT2_CMP3_PosbÚP
PWM_CMPDAT2_CMP3_MskiÚP
PWM_CMPDAT2_CMP4_PosaÚP
PWM_CMPDAT2_CMP4_MskhÚP
PWM_CMPDAT2_CMP5_Pos`ÚP
PWM_CMPDAT2_CMP5_MskgÚP
PWM_CMPDAT2_CMP6_Pos_ÚP
PWM_CMPDAT2_CMP6_MskfÚP
PWM_CMPDAT2_CMP7_Pos^ÚP
PWM_CMPDAT2_CMP7_MskeÚP
PWM_CMPDAT2_CMPD0_PosÚP
PWM_CMPDAT2_CMPD0_Msk&ÚP
PWM_CMPDAT2_CMPD1_PosÚP
PWM_CMPDAT2_CMPD1_Msk%ÚP
PWM_CMPDAT2_CMPD2_PosÚP
PWM_CMPDAT2_CMPD2_Msk$ÚP
PWM_CMPDAT2_CMPD3_PosÚP
PWM_CMPDAT2_CMPD3_Msk#ÚP
PWM_CMPDAT2_CMPD4_PosÚP
PWM_CMPDAT2_CMPD4_Msk"ÚP
PWM_CMPDAT2_CMPD5_PosÚP
PWM_CMPDAT2_CMPD5_Msk!ÚP
PWM_CMPDAT2_CMPD6_PosÚP
PWM_CMPDAT2_CMPD6_Msk ÚP
PWM_CMPDAT2_CMPD7_PosÚP
PWM_CMPDAT2_CMPD7_MskÚP
PWM_CMPDAT3_CMP0_PosdÚP
PWM_CMPDAT3_CMP0_MskkÚP
PWM_CMPDAT3_CMP1_PoscÚP
PWM_CMPDAT3_CMP1_MskjÚP
PWM_CMPDAT3_CMP2_PosbÚP
PWM_CMPDAT3_CMP2_MskiÚP
PWM_CMPDAT3_CMP3_PosaÚP
PWM_CMPDAT3_CMP3_MskhÚP
PWM_CMPDAT3_CMP4_Pos`ÚP
PWM_CMPDAT3_CMP4_MskgÚP
PWM_CMPDAT3_CMP5_Pos_ÚP
PWM_CMPDAT3_CMP5_MskfÚP
PWM_CMPDAT3_CMP6_Pos^ÚP
PWM_CMPDAT3_CMP6_MskeÚP
PWM_CMPDAT3_CMP7_Pos]ÚP
PWM_CMPDAT3_CMP7_MskdÚP
PWM_CMPDAT3_CMPD0_PosÚP
PWM_CMPDAT3_CMPD0_Msk%ÚP
PWM_CMPDAT3_CMPD1_PosÚP
PWM_CMPDAT3_CMPD1_Msk$ÚP
PWM_CMPDAT3_CMPD2_PosÚP
PWM_CMPDAT3_CMPD2_Msk#ÚP
PWM_CMPDAT3_CMPD3_PosÚP
PWM_CMPDAT3_CMPD3_Msk"ÚP
PWM_CMPDAT3_CMPD4_PosÚP
PWM_CMPDAT3_CMPD4_Msk!ÚP
PWM_CMPDAT3_CMPD5_PosÚP
PWM_CMPDAT3_CMPD5_Msk ÚP
PWM_CMPDAT3_CMPD6_PosÚP
PWM_CMPDAT3_CMPD6_MskÚP
PWM_CMPDAT3_CMPD7_PosÚP
PWM_CMPDAT3_CMPD7_MskÚP
PWM_CMPDAT4_CMP0_PoscÚP
PWM_CMPDAT4_CMP0_MskjÚP
PWM_CMPDAT4_CMP1_PosbÚP
PWM_CMPDAT4_CMP1_MskiÚP
PWM_CMPDAT4_CMP2_PosaÚP
PWM_CMPDAT4_CMP2_MskhÚP
PWM_CMPDAT4_CMP3_Pos`ÚP
PWM_CMPDAT4_CMP3_MskgÚP
PWM_CMPDAT4_CMP4_Pos_ÚP
PWM_CMPDAT4_CMP4_MskfÚP
PWM_CMPDAT4_CMP5_Pos^ÚP
PWM_CMPDAT4_CMP5_MskeÚP
PWM_CMPDAT4_CMP6_Pos]ÚP
PWM_CMPDAT4_CMP6_MskdÚP
PWM_CMPDAT4_CMP7_Pos\ÚP
PWM_CMPDAT4_CMP7_MskcÚP
PWM_CMPDAT4_CMPD0_PosÚP
PWM_CMPDAT4_CMPD0_Msk$ÚP
PWM_CMPDAT4_CMPD1_PosÚP
PWM_CMPDAT4_CMPD1_Msk#ÚP
PWM_CMPDAT4_CMPD2_PosÚP
PWM_CMPDAT4_CMPD2_Msk"ÚP
PWM_CMPDAT4_CMPD3_PosÚP
PWM_CMPDAT4_CMPD3_Msk!ÚP
PWM_CMPDAT4_CMPD4_PosÚP
PWM_CMPDAT4_CMPD4_Msk ÚP
PWM_CMPDAT4_CMPD5_PosÚP
PWM_CMPDAT4_CMPD5_MskÚP
PWM_CMPDAT4_CMPD6_PosÚP
PWM_CMPDAT4_CMPD6_MskÚP
PWM_CMPDAT4_CMPD7_PosÚP
PWM_CMPDAT4_CMPD7_MskÚP
PWM_CMPDAT5_CMP0_PosbÚP
PWM_CMPDAT5_CMP0_MskiÚP
PWM_CMPDAT5_CMP1_PosaÚP
PWM_CMPDAT5_CMP1_MskhÚP
PWM_CMPDAT5_CMP2_Pos`ÚP
PWM_CMPDAT5_CMP2_MskgÚP
PWM_CMPDAT5_CMP3_Pos_ÚP
PWM_CMPDAT5_CMP3_MskfÚP
PWM_CMPDAT5_CMP4_Pos^ÚP
PWM_CMPDAT5_CMP4_MskeÚP
PWM_CMPDAT5_CMP5_Pos]ÚP
PWM_CMPDAT5_CMP5_MskdÚP
PWM_CMPDAT5_CMP6_Pos\ÚP
PWM_CMPDAT5_CMP6_MskcÚP
PWM_CMPDAT5_CMP7_Pos[ÚP
PWM_CMPDAT5_CMP7_MskbÚP
PWM_CMPDAT5_CMPD0_PosÚP
PWM_CMPDAT5_CMPD0_Msk#ÚP
PWM_CMPDAT5_CMPD1_PosÚP
PWM_CMPDAT5_CMPD1_Msk"ÚP
PWM_CMPDAT5_CMPD2_PosÚP
PWM_CMPDAT5_CMPD2_Msk!ÚP
PWM_CMPDAT5_CMPD3_PosÚP
PWM_CMPDAT5_CMPD3_Msk ÚP
PWM_CMPDAT5_CMPD4_PosÚP
PWM_CMPDAT5_CMPD4_MskÚP
PWM_CMPDAT5_CMPD5_PosÚP
PWM_CMPDAT5_CMPD5_MskÚP
PWM_CMPDAT5_CMPD6_PosÚP
PWM_CMPDAT5_CMPD6_MskÚP
PWM_CMPDAT5_CMPD7_PosÚP
PWM_CMPDAT5_CMPD7_MskÚP
PWM_CMPDAT6_CMP0_PosaÚP
PWM_CMPDAT6_CMP0_MskhÚP
PWM_CMPDAT6_CMP1_Pos`ÚP
PWM_CMPDAT6_CMP1_MskgÚP
PWM_CMPDAT6_CMP2_Pos_ÚP
PWM_CMPDAT6_CMP2_MskfÚP
PWM_CMPDAT6_CMP3_Pos^ÚP
PWM_CMPDAT6_CMP3_MskeÚP
PWM_CMPDAT6_CMP4_Pos]ÚP
PWM_CMPDAT6_CMP4_MskdÚP
PWM_CMPDAT6_CMP5_Pos\ÚP
PWM_CMPDAT6_CMP5_MskcÚP
PWM_CMPDAT6_CMP6_Pos[ÚP
PWM_CMPDAT6_CMP6_MskbÚP
PWM_CMPDAT6_CMP7_PosZÚP
PWM_CMPDAT6_CMP7_MskaÚP
PWM_CMPDAT6_CMPD0_PosÚP
PWM_CMPDAT6_CMPD0_Msk"ÚP
PWM_CMPDAT6_CMPD1_PosÚP
PWM_CMPDAT6_CMPD1_Msk!ÚP
PWM_CMPDAT6_CMPD2_PosÚP
PWM_CMPDAT6_CMPD2_Msk ÚP
PWM_CMPDAT6_CMPD3_PosÚP
PWM_CMPDAT6_CMPD3_MskÚP
PWM_CMPDAT6_CMPD4_PosÚP
PWM_CMPDAT6_CMPD4_MskÚP
PWM_CMPDAT6_CMPD5_PosÚP
PWM_CMPDAT6_CMPD5_MskÚP
PWM_CMPDAT6_CMPD6_PosÚP
PWM_CMPDAT6_CMPD6_MskÚP
PWM_CMPDAT6_CMPD7_PosÚP
PWM_CMPDAT6_CMPD7_MskÚP
PWM_CMPDAT7_CMP0_Pos`ÚP
PWM_CMPDAT7_CMP0_MskgÚP
PWM_CMPDAT7_CMP1_Pos_ÚP
PWM_CMPDAT7_CMP1_MskfÚP
PWM_CMPDAT7_CMP2_Pos^ÚP
PWM_CMPDAT7_CMP2_MskeÚP
PWM_CMPDAT7_CMP3_Pos]ÚP
PWM_CMPDAT7_CMP3_MskdÚP
PWM_CMPDAT7_CMP4_Pos\ÚP
PWM_CMPDAT7_CMP4_MskcÚP
PWM_CMPDAT7_CMP5_Pos[ÚP
PWM_CMPDAT7_CMP5_MskbÚP
PWM_CMPDAT7_CMP6_PosZÚP
PWM_CMPDAT7_CMP6_MskaÚP
PWM_CMPDAT7_CMP7_PosYÚP
PWM_CMPDAT7_CMP7_Msk`ÚP
PWM_CMPDAT7_CMPD0_PosÚP
PWM_CMPDAT7_CMPD0_Msk!ÚP
PWM_CMPDAT7_CMPD1_PosÚP
PWM_CMPDAT7_CMPD1_Msk ÚP
PWM_CMPDAT7_CMPD2_PosÚP
PWM_CMPDAT7_CMPD2_MskÚP
PWM_CMPDAT7_CMPD3_PosÚP
PWM_CMPDAT7_CMPD3_MskÚP
PWM_CMPDAT7_CMPD4_PosÚP
PWM_CMPDAT7_CMPD4_MskÚP
PWM_CMPDAT7_CMPD5_PosÚP
PWM_CMPDAT7_CMPD5_MskÚP
PWM_CMPDAT7_CMPD6_PosÚP
PWM_CMPDAT7_CMPD6_MskÚP
PWM_CMPDAT7_CMPD7_PosÚP
PWM_CMPDAT7_CMPD7_MskÚP
PWM_CTL2_BRKIEN_Pos’ÚP
PWM_CTL2_BRKIEN_Msk™ÚP
PWM_CTL2_PINTTYPE_PosÌÚP
PWM_CTL2_PINTTYPE_MskÓÚP
PWM_CTL2_DTCNT01_PosmÚP
PWM_CTL2_DTCNT01_MsktÚP
PWM_CTL2_DTCNT23_PosiÚP
PWM_CTL2_DTCNT23_MskpÚP
PWM_CTL2_DTCNT45_PoseÚP
PWM_CTL2_DTCNT45_MsklÚP
PWM_CTL2_DTCNT67_PosaÚP
PWM_CTL2_DTCNT67_MskhÚP
PWM_CTL2_CNTCLR_Pos‡ÚP
PWM_CTL2_CNTCLR_MskŽÚP
PWM_CTL2_MODE_Pos,ÚP
PWM_CTL2_MODE_Msk3ÚP
PWM_CTL2_GROUPEN_Pos+ÚP
PWM_CTL2_GROUPEN_Msk2ÚP
PWM_CTL2_CNTTYPE_Pos$ÚP
PWM_CTL2_CNTTYPE_Msk+ÚP
PWM_FLAG_ZF0_Pos~ÚP
PWM_FLAG_ZF0_Msk…ÚP
PWM_FLAG_ZF1_Pos}ÚP
PWM_FLAG_ZF1_Msk„ÚP
PWM_FLAG_ZF2_Pos|ÚP
PWM_FLAG_ZF2_MskƒÚP
PWM_FLAG_ZF3_Pos{ÚP
PWM_FLAG_ZF3_Msk‚ÚP
PWM_FLAG_ZF4_PoszÚP
PWM_FLAG_ZF4_MskÚP
PWM_FLAG_ZF5_PosyÚP
PWM_FLAG_ZF5_Msk€ÚP
PWM_FLAG_ZF6_PosxÚP
PWM_FLAG_ZF6_MskÚP
PWM_FLAG_ZF7_PoswÚP
PWM_FLAG_ZF7_Msk~ÚP
PWM_FLAG_CMPDF0_Pos®ÚP
PWM_FLAG_CMPDF0_MskµÚP
PWM_FLAG_CMPDF1_Pos­ÚP
PWM_FLAG_CMPDF1_Msk´ÚP
PWM_FLAG_CMPDF2_Pos¬ÚP
PWM_FLAG_CMPDF2_Msk³ÚP
PWM_FLAG_CMPDF3_Pos«ÚP
PWM_FLAG_CMPDF3_Msk²ÚP
PWM_FLAG_CMPDF4_PosªÚP
PWM_FLAG_CMPDF4_Msk±ÚP
PWM_FLAG_CMPDF5_Pos©ÚP
PWM_FLAG_CMPDF5_Msk°ÚP
PWM_FLAG_CMPDF6_Pos¨ÚP
PWM_FLAG_CMPDF6_Msk¯ÚP
PWM_FLAG_CMPDF7_Pos§ÚP
PWM_FLAG_CMPDF7_Msk®ÚP
PWM_FLAG_PF0_PosˆÚP
PWM_FLAG_PF0_MskÚP
PWM_FLAG_PF1_Pos‡ÚP
PWM_FLAG_PF1_MskŽÚP
PWM_FLAG_PF2_Pos†ÚP
PWM_FLAG_PF2_MskÚP
PWM_FLAG_PF3_Pos…ÚP
PWM_FLAG_PF3_MskŒÚP
PWM_FLAG_PF4_Pos„ÚP
PWM_FLAG_PF4_Msk‹ÚP
PWM_FLAG_PF5_PosƒÚP
PWM_FLAG_PF5_MskŠÚP
PWM_FLAG_PF6_Pos‚ÚP
PWM_FLAG_PF6_Msk‰ÚP
PWM_FLAG_PF7_PosÚP
PWM_FLAG_PF7_MskˆÚP
PWM_FLAG_CMPUF0_PosÚP
PWM_FLAG_CMPUF0_Msk¤ÚP
PWM_FLAG_CMPUF1_PosœÚP
PWM_FLAG_CMPUF1_Msk£ÚP
PWM_FLAG_CMPUF2_Pos›ÚP
PWM_FLAG_CMPUF2_Msk¢ÚP
PWM_FLAG_CMPUF3_PosšÚP
PWM_FLAG_CMPUF3_Msk¡ÚP
PWM_FLAG_CMPUF4_Pos™ÚP
PWM_FLAG_CMPUF4_Msk ÚP
PWM_FLAG_CMPUF5_Pos˜ÚP
PWM_FLAG_CMPUF5_MskŸÚP
PWM_FLAG_CMPUF6_Pos—ÚP
PWM_FLAG_CMPUF6_MskžÚP
PWM_FLAG_CMPUF7_Pos–ÚP
PWM_FLAG_CMPUF7_MskÚP
PWM_INTEN_ZIEN0_Pos~ÚP
PWM_INTEN_ZIEN0_Msk…ÚP
PWM_INTEN_ZIEN1_Pos}ÚP
PWM_INTEN_ZIEN1_Msk„ÚP
PWM_INTEN_ZIEN2_Pos|ÚP
PWM_INTEN_ZIEN2_MskƒÚP
PWM_INTEN_ZIEN3_Pos{ÚP
PWM_INTEN_ZIEN3_Msk‚ÚP
PWM_INTEN_ZIEN4_PoszÚP
PWM_INTEN_ZIEN4_MskÚP
PWM_INTEN_ZIEN5_PosyÚP
PWM_INTEN_ZIEN5_Msk€ÚP
PWM_INTEN_ZIEN6_PosxÚP
PWM_INTEN_ZIEN6_MskÚP
PWM_INTEN_ZIEN7_PoswÚP
PWM_INTEN_ZIEN7_Msk~ÚP
PWM_INTEN_CMPDIEN0_Pos®ÚP
PWM_INTEN_CMPDIEN0_MskµÚP
PWM_INTEN_CMPDIEN1_Pos­ÚP
PWM_INTEN_CMPDIEN1_Msk´ÚP
PWM_INTEN_CMPDIEN2_Pos¬ÚP
PWM_INTEN_CMPDIEN2_Msk³ÚP
PWM_INTEN_CMPDIEN3_Pos«ÚP
PWM_INTEN_CMPDIEN3_Msk²ÚP
PWM_INTEN_CMPDIEN4_PosªÚP
PWM_INTEN_CMPDIEN4_Msk±ÚP
PWM_INTEN_CMPDIEN5_Pos©ÚP
PWM_INTEN_CMPDIEN5_Msk°ÚP
PWM_INTEN_CMPDIEN6_Pos¨ÚP
PWM_INTEN_CMPDIEN6_Msk¯ÚP
PWM_INTEN_CMPDIEN7_Pos§ÚP
PWM_INTEN_CMPDIEN7_Msk®ÚP
PWM_INTEN_PIEN0_PosˆÚP
PWM_INTEN_PIEN0_MskÚP
PWM_INTEN_PIEN1_Pos‡ÚP
PWM_INTEN_PIEN1_MskŽÚP
PWM_INTEN_PIEN2_Pos†ÚP
PWM_INTEN_PIEN2_MskÚP
PWM_INTEN_PIEN3_Pos…ÚP
PWM_INTEN_PIEN3_MskŒÚP
PWM_INTEN_PIEN4_Pos„ÚP
PWM_INTEN_PIEN4_Msk‹ÚP
PWM_INTEN_PIEN5_PosƒÚP
PWM_INTEN_PIEN5_MskŠÚP
PWM_INTEN_PIEN6_Pos‚ÚP
PWM_INTEN_PIEN6_Msk‰ÚP
PWM_INTEN_PIEN7_PosÚP
PWM_INTEN_PIEN7_MskˆÚP
PWM_INTEN_CMPUIEN0_PosÚP
PWM_INTEN_CMPUIEN0_Msk¤ÚP
PWM_INTEN_CMPUIEN1_PosœÚP
PWM_INTEN_CMPUIEN1_Msk£ÚP
PWM_INTEN_CMPUIEN2_Pos›ÚP
PWM_INTEN_CMPUIEN2_Msk¢ÚP
PWM_INTEN_CMPUIEN3_PosšÚP
PWM_INTEN_CMPUIEN3_Msk¡ÚP
PWM_INTEN_CMPUIEN4_Pos™ÚP
PWM_INTEN_CMPUIEN4_Msk ÚP
PWM_INTEN_CMPUIEN5_Pos˜ÚP
PWM_INTEN_CMPUIEN5_MskŸÚP
PWM_INTEN_CMPUIEN6_Pos—ÚP
PWM_INTEN_CMPUIEN6_MskžÚP
PWM_INTEN_CMPUIEN7_Pos–ÚP
PWM_INTEN_CMPUIEN7_MskÚP
PWM_INTSTS_ZIF0_PosdÚP
PWM_INTSTS_ZIF0_MskkÚP
PWM_INTSTS_ZIF1_PoscÚP
PWM_INTSTS_ZIF1_MskjÚP
PWM_INTSTS_ZIF2_PosbÚP
PWM_INTSTS_ZIF2_MskiÚP
PWM_INTSTS_ZIF3_PosaÚP
PWM_INTSTS_ZIF3_MskhÚP
PWM_INTSTS_ZIF4_Pos`ÚP
PWM_INTSTS_ZIF4_MskgÚP
PWM_INTSTS_ZIF5_Pos_ÚP
PWM_INTSTS_ZIF5_MskfÚP
PWM_INTSTS_ZIF6_Pos^ÚP
PWM_INTSTS_ZIF6_MskeÚP
PWM_INTSTS_ZIF7_Pos]ÚP
PWM_INTSTS_ZIF7_MskdÚP
PWM_INTSTS_CMPDIF0_Pos”ÚP
PWM_INTSTS_CMPDIF0_Msk›ÚP
PWM_INTSTS_CMPDIF1_Pos“ÚP
PWM_INTSTS_CMPDIF1_MskšÚP
PWM_INTSTS_CMPDIF2_Pos’ÚP
PWM_INTSTS_CMPDIF2_Msk™ÚP
PWM_INTSTS_CMPDIF3_Pos‘ÚP
PWM_INTSTS_CMPDIF3_Msk˜ÚP
PWM_INTSTS_CMPDIF4_PosÚP
PWM_INTSTS_CMPDIF4_Msk—ÚP
PWM_INTSTS_CMPDIF5_PosÚP
PWM_INTSTS_CMPDIF5_Msk–ÚP
PWM_INTSTS_CMPDIF6_PosŽÚP
PWM_INTSTS_CMPDIF6_Msk•ÚP
PWM_INTSTS_CMPDIF7_PosÚP
PWM_INTSTS_CMPDIF7_Msk”ÚP
PWM_INTSTS_PIF0_PosnÚP
PWM_INTSTS_PIF0_MskuÚP
PWM_INTSTS_PIF1_PosmÚP
PWM_INTSTS_PIF1_MsktÚP
PWM_INTSTS_PIF2_PoslÚP
PWM_INTSTS_PIF2_MsksÚP
PWM_INTSTS_PIF3_PoskÚP
PWM_INTSTS_PIF3_MskrÚP
PWM_INTSTS_PIF4_PosjÚP
PWM_INTSTS_PIF4_MskqÚP
PWM_INTSTS_PIF5_PosiÚP
PWM_INTSTS_PIF5_MskpÚP
PWM_INTSTS_PIF6_PoshÚP
PWM_INTSTS_PIF6_MskoÚP
PWM_INTSTS_PIF7_PosgÚP
PWM_INTSTS_PIF7_MsknÚP
PWM_INTSTS_CMPUIF0_PosƒÚP
PWM_INTSTS_CMPUIF0_MskŠÚP
PWM_INTSTS_CMPUIF1_Pos‚ÚP
PWM_INTSTS_CMPUIF1_Msk‰ÚP
PWM_INTSTS_CMPUIF2_PosÚP
PWM_INTSTS_CMPUIF2_MskˆÚP
PWM_INTSTS_CMPUIF3_Pos€ÚP
PWM_INTSTS_CMPUIF3_Msk‡ÚP
PWM_INTSTS_CMPUIF4_PosÚP
PWM_INTSTS_CMPUIF4_Msk†ÚP
PWM_INTSTS_CMPUIF5_Pos~ÚP
PWM_INTSTS_CMPUIF5_Msk…ÚP
PWM_INTSTS_CMPUIF6_Pos}ÚP
PWM_INTSTS_CMPUIF6_Msk„ÚP
PWM_INTSTS_CMPUIF7_Pos|ÚP
PWM_INTSTS_CMPUIF7_MskƒÚP
PWM_POEN_POEN0_PosÐÚP
PWM_POEN_POEN0_Msk×ÚP
PWM_POEN_POEN1_PosÏÚP
PWM_POEN_POEN1_MskÖÚP
PWM_POEN_POEN2_PosÎÚP
PWM_POEN_POEN2_MskÕÚP
PWM_POEN_POEN3_PosÍÚP
PWM_POEN_POEN3_MskÔÚP
PWM_POEN_POEN4_PosÌÚP
PWM_POEN_POEN4_MskÓÚP
PWM_POEN_POEN5_PosËÚP
PWM_POEN_POEN5_MskÒÚP
PWM_POEN_POEN6_PosÊÚP
PWM_POEN_POEN6_MskÑÚP
PWM_POEN_POEN7_PosÉÚP
PWM_POEN_POEN7_MskÐÚP
PWM_BRKCTL_BRK0EN_PosúÚP
PWM_BRKCTL_BRK0EN_Msk
ÚP
PWM_BRKCTL_BRK1EN_PosùÚP
PWM_BRKCTL_BRK1EN_MskÚP
PWM_BRKCTL_BRK0SEL_Pos§ÚP
PWM_BRKCTL_BRK0SEL_Msk®ÚP
PWM_BRKCTL_BRK1SEL_Pos¦ÚP
PWM_BRKCTL_BRK1SEL_Msk­ÚP
PWM_BRKCTL_BRKSTS_PosÃÚP
PWM_BRKCTL_BRKSTS_MskÊÚP
PWM_BRKCTL_BRKACT_PosåÚP
PWM_BRKCTL_BRKACT_MskìÚP
PWM_BRKCTL_SWBRK_PosÚP
PWM_BRKCTL_SWBRK_MskÚP
PWM_BRKCTL_BRKIF0_PosþÚP
PWM_BRKCTL_BRKIF0_MskÚP
PWM_BRKCTL_BRKIF1_PosýÚP
PWM_BRKCTL_BRKIF1_MskÚP
PWM_BRKCTL_BRKF0_PosIÚP
PWM_BRKCTL_BRKF0_MskPÚP
PWM_BRKCTL_BRKF1_PosHÚP
PWM_BRKCTL_BRKF1_MskOÚP
PWM_BRKCTL_BKOD0_PosNÚP
PWM_BRKCTL_BKOD0_MskUÚP
PWM_BRKCTL_BKOD1_PosMÚP
PWM_BRKCTL_BKOD1_MskTÚP
PWM_BRKCTL_BKOD2_PosLÚP
PWM_BRKCTL_BKOD2_MskSÚP
PWM_BRKCTL_BKOD3_PosKÚP
PWM_BRKCTL_BKOD3_MskRÚP
PWM_BRKCTL_BKOD4_PosJÚP
PWM_BRKCTL_BKOD4_MskQÚP
PWM_BRKCTL_BKOD5_PosIÚP
PWM_BRKCTL_BKOD5_MskPÚP
PWM_BRKCTL_D6BKOD_PosÚP
PWM_BRKCTL_D6BKOD_Msk    ÚP
PWM_BRKCTL_D7BKOD_Pos
ÚP
PWM_BRKCTL_D7BKOD_MskÚP
PWM_DTCTL_DTI01_Pos¥ÚP
PWM_DTCTL_DTI01_Msk¬ÚP
PWM_DTCTL_DTI23_Pos¡ÚP
PWM_DTCTL_DTI23_Msk¨ÚP
PWM_DTCTL_DTI45_PosÚP
PWM_DTCTL_DTI45_Msk¤ÚP
PWM_DTCTL_DTI67_Pos™ÚP
PWM_DTCTL_DTI67_Msk Ú"P
PWM_ADCTCTL0_CUTRGEN0_PosßÚ"P
PWM_ADCTCTL0_CUTRGEN0_MskæÚ"P
PWM_ADCTCTL0_CPTRGEN0_PosäÚ"P
PWM_ADCTCTL0_CPTRGEN0_MskëÚ"P
PWM_ADCTCTL0_CDTRGEN0_PosðÚ"P
PWM_ADCTCTL0_CDTRGEN0_Msk÷Ú"P
PWM_ADCTCTL0_ZPTRGEN0_PosÍÚ"P
PWM_ADCTCTL0_ZPTRGEN0_MskÔÚ"P
PWM_ADCTCTL0_CUTRGEN1_PosÞÚ"P
PWM_ADCTCTL0_CUTRGEN1_MskåÚ"P
PWM_ADCTCTL0_CPTRGEN1_PosãÚ"P
PWM_ADCTCTL0_CPTRGEN1_MskêÚ"P
PWM_ADCTCTL0_CDTRGEN1_PosïÚ"P
PWM_ADCTCTL0_CDTRGEN1_MsköÚ"P
PWM_ADCTCTL0_ZPTRGEN1_PosÌÚ"P
PWM_ADCTCTL0_ZPTRGEN1_MskÓÚ"P
PWM_ADCTCTL0_CUTRGEN2_PosÝÚ"P
PWM_ADCTCTL0_CUTRGEN2_MskäÚ"P
PWM_ADCTCTL0_CPTRGEN2_PosâÚ"P
PWM_ADCTCTL0_CPTRGEN2_MskéÚ"P
PWM_ADCTCTL0_CDTRGEN2_PosîÚ"P
PWM_ADCTCTL0_CDTRGEN2_MskõÚ"P
PWM_ADCTCTL0_ZPTRGEN2_PosËÚ"P
PWM_ADCTCTL0_ZPTRGEN2_MskÒÚ"P
PWM_ADCTCTL0_CUTRGEN3_PosÜÚ"P
PWM_ADCTCTL0_CUTRGEN3_MskãÚ"P
PWM_ADCTCTL0_CPTRGEN3_PosáÚ"P
PWM_ADCTCTL0_CPTRGEN3_MskèÚ"P
PWM_ADCTCTL0_CDTRGEN3_PosíÚ"P
PWM_ADCTCTL0_CDTRGEN3_MskôÚ"P
PWM_ADCTCTL0_ZPTRGEN3_PosÊÚ"P
PWM_ADCTCTL0_ZPTRGEN3_MskÑÚ"P
PWM_ADCTCTL1_CUTRGEN4_PosÚÚ"P
PWM_ADCTCTL1_CUTRGEN4_MskáÚ"P
PWM_ADCTCTL1_CPTRGEN4_PosßÚ"P
PWM_ADCTCTL1_CPTRGEN4_MskæÚ"P
PWM_ADCTCTL1_CDTRGEN4_PosëÚ"P
PWM_ADCTCTL1_CDTRGEN4_MskòÚ"P
PWM_ADCTCTL1_ZPTRGEN4_PosÈÚ"P
PWM_ADCTCTL1_ZPTRGEN4_MskÏÚ"P
PWM_ADCTCTL1_CUTRGEN5_PosÙÚ"P
PWM_ADCTCTL1_CUTRGEN5_MskàÚ"P
PWM_ADCTCTL1_CPTRGEN5_PosÞÚ"P
PWM_ADCTCTL1_CPTRGEN5_MskåÚ"P
PWM_ADCTCTL1_CDTRGEN5_PosêÚ"P
PWM_ADCTCTL1_CDTRGEN5_MskñÚ"P
PWM_ADCTCTL1_ZPTRGEN5_PosÇÚ"P
PWM_ADCTCTL1_ZPTRGEN5_MskÎÚ"P
PWM_ADCTCTL1_CUTRGEN6_PosØÚ"P
PWM_ADCTCTL1_CUTRGEN6_MskßÚ"P
PWM_ADCTCTL1_CPTRGEN6_PosÝÚ"P
PWM_ADCTCTL1_CPTRGEN6_MskäÚ"P
PWM_ADCTCTL1_CDTRGEN6_PoséÚ"P
PWM_ADCTCTL1_CDTRGEN6_MskðÚ"P
PWM_ADCTCTL1_ZPTRGEN6_PosÆÚ"P
PWM_ADCTCTL1_ZPTRGEN6_MskÍÚ"P
PWM_ADCTCTL1_CUTRGEN7_Pos×Ú"P
PWM_ADCTCTL1_CUTRGEN7_MskÞÚ"P
PWM_ADCTCTL1_CPTRGEN7_PosÜÚ"P
PWM_ADCTCTL1_CPTRGEN7_MskãÚ"P
PWM_ADCTCTL1_CDTRGEN7_PosèÚ"P
PWM_ADCTCTL1_CDTRGEN7_MskïÚ"P
PWM_ADCTCTL1_ZPTRGEN7_PosÅÚ"P
PWM_ADCTCTL1_ZPTRGEN7_MskÌÚ!P
PWM_ADCTSTS0_CUTRGF0_PosÚ!P
PWM_ADCTSTS0_CUTRGF0_MskÚ!P
PWM_ADCTSTS0_CPTRGF0_PosÚ!P
PWM_ADCTSTS0_CPTRGF0_Msk#Ú!P
PWM_ADCTSTS0_CDTRGF0_Pos(Ú!P
PWM_ADCTSTS0_CDTRGF0_Msk/Ú!P
PWM_ADCTSTS0_ZPTRGF0_PosÚ!P
PWM_ADCTSTS0_ZPTRGF0_MskÚ!P
PWM_ADCTSTS0_CUTRGF1_PosÚ!P
PWM_ADCTSTS0_CUTRGF1_MskÚ!P
PWM_ADCTSTS0_CPTRGF1_PosÚ!P
PWM_ADCTSTS0_CPTRGF1_Msk"Ú!P
PWM_ADCTSTS0_CDTRGF1_Pos'Ú!P
PWM_ADCTSTS0_CDTRGF1_Msk.Ú!P
PWM_ADCTSTS0_ZPTRGF1_PosÚ!P
PWM_ADCTSTS0_ZPTRGF1_MskÚ!P
PWM_ADCTSTS0_CUTRGF2_PosÚ!P
PWM_ADCTSTS0_CUTRGF2_MskÚ!P
PWM_ADCTSTS0_CPTRGF2_PosÚ!P
PWM_ADCTSTS0_CPTRGF2_Msk!Ú!P
PWM_ADCTSTS0_CDTRGF2_Pos&Ú!P
PWM_ADCTSTS0_CDTRGF2_Msk-Ú!P
PWM_ADCTSTS0_ZPTRGF2_PosÚ!P
PWM_ADCTSTS0_ZPTRGF2_Msk
Ú!P
PWM_ADCTSTS0_CUTRGF3_PosÚ!P
PWM_ADCTSTS0_CUTRGF3_MskÚ!P
PWM_ADCTSTS0_CPTRGF3_PosÚ!P
PWM_ADCTSTS0_CPTRGF3_Msk Ú!P
PWM_ADCTSTS0_CDTRGF3_Pos%Ú!P
PWM_ADCTSTS0_CDTRGF3_Msk,Ú!P
PWM_ADCTSTS0_ZPTRGF3_PosÚ!P
PWM_ADCTSTS0_ZPTRGF3_Msk    Ú!P
PWM_ADCTSTS1_CUTRGF4_PosÚ!P
PWM_ADCTSTS1_CUTRGF4_MskÚ!P
PWM_ADCTSTS1_CPTRGF4_PosÚ!P
PWM_ADCTSTS1_CPTRGF4_MskÚ!P
PWM_ADCTSTS1_CDTRGF4_Pos#Ú!P
PWM_ADCTSTS1_CDTRGF4_Msk*Ú!P
PWM_ADCTSTS1_ZPTRGF4_PosÚ!P
PWM_ADCTSTS1_ZPTRGF4_MskÚ!P
PWM_ADCTSTS1_CUTRGF5_PosÚ!P
PWM_ADCTSTS1_CUTRGF5_MskÚ!P
PWM_ADCTSTS1_CPTRGF5_PosÚ!P
PWM_ADCTSTS1_CPTRGF5_MskÚ!P
PWM_ADCTSTS1_CDTRGF5_Pos"Ú!P
PWM_ADCTSTS1_CDTRGF5_Msk)Ú!P
PWM_ADCTSTS1_ZPTRGF5_PosÿÚ!P
PWM_ADCTSTS1_ZPTRGF5_MskÚ!P
PWM_ADCTSTS1_CUTRGF6_PosÚ!P
PWM_ADCTSTS1_CUTRGF6_MskÚ!P
PWM_ADCTSTS1_CPTRGF6_PosÚ!P
PWM_ADCTSTS1_CPTRGF6_MskÚ!P
PWM_ADCTSTS1_CDTRGF6_Pos!Ú!P
PWM_ADCTSTS1_CDTRGF6_Msk(Ú!P
PWM_ADCTSTS1_ZPTRGF6_PosþÚ!P
PWM_ADCTSTS1_ZPTRGF6_MskÚ!P
PWM_ADCTSTS1_CUTRGF7_PosÚ!P
PWM_ADCTSTS1_CUTRGF7_MskÚ!P
PWM_ADCTSTS1_CPTRGF7_PosÚ!P
PWM_ADCTSTS1_CPTRGF7_MskÚ!P
PWM_ADCTSTS1_CDTRGF7_Pos Ú!P
PWM_ADCTSTS1_CDTRGF7_Msk'Ú!P
PWM_ADCTSTS1_ZPTRGF7_PosýÚ!P
PWM_ADCTSTS1_ZPTRGF7_MskÚP
PWM_PCACTL_PCAEN_PosBÚP
PWM_PCACTL_PCAEN_MskIÚ8

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›    X_FL_CTLyÚ "

›
X_FL_TRIG+Ú "

›X_FL_CONFIG§Ú <"
›X_FL_WDÚ 
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›X_FL_X_MODEzÚ "

›X_FL_X2_CMD Ú "

›X_FL_X4_CMDžÚ "

›X_FL_DP_CMD–Ú "

› X_FL_RDP_CMDBÚ 
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›X_FL_REMAP_ADDR_Ú 
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›X_FL_DP_CTL€Ú 
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› X_FL_IRQ_CTL&Ú 
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›X_FL_SUS_RESU_CMD~Ú
FLCTL_TËÚ8

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€ªX_FL_BUFFERÜÚ
FLCTL_W_BUFF_T…Ú"P
FLCTL_CTL_BYTES_NUM_R_PoskÚ"P
FLCTL_CTL_BYTES_NUM_R_MskrÚ"P
FLCTL_CTL_BYTES_NUM_W_PosfÚ"P
FLCTL_CTL_BYTES_NUM_W_MskmÚP
FLCTL_TRIG_TRG_PosÀÚP
FLCTL_TRIG_TRG_MskÇÚ#P
FLCTL_CONFIG_FLASH_CAP_Pos|Ú#P
FLCTL_CONFIG_FLASH_CAP_MskƒÚ'P
FLCTL_CONFIG_TX_ADDR_TRANS_PosÚ'P
FLCTL_CONFIG_TX_ADDR_TRANS_MskÚ!P
FLCTL_CONFIG_INFO_EN_PosÚ!P
FLCTL_CONFIG_INFO_EN_Msk
Ú#P
FLCTL_CONFIG_PP_ACTIVE_PosbÚ#P
FLCTL_CONFIG_PP_ACTIVE_MskiÚP
FLCTL_W_DATA_PosvÚP
FLCTL_W_DATA_Msk}Ú%P
FLCTL_X_MODE_TIMEOUT_CNT_PosˆÚ%P
FLCTL_X_MODE_TIMEOUT_CNT_MskÚ#P
FLCTL_X_MODE_RESUME_EN_Pos4Ú#P
FLCTL_X_MODE_RESUME_EN_Msk;Ú%P
FLCTL_X_MODE_SUS_SUCCESS_Pos€Ú%P
FLCTL_X_MODE_SUS_SUCCESS_Msk‡Ú!P
FLCTL_X_MODE_CLK_DLY_PosÙÚ!P
FLCTL_X_MODE_CLK_DLY_MskàÚ P
FLCTL_X_MODE_RX_NEG_PosÚ P
FLCTL_X_MODE_RX_NEG_Msk!Ú"P
FLCTL_X_MODE_CRC32_EN_PosÊÚ"P
FLCTL_X_MODE_CRC32_EN_MskÑÚ&P
FLCTL_X_MODE_ENHANCE_MODE_Pos{Ú&P
FLCTL_X_MODE_ENHANCE_MODE_Msk‚Ú&P
FLCTL_X_MODE_LONG_TIME_OP_Pos5Ú&P
FLCTL_X_MODE_LONG_TIME_OP_Msk<Ú'P
FLCTL_X_MODE_EN_BURST_WRAP_PosÔÚ'P
FLCTL_X_MODE_EN_BURST_WRAP_MskÛÚ'P
FLCTL_X_MODE_CS_IDLE_CYCLE_Pos Ú'P
FLCTL_X_MODE_CS_IDLE_CYCLE_MskÚ P
FLCTL_X_MODE_X_MODE_Pos!Ú P
FLCTL_X_MODE_X_MODE_Msk(ÚP
FLCTL_X2_CMD_Pos‰ÚP
FLCTL_X2_CMD_MskÚP
FLCTL_X4_CMD_Pos‡ÚP
FLCTL_X4_CMD_MskŽÚP
FLCTL_DP_CMD_PosÚP
FLCTL_DP_CMD_Msk†ÚP
FLCTL_RDP_CMD_Pos+ÚP
FLCTL_RDP_CMD_Msk2ÚP
FLCTL_REMAP_ADDR_PosOÚP
FLCTL_REMAP_ADDR_MskVÚ$P
FLCTL_DP_CTL_RDP_WT_CNT_PosÇÚ$P
FLCTL_DP_CTL_RDP_WT_CNT_MskÎÚ#P
FLCTL_DP_CTL_DP_WT_CNT_PosÚ#P
FLCTL_DP_CTL_DP_WT_CNT_Msk"ÚP
FLCTL_DP_CTL_DP_EN_PosÚP
FLCTL_DP_CTL_DP_EN_Msk†Ú"P
FLCTL_PROGRAM_SUS_CMD_PosÚ"P
FLCTL_PROGRAM_SUS_CMD_Msk–Ú%P
FLCTL_PROGRAM_RESUME_CMD_Pos³Ú%P
FLCTL_PROGRAM_RESUME_CMD_MskºÚ P
FLCTL_ERASE_SUS_CMD_Pos;Ú P
FLCTL_ERASE_SUS_CMD_MskBÚ#P
FLCTL_ERASE_RESUME_CMD_Pos_Ú#P
FLCTL_ERASE_RESUME_CMD_MskfÚ8

<unnamed>QÚ 
"
ëX_CACHE_EN³Ú 
"
ëX_RESVRmÚ 
"
ëX_CACHE_INIdÚ 
CR_T±Ú8

<unnamed>QÚ 
"
ðCR0ôÚ 
"
ðCR1óÚ  
"
ðDR%Ú  
"
ðSRÚ 
"
ðCPSRÚ 
"
ðIMSC‹Ú 
"
ðRISËÚ 
"
ðMISÐÚ 
"
ðICRÛÚ 
"
ðDMACRNÚ
SPI_TXÚP
SPI_CR0_SCR_PosÅÚP
SPI_CR0_SCR_MskÌÚP
SPI_CR0_SPH_PosÂÚP
SPI_CR0_SPH_MskÉÚP
SPI_CR0_SPO_Pos»ÚP
SPI_CR0_SPO_MskÂÚP
SPI_CR0_FRF_PosÏÚP
SPI_CR0_FRF_MskÖÚP
SPI_CR0_DSS_PosÃÚP
SPI_CR0_DSS_MskÊÚ!P
SPI_CR1_SPI_MODE_SEL_PosçÚ!P
SPI_CR1_SPI_MODE_SEL_MskîÚP
SPI_CR1_CMD_DAT_EN_Pos ÚP
SPI_CR1_CMD_DAT_EN_Msk§Ú!P
SPI_CR1_CMD_DAT_CTRL_PosúÚ!P
SPI_CR1_CMD_DAT_CTRL_Msk
ÚP
SPI_CR1_WR_CTRL_PosgÚP
SPI_CR1_WR_CTRL_MsknÚP
SPI_CR1_RX_LSB_EN_PosÄÚP
SPI_CR1_RX_LSB_EN_MskËÚP
SPI_CR1_TX_LSB_EN_PosÂÚP
SPI_CR1_TX_LSB_EN_MskÉÚP
SPI_CR1_SOD_PosÆÚP
SPI_CR1_SOD_MskÍÚP
SPI_CR1_MS_PosÚP
SPI_CR1_MS_MskÚP
SPI_CR1_SSE_PosÁÚP
SPI_CR1_SSE_MskÈÚP
SPI_CR1_LBM_PosÑÚP
SPI_CR1_LBM_MskØÚP
SPI_DR_PosEÚP
SPI_DR_MskLÚP
SPI_SR_BUSY_PosŠÚP
SPI_SR_BUSY_Msk‘ÚP
SPI_SR_RFF_PosñÚP
SPI_SR_RFF_MskøÚP
SPI_SR_RFNE_Pos¢ÚP
SPI_SR_RFNE_Msk©ÚP
SPI_SR_TFNF_PosŸÚP
SPI_SR_TFNF_Msk¦ÚP
SPI_SR_TFE_PosðÚP
SPI_SR_TFE_Msk÷ÚP
SPI_CPSR_DIV_PosUÚP
SPI_CPSR_DIV_Msk\ÚP
SPI_IMSC_TXIM_PosÚP
SPI_IMSC_TXIM_MskÚP
SPI_IMSC_RXIM_PosÚP
SPI_IMSC_RXIM_Msk    ÚP
SPI_IMSC_RTIM_PosÚP
SPI_IMSC_RTIM_Msk ÚP
SPI_RIS_TXIS_Pos:ÚP
SPI_RIS_TXIS_MskAÚP
SPI_RIS_RXIS_Pos<ÚP
SPI_RIS_RXIS_MskCÚP
SPI_RIS_RTIS_Pos@ÚP
SPI_RIS_RTIS_MskGÚP
SPI_RIS_RORIS_PosñÚP
SPI_RIS_RORIS_MskøÚP
SPI_MIS_TXMIS_PosðÚP
SPI_MIS_TXMIS_Msk÷ÚP
SPI_MIS_RXMIS_PosòÚP
SPI_MIS_RXMIS_MskùÚP
SPI_MIS_RTMIS_PosöÚP
SPI_MIS_RTMIS_MskýÚP
SPI_MIS_RORMIS_Pos§ÚP
SPI_MIS_RORMIS_Msk®ÚP
SPI_ICR_RTICR_PosÚP
SPI_ICR_RTICR_MskÚP
SPI_ICR_RORICR_Pos½ÚP
SPI_ICR_RORICR_MskÄÚP
SPI_DMACR_TDMAE_Pos˜ÚP
SPI_DMACR_TDMAE_MskŸÚP
SPI_DMACR_RDMAE_PosšÚP
SPI_DMACR_RDMAE_Msk¡Ú8

<unnamed>QÚ 
"
ÆRBR_THR_DLLdÚ 
"
ÆIER_DLHÃÚ 
"
ÆIIR_FCR¼Ú 
"
ÆLCR
Ú 
"
ÆMCRÚ 
"
ÆLSRñÚ 
"
ÆMSRðÚ 
"
ÆSCRúÚ 
"
ÆLPDLLfÚ 
"
ÆLPDLHjÚ <"
TÆ
RESERVED0ÄÚ 
"
ÆUSRèÚ 
"
ÆTFLüÚ 
"
ÆRFLþÚ <"
Æ
RESERVED1ûÚ 
"
ÆHTXîÚ 
"
ÆDMASAxÚ <"
Æ
RESERVED2Ú 
"
ÆDLFÚ 
"
ÆRARýÚ 
"
ÆTARûÚ 
"
ÆLCR_EXT©Ú
UART_TÚP
UART_RBR_MSB9_PosÚP
UART_RBR_MSB9_Msk$ÚP
UART_RBR_DAT_PosaÚP
UART_RBR_DAT_MskhÚP
UART_THR_MSB9_PosÚP
UART_THR_MSB9_MskÚP
UART_THR_DAT_PosYÚP
UART_THR_DAT_Msk`ÚP
 UART_DLH_Pos¯ÚP
 UART_DLH_Msk¶ÚP
 UART_DLL_Pos«ÚP
 UART_DLL_Msk²ÚP
UART_IER_EPTI_PosÚP
UART_IER_EPTI_MskÚP
UART_IER_EMSI_PosÚP
UART_IER_EMSI_MskÚP
UART_IER_ERLSI_Pos½ÚP
UART_IER_ERLSI_MskÄÚP
UART_IER_ETHREI_PosyÚP
UART_IER_ETHREI_Msk€ÚP
UART_IER_ERDAI_Pos×ÚP
UART_IER_ERDAI_MskÞÚP
UART_IER_ALL_IRQ_PosÚP
UART_IER_ALL_IRQ_MskÚP
UART_IIR_FIFOSE_PoszÚP
UART_IIR_FIFOSE_MskÚP
UART_IIR_IID_PosfÚP
UART_IIR_IID_MskmÚP
UART_FCR_RT_Pos¡ÚP
UART_FCR_RT_Msk¨ÚP
UART_FCR_TET_PosXÚP
UART_FCR_TET_Msk_ÚP
UART_FCR_DMAM_Pos$ÚP
UART_FCR_DMAM_Msk+ÚP
UART_FCR_XFIFOR_PosqÚP
UART_FCR_XFIFOR_MskxÚP
UART_FCR_RFIFOR_PoswÚP
UART_FCR_RFIFOR_Msk~ÚP
UART_FCR_FIFOE_PosØÚP
UART_FCR_FIFOE_MskßÚP
UART_LCR_DLAB_Pos*ÚP
UART_LCR_DLAB_Msk1ÚP
UART_LCR_BC_Pos¼ÚP
UART_LCR_BC_MskÃÚP
UART_LCR_SP_PosžÚP
UART_LCR_SP_Msk¥ÚP
UART_LCR_EPS_PosWÚP
UART_LCR_EPS_Msk^ÚP
UART_LCR_PEN_Pos\ÚP
UART_LCR_PEN_MskcÚP
UART_LCR_STOP_Pos÷ÚP
UART_LCR_STOP_MskþÚP
UART_LCR_DLS_Pos\ÚP
UART_LCR_DLS_MskcÚP
UART_MCR_SIRE_Pos    ÚP
UART_MCR_SIRE_MskÚP
UART_MCR_AFCE_Pos-ÚP
UART_MCR_AFCE_Msk4ÚP
UART_MCR_LB_Pos²ÚP
UART_MCR_LB_Msk¹ÚP
UART_MCR_OUT2_PosÚP
UART_MCR_OUT2_MskÚP
UART_MCR_OUT1_PosÚP
UART_MCR_OUT1_MskÚP
UART_MCR_RTS_PosEÚP
UART_MCR_RTS_MskLÚP
UART_MCR_DTR_PosTÚP
UART_MCR_DTR_Msk[ÚP
UART_LSR_ADDR_RCVD_PoszÚP
UART_LSR_ADDR_RCVD_MskÚP
UART_LSR_RFE_PosRÚP
UART_LSR_RFE_MskYÚP
UART_LSR_TEMT_PosóÚP
UART_LSR_TEMT_MskúÚP
UART_LSR_THRE_PosúÚP
UART_LSR_THRE_Msk
ÚP
UART_LSR_BI_Pos¦ÚP
UART_LSR_BI_Msk­ÚP
UART_LSR_FE_Pos¦ÚP
UART_LSR_FE_Msk­ÚP
UART_LSR_PE_PosœÚP
UART_LSR_PE_Msk£ÚP
UART_LSR_OE_PosÚP
UART_LSR_OE_Msk¤ÚP
UART_LSR_DR_Pos›ÚP
UART_LSR_DR_Msk¢Ú!P
UART_LSR_LINE_STATUS_Pos´Ú!P
UART_LSR_LINE_STATUS_Msk»ÚP
UART_MSR_DCD_PoscÚP
UART_MSR_DCD_MskjÚP
UART_MSR_RI_Pos•ÚP
UART_MSR_RI_MskœÚP
UART_MSR_DSR_PosEÚP
UART_MSR_DSR_MskLÚP
UART_MSR_CTS_PosDÚP
UART_MSR_CTS_MskKÚP
UART_MSR_DDCD_PosÚP
UART_MSR_DDCD_Msk$ÚP
UART_MSR_TERI_PosøÚP
UART_MSR_TERI_MskÿÚP
UART_MSR_DDSR_PosÿÚP
UART_MSR_DDSR_MskÚP
UART_MSR_DCTS_PosþÚP
UART_MSR_DCTS_MskÚ"P
UART_MSR_MODEM_STATUS_PosgÚ"P
UART_MSR_MODEM_STATUS_MsknÚP
 UART_SCR_PosŸÚP
 UART_SCR_Msk¦ÚP
UART_LPDLL_PosÚP
UART_LPDLL_MskÚP
UART_LPDLH_PosÚP
UART_LPDLH_MskÚP
UART_USR_RFF_PosHÚP
UART_USR_RFF_MskOÚP
UART_USR_RFNE_PosùÚP
UART_USR_RFNE_MskÚP
UART_USR_TFE_PosGÚP
UART_USR_TFE_MskNÚP
UART_USR_TFNF_PosöÚP
UART_USR_TFNF_MskýÚP
 UART_TFL_Pos¡ÚP
 UART_TFL_Msk¨ÚP
 UART_RFL_Pos£ÚP
 UART_RFL_MskªÚP
UART_DMASA_PosÚP
UART_DMASA_Msk$ÚP
 UART_DLF_Pos±ÚP
 UART_DLF_Msk¸ÚP
 UART_RAR_Pos¢ÚP
 UART_RAR_Msk©ÚP
 UART_TAR_Pos ÚP
 UART_TAR_Msk§Ú'P
UART_LCR_EXT_TRANSMIT_MODE_PosÝÚ'P
UART_LCR_EXT_TRANSMIT_MODE_MskäÚ#P
UART_LCR_EXT_SEND_ADDR_Pos7Ú#P
UART_LCR_EXT_SEND_ADDR_Msk>Ú$P
UART_LCR_EXT_ADDR_MATCH_PosòÚ$P
UART_LCR_EXT_ADDR_MATCH_MskùÚP
UART_LCR_EXT_DLS_E_Pos\ÚP
UART_LCR_EXT_DLS_E_MskcÚP
UART_DR_OE“ÚP
UART_DR_BE ÚP
UART_DR_PE’ÚP
UART_DR_FEœÚP
 UART_DR_DATA    ÚP
 UART_RSCR_OEëÚP
 UART_RSCR_BEøÚP
 UART_RSCR_PEêÚP
 UART_RSCR_FEôÚP
UART_RSCR_CLR_ERRLÚP
UART_STATUS_RI6ÚP
UART_STATUS_TXFE–ÚP
UART_STATUS_RXFF—ÚP
UART_STATUS_TXFF•ÚP
UART_STATUS_RXFE˜ÚP
UART_STATUS_BUSYŠÚP
UART_STATUS_DCDÚP
UART_STATUS_DSRæÚP
UART_STATUS_CTSåÚP
UART_IRDA_LP_DIV³ÚP
UART_BRD_IBRD¾ÚP
UART_BRD_FBRDÁÚP
UART_LC_CLEAR_MSKoÚP
UART_LC_SPS6ÚP
 UART_LC_WLENôÚP
UART_LC_FENSÚP
 UART_LC_STP2
ÚP
UART_LC_EPSDÚP
UART_LC_PENIÚP
UART_LC_BRKMÚP
UART_CR_CLEAR_MSKiÚP
UART_CR_CTSEN¥ÚP
UART_CR_RTSEN–ÚP
 UART_CR_OUT2úÚP
 UART_CR_OUT1ûÚP
UART_CR_RTS-ÚP
UART_CR_DTR<ÚP
UART_CR_RXE7ÚP
UART_CR_TXE5ÚP
UART_CR_LBESÚP
UART_CR_SIRLP˜ÚP
UART_CR_SIREN¡ÚP
UART_CR_UARTENQÚP
UART_INT_FIFO_RXIFLSELÎÚP
UART_INT_FIFO_TXIFLSELÌÚP
UART_INT_MSK_OEIMPÚP
UART_INT_MSK_BEIM]ÚP
UART_INT_MSK_PEIMOÚP
UART_INT_MSK_FEIMYÚP
UART_INT_MSK_RTIM>ÚP
UART_INT_MSK_TXIM8ÚP
UART_INT_MSK_RXIM:ÚP
UART_INT_MSK_DSRMIMªÚP
UART_INT_MSK_DCDMIMÈÚP
UART_INT_MSK_CTSMIM©ÚP
UART_INT_MSK_RIMIMúÚP
UART_RAW_INT_MSK_OEIMÿÚP
UART_RAW_INT_MSK_BEIMÚP
UART_RAW_INT_MSK_PEIMþÚP
UART_RAW_INT_MSK_FEIMÚP
UART_RAW_INT_MSK_RTIMíÚP
UART_RAW_INT_MSK_TXIMçÚP
UART_RAW_INT_MSK_RXIMéÚ P
UART_RAW_INT_MSK_DSRMIMYÚ P
UART_RAW_INT_MSK_DCDMIMwÚ P
UART_RAW_INT_MSK_CTSMIMXÚP
UART_RAW_INT_MSK_RIMIM©Ú"P
UART_MASKED_INT_STAT_OEIMÛÚ"P
UART_MASKED_INT_STAT_BEIMèÚ"P
UART_MASKED_INT_STAT_PEIMÚÚ"P
UART_MASKED_INT_STAT_FEIMäÚ"P
UART_MASKED_INT_STAT_RTIMÉÚ"P
UART_MASKED_INT_STAT_TXIMÃÚ"P
UART_MASKED_INT_STAT_RXIMÅÚ$P
UART_MASKED_INT_STAT_DSRMIM5Ú$P
UART_MASKED_INT_STAT_DCDMIMSÚ$P
UART_MASKED_INT_STAT_CTSMIM4Ú#P
UART_MASKED_INT_STAT_RIMIM…ÚP
UART_CLR_INT_OEIMZÚP
UART_CLR_INT_BEIMgÚP
UART_CLR_INT_PEIMYÚP
UART_CLR_INT_FEIMcÚP
UART_CLR_INT_RTIMHÚP
UART_CLR_INT_TXIMBÚP
UART_CLR_INT_RXIMDÚP
UART_CLR_INT_DSRMIM´ÚP
UART_CLR_INT_DCDMIMÒÚP
UART_CLR_INT_CTSMIM³ÚP
UART_CLR_INT_RIMIMÚP
UART_DMA_CR_DMAONERR‹ÚP
UART_DMA_CR_TXDMAE$ÚP
UART_DMA_CR_RXDMAE&Ú8

<unnamed>QÚ8

<unnamed>QÚ 
"
ÇSAR_LJÚ 
"
ÇSAR_HNÚ 
"
ÇDAR_LYÚ 
"
ÇDAR_H]Ú <"
Ç
RESERVED0 Ú 
"
ÇCTL_LMÚ 
"
ÇCTL_HQÚ <"
 Ç
RESERVED1ôÚ 
"
ÇCFG_L`Ú 
"
ÇCFG_HdÚ 
"
ÇSGR_LDÚ 
"
ÇSGR_HHÚ 
"
ÇDSR_LGÚ 
"
ÇDSR_HKÚ <"
ÀÆCHcÚ 
"
Æ
RAW_TFR_LôÚ 
"
Æ
RAW_TFR_HøÚ 
"
ÆRAW_BLOCK_LqÚ 
"
ÆRAW_BLOCK_HuÚ 
"
ÆRAW_SRCTRAN_L»Ú 
"
ÆRAW_SRCTRAN_H¿Ú 
"
ÆRAW_DSTTRAN_L¸Ú 
"
ÆRAW_DSTTRAN_H¼Ú 
"
Æ
RAW_ERR_L÷Ú 
"
Æ
RAW_ERR_HûÚ 
"
Æ STATUS_TFR_LôÚ 
"
Æ STATUS_TFR_HøÚ 
"
ÆSTATUS_BLOCK_LqÚ 
"
ÆSTATUS_BLOCK_HuÚ 
"
ÆSTATUS_SRCTRAN_L»Ú 
"
ÆSTATUS_SRCTRAN_H¿Ú 
"
ÆSTATUS_DSTTRAN_L¸Ú 
"
ÆSTATUS_DSTTRAN_H¼Ú 
"
Æ STATUS_ERR_L÷Ú 
"
Æ STATUS_ERR_HûÚ 
"
Æ
MSK_TFR_LóÚ 
"
Æ
MSK_TFR_H÷Ú 
"
ÆMSK_BLOCK_LpÚ 
"
ÆMSK_BLOCK_HtÚ 
"
ÆMSK_SRCTRAN_LºÚ 
"
ÆMSK_SRCTRAN_H¾Ú 
"
ÆMSK_DSTTRAN_L·Ú 
"
ÆMSK_DSTTRAN_H»Ú 
"
Æ
MSK_ERR_LöÚ 
"
Æ
MSK_ERR_HúÚ 
"
ÆCLEAR_TFR_LsÚ 
"
ÆCLEAR_TFR_HwÚ 
"
ÆCLEAR_BLOCK_LðÚ 
"
ÆCLEAR_BLOCK_HôÚ 
"
ÆCLEAR_SRCTRAN_L:Ú 
"
ÆCLEAR_SRCTRAN_H>Ú 
"
ÆCLEAR_DSTTRAN_L7Ú 
"
ÆCLEAR_DSTTRAN_H;Ú 
"
ÆCLEAR_ERR_LvÚ 
"
ÆCLEAR_ERR_HzÚ 
"
Æ STATUS_INT_LõÚ 
"
Æ STATUS_INT_HùÚ <"
0Æ
RESERVED3ãÚ 
"
ÆDMA_CFG_REG_LãÚ 
"
ÆDMA_CFG_REG_HçÚ 
"
ÆCH_EN_REG_LkÚ 
"
ÆCH_EN_REG_HoÚ
DMA_TrÚ$P
DMAC_DMACFGREG_L_DMA_EN_PosBÚ$P
DMAC_DMACFGREG_L_DMA_EN_MskIÚ!P
DMAC_CHENREG_L_CH_EN_PosÚ!P
DMAC_CHENREG_L_CH_EN_MskÚ%P
DMAC_CHENREG_L_CH_EN_ALL_PosÓÚ%P
DMAC_CHENREG_L_CH_EN_ALL_MskÚÚ$P
DMAC_CHENREG_L_CH_EN_WE_PosÚ$P
DMAC_CHENREG_L_CH_EN_WE_MskÚ(P
 DMAC_CHENREG_L_CH_EN_WE_ALL_PosÒÚ(P
 DMAC_CHENREG_L_CH_EN_WE_ALL_MskÙÚP
DMAC_SAR_L_SAR_PosÌÚP
DMAC_SAR_L_SAR_MskÓÚP
DMAC_DAR_L_DAR_PosêÚP
DMAC_DAR_L_DAR_MskñÚP
DMAC_CTL_L_INT_EN_PosÒÚP
DMAC_CTL_L_INT_EN_MskÙÚ$P
DMAC_CTL_L_DST_TR_WIDTH_PosÔÚ$P
DMAC_CTL_L_DST_TR_WIDTH_MskÛÚ$P
DMAC_CTL_L_SRC_TR_WIDTH_Pos×Ú$P
DMAC_CTL_L_SRC_TR_WIDTH_MskÞÚP
DMAC_CTL_L_DINC_Pos•ÚP
DMAC_CTL_L_DINC_MskœÚP
DMAC_CTL_L_SINC_Pos†ÚP
DMAC_CTL_L_SINC_MskÚ"P
DMAC_CTL_L_DEST_MSIZE_PosÚ"P
DMAC_CTL_L_DEST_MSIZE_Msk—Ú!P
DMAC_CTL_L_SRC_MSIZE_PosÚÚ!P
DMAC_CTL_L_SRC_MSIZE_MskáÚP
DMAC_CTL_L_TT_FC_Pos!ÚP
DMAC_CTL_L_TT_FC_Msk(Ú P
DMAC_CTL_H_BLOCK_TS_Pos>Ú P
DMAC_CTL_H_BLOCK_TS_MskEÚP
DMAC_CTL_H_DONE_Pos‘ÚP
DMAC_CTL_H_DONE_Msk˜Ú P
DMAC_CFG_L_CH_PRIOR_PosHÚ P
DMAC_CFG_L_CH_PRIOR_MskOÚP
DMAC_CFG_L_CH_SUSP_Pos‹ÚP
DMAC_CFG_L_CH_SUSP_Msk’Ú"P
DMAC_CFG_L_FIFO_EMPTY_Pos¨Ú"P
DMAC_CFG_L_FIFO_EMPTY_Msk¯Ú"P
DMAC_CFG_L_HS_SEL_DST_Pos’Ú"P
DMAC_CFG_L_HS_SEL_DST_Msk™Ú"P
DMAC_CFG_L_HS_SEL_SRC_Pos•Ú"P
DMAC_CFG_L_HS_SEL_SRC_MskœÚ"P
DMAC_CFG_L_DST_HS_POL_Pos‹Ú"P
DMAC_CFG_L_DST_HS_POL_Msk’Ú"P
DMAC_CFG_L_SRC_HS_POL_PosŽÚ"P
DMAC_CFG_L_SRC_HS_POL_Msk•ÚP
DMAC_CFG_H_FCMODE_PosÚP
DMAC_CFG_H_FCMODE_MskÚ!P
DMAC_CFG_H_FIFO_MODE_PosÚ!P
DMAC_CFG_H_FIFO_MODE_MskÚP
DMAC_CFG_H_PROTCTL_PosœÚP
DMAC_CFG_H_PROTCTL_Msk£ÚP
DMAC_CFG_H_SRC_PER_Pos–ÚP
DMAC_CFG_H_SRC_PER_MskÚ P
DMAC_CFG_H_DEST_PER_PosLÚ P
DMAC_CFG_H_DEST_PER_MskSÚ"P
DMAC_INT_RAW_STAT_CLR_Pos…Ú"P
DMAC_INT_RAW_STAT_CLR_MskŒÚ&P
DMAC_INT_RAW_STAT_CLR_ALL_PosEÚ&P
DMAC_INT_RAW_STAT_CLR_ALL_MskLÚP
DMAC_INT_MASK_L_PosÚP
DMAC_INT_MASK_L_Msk†Ú P
DMAC_INT_MASK_L_ALL_Pos?Ú P
DMAC_INT_MASK_L_ALL_MskFÚP
DMAC_INT_MASK_L_WE_Pos~ÚP
DMAC_INT_MASK_L_WE_Msk…Ú#P
DMAC_INT_MASK_L_WE_ALL_Pos>Ú#P
DMAC_INT_MASK_L_WE_ALL_MskEÚ!P
DMAC_STATUSINT_L_TFR_PosÑÚ!P
DMAC_STATUSINT_L_TFR_MskØÚ#P
DMAC_STATUSINT_L_BLOCK_PosNÚ#P
DMAC_STATUSINT_L_BLOCK_MskUÚ%P
DMAC_STATUSINT_L_SRCTRAN_Pos˜Ú%P
DMAC_STATUSINT_L_SRCTRAN_MskŸÚ%P
DMAC_STATUSINT_L_DSTTRAN_Pos•Ú%P
DMAC_STATUSINT_L_DSTTRAN_MskœÚ!P
DMAC_STATUSINT_L_ERR_PosÔÚ!P
DMAC_STATUSINT_L_ERR_MskÛÚ8

<unnamed>QÚ 
"
×CONîÚ 
"
×TARçÚ 
"
×SARèÚ 
"
×    HS_MADDRbÚ 
"
×DATACMDØÚ 
"
×SS_SCL_HCNTKÚ 
"
×SS_SCL_LCNTGÚ 
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×FS_SCL_HCNTXÚ 
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×FS_SCL_LCNTTÚ 
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×HS_SCL_HCNTVÚ 
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×HS_SCL_LCNTRÚ 
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×
INTR_STATêÚ 
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×
INTR_MASKúÚ 
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×RAW_INTR_STAT™Ú 
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×RX_TL!Ú 
"
×TX_TLÚ 
"
×    CLR_INTRGÚ 
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×CLR_RX_UNDÚ 
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×CLR_RX_OVR€Ú 
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×CLR_TX_OVR~Ú 
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×CLR_RD_REQ£Ú 
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×CLR_TX_ABRTJÚ 
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×CLR_RX_DONEOÚ 
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× CLR_ACTIVITYÚ 
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× CLR_STOP_DETúÚ 
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×CLR_START_DET°Ú 
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× CLR_GEN_CALL'Ú 
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×
IC_ENABLE0Ú 
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×STATUSäÚ 
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×TXFLR:Ú 
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×RXFLR<Ú 
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×    SDA_HOLDfÚ 
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×TX_ABRT_SRCCÚ 
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×SLV_DATA_NACKÐÚ 
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×DMA_CRÚ 
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×    DMA_TDLR]Ú 
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×    DMA_RDLR_Ú 
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×
SDA_SETUPúÚ 
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×ACK_GENERAL_CALL Ú 
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×ENABLE_STATUSÐÚ 
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×
FS_SPKLENýÚ 
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×
HS_SPKLENûÚ 
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×CLR_RESTART_DETÚ
I2C_T†ÚP
I2C_CON_MASTER_MODEùÚP
I2C_CON_SPEEDäÚP
I2C_CON_SPEED_0QÚP
I2C_CON_SPEED_1PÚ#P
I2C_CON_IC_10BITADDR_SLAVEÚ$P
I2C_CON_IC_10BITADDR_MASTERÈÚP
I2C_CON_IC_RESTART_ENCÚ!P
I2C_CON_IC_SLAVE_DISABLE†Ú%P
I2C_CON_STOP_DET_IFADDRESSED8ÚP
I2C_CON_TX_EMPTY_CTRLÚP
I2C_TAR_TARkÚP
I2C_TAR_IC_TAR_0çÚP
I2C_TAR_IC_TAR_1æÚP
I2C_TAR_IC_TAR_2åÚP
I2C_TAR_IC_TAR_3äÚP
I2C_TAR_IC_TAR_4ãÚP
I2C_TAR_IC_TAR_5âÚP
I2C_TAR_IC_TAR_6áÚP
I2C_TAR_IC_TAR_7àÚP
I2C_TAR_IC_TAR_8ßÚP
I2C_TAR_IC_TAR_9ÞÚP
I2C_TAR_GC_OR_STARTËÚP
I2C_TAR_SPECIALIÚ$P
I2C_TAR_IC_10BITADDR_MASTERÁÚP
I2C_SAR_IC_SAR|ÚP
I2C_HS_MADDR_IC_HS_MARüÚP
I2C_DATA_CMD_DAT    ÚP
I2C_DATA_CMD_CMD_RYÚP
I2C_DATA_CMD_STOPšÚP
I2C_DATA_CMD_RESTARTµÚP
I2C_SS_SCL_HCNTÚP
I2C_SS_SCL_LCNTÚP
I2C_FS_SCL_HCNT*ÚP
I2C_FS_SCL_LCNT&ÚP
I2C_HS_SCL_HCNT(ÚP
I2C_HS_SCL_LCNT$Ú!P
I2C_INTR_STAT_R_RX_UNDERÚ P
I2C_INTR_STAT_R_RX_OVERSÚ P
I2C_INTR_STAT_R_RX_FULL\Ú P
I2C_INTR_STAT_R_TX_OVERQÚ!P
I2C_INTR_STAT_R_TX_EMPTYüÚP
I2C_INTR_STAT_R_RD_REQ½Ú P
I2C_INTR_STAT_R_TX_ABRTdÚ P
I2C_INTR_STAT_R_RX_DONEiÚ!P
I2C_INTR_STAT_R_ACTIVITY)Ú!P
I2C_INTR_STAT_R_STOP_DETÚ"P
I2C_INTR_STAT_R_START_DETÊÚ!P
I2C_INTR_STAT_R_GEN_CALLAÚ$P
I2C_INTR_STAT_R_RESTART_DET/Ú$P
I2C_INTR_STAT_R_MST_ON_HOLDÚ!P
I2C_INTR_MASK_M_RX_UNDER$Ú P
I2C_INTR_MASK_M_RX_OVERhÚ P
I2C_INTR_MASK_M_RX_FULLqÚ P
I2C_INTR_MASK_M_TX_OVERfÚ!P
I2C_INTR_MASK_M_TX_EMPTYÚP
I2C_INTR_MASK_M_RD_REQÒÚ P
I2C_INTR_MASK_M_TX_ABRTyÚ P
I2C_INTR_MASK_M_RX_DONE~Ú!P
I2C_INTR_MASK_M_ACTIVITY>Ú!P
I2C_INTR_MASK_M_STOP_DET)Ú"P
I2C_INTR_MASK_M_START_DETßÚ!P
I2C_INTR_MASK_M_GEN_CALLVÚ$P
I2C_INTR_MASK_M_RESTART_DETDÚ$P
I2C_INTR_MASK_M_MST_ON_HOLD/Ú#P
I2C_RAW_INTR_STAT_RX_UNDERsÚ"P
I2C_RAW_INTR_STAT_RX_OVER·Ú"P
I2C_RAW_INTR_STAT_RX_FULLÀÚ"P
I2C_RAW_INTR_STAT_TX_OVERµÚ#P
I2C_RAW_INTR_STAT_TX_EMPTY`Ú!P
I2C_RAW_INTR_STAT_RD_REQ!Ú"P
I2C_RAW_INTR_STAT_TX_ABRTÈÚ"P
I2C_RAW_INTR_STAT_RX_DONEÍÚ#P
I2C_RAW_INTR_STAT_ACTIVITYÚ#P
I2C_RAW_INTR_STAT_STOP_DETxÚ$P
I2C_RAW_INTR_STAT_START_DET.Ú#P
I2C_RAW_INTR_STAT_GEN_CALL¥Ú&P
I2C_RAW_INTR_STAT_RESTART_DET“Ú&P
I2C_RAW_INTR_STAT_MST_ON_HOLD~ÚP

I2C_RX_TLóÚP

I2C_TX_TLñÚP
 I2C_CLR_INTRÚP
I2C_CLR_RX_UNDERÇÚP
I2C_CLR_TX_OVER    ÚP
I2C_CLR_RD_REQuÚP
I2C_CLR_TX_ABORTËÚP
I2C_CLR_RX_DONE!ÚP
I2C_CLR_ACTIVITYáÚP
I2C_CLR_STOP_DETÌÚP
I2C_CLR_START_DET‚ÚP
I2C_CLR_GEN_CALLùÚP
I2C_CLR_RESTART_DETçÚP
I2C_CLR_MST_ON_HOLDÒÚP
I2C_ENABLE_ENABLEßÚP
I2C_ENABLE_ABORTÚP
I2C_STATUS_ACTIVITYØÚP
I2C_STATUS_TFNFÚP
I2C_STATUS_TFEpÚP
I2C_STATUS_RFNE"ÚP
I2C_STATUS_RFErÚ P
I2C_STATUS_MST_ACTIVITY}Ú P
I2C_STATUS_SLV_ACTIVITY|ÚP

I2C_TXFLRÚP

I2C_RXFLRÚP
 I2C_SDA_HOLD8Ú)P
!I2C_TX_ABRT_SOURCE_7B_ADDR_NOACKíÚ)P
!I2C_TX_ABRT_SOURCE_10ADDR1_NOACK3Ú)P
!I2C_TX_ABRT_SOURCE_10ADDR2_NOACK2Ú(P
 I2C_TX_ABRT_SOURCE_TXDATA_NOACKÚ'P
I2C_TX_ABRT_SOURCE_GCALL_NOACKÚ&P
I2C_TX_ABRT_SOURCE_GCALL_READÓÚ%P
I2C_TX_ABRT_SOURCE_HS_ACKDET Ú(P
 I2C_TX_ABRT_SOURCE_SBYTE_ACKDETÚ&P
I2C_TX_ABRT_SOURCE_HS_NORSTRT{Ú)P
!I2C_TX_ABRT_SOURCE_SBYTE_NORSTRT‰Ú*P
"I2C_TX_ABRT_SOURCE_10B_RD_NORSTRTvÚ&P
I2C_TX_ABRT_SOURCE_MASTER_DIS¦Ú$P
I2C_TX_ABRT_SOURCE_ARB_LOST?Ú+P
#I2C_TX_ABRT_SOURCE_SLVFLUSH_TXFIFO
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I2C_TX_ABRT_SOURCE_SLV_ARBLOSTDÚ&P
I2C_TX_ABRT_SOURCE_SLVRD_INTX„Ú%P
I2C_TX_ABRT_SOURCE_USER_ABRTìÚ(P
 I2C_TX_ABRT_SOURCE_TX_FLUSH_CNTÜÚP
I2C_SLV_DATA_NACK_ONLY÷ÚP
I2C_DMA_CR_RDMAEÚP
I2C_DMA_CR_TDMAEþÚP
 I2C_DMA_TDLR/ÚP
 I2C_DMA_RDLR1ÚP
I2C_SDA_SETUPÌÚP
I2C_ACK_GENERAL_CALLßÚ P
I2C_ENABLE_STATUS_IC_EN¹Ú)P
!I2C_ENABLE_STATUS_SLV_RX_ABORTEDÇÚ6P
.I2C_ENABLE_STATUS_SLV_FIFO_FILLED_AND_FLUSHEDèÚP
I2C_FS_SPKLENÏÚP
I2C_HS_SPKLENÍÚ'P
I2C_COMP_PARAM1_APB_DATA_WIDTH¸Ú'P
I2C_COMP_PARAM1_MAX_SPEED_MODE©Ú(P
 I2C_COMP_PARAM1_HC_COUNT_VALUES?Ú P
I2C_COMP_PARAM1_INTR_IO½Ú P
I2C_COMP_PARAM1_HAS_DMAäÚ+P
#I2C_COMP_PARAM1_ADD_ENCODED_PARAMSžÚ(P
 I2C_COMP_PARAM1_RX_BUFFER_DEPTHJÚ(P
 I2C_COMP_PARAM1_TX_BUFFER_DEPTHHÚP
I2C_COMP_VERSIONÚÚP
I2C_COMP_TYPEÄÚ8

<unnamed>QÚ 
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” LP_REG_SYNCŠÚ 
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” LP_FL_CTRL_3VòÚ 
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” LP_SPACING_TIME07Ú 
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” LP_SPACING_TIME16Ú 
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” LP_SPACING_TIME25Ú 
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” 
LP_SLPTMR&Ú 
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” LP_INT_CTRL…Ú 
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” LP_DLY_CTRL_3V™Ú 
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”  LP_PTAT_POLY&Ú 
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” 
LP_HP_LDO2Ú 
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”  LP_LP_LDO_3V@Ú 
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” LP_ANA_LDOøÚ 
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” LP_FSYN_LDO†Ú 
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” LP_SWfÚ 
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” LP_BUCK_3VùÚ 
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” ANA_ADC_LDOÊÚ 
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”  ANA_RFFE_LDOmÚ 
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” ANA_VCO_LDOªÚ 
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” ANA_DFTúÚ 
"
” ANA_MISC_3V¼Ú 
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” ANA_RESERVED_3V€Ú 
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”  ACT_32K_CTRL‚Ú 
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” ACT_32K_BASECORR^Ú 
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” CPU_ADDR_REMAP_CTRL%Ú 
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” RCL_HW_CAL_CTRLUÚ
ANA_TtÚ P
ANAC_LP_REG_SYNC_3V_Pos=Ú P
ANAC_LP_REG_SYNC_3V_MskDÚ$P
ANAC_LP_REG_SYNC_3V_TRG_PoséÚ$P
ANAC_LP_REG_SYNC_3V_TRG_MskðÚ#P
ANAC_FL_SLEEP_MODE_SEL_PoscÚ#P
ANAC_FL_SLEEP_MODE_SEL_MskjÚ&P
ANAC_FL_EXT_WAKEUP_SEL_Pos_3v5Ú&P
ANAC_FL_EXT_WAKEUP_SEL_Msk_3v<Ú!P
ANAC_FL_SLEEP_CNT_EN_PosøÚ!P
ANAC_FL_SLEEP_CNT_EN_MskÿÚ%P
ANAC_FL_CPU_RETENTION_EN_Pos®Ú%P
ANAC_FL_CPU_RETENTION_EN_MskµÚ#P
ANAC_FL_LDO_ISOLATE_EN_PosbÚ#P
ANAC_FL_LDO_ISOLATE_EN_MskiÚ P
ANAC_FL_RCL_GATE_EN_PosVÚ P
ANAC_FL_RCL_GATE_EN_Msk]ÚP
ANAC_FL_PWR_CTL_EN_Pos~ÚP
ANAC_FL_PWR_CTL_EN_Msk…Ú P
ANAC_FL_FLASH_BP_EN_PosXÚ P
ANAC_FL_FLASH_BP_EN_Msk_Ú P
ANAC_FL_FLASH_LP_EN_PosNÚ P
ANAC_FL_FLASH_LP_EN_MskUÚP
ANAC_FL_BUCK_BP_EN_Pos£ÚP
ANAC_FL_BUCK_BP_EN_MskªÚP
ANAC_FL_BUCK_EN_PosšÚP
ANAC_FL_BUCK_EN_Msk¡ÚP
ANAC_FL_DPLL_EN_Pos“ÚP
ANAC_FL_DPLL_EN_MskšÚP
ANAC_FL_RCH_EN_PosäÚP
ANAC_FL_RCH_EN_MskëÚP
ANAC_FL_XTH_EN_PosÍÚP
ANAC_FL_XTH_EN_MskÔÚ"P
ANAC_FL_XTAL32K_EN_Pos_3vÂÚ"P
ANAC_FL_XTAL32K_EN_Msk_3vÉÚ P
ANAC_FL_RC32K_EN_Pos_3vjÚ P
ANAC_FL_RC32K_EN_Msk_3vqÚP
ANAC_FL_LDO_HP_EN_PosåÚP
ANAC_FL_LDO_HP_EN_MskìÚP
ANAC_FL_PMU_EN_PosÏÚP
ANAC_FL_PMU_EN_MskÖÚ!P
ANAC_SRAM0_POWER_CTL_PosÚ!P
ANAC_SRAM0_POWER_CTL_MskÚ!P
ANAC_SRAM1_POWER_CTL_PosÚ!P
ANAC_SRAM1_POWER_CTL_Msk ÚP
ANAC_CPU_POWER_CTL_Pos†ÚP
ANAC_CPU_POWER_CTL_MskÚP
ANAC_PHY_POWER_CTL_Pos}ÚP
ANAC_PHY_POWER_CTL_Msk„Ú#P
ANAC_LL_SRAM_POWER_CTL_Pos<Ú#P
ANAC_LL_SRAM_POWER_CTL_MskCÚ!P
ANAC_FLASH_POWER_CTL_PosüÚ!P
ANAC_FLASH_POWER_CTL_MskÚP
ANAC_LDO_POWER_CTL_PosÚP
ANAC_LDO_POWER_CTL_Msk–Ú P
ANAC_LDOL_POWER_CTL_PosAÚ P
ANAC_LDOL_POWER_CTL_MskHÚP
ANAC_INT_LP_INT_EN_PoszÚP
ANAC_INT_LP_INT_EN_MskÚP
ANAC_INT_DP_FLAG_PosIÚP
ANAC_INT_DP_FLAG_MskPÚ%P
ANAC_INT_STANDBY_M1_FLAG_PosÛÚ%P
ANAC_INT_STANDBY_M1_FLAG_MskâÚ%P
ANAC_INT_STANDBY_M0_FLAG_PosÜÚ%P
ANAC_INT_STANDBY_M0_FLAG_MskãÚ#P
ANAC_INT_SRAM_RET_FLAG_PosTÚ#P
ANAC_INT_SRAM_RET_FLAG_Msk[Ú&P
ANAC_INT_SLEEP_TMR_INT_EN_Pos=Ú&P
ANAC_INT_SLEEP_TMR_INT_EN_MskDÚ P
ANAC_INT_SLEEP_TMR0_PosUÚ P
ANAC_INT_SLEEP_TMR0_Msk\Ú P
ANAC_INT_SLEEP_TMR1_PosTÚ P
ANAC_INT_SLEEP_TMR1_Msk[Ú P
ANAC_INT_SLEEP_TMR2_PosSÚ P
ANAC_INT_SLEEP_TMR2_MskZÚ%P
ANAC_INT_SLEEP_TMR_WK_EN_PosˆÚ%P
ANAC_INT_SLEEP_TMR_WK_EN_MskÚ!P
ANAC_32KCLK_DLY_TIME_Pos8Ú!P
ANAC_32KCLK_DLY_TIME_Msk?ÚP
ANAC_32KCLK_DLY_EN_PosØÚP
ANAC_32KCLK_DLY_EN_MskßÚ"P
ANAC_HPLDO_RDY_BYPASS_Pos Ú"P
ANAC_HPLDO_RDY_BYPASS_Msk§Ú$P
ANAC_LPLDOH_DLY_TIME_Pos_3vñÚ$P
ANAC_LPLDOH_DLY_TIME_Msk_3vøÚP
ANAC_PTAT_CORE_EN_PosëÚP
ANAC_PTAT_CORE_EN_MskòÚP
ANAC_PTAT_TMP_TRIM_PosxÚP
ANAC_PTAT_TMP_TRIM_MskÚP
ANAC_PTAT_TRIM_PosÐÚP
ANAC_PTAT_TRIM_Msk×Ú#P
ANAC_PTAT_FLT_SHIFT_EN_PosGÚ#P
ANAC_PTAT_FLT_SHIFT_EN_MskNÚ!P
ANAC_PTAT_FLT_ACT_EN_PosñÚ!P
ANAC_PTAT_FLT_ACT_EN_MskøÚP
ANAC_POLY_EN_PosrÚP
ANAC_POLY_EN_MskyÚP
ANAC_IPOLY_TRIM_PoszÚP
ANAC_IPOLY_TRIM_MskÚP
ANAC_HPLDO_EN_Pos=ÚP
ANAC_HPLDO_EN_MskDÚP
ANAC_HPLDO_BYPASS_PosöÚP
ANAC_HPLDO_BYPASS_MskýÚP
ANAC_HPLDO_TRIM_PosÚP
ANAC_HPLDO_TRIM_Msk—ÚP
ANAC_HPLDO_SEL_PosêÚP
ANAC_HPLDO_SEL_MskñÚ&P
ANAC_HPLDO_FLASHLDO_BP_Pos_3vrÚ&P
ANAC_HPLDO_FLASHLDO_BP_Msk_3vyÚ&P
ANAC_HPLDO_FLASHLDO_EN_Pos_3vqÚ&P
ANAC_HPLDO_FLASHLDO_EN_Msk_3vxÚ&P
ANAC_HPLDO_FLASHLDO_LP_EN_Pos~Ú&P
ANAC_HPLDO_FLASHLDO_LP_EN_Msk…Ú(P
 ANAC_HPLDO_FLASHLDO_CAP_SEL_PosñÚ(P
 ANAC_HPLDO_FLASHLDO_CAP_SEL_MskøÚ%P
ANAC_HPLDO_FLASHLDO_TRIM_PosÒÚ%P
ANAC_HPLDO_FLASHLDO_TRIM_MskÙÚP
ANAC_LPLDO_L_EN_PosŠÚP
ANAC_LPLDO_L_EN_Msk‘Ú"P
ANAC_LPLDO_L_DVDD_SEL_Pos¬Ú"P
ANAC_LPLDO_L_DVDD_SEL_Msk³ÚP
ANAC_LPLDO_H_EN_Pos_3v€ÚP
ANAC_LPLDO_H_EN_Msk_3v‡Ú%P
ANAC_LPLDO_H_DVDD_SEL_Pos_3v¢Ú%P
ANAC_LPLDO_H_DVDD_SEL_Msk_3v©Ú%P
ANAC_LPLDO_H_REF_TRIM_Pos_3vÚ%P
ANAC_LPLDO_H_REF_TRIM_Msk_3v–Ú%P
ANAC_LPLDO_H_MODE_SEL_Pos_3vŸÚ%P
ANAC_LPLDO_H_MODE_SEL_Msk_3v¦ÚP
ANAC_ANA_LDO_EN_Pos¢ÚP
ANAC_ANA_LDO_EN_Msk©ÚP
ANAC_ANA_LDO_TRIM_PosõÚP
ANAC_ANA_LDO_TRIM_MsküÚP
ANAC_FSYN_LDO_EN_Pos0ÚP
ANAC_FSYN_LDO_EN_Msk7ÚP
ANAC_FSYN_LDO_TRIM_PosƒÚP
ANAC_FSYN_LDO_TRIM_MskŠÚP
ANAC_HP_DVDD_PD_Pos–ÚP
ANAC_HP_DVDD_PD_MskÚP
ANAC_HP_DVDD_EN_Pos—ÚP
ANAC_HP_DVDD_EN_MskžÚP
ANAC_DVDD_SRAM0_EN_PosÆÚP
ANAC_DVDD_SRAM0_EN_MskÍÚP
ANAC_DVDD_SRAM1_EN_PosÅÚP
ANAC_DVDD_SRAM1_EN_MskÌÚP
ANAC_DVDD_LPLDO_EN_Pos®ÚP
ANAC_DVDD_LPLDO_EN_MskµÚP
ANAC_VDD_FLASH_EN_Pos
ÚP
ANAC_VDD_FLASH_EN_MskÚP
ANAC_DVDD_DLL_EN_PosQÚP
ANAC_DVDD_DLL_EN_MskXÚP
ANAC_DVDD_PHY_EN_Pos<ÚP
ANAC_DVDD_PHY_EN_MskCÚP
ANAC_DVDD_CPU_EN_PosEÚP
ANAC_DVDD_CPU_EN_MskLÚ#P
ANAC_BUCK_BYPASS_EN_Pos_3vDÚ#P
ANAC_BUCK_BYPASS_EN_Msk_3vKÚP
ANAC_BUCK_EN_Pos_3vƒÚP
ANAC_BUCK_EN_Msk_3vŠÚP
ANAC_BUCK_VOUT_Pos_3vÄÚP
ANAC_BUCK_VOUT_Msk_3vËÚP
ANAC_BUCK_IMAX_Pos_3vãÚP
ANAC_BUCK_IMAX_Msk_3vêÚ"P
ANAC_BUCK_IMAX_CAL_Pos_3v¬Ú"P
ANAC_BUCK_IMAX_CAL_Msk_3v³Ú"P
ANAC_BUCK_ZERO_CAL_Pos_3v›Ú"P
ANAC_BUCK_ZERO_CAL_Msk_3v¢Ú%P
ANAC_BUCK_DLY_MODE_EN_Pos_3v¥Ú%P
ANAC_BUCK_DLY_MODE_EN_Msk_3v¬ÚP
ANAC_BUCK_TEST_EN_PosèÚP
ANAC_BUCK_TEST_EN_MskïÚ%P
ANAC_BUCK_DEBOUNCE_EN_Pos_3vÍÚ%P
ANAC_BUCK_DEBOUNCE_EN_Msk_3vÔÚ P
ANAC_BUCK_CAL_EN_Pos_3vLÚ P
ANAC_BUCK_CAL_EN_Msk_3vSÚP
ANAC_BUCK_CAL_OUT_PosóÚP
ANAC_BUCK_CAL_OUT_MskúÚ&P
ANAC_BUCK_VOL_LIMIT_EN_Pos_3vAÚ&P
ANAC_BUCK_VOL_LIMIT_EN_Msk_3vHÚP
ANAC_ADC_LDO_EN_PosªÚP
ANAC_ADC_LDO_EN_Msk±ÚP
ANAC_ADC_LDO_TRIM_PosýÚP
ANAC_ADC_LDO_TRIM_MskÚP
ANAC_RFFE_LDO_EN_PosMÚP
ANAC_RFFE_LDO_EN_MskTÚP
ANAC_RFFE_LDO_TRIM_Pos ÚP
ANAC_RFFE_LDO_TRIM_Msk§ÚP
ANAC_VCO_LDO_EN_PosŠÚP
ANAC_VCO_LDO_EN_Msk‘ÚP
ANAC_VCO_LDO_TRIM_PosÝÚP
ANAC_VCO_LDO_TRIM_MskäÚ P
ANAC_DFT_BUF_BYPASS_PosOÚ P
ANAC_DFT_BUF_BYPASS_MskVÚP
ANAC_DFT_FLAG_SEL_PosÚP
ANAC_DFT_FLAG_SEL_MskÚP
ANAC_DFT_CLK_SEL_PosFÚP
ANAC_DFT_CLK_SEL_MskMÚP
ANAC_DFT_I_SEL_PosÛÚP
ANAC_DFT_I_SEL_MskâÚP
ANAC_DFT_V_SEL_PosÎÚP
ANAC_DFT_V_SEL_MskÕÚ$P
ANAC_DFT_FLAG_OUTPUT_EN_PosùÚ$P
ANAC_DFT_FLAG_OUTPUT_EN_MskÚ#P
ANAC_DFT_CLK_OUTPUT_EN_Pos;Ú#P
ANAC_DFT_CLK_OUTPUT_EN_MskBÚ!P
ANAC_DFT_I_OUTPUT_EN_PosÐÚ!P
ANAC_DFT_I_OUTPUT_EN_Msk×Ú!P
ANAC_DFT_V_OUTPUT_EN_PosÃÚ!P
ANAC_DFT_V_OUTPUT_EN_MskÊÚ"P
ANAC_DFT_PAD_TEST_SEL_Pos¢Ú"P
ANAC_DFT_PAD_TEST_SEL_Msk©Ú%P
ANAC_DFT_BATTERY_TEST_EN_Pos§Ú%P
ANAC_DFT_BATTERY_TEST_EN_Msk®Ú&P
ANAC_DFT_BATTERY_TEST_SEL_PosTÚ&P
ANAC_DFT_BATTERY_TEST_SEL_Msk[Ú'P
ANAC_DFT_BATTERY_TEST_TRIM_PosúÚ'P
ANAC_DFT_BATTERY_TEST_TRIM_Msk
Ú'P
ANAC_MISC_RST_VREF_TRIM_Pos_3vÓÚ'P
ANAC_MISC_RST_VREF_TRIM_Msk_3vÚÚ"P
ANAC_MISC_PMU_LDO_TST_PosÚ"P
ANAC_MISC_PMU_LDO_TST_MskˆÚ%P
ANAC_MISC_PMU_VBG_BUF_EN_Pos§Ú%P
ANAC_MISC_PMU_VBG_BUF_EN_Msk®Ú.P
&ANAC_MISC_LPLDO_LEVEL_SHIFT_EN_Pos_3vÊÚ.P
&ANAC_MISC_LPLDO_LEVEL_SHIFT_EN_Msk_3vÑÚ+P
#ANAC_MISC_HPLDO_LEVEL_SHIFT_EN_PosÜÚ+P
#ANAC_MISC_HPLDO_LEVEL_SHIFT_EN_MskãÚ%P
ANAC_MISC_FLASH_PAD_PUEN_PosÌÚ%P
ANAC_MISC_FLASH_PAD_PUEN_MskÓÚ%P
ANAC_MISC_FLASH_PAD_PDEN_PosÝÚ%P
ANAC_MISC_FLASH_PAD_PDEN_MskäÚP
ANAC_MISC_USB_EN_Pos9ÚP
ANAC_MISC_USB_EN_Msk@Ú P
ANAC_MISC_USB_DP_PU_Pos.Ú P
ANAC_MISC_USB_DP_PU_Msk5Ú P
ANAC_MISC_USB_DM_PU_Pos1Ú P
ANAC_MISC_USB_DM_PU_Msk8ÚP
ANAC_ACT_32K_EN_PosÉÚP
ANAC_ACT_32K_EN_MskÐÚP
ANAC_ACT_32K_SEL_PosvÚP
ANAC_ACT_32K_SEL_Msk}Ú!P
ANAC_ACT_32K_UP_DONE_Pos(Ú!P
ANAC_ACT_32K_UP_DONE_Msk/Ú%P
ANAC_ACT_32K_FINE_OFFSET_PosÚ%P
ANAC_ACT_32K_FINE_OFFSET_Msk    Ú&P
ANAC_ACT_32K_FINE_CORRECT_PosµÚ&P
ANAC_ACT_32K_FINE_CORRECT_Msk¼ÚP
ANAC_CPU_REMAP_ADR_PosªÚP
ANAC_CPU_REMAP_ADR_Msk±Ú"P
ANAC_CPU_ADR_REMAP_EN_Pos²Ú"P
ANAC_CPU_ADR_REMAP_EN_Msk¹Ú!P
ANAC_RCL_HW_CAL_TIME_PosüÚ!P
ANAC_RCL_HW_CAL_TIME_MskÚP
ANAC_RCL_HW_CAL_EN_PosœÚP
ANAC_RCL_HW_CAL_EN_Msk£Ú!P
ANAC_RCL_HW_CAL_BUSY_PosèÚ!P
ANAC_RCL_HW_CAL_BUSY_MskïÚ8

<unnamed>QÚ 
"
¯"EF_CTLÚ 
"
¯"EF_ADDRåÚ 
"
¯"EF_DAT)Ú 
"
¯"EF_RSV0ÕÚ 
"
¯"EF_VDD$Ú 
"
¯"EF_RSV1ÔÚ 
"
¯"EF_CMD.Ú 
"
¯"EF_TRGÚ 
"
¯"EF_PROG_TIMING1`Ú 
"
¯"EF_PROG_TIMING2_Ú 
"
¯"EF_PROG_TIMING3^Ú 
"
¯"EF_READ_TIMING4yÚ 
"
¯"EF_READ_TIMING5xÚ <"
0¯"EF_RSV2uÚ 
"
¯"EF_OP_ERRORpÚ 
"
¯"EF_VERIFY_DEBUG1"Ú 
"
¯"EF_VERIFY_DEBUG2!Ú 
"
¯"EF_VERIFY_DEBUG3 Ú 
"
¯"EF_VERIFY_DEBUG4Ú 
"
¯"EF_FLASH_PERMISSIONÚ
EFUSE_TÈÚP
EFUSE_CTL_EFUSE_EN_Pos‹ÚP
EFUSE_CTL_EFUSE_EN_Msk’ÚP
EFUSE_CTL_THR_DVDD_Pos†ÚP
EFUSE_CTL_THR_DVDD_MskÚ"P
EFUSE_CTL_TAEN_RD_CTL_PosÚ"P
EFUSE_CTL_TAEN_RD_CTL_Msk—Ú!P
EFUSE_CTL_THR_RD_CTL_PosÌÚ!P
EFUSE_CTL_THR_RD_CTL_MskÓÚP
EFUSE_CTL_TRD_CTL_PosËÚP
EFUSE_CTL_TRD_CTL_MskÒÚ!P
EFUSE_CTL_TSR_RD_CTL_PosÁÚ!P
EFUSE_CTL_TSR_RD_CTL_MskÈÚ#P
EFUSE_CTL_TSR_DVDD_CTL_Pos1Ú#P
EFUSE_CTL_TSR_DVDD_CTL_Msk8Ú!P
EFUSE_CTL_THP_RD_CTL_PosÎÚ!P
EFUSE_CTL_THP_RD_CTL_MskÕÚ&P
EFUSE_CTL_THP_PG_AVDD_CTL_PosEÚ&P
EFUSE_CTL_THP_PG_AVDD_CTL_MskLÚ#P
EFUSE_CTL_TAEN_PGM_CTL_Pos@Ú#P
EFUSE_CTL_TAEN_PGM_CTL_MskGÚ"P
EFUSE_CTL_THP_PGM_CTL_Pos~Ú"P
EFUSE_CTL_THP_PGM_CTL_Msk…ÚP
EFUSE_CTL_TPGM_CTL_Pos{ÚP
EFUSE_CTL_TPGM_CTL_Msk‚Ú"P
EFUSE_CTL_TSP_PGM_CTL_PossÚ"P
EFUSE_CTL_TSP_PGM_CTL_MskzÚ&P
EFUSE_CTL_TSP_PG_AVDD_CTL_Pos:Ú&P
EFUSE_CTL_TSP_PG_AVDD_CTL_MskAÚ!P
EFUSE_CTL_TSP_RD_CTL_PosÃÚ%P
EFUSE_CTL_TSP_TSP_RD_CTL_MsklÚ%P
EFUSE_ADDR_EFUSEADDR_ADR_PosèÚ%P
EFUSE_ADDR_EFUSEADDR_ADR_MskïÚ#P
EFUSE_DAT_EFUSEDAT_DAT_PosnÚ#P
EFUSE_DAT_EFUSEDAT_DAT_MskuÚ+P
#EFUSE_DAT_EFUSEDAT_DAT_CONFIRM_PosñÚ+P
#EFUSE_DAT_EFUSEDAT_DAT_CONFIRM_MskøÚP
EFUSE_VDD_DVDD_REG_Pos›ÚP
EFUSE_VDD_DVDD_REG_Msk¢ÚP
EFUSE_VDD_AVDD_REG_PosžÚP
EFUSE_VDD_AVDD_REG_Msk¥Ú#P
EFUSE_CMD_EFUSECMD_CMD_Pos}Ú#P
EFUSE_CMD_EFUSECMD_CMD_Msk„Ú"P
EFUSE_TRG_EFUSETRG_GO_Pos‹Ú"P
EFUSE_TRG_EFUSETRG_GO_Msk’Ú*P
"EFUSE_PROG_TIMING1_TSP_RD_SET_PosûÚ*P
"EFUSE_PROG_TIMING1_TSP_RD_SET_MskÚ/P
'EFUSE_PROG_TIMING1_TSP_PG_AVDD_SET_PosrÚ/P
'EFUSE_PROG_TIMING1_TSP_PG_AVDD_SET_MskyÚ+P
#EFUSE_PROG_TIMING1_TSP_PGM_SET_Pos«Ú+P
#EFUSE_PROG_TIMING1_TSP_PGM_SET_Msk²Ú(P
 EFUSE_PROG_TIMING2_TPGM_SET_Pos²Ú(P
 EFUSE_PROG_TIMING2_TPGM_SET_Msk¹Ú+P
#EFUSE_PROG_TIMING2_THP_PGM_SET_PosµÚ+P
#EFUSE_PROG_TIMING2_THP_PGM_SET_Msk¼Ú,P
$EFUSE_PROG_TIMING2_TAEN_PGM_SET_PoswÚ,P
$EFUSE_PROG_TIMING2_TAEN_PGM_SET_Msk~Ú/P
'EFUSE_PROG_TIMING3_THP_PG_AVDD_SET_Pos{Ú/P
'EFUSE_PROG_TIMING3_THP_PG_AVDD_SET_Msk‚Ú*P
"EFUSE_PROG_TIMING3_THP_RD_SET_PosÚ*P
"EFUSE_PROG_TIMING3_THP_RD_SET_MskÚ,P
$EFUSE_READ_TIMING4_TSR_DVDD_SET_Pos‚Ú,P
$EFUSE_READ_TIMING4_TSR_DVDD_SET_Msk‰Ú*P
"EFUSE_READ_TIMING4_TSR_RD_SET_PosÚ*P
"EFUSE_READ_TIMING4_TSR_RD_SET_MskÚ'P
EFUSE_READ_TIMING4_TRD_SET_PosÚ'P
EFUSE_READ_TIMING4_TRD_SET_Msk#Ú*P
"EFUSE_READ_TIMING5_THR_RD_SET_PosÚ*P
"EFUSE_READ_TIMING5_THR_RD_SET_Msk#Ú+P
#EFUSE_READ_TIMING5_TAEN_RD_SET_PosàÚ+P
#EFUSE_READ_TIMING5_TAEN_RD_SET_MskçÚ,P
$EFUSE_READ_TIMING5_THR_DVDD_SET_PosŒÚ,P
$EFUSE_READ_TIMING5_THR_DVDD_SET_Msk“Ú$P
EFUSE_OP_ERROR_OP_ERROR_Pos¾Ú$P
EFUSE_OP_ERROR_OP_ERROR_MskÅÚ0P
(EFUSE_VERIFY_DEBUG1_VERIFY_DBG_KEY1_PospÚ0P
(EFUSE_VERIFY_DEBUG1_VERIFY_DBG_KEY1_MskwÚ0P
(EFUSE_VERIFY_DEBUG2_VERIFY_DBG_KEY2_PosnÚ0P
(EFUSE_VERIFY_DEBUG2_VERIFY_DBG_KEY2_MskuÚ0P
(EFUSE_VERIFY_DEBUG3_VERIFY_DBG_KEY3_PoslÚ0P
(EFUSE_VERIFY_DEBUG3_VERIFY_DBG_KEY3_MsksÚ0P
(EFUSE_VERIFY_DEBUG4_VERIFY_DBG_KEY4_PosjÚ0P
(EFUSE_VERIFY_DEBUG4_VERIFY_DBG_KEY4_MskqÚ(P
 EFUSE_FLASH_PERMISSION_CTRL_Pos»Ú(P
 EFUSE_FLASH_PERMISSION_CTRL_MskÂÚ8

<unnamed>QÚ "

™#FADDR©Ú "

™#POWER}Ú "

™#INT_IN1ôÚ "

™#INT_IN2óÚ "

™#    INT_OUT1‘Ú "

™#    INT_OUT2Ú "

™#INT_USBÒÚ "

™#    INT_IN1E­Ú "

™#    INT_IN2E¬Ú "

™#
INT_OUT1EJÚ "

™#
INT_OUT2EIÚ "

™#    INT_USBE‹Ú "

™#FRAME1lÚ "

™#FRAME2kÚ "

™#INDEX’Ú "

™#REV!Ú "

™#MAX_PKT_INÖÚ "

™#CSR0_INCSR1×Ú "

™#IN_CSR2öÚ "

™#MAX_PKT_OUTsÚ "

™#    OUT_CSR1”Ú "

™#    OUT_CSR2“Ú "

™#OUT_COUNT1ïÚ "

™#OUT_COUNT2îÚ <"
™#REV0²Ú "

™#    FIFO_EP0¼Ú <"
™#REV1¶Ú "

™#    FIFO_EP1»Ú <"
™#REV2µÚ "

™#    FIFO_EP2ºÚ <"
™#REV3´Ú "

™#    FIFO_EP3¹Ú
USB_TZÚ8

<unnamed>QÚ 
"
»#    DMA_INTRmÚ 
"
»#CNTL1Ú 
"
»#ADDR1•Ú 
"
»#COUNT1%Ú
    USBDMA_T‚ÚP
USB_DMA_REQUEST_PosqÚP
USB_DMA_REQUEST_MskxÚP
USB_DMA_DIRECTION_PosõÚP
USB_DMA_DIRECTION_MsküÚP
USB_DMA_MODE_SEL_Pos0ÚP
USB_DMA_MODE_SEL_Msk7ÚP
USB_DMA_EP_NUM_Pos¸ÚP
USB_DMA_EP_NUM_Msk¿Ú8

<unnamed>QÚ 
"
É#revs0ãÚ 
"
É#FSM5ºÚ 
"
É#FSM6¹Ú 
"
É#FSM13‰Ú 
"
É#FSM14ˆÚ 
"
É#FSM15‡Ú 
"
É#FSM16†Ú 
"
É#FSM17…Ú 
"
É#FSM18„Ú 
"
É#FSM19ƒÚ 
"
É#PHY1³Ú 
"
É#PHY2²Ú 
"
É#PHY3±Ú 
"
É#PHY4°Ú 
"
É#PHY5¯Ú <"
É#revs1¬Ú 
"
É#INTR1eÚ 
"
É#INTCLRÚ 
"
É#INTMSKûÚ 
"
É#INTR4bÚ 
"
É#revs2áÚ 
"
É#ACTTMR1ÓÚ 
"
É#ACTTMR2ÒÚ 
"
É#ACTTMR6ÎÚ 
"
É#ACTTMR7ÍÚ 
"
É#revs3àÚ 
"
É#SECURE1×Ú 
"
É#SECURE2ÖÚ 
"
É#SECURE3ÕÚ 
"
É#SECURE4ÔÚ 
"
É#SECURE5ÓÚ 
"
É#SECURE6ÒÚ 
"
É#SECURE7ÑÚ 
"
É#SECURE8ÐÚ 
"
É#SECURE9ÏÚ 
"
É#    SECURE10¥Ú 
"
É#revs4ßÚ 
"
É#TEST_MUX00ÐÚ 
"
É#RNG1½Ú 
"
É#RNG2¼Ú 
"
É#revs5ÞÚ 
"
É#LL_MAC_CTRLkÚ 
"
É#TEST_MUX01ÏÚ 
"
É#TEST_MUX02ÎÚ 
"
É#TEST_MUX03ÍÚ <"
É#revs6§Ú 
"
É#R00_CTLÛÚ 
"
É#R01_INTÒÚ 
"
É#R02_TMR_CTLÚ 
"
É#R03_RX_ADDR_LàÚ 
"
É#R04_RX_CTLÈÚ 
"
É#R05_TX_ADDR_LÜÚ 
"
É#R06_TX_CTLÄÚ 
"
É# R07_SRAM_CTL8Ú 
"
É#R08_RX_ADDR1_L¨Ú 
"
É#R09_RX_ADDR2_L¦Ú 
"
É#R0A_RX_ADDR3_LÚ 
"
É#R0B_RX_ADDR4_L›Ú 
"
É#R0C_RX_ADDR5_L™Ú 
"
É#R0D_RX_ADDR6_L—Ú 
"
É#R0E_RX_ADDR7_L•Ú 
"
É#R0F_RX_ADDR_HÑÚ 
"
É#R10_RX_ADDR_EN™Ú 
"
É#R11_CFGìÚ
    PRI_RF_T\ÚP
FSM5_SM_STP_Pos¬ÚP
FSM5_SM_STP_Msk³ÚP
FSM5_SM_TX_LATENCY_PoszÚP
FSM5_SM_TX_LATENCY_MskÚP
FSM6_SM_RX_LATENCY_Pos{ÚP
FSM6_SM_RX_LATENCY_Msk‚Ú&P
FSM13_SM_RX_PACKET_ADDR_1_PosÚ&P
FSM13_SM_RX_PACKET_ADDR_1_Msk”Ú&P
FSM13_SM_TX_PACKET_ADDR_1_Pos‹Ú&P
FSM13_SM_TX_PACKET_ADDR_1_Msk’Ú&P
FSM14_SM_RX_PACKET_ADDR_2_Pos‹Ú&P
FSM14_SM_RX_PACKET_ADDR_2_Msk’Ú&P
FSM14_SM_TX_PACKET_ADDR_2_Pos‰Ú&P
FSM14_SM_TX_PACKET_ADDR_2_MskÚ&P
FSM15_SM_RX_PACKET_ADDR_3_Pos‰Ú&P
FSM15_SM_RX_PACKET_ADDR_3_MskÚ&P
FSM15_SM_TX_PACKET_ADDR_3_Pos‡Ú&P
FSM15_SM_TX_PACKET_ADDR_3_MskŽÚ&P
FSM16_SM_RX_PACKET_ADDR_4_Pos‡Ú&P
FSM16_SM_RX_PACKET_ADDR_4_MskŽÚ&P
FSM16_SM_TX_PACKET_ADDR_4_Pos…Ú&P
FSM16_SM_TX_PACKET_ADDR_4_MskŒÚ&P
FSM17_SM_RX_PACKET_ADDR_5_Pos…Ú&P
FSM17_SM_RX_PACKET_ADDR_5_MskŒÚ&P
FSM17_SM_TX_PACKET_ADDR_5_PosƒÚ&P
FSM17_SM_TX_PACKET_ADDR_5_MskŠÚ&P
FSM18_SM_RX_PACKET_ADDR_6_PosƒÚ&P
FSM18_SM_RX_PACKET_ADDR_6_MskŠÚ&P
FSM18_SM_TX_PACKET_ADDR_6_PosÚ&P
FSM18_SM_TX_PACKET_ADDR_6_MskˆÚ&P
FSM19_SM_RX_PACKET_ADDR_7_PosÚ&P
FSM19_SM_RX_PACKET_ADDR_7_MskˆÚ&P
FSM19_SM_TX_PACKET_ADDR_7_PosÚ&P
FSM19_SM_TX_PACKET_ADDR_7_Msk†Ú&P
PHY1_PHY_DRV_RSP_BUF_FULL_Pos!Ú&P
PHY1_PHY_DRV_RSP_BUF_FULL_Msk(Ú'P
PHY1_PHY_DRV_RSP_BUF_EMPTY_PosÃÚ'P
PHY1_PHY_DRV_RSP_BUF_EMPTY_MskÊÚ'P
PHY1_PHY_DRV_CFG_BUF_ERROR_PosíÚ'P
PHY1_PHY_DRV_CFG_BUF_ERROR_MskôÚ&P
PHY1_PHY_DRV_CFG_BUF_FULL_PosFÚ&P
PHY1_PHY_DRV_CFG_BUF_FULL_MskMÚ'P
PHY1_PHY_DRV_CFG_BUF_EMPTY_PosèÚ'P
PHY1_PHY_DRV_CFG_BUF_EMPTY_MskïÚ!P
PHY1_IF_CLK_PRESCALE_PosÚ!P
PHY1_IF_CLK_PRESCALE_MskÚ'P
PHY1_PHY_DRV_RSSI_REG_ADDR_PosêÚ'P
PHY1_PHY_DRV_RSSI_REG_ADDR_MskñÚ!P
PHY1_PHY_DRV_CFG_TRG_PosÒÚ!P
PHY1_PHY_DRV_CFG_TRG_MskÙÚ!P
PHY1_PHY_DRV_CFG_REG_PosáÚ!P
PHY1_PHY_DRV_CFG_REG_MskèÚ'P
PHY1_PHY_DRV_RSP_BUF_FLUSH_PosÐÚ'P
PHY1_PHY_DRV_RSP_BUF_FLUSH_Msk×Ú'P
PHY1_PHY_DRV_CFG_BUF_FLUSH_PosõÚ'P
PHY1_PHY_DRV_CFG_BUF_FLUSH_MsküÚ'P
PHY2_PHY_DRV_RSP_BUF_ERROR_PosÇÚ'P
PHY2_PHY_DRV_RSP_BUF_ERROR_MskÎÚ)P
!PHY2_PHY_DRV_SEQ_RX_END_ADDR_Pos;Ú)P
!PHY2_PHY_DRV_SEQ_RX_END_ADDR_MskBÚ)P
!PHY2_PHY_DRV_SEQ_TX_END_ADDR_Pos9Ú)P
!PHY2_PHY_DRV_SEQ_TX_END_ADDR_Msk@Ú*P
"PHY2_PHY_DRV_SEQ_RX_STRT_ADDR_PosÃÚ*P
"PHY2_PHY_DRV_SEQ_RX_STRT_ADDR_MskÊÚ*P
"PHY2_PHY_DRV_SEQ_TX_STRT_ADDR_PosÁÚ*P
"PHY2_PHY_DRV_SEQ_TX_STRT_ADDR_MskÈÚ%P
PHY3_PHY_DRV_CFG_BUF_DIN_PosžÚ%P
PHY3_PHY_DRV_CFG_BUF_DIN_Msk¥Ú&P
PHY4_PHY_DRV_RSP_BUF_DOUT_PosÚ&P
PHY4_PHY_DRV_RSP_BUF_DOUT_MskÚ+P
#PHY5_PHY_DRV_SET_CHAN_REG_ADDR_PosºÚ+P
#PHY5_PHY_DRV_SET_CHAN_REG_ADDR_MskÁÚP
INTR1_IC_RNG_DONE_PosìÚP
INTR1_IC_RNG_DONE_MskóÚP
INTR1_IC_SEC_DONE_PosøÚP
INTR1_IC_SEC_DONE_MskÿÚ0P
(INTR1_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_PosÚ0P
(INTR1_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_MskÚ&P
INTR1_IC_PHY_DRV_CFG_DONE_PosXÚ&P
INTR1_IC_PHY_DRV_CFG_DONE_Msk_Ú#P
INTCLR_IC_RNG_DONE_CLR_PosDÚ#P
INTCLR_IC_RNG_DONE_CLR_MskKÚ#P
INTCLR_IC_SEC_DONE_CLR_PosPÚ#P
INTCLR_IC_SEC_DONE_CLR_MskWÚ5P
-INTCLR_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_CLR_PosXÚ5P
-INTCLR_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_CLR_Msk_Ú+P
#INTCLR_IC_PHY_DRV_CFG_DONE_CLR_Pos°Ú+P
#INTCLR_IC_PHY_DRV_CFG_DONE_CLR_Msk·Ú$P
INTMSK_IC_RNG_DONE_MASK_PosíÚ$P
INTMSK_IC_RNG_DONE_MASK_MskôÚ$P
INTMSK_IC_SEC_DONE_MASK_PosùÚ$P
INTMSK_IC_SEC_DONE_MASK_MskÚ6P
.INTMSK_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_MASK_Pos
Ú6P
.INTMSK_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_MASK_MskÚ,P
$INTMSK_IC_PHY_DRV_CFG_DONE_MASK_PosYÚ,P
$INTMSK_IC_PHY_DRV_CFG_DONE_MASK_Msk`ÚP
INTR4_IC_CLR_IRQ_Pos+ÚP
INTR4_IC_CLR_IRQ_Msk2Ú(P
 INTR4_IC_ONE_PULSE_FLAG_IRQ_Pos³Ú(P
 INTR4_IC_ONE_PULSE_FLAG_IRQ_MskºÚP
INTR4_IC_MODE_IRQ_PosåÚP
INTR4_IC_MODE_IRQ_MskìÚP
INTR4_IC_PULSE_CNT_Pos†ÚP
INTR4_IC_PULSE_CNT_MskÚ.P
&ACTTMR1_ACTTMR_CMPR_MAX_EVENT_DIN_PosÙÚ.P
&ACTTMR1_ACTTMR_CMPR_MAX_EVENT_DIN_MskàÚ'P
ACTTMR2_ACTTMR_DISABLE_FLG_PosLÚ'P
ACTTMR2_ACTTMR_DISABLE_FLG_MskSÚ&P
ACTTMR2_ACT_CLK_ACCUR_FLG_PosŽÚ&P
ACTTMR2_ACT_CLK_ACCUR_FLG_Msk•Ú-P
%ACTTMR2_ACTTMR_CMPR_MAX_EVENT_EN_Pos"Ú-P
%ACTTMR2_ACTTMR_CMPR_MAX_EVENT_EN_Msk)Ú/P
'ACTTMR6_ACTTMR_CMPR_STRT_EVENT_DIN_PoskÚ/P
'ACTTMR6_ACTTMR_CMPR_STRT_EVENT_DIN_MskrÚ*P
"ACTTMR7_ACTTMR_CPTUR_BUS_DOUT_PosûÚ*P
"ACTTMR7_ACTTMR_CPTUR_BUS_DOUT_MskÚ#P
SECURE1_SEC_DECRYPT_EN_PoshÚ#P
SECURE1_SEC_DECRYPT_EN_MskoÚP
SECURE1_SEC_AD_LEN_PosºÚP
SECURE1_SEC_AD_LEN_MskÁÚ P
SECURE1_SEC_MIC_LEN_PosdÚ P
SECURE1_SEC_MIC_LEN_MskkÚ P
SECURE1_SEC_VLD_MAC_PoseÚ P
SECURE1_SEC_VLD_MAC_MsklÚ$P
SECURE1_SEC_PKT_ENABLES_Pos+Ú$P
SECURE1_SEC_PKT_ENABLES_Msk2ÚP
SECURE1_SEC_MODE_Pos\ÚP
SECURE1_SEC_MODE_MskcÚP
SECURE1_SEC_ENABLE_PosÖÚP
SECURE1_SEC_ENABLE_MskÝÚP
SECURE2_SEC_IV3_Pos°ÚP
SECURE2_SEC_IV3_Msk·ÚP
SECURE2_SEC_IV2_Pos±ÚP
SECURE2_SEC_IV2_Msk¸ÚP
SECURE2_SEC_IV1_Pos²ÚP
SECURE2_SEC_IV1_Msk¹ÚP
SECURE2_SEC_IV0_Pos³ÚP
SECURE2_SEC_IV0_MskºÚP
SECURE3_SEC_IV7_Pos«ÚP
SECURE3_SEC_IV7_Msk²ÚP
SECURE3_SEC_IV6_Pos¬ÚP
SECURE3_SEC_IV6_Msk³ÚP
SECURE3_SEC_IV5_Pos­ÚP
SECURE3_SEC_IV5_Msk´ÚP
SECURE3_SEC_IV4_Pos®ÚP
SECURE3_SEC_IV4_MskµÚ%P
SECURE4_SEC_KEY2_RX_ADDR_PosÐÚ%P
SECURE4_SEC_KEY2_RX_ADDR_Msk×Ú%P
SECURE4_SEC_KEY1_RX_ADDR_PosÑÚ%P
SECURE4_SEC_KEY1_RX_ADDR_MskØÚ%P
SECURE5_SEC_KEY4_RX_ADDR_PosÍÚ%P
SECURE5_SEC_KEY4_RX_ADDR_MskÔÚ%P
SECURE5_SEC_KEY3_RX_ADDR_PosÎÚ%P
SECURE5_SEC_KEY3_RX_ADDR_MskÕÚ%P
SECURE6_SEC_KEY6_RX_ADDR_PosÊÚ%P
SECURE6_SEC_KEY6_RX_ADDR_MskÑÚ%P
SECURE6_SEC_KEY5_RX_ADDR_PosËÚ%P
SECURE6_SEC_KEY5_RX_ADDR_MskÒÚP
SECURE7_SEC_MD_LEN_Pos¨ÚP
SECURE7_SEC_MD_LEN_Msk¯Ú%P
SECURE7_SEC_KEY7_RX_ADDR_PosÈÚ%P
SECURE7_SEC_KEY7_RX_ADDR_MskÏÚ'P
SECURE7_SEC_PKT_CNT_TX_MSB_PosèÚ'P
SECURE7_SEC_PKT_CNT_TX_MSB_MskïÚ'P
SECURE8_SEC_PKT_CNT_TX_LSB_PosèÚ'P
SECURE8_SEC_PKT_CNT_TX_LSB_MskïÚ'P
SECURE9_SEC_PKT_CNT_RX_MSB_PosèÚ'P
SECURE9_SEC_PKT_CNT_RX_MSB_MskïÚ(P
 SECURE10_SEC_PKT_CNT_RX_LSB_Pos¿Ú(P
 SECURE10_SEC_PKT_CNT_RX_LSB_MskÆÚ)P
!TEST_MUX00_TST_MUX_SELECT_03_PosmÚ)P
!TEST_MUX00_TST_MUX_SELECT_03_MsktÚ)P
!TEST_MUX00_TST_MUX_SELECT_02_PosnÚ)P
!TEST_MUX00_TST_MUX_SELECT_02_MskuÚ)P
!TEST_MUX00_TST_MUX_SELECT_01_PosoÚ)P
!TEST_MUX00_TST_MUX_SELECT_01_MskvÚ)P
!TEST_MUX00_TST_MUX_SELECT_00_PospÚ)P
!TEST_MUX00_TST_MUX_SELECT_00_MskwÚ$P
RNG1_RNG_RING_SCRMB_SEL_PosþÚ$P
RNG1_RNG_RING_SCRMB_SEL_MskÚP
RNG1_RNG_EN_PosÌÚP
RNG1_RNG_EN_MskÓÚP
RNG2_RNG_DATA_Pos@ÚP
RNG2_RNG_DATA_MskGÚ#P
LL_MAC_CTRL_CTRL_LL_EN_Pos-Ú#P
LL_MAC_CTRL_CTRL_LL_EN_Msk4Ú)P
!TEST_MUX01_TST_MUX_SELECT_07_PoshÚ)P
!TEST_MUX01_TST_MUX_SELECT_07_MskoÚ)P
!TEST_MUX01_TST_MUX_SELECT_06_PosiÚ)P
!TEST_MUX01_TST_MUX_SELECT_06_MskpÚ)P
!TEST_MUX01_TST_MUX_SELECT_05_PosjÚ)P
!TEST_MUX01_TST_MUX_SELECT_05_MskqÚ)P
!TEST_MUX01_TST_MUX_SELECT_04_PoskÚ)P
!TEST_MUX01_TST_MUX_SELECT_04_MskrÚ)P
!TEST_MUX02_TST_MUX_SELECT_11_PoslÚ)P
!TEST_MUX02_TST_MUX_SELECT_11_MsksÚ)P
!TEST_MUX02_TST_MUX_SELECT_10_PosmÚ)P
!TEST_MUX02_TST_MUX_SELECT_10_MsktÚ)P
!TEST_MUX02_TST_MUX_SELECT_09_PoseÚ)P
!TEST_MUX02_TST_MUX_SELECT_09_MsklÚ)P
!TEST_MUX02_TST_MUX_SELECT_08_PosfÚ)P
!TEST_MUX02_TST_MUX_SELECT_08_MskmÚ)P
!TEST_MUX03_TST_MUX_SELECT_15_PosgÚ)P
!TEST_MUX03_TST_MUX_SELECT_15_MsknÚ)P
!TEST_MUX03_TST_MUX_SELECT_14_PoshÚ)P
!TEST_MUX03_TST_MUX_SELECT_14_MskoÚ)P
!TEST_MUX03_TST_MUX_SELECT_13_PosiÚ)P
!TEST_MUX03_TST_MUX_SELECT_13_MskpÚ)P
!TEST_MUX03_TST_MUX_SELECT_12_PosjÚ)P
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R00_CTL_TX_PAYLOAD_LEN_Pos`Ú#P
R00_CTL_TX_PAYLOAD_LEN_MskgÚ#P
R00_CTL_RX_PAYLOAD_LEN_PosbÚ#P
R00_CTL_RX_PAYLOAD_LEN_MskiÚ#P
R00_CTL_CRC_ACCESS_ADR_Pos”Ú#P
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R00_CTL_CRC24_EN_PosÚP
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R00_CTL_ADDR_BYTE_LEN_PosÉÚ"P
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R00_CTL_CRC_EN_PosùÚP
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R00_CTL_CRC_SEL16_Pos;ÚP
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R00_CTL_SCR_EN_PoséÚP
R00_CTL_SCR_EN_MskðÚ P
R00_CTL_NRF_ENHANCE_Pos‚Ú P
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R00_CTL_ENHANCE_PosÏÚP
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R00_CTL_BW_MODE_Pos¤ÚP
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R00_CTL_TX_NOACK_EN_PosPÚ P
R00_CTL_TX_NOACK_EN_MskWÚP
R00_CTL_PRI_RX_PosÏÚP
R00_CTL_PRI_RX_MskÖÚP
R01_INT_PRI_RX_PID_Pos‚ÚP
R01_INT_PRI_RX_PID_Msk‰ÚP
R01_INT_PRI_TX_PID_Pos€ÚP
R01_INT_PRI_TX_PID_Msk‡Ú"P
R01_INT_RX_LENGTH_ERR_Pos™Ú"P
R01_INT_RX_LENGTH_ERR_Msk Ú#P
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R01_INT_RX_LENGTH_ERR_MASK_PosÚ'P
R01_INT_RX_LENGTH_ERR_MASK_MskÚP
R01_INT_PRI_ENDIAN_Pos¹ÚP
R01_INT_PRI_ENDIAN_MskÀÚ'P
R01_INT_PRI_TX_DONE_IRQ_EN_PosêÚ'P
R01_INT_PRI_TX_DONE_IRQ_EN_MskñÚ'P
R01_INT_PRI_RX_DONE_IRQ_EN_PosìÚ'P
R01_INT_PRI_RX_DONE_IRQ_EN_MskóÚ P
R01_INT_PRI_RX_GOON_Pos*Ú P
R01_INT_PRI_RX_GOON_Msk1ÚP
R01_INT_PRI_RST_PosuÚP
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R01_INT_TX_TIMEOUT_IRQ_Pos-Ú#P
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R04_RX_CTL_TX_FEC_Pos×ÚP
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R10_RX_ADDR7_EN_PosµÚP
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R10_RX_ADDR6_EN_Pos¶ÚP
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R10_RX_ADDR5_EN_Pos·ÚP
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R10_RX_ADDR4_EN_Pos¸ÚP
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SYS_MFP_P21_GPIOÊÚP
SYS_MFP_P21_SPI1_MOSI;ÚP
SYS_MFP_P21_PWM_CH7ÞÚP
SYS_MFP_P21_TADC_VLDÚP
SYS_MFP_P21_LL_DBG_7—ÚP
SYS_MFP_P21_MDM_DBG_1UÚP
SYS_MFP_P21_XTL_C2_CLKèÚP
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SYS_MFP_P22_SPI1_CLKšÚP
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SYS_MFP_P22_TADC_DATl.ÚP
SYS_MFP_P22_MDM_DBG_0UÚP
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SYS_MFP_P23_GPIOÈÚP
SYS_MFP_P23_SPI1_CSßÚP
SYS_MFP_P23_PWM_CH1âÚP
SYS_MFP_P23_DPLL_DIV8GÚP
SYS_MFP_P23_TADC_DATHQÚP
SYS_MFP_P23_MDM_DBG_10!ÚP
SYS_MFP_P23_I2C0_SCLÀÚP
SYS_MFP_P23_RESERVEDÚP
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SYS_MFP_P24_GPIOÇÚP
SYS_MFP_P24_SPI1_MISO8ÚP
SYS_MFP_P24_UART1_RXxÚP
SYS_MFP_P24_PWM_CH2àÚ#P
SYS_MFP_P24_TIMER1_CNT_OUT•ÚP
SYS_MFP_P24_MDM_DBG_4OÚP
SYS_MFP_P24_RESERVEDŽÚP
SYS_MFP_P24_RESERVED1[ÚP
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SYS_MFP_P25_GPIOÆÚP
SYS_MFP_P25_SPI1_MOSI7ÚP
SYS_MFP_P25_UART1_TXuÚP
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SYS_MFP_P25_MDM_DBG_5MÚP
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SYS_MFP_P26_UART1_RTS%ÚP
SYS_MFP_P26_PWM_CH4ÜÚP
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ÚP
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SYS_MFP_P30_UART1_RX{ÚP
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SYS_SET_MFP)Ú
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ÚP
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cmd¬Ú
 FMC_ReadByte‹Ú,
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addr<Ú ,

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data;Ú
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 FMC_ReadWordƒÚ,
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 FMC_ReadPage¢Ú,
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lenšÚ
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lenšÚ
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lenšÚ
FMC_ReadInfoAreaÚ,
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lenšÚ
FMC_WriteInfoAreaÚ,
fmc•Ú
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mode2Ú,

enhanceÚ
FMC_SetFlashModeôÚ,
fmc•Ú
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fmc•Ú ,

mode2Ú
FMC_EnterEnhanceModeVÚ,
fmc•Ú
FMC_EnableAutoDpÿÚ,
fmc•Ú
FMC_DisableAutoDpÚ,
fmc•Ú,

cnt”Ú
FMC_SetRdpWaitCountÚ,
fmc•Ú,

cnt”Ú
FMC_SetDpWaitCountÚ,
fmc•Ú ,"

IRQnhÚ,"

    NewStateÚ
FMC_SetSuspendIrqWÚ,
fmc•Ú,

timeoutÊÚ
FMC_SetSuspendTimeout”ÚP
__PAN_DMAC_H__9ÚP
DMAC_CHANNEL_NUMBERÚP
DMA_INVLID_CHANNELXÚ"P
DMAC_TransferType_Mem2MemoÚ"P
DMAC_TransferType_Mem2PergÚ"P
DMAC_TransferType_Per2MemgÚ"P
DMAC_TransferType_Per2Per_ÚP
DMAC_FlowControl_DMA…Ú$P
DMAC_FlowControl_Peripheral=ÚP
DMAC_BurstLen_1zÚP
DMAC_BurstLen_4wÚP
DMAC_BurstLen_8sÚP
DMAC_BurstLen_16BÚP
DMAC_BurstLen_32DÚP
DMAC_BurstLen_64?ÚP
DMAC_BurstLen_128ÚP
DMAC_BurstLen_256
Ú"P
DMAC_AddrChange_Increment`Ú"P
DMAC_AddrChange_DecrementnÚ!P
DMAC_AddrChange_NoChangeÚP
DMAC_DataWidth_8&ÚP
DMAC_DataWidth_16õÚP
DMAC_DataWidth_32÷ÚP
DMAC_DataWidth_64òÚP
DMAC_DataWidth_128¿ÚP
DMAC_DataWidth_256½Ú P
DMAC_Peripheral_I2C0_Tx¥Ú P
DMAC_Peripheral_I2C0_Rx§Ú P
DMAC_Peripheral_SPI0_TxwÚ P
DMAC_Peripheral_SPI0_RxyÚ!P
DMAC_Peripheral_UART0_Tx%Ú!P
DMAC_Peripheral_UART0_Rx'Ú P
DMAC_Peripheral_SPI1_TxvÚ P
DMAC_Peripheral_SPI1_RxxÚ!P
DMAC_Peripheral_UART1_Tx$Ú!P
DMAC_Peripheral_UART1_Rx&ÚP
DMAC_Peripheral_ADCþÚP
DMAC_Peripheral_USB_Rx­ÚP
DMAC_Peripheral_USB_Tx«Ú#P
DMAC_HandshakePolarity_Low·Ú$P
DMAC_HandshakePolarity_HighgÚP
DMAC_Handshake_Default€Ú P
DMAC_Handshake_SoftwareøÚ P
DMAC_Handshake_HardwareÚ$P
DMAC_LockLevel_Tfr_Complete}Ú&P
DMAC_LockLevel_Block_CompleteºÚ,P
$DMAC_LockLevel_Transaction_CompleteÚP
DMAC_ChannelPriority_0ÚP
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DMAC_ChannelPriority_2ÚP
DMAC_ChannelPriority_3~ÚP
DMAC_ChannelPriority_4}ÚP
DMAC_ChannelPriority_5|ÚP
DMAC_ChannelPriority_6{ÚP
DMAC_ChannelPriority_7zÚP
DMAC_CHANNELALL_MASKÒÚP
DMAC_FLAG_INDEX_TFRõÚP
DMAC_FLAG_INDEX_BLKÚP
DMAC_FLAG_INDEX_SRCTFRÚP
DMAC_FLAG_INDEX_DSTTFRÚP
DMAC_FLAG_INDEX_ERRøÚP
DMAC_FLAG_MASK_TFRCÚP
DMAC_FLAG_MASK_BLKVÚP
DMAC_FLAG_MASK_SRCTFRUÚP
DMAC_FLAG_MASK_DSTTFRRÚP
DMAC_FLAG_MASK_ERRFÚP
DMAC_FLAG_MASK_ALLVÚ$8
__DMAC_ChannelConfigTypeDefÚ 
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DMAC_ChannelConfigTypeDef_Ú 
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IntEnableHÚ 
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BlockSize4Ú 
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FifoEmpty'Ú 
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DMAC_ChannelConfigTypeDef›Ú
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 DMAC_IntFlagÃÚ,"
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GPIO_PIN_ADDRÂÚP
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Ú"
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Ú
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‰4UARTx4Ú
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 READ_4_BYTESÚP
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Ú ,"
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*BLE_L2CAP_COC_ERR_SOURCE_CID_ALREADY_USED)Ú2P
*BLE_L2CAP_COC_ERR_UNACCEPTABLE_PARAMETERS`Ú-P
%BLE_L2CAP_COC_ERR_INVALID_PARAMETERSÊÚ'P
BLE_L2CAP_ERR_RECONFIG_SUCCEED¼Ú9P
1BLE_L2CAP_ERR_RECONFIG_REDUCTION_MTU_NOT_ALLOWEDÛÚ9P
1BLE_L2CAP_ERR_RECONFIG_REDUCTION_MPS_NOT_ALLOWEDáÚ,P
$BLE_L2CAP_ERR_RECONFIG_INVALID_DCID4Ú0P
(BLE_L2CAP_ERR_RECONFIG_UNACCAPTED_PARAMþÚ&P
BLE_L2CAP_EVENT_COC_CONNECTEDÚ)P
!BLE_L2CAP_EVENT_COC_DISCONNECTED Ú#P
BLE_L2CAP_EVENT_COC_ACCEPTïÚ*P
"BLE_L2CAP_EVENT_COC_DATA_RECEIVEDÑÚ)P
!BLE_L2CAP_EVENT_COC_TX_UNSTALLEDÜÚ/P
'BLE_L2CAP_EVENT_COC_RECONFIG_COMPLETED>Ú.P
&BLE_L2CAP_EVENT_COC_PEER_RECONFIGUREDÚ 
ble_l2cap_sig_update_fn¸Ú$8
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H_BLE_SM_áÚP
BLE_SM_ERR_PASSKEYÚP
BLE_SM_ERR_OOBVÚP
BLE_SM_ERR_AUTHREQÚ$P
BLE_SM_ERR_CONFIRM_MISMATCHYÚ!P
BLE_SM_ERR_PAIR_NOT_SUPPÿÚP
BLE_SM_ERR_ENC_KEY_SZþÚ P
BLE_SM_ERR_CMD_NOT_SUPPYÚP
BLE_SM_ERR_UNSPECIFIED÷ÚP
BLE_SM_ERR_REPEATEDâÚP
BLE_SM_ERR_INVAL¸ÚP
BLE_SM_ERR_DHKEY½ÚP
BLE_SM_ERR_NUMCMP`ÚP
BLE_SM_ERR_ALREADY,ÚP
BLE_SM_ERR_CROSS_TRANSµÚP
BLE_SM_ERR_MAX_PLUS_1ÚP
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BLE_SM_PAIR_ALG_PASSKEYŽÚP
BLE_SM_PAIR_ALG_OOBÖÚP
BLE_SM_PAIR_ALG_NUMCMPàÚ!P
BLE_SM_PAIR_KEY_DIST_ENC.Ú P
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