//*** <<< Use Configuration Wizard in Context Menu >>> ***
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#ifndef SAMPLE_CONFIG_H
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#define SAMPLE_CONFIG_H
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// <h> APP and MCU Config
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/* System main frequency, Unit M */
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// <o> System Clock <48=> 48M <32=> 32M
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#define CONFIG_SYSTEM_CLOCK 32
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// <i> System main frequency, Unit M
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/* Peripherals frequency divide, It can only be even numbers */
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// <o> Periph Divide <0=> 0 <2=> 2 <4=> 4 <6=> 6 <8=> 8 <10=> 10
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#define CONFIG_PERIPH_DIVIDE 2
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// <i> Peripherals frequency divide, It can only be even numbers
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/* Enable DCDC Mode */
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// <q> Enable DCDC (if disabled means LDO mode)
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#define CONFIG_SOC_DCDC_PAN1070 1
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// <i> Enable DCDC (if disabled means LDO mode)
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/* FreeRTOS Heap Usage Print*/
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// <q> FreeRTOS Heap Usage Print
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#define CONFIG_FREERTOS_HEAP_PRINT 0
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// <i> FreeRTOS Heap Usage Print
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/*vector table remap to ram */
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// <q> Vector Remap to Ram
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#define CONFIG_VECTOR_REMAP_TO_RAM 1
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// <i> vector remap to ram
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/*system watch dog enable */
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// <q> System Watch Dog Enable
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#define CONFIG_SYSTEM_WATCH_DOG_ENABLE 0
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// <i> System Watch Dog Enable
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/* App Use Ram Function */
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// <q> RAM Function
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#define CONFIG_RAM_FUNCTION 1
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// <i> adding parts of ram function can improve running ability
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#if CONFIG_RAM_FUNCTION
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#define CONFIG_RAM_CODE __attribute__((section(".ramfunc")))
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#else
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#define CONFIG_RAM_CODE
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#endif
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/* Log enable */
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// <q> Log Enable
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#define CONFIG_LOG_ENABLE 1
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// <i> Log enable
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/* Flash LDO Config */
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//<e> Flash LDO Config
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// <q> Flash LDO Enable
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#define CONFIG_FLASH_LDO_EN 1
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// <i> Flash LDO enable
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// <o> Flash LDO Voltage Select
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// <i> default:None => Flash LDO Voltage from FT Info
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// <0=>1.5V
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// <1=>1.6V
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// <2=>1.7V
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// <3=>1.8V
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// <4=>1.9V
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// <5=>2.0V
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// <6=>2.1V
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// <7=>2.2V
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// <8=>None
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#define CONFIG_FLASH_LDO_VOL 8
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//</e>
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// </h>
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// <h> BLE Stack Config
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/* user chip unique mac address */
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// <q> Use Chip unique Mac Address
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#define CONFIG_USER_CHIP_MAC_ADDR 1
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// <i> Use Chip unique Mac Address
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/* Select a low-speed clock source */
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// <o> Low-Speed Clock <0=> RCL <1=> XTL <2=> ACT32K
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#define CONFIG_LOW_SPEED_CLOCK_SRC 1
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// <i> Select a low-speed clock source
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/* CENTRAL maximum number of states supported */
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// <o> BT_MAX_NUM_OF_CENTRAL
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#define CONFIG_BT_MAX_NUM_OF_CENTRAL 1
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// <i> CENTRAL maximum number of states supported
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/* PERIPHERAL maximum number of states supported */
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// <o> BT_MAX_NUM_OF_PERIPHERAL
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#define CONFIG_BT_MAX_NUM_OF_PERIPHERAL 1
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// <i> PERIPHERAL maximum number of states supported
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/* Select BLE TX POWER */
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// <o> TX Power <0=> 0dBm <1=> 1dBm <2=> 2dBm <3=> 3dBm <4=> 4dBm <5=> 5dBm <6=> 6dBm <7=> 7dBm <8=> 8dBm <9=> 9dBm
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#define CONFIG_BT_CTLR_TX_POWER_DFT 0
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// <i> Select BLE TX POWER
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/* Force manual calibration of the RCL clock */
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// <q> Force Calib RCL
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#define CONFIG_FORCE_CALIB_RCL_CLK 0
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// <i> Force manual calibration of the RCL clock, production chips do not need to be turned on
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/* BT controller Memory Pool usage print*/
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// <q> BT controller Memory Pool usage print
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#define CONFIG_CNTRL_MEM_POOL_PRINT 0
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// <i> BT controller Memory Pool usage print
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/* BT AGC Init Mode*/
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// <o> BT AGC Init Mode
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#define CONFIG_BT_CTLR_AGC_MODE 0
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// <i> BT AGC Init Mode
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/* BT Debug Pin Init*/
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// <q> BT Debug Pin Init
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#define CONFIG_BT_CTLR_LINK_LAYER_DEBUG 0
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// <i> BT Debug Pin Init
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/* Calib RF Frequency offset*/
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// <q> Calib RF Frequency offset
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#define CONFIG_RF_CALIB 0
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// <i> Calib RF Frequency offset
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// </h>
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// <h> Low Power Config
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/* low power enable */
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// <q> Low Power Enable
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#define CONFIG_PM 1
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// <i> low power enable
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// <q> Keep Flash Power in Low Power Mode
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#define CONFIG_KEEP_FLASH_POWER_IN_LP_MODE 1
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// <i> Select this means flash power would be retained in Low Power Mode, and
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// <i> there would be a little avg-current increase (about 1uA). The benefit is that
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// <i> the large peak current (>15mA) would not occur.
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// <q> Enable DeepSleep Mode 2
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#define CONFIG_DEEPSLEEP_MODE_2 0
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// <i> Enable DeepSleep Mode 2 (Only LPLDOH in use), and the HW APB Timer Wakeup
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// <i> and PWM waveform output can be use in this mode.
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// <o> Increase LPLDOH trim value <0=> +0 <1=> +1 <2=> +2 <3=> +3 <4=> +4 <5=> +5 <6=> +6 <7=> +7 <8=> +8
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#define CONFIG_SOC_INCREASE_LPLDOH_CALIB_CODE 0
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// <i> Increase LPLDOH voltage for specific LowPower scenario use.
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// <q> Continue Run After Standby M1 Wakeup
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#define CONFIG_PM_STANDBY_M1_WAKEUP_WITHOUT_RESET 0
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// <i> Check this configuration to let CPU continue run after standby M1 waking up,
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// <i> or CPU would reset after waking up from standby M1.
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// <q> Detecting Temperature Optimize Param Enable
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#define CONFIG_AUTO_OPTIMIZE_POWER_PARAM 0
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/* ADC temperature sample interval(s)*/
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// <o> Temperature Sample Interval
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#define CONFIG_TEMP_SAMPLE_INTERVAL_S 300
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// <i> ADC temperature sample interval(s)
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/* DCDC vol */
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// <q> DVDD Voltage Optimize Enable
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#define CONFIG_DVDD_VOL_OPTIMIZE_EN 0
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// <q> HCLK Optimize Enable
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#define CONFIG_HCLK_OPTIMIZE_EN 0
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// </h>
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// <h> Flash Settings Config
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/* Flash Settings(kv_store) Start Address*/
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// <o> Flash Settings(kv_store) Start Address
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#define CONFIG_SETTINGS_START_ADDR 0x6D000
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// <i> Flash Settings(kv_store) Start Address
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/* Flash Settings(kv_store) Sector Number*/
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// <o> Flash Settings(kv_store) Sector Number (>=2)
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#define CONFIG_SETTINGS_SECTOR_NUM 2
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// <i> Flash Settings(kv_store) Sector Number
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// </h>
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#endif // SAMPLE_CONFIG_H
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//*** <<< end of configuration section >>> ***
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