/**************************************************************************//**
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* @file pan_hal_dmac.c
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* @version V0.0.0
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* $Revision: 1 $
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* $Date: 23/09/10 $
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* @brief Panchip series DMAC (Direct Memory Access Controller) HAL source file.
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* @note
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* Copyright (C) 2023 Panchip Technology Corp. All rights reserved.
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*****************************************************************************/
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#include "pan_hal.h"
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DMAC_HandleTypeDef DMAC_Channel_Array[DMAC_CHANNEL_NUMS] = {{0,}, {0,}};
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//uart ReceiveDma
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DMAC_ChannelConfigTypeDef dma_uart2mem_config = {
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.TransferType = DMAC_TransferType_Per2Mem,
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// Destination config (Memory)
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.AddrChangeDst = DMAC_AddrChange_Increment,
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.BurstLenDst = DMAC_BurstLen_8,
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.DataWidthDst = DMAC_DataWidth_8,
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.HandshakeDst = DMAC_Handshake_Default,
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// Source config (Peripheral)
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.AddrChangeSrc = DMAC_AddrChange_NoChange,
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.BurstLenSrc = DMAC_BurstLen_8, //According to peripheral FIFO threshold
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.DataWidthSrc = DMAC_DataWidth_8, //According to peripheral FIFO width
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.HandshakeSrc = DMAC_Handshake_Hardware,
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.PeripheralSrc = NULL, //Config to corresponding peripheral
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.FlowControl = DMAC_FlowControl_DMA,
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.IntEnable = ENABLE,
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};
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//uart sendDma
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DMAC_ChannelConfigTypeDef dma_mem2uart_config = {
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.TransferType = DMAC_TransferType_Mem2Per,
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.AddrChangeDst = DMAC_AddrChange_NoChange,
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.BurstLenDst = DMAC_BurstLen_8,
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.DataWidthDst = DMAC_DataWidth_8,
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.HandshakeDst = DMAC_Handshake_Hardware,
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//.PeripheralDst = TGT_UART_DMA_DST,
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.PeripheralDst = NULL,
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.AddrChangeSrc = DMAC_AddrChange_Increment,
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// .BurstLenSrc = DMAC_BurstLen_4,
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.BurstLenSrc = DMAC_BurstLen_8,
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//.DataWidthSrc = DMAC_DataWidth_32,
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.DataWidthSrc = DMAC_DataWidth_8,
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.HandshakeSrc = DMAC_Handshake_Default,
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.FlowControl = DMAC_FlowControl_DMA,
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.IntEnable = ENABLE
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};
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DMAC_ChannelConfigTypeDef dma_spi2mem_config = {
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/* Set dma channel control & config register */
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.TransferType = DMAC_TransferType_Per2Mem,
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// Destination config (Memory)
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.AddrChangeDst = DMAC_AddrChange_Increment,
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.BurstLenDst = DMAC_BurstLen_4,
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// .DataWidthDst = DMAC_DataWidth_32,
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.DataWidthDst = DMAC_DataWidth_16,
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.HandshakeDst = DMAC_Handshake_Default,
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// Source config (Peripheral)
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.AddrChangeSrc = DMAC_AddrChange_NoChange,
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.BurstLenSrc = DMAC_BurstLen_4, // According to peripheral FIFO threshold
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.DataWidthSrc = DMAC_DataWidth_16, // According to peripheral FIFO width
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.HandshakeSrc = DMAC_Handshake_Hardware,
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//.PeripheralSrc = TGT_SPI_DMA_SRC, // Config to corresponding peripheral
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.PeripheralSrc = NULL, // Config to corresponding peripheral
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// General config
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.FlowControl = DMAC_FlowControl_DMA,
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.IntEnable = ENABLE,
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/* Items in RxConfigTmp which are not influenced here is initialized as 0 by compiler. */
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};
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DMAC_ChannelConfigTypeDef dma_mem2spi_config = {
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/* Set dma channel control & config register */
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.TransferType = DMAC_TransferType_Mem2Per,
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// Destination config (Peripheral)
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.AddrChangeDst = DMAC_AddrChange_NoChange,
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.BurstLenDst = DMAC_BurstLen_4, // According to peripheral FIFO threshold
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.DataWidthDst = DMAC_DataWidth_16, // According to peripheral FIFO width
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.HandshakeDst = DMAC_Handshake_Hardware,
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//.PeripheralDst = TGT_SPI_DMA_DST, // Config to corresponding peripheral
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.PeripheralDst = NULL, // Config to corresponding peripheral
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// Source config (Memory)
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.AddrChangeSrc = DMAC_AddrChange_Increment,
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.BurstLenSrc = DMAC_BurstLen_4,
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// .DataWidthSrc = DMAC_DataWidth_32,
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.DataWidthSrc = DMAC_DataWidth_16,
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.HandshakeSrc = DMAC_Handshake_Default,
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// General config
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.FlowControl = DMAC_FlowControl_DMA,
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.IntEnable = ENABLE,
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/* Items in TxConfigTmp which are not influenced here is initialized as 0 by compiler. */
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};
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DMAC_ChannelConfigTypeDef dma_mem2i2c_config = {
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/*set tx dma channel control&config register*/
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.AddrChangeDst = DMAC_AddrChange_NoChange,
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.AddrChangeSrc = DMAC_AddrChange_Increment,
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.BurstLenDst = DMAC_BurstLen_1,
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.BurstLenSrc = DMAC_BurstLen_1,
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.DataWidthDst = DMAC_DataWidth_8,
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.DataWidthSrc = DMAC_DataWidth_8,
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.TransferType = DMAC_TransferType_Mem2Per,
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.FlowControl = DMAC_FlowControl_DMA,
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.HandshakeDst = DMAC_Handshake_Hardware,
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.HandshakeSrc = DMAC_Handshake_Hardware,
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// .PeripheralDst = DMAC_Peripheral_I2C0_Tx,
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.PeripheralDst = NULL,
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.IntEnable = ENABLE,
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};
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DMAC_ChannelConfigTypeDef dma_mem2i2c_u16_config = {
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/*set tx dma channel control&config register*/
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.AddrChangeDst = DMAC_AddrChange_NoChange,
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.AddrChangeSrc = DMAC_AddrChange_Increment,
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.BurstLenDst = DMAC_BurstLen_1,
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.BurstLenSrc = DMAC_BurstLen_1,
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.DataWidthDst = DMAC_DataWidth_16,
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.DataWidthSrc = DMAC_DataWidth_16,
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.TransferType = DMAC_TransferType_Mem2Per,
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.FlowControl = DMAC_FlowControl_DMA,
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.HandshakeDst = DMAC_Handshake_Hardware,
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.HandshakeSrc = DMAC_Handshake_Hardware,
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// .PeripheralDst = DMAC_Peripheral_I2C0_Tx,
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.PeripheralDst = NULL,
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.IntEnable = ENABLE,
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};
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DMAC_ChannelConfigTypeDef dma_i2c2mem_config = {
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/*set tx dma channel control&config register*/
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.AddrChangeDst = DMAC_AddrChange_Increment,
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.AddrChangeSrc = DMAC_AddrChange_NoChange,
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.BurstLenDst = DMAC_BurstLen_4,
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.BurstLenSrc = DMAC_BurstLen_4,
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.DataWidthDst = DMAC_DataWidth_8,
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.DataWidthSrc = DMAC_DataWidth_8,
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.TransferType = DMAC_TransferType_Per2Mem,
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.FlowControl = DMAC_FlowControl_DMA,
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.HandshakeDst = DMAC_Handshake_Hardware,
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.HandshakeSrc = DMAC_Handshake_Hardware,
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// .PeripheralSrc = DMAC_Peripheral_I2C0_Rx,
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.PeripheralSrc = NULL,
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.IntEnable = ENABLE,
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};
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DMAC_ChannelConfigTypeDef dma_adc2mem_config = {
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.AddrChangeDst = DMAC_AddrChange_Increment,
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.AddrChangeSrc = DMAC_AddrChange_NoChange,
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.BurstLenDst = DMAC_BurstLen_8,
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.BurstLenSrc = DMAC_BurstLen_8,
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.DataWidthDst = DMAC_DataWidth_16,
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.DataWidthSrc = DMAC_DataWidth_32,
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.TransferType = DMAC_TransferType_Per2Mem,
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.FlowControl = DMAC_FlowControl_DMA,
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.HandshakeDst = DMAC_Handshake_Hardware,
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.HandshakeSrc = DMAC_Handshake_Hardware,
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.PeripheralSrc = DMAC_Peripheral_ADC,
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.IntEnable = ENABLE
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};
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void HAL_DMA_Init(void)
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{
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CLK_AHBPeriphClockCmd(CLK_AHBPeriph_DMAC, ENABLE);
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DMAC_Init(DMA);
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NVIC_EnableIRQ(DMA_IRQn);
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}
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__WEAK void DMA_IRQHandlerOverlay(void)
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{
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int16_t remaind_cnt;
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/* Handle DMA Transfer Complete Interrupt */
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if (DMAC_CombinedIntStatus(DMA, DMAC_FLAG_MASK_TFR))
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{
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for (int i = 0; i < DMAC_CHANNEL_NUMS; i++)
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{
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if (DMAC_IntFlag(DMA, i, DMAC_FLAG_INDEX_TFR))
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{
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DMAC_ClrIntFlag(DMA, i, DMAC_FLAG_INDEX_TFR);
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switch (DMAC_Channel_Array[i].PeriMode)
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{
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case DMAC_Peri_UART:
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DMAC_Channel_Array[i].XferCount += DMAC_GetXferredBlockCount(DMA, i);
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remaind_cnt = DMAC_Channel_Array[i].XferSize - DMAC_Channel_Array[i].XferCount;
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if (remaind_cnt > 0)
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{
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if (remaind_cnt < 1024)
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{
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DMAC_ContinueChannel(DMA, i, remaind_cnt);
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}
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else
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{
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DMAC_ContinueChannel(DMA, i, 1023);
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}
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}
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else
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{
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if (DMAC_Channel_Array[i].CallbackUart != NULL)
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{
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if (DMAC_Channel_Array[i].ConfigTmp.TransferType == DMAC_TransferType_Per2Mem)
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{
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((HAL_UART_HandleTypeDef*)DMAC_Channel_Array[i].periph)->isRxBusy = false;
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}
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else if (DMAC_Channel_Array[i].ConfigTmp.TransferType == DMAC_TransferType_Mem2Per)
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{
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((HAL_UART_HandleTypeDef*)DMAC_Channel_Array[i].periph)->isTxBusy = false;
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}
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DMAC_Channel_Array[i].CallbackUart(UART_CB_FLAG_DMA, (uint8_t *)DMAC_Channel_Array[i].pBuffPtr,
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DMAC_Channel_Array[i].XferCount);
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}
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}
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break;
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case DMAC_Peri_I2C:
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DMAC_ReleaseChannel(DMA, i);
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if (DMAC_Channel_Array[i].CallbackI2c != NULL)
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{
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DMAC_Channel_Array[i].CallbackI2c(I2C_CB_FLAG_DMA, (uint8_t *)DMAC_Channel_Array[i].pBuffPtr,
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DMAC_Channel_Array[i].XferSize);
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}
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case DMAC_Peri_SPI:
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DMAC_ReleaseChannel(DMA, i);
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if (DMAC_Channel_Array[i].CallbackSpi!= NULL)
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{
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DMAC_Channel_Array[i].CallbackSpi(SPI_CB_FLAG_DMA, (uint16_t *)DMAC_Channel_Array[i].pBuffPtr,
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DMAC_Channel_Array[i].XferSize);
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}
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default:
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break;
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}
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}
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}
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}
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/* Handle Block Transfer Complete Interrupt */
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if(DMAC_CombinedIntStatus(DMA, DMAC_FLAG_MASK_BLK))
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{
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if(DMAC_IntFlag(DMA, 0, DMAC_FLAG_INDEX_BLK)){
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DMAC_ClrIntFlag(DMA, 0, DMAC_FLAG_INDEX_BLK);
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}
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if(DMAC_IntFlag(DMA, 1, DMAC_FLAG_INDEX_BLK)){
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DMAC_ClrIntFlag(DMA, 1, DMAC_FLAG_INDEX_BLK);
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}
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if(DMAC_IntFlag(DMA, 2, DMAC_FLAG_INDEX_BLK)){
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DMAC_ClrIntFlag(DMA, 2, DMAC_FLAG_INDEX_BLK);
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}
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}
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/* Handle Source Transation Complete Interrupt */
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if(DMAC_CombinedIntStatus(DMA, DMAC_FLAG_MASK_SRCTFR))
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{
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//idx_srctfr++;
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if(DMAC_IntFlag(DMA, 0, DMAC_FLAG_INDEX_SRCTFR)){
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DMAC_ClrIntFlag(DMA, 0, DMAC_FLAG_INDEX_SRCTFR);
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}
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if(DMAC_IntFlag(DMA, 1, DMAC_FLAG_INDEX_SRCTFR)){
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DMAC_ClrIntFlag(DMA, 1, DMAC_FLAG_INDEX_SRCTFR);
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}
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if(DMAC_IntFlag(DMA, 2, DMAC_FLAG_INDEX_SRCTFR)){
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DMAC_ClrIntFlag(DMA, 2, DMAC_FLAG_INDEX_SRCTFR);
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}
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}
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/* Handle Destination Transaction Complete Interrupt */
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if(DMAC_CombinedIntStatus(DMA, DMAC_FLAG_MASK_DSTTFR))
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{
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//idx_dsttfr++;
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if(DMAC_IntFlag(DMA, 0, DMAC_FLAG_INDEX_DSTTFR)){
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DMAC_ClrIntFlag(DMA, 0, DMAC_FLAG_INDEX_DSTTFR);
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}
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if(DMAC_IntFlag(DMA, 1, DMAC_FLAG_INDEX_DSTTFR)){
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DMAC_ClrIntFlag(DMA, 1, DMAC_FLAG_INDEX_DSTTFR);
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}
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if(DMAC_IntFlag(DMA, 2, DMAC_FLAG_INDEX_DSTTFR)){
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DMAC_ClrIntFlag(DMA, 2, DMAC_FLAG_INDEX_DSTTFR);
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}
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}
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/* Handle Error Interrupt */
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if(DMAC_CombinedIntStatus(DMA, DMAC_FLAG_MASK_ERR))
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{
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if(DMAC_IntFlag(DMA, 0, DMAC_FLAG_INDEX_ERR)){
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DMAC_ClrIntFlag(DMA, 0, DMAC_FLAG_INDEX_ERR);
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}
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if(DMAC_IntFlag(DMA, 1, DMAC_FLAG_INDEX_ERR)){
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DMAC_ClrIntFlag(DMA, 1, DMAC_FLAG_INDEX_ERR);
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}
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if(DMAC_IntFlag(DMA, 2, DMAC_FLAG_INDEX_ERR)){
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DMAC_ClrIntFlag(DMA, 2, DMAC_FLAG_INDEX_ERR);
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}
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}
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}
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void DMA_IRQHandler(void)
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{
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PAN_IO_TIMING_TRACK_LEVEL(CONFIG_TRACK_PIN_DMA_IRQ, 1);
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DMA_IRQHandlerOverlay();
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PAN_IO_TIMING_TRACK_LEVEL(CONFIG_TRACK_PIN_DMA_IRQ, 0);
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}
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