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L ..\\..\\..\\modules\\hal\\panchip\\panplat\\pan1070\\bsp\\peripheral\\src\\pan_hal_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil __asm___14_pan_hal_uart_c_ad6b4315____REV16 o ..\\..\\..\\modules\\hal\\panchip\\panplat\\pan1070\\bsp\\cmsis\\include\\ cmsis_armcc.h í L ..\\..\\..\\modules\\hal\\panchip\\panplat\\pan1070\\bsp\\peripheral\\src\\pan_hal_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil __asm___14_pan_hal_uart_c_ad6b4315____REVSH o ..\\..\\..\\modules\\hal\\panchip\\panplat\\pan1070\\bsp\\cmsis\\include\\ cmsis_armcc.h ü 0 ÿÿÿÿarmcc+ |
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..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\src\pan_hal_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\src\pan_hal_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil pUART_Handle_Array È ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\src\pan_hal_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil ¬ >È> HAL_UART_Init Ò ¬ ipUart © ] ___result Ò 4 \tmpreg Y Zintegerdivider Y ! Yfractionaldivider Y Yapbclock i PQFÇâ ¨ rnû ø ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\src\pan_hal_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil >øw HAL_UART_SendData Ò ipUart © c ipBuf D isize I % itimeout Y ___result Ò Ó Ztimeout_tick Y ª Zuptime_ref Y Fت J N nÉ eÓ F÷ª p t nÉ eÓ ü ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\src\pan_hal_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil >ü¢ HAL_UART_ReceiveData Ò ipUart © N ipBuf / isize I itimeout Y ò ___result Ò ¾ Ztimeout_tick Y Zuptime_ref Y Fܪ J N ¹ nÉ eÓ Fû¸ R T ¼ n× eá 8 ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\src\pan_hal_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil Ö >¹ HAL_UART_Init_INT Ò Ö ipUart © ___result Ò s Fø3
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nM F 4 n b* t F»X 8 N ns n} FÛ P f n£ n Fõò f p n F¾ v ¼ oÚ U oå B F¸ À Ð o² / ¤ ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\src\pan_hal_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil @ >£ HAL_UART_SendData_INT Ò @ ipUart © Ö ipBuf ¸ isize I ___result Ò q F¢ , 4 ²o/ ^ f9 À ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\src\pan_hal_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil H >· HAL_UART_ReceiveData_INT Ò H ipUart ©  ipBuf ¤ isize I ___result Ò ] F¢ * 2 Én/ f9 FÁ 4 < Ên/ f9 Ð ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\src\pan_hal_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil P >ÑÏ HAL_UART_ReceiveDataContinuously_INT Ò P ipUart ©  ipBuf ¤ ibufSize I ___result Ò ] F± 2 : èn/ f9 FÐ < D én/ f9 ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\src\pan_hal_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil 0 >¡î HAL_UART_SendDataAbort_INT Ò 0 ipUart © 5 ___result Ò FB ön[ fe F 3 " ùnM Ì ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\src\pan_hal_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil F >Ì HAL_UART_ReceiveDataAbort_INT Ò F ipUart © e ___result Ò G FB n[ fe F¨B n[ fe FË 2 n b* | ( ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\src\pan_hal_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil & >¨ HAL_UART_Init_DMA Ò & ipUart © £ idmaDir
icallback \ ___result Ò ZdmaCh Y > F¬3 2 nM FËX 2 F ¡ ns f} Fåò N ¢ n F ² n b* h F§ ¢ ¶ ³ n£ f ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\src\pan_hal_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil h >Í HAL_UART_SendData_DMA Ò h ipUart © ipBuf s isize I J ___result Ò ! ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\src\pan_hal_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil f >ê HAL_UART_ReceiveData_DMA Ò f ipUart ©
ipBuf g isize I I ___result Ò ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\src\pan_hal_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil 2 >
HAL_UART_SendDataAbort_DMA Ò 2 ipUart © T ___result Ò 6 F3 , oM # ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\src\pan_hal_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil 6 > HAL_UART_ReceiveDataAbort_DMA Ò 6 ipUart © T ___result Ò 6 F 0 ¤o # b* p < ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\src\pan_hal_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil
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< ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\src\pan_hal_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil
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?¼ù UART1_IRQHandlerOverlay
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4 ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\src\pan_hal_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil ?µþUART0_IRQHandler 4 ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\src\pan_hal_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil ?µUART1_IRQHandler ð ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\src\pan_hal_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil Î Iò? Î oX f bd F÷
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} } } } } } Î } H p U B T . P Î P 8 P P } } Q P T __DATE__ "Jan 20 2025" __TIME__ "09:43:58" __STDC__ 1 __STDC_VERSION__ 199901L __STDC_HOSTED__ 1 __STDC_ISO_10646__ 200607 __EDG__ 1 __EDG_VERSION__ 407 __EDG_SIZE_TYPE__ unsigned int __EDG_PTRDIFF_TYPE__ int __GNUC__ 4 __GNUC_STDC_INLINE__ 1 __GNUC_MINOR__ 7 __GNUC_PATCHLEVEL__ 0 __VERSION__ "4.7 (EDG gcc mode)" __CHAR16_TYPE__ unsigned short __CHAR32_TYPE__ unsigned int __USER_LABEL_PREFIX__ __CHAR_UNSIGNED__ 1 __WCHAR_UNSIGNED__ 1 __SIZE_TYPE__ unsigned int __PTRDIFF_TYPE__ int __WCHAR_TYPE__ unsigned short __WINT_TYPE__ unsigned short __INTMAX_TYPE__ long long __UINTMAX_TYPE__ unsigned long long __sizeof_int 4 __sizeof_long 4 __sizeof_ptr 4 __ARMCC_VERSION 5060750 __TARGET_CPU_CORTEX_M0 1 __TARGET_FPU_SOFTVFP 1 __TARGET_FPU_SOFTVFP 1 __MICROLIB 1 __UVISION_VERSION 530 ARMCM0 1 _RTE_ 1 IS_BOOTLOADER 1 CONFIG_FLASH_LINE_MODE FLASH_X2_MODE BLE_EN 0 CONFIG_OS_EN 0 __CC_ARM 1 __arm 1 __arm__ 1 __TARGET_ARCH_6S_M 1 __TARGET_ARCH_ARM 0 __TARGET_ARCH_THUMB 3 __TARGET_ARCH_A64 0 __TARGET_ARCH_AARCH32 1 __TARGET_PROFILE_M 1 __TARGET_FEATURE_HALFWORD 1 __TARGET_FEATURE_THUMB 1 __TARGET_FEATURE_DMB 1 __TARGET_FEATURE_EXTENSION_REGISTER_COUNT 0 __APCS_INTERWORK 1 __thumb 1 __thumb__ 1 __t32__ 1 __OPTIMISE_TIME 1 __OPTIMIZE__ 1 __OPT_SMALL_ASSERT 1 __OPTIMISE_LEVEL 3 __SOFTFP__ 1 $ $ UART_Handle_Array Ì HAL_UART_Init $ ü HAL_UART_SendData ' HAL_UART_ReceiveData $ < HAL_UART_Init_INT ( ¨ HAL_UART_SendData_INT + Ä HAL_UART_ReceiveData_INT 7 Ô HAL_UART_ReceiveDataContinuously_INT - ¤ HAL_UART_SendDataAbort_INT 0 Ð HAL_UART_ReceiveDataAbort_INT $ , HAL_UART_Init_DMA ( HAL_UART_SendData_DMA + HAL_UART_ReceiveData_DMA - HAL_UART_SendDataAbort_DMA 0 HAL_UART_ReceiveDataAbort_DMA * @ UART0_IRQHandlerOverlay * @ UART1_IRQHandlerOverlay # 8 UART0_IRQHandler # 8 UART1_IRQHandler % . SDK_CONFIG_H
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BOOT_ENABLE_UART_DFU 1 BOOT_ENABLE_USB_DFU 1 BOOT_ENABLE_PRF_OTA 1 CONFIG_FLASH_PARTITION_BOOTLOADER_ADDR 0x00000 CONFIG_FLASH_PARTITION_BOOTLOADER_SIZE 0x0A000 CONFIG_FLASH_PARTITION_APP_ADDR 0x0A000 CONFIG_FLASH_PARTITION_APP_SIZE 0x37000 "CONFIG_FLASH_PARTITION_APP_BACKUP_ADDR 0x41000 %CONFIG_FLASH_PARTITION_APP_BACKUP_SIZE 0x37000 KCONFIG_APP_USE_IMAGE_HEADER 1 WCONFIG_SOC_DCDC_PAN1070 0 ]CONFIG_SYSTEM_CLOCK 48 jCONFIG_APB1_CLOCK_DIVISOR 0 wCONFIG_APB2_CLOCK_DIVISOR 0 ~CONFIG_LOW_SPEED_CLOCK_SRC 0 CONFIG_FORCE_CALIB_RCL_CLK 0 CONFIG_RAM_FUNCTION 1 CONFIG_FLASH_LDO_EN 0 APP_LOG_EN 1 APP_LOG_LVL 4 ¡APP_LOG_LVL_OUTPUT_EN 1 ¤APP_LOG_TRACE_OUTPUT_EN 0 §CONFIG_UART_LOG_ENABLE 1 ³CONFIG_LOG_UART_PIN 2 ¼CONFIG_LOG_UART_BAUDRATE 921600 ÃCONFIG_RTT_LOG_ENABLE 0 ÇCONFIG_LOG_RTT_UP_BUFFER_SIZE 512 ÍCONFIG_IO_TIMING_TRACK 0 ÔCONFIG_BT_CTLR_LINK_LAYER_DEBUG 0 óCONFIG_TRACK_PIN_DEEPSLEEP_MODE 0x22 CONFIG_TRACK_PIN_SLEEP_MODE 0x23 ±CONFIG_TRACK_PIN_LL_IRQ 0x99 ÑCONFIG_TRACK_PIN_BLE_EVNT_IRQ 0x99 ðCONFIG_TRACK_PIN_OS_TICK_IRQ 0x99 CONFIG_TRACK_PIN_SLPTMR_IRQ 0x99 ®CONFIG_TRACK_PIN_HARDFAULT_IRQ 0x99 ÍCONFIG_TRACK_PIN_DMA_IRQ 0x99 ìCONFIG_TRACK_PIN_GPIO0_IRQ 0x99 CONFIG_TRACK_PIN_GPIO1_IRQ 0x99 ªCONFIG_TRACK_PIN_GPIO2_IRQ 0x99 ÉCONFIG_TRACK_PIN_GPIO3_IRQ 0x99 èCONFIG_TRACK_PIN_I2C_IRQ 0x99 CONFIG_TRACK_PIN_SPI0_IRQ 0x99 ¦CONFIG_TRACK_PIN_SPI1_IRQ 0x99 ÅCONFIG_TRACK_PIN_TMR0_IRQ 0x99 äCONFIG_TRACK_PIN_TMR1_IRQ 0x99 CONFIG_TRACK_PIN_TMR2_IRQ 0x99 ¢CONFIG_TRACK_PIN_UART0_IRQ 0x99 ÁCONFIG_TRACK_PIN_UART1_IRQ 0x99 àCONFIG_TRACK_PIN_WDT_IRQ 0x99 ÿCONFIG_TRACK_PIN_WWDT_IRQ 0x99 CONFIG_TRACK_USER_APP_CHN0 0x99 ½CONFIG_TRACK_USER_APP_CHN1 0x99 ÜCONFIG_TRACK_USER_APP_CHN2 0x99 ûCONFIG_TRACK_USER_APP_CHN3 0x99 CONFIG_TRACK_USER_APP_CHN4 0x99 ¹CONFIG_TRACK_USER_APP_CHN5 0x99 ØCONFIG_TRACK_USER_APP_CHN6 0x99 ÷CONFIG_TRACK_USER_APP_CHN7 0x99 @ 4 .\configuration\ sdk_config.h Ø
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.\configuration\sdk_config.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil _SOC_CONFIG_H_ TCONFIG_RAM_CODE __attribute__((section(".ramfunc"))) `CONFIG_VECTOR_REMAP_TO_RAM 0 eCONFIG_AUTO_OPTIMIZE_POWER_PARAM 0 jCONFIG_TEMP_SAMPLE_INTERVAL_S 300 oCONFIG_DVDD_VOL_OPTIMIZE_EN 0 tCONFIG_PM 0 yCONFIG_SYSTEM_WATCH_DOG_ENABLE 0 ~CONFIG_KEEP_FLASH_POWER_IN_LP_MODE 0 CONFIG_DEEPSLEEP_MODE_2 0 CONFIG_SOC_INCREASE_LPLDOH_CALIB_CODE 0 CONFIG_PM_STANDBY_M1_WAKEUP_WITHOUT_RESET 0 CONFIG_HCLK_OPTIMIZE_EN 0 «IS_BOOTABLE_APP 0 °CONFIG_APP_IMG_VER_MAJOR 0 ´CONFIG_APP_IMG_VER_MINOR 0 ¸CONFIG_APP_IMG_VER_REVISION 0 ¼CONFIG_APP_IMG_VER_BUILD 0 ÃENCRYPT_SECTION \ R ..\..\config\ .\configuration\ soc_config.h sdk_config.h Ô
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..\..\config\soc_config.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil __stdint_h __ARMCLIB_VERSION 5060037 __INT64 __int64 __INT64_C_SUFFIX__ ll __PASTE2(x,y) x ## y __PASTE(x,y) __PASTE2(x, y) __INT64_C(x) __ESCAPE__(__PASTE(x, __INT64_C_SUFFIX__)) __UINT64_C(x) __ESCAPE__(__PASTE(x ## u, __INT64_C_SUFFIX__)) __LONGLONG long long #__STDINT_DECLS %__CLIBNS ,__CLIBNS sINT8_MIN -128 tINT16_MIN -32768 uINT32_MIN (~0x7fffffff) vINT64_MIN __INT64_C(~0x7fffffffffffffff) yINT8_MAX 127 zINT16_MAX 32767 {INT32_MAX 2147483647 |INT64_MAX __INT64_C(9223372036854775807) UINT8_MAX 255 UINT16_MAX 65535 UINT32_MAX 4294967295u UINT64_MAX __UINT64_C(18446744073709551615) INT_LEAST8_MIN -128 INT_LEAST16_MIN -32768 INT_LEAST32_MIN (~0x7fffffff) INT_LEAST64_MIN __INT64_C(~0x7fffffffffffffff) INT_LEAST8_MAX 127 INT_LEAST16_MAX 32767 INT_LEAST32_MAX 2147483647 INT_LEAST64_MAX __INT64_C(9223372036854775807) UINT_LEAST8_MAX 255 UINT_LEAST16_MAX 65535 UINT_LEAST32_MAX 4294967295u UINT_LEAST64_MAX __UINT64_C(18446744073709551615) INT_FAST8_MIN (~0x7fffffff) INT_FAST16_MIN (~0x7fffffff) INT_FAST32_MIN (~0x7fffffff) INT_FAST64_MIN __INT64_C(~0x7fffffffffffffff) ¡INT_FAST8_MAX 2147483647 ¢INT_FAST16_MAX 2147483647 £INT_FAST32_MAX 2147483647 ¤INT_FAST64_MAX __INT64_C(9223372036854775807) §UINT_FAST8_MAX 4294967295u ¨UINT_FAST16_MAX 4294967295u ©UINT_FAST32_MAX 4294967295u ªUINT_FAST64_MAX __UINT64_C(18446744073709551615) ²INTPTR_MIN INT32_MIN ¹INTPTR_MAX INT32_MAX ÀUINTPTR_MAX UINT32_MAX ÆINTMAX_MIN __ESCAPE__(~0x7fffffffffffffffll) ÉINTMAX_MAX __ESCAPE__(9223372036854775807ll) ÌUINTMAX_MAX __ESCAPE__(18446744073709551615ull) ÕPTRDIFF_MIN INT32_MIN ÖPTRDIFF_MAX INT32_MAX ÚSIG_ATOMIC_MIN (~0x7fffffff) ÛSIG_ATOMIC_MAX 2147483647 áSIZE_MAX UINT32_MAX çWCHAR_MIN èWCHAR_MAX îWCHAR_MIN 0 ïWCHAR_MAX 65535 óWINT_MIN (~0x7fffffff) ôWINT_MAX 2147483647 ûINT8_C(x) (x) üINT16_C(x) (x) ýINT32_C(x) (x) þINT64_C(x) __INT64_C(x) UINT8_C(x) (x ## u) UINT16_C(x) (x ## u) UINT32_C(x) (x ## u) UINT64_C(x) __UINT64_C(x) INTMAX_C(x) __ESCAPE__(x ## ll) UINTMAX_C(x) __ESCAPE__(x ## ull) ²__INT64 ³__LONGLONG P D C:\Keil_v5\ARM\ARMCC\Bin\..\include\ stdint.h C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] signed char short int long long unsigned char unsigned short unsigned int unsigned long long Pint8_t 8 Pint16_t 9 Pint32_t ¢ : Pint64_t © ; Puint8_t ¶ > Puint16_t Ç ? Puint32_t Ù @ Puint64_t é A Pint_least8_t G Pint_least16_t H Pint_least32_t ¢ I Pint_least64_t © J Puint_least8_t ¶ M Puint_least16_t Ç N Puint_least32_t Ù O Puint_least64_t é P Pint_fast8_t ¢ U Pint_fast16_t ¢ V Pint_fast32_t ¢ W Pint_fast64_t © X Puint_fast8_t Ù [ Puint_fast16_t Ù \ Puint_fast32_t Ù ] Puint_fast64_t é ^ Pintptr_t ¢ e Puintptr_t Ù f Pintmax_t © j!Puintmax_t é k! __bool_true_false_are_defined 1 __ARMCLIB_VERSION 5060037 bool _Bool true 1 false 0 P E C:\Keil_v5\ARM\ARMCC\Bin\..\include\ stdbool.h C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdbool.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] __stdio_h __ARMCLIB_VERSION 5060037 "_ARMABI __declspec(__nothrow) %__STDIO_DECLS '__CLIBNS -__CLIBNS <NULL =NULL 0 g_SYS_OPEN 16 ¥stdin (&__CLIBNS __stdin) §stdout (&__CLIBNS __stdout) ©stderr (&__CLIBNS __stderr) ¬_IOFBF 0x100 _IOLBF 0x200 ®_IONBF 0x400 ±BUFSIZ (512) ³FOPEN_MAX _SYS_OPEN ¹FILENAME_MAX 256 ¾L_tmpnam FILENAME_MAX ÄTMP_MAX 256 ÌEOF (-1) ÒSEEK_SET 0 ÓSEEK_CUR 1 ÔSEEK_END 2 Ú_IOBIN 0x04 Ü__STDIN_BUFSIZ (64) Ý__STDOUT_BUFSIZ (64) Þ__STDERR_BUFSIZ (16) ¿getchar() getc(stdin) àputchar(c) putc(c, stdout) L C C:\Keil_v5\ARM\ARMCC\Bin\..\include\ stdio.h ¸ C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] unsigned int unsigned long long Psize_t 5P__va_list N F *õ __state1 # __state2 # )¨__fpos_t_struct __pos # __mbstate Ð # Pfpos_t õ a-__FILE PFILE 6lq__stdin >q__stdout >q__stderr >">q__aeabi_stdin vq__aeabi_stdout vq__aeabi_stderr v l ¼ J __stdin X __stdout g __stderr z __aeabi_stdin __aeabi_stdout £ __aeabi_stderr __stdlib_h __ARMCLIB_VERSION 5060037 __LONGLONG long long _ARMABI __declspec(__nothrow) _ARMABI_PURE __declspec(__nothrow) __attribute__((const)) _ARMABI_NORETURN __declspec(__nothrow) __declspec(__noreturn) _ARMABI_THROW !__STDLIB_DECLS )__USE_C99_STDLIB 1 -__CLIBNS 4__CLIBNS GNULL HNULL 0 mEXIT_FAILURE 1 oEXIT_SUCCESS 0 RAND_MAX 0x7fffffff MB_CUR_MAX ( __aeabi_MB_CUR_MAX() ) ¥__fpsr_IXE 0x100000 ¦__fpsr_UFE 0x80000 §__fpsr_OFE 0x40000 ¨__fpsr_DZE 0x20000 ©__fpsr_IOE 0x10000 «__fpsr_IXC 0x10 ¬__fpsr_UFC 0x8 __fpsr_OFC 0x4 ®__fpsr_DZC 0x2 ¯__fpsr_IOC 0x1 ý__LONGLONG X O C:\Keil_v5\ARM\ARMCC\Bin\..\include\ stdlib.h stdio.h À C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdlib.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] unsigned short int long long long uvoid char unsigned int Pwchar_t P )div_t quot # rem # Pdiv_t å \))·ldiv_t quot £ # rem £ # Pldiv_t ^/)élldiv_t quot « # rem « # Plldiv_t Ea2)_rand_state ä 8 __x # )È_ANSI_rand_state ¼ __x ³# NØ %Ø%àV "¸ ¾ "Ü"ÈP__heapprt äò)£__sdiv32by16 quot # rem # P__sdiv32by16 úÿ0)á__udiv32by16 quot Æ # rem Æ # P__udiv32by16 89)__sdiv64by32 rem # quot # P__sdiv64by32 v0Psize_t Æ 5 ¡ ¢ £ __string_h __ARMCLIB_VERSION 5060037 _ARMABI __declspec(__nothrow) __STRING_DECLS __CLIBNS $__CLIBNS 7NULL 8NULL 0 X O C:\Keil_v5\ARM\ARMCC\Bin\..\include\ string.h stdio.h ¨ C:\Keil_v5\ARM\ARMCC\Bin\..\include\string.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] unsigned int Psize_t 5 ¥ ¦ § __CMSIS_VERSION_H #__CM_CMSIS_VERSION_MAIN ( 5U) $__CM_CMSIS_VERSION_SUB ( 3U) %__CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | __CM_CMSIS_VERSION_SUB ) p f ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\ cmsis_version.h
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..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\cmsis_version.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil © ª « __CMSIS_ARMCC_H $__ARM_ARCH_6M__ 1 9__ASM __asm <__INLINE __inline ?__STATIC_INLINE static __inline B__STATIC_FORCEINLINE static __forceinline E__NO_RETURN __declspec(noreturn) H__USED __attribute__((used)) K__WEAK __attribute__((weak)) N__PACKED __attribute__((packed)) Q__PACKED_STRUCT __packed struct T__PACKED_UNION __packed union W__UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) Z__UNALIGNED_UINT16_WRITE(addr,val) ((*((__packed uint16_t *)(addr))) = (val)) ]__UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) `__UNALIGNED_UINT32_WRITE(addr,val) ((*((__packed uint32_t *)(addr))) = (val)) c__UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) f__ALIGNED(x) __attribute__((aligned(x))) i__RESTRICT __restrict l__COMPILER_BARRIER() __memory_changed() r__PROGRAM_START __main v__INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit z__STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base ~__VECTOR_TABLE __Vectors __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) __NOP __nop §__WFI __wfi ¯__WFE __wfe ¶__SEV __sev ¿__ISB() do { __schedule_barrier(); __isb(0xF); __schedule_barrier(); } while (0U) Ê__DSB() do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0U) Õ__DMB() do { __schedule_barrier(); __dmb(0xF); __schedule_barrier(); } while (0U) â__REV __rev __ROR __ror __BKPT(value) __breakpoint(value) ¹__CLZ __clz p d ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\ cmsis_armcc.h ü
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..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\cmsis_armcc.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil ;Ê__get_CONTROL Y a__result Y Y__regControl Y P <«__set_CONTROL $Y control Y__regControl Y P ;¿·__get_IPSR Y a__result Y Y__regIPSR Y P ;úÃ__get_APSR Y a__result Y Y__regAPSR Y P ;µÏ__get_xPSR Y a__result Y Y__regXPSR Y P ;þÛ__get_PSP Y a__result Y Y__regProcessStackPointer Y P <Çç__set_PSP $Y topOfProcStack Y__regProcessStackPointer Y P ;ó__get_MSP Y a__result Y Y__regMainStackPointer Y P <Óÿ__set_MSP $Y topOfMainStack Y__regMainStackPointer Y P ;__get_PRIMASK Y a__result Y Y__regPriMask Y P <Î__set_PRIMASK $Y priMask Y__regPriMask Y P ;øö__get_FPSCR Y a__result Y <__set_FPSCR $Y fpscr ;ß¡9__RBIT Y $Y value a__result Y \result Y \s Y ;¬ ý8__SSAT $ val $Y sat a__result « \max ¬\min ¬ ;÷ 9__USAT Y $ val $Y sat a__result Y ö \max ÷ Y ® ¯ __CMSIS_COMPILER_H " ´ © ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\ C:\Keil_v5\ARM\ARMCC\Bin\..\include\ cmsis_compiler.h stdint.h cmsis_armcc.h
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..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\cmsis_compiler.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil ± ² ³ __CORE_CM0_H_GENERIC "?B__CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) C__CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) D__CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | __CM0_CMSIS_VERSION_SUB ) G__CORTEX_M (0U) L__FPU_USED 0U s__CORE_CM0_H_DEPENDANT ¢__I volatile const ¤__O volatile ¥__IO volatile ¨__IM volatile const ©__OM volatile ª__IOM volatile ÕAPSR_N_Pos 31U ÖAPSR_N_Msk (1UL << APSR_N_Pos) ØAPSR_Z_Pos 30U ÙAPSR_Z_Msk (1UL << APSR_Z_Pos) ÛAPSR_C_Pos 29U ÜAPSR_C_Msk (1UL << APSR_C_Pos) ÞAPSR_V_Pos 28U ßAPSR_V_Msk (1UL << APSR_V_Pos) ðIPSR_ISR_Pos 0U ñIPSR_ISR_Msk (0x1FFUL ) xPSR_N_Pos 31U xPSR_N_Msk (1UL << xPSR_N_Pos) xPSR_Z_Pos 30U xPSR_Z_Msk (1UL << xPSR_Z_Pos) xPSR_C_Pos 29U xPSR_C_Msk (1UL << xPSR_C_Pos) xPSR_V_Pos 28U xPSR_V_Msk (1UL << xPSR_V_Pos) xPSR_T_Pos 24U xPSR_T_Msk (1UL << xPSR_T_Pos) xPSR_ISR_Pos 0U xPSR_ISR_Msk (0x1FFUL ) ªCONTROL_SPSEL_Pos 1U «CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) ãSCB_CPUID_IMPLEMENTER_Pos 24U äSCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) æSCB_CPUID_VARIANT_Pos 20U çSCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) éSCB_CPUID_ARCHITECTURE_Pos 16U êSCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) ìSCB_CPUID_PARTNO_Pos 4U íSCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) ïSCB_CPUID_REVISION_Pos 0U ðSCB_CPUID_REVISION_Msk (0xFUL ) óSCB_ICSR_NMIPENDSET_Pos 31U ôSCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) öSCB_ICSR_PENDSVSET_Pos 28U ÷SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) ùSCB_ICSR_PENDSVCLR_Pos 27U úSCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) üSCB_ICSR_PENDSTSET_Pos 26U ýSCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) ÿSCB_ICSR_PENDSTCLR_Pos 25U SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) SCB_ICSR_ISRPREEMPT_Pos 23U SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
SCB_ICSR_ISRPENDING_Pos 22U SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) SCB_ICSR_VECTPENDING_Pos 12U SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) SCB_ICSR_VECTACTIVE_Pos 0U SCB_ICSR_VECTACTIVE_Msk (0x1FFUL ) SCB_AIRCR_VECTKEY_Pos 16U SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) SCB_AIRCR_VECTKEYSTAT_Pos 16U SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) SCB_AIRCR_ENDIANESS_Pos 15U SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) SCB_AIRCR_SYSRESETREQ_Pos 2U SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) SCB_AIRCR_VECTCLRACTIVE_Pos 1U SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) SCB_SCR_SEVONPEND_Pos 4U SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) ¢SCB_SCR_SLEEPDEEP_Pos 2U £SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) ¥SCB_SCR_SLEEPONEXIT_Pos 1U ¦SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) ©SCB_CCR_STKALIGN_Pos 9U ªSCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) ¬SCB_CCR_UNALIGN_TRP_Pos 3U SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) °SCB_SHCSR_SVCALLPENDED_Pos 15U ±SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) ÉSysTick_CTRL_COUNTFLAG_Pos 16U ÊSysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) ÌSysTick_CTRL_CLKSOURCE_Pos 2U ÍSysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) ÏSysTick_CTRL_TICKINT_Pos 1U ÐSysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) ÒSysTick_CTRL_ENABLE_Pos 0U ÓSysTick_CTRL_ENABLE_Msk (1UL ) ÖSysTick_LOAD_RELOAD_Pos 0U ×SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL ) ÚSysTick_VAL_CURRENT_Pos 0U ÛSysTick_VAL_CURRENT_Msk (0xFFFFFFUL ) ÞSysTick_CALIB_NOREF_Pos 31U ßSysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) áSysTick_CALIB_SKEW_Pos 30U âSysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) äSysTick_CALIB_TENMS_Pos 0U åSysTick_CALIB_TENMS_Msk (0xFFFFFFUL ) _VAL2FLD(field,value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) _FLD2VAL(field,value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) SCS_BASE (0xE000E000UL) SysTick_BASE (SCS_BASE + 0x0010UL) NVIC_BASE (SCS_BASE + 0x0100UL) SCB_BASE (SCS_BASE + 0x0D00UL) SCB ((SCB_Type *) SCB_BASE ) SysTick ((SysTick_Type *) SysTick_BASE ) NVIC ((NVIC_Type *) NVIC_BASE ) ¿NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping ÀNVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping ÁNVIC_EnableIRQ __NVIC_EnableIRQ ÂNVIC_GetEnableIRQ __NVIC_GetEnableIRQ ÃNVIC_DisableIRQ __NVIC_DisableIRQ ÄNVIC_GetPendingIRQ __NVIC_GetPendingIRQ ÅNVIC_SetPendingIRQ __NVIC_SetPendingIRQ ÆNVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ ÈNVIC_SetPriority __NVIC_SetPriority ÉNVIC_GetPriority __NVIC_GetPriority ÊNVIC_SystemReset __NVIC_SystemReset ÓNVIC_SetVector __NVIC_SetVector ÔNVIC_GetVector __NVIC_GetVector ×NVIC_USER_IRQ_OFFSET 16 ÛEXC_RETURN_HANDLER (0xFFFFFFF1UL) ÜEXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) ÝEXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) â_BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) ã_SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) ä_IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) æ__NVIC_SetPriorityGrouping(X) (void)(X) ç__NVIC_GetPriorityGrouping() (0U) Ä ¹ ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\ C:\Keil_v5\ARM\ARMCC\Bin\..\include\ core_cm0.h stdint.h cmsis_version.h cmsis_compiler.h ô
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..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\core_cm0.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil *Ú!_reserved0 Y # !V Y # !C Y # !Z Y # !N Y # Sí b w Y PAPSR_Type ZÒ*«!ISR Y # !_reserved0 Y # S¾ b w Y PIPSR_Type «í*Ù!ISR Y # !_reserved0 Y # !T Y # !_reserved1 Y # !V Y # !C Y # !Z Y # !N Y # Sì b Ð w Y PxPSR_Type Y
*Ã!_reserved0 Y # !SPSEL Y # !_reserved1 Y # SÖ b ~ w Y PCONTROL_Type ç*ì ùì ISER ð# Y RESERVED0 #ªì ICER !#ÂY RESERVED1 7#Ýì ISPR T#õY RESERVED2 j#ì ICPR #¨Y RESERVED3 #ÅY ? RESERVED4 º#àì IP ×# tY PNVIC_Type ëÆ* ( CPUID # ICSR ì# RESERVED0 Y # AIRCR ì# SCR ì# CCR ì# RESERVED1 Y #óì SHP j# SHCSR ì#$ Y tPSCB_Type à*Ü CTRL ì# LOAD ì# VAL ì# CALIB # PSysTick_Type §Æ;®
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__NVIC_GetEnableIRQ Y $ IRQn a__result Y <Ô
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__NVIC_DisableIRQ $ IRQn ; ¨__NVIC_GetPendingIRQ Y $ IRQn a__result Y <» »__NVIC_SetPendingIRQ $ IRQn <æ Ê__NVIC_ClearPendingIRQ $ IRQn ;¢ ô__NVIC_GetPriority Y $ IRQn a__result Y ;× NVIC_EncodePriority Y $Y PriorityGroup $Y PreemptPriority $Y SubPriority a__result Y \PriorityGroupTmp Y \PreemptPriorityBits Y \SubPriorityBits Y <¨NVIC_DecodePriority $Y Priority $Y PriorityGroup $pPreemptPriority $pSubPriority \PriorityGroupTmp Y \PreemptPriorityBits Y \SubPriorityBits Y "Y <ÎÀ__NVIC_SetVector $ IRQn $Y vector \vectors Y ;Ð__NVIC_GetVector Y $ IRQn a__result Y \vectors Y <²Û"__NVIC_SystemReset ;ßüSCB_GetFPUType Y a__result Y ;SysTick_Config Y $Y ticks a__result Y 9¾ï__NVIC_EnableIRQ $ IRQn 9õÜ__NVIC_SetPriority $ IRQn $Y priority µ ¶ · ¸ __SYSTEM_PANSERIES_H__ __PAN_STRINGIFY(x) #x PAN_STRINGIFY(s) __PAN_STRINGIFY(s) __PAN_CONCAT(x,y) x ## y PAN_CONCAT(x,y) __PAN_CONCAT(x, y) #__PAN_COND_CODE_1(_flag,_if_1_code,_else_code) __PAN_COND_CODE(_AAAAA ## _flag, _if_1_code, _else_code) %__PAN_COND_CODE_0(_flag,_if_0_code,_else_code) __PAN_COND_CODE(_BBBBB ## _flag, _if_0_code, _else_code) '_AAAAA1 _ZZZZZ, (_BBBBB0 _ZZZZZ, )__PAN_COND_CODE(one_or_two_args,_if_code,_else_code) __PAN_GET_ARG2_DEBRACKET(one_or_two_args _if_code, _else_code) -__PAN_GET_ARG2_DEBRACKET(ignore_this,val,__VA_ARGS__...) __PAN_DEBRACKET val /__PAN_DEBRACKET(__VA_ARGS__...) __VA_ARGS__ @PAN_COND_CODE_1(_flag,_if_1_code,_else_code) __PAN_COND_CODE_1(_flag, _if_1_code, _else_code) PPAN_COND_CODE_0(_flag,_if_0_code,_else_code) __PAN_COND_CODE_0(_flag, _if_0_code, _else_code) ´ ¨ ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\ C:\Keil_v5\ARM\ARMCC\Bin\..\include\ system_PanSeries.h stdint.h stdbool.h °
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..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\system_PanSeries.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil float _Bool *»±: rsvd0 &# !pmu_vbg_trim : # !rsvd1 : # !pmu_vbg_volt_l : # pmu_vbg_volt_h : # !hp_ldo_trim : # !hp_ldo_volt_l : # hp_ldo_volt_h : #!!lph_ldo_trim : #"!lph_ldo_volt_l : #" lph_ldo_volt_h : ##!lpl_ldo_trim : #$!lpl_ldo_volt_l : #$ lpl_ldo_volt_h : #%!flash_ldo_trim : #&!rsvd2 : #&!flash_ldo_volt_l : #& flash_ldo_volt_h : #'!ana_ldo_trim : #(!rffe_ldo_trim : #( !fsyn_ldo_trim : #)!adc_ldo_trim : #) !vco_ldo_trim : #*!ipoly_trim : #*!rsvd3 : #* !bod_vref_trim : #+!rsvd4 : #+!bod_vref_volt_l : #+ bod_vref_volt_h : #, rsvd5 : #-!xtl_core : #.!xth_icore : #.!rch_bias : #.!dpll_vco_freq_trim : #. !dpll_kvco_ctrl : #/!dpll_icp_ctrl : #/!dpll_icp_bias : #/!rsvd6 : #/ !adc_vbg_1v20_trim : #0!ptat_temp_trim : #0 adc_vbg_1v20_volt I #1 rch_trim : #3 rch_freq Y #4!rcl_coarse_trim : #8!lph_ldo_vref_trim : #8!rsvd7 : #8 rcl_fine_trim : #9 rcl_freq I #: analog_temp_volt I #<Ë : rsvd_0x3e À#> analog_0p6v_volt I #H : rsvd8 ö#J!buck_imax_cal_trim : #T!rsvd9 : #T !buck_zero_cal_trim : #U!rsvd10 : #U !buck_out_trim : #V!rsvd11 : #V buck_vout_volt I #W adc_vdd_k I #Y adc_vdd_b ÿ #[ adc_vbg_k I #\ adc_vbg_b #^ adc_temp_volt I #` current_temp_value #b battery_trim : #dÖ: rsvd12 K#eï: uid d#l chip_info : #u cp_version : #v ft_version : #w cp_pass_flag : #x ft_pass_flag : #y cp_checksum : #z ft_checksum : #{: user_rw_data #|µ: mac_addr *# xth_xocap_a # xth_xocap_m # xth_xocap_n # xth_xocap_trim : # xtl_xocap_a # xtl_xocap_m # xtl_xocap_n # xtl_xocap_trim : #ùo
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adc_vbg_kb ð# adc_vbat_k I #¼ adc_vbat_b #¾ adc_vbat_dtemp_k #À adc_vbat_dtemp_b #Â adc_temp_k #Ä adc_ctrl2 Y #È adc_extsmpt Y #Ì xth_fix_code1 : #Ð xth_fix_code2 : #Ñ xtl_fix_code1 : #Ò xtl_fix_code2 : #Ó: * rsvd13
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#Ô ft_checksum2 : #ÿ Rï_otp_struct Ø: ÿ d8 L
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m û
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m_v2 ! PADC_VBG_KB_T Ä
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XPOTP_STRUCT_T ;
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qisFtDataValid qSystemCoreClock Y )û_adc_vbg_kb adc_vbg_k I # adc_vbg_b # *¯#: rsvd0 # !pmu_vbg_trim : # !rsvd1 : # !pmu_vbg_volt_l : # pmu_vbg_volt_h : # !hp_ldo_trim : # !hp_ldo_volt_l : # hp_ldo_volt_h : #!!lph_ldo_trim : #"!lph_ldo_volt_l : #" lph_ldo_volt_h : ##!lpl_ldo_trim : #$!lpl_ldo_volt_l : #$ lpl_ldo_volt_h : #%!flash_ldo_trim : #&!rsvd2 : #&!flash_ldo_volt_l : #& flash_ldo_volt_h : #'!ana_ldo_trim : #(!rffe_ldo_trim : #( !fsyn_ldo_trim : #)!adc_ldo_trim : #) !vco_ldo_trim : #*!ipoly_trim : #*!rsvd3 : #* !bod_vref_trim : #+!rsvd4 : #+!bod_vref_volt_l : #+ bod_vref_volt_h : #,!adc_vbg_1v17_trim : #-!rsvd5 : #- adc_vbg_1v17_volt I #.!adc_vbg_1v20_trim : #0!rsvd6 : #0 adc_vbg_1v20_volt I #1 rch_trim : #3 rch_freq Y #4!rcl_coarse_trim : #8!rsvd7 : #8 rcl_fine_trim : #9 rcl_freq I #: xth_xocap_a #< xth_xocap_m #@ xth_xocap_n #D xtl_xocap_a #H xtl_xocap_m #L xtl_xocap_n #P!buck_imax_cal_trim : #T!rsvd8 : #T !buck_zero_cal_trim : #U!rsvd9 : #U !buck_out_trim : #V!rsvd10 : #V buck_vout_volt I #W adc_vdd_k I #Y adc_vdd_b ÿ #[ adc_vbg_k I #\ adc_vbg_b #^ adc_temp_volt I #` current_temp_value #b battery_trim : #d!pa_power_calib_trim_6dbm : #e!pa_power_calib_trim_0dbm : #e Ø!: mac_addr Í#fó!: uid è#l chip_info : #u cp_version : #v ft_version : #w cp_pass_flag : #x ft_pass_flag : #y cp_checksum : #z ft_checksum : #{#: user_rw_data #| 4 ´
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isFtDataValid ¬
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SystemCoreClock º » ¼ __PAN_SYS_LOG_H__ DBG_ON 0 INFO_ON 1 WARN_ON 1 ERR_ON 1 TEST_ON 1 ASSERT_ON 1 SYS_ABORT() do { } while (1) !LOG(flags,__VA_ARGS__...) do { if (flags) printf(__VA_ARGS__); } while (0) 'SYS_DBG(fmt,__VA_ARGS__...) LOG(DBG_ON, "[SYS DBG] %s:%s():%d, " fmt, __FILE__, __FUNCTION__, __LINE__, ## __VA_ARGS__) (SYS_INFO(fmt,__VA_ARGS__...) LOG(INFO_ON, "[SYS INFO] %s:%s():%d, " fmt, __FILE__, __FUNCTION__, __LINE__, ## __VA_ARGS__) )SYS_WARN(fmt,__VA_ARGS__...) LOG(WARN_ON, "[SYS WARN] %s:%s():%d, " fmt, __FILE__, __FUNCTION__, __LINE__, ## __VA_ARGS__) *SYS_TEST(__VA_ARGS__...) LOG(TEST_ON, __VA_ARGS__) ,SYS_ERR(fmt,__VA_ARGS__...) do { LOG(ERR_ON, "[SYS ERR] %s:%s():%d, "fmt, __FILE__, __FUNCTION__, __LINE__, ## __VA_ARGS__); if (ERR_ON) SYS_ABORT(); } while (0) 5SYS_ASSERT(expr) ((expr) ? (void)0u : SYS_AssertError((uint8_t*)__FILE__, __LINE__, (uint8_t*)(#expr))) ¬ ¡ ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\ C:\Keil_v5\ARM\ARMCC\Bin\..\include\ pan_sys_log.h stdio.h stdint.h
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..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_sys_log.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil ¾ ¿ À __PAN_SYS_H__ SYS_MFP_TYPE_Msk(bit) (1UL << ((bit) +16)) !SYS_MFP_ALT_Msk(bit) (1UL << ((bit) + 8)) "SYS_MFP_MFP_Msk(bit) (1UL << ((bit) )) $SYS_MFP_GPIO 0x00000000UL 'SYS_MFP_P00_GPIO 0x00000000UL (SYS_MFP_P00_SWD_CLK 0x00000001UL )SYS_MFP_P00_UART1_RX 0x00000100UL *SYS_MFP_P00_I2C0_SCL 0x00000101UL +SYS_MFP_P00_SPI0_CLK 0x00010000UL ,SYS_MFP_P00_LL_DBG_14 0x00010001UL -SYS_MFP_P00_MDM_DBG_11 0x00010100UL .SYS_MFP_P00_RESERVED 0x00010101UL /SYS_MFP_P00_Msk 0x00010101UL 1SYS_MFP_P01_GPIO 0x00000000UL 2SYS_MFP_P01_SWD_DAT 0x00000002UL 3SYS_MFP_P01_UART1_TX 0x00000200UL 4SYS_MFP_P01_I2C0_SDA 0x00000202UL 5SYS_MFP_P01_SPI0_CS 0x00020000UL 6SYS_MFP_P01_LL_DBG_15 0x00020002UL 7SYS_MFP_P01_MDM_DBG_12 0x00020200UL 8SYS_MFP_P01_RESERVED 0x00020202UL 9SYS_MFP_P01_Msk 0x00020202UL ;SYS_MFP_P02_GPIO 0x00000000UL <SYS_MFP_P02_UART0_CTS 0x00000004UL =SYS_MFP_P02_SPI1_MISO 0x00000400UL >SYS_MFP_P02_PWM_CH3 0x00000404UL ?SYS_MFP_P02_UART1_CTS 0x00040000UL @SYS_MFP_P02_LL_DBG_8 0x00040004UL ASYS_MFP_P02_MDM_DBG_19 0x00040400UL BSYS_MFP_P02_RESERVED 0x00040404UL CSYS_MFP_P02_Msk 0x00040404UL ESYS_MFP_P03_GPIO 0x00000000UL FSYS_MFP_P03_UART0_CTS 0x00000008UL GSYS_MFP_P03_SPI0_CS 0x00000800UL HSYS_MFP_P03_PWM_CH2 0x00000808UL ISYS_MFP_P03_TIMER0_CNT_OUT 0x00080000UL JSYS_MFP_P03_LL_DBG_8 0x00080008UL KSYS_MFP_P03_MDM_DBG_5 0x00080800UL LSYS_MFP_P03_RESERVED 0x00080808UL MSYS_MFP_P03_Msk 0x00080808UL OSYS_MFP_P04_GPIO 0x00000000UL PSYS_MFP_P04_UART0_RTS 0x00000010UL QSYS_MFP_P04_SPI0_CLK 0x00001000UL RSYS_MFP_P04_PWM_CH3 0x00001010UL SSYS_MFP_P04_TIMER0_EXT 0x00100000UL TSYS_MFP_P04_LL_DBG_9 0x00100010UL USYS_MFP_P04_MDM_DBG_6 0x00101000UL VSYS_MFP_P04_RESERVED 0x00101010UL WSYS_MFP_P04_Msk 0x00101010UL YSYS_MFP_P05_GPIO 0x00000000UL ZSYS_MFP_P05_UART0_TX 0x00000020UL [SYS_MFP_P05_SPI0_MISO 0x00002000UL \SYS_MFP_P05_PWM_CH4 0x00002020UL ]SYS_MFP_P05_EXT_STADC 0x00200000UL ^SYS_MFP_P05_LL_DBG_12 0x00200020UL _SYS_MFP_P05_MDM_DBG_9 0x00202000UL `SYS_MFP_P05_RESERVED 0x00202020UL aSYS_MFP_P05_Msk 0x00202020UL cSYS_MFP_P06_GPIO 0x00000000UL dSYS_MFP_P06_UART0_RX 0x00000040UL eSYS_MFP_P06_SPI0_MISO 0x00004000UL fSYS_MFP_P06_PWM_CH5 0x00004040UL gSYS_MFP_P06_TIMER1_EXT 0x00400000UL hSYS_MFP_P06_LL_DBG_13 0x00400040UL iSYS_MFP_P06_MDM_DBG_3 0x00404000UL jSYS_MFP_P06_AHB_CLK 0x00404040UL kSYS_MFP_P06_Msk 0x00404040UL mSYS_MFP_P07_GPIO 0x00000000UL nSYS_MFP_P07_UART1_RX 0x00000080UL oSYS_MFP_P07_I2C0_SCL 0x00008000UL pSYS_MFP_P07_SPI0_MOSI 0x00008080UL qSYS_MFP_P07_PWM_CH0 0x00800000UL rSYS_MFP_P07_LL_DBG_10 0x00800080UL sSYS_MFP_P07_MDM_DBG_7 0x00808000UL tSYS_MFP_P07_RESERVED 0x00808080UL uSYS_MFP_P07_Msk 0x00808080UL xSYS_MFP_P10_GPIO 0x00000000UL ySYS_MFP_P10_UART1_TX 0x00000001UL zSYS_MFP_P10_I2C0_SDA 0x00000100UL {SYS_MFP_P10_SPI0_MISO 0x00000101UL |SYS_MFP_P10_PWM_CH5 0x00010000UL }SYS_MFP_P10_LL_DBG_11 0x00010001UL ~SYS_MFP_P10_MDM_DBG_8 0x00010100UL SYS_MFP_P10_RESERVED 0x00010101UL SYS_MFP_P10_Msk 0x00010101UL SYS_MFP_P11_GPIO 0x00000000UL SYS_MFP_P11_UART1_RTS 0x00000002UL SYS_MFP_P11_SPI0_MOSI 0x00000200UL
SYS_MFP_P11_PWM_CH7 0x00000202UL SYS_MFP_P11_CLK_32K 0x00020000UL SYS_MFP_P11_LL_DBG_9 0x00020002UL SYS_MFP_P11_MDM_DBG_0 0x00020200UL SYS_MFP_P11_UART0_TX 0x00020202UL SYS_MFP_P11_Msk 0x00020202UL SYS_MFP_P12_GPIO 0x00000000UL SYS_MFP_P12_UART0_RX 0x00000004UL SYS_MFP_P12_PWM_CH4 0x00000400UL SYS_MFP_P12_TIMER0_CNT_OUT 0x00000404UL SYS_MFP_P12_UART1_TX 0x00040000UL SYS_MFP_P12_LL_DBG_4 0x00040004UL SYS_MFP_P12_MDM_DBG_17 0X00040400UL SYS_MFP_P12_SPI0_MISO 0x00040404UL SYS_MFP_P12_Msk 0x00040404UL SYS_MFP_P13_GPIO 0x00000000UL SYS_MFP_P13_UART0_RTS 0x00000008UL SYS_MFP_P13_I2C0_SDA 0x00000800UL SYS_MFP_P13_PWM_CH3 0x00000808UL SYS_MFP_P13_LL_DBG_3 0x00080000UL SYS_MFP_P13_MDM_DBG_16 0x00080008UL SYS_MFP_P13_SPI1_CS 0x00080800UL SYS_MFP_P13_SPI0_CS 0x00080808UL SYS_MFP_P13_Msk 0x00080808UL SYS_MFP_P14_GPIO 0x00000000UL ¡SYS_MFP_P14_UART0_CTS 0x00000010UL ¢SYS_MFP_P14_I2C0_SCL 0x00001000UL £SYS_MFP_P14_PWM_CH2 0x00001010UL ¤SYS_MFP_P14_LL_DEBUG_2 0x00100000UL ¥SYS_MFP_P14_MDM_DBG_15 0x00100010UL ¦SYS_MFP_P14_SPI0_CLK 0x00101000UL §SYS_MFP_P14_RESERVED 0x00101010UL ¨SYS_MFP_P14_Msk 0x00101010UL ªSYS_MFP_P15_GPIO 0x00000000UL «SYS_MFP_P15_SPI0_CS 0x00000020UL ¬SYS_MFP_P15_PWM_CH5 0x00002000UL SYS_MFP_P15_TIMER0_EXT 0x00002020UL ®SYS_MFP_P15_UART0_RX 0x00200000UL ¯SYS_MFP_P15_LL_DBG_5 0x00200020UL °SYS_MFP_P15_MDM_DBG_18 0x00202000UL ±SYS_MFP_P15_RESERVED 0x00202020UL ²SYS_MFP_P15_Msk 0x00202020UL ´SYS_MFP_P16_GPIO 0x00000000UL µSYS_MFP_P16_UART0_TX 0x00000040UL ¶SYS_MFP_P16_TIMER2_CNT_OUT 0x00004000UL ·SYS_MFP_P16_PWM_CH0 0x00004040UL ¸SYS_MFP_P16_LL_DBG_0 0x00400000UL ¹SYS_MFP_P16_MDM_DBG_13 0x00400040UL ºSYS_MFP_P16_SPI1_CLK 0x00404000UL »SYS_MFP_P16_I2C0_SCL 0x00404040UL ¼SYS_MFP_P16_Msk 0x00404040UL ¾SYS_MFP_P17_GPIO 0x00000000UL ¿SYS_MFP_P17_UART0_RX 0x00000080UL ÀSYS_MFP_P17_TIMER2_EXT 0x00008000UL ÁSYS_MFP_P17_PWM_CH1 0x00008080UL ÂSYS_MFP_P17_LL_DBG_1 0x00800000UL ÃSYS_MFP_P17_MDM_DBG_14 0x00800080UL ÄSYS_MFP_P17_RCH 0x00808000UL ÅSYS_MFP_P17_RESERVED 0x00808080UL ÆSYS_MFP_P17_Msk 0x00808080UL ÉSYS_MFP_P20_GPIO 0x00000000UL ÊSYS_MFP_P20_SPI1_MISO 0x00000001UL ËSYS_MFP_P20_PWM_CH6 0x00000100UL ÌSYS_MFP_P20_TADC_CLK 0x00000101UL ÍSYS_MFP_P20_LL_DBG_6 0x00010000UL ÎSYS_MFP_P20_MDM_DBG_2 0x00010001UL ÏSYS_MFP_P20_XTL_C1_CLK 0x00010100UL ÐSYS_MFP_P20_RESERVED 0x00010101UL ÑSYS_MFP_P20_Msk 0x00010101UL ÓSYS_MFP_P21_GPIO 0x00000000UL ÔSYS_MFP_P21_SPI1_MOSI 0x00000002UL ÕSYS_MFP_P21_PWM_CH7 0x00000200UL ÖSYS_MFP_P21_TADC_VLD 0x00000202UL ×SYS_MFP_P21_LL_DBG_7 0x00020000UL ØSYS_MFP_P21_MDM_DBG_1 0x00020002UL ÙSYS_MFP_P21_XTL_C2_CLK 0x00020200UL ÚSYS_MFP_P21_RESERVED 0x00020202UL ÛSYS_MFP_P21_Msk 0x00020202UL ÝSYS_MFP_P22_GPIO 0x00000000UL ÞSYS_MFP_P22_SPI1_CLK 0x00000004UL ßSYS_MFP_P22_PWM_CH0 0x00000400UL àSYS_MFP_P22_RESERVED 0x00000404UL áSYS_MFP_P22_TADC_DATl 0x00040000UL âSYS_MFP_P22_MDM_DBG_0 0x00040004UL ãSYS_MFP_P22_SPI0_MOSI 0x00040400UL äSYS_MFP_P22_RESERVED1 0x00040404UL åSYS_MFP_P22_Msk 0x00040404UL çSYS_MFP_P23_GPIO 0x00000000UL èSYS_MFP_P23_SPI1_CS 0x00000008UL éSYS_MFP_P23_PWM_CH1 0x00000800UL êSYS_MFP_P23_DPLL_DIV8 0x00000808UL ëSYS_MFP_P23_TADC_DATH 0x00080000UL ìSYS_MFP_P23_MDM_DBG_10 0x00080008UL íSYS_MFP_P23_I2C0_SCL 0x00080800UL îSYS_MFP_P23_RESERVED 0x00080808UL ïSYS_MFP_P23_Msk 0x00080808UL ñSYS_MFP_P24_GPIO 0x00000000UL òSYS_MFP_P24_SPI1_MISO 0x00000010UL óSYS_MFP_P24_UART1_RX 0x00001000UL ôSYS_MFP_P24_PWM_CH2 0x00001010UL õSYS_MFP_P24_TIMER1_CNT_OUT 0x00100000UL öSYS_MFP_P24_MDM_DBG_4 0x00100010UL ÷SYS_MFP_P24_RESERVED 0x00101000UL øSYS_MFP_P24_RESERVED1 0x00101010UL ùSYS_MFP_P24_Msk 0x00101010UL ûSYS_MFP_P25_GPIO 0x00000000UL üSYS_MFP_P25_SPI1_MOSI 0x00000020UL ýSYS_MFP_P25_UART1_TX 0x00002000UL þSYS_MFP_P25_PWM_CH3 0x00002020UL ÿSYS_MFP_P25_MDM_DBG_5 0x00200000UL SYS_MFP_P25_RESERVED 0x00200020UL SYS_MFP_P25_I2C0_SDA 0x00202000UL SYS_MFP_P25_RESERVED1 0x00202020UL SYS_MFP_P25_Msk 0x00202020UL
SYS_MFP_P26_GPIO 0x00000000UL SYS_MFP_P26_UART1_RTS 0x00000040UL SYS_MFP_P26_PWM_CH4 0x00004000UL SYS_MFP_P26_SPI1_CS 0x00004040UL SYS_MFP_P26_MDM_DBG_4 0x00400000UL SYS_MFP_P26_MDM_DBG_10 0x00400040UL SYS_MFP_P26_RESERVED 0x00404000UL SYS_MFP_P26_RESERVED1 0x00404040UL SYS_MFP_P26_Msk 0x00404040UL SYS_MFP_P27_GPIO 0x00000000UL SYS_MFP_P27_UART1_CTS 0x00000080UL SYS_MFP_P27_PWM_CH5 0x00008000UL SYS_MFP_P27_SPI1_CLK 0x00008080UL SYS_MFP_P27_RESERVED 0x00800000UL SYS_MFP_P27_MDM_DBG_20 0x00800080UL SYS_MFP_P27_XTH 0x00808000UL SYS_MFP_P27_RESERVED1 0x00808080UL SYS_MFP_P27_Msk 0x00808080UL SYS_MFP_P30_GPIO 0x00000000UL SYS_MFP_P30_UART1_RX 0x00000001UL SYS_MFP_P30_PWM_CH6 0x00000100UL SYS_MFP_P30_SPI1_MISO 0x00000101UL SYS_MFP_P30_MDM_DBG_10 0x00010000UL SYS_MFP_P30_RESERVED 0x00010001UL SYS_MFP_P30_RESERVED1 0x00010100UL ¡SYS_MFP_P30_RESERVED2 0x00010101UL ¢SYS_MFP_P30_Msk 0x00010101UL ¤SYS_MFP_P31_GPIO 0x00000000UL ¥SYS_MFP_P31_UART1_TX 0x00000002UL ¦SYS_MFP_P31_PWM_CH7 0x00000200UL §SYS_MFP_P31_SPI1_MOSI 0x00000202UL ¨SYS_MFP_P31_RESERVED 0x00020000UL ©SYS_MFP_P31_RESERVED1 0x00020002UL ªSYS_MFP_P31_RESERVED2 0x00020200UL «SYS_MFP_P31_RESERVED3 0x00020202UL ¬SYS_MFP_P31_Msk 0x00020202UL ¶SYS_SET_MFP(Port,Bit,Func) (SYS->Port ## _MFP = (SYS->Port ## _MFP & ~SYS_MFP_ ## Port ## Bit ## _Msk) | SYS_MFP_ ## Port ## Bit ## _ ## Func) l a ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\ pan_sys.h 0
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..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_sys.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil <ÃSYS_UnlockReg <²ÔSYS_LockReg Â Ã Ä __PAN_CLK_H__ CLK_APB1_WDTSEL_MILLI_PULSE (0x00010000UL) CLK_APB1_WDTSEL_RCL32K (0x00000000UL) CLK_APB1_WWDTSEL_MILLI_PULSE (0x00000000UL) CLK_APB1_WWDTSEL_RCL32K (0x00020000UL) "CLK_APB1_TMR0SEL_APB1CLK (0x00000000UL) #CLK_APB1_TMR0SEL_RCL32K (0x00040000UL) $CLK_APB1_TMR0SEL_TM0 (0x00080000UL) &CLK_APB2_TMR1SEL_APB2CLK (0x00000000UL) 'CLK_APB2_TMR1SEL_RCL32K (0x00000100UL) (CLK_APB2_TMR1SEL_TM1 (0x00000200UL) *CLK_APB2_TMR2SEL_APB2CLK (0x00000000UL) +CLK_APB2_TMR2SEL_RCL32K (0x00000400UL) ,CLK_APB2_TMR2SEL_TM2 (0x00000800UL) .CLK_APB1_PWM_CH01_SEL_APB (0x00000000UL) /CLK_APB1_PWM_CH01_SEL_CLK32K (0x00100000UL) 0CLK_APB1_PWM_CH23_SEL_APB (0x00000000UL) 1CLK_APB1_PWM_CH23_SEL_CLK32K (0x00200000UL) 2CLK_APB1_PWM_CH45_SEL_APB (0x00000000UL) 3CLK_APB1_PWM_CH45_SEL_CLK32K (0x00400000UL) 4CLK_APB1_PWM_CH67_SEL_APB (0x00000000UL) 5CLK_APB1_PWM_CH67_SEL_CLK32K (0x00800000UL) ;FREQ_1MHZ (1000000) <FREQ_8MHZ (8000000) =FREQ_16MHZ (16000000) >FREQ_25MHZ (25000000) ?FREQ_32MHZ (32000000) @FREQ_48MHZ (48000000) AFREQ_64MHZ (64000000) BFREQ_96MHZ (96000000) CFREQ_50MHZ (50000000) DFREQ_72MHZ (72000000) EFREQ_100MHZ (100000000) LCLK_SYS_SRCSEL_RCH ((uint32_t)0x00000000) MCLK_SYS_SRCSEL_XTH ((uint32_t)0x00000100) NCLK_SYS_SRCSEL_DPLL ((uint32_t)0x00000200) UCLK_DPLL_REF_CLKSEL_RCH ((uint32_t)0x00000000) VCLK_DPLL_REF_CLKSEL_XTH ((uint32_t)0x00000008) WCLK_DPLL_OUT_48M ((uint32_t)0x00000000) XCLK_DPLL_OUT_64M ((uint32_t)0x00000004) `CLK_APB1Periph_I2C0 ((uint32_t)0x00000001) aCLK_APB1Periph_SPI0 ((uint32_t)0x00000002) bCLK_APB1Periph_UART0 ((uint32_t)0x00000008) cCLK_APB1Periph_PWM0_CH01 ((uint32_t)0x00000010) dCLK_APB1Periph_PWM0_CH23 ((uint32_t)0x00000020) eCLK_APB1Periph_PWM0_CH45 ((uint32_t)0x00000040) fCLK_APB1Periph_PWM0_CH67 ((uint32_t)0x00000080) gCLK_APB1Periph_PWM0_EN ((uint32_t)0x00000100) hCLK_APB1Periph_ADC ((uint32_t)0x00000200) iCLK_APB1Periph_WDT ((uint32_t)0x00000400) jCLK_APB1Periph_WWDT ((uint32_t)0x00000800) kCLK_APB1Periph_TMR0 ((uint32_t)0x00001000) lCLK_APB1Periph_MILI_CLK ((uint32_t)0x00002000) mCLK_APB1Periph_All ((uint32_t)0x00003ffb) uCLK_APB2Periph_SPI1 ((uint32_t)0x00000002) vCLK_APB2Periph_UART1 ((uint32_t)0x00000008) wCLK_APB2Periph_TMR1 ((uint32_t)0x00000010) xCLK_APB2Periph_TMR2 ((uint32_t)0x00000020) yCLK_APB2Periph_All ((uint32_t)0x0000003a) CLK_AHBPeriph_DMAC ((uint32_t)0x00000001) CLK_AHBPeriph_GPIO ((uint32_t)0x00000002) CLK_AHBPeriph_SYSTICK ((uint32_t)0x00000004) CLK_AHBPeriph_APB1 ((uint32_t)0x00000008) CLK_AHBPeriph_APB2 ((uint32_t)0x00000010)
CLK_AHBPeriph_AHB ((uint32_t)0x00000020) CLK_AHBPeriph_BLE_32M ((uint32_t)0x00000040) CLK_AHBPeriph_BLE_32K ((uint32_t)0x00000080) CLK_AHBPeriph_ROM ((uint32_t)0x00000400) CLK_AHBPeriph_EFUSE ((uint32_t)0x00000800) CLK_AHBPeriph_USB_AHB ((uint32_t)0x00002000) CLK_AHBPeriph_USB_48M ((uint32_t)0x00004000) CLK_AHBPeriph_All ((uint32_t)0x00006CFF) CLK_DivideSource_Ahb (1) CLK_DivideSource_Apb1 (2) CLK_DivideSource_Apb2 (4) CLK_RCL_SELECT (0) CLK_RCH_SELECT (1) CLK_XTL_SELECT (2) CLK_XTH_SELECT (3) CLK_DPLL_SELECT (4) ¢CLK_STABLE_STATUS_Pos (24) £CLK_STABLE_STATUS_Msk (0x1ul << CLK_STABLE_STATUS_Pos) ¥CLKTRIM_CALC_CLK_SEL_32K (0) ¦CLKTRIM_CALC_CLK_SEL_32M (1) ¨CLKTRIM_QDEC_CLK_SEL_APB (0) ©CLKTRIM_QDEC_CLK_SEL_32K (1) «CLKTRIM_KSCAN_CLK_SEL_APB (0) ¬CLKTRIM_KSCAN_CLK_SEL_32K (1) ³DMA_RST ((0x0<<24) | CLK_IPRST0_DMARST_Pos ) ´LL_RST ((0x0<<24) | CLK_IPRST0_RFRST_Pos ) µEFUSE_RST ((0x0<<24) | CLK_IPRST0_EFUSERST_Pos ) ¶USB_RST ((0x0<<24) | CLK_IPRST0_USBRST_Pos ) ·MDMSTB_RST ((0x0<<24) | CLK_IPRST0_MDMSTDBYRST_Pos ) ¸MDM_RST ((0x0<<24) | CLK_IPRST0_MDMRST_Pos ) ¹I2C0_RST ((0x4<<24) | CLK_IPRST1_I2C0RST_Pos ) ºSPI0_RST ((0x4<<24) | CLK_IPRST1_SPI0RST_Pos ) »SPI1_RST ((0x4<<24) | CLK_IPRST1_SPI1RST_Pos ) ¼UART0_RST ((0x4<<24) | CLK_IPRST1_UART0RST_Pos ) ½UART1_RST ((0x4<<24) | CLK_IPRST1_UART1RST_Pos ) ¾PWM0_RST ((0x4<<24) | CLK_IPRST1_PWM0RST_Pos ) ¿ADC_RST ((0x4<<24) | CLK_IPRST1_ADCRST_Pos ) ÀWDT_RST ((0x4<<24) | CLK_IPRST1_WDTRST_Pos ) ÁWWDT_RST ((0x4<<24) | CLK_IPRST1_WWDTRST_Pos ) ÂTMR0_RST ((0x4<<24) | CLK_IPRST1_TMR0RST_Pos ) ÃTMR1_RST ((0x4<<24) | CLK_IPRST1_TMR1RST_Pos ) ÄTMR2_RST ((0x4<<24) | CLK_IPRST1_TMR2RST_Pos ) ÅGPIO_RST ((0x4<<24) | CLK_IPRST1_GPIORST_Pos ) ÆCLKTRIM_RST ((0x4<<24) | CLK_IPRST1_TRIMRST_Pos ) ÎCLK_BODCTL_BOD_INT_EN (0UL<<CLK_BODCTL_BODRSTEN_Pos_3v) ÏCLK_BODCTL_BOD_RST_EN (1UL<<CLK_BODCTL_BODRSTEN_Pos_3v) ÐCLK_BODCTL_BODSEL_1_75V (0UL<<CLK_BODCTL_BODSEL_Pos_3v) ÑCLK_BODCTL_BODSEL_1_95V (1UL<<CLK_BODCTL_BODSEL_Pos_3v) ÒCLK_BODCTL_BODSEL_2_15V (2UL<<CLK_BODCTL_BODSEL_Pos_3v) ÓCLK_BODCTL_BODSEL_2_35V (3UL<<CLK_BODCTL_BODSEL_Pos_3v) ÔCLK_BODCTL_BODSEL_2_55V (4UL<<CLK_BODCTL_BODSEL_Pos_3v) ÕCLK_BODCTL_BODSEL_2_75V (5UL<<CLK_BODCTL_BODSEL_Pos_3v) ÖCLK_BODCTL_BODSEL_2_95V (6UL<<CLK_BODCTL_BODSEL_Pos_3v) ßCLK_BLDBCTL_BODDBSEL_2POW0 0x00000001UL àCLK_BLDBCTL_BODDBSEL_2POW1 0x00000002UL áCLK_BLDBCTL_BODDBSEL_2POW2 0x00000004UL âCLK_BLDBCTL_BODDBSEL_2POW3 0x00000008UL ãCLK_BLDBCTL_BODDBSEL_2POW4 0x00000010UL äCLK_BLDBCTL_BODDBSEL_2POW5 0x00000020UL ìCLK_BLDBCTL_LVRDBSEL_2POW0 0x00000100UL íCLK_BLDBCTL_LVRDBSEL_2POW1 0x00000200UL îCLK_BLDBCTL_LVRDBSEL_2POW2 0x00000400UL ïCLK_BLDBCTL_LVRDBSEL_2POW3 0x00000800UL ðCLK_BLDBCTL_LVRDBSEL_2POW4 0x00001000UL ñCLK_BLDBCTL_LVRDBSEL_2POW5 0x00002000UL l a ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\ pan_clk.h
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..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_clk.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil CLK_FLASH_CLKDIV_1 CLK_FLASH_CLKDIV_2 CLK_FLASH_CLKDIV_4 CLK_FLASH_CLKDIV_8 CLK_FLASH_CLKDIV_16 CLK_FLASH_CLKDIV_30 <¯øCLK_XthStartupConfig <×CLK_HCLKConfig $Y u32ClkDiv <CLK_PCLK1Config $Y u32ClkDiv <©CLK_PCLK2Config $Y u32ClkDiv <Ó¾CLK_SetDpllOutputFreq $Y freq <ýáCLK_EnableClkTrim $æ NewState <¥ïCLK_SelectClkTrimSrc $Y src <ÚûCLK_SetClkTrimCalClkDiv $I div \reg Y <CLK_SetFlashClkDiv $: div \reg Y Æ Ç È É __PAN_ADC_H__ ADC_INPUTRANGE_HIGH (1UL) ADC_INPUTRANGE_LOW (0UL) ADC_CH8_EXT (0UL) ADC_CH8_BGP (ADC_CHEN_CH8SEL_Msk) ADC_CMP0_LESS_THAN (0UL << ADC_CMP0_CMPCOND_Pos) !ADC_CMP1_LESS_THAN (0UL << ADC_CMP1_CMPCOND_Pos) "ADC_CMP0_GREATER_OR_EQUAL_TO (1ul << ADC_CMP0_CMPCOND_Pos) #ADC_CMP1_GREATER_OR_EQUAL_TO (1ul << ADC_CMP1_CMPCOND_Pos) $ADC_TRIGGER_BY_EXT_PIN (0UL << ADC_CTL_HWTRGSEL_Pos) %ADC_TRIGGER_BY_PWM (ADC_CTL_HWTRGSEL_Msk) &ADC_FALLING_EDGE_TRIGGER (0UL << ADC_CTL_HWTRGCOND_Pos) 'ADC_RISING_EDGE_TRIGGER (ADC_CTL_HWTRGCOND_Msk) ,ADC_ADIF_INT (ADC_STATUS_ADIF_Msk) -ADC_CMP0_INT (ADC_STATUS_ADCMPIF0_Msk) .ADC_CMP1_INT (ADC_STATUS_ADCMPIF1_Msk) /ADC_FIFO_FULL_INT (ADC_STATUS_INTFLG_FULL_Msk) 0ADC_FIFO_EMPTY_INT (ADC_STATUS_INTFLG_EMPTY_Msk) 1ADC_FIFO_OVER_INT (ADC_STATUS_INTFLG_OVER_Msk) 2ADC_FIFO_HALF_INT (ADC_STATUS_INTFLG_HALF_Msk) 8ADC_SAMPLE_CLOCK_0 (0UL) 9ADC_SAMPLE_CLOCK_1 (1UL) :ADC_SAMPLE_CLOCK_2 (2UL) ;ADC_SAMPLE_CLOCK_4 (3UL) <ADC_SAMPLE_CLOCK_8 (4UL) =ADC_SAMPLE_CLOCK_16 (5UL) >ADC_SAMPLE_CLOCK_32 (6UL) ?ADC_SAMPLE_CLOCK_64 (7UL) @ADC_SAMPLE_CLOCK_128 (8UL) AADC_SAMPLE_CLOCK_256 (9UL) BADC_SAMPLE_CLOCK_512 (10UL) CADC_SAMPLE_CLOCK_1024 (11UL) DADC_SEQMODE_TYPE_23SHUNT (0UL) EADC_SEQMODE_TYPE_1SHUNT (1UL) FADC_SEQMODE_MODESELECT_CH01 (0UL) GADC_SEQMODE_MODESELECT_CH12 (1UL) HADC_SEQMODE_MODESELECT_CH02 (2UL) IADC_SEQMODE_MODESELECT_ONE (3UL) JADC_SEQMODE_PWM0_RISING (0UL) KADC_SEQMODE_PWM0_CENTER (1UL) LADC_SEQMODE_PWM0_FALLING (2UL) MADC_SEQMODE_PWM0_PERIOD (3UL) NADC_SEQMODE_PWM2_RISING (4UL) OADC_SEQMODE_PWM2_CENTER (5UL) PADC_SEQMODE_PWM2_FALLING (6UL) QADC_SEQMODE_PWM2_PERIOD (7UL) RADC_SEQMODE_PWM4_RISING (8UL) SADC_SEQMODE_PWM4_CENTER (9UL) TADC_SEQMODE_PWM4_FALLING (10UL) UADC_SEQMODE_PWM4_PERIOD (11UL) VADC_SEQMODE_PWM6_RISING (12UL) WADC_SEQMODE_PWM6_CENTER (13UL) XADC_SEQMODE_PWM6_FALLING (14UL) YADC_SEQMODE_PWM6_PERIOD (15UL) \ADC_COMPARATOR_0 (0) ]ADC_COMPARATOR_1 (1) _ADC_FIFO_TRIG_LEVEL_HALF (0) `ADC_FIFO_TRIG_LEVEL_FULL (1) l a ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\ pan_adc.h ì
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..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_adc.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil float _Bool PADC_OPT_T [vqm_adc_opt qglobal_calc_vbat_mv Y ;ADC_GetConversionData Y $ADCx a__result Y "Ð ;ØADC_StatusFlag $ADCx $Y IntMask a__result <¦ADC_ClearStatusFlag $ADCx $Y IntMask <ǹADC_IntMask $ADCx $Y IntMask $æ NewState ;ÌADC_IsIntOccured $ADCx $Y IntMask a__result <ºßADC_ClearIntFlag $ADCx $Y IntMask ;èëADC_IsBusy $ADCx a__result ;÷ADC_IsDataOverrun $ADCx a__result ;ÐADC_IsDataValid $ADCx a__result <ðADC_PowerDown $ADCx <ADC_PowerOn $ADCx <º¡ADC_SequentialModeDisable $ADCx <î¬ADC_Trigger2Select $ADCx $æ NewState <¶ADC_DisableCompare0 $ADCx <ºÀADC_DisableCompare1 $ADCx <ÝÊADC_StartConvert $ADCx <ÿÓADC_StopConvert $ADCx <¤ ÞADC_TestModeEnable $ADCx <Ê èADC_TestModeDisable $ADCx <ý óADC_DmaModeEnable $ADCx $æ NewState <±
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ÿADC_SetClockDivider $ADCx $Y Divider <Ù
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ADC_Open $ADCx $Y ChMask < ADC_SelInputRange $ADCx $Y EnableHigh <¼ ¢ADC_TriggerDelay $ADCx $Y Data <ö ¸ADC_SetExtraSampleTime $ADCx $Y SampleTime ;¯ ÃADC_IsOneChConvertEnd $ADCx a__result <Þ ÏADC_ClearByHw $ADCx $æ NewState < ÛADC_LeftShiftEn $ADCx $æ NewState <Ã çADC_SubtractBiasEn $ADCx $æ NewState <ô óADC_SetBiasData $ADCx $Y BiasData <§ADC_SetFifoTrigLevel $ADCx $: Level <ÛADC_SeqModeOneChEn $ADCx $æ NewState *í@ chip_info : # ft_version : # adc_vdd_b ÿ # adc_vdd_k I # adc_vbg_k I # adc_vbg_b # adc_temp_volt I #
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current_temp_value # !adc_vbg_1v20_trim : #!rsvd_0x30 : # Äo
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adc_vbg_kb 9# adc_vbat_k I #, adc_vbat_b #. adc_vbat_dtemp_k #0 adc_vbat_dtemp_b #2 adc_temp_k #4 adc_ctrl2 Y #8 adc_extsmpt Y #< 4 ð ) m_adc_opt 9 global_calc_vbat_mv Ë Ì Í Î __PAN_FMC_H__ M32(adr) (*((vu32 *) (adr))) CMD_ERASE_PAGE (0X81) CMD_ERASE_SECTOR (0X20) CMD_ERASE_32K (0X52) !CMD_ERASE_64K (0Xd8) "CMD_ERASE_CHIP (0xc7) (CMD_READ_STATUS_L (0x05) )CMD_READ_STATUS_H (0x35) *CMD_WRITE_STATUS (0x01) 0OPS_WR_STU_REG_NOR (0x00) 1OPS_WR_STU_REG_ALL (0x01) 7CMD_FAST_READ (0x0b) 8CMD_NORM_READ (0x03) 9CMD_DREAD (0x3B) :CMD_2READ (0xBB) ;CMD_QREAD (0x6B) <CMD_4READ (0xEB) BCMD_BURST_READ (0x77) CBURST_READ_MODE_8 (0x00) DBURST_READ_MODE_16 (0x01) EBURST_READ_MODE_32 (0x02) FBURST_READ_MODE_64 (0x03) JCMD_TRIG (0x01) KCMD_WRITE_ENABLE (0x06) LCMD_WRITE_DISABLE (0x04) QFLASH_X1_MODE 0 RFLASH_X2_MODE 1 SFLASH_X4_MODE 2 VQUAD_ENABLE_Pos (9) WQUAD_ENABLE_Msk (0x1ul << QUAD_ENABLE_Pos) XWrite_Enable_Latch_Pos (1) YWrite_Enable_Latch_Msk (0x1ul << Write_Enable_Latch_Pos) ZWrite_In_Process_Pos (0) [Write_In_Process_Msk (0x1ul << Write_In_Process_Pos) \Long_Time_Op_Pos (17) ^PAGE_SIZE (256) _SECTOR_SIZE (4096) l a ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\ pan_fmc.h \
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..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_fmc.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil _Bool ;Ã FMC_IsBusyWorking $+fmc a__result *û memory_type_id : # memory_density_id : # S: d C )Ý_flash_ids manufacturer_id : # {#Ñ: uid Æ# PFLASH_IDS_T tqflash_ids Ý<«FMC_EnterDeepPowerDownMode $+fmc " <ÜFMC_ExitDeepPowerDownMode $+fmc ` ð flash_ids Ð Ñ Ò __PAN_DMAC_H__ DMAC_CHANNEL_NUMBER 2 DMA_INVLID_CHANNEL (~0ul) $DMAC_TransferType_Mem2Mem (0) %DMAC_TransferType_Mem2Per (1) &DMAC_TransferType_Per2Mem (2) 'DMAC_TransferType_Per2Per (3) +DMAC_FlowControl_DMA (0) ,DMAC_FlowControl_Peripheral (1) 2DMAC_BurstLen_1 (0) 3DMAC_BurstLen_4 (1) 4DMAC_BurstLen_8 (2) 5DMAC_BurstLen_16 (3) 6DMAC_BurstLen_32 (4) 7DMAC_BurstLen_64 (5) 8DMAC_BurstLen_128 (6) 9DMAC_BurstLen_256 (7) @DMAC_AddrChange_Increment (0) ADMAC_AddrChange_Decrement (1) BDMAC_AddrChange_NoChange (2) IDMAC_DataWidth_8 (0) JDMAC_DataWidth_16 (1) KDMAC_DataWidth_32 (2) LDMAC_DataWidth_64 (3) MDMAC_DataWidth_128 (4) NDMAC_DataWidth_256 (5) UDMAC_Peripheral_I2C0_Tx 0 VDMAC_Peripheral_I2C0_Rx 1 WDMAC_Peripheral_SPI0_Tx 2 XDMAC_Peripheral_SPI0_Rx 3 YDMAC_Peripheral_UART0_Tx 4 ZDMAC_Peripheral_UART0_Rx 5 ]DMAC_Peripheral_SPI1_Tx 8 ^DMAC_Peripheral_SPI1_Rx 9 _DMAC_Peripheral_UART1_Tx 10 `DMAC_Peripheral_UART1_Rx 11 aDMAC_Peripheral_ADC 12 bDMAC_Peripheral_USB_Rx 15 cDMAC_Peripheral_USB_Tx 14 hDMAC_HandshakePolarity_Low (1) iDMAC_HandshakePolarity_High (0) pDMAC_Handshake_Default (1) qDMAC_Handshake_Software (1) rDMAC_Handshake_Hardware (0) uDMAC_LockLevel_Tfr_Complete (0) vDMAC_LockLevel_Block_Complete (1) wDMAC_LockLevel_Transaction_Complete (2) |DMAC_ChannelPriority_0 (0) }DMAC_ChannelPriority_1 (1) ~DMAC_ChannelPriority_2 (2) DMAC_ChannelPriority_3 (3) DMAC_ChannelPriority_4 (4) DMAC_ChannelPriority_5 (5) DMAC_ChannelPriority_6 (6) DMAC_ChannelPriority_7 (7) DMAC_CHANNELALL_MASK (~((~0ul)<<DMAC_CHANNEL_NUMBER)) DMAC_FLAG_INDEX_TFR (0<<1) DMAC_FLAG_INDEX_BLK (1<<1) DMAC_FLAG_INDEX_SRCTFR (2<<1) DMAC_FLAG_INDEX_DSTTFR (3<<1) DMAC_FLAG_INDEX_ERR (4<<1) DMAC_FLAG_MASK_TFR (1ul<<(DMAC_FLAG_INDEX_TFR >>1)) DMAC_FLAG_MASK_BLK (1ul<<(DMAC_FLAG_INDEX_BLK >>1)) DMAC_FLAG_MASK_SRCTFR (1ul<<(DMAC_FLAG_INDEX_SRCTFR>>1)) DMAC_FLAG_MASK_DSTTFR (1ul<<(DMAC_FLAG_INDEX_DSTTFR>>1)) DMAC_FLAG_MASK_ERR (1ul<<(DMAC_FLAG_INDEX_ERR >>1)) DMAC_FLAG_MASK_ALL (0x1Ful) DMAC_ChannelMask(idx) (1ul<<(idx)) l b ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\ pan_dmac.h
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..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_dmac.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil )ä__DMAC_ChannelConfigTypeDef CTL_L Y # CTL_H Y # CFG_L Y # CFG_H Y # P__DMAC_ChannelConfigTypeDef ¯)¸
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DMAC_ChannelConfigTypeDef !IntEnable Y # !DataWidthDst Y # !DataWidthSrc Y # !AddrChangeDst Y # !AddrChangeSrc Y # !BurstLenDst Y # !BurstLenSrc Y # !GatherEnSrc Y # !ScatterEnDst Y # !__Rev0 Y # !TransferType Y #
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!FlowControl Y # !__Rev1 Y # !BlockSize Y # !Done Y #!__Rev3 Y # !__Rev4 Y #!ChannelPriority Y #!ChannelSuspend Y #!FifoEmpty Y #!HandshakeDst Y #!HandshakeSrc Y #!LockBus Y #!LockChannel Y #!LockBusLevel Y #!LockChannelLevel Y #!HandshakePolarityDst Y # !HandshakePolaritySrc Y # !__Rev6 Y #
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!AutoReloadSrc Y #!AutoReloadDst Y # !FlowControlMode Y # !FifoMode Y # !ProtectControl Y # !__Rev7 Y # !PeripheralSrc Y # !PeripheralDst Y # !__Rev8 Y # PDMAC_ChannelConfigTypeDef ; DMAC_IsChannelValid Y $ dma $Y ChIdx a__result Y "T ;ð DMAC_CombinedIntStatus Y $ dma $Y FlgMsk a__result Y ;¿ ¾DMAC_StatusFlag Y $ dma $Y ChIdx $Y FlgIdx a__result Y ; ÊDMAC_IntFlag Y $ dma $Y ChIdx $Y FlgIdx a__result Y ;Ú ÏDMAC_IntFlagMsk Y $ dma $Y ChIdx $Y FlgIdx a__result Y <ÛDMAC_ClrIntFlag $ dma $Y ChIdx $Y FlgIdx Ô Õ Ö __PAN_GPIO_H__ GPIO_PIN_MAX 8 xGPIO_PIN_ADDR(port,pin) (*((volatile uint32_t *)((GPIOBIT0_BASE+(0x20*(port))) + ((pin)<<2)))) yP00 GPIO_PIN_ADDR(0, 0) zP01 GPIO_PIN_ADDR(0, 1) {P02 GPIO_PIN_ADDR(0, 2) |P03 GPIO_PIN_ADDR(0, 3) }P04 GPIO_PIN_ADDR(0, 4) ~P05 GPIO_PIN_ADDR(0, 5) P06 GPIO_PIN_ADDR(0, 6) P07 GPIO_PIN_ADDR(0, 7) P10 GPIO_PIN_ADDR(1, 0) P11 GPIO_PIN_ADDR(1, 1) P12 GPIO_PIN_ADDR(1, 2) P13 GPIO_PIN_ADDR(1, 3)
P14 GPIO_PIN_ADDR(1, 4) P15 GPIO_PIN_ADDR(1, 5) P16 GPIO_PIN_ADDR(1, 6) P17 GPIO_PIN_ADDR(1, 7) P20 GPIO_PIN_ADDR(2, 0) P21 GPIO_PIN_ADDR(2, 1) P22 GPIO_PIN_ADDR(2, 2) P23 GPIO_PIN_ADDR(2, 3) P24 GPIO_PIN_ADDR(2, 4) P25 GPIO_PIN_ADDR(2, 5) P26 GPIO_PIN_ADDR(2, 6) P27 GPIO_PIN_ADDR(2, 7) P30 GPIO_PIN_ADDR(3, 0) P31 GPIO_PIN_ADDR(3, 1) óGPIO_EnableEINT0 GPIO_EnableInt GPIO_DisableEINT0 GPIO_DisableInt GPIO_EnableEINT1 GPIO_EnableInt GPIO_DisableEINT1 GPIO_DisableInt ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\ C:\Keil_v5\ARM\ARMCC\Bin\..\include\ pan_gpio.h stdint.h
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..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_gpio.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil _Bool ;ÔëGPIO_GetIntFlag $:gpio $Y u32PinMask a__result <GPIO_SetDebounceTime $clksrc $ñclksel ;¾GPIO_GetInData Y $:gpio a__result Y <ëGPIO_SetOutData $:gpio $Y data ;¢GPIO_GetOutData Y $:gpio a__result Y <ѼGPIO_Toggle $:gpio $Y u32PinMask <ÑGPIO_EnableInt $:gpio $Y u32Pin $¶IntAttribs <½áGPIO_DisableInt $:gpio $Y u32Pin ¢_GPIO_ModeDef GPIO_MODE_INPUT GPIO_MODE_OUTPUT GPIO_MODE_OPEN_DRAIN GPIO_MODE_QUASI PGPIO_ModeDef ½)¶_GPIO_IntAttrDef GPIO_INT_RISING GPIO_INT_FALLING GPIO_INT_BOTH_EDGE GPIO_INT_HIGH GPIO_INT_LOW PGPIO_IntAttrDef 67_GPIO_ClkSrcDef GPIO_DBCTL_DBCLKSRC_RCL GPIO_DBCTL_DBCLKSRC_HCLK PGPIO_ClkSrcDef ÍCñ _GPIO_ClkSelDef GPIO_DBCTL_DBCLKSEL_1 GPIO_DBCTL_DBCLKSEL_2 GPIO_DBCTL_DBCLKSEL_4 GPIO_DBCTL_DBCLKSEL_8 GPIO_DBCTL_DBCLKSEL_16 GPIO_DBCTL_DBCLKSEL_32 GPIO_DBCTL_DBCLKSEL_64 GPIO_DBCTL_DBCLKSEL_128 GPIO_DBCTL_DBCLKSEL_256 GPIO_DBCTL_DBCLKSEL_512 GPIO_DBCTL_DBCLKSEL_1024
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GPIO_DBCTL_DBCLKSEL_2048 GPIO_DBCTL_DBCLKSEL_4096 GPIO_DBCTL_DBCLKSEL_8192 GPIO_DBCTL_DBCLKSEL_16384 GPIO_DBCTL_DBCLKSEL_32768 PGPIO_ClkSelDef /]<º ¢GPIO_ClrIntFlag $:gpio $Y u32PinMask " <å »GPIO_ClrAllIntFlag $:gpio < ÔGPIO_DisableDebounce $:gpio $Y u32PinMask <Ô ãGPIO_EnableDebounce $:gpio $Y u32PinMask <òGPIO_DisableDigitalPath $:gpio $Y u32PinMask <ÉGPIO_EnableDigitalPath $:gpio $Y u32PinMask <GPIO_DisablePullupPath $:gpio $Y u32PinMask <¼GPIO_EnablePullupPath $:gpio $Y u32PinMask <ø®GPIO_DisablePulldownPath $:gpio $Y u32PinMask <³½GPIO_EnablePulldownPath $:gpio $Y u32PinMask <ëÌGPIO_DisableDoutMask $:gpio $Y u32PinMask <¢ÛGPIO_EnableDoutMask $:gpio $Y u32PinMask Ø Ù Ú __PAN_SPI_H__ jSPI_BAUD_RATE_DIV(x) ((x)?(x):(256)) l a ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\ pan_spi.h è
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..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_spi.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil _Bool ;ÐäSPI_IsSpiEnabled $´ SPIx a__result \tmpreg Y <ÿõSPI_EnableDmaTx $´ SPIx \tmpreg Y <¯SPI_DisableDmaTx $´ SPIx \tmpreg Y ;òSPI_IsDmaTxEnabled $´ SPIx a__result \tmpreg Y <¡¤SPI_EnableDmaRx $´ SPIx \tmpreg Y <ѳSPI_DisableDmaRx $´ SPIx \tmpreg Y ;ÂSPI_IsDmaRxEnabled $´ SPIx a__result \tmpreg Y <¾ÓSPI_SendData $´ SPIx $Y Data ;õÞSPI_ReceiveData Y $´ SPIx a__result Y <ªïSPI_EnableIrq $´ SPIx $Ëirq \tmpreg Y <àSPI_DisableIrq $´ SPIx $Ëirq \tmpreg Y ;©SPI_IsIrqEnabled $´ SPIx $Ëirq a__result \tmpreg Y ;ï¯ SPI_GetMskedActiveIrq Ë$´ SPIx a__result Ë\tmpreg Y ;·ÅSPI_IsIrqActive $´ SPIx $Ëirq a__result \tmpreg Y ; ÜSPI_IsRawIrqActive $´ SPIx $Ëirq a__result \tmpreg Y <¶ ðSPI_ClearIrq $´ SPIx $Ëirq \tmpreg Y ;ú SPI_GetRawActiveIrq Ë$´ SPIx a__result Ë\tmpreg Y ;¼
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SPI_IsTxFifoEmpty $´ SPIx a__result \tmpreg Y ;ý
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£SPI_IsTxFifoFull $´ SPIx a__result \tmpreg Y ;¿ ´SPI_IsRxFifoEmpty $´ SPIx a__result \tmpreg Y ; ÆSPI_IsRxFifoFull $´ SPIx a__result \tmpreg Y ;» ØSPI_IsBusy $´ SPIx a__result \tmpreg Y <è éSPI_TxLsbEnable $´ SPIx $enable < ôSPI_RxLsbEnable $´ SPIx $enable <¾ SPI_SetWireNum $´ SPIx $= num <õ SPI_DataCmdLineEnable $´ SPIx $æ NewState <§SPI_DataCmdSelCmdDat $´ SPIx $ cmdDat <ÒSPI_WriteReadCtrl $´ SPIx $Ú wr ËSPI_Irq SPI_IRQ_TX_HALF_EMPTY SPI_IRQ_RX_HALF_FULL SPI_IRQ_RX_TIMEOUT SPI_IRQ_RX_OVERRUN SPI_IRQ_ALL PSPI_IrqDef R$SPI_Role SPI_RoleMaster SPI_RoleSlave PSPI_RoleDef Ý.ÃSPI_DataFrameSize SPI_DataFrame_4b SPI_DataFrame_5b SPI_DataFrame_6b SPI_DataFrame_7b SPI_DataFrame_8b SPI_DataFrame_9b SPI_DataFrame_10b SPI_DataFrame_11b
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SPI_DataFrame_12b SPI_DataFrame_13b SPI_DataFrame_14b SPI_DataFrame_15b SPI_DataFrame_16b PSPI_DataFrameSizeDef !PÀSPI_BaudRateDiv SPI_BaudRateDiv_2 SPI_BaudRateDiv_4 SPI_BaudRateDiv_6 SPI_BaudRateDiv_8 SPI_BaudRateDiv_16 SPI_BaudRateDiv_32 SPI_BaudRateDiv_48 0SPI_BaudRateDiv_64 @SPI_BaudRateDiv_96 `SPI_BaudRateDiv_128 SPI_BaudRateDiv_160 SPI_BaudRateDiv_192 ÀSPI_BaudRateDiv_224 àSPI_BaudRateDiv_240 ðSPI_BaudRateDiv_250 ú PSPI_BaudRateDivDef _ gSPI_ClockPol SPI_ClockPolarityLow SPI_ClockPolarityHigh PSPI_ClockPolDef Ú
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uÿSPI_ClockPhase SPI_ClockPhaseFirstEdge SPI_ClockPhaseSecondEdge PSPI_ClockPhaseDef 4 êSPI_FrameFormat SPI_FormatMotorola SPI_FormatTi SPI_FormatMicrowire PSPI_FrameFormatDef ½SPI_WireNum SPI_WireNumThree SPI_WireNumFour PSPI_WireNumDef SPI_CmdDat SPI_CommandSelect SPI_DataSelect PSPI_CmdDatDef T ÚSPI_WriteReadSel SPI_3WireRead SPI_3WireWrite PSPI_WriteReadSelDef ¡ §*ï SPI_role # SPI_dataFrameSize C # SPI_CPOL # SPI_CPHA # SPI_baudRateDiv I # SPI_format ê # PSPI_InitTypeDef ö ½<´ÆSPI_EnableSpi $´ SPIx \tmpreg Y " <èÕSPI_DisableSpi $´ SPIx \tmpreg Y Ü Ý Þ __PAN_UART_H__ l b ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\ pan_uart.h è
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..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_uart.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil _Bool ;ÇUART_IsFifoEnabled $ZUARTx a__result tY ;âUART_GetTxFifoLevel : $ZUARTx a__result : ;ÅíUART_GetRxFifoLevel : $ZUARTx a__result : <çøUART_EnableAfc $ZUARTx <UART_DisableAfc $ZUARTx ;ÀUART_IsAfcEnabled $ZUARTx a__result <ìUART_SendData $ZUARTx $: Data <»UART_DisablePtime $ZUARTx ;ÉÆUART_IsPtimeEnabled $ZUARTx a__result ;êUART_IsIrqEnabled $ZUARTx $m irq a__result ;ÁõUART_GetIrqMasked : $ZUARTx a__result : ;ù UART_GetActiveEvent $ZUARTx a__result ;°UART_IsTxFifoEmpty $ZUARTx a__result ;æ¬UART_IsRxFifoFull $ZUARTx a__result <·UART_EnableHaltTX $ZUARTx <±ÂUART_DisableHaltTX $ZUARTx <ÓÍUART_EnableRts $ZUARTx <öØUART_DisableRts $ZUARTx < ãUART_Enable9BitData $ZUARTx <Å îUART_Disable9BitData $ZUARTx <ñ ùUART_EnableAddrMatchMode $ZUARTx <
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UART_DisableAddrMatchMode $ZUARTx <¿
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UART_SendAddr $ZUARTx <ô
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UART_SetReceiveAddress $ZUARTx $Y addr <ª ¨UART_SetTransmitAddress $ZUARTx $Y addr 8â æ$UART_GetLineStatus $ZUARTx a__result 9 ÷UART_EnableFifo $ZUARTx 9³ UART_ResetRxFifo $ZUARTx \val G 9Ø ²UART_ResetTxFifo $ZUARTx 9 ÂUART_SetTxTrigger $ZUARTx $Xlevel 9¸ ÓUART_SetRxTrigger $ZUARTx $ølevel 8ò ¥UART_ReceiveData : $ZUARTx a__result : 9°UART_EnablePtime $ZUARTx 9ÂÒUART_EnableIrq $ZUARTx $m irq 9îÞUART_DisableIrq $ZUARTx $m irq 8¥UART_IsTxFifoFull $ZUARTx a__result 8Ý¡UART_IsRxFifoEmpty $ZUARTx a__result ØUART_TxTrigger UART_TX_FIFO_EMPTY UART_TX_FIFO_TWO_CHARS UART_TX_FIFO_QUARTER_FULL UART_TX_FIFO_HALF_FULL PUART_TxTriggerDef Ý$øUART_RxTrigger UART_RX_FIFO_ONE_CHAR UART_RX_FIFO_QUARTER_FULL UART_RX_FIFO_HALF_FULL UART_RX_FIFO_TWO_LESS_THAN_FULL PUART_RxTriggerDef q0ÖUART_LineCtrl Uart_Line_5n1 Uart_Line_5n1_5 Uart_Line_5e1 Uart_Line_5e1_5 Uart_Line_5o1 Uart_Line_5o1_5 Uart_Line_5s1 8Uart_Line_5s1_5 <Uart_Line_5m1 (Uart_Line_5m1_5 ,Uart_Line_6n1 Uart_Line_6n2 Uart_Line_6e1 Uart_Line_6e2 Uart_Line_6o1 Uart_Line_6o2 Uart_Line_6s1 9Uart_Line_6s2 =Uart_Line_6m1 )Uart_Line_6m2 -Uart_Line_7n1 Uart_Line_7n2 Uart_Line_7e1 Uart_Line_7e2 Uart_Line_7o1
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Uart_Line_7o2 Uart_Line_7s1 :Uart_Line_7s2 >Uart_Line_7m1 *Uart_Line_7m2 .Uart_Line_8n1 Uart_Line_8n2 Uart_Line_8e1 Uart_Line_8e2 Uart_Line_8o1 Uart_Line_8o2 Uart_Line_8s1 ;Uart_Line_8s2 ?Uart_Line_8m1 +Uart_Line_8m2 / PUART_LineCtrlDef bíUART_Irq UART_IRQ_RECV_DATA_AVL UART_IRQ_THR_EMPTY UART_IRQ_LINE_STATUS UART_IRQ_MODEM_STATUS UART_IRQ_ALL PUART_IrqDef î sUART_Event UART_EVENT_MODEM UART_EVENT_NONE UART_EVENT_THR_EMPTY UART_EVENT_DATA UART_EVENT_LINE UART_EVENT_TIMEOUT PUART_EventDef UART_LineStatus UART_LINE_DATA_RDY UART_LINE_OVERRUN_ERR UART_LINE_PARITY_ERR UART_LINE_FRAME_ERR UART_LINE_BREAK_INT UART_LINE_THRE UART_LINE_TXSR_EMPTY @UART_LINE_RX_FIFO_ERR UART_LINE_ADDR_RCVD PUART_LineStatusDef ! §Ê UART_ModemStatus UART_MODEM_DCTS UART_MODEM_DDSR UART_MODEM_TERI UART_MODEM_DDCD UART_MODEM_CTS UART_MODEM_DSR UART_MODEM_RI @UART_MODEM_DCD PUART_ModemStatusDef !·* UART_BaudRate Y # UART_LineCtrl Ö # PUART_InitTypeDef æÅ<Ú ÐUART_EnableStickParity $ZUARTx "l < ÛUART_DisableStickParity $ZUARTx ;à ë%UART_GetModemStatus Ê$ZUARTx a__result Ê <ç UART_DisableFifo $ZUARTx à á â __PAN_I2C_H__ =I2C_DYNAMIC_TAR_UPDATE 0 DI2C_MODE_MASTER ((uint16_t)0x0021) EI2C_MODE_SLAVE ((uint16_t)0x0000) LIS_I2C_MODE(MODE) (((MODE) == I2C_MODE_MASTER) || ((MODE) == I2C_MODE_SLAVE)) TI2C_SPEED_STANDARD_MODE (uint16_t)(0x0002) UI2C_SPEED_FAST_MODE (uint16_t)(0x0004) VI2C_SPEED_HIGH_MODE (uint16_t)(0x0006) ^I2C_DutyCycle_16_9 ((uint16_t)0x4000) _I2C_DutyCycle_2 ((uint16_t)0xBFFF) `I2C_DutyCycle_1_1 ((uint16_t)0x0800) aI2C_DutyCycle_1_2 ((uint16_t)0x0400) fIS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || ((CYCLE) == I2C_DutyCycle_2)) mI2C_Direction_Transmitter ((uint16_t)0x0000) nI2C_Direction_Receiver ((uint16_t)0x0100) oIS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || ((DIRECTION) == I2C_Direction_Receiver)) vI2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) wI2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) xIS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || ((ADDRESS) == I2C_AcknowledgedAddress_10bit)) I2C_CMD_WR ((uint8_t)0x00) I2C_CMD_RD ((uint8_t)0x01) I2C_CMD_STOP ((uint8_t)0x02) I2C_CMD_RESTART ((uint8_t)0x04) I2C_RX_TL_0 ((uint8_t)0x00) I2C_RX_TL_1 ((uint8_t)0x01) I2C_RX_TL_2 ((uint8_t)0x02) I2C_RX_TL_3 ((uint8_t)0x03) I2C_RX_TL_4 ((uint8_t)0x04) I2C_RX_TL_5 ((uint8_t)0x05) I2C_RX_TL_6 ((uint8_t)0x06) I2C_RX_TL_7 ((uint8_t)0x07) I2C_RX_TL_8 ((uint8_t)0x08) I2C_TX_TL_0 ((uint8_t)0x00) I2C_TX_TL_1 ((uint8_t)0x01) I2C_TX_TL_2 ((uint8_t)0x02) I2C_TX_TL_3 ((uint8_t)0x03) I2C_TX_TL_4 ((uint8_t)0x04) I2C_TX_TL_5 ((uint8_t)0x05) I2C_TX_TL_6 ((uint8_t)0x06) I2C_TX_TL_7 ((uint8_t)0x07) I2C_TX_TL_8 ((uint8_t)0x08) ¥I2C_IT_RX_UNDER ((uint16_t)0x0001) ¦I2C_IT_RX_OVER ((uint16_t)0x0002) §I2C_IT_RX_FULL ((uint16_t)0x0004) ¨I2C_IT_TX_OVER ((uint16_t)0x0008) ©I2C_IT_TX_EMPTY ((uint16_t)0x0010) ªI2C_IT_RD_REQ ((uint16_t)0x0020) «I2C_IT_TX_ABORT ((uint16_t)0x0040) ¬I2C_IT_RX_DONE ((uint16_t)0x0080) I2C_IT_ACTIVITY ((uint16_t)0x0100) ®I2C_IT_STOP_DET ((uint16_t)0x0200) ¯I2C_IT_START_DET ((uint16_t)0x0400) °I2C_IT_GEN_CALL ((uint16_t)0x0800) ±I2C_IT_MST_ON_HOLD ((uint16_t)0x2000) ²I2C_IT_ALL ((uint16_t)0x2FFF) ´IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x0FFF) == 0x00) && ((IT) != (uint16_t)0x00)) ¶IS_I2C_GET_IT(IT) (((IT) == I2C_IT_RX_UNDER) || ((IT) == I2C_IT_RX_OVER) || ((IT) == I2C_IT_RX_FULL) || ((IT) == I2C_IT_TX_OVER) || ((IT) == I2C_IT_TX_EMPTY) || ((IT) == I2C_IT_RD_REQ) || ((IT) == I2C_IT_TX_ABORT) || ((IT) == I2C_IT_RX_DONE) || ((IT) == I2C_IT_ACTIVITY) || ((IT) == I2C_IT_STOP_DET) || ((IT) == I2C_IT_START_DET)|| ((IT) == I2C_IT_GEN_CALL)) ÁI2C_FLAG_SLV_ACTIVITY ((uint32_t)0x00000040) ÂI2C_FLAG_MST_ACTIVITY ((uint32_t)0x00000020) ÃI2C_FLAG_RFF ((uint32_t)0x00000010) ÄI2C_FLAG_RFNE ((uint32_t)0x00000008) ÅI2C_FLAG_TFE ((uint32_t)0x00000004) ÆI2C_FLAG_TFNF ((uint32_t)0x00000002) ÇI2C_FLAG_ACTIVITY ((uint32_t)0x00000001) ÈIS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x007F) == 0x00) && ((FLAG) != (uint16_t)0x00)) ÉIS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_ACTIVITY) || ((FLAG) == I2C_FLAG_TFNF) || ((FLAG) == I2C_FLAG_TFE) || ((FLAG) == I2C_FLAG_RFNE) || ((FLAG) == I2C_FLAG_RFF) || ((FLAG) == I2C_FLAG_MST_ACTIVITY) || ((FLAG) == I2C_FLAG_SLV_ACTIVITY)) ÓFLAG_MASK ((uint32_t)0x007F0FFF) ÔITEN_MASK ((uint16_t)0x2FFF) ÕIT_FLAG_MASK ((uint16_t)0x2FFF) l a ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\ pan_i2c.h
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..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_i2c.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil _Bool ;ÑÇI2C_AbortSrcCheck $?I2Cx $Y IC_MSK a__result <ÿÓI2C_SetSlaveAddr $?I2Cx $Y addr *ÿ I2C_ClockSpeed Y # I2C_Mode I # I2C_DutyCycle I # I2C_OwnAddress1 I # I2C_AcknowledgedAddress I #
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PI2C_InitTypeDef 8<¿áI2C_SetMode $?I2Cx $I Mode "[ <òI2C_SetTxTirggerLevel $?I2Cx $: ThresholdValue <¿I2C_SetRxTirggerLevel $?I2Cx $: ThresholdValue <èI2C_Cmd $?I2Cx $æ NewState <I2C_GeneralCallCmd $?I2Cx $æ NewState <Ó¦I2C_SendDataCmd $?I2Cx $: Data $: Cmd <û°I2C_SendCmd $?I2Cx $: Cmd ;²¹I2C_ReceiveData : $?I2Cx a__result : <ÖÂI2C_AbortTransfer $?I2Cx <ÍI2C_DMACmd $?I2Cx $æ NewState <¹×I2C_DMATransferDataLevel $?I2Cx $: Level <ïáI2C_DMAReceiveDataLevel $?I2Cx $: Level ;³ ùI2C_GetITStatus ¼ $?I2Cx $I I2C_IT a__result ¼ ;ú I2C_GetRawITStatus ¼ $?I2Cx $I I2C_IT a__result ¼ <µ
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ªI2C_ITConfig $?I2Cx $I I2C_IT $æ NewState <Ø
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´I2C_DisableAllIT $?I2Cx < ½I2C_ClearAllITPendingBit $?I2Cx ä å æ __PAN_TIMER_H__ aFIXED_DEVIATION (12) l c ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\ pan_timer.h
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..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_timer.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil _Bool ;ÄÄTIMER_IsActive $ü timer a__result <ãÏTIMER_Start $ü timer <ÙTIMER_Stop $ü timer < ãTIMER_Reset $ü timer <ÆîTIMER_EnableWakeup $ü timer <íøTIMER_DisableWakeup $ü timer <TIMER_EnableCaptureDebounce $ü timer <ÌTIMER_DisableCaptureDebounce $ü timer <TIMER_EnableEventCounterDebounce $ü timer <µ¢TIMER_DisableEventCounterDebounce $ü timer <جTIMER_EnableInt $ü timer <ü¶TIMER_DisableInt $ü timer <¦ÀTIMER_EnableCaptureInt $ü timer <ÑÊTIMER_DisableCaptureInt $ü timer ;ÖTIMER_GetIntFlag Y $ü timer a__result Y <°àTIMER_ClearIntFlag $ü timer ;èìTIMER_GetTFFlag Y $ü timer a__result Y <ûTIMER_ClearTFFlag $ü timer $Y timer_flag ;ÚTIMER_GetWakeupFlag Y $ü timer a__result Y < TIMER_ClearWakeupFlag $ü timer $Y wake_flag ;Ó ¢TIMER_GetCaptureIntFlag Y $ü timer a__result Y <
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¬TIMER_ClearCaptureIntFlag $ü timer ;½
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¸TIMER_GetCaptureFlag Y $ü timer a__result Y <ç
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ÂTIMER_ClearCaptureFlag $ü timer < ÐTIMER_SetCaptureSource $ü timer $% capSrc ;Ù ÚTIMER_GetCaptureData Y $ü timer a__result Y ; äTIMER_GetCounter Y $ü timer a__result Y <Î ïTIMER_SetTmrCounterMode $ü timer $Y u32CntMode É _TIMER_CntModeDef TIMER_ONESHOT_MODE TIMER_PERIODIC_MODE TIMER_TOGGLE_MODE TIMER_CONTINUOUS_MODE PTIMER_CntModeDef N%è_TIMER_CapModeDef TIMER_CAPTURE_FREE_COUNTING_MODE TIMER_CAPTURE_TRIGGER_COUNTING_MODE TIMER_CAPTURE_COUNTER_RESET_MODE PTIMER_CapModeDef á0Á_TIMER_CapEdgeDef TIMER_CAPTURE_FALLING_EDGE TIMER_CAPTURE_RISING_EDGE TIMER_CAPTURE_BOTH_EDGE TIMER_CAPTURE_FALLING_THEN_RISING_EDGE TIMER_CAPTURE_RISING_THEN_FALLING_EDGE PTIMER_CapEdgeDef =®_TIMER_EvtCntEdgeDef TIMER_COUNTER_FALLING_EDGE TIMER_COUNTER_RISING_EDGE PTIMER_EvtCntEdgeDef YG¥_TIMER_CapSrcDef TIMER_CAPTURE_SOURCE_EXT_PIN TIMER_CAPTURE_SOURCE_32K_OUTPUT PTIMER_CapSrcDef ÉS¦_TIMER0_CmpSelDef TMR0_COMPARATOR_SEL_CMP TMR0_COMPARATOR_SEL_CMP1 TMR0_COMPARATOR_SEL_CMP2 PTIMER0_CmpSelDef < ^<ütTIMER_EnableCapture $ü timer $hcapMode $AcapEdge " <ªTIMER_DisableCapture $ü timer <åTIMER_EnableEventCounter $ü timer $®evtCntEdge <TIMER_DisableEventCounter $ü timer <˨TIMER_SetPrescaleValue $ü timer $Y u32Value <·TIMER_SetCountingMode $ü timer $ÉcntMode è é ê __PAN_PWM_H__ PWM_CHANNEL_NUM (8) PWM_CH0 0x0 !PWM_CH1 0x1 "PWM_CH2 0x2 #PWM_CH3 0x3 $PWM_CH4 0x4 %PWM_CH5 0x5 &PWM_CH6 0x6 'PWM_CH7 0x7 l a ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\ pan_pwm.h x
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..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_pwm.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil Ö_PWM_ClkSrcSelDef PWM_CLK_SRC_APB PWM_CLK_SRC_RCL PWM_CLK_SRC_XTL PPWM_ClkSrcSelDef 6ê_PWM_ClkDivDef PWM_CLK_DIV_1 PWM_CLK_DIV_2 PWM_CLK_DIV_4 PWM_CLK_DIV_8 PWM_CLK_DIV_16 PWM_CLK_DIRECT PPWM_ClkDivDef nCÂ_PWM_AlignedTypeDef PWM_EDGE_ALIGNED PWM_CENTER_ALIGNED PPWM_AlignedTypeDef ÿM¯_PWM_IntPeriodTypeDef PWM_PERIOD_INT_UNDERFLOW PWM_PERIOD_INT_MATCH_CNR PPWM_IntPeriodTypeDef \W¾_PWM_OperateTypeDef OPERATION_EDGE_ALIGNED OPERATION_CENTER_ALIGNED OPERATION_PRECISE_CENTER_ALIGNED PPWM_OperateTypeDef Ëb _PWM_CntModeDef PWM_CNTMODE_ONE_SHOT PWM_CNTMODE_AUTO_RELOAD PPWM_CntModeDef Xl<ìvPWM_EnableOutput $ìpwm $Y u32ChannelMask "ô <ªPWM_DisableOutput $ìpwm $Y u32ChannelMask <àPWM_StartChannel $ìpwm $Y u32ChannelNum < PWM_StopChannel $ìpwm $Y u32ChannelNum <ß ¥PWM_EnableDeadZone $ìpwm $Y u32ChannelNum $Y u32Duration <
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µPWM_DisableDeadZone $ìpwm $Y u32ChannelNum <Ï
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ÃPWM_EnableCMPDInt $ìpwm $Y u32ChannelNum < ÎPWM_DisableCMPDInt $ìpwm $Y u32ChannelNum <Á ÙPWM_ClearCMPDIntFlag $ìpwm $Y u32ChannelNum ; æPWM_GetCMPDIntFlag Y $ìpwm $Y u32ChannelNum a__result Y <Ç ñPWM_EnablePeriodInt $ìpwm $Y u32ChannelNum < üPWM_DisablePeriodInt $ìpwm $Y u32ChannelNum <½ PWM_ClearPeriodIntFlag $ìpwm $Y u32ChannelNum ;PWM_GetPeriodIntFlag Y $ìpwm $Y u32ChannelNum a__result Y <áPWM_EnableZeroInt $ìpwm $Y u32ChannelNum <û¬PWM_DisableZeroInt $ìpwm $Y u32ChannelNum <µ·PWM_ClearZeroIntFlag $ìpwm $Y u32ChannelNum ;ÄPWM_GetZeroIntFlag Y $ìpwm $Y u32ChannelNum a__result Y <¹ÏPWM_EnableCMPUInt $ìpwm $Y u32ChannelNum <ñÚPWM_DisableCMPUInt $ìpwm $Y u32ChannelNum <«åPWM_ClearCMPUIntFlag $ìpwm $Y u32ChannelNum ;øòPWM_GetCMPUIntFlag Y $ìpwm $Y u32ChannelNum a__result Y <ÃPWM_EnableCenterInt $ìpwm $Y u32ChannelNum $¯IntPeriodType <ýPWM_DisableCenterInt $ìpwm $Y u32ChannelNum <¹PWM_ClearCenterIntFlag $ìpwm $Y u32ChannelNum ;¦PWM_GetCenterIntFlag Y $ìpwm $Y u32ChannelNum a__result Y <³°PWM_EnableIndependentMode $ìpwm <à¹PWM_EnableComplementaryMode $ìpwm <ÃPWM_DisableComplementaryMode $ìpwm <³ÍPWM_EnableGroupMode $ìpwm <Ù×PWM_DisableGroupMode $ìpwm <ýáPWM_EnableSyncMode $ìpwm <¢ëPWM_DisableSyncMode $ìpwm <ëùPWM_SetPrescaler $ìpwm $Y u32ChannelNum $Y u32Prescaler <£PWM_ResetPrescaler $ìpwm $Y u32ChannelNum <ãPWM_SetDivider $ìpwm $Y u32ChannelNum $êDivider < ¥PWM_SetCMR $ìpwm $Y u32ChannelNum $Y u32CMR <ݲPWM_SetCNR $ìpwm $Y u32ChannelNum $Y u32CNR <¿PWM_SetCMRD $ìpwm $Y u32ChannelNum $Y u32CMRD <åÍPWM_SetAlignedType $ìpwm $Y u32ChannelMask $BAlignedType <×PWM_EnableAsymmetricMode $ìpwm <ºáPWM_DisableAsymmetricMode $ìpwm <ÙëPWM_EnablePCA $ìpwm <ùõPWM_DisablePCA $ìpwm ì í î __PAN_WDT_H__ l a ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\ pan_wdt.h
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..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_wdt.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil _Bool ;¹hWDT_GetResetFlag a__result ;åtWDT_GetTimeoutFlag a__result ;WDT_GetTimeoutIntFlag a__result ;ÈWDT_GetTimeoutWakeupFlag a__result <âWDT_ResetCounter à_WDT_Timeout WDT_TIMEOUT_2POW4 WDT_TIMEOUT_2POW6 WDT_TIMEOUT_2POW8 WDT_TIMEOUT_2POW10 WDT_TIMEOUT_2POW12 WDT_TIMEOUT_2POW14 WDT_TIMEOUT_2POW15 WDT_TIMEOUT_2POW16 WDT_TIMEOUT_2POW17 WDT_TIMEOUT_2POW18 WDT_TIMEOUT_2POW19
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WDT_TIMEOUT_2POW20 WDT_TIMEOUT_2POW21 WDT_TIMEOUT_2POW22 WDT_TIMEOUT_2POW23 WDT_TIMEOUT_2POW24 PWDT_TimeoutDef â.ñ_WDT_ResetDelay WDT_RESET_DELAY_2CLK WDT_RESET_DELAY_17CLK WDT_RESET_DELAY_129CLK WDT_RESET_DELAY_1025CLK PWDT_ResetDelayDef v:<¥AWDT_ClearResetFlag <ÂJWDT_ClearTimeoutFlag <âSWDT_ClearTimeoutIntFlag <
\WDT_ClearTimeoutWakeupFlag ð ñ ò __PAN_WWDT_H__ 3WWDT_RELOAD_WORD (0x00005AA5) l b ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\ pan_wwdt.h ð
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..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_wwdt.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil _Bool ;»^WWDT_GetResetFlag a__result ;äjWWDT_GetIntFlag a__result ;vWWDT_GetWWDTFFlag a__result ;½WWDT_GetCounter Y a__result Y ;ðWWDT_GetCompareValue Y a__result Y <WWDT_ReloadCounter _WWDT_Prescale WWDT_PRESCALER_1 WWDT_PRESCALER_2 WWDT_PRESCALER_4 WWDT_PRESCALER_8 WWDT_PRESCALER_16 WWDT_PRESCALER_32 WWDT_PRESCALER_64 WWDT_PRESCALER_128 WWDT_PRESCALER_192 WWDT_PRESCALER_256 WWDT_PRESCALER_384
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WWDT_PRESCALER_512 WWDT_PRESCALER_768 WWDT_PRESCALER_1024 WWDT_PRESCALER_1536 WWDT_PRESCALER_2048 PWWDT_PrescaleDef 0<»<WWDT_ClearResetFlag <ÕGWWDT_ClearIntFlag <ñRWWDT_ClearWWDTFFlag ô õ ö __PAN_LP_H__ LP_EXT_P56_WK_EN (1) LP_EXT_P56_WK_DISABLE (0) LP_EXT_P56_WK_EDGE_LOW (0) LP_EXT_P56_WK_EDGE_HIGH (1) #LP_SLPTMR_CH0 (0) $LP_SLPTMR_CH1 (1) %LP_SLPTMR_CH2 (2) 'LP_MODE_SEL_SLEEP_MODE (0) (LP_MODE_SEL_DEEPSLEEP_MODE (1) )LP_MODE_SEL_STANDBY_M1_MODE (2) *LP_MODE_SEL_STANDBY_M0_MODE (3) ,LP_DEEPSLEEP_MODE1 (1) -LP_DEEPSLEEP_MODE2 (2) .LP_DEEPSLEEP_MODE3 (3) 0LP_STANDBY_M1_MODE_SEL LP_STANDBY_M1_MODE1 1LP_STANDBY_M1_MODE1 (1) 2LP_STANDBY_M1_MODE2 (2) 3LP_STANDBY_M1_MODE3 (3) 5LP_STBM1_WAKEUP_SRC_GPIO BIT0 6LP_STBM1_WAKEUP_SRC_SLPTMR BIT1 8LP_RETENTION_SRAM_NONE (0) 9LP_RETENTION_SRAM_BLOCK0 BIT0 :LP_RETENTION_SRAM_BLOCK1 BIT1 ;LP_RETENTION_SRAM_DECRYPT BIT2 <LP_RETENTION_SRAM_PHY_REGS BIT3 =LP_RETENTION_SRAM_LL BIT4 >LP_RETENTION_SRAM_ALL (BIT0 | BIT1 | BIT2 | BIT3 | BIT4) l ` ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\ pan_lp.h È
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..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_lp.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil <±GLP_EnableInt $1ana $æ NewState "f <æRLP_ClearWakeFlag $1ana $Y u32Mask <]LP_HpldoRdyBypassEn $1ana $æ NewState <ÊhLP_FastClkDelayEn $1ana $æ NewState ø ù ú __PAN_EFUSE_H__ EFUSE_CMD_READ (0X0) EFUSE_CMD_PROGRAM (0X1) EFUSE_CMD_INACTIVE (0X2) %EFUSE_STATUS_OK (0x0) &EFUSE_STATUS_FAIL (0x1) l c ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\ pan_efuse.h ¬
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..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_efuse.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil <¥1EFUSE_Init $%efuse " <Ê?EFUSE_UnInit $%efuse ;LEFUSE_GetErrorStatus Y $%efuse a__result Y <WEFUSE_ClrErrorStatus $%efuse ü ý þ __PANSERIES_H__ J__CM0_REV 0x0000 K__MPU_PRESENT 0 L__NVIC_PRIO_BITS 2 M__Vendor_SysTickConfig 0 N__FPU_PRESENT 0 PQUZIS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) ¹TIMER_CTL_PSC_Pos (0) ºTIMER_CTL_PSC_Msk (0xfful << TIMER_CTL_PSC_Pos) ¼TIMER_CTL_CAPSRC_Pos (19) ½TIMER_CTL_CAPSRC_Msk (0x1ul << TIMER_CTL_CAPSRC_Pos) ¿TIMER_CTL_WKEN_Pos (23) ÀTIMER_CTL_WKEN_Msk (0x1ul << TIMER_CTL_WKEN_Pos) ÂTIMER_CTL_EXTCNTEN_Pos (24) ÃTIMER_CTL_EXTCNTEN_Msk (0x1ul << TIMER_CTL_EXTCNTEN_Pos) ÅTIMER_CTL_ACTSTS_Pos (25) ÆTIMER_CTL_ACTSTS_Msk (0x1ul << TIMER_CTL_ACTSTS_Pos) ÈTIMER_CTL_RSTCNT_Pos (26) ÉTIMER_CTL_RSTCNT_Msk (0x1ul << TIMER_CTL_RSTCNT_Pos) ËTIMER_CTL_OPMODE_Pos (27) ÌTIMER_CTL_OPMODE_Msk (0x3ul << TIMER_CTL_OPMODE_Pos) ÎTIMER_CTL_INTEN_Pos (29) ÏTIMER_CTL_INTEN_Msk (0x1ul << TIMER_CTL_INTEN_Pos) ÑTIMER_CTL_CNTEN_Pos (30) ÒTIMER_CTL_CNTEN_Msk (0x1ul << TIMER_CTL_CNTEN_Pos) ÔTIMER_CTL_ICEDEBUG_Pos (31) ÕTIMER_CTL_ICEDEBUG_Msk (0x1ul << TIMER_CTL_ICEDEBUG_Pos) ×TIMER_CMP_CMPDAT_Pos (0) ØTIMER_CMP_CMPDAT_Msk (0xFFfffffful << TIMER_CMP_CMPDAT_Pos) ÚTIMER_INTSTS_TIF_Pos (0) ÛTIMER_INTSTS_TIF_Msk (0x1ul << TIMER_INTSTS_TIF_Pos) ÝTIMER_INTSTS_TWKF0_Pos (1) ÞTIMER_INTSTS_TWKF0_Msk (0x1ul << TIMER_INTSTS_TWKF0_Pos) àTIMER_INTSTS_TWKF1_Pos (2) áTIMER_INTSTS_TWKF1_Msk (0x1ul << TIMER_INTSTS_TWKF1_Pos) ãTIMER_INTSTS_TWKF2_Pos (3) äTIMER_INTSTS_TWKF2_Msk (0x1ul << TIMER_INTSTS_TWKF2_Pos) æTIMER_INTSTS_TF0_Pos (4) çTIMER_INTSTS_TF0_Msk (0x1ul << TIMER_INTSTS_TF0_Pos) éTIMER_INTSTS_TF1_Pos (5) êTIMER_INTSTS_TF1_Msk (0x1ul << TIMER_INTSTS_TF1_Pos) ìTIMER_INTSTS_TF2_Pos (6) íTIMER_INTSTS_TF2_Msk (0x1ul << TIMER_INTSTS_TF2_Pos) ïTIMER_CNT_CNT_Pos (0) ðTIMER_CNT_CNT_Msk (0xFFfffffful << TIMER_CNT_CNT_Pos) òTIMER_CAP_CAPDAT_Pos (0) óTIMER_CAP_CAPDAT_Msk (0xFFfffffful << TIMER_CAP_CAPDAT_Pos) õTIMER_EXTCTL_CNTPHASE_Pos (0) öTIMER_EXTCTL_CNTPHASE_Msk (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos) øTIMER_EXTCTL_CAPEDGE_Pos (1) ùTIMER_EXTCTL_CAPEDGE_Msk (0x3ul << TIMER_EXTCTL_CAPEDGE_Pos) ûTIMER_EXTCTL_CAPEN_Pos (3) üTIMER_EXTCTL_CAPEN_Msk (0x1ul << TIMER_EXTCTL_CAPEN_Pos) þTIMER_EXTCTL_CAPFUNCS_Pos (4) ÿTIMER_EXTCTL_CAPFUNCS_Msk (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos) TIMER_EXTCTL_CAPIEN_Pos (5) TIMER_EXTCTL_CAPIEN_Msk (0x1ul << TIMER_EXTCTL_CAPIEN_Pos) TIMER_EXTCTL_CAPDBEN_Pos (6)
TIMER_EXTCTL_CAPDBEN_Msk (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos) TIMER_EXTCTL_CNTDBEN_Pos (7) TIMER_EXTCTL_CNTDBEN_Msk (0x1ul << TIMER_EXTCTL_CNTDBEN_Pos) TIMER_EXTCTL_CAPSEL_Pos (8) TIMER_EXTCTL_CAPSEL_Msk (0x1ul << TIMER_EXTCTL_CAPSEL_Pos) TIMER_EXTCTL_ACMPSSEL_Pos (9) TIMER_EXTCTL_ACMPSSEL_Msk (0x1ul << TIMER_EXTCTL_ACMPSSEL_Pos) TIMER_EINTSTS_CAPIF_Pos (0) TIMER_EINTSTS_CAPIF_Msk (0x1ul << TIMER_EINTSTS_CAPIF_Pos) TIMER_EINTSTS_CAPF_Pos (1) TIMER_EINTSTS_CAPF_Msk (0x1ul << TIMER_EINTSTS_CAPF_Pos) §TRIM_MEASURE_TUNING_EN_Pos (0) ¨TRIM_MEASURE_TUNING_EN_Msk (0x1ul << TRIM_MEASURE_TUNING_EN_Pos) ©TRIM_COARSE_TUNING_EN_Pos (1) ªTRIM_COARSE_TUNING_EN_Msk (0x1ul << TRIM_COARSE_TUNING_EN_Pos) «TRIM_FINE_TUNING_EN_Pos (2) ¬TRIM_FINE_TUNING_EN_Msk (0x1ul << TRIM_FINE_TUNING_EN_Pos) ¯TRIM_COARSE_CODE_Pos (0) °TRIM_COARSE_CODE_Msk (0xful << TRIM_COARSE_CODE_Pos) ±TRIM_FINE_CODE_Pos (8) ²TRIM_FINE_CODE_Msk (0xfful << TRIM_FINE_CODE_Pos) ³TRIM_BIT_WIDTH_Pos (16) ´TRIM_BIT_WIDTH_Msk (0x7ul << TRIM_BIT_WIDTH_Pos) ·TRIM_CLRL_RELATION_Pos (0) ¸TRIM_CLRL_RELATION_Msk (0x1ul << TRIM_CLRL_RELATION_Pos) ¹TRIM_CLRL_EARLY_TERM_EN_Pos (1) ºTRIM_CLRL_EARLY_TERM_EN_Msk (0x1ul << TRIM_CLRL_EARLY_TERM_EN_Pos) »TRIM_CLRL_FAIL_CLAC_FLAG_Pos (2) ¼TRIM_CLRL_FAIL_CLAC_FLAG_Msk (0x1ul << TRIM_CLRL_FAIL_CLAC_FLAG_Pos) ½TRIM_CLRL_CODE_STEP_Pos (8) ¾TRIM_CLRL_CODE_STEP_Msk (0xfful << TRIM_CLRL_CODE_STEP_Pos) ¿TRIM_CLRL_ERR_RANGE_Pos (16) ÀTRIM_CLRL_ERR_RANGE_Msk (0xfffful << TRIM_CLRL_ERR_RANGE_Pos) ÃTRIM_INT_EN_Pos (0) ÄTRIM_INT_EN_Msk (0x1ul << TRIM_INT_EN_Pos) ÅTRIM_INT_MEASURE_STOP_Pos (1) ÆTRIM_INT_MEASURE_STOP_Msk (0x1ul << TRIM_INT_MEASURE_STOP_Pos) ÇTRIM_FLAG_MEASURE_STOP_Pos (2) ÈTRIM_FLAG_MEASURE_STOP_Msk (0x1ul << TRIM_FLAG_MEASURE_STOP_Pos) ÉTRIM_INT_CTUNE_STOP_Pos (3) ÊTRIM_INT_CTUNE_STOP_Msk (0x1ul << TRIM_INT_CTUNE_STOP_Pos) ËTRIM_FLAG_CTUNE_STOP_Pos (4) ÌTRIM_FLAG_CTUNE_STOP_Msk (0x1ul << TRIM_FLAG_CTUNE_STOP_Pos) ÍTRIM_INT_FTUNE_STOP_Pos (5) ÎTRIM_INT_FTUNE_STOP_Msk (0x1ul << TRIM_INT_FTUNE_STOP_Pos) ÏTRIM_FLAG_FTUNE_STOP_Pos (6) ÐTRIM_FLAG_FTUNE_STOP_Msk (0x1ul << TRIM_FLAG_FTUNE_STOP_Pos) ÑTRIM_INT_OVERFLOW_Pos (9) ÒTRIM_INT_OVERFLOW_Msk (0x1ul << TRIM_INT_OVERFLOW_Pos) ÓTRIM_FLAG_OVERFLOW_Pos (10) ÔTRIM_FLAG_OVERFLOW_Msk (0x1ul << TRIM_FLAG_OVERFLOW_Pos) ÚTRIM_CALC_CNT_Pos (0) ÛTRIM_CALC_CNT_Msk (0xFFFFFFul << TRIM_INT_EN_Pos) ÜTRIM_CALC_WATI_CNT_Pos (24) ÝTRIM_CALC_WATI_CNT_Msk (0xFFul << TRIM_CALC_WATI_CNT_Pos) ·GP_MODE_MODE0_Pos (0) ¸GP_MODE_MODE0_Msk (0x3ul << GP_MODE_MODE0_Pos) ºGP_MODE_MODE1_Pos (2) »GP_MODE_MODE1_Msk (0x3ul << GP_MODE_MODE1_Pos) ½GP_MODE_MODE2_Pos (4) ¾GP_MODE_MODE2_Msk (0x3ul << GP_MODE_MODE2_Pos) ÀGP_MODE_MODE3_Pos (6) ÁGP_MODE_MODE3_Msk (0x3ul << GP_MODE_MODE3_Pos) ÃGP_MODE_MODE4_Pos (8) ÄGP_MODE_MODE4_Msk (0x3ul << GP_MODE_MODE4_Pos) ÆGP_MODE_MODE5_Pos (10) ÇGP_MODE_MODE5_Msk (0x3ul << GP_MODE_MODE5_Pos) ÉGP_DINOFF_DINOFF0_Pos (16) ÊGP_DINOFF_DINOFF0_Msk (0x1ul << GP_DINOFF_DINOFF0_Pos) ÌGP_DINOFF_DINOFF1_Pos (17) ÍGP_DINOFF_DINOFF1_Msk (0x1ul << GP_DINOFF_DINOFF1_Pos) ÏGP_DINOFF_DINOFF2_Pos (18) ÐGP_DINOFF_DINOFF2_Msk (0x1ul << GP_DINOFF_DINOFF2_Pos) ÒGP_DINOFF_DINOFF3_Pos (19) ÓGP_DINOFF_DINOFF3_Msk (0x1ul << GP_DINOFF_DINOFF3_Pos) ÕGP_DINOFF_DINOFF4_Pos (20) ÖGP_DINOFF_DINOFF4_Msk (0x1ul << GP_DINOFF_DINOFF4_Pos) ØGP_DINOFF_DINOFF5_Pos (21) ÙGP_DINOFF_DINOFF5_Msk (0x1ul << GP_DINOFF_DINOFF5_Pos) ÛGP_DINOFF_DINOFF6_Pos (22) ÜGP_DINOFF_DINOFF6_Msk (0x1ul << GP_DINOFF_DINOFF6_Pos) ÞGP_DINOFF_DINOFF7_Pos (23) ßGP_DINOFF_DINOFF7_Msk (0x1ul << GP_DINOFF_DINOFF7_Pos) áGP_DOUT_DOUT0_Pos (0) âGP_DOUT_DOUT0_Msk (0x1ul << GP_DOUT_DOUT0_Pos) äGP_DOUT_DOUT1_Pos (1) åGP_DOUT_DOUT1_Msk (0x1ul << GP_DOUT_DOUT1_Pos) çGP_DOUT_DOUT2_Pos (2) èGP_DOUT_DOUT2_Msk (0x1ul << GP_DOUT_DOUT2_Pos) êGP_DOUT_DOUT3_Pos (3) ëGP_DOUT_DOUT3_Msk (0x1ul << GP_DOUT_DOUT3_Pos) íGP_DOUT_DOUT4_Pos (4) îGP_DOUT_DOUT4_Msk (0x1ul << GP_DOUT_DOUT4_Pos) ðGP_DOUT_DOUT5_Pos (5) ñGP_DOUT_DOUT5_Msk (0x1ul << GP_DOUT_DOUT5_Pos) óGP_DOUT_DOUT6_Pos (6) ôGP_DOUT_DOUT6_Msk (0x1ul << GP_DOUT_DOUT6_Pos) öGP_DOUT_DOUT7_Pos (7) ÷GP_DOUT_DOUT7_Msk (0x1ul << GP_DOUT_DOUT7_Pos) ùGP_DATMSK_DATMSK0_Pos (0) úGP_DATMSK_DATMSK0_Msk (0x1ul << GP_DATMSK_DATMSK0_Pos) üGP_DATMSK_DATMSK1_Pos (1) ýGP_DATMSK_DATMSK1_Msk (0x1ul << GP_DATMSK_DATMSK1_Pos) ÿGP_DATMSK_DATMSK2_Pos (2) GP_DATMSK_DATMSK2_Msk (0x1ul << GP_DATMSK_DATMSK2_Pos) GP_DATMSK_DATMSK3_Pos (3) GP_DATMSK_DATMSK3_Msk (0x1ul << GP_DATMSK_DATMSK3_Pos)
GP_DATMSK_DATMSK4_Pos (4) GP_DATMSK_DATMSK4_Msk (0x1ul << GP_DATMSK_DATMSK4_Pos) GP_DATMSK_DATMSK5_Pos (5) GP_DATMSK_DATMSK5_Msk (0x1ul << GP_DATMSK_DATMSK5_Pos) GP_DATMSK_DATMSK6_Pos (6) GP_DATMSK_DATMSK6_Msk (0x1ul << GP_DATMSK_DATMSK6_Pos) GP_DATMSK_DATMSK7_Pos (7) GP_DATMSK_DATMSK7_Msk (0x1ul << GP_DATMSK_DATMSK7_Pos) GP_PIN_PIN0_Pos (0) GP_PIN_PIN0_Msk (0x1ul << GP_PIN_PIN0_Pos) GP_PIN_PIN1_Pos (1) GP_PIN_PIN1_Msk (0x1ul << GP_PIN_PIN1_Pos) GP_PIN_PIN2_Pos (2) GP_PIN_PIN2_Msk (0x1ul << GP_PIN_PIN2_Pos) GP_PIN_PIN3_Pos (3) GP_PIN_PIN3_Msk (0x1ul << GP_PIN_PIN3_Pos) GP_PIN_PIN4_Pos (4) GP_PIN_PIN4_Msk (0x1ul << GP_PIN_PIN4_Pos) GP_PIN_PIN5_Pos (5) ¡GP_PIN_PIN5_Msk (0x1ul << GP_PIN_PIN5_Pos) £GP_PIN_PIN6_Pos (6) ¤GP_PIN_PIN6_Msk (0x1ul << GP_PIN_PIN6_Pos) ¦GP_PIN_PIN7_Pos (7) §GP_PIN_PIN7_Msk (0x1ul << GP_PIN_PIN7_Pos) ©GP_DBEN_DBEN0_Pos (0) ªGP_DBEN_DBEN0_Msk (0x1ul << GP_DBEN_DBEN0_Pos) ¬GP_DBEN_DBEN1_Pos (1) GP_DBEN_DBEN1_Msk (0x1ul << GP_DBEN_DBEN1_Pos) ¯GP_DBEN_DBEN2_Pos (2) °GP_DBEN_DBEN2_Msk (0x1ul << GP_DBEN_DBEN2_Pos) ²GP_DBEN_DBEN3_Pos (3) ³GP_DBEN_DBEN3_Msk (0x1ul << GP_DBEN_DBEN3_Pos) µGP_DBEN_DBEN4_Pos (4) ¶GP_DBEN_DBEN4_Msk (0x1ul << GP_DBEN_DBEN4_Pos) ¸GP_DBEN_DBEN5_Pos (5) ¹GP_DBEN_DBEN5_Msk (0x1ul << GP_DBEN_DBEN5_Pos) »GP_DBEN_DBEN6_Pos (6) ¼GP_DBEN_DBEN6_Msk (0x1ul << GP_DBEN_DBEN6_Pos) ¾GP_DBEN_DBEN7_Pos (7) ¿GP_DBEN_DBEN7_Msk (0x1ul << GP_DBEN_DBEN7_Pos) ÁGP_INTTYPE_TYPE0_Pos (0) ÂGP_INTTYPE_TYPE0_Msk (0x1ul << GP_INTTYPE_TYPE0_Pos) ÄGP_INTTYPE_TYPE1_Pos (1) ÅGP_INTTYPE_TYPE1_Msk (0x1ul << GP_INTTYPE_TYPE1_Pos) ÇGP_INTTYPE_TYPE2_Pos (2) ÈGP_INTTYPE_TYPE2_Msk (0x1ul << GP_INTTYPE_TYPE2_Pos) ÊGP_INTTYPE_TYPE3_Pos (3) ËGP_INTTYPE_TYPE3_Msk (0x1ul << GP_INTTYPE_TYPE3_Pos) ÍGP_INTTYPE_TYPE4_Pos (4) ÎGP_INTTYPE_TYPE4_Msk (0x1ul << GP_INTTYPE_TYPE4_Pos) ÐGP_INTTYPE_TYPE5_Pos (5) ÑGP_INTTYPE_TYPE5_Msk (0x1ul << GP_INTTYPE_TYPE5_Pos) ÓGP_INTTYPE_TYPE6_Pos (6) ÔGP_INTTYPE_TYPE6_Msk (0x1ul << GP_INTTYPE_TYPE6_Pos) ÖGP_INTTYPE_TYPE7_Pos (7) ×GP_INTTYPE_TYPE7_Msk (0x1ul << GP_INTTYPE_TYPE7_Pos) ÙGP_INTEN_FLIEN0_Pos (0) ÚGP_INTEN_FLIEN0_Msk (0x1ul << GP_INTEN_FLIEN0_Pos) ÜGP_INTEN_FLIEN1_Pos (1) ÝGP_INTEN_FLIEN1_Msk (0x1ul << GP_INTEN_FLIEN1_Pos) ßGP_INTEN_FLIEN2_Pos (2) àGP_INTEN_FLIEN2_Msk (0x1ul << GP_INTEN_FLIEN2_Pos) âGP_INTEN_FLIEN3_Pos (3) ãGP_INTEN_FLIEN3_Msk (0x1ul << GP_INTEN_FLIEN3_Pos) åGP_INTEN_FLIEN4_Pos (4) æGP_INTEN_FLIEN4_Msk (0x1ul << GP_INTEN_FLIEN4_Pos) èGP_INTEN_FLIEN5_Pos (5) éGP_INTEN_FLIEN5_Msk (0x1ul << GP_INTEN_FLIEN5_Pos) ëGP_INTEN_FLIEN6_Pos (6) ìGP_INTEN_FLIEN6_Msk (0x1ul << GP_INTEN_FLIEN6_Pos) îGP_INTEN_FLIEN7_Pos (7) ïGP_INTEN_FLIEN7_Msk (0x1ul << GP_INTEN_FLIEN7_Pos) ñGP_INTEN_RHIEN0_Pos (16) òGP_INTEN_RHIEN0_Msk (0x1ul << GP_INTEN_RHIEN0_Pos) ôGP_INTEN_RHIEN1_Pos (17) õGP_INTEN_RHIEN1_Msk (0x1ul << GP_INTEN_RHIEN1_Pos) ÷GP_INTEN_RHIEN2_Pos (18) øGP_INTEN_RHIEN2_Msk (0x1ul << GP_INTEN_RHIEN2_Pos) úGP_INTEN_RHIEN3_Pos (19) ûGP_INTEN_RHIEN3_Msk (0x1ul << GP_INTEN_RHIEN3_Pos) ýGP_INTEN_RHIEN4_Pos (20) þGP_INTEN_RHIEN4_Msk (0x1ul << GP_INTEN_RHIEN4_Pos) GP_INTEN_RHIEN5_Pos (21) GP_INTEN_RHIEN5_Msk (0x1ul << GP_INTEN_RHIEN5_Pos) GP_INTEN_RHIEN6_Pos (22) GP_INTEN_RHIEN6_Msk (0x1ul << GP_INTEN_RHIEN6_Pos) GP_INTEN_RHIEN7_Pos (23) GP_INTEN_RHIEN7_Msk (0x1ul << GP_INTEN_RHIEN7_Pos) GP_INTSRC_INTSRC0_Pos (0) GP_INTSRC_INTSRC0_Msk (0x1ul << GP_INTSRC_INTSRC0_Pos) GP_INTSRC_INTSRC1_Pos (1) GP_INTSRC_INTSRC1_Msk (0x1ul << GP_INTSRC_INTSRC1_Pos) GP_INTSRC_INTSRC2_Pos (2) GP_INTSRC_INTSRC2_Msk (0x1ul << GP_INTSRC_INTSRC2_Pos) GP_INTSRC_INTSRC3_Pos (3) GP_INTSRC_INTSRC3_Msk (0x1ul << GP_INTSRC_INTSRC3_Pos) GP_INTSRC_INTSRC4_Pos (4) GP_INTSRC_INTSRC4_Msk (0x1ul << GP_INTSRC_INTSRC4_Pos) GP_INTSRC_INTSRC5_Pos (5) GP_INTSRC_INTSRC5_Msk (0x1ul << GP_INTSRC_INTSRC5_Pos) GP_INTSRC_INTSRC6_Pos (6) GP_INTSRC_INTSRC6_Msk (0x1ul << GP_INTSRC_INTSRC6_Pos) GP_INTSRC_INTSRC7_Pos (7) GP_INTSRC_INTSRC7_Msk (0x1ul << GP_INTSRC_INTSRC7_Pos) ¡GP_INTSRC_INTSRC8_Pos (8) ¢GP_INTSRC_INTSRC8_Msk (0x1ul << GP_INTSRC_INTSRC8_Pos) ¤GP_INTSRC_INTSRC9_Pos (9) ¥GP_INTSRC_INTSRC9_Msk (0x1ul << GP_INTSRC_INTSRC9_Pos) §GP_INTSRC_INTSRC10_Pos (10) ¨GP_INTSRC_INTSRC10_Msk (0x1ul << GP_INTSRC_INTSRC10_Pos) ªGP_INTSRC_INTSRC11_Pos (11) «GP_INTSRC_INTSRC11_Msk (0x1ul << GP_INTSRC_INTSRC11_Pos) GP_INTSRC_INTSRC12_Pos (12) ®GP_INTSRC_INTSRC12_Msk (0x1ul << GP_INTSRC_INTSRC12_Pos) °GP_INTSRC_INTSRC13_Pos (13) ±GP_INTSRC_INTSRC13_Msk (0x1ul << GP_INTSRC_INTSRC13_Pos) ³GP_INTSRC_INTSRC14_Pos (14) ´GP_INTSRC_INTSRC14_Msk (0x1ul << GP_INTSRC_INTSRC14_Pos) ¶GP_INTSRC_INTSRC15_Pos (15) ·GP_INTSRC_INTSRC15_Msk (0x1ul << GP_INTSRC_INTSRC15_Pos) ¹GP_MODE_MODE0_Pos (0) ºGP_MODE_MODE0_Msk (0x3ul << GP_MODE_MODE0_Pos) ¼GP_MODE_MODE1_Pos (2) ½GP_MODE_MODE1_Msk (0x3ul << GP_MODE_MODE1_Pos) ¿GP_MODE_MODE2_Pos (4) ÀGP_MODE_MODE2_Msk (0x3ul << GP_MODE_MODE2_Pos) ÂGP_MODE_MODE3_Pos (6) ÃGP_MODE_MODE3_Msk (0x3ul << GP_MODE_MODE3_Pos) ÅGP_MODE_MODE4_Pos (8) ÆGP_MODE_MODE4_Msk (0x3ul << GP_MODE_MODE4_Pos) ÈGP_MODE_MODE5_Pos (10) ÉGP_MODE_MODE5_Msk (0x3ul << GP_MODE_MODE5_Pos) ËGP_DINOFF_DINOFF0_Pos (16) ÌGP_DINOFF_DINOFF0_Msk (0x1ul << GP_DINOFF_DINOFF0_Pos) ÎGP_DINOFF_DINOFF1_Pos (17) ÏGP_DINOFF_DINOFF1_Msk (0x1ul << GP_DINOFF_DINOFF1_Pos) ÑGP_DINOFF_DINOFF2_Pos (18) ÒGP_DINOFF_DINOFF2_Msk (0x1ul << GP_DINOFF_DINOFF2_Pos) ÔGP_DINOFF_DINOFF3_Pos (19) ÕGP_DINOFF_DINOFF3_Msk (0x1ul << GP_DINOFF_DINOFF3_Pos) ×GP_DINOFF_DINOFF4_Pos (20) ØGP_DINOFF_DINOFF4_Msk (0x1ul << GP_DINOFF_DINOFF4_Pos) ÚGP_DINOFF_DINOFF5_Pos (21) ÛGP_DINOFF_DINOFF5_Msk (0x1ul << GP_DINOFF_DINOFF5_Pos) ÝGP_DINOFF_DINOFF6_Pos (22) ÞGP_DINOFF_DINOFF6_Msk (0x1ul << GP_DINOFF_DINOFF6_Pos) àGP_DINOFF_DINOFF7_Pos (23) áGP_DINOFF_DINOFF7_Msk (0x1ul << GP_DINOFF_DINOFF7_Pos) ãGP_DOUT_DOUT0_Pos (0) äGP_DOUT_DOUT0_Msk (0x1ul << GP_DOUT_DOUT0_Pos) æGP_DOUT_DOUT1_Pos (1) çGP_DOUT_DOUT1_Msk (0x1ul << GP_DOUT_DOUT1_Pos) éGP_DOUT_DOUT2_Pos (2) êGP_DOUT_DOUT2_Msk (0x1ul << GP_DOUT_DOUT2_Pos) ìGP_DOUT_DOUT3_Pos (3) íGP_DOUT_DOUT3_Msk (0x1ul << GP_DOUT_DOUT3_Pos) ïGP_DOUT_DOUT4_Pos (4) ðGP_DOUT_DOUT4_Msk (0x1ul << GP_DOUT_DOUT4_Pos) òGP_DOUT_DOUT5_Pos (5) óGP_DOUT_DOUT5_Msk (0x1ul << GP_DOUT_DOUT5_Pos) õGP_DOUT_DOUT6_Pos (6) öGP_DOUT_DOUT6_Msk (0x1ul << GP_DOUT_DOUT6_Pos) øGP_DOUT_DOUT7_Pos (7) ùGP_DOUT_DOUT7_Msk (0x1ul << GP_DOUT_DOUT7_Pos) ûGP_DATMSK_DATMSK0_Pos (0) üGP_DATMSK_DATMSK0_Msk (0x1ul << GP_DATMSK_DATMSK0_Pos) þGP_DATMSK_DATMSK1_Pos (1) ÿGP_DATMSK_DATMSK1_Msk (0x1ul << GP_DATMSK_DATMSK1_Pos) GP_DATMSK_DATMSK2_Pos (2) GP_DATMSK_DATMSK2_Msk (0x1ul << GP_DATMSK_DATMSK2_Pos) GP_DATMSK_DATMSK3_Pos (3)
GP_DATMSK_DATMSK3_Msk (0x1ul << GP_DATMSK_DATMSK3_Pos) GP_DATMSK_DATMSK4_Pos (4) GP_DATMSK_DATMSK4_Msk (0x1ul << GP_DATMSK_DATMSK4_Pos) GP_DATMSK_DATMSK5_Pos (5) GP_DATMSK_DATMSK5_Msk (0x1ul << GP_DATMSK_DATMSK5_Pos) GP_DATMSK_DATMSK6_Pos (6) GP_DATMSK_DATMSK6_Msk (0x1ul << GP_DATMSK_DATMSK6_Pos) GP_DATMSK_DATMSK7_Pos (7) GP_DATMSK_DATMSK7_Msk (0x1ul << GP_DATMSK_DATMSK7_Pos) GP_PIN_PIN0_Pos (0) GP_PIN_PIN0_Msk (0x1ul << GP_PIN_PIN0_Pos) GP_PIN_PIN1_Pos (1) GP_PIN_PIN1_Msk (0x1ul << GP_PIN_PIN1_Pos) GP_PIN_PIN2_Pos (2) GP_PIN_PIN2_Msk (0x1ul << GP_PIN_PIN2_Pos) GP_PIN_PIN3_Pos (3) GP_PIN_PIN3_Msk (0x1ul << GP_PIN_PIN3_Pos) GP_PIN_PIN4_Pos (4) GP_PIN_PIN4_Msk (0x1ul << GP_PIN_PIN4_Pos) ¢GP_PIN_PIN5_Pos (5) £GP_PIN_PIN5_Msk (0x1ul << GP_PIN_PIN5_Pos) ¥GP_PIN_PIN6_Pos (6) ¦GP_PIN_PIN6_Msk (0x1ul << GP_PIN_PIN6_Pos) ¨GP_PIN_PIN7_Pos (7) ©GP_PIN_PIN7_Msk (0x1ul << GP_PIN_PIN7_Pos) «GP_DBEN_DBEN0_Pos (0) ¬GP_DBEN_DBEN0_Msk (0x1ul << GP_DBEN_DBEN0_Pos) ®GP_DBEN_DBEN1_Pos (1) ¯GP_DBEN_DBEN1_Msk (0x1ul << GP_DBEN_DBEN1_Pos) ±GP_DBEN_DBEN2_Pos (2) ²GP_DBEN_DBEN2_Msk (0x1ul << GP_DBEN_DBEN2_Pos) ´GP_DBEN_DBEN3_Pos (3) µGP_DBEN_DBEN3_Msk (0x1ul << GP_DBEN_DBEN3_Pos) ·GP_DBEN_DBEN4_Pos (4) ¸GP_DBEN_DBEN4_Msk (0x1ul << GP_DBEN_DBEN4_Pos) ºGP_DBEN_DBEN5_Pos (5) »GP_DBEN_DBEN5_Msk (0x1ul << GP_DBEN_DBEN5_Pos) ½GP_DBEN_DBEN6_Pos (6) ¾GP_DBEN_DBEN6_Msk (0x1ul << GP_DBEN_DBEN6_Pos) ÀGP_DBEN_DBEN7_Pos (7) ÁGP_DBEN_DBEN7_Msk (0x1ul << GP_DBEN_DBEN7_Pos) ÃGP_INTTYPE_TYPE0_Pos (0) ÄGP_INTTYPE_TYPE0_Msk (0x1ul << GP_INTTYPE_TYPE0_Pos) ÆGP_INTTYPE_TYPE1_Pos (1) ÇGP_INTTYPE_TYPE1_Msk (0x1ul << GP_INTTYPE_TYPE1_Pos) ÉGP_INTTYPE_TYPE2_Pos (2) ÊGP_INTTYPE_TYPE2_Msk (0x1ul << GP_INTTYPE_TYPE2_Pos) ÌGP_INTTYPE_TYPE3_Pos (3) ÍGP_INTTYPE_TYPE3_Msk (0x1ul << GP_INTTYPE_TYPE3_Pos) ÏGP_INTTYPE_TYPE4_Pos (4) ÐGP_INTTYPE_TYPE4_Msk (0x1ul << GP_INTTYPE_TYPE4_Pos) ÒGP_INTTYPE_TYPE5_Pos (5) ÓGP_INTTYPE_TYPE5_Msk (0x1ul << GP_INTTYPE_TYPE5_Pos) ÕGP_INTTYPE_TYPE6_Pos (6) ÖGP_INTTYPE_TYPE6_Msk (0x1ul << GP_INTTYPE_TYPE6_Pos) ØGP_INTTYPE_TYPE7_Pos (7) ÙGP_INTTYPE_TYPE7_Msk (0x1ul << GP_INTTYPE_TYPE7_Pos) ÛGP_INTEN_FLIEN0_Pos (0) ÜGP_INTEN_FLIEN0_Msk (0x1ul << GP_INTEN_FLIEN0_Pos) ÞGP_INTEN_FLIEN1_Pos (1) ßGP_INTEN_FLIEN1_Msk (0x1ul << GP_INTEN_FLIEN1_Pos) áGP_INTEN_FLIEN2_Pos (2) âGP_INTEN_FLIEN2_Msk (0x1ul << GP_INTEN_FLIEN2_Pos) äGP_INTEN_FLIEN3_Pos (3) åGP_INTEN_FLIEN3_Msk (0x1ul << GP_INTEN_FLIEN3_Pos) çGP_INTEN_FLIEN4_Pos (4) èGP_INTEN_FLIEN4_Msk (0x1ul << GP_INTEN_FLIEN4_Pos) êGP_INTEN_FLIEN5_Pos (5) ëGP_INTEN_FLIEN5_Msk (0x1ul << GP_INTEN_FLIEN5_Pos) íGP_INTEN_FLIEN6_Pos (6) îGP_INTEN_FLIEN6_Msk (0x1ul << GP_INTEN_FLIEN6_Pos) ðGP_INTEN_FLIEN7_Pos (7) ñGP_INTEN_FLIEN7_Msk (0x1ul << GP_INTEN_FLIEN7_Pos) óGP_INTEN_RHIEN0_Pos (16) ôGP_INTEN_RHIEN0_Msk (0x1ul << GP_INTEN_RHIEN0_Pos) öGP_INTEN_RHIEN1_Pos (17) ÷GP_INTEN_RHIEN1_Msk (0x1ul << GP_INTEN_RHIEN1_Pos) ùGP_INTEN_RHIEN2_Pos (18) úGP_INTEN_RHIEN2_Msk (0x1ul << GP_INTEN_RHIEN2_Pos) üGP_INTEN_RHIEN3_Pos (19) ýGP_INTEN_RHIEN3_Msk (0x1ul << GP_INTEN_RHIEN3_Pos) ÿGP_INTEN_RHIEN4_Pos (20) GP_INTEN_RHIEN4_Msk (0x1ul << GP_INTEN_RHIEN4_Pos) GP_INTEN_RHIEN5_Pos (21) GP_INTEN_RHIEN5_Msk (0x1ul << GP_INTEN_RHIEN5_Pos)
GP_INTEN_RHIEN6_Pos (22) GP_INTEN_RHIEN6_Msk (0x1ul << GP_INTEN_RHIEN6_Pos) GP_INTEN_RHIEN7_Pos (23) GP_INTEN_RHIEN7_Msk (0x1ul << GP_INTEN_RHIEN7_Pos) GP_INTSRC_INTSRC0_Pos (0) GP_INTSRC_INTSRC0_Msk (0x1ul << GP_INTSRC_INTSRC0_Pos) GP_INTSRC_INTSRC1_Pos (1) GP_INTSRC_INTSRC1_Msk (0x1ul << GP_INTSRC_INTSRC1_Pos) GP_INTSRC_INTSRC2_Pos (2) GP_INTSRC_INTSRC2_Msk (0x1ul << GP_INTSRC_INTSRC2_Pos) GP_INTSRC_INTSRC3_Pos (3) GP_INTSRC_INTSRC3_Msk (0x1ul << GP_INTSRC_INTSRC3_Pos) GP_INTSRC_INTSRC4_Pos (4) GP_INTSRC_INTSRC4_Msk (0x1ul << GP_INTSRC_INTSRC4_Pos) GP_INTSRC_INTSRC5_Pos (5) GP_INTSRC_INTSRC5_Msk (0x1ul << GP_INTSRC_INTSRC5_Pos) GP_INTSRC_INTSRC6_Pos (6) GP_INTSRC_INTSRC6_Msk (0x1ul << GP_INTSRC_INTSRC6_Pos) GP_INTSRC_INTSRC7_Pos (7) ¡GP_INTSRC_INTSRC7_Msk (0x1ul << GP_INTSRC_INTSRC7_Pos) £GP_INTSRC_INTSRC8_Pos (8) ¤GP_INTSRC_INTSRC8_Msk (0x1ul << GP_INTSRC_INTSRC8_Pos) ¦GP_INTSRC_INTSRC9_Pos (9) §GP_INTSRC_INTSRC9_Msk (0x1ul << GP_INTSRC_INTSRC9_Pos) ©GP_INTSRC_INTSRC10_Pos (10) ªGP_INTSRC_INTSRC10_Msk (0x1ul << GP_INTSRC_INTSRC10_Pos) ¬GP_INTSRC_INTSRC11_Pos (11) GP_INTSRC_INTSRC11_Msk (0x1ul << GP_INTSRC_INTSRC11_Pos) ¯GP_INTSRC_INTSRC12_Pos (12) °GP_INTSRC_INTSRC12_Msk (0x1ul << GP_INTSRC_INTSRC12_Pos) ²GP_INTSRC_INTSRC13_Pos (13) ³GP_INTSRC_INTSRC13_Msk (0x1ul << GP_INTSRC_INTSRC13_Pos) µGP_INTSRC_INTSRC14_Pos (14) ¶GP_INTSRC_INTSRC14_Msk (0x1ul << GP_INTSRC_INTSRC14_Pos) ¸GP_INTSRC_INTSRC15_Pos (15) ¹GP_INTSRC_INTSRC15_Msk (0x1ul << GP_INTSRC_INTSRC15_Pos) »GP_MODE_MODE0_Pos (0) ¼GP_MODE_MODE0_Msk (0x3ul << GP_MODE_MODE0_Pos) ¾GP_MODE_MODE1_Pos (2) ¿GP_MODE_MODE1_Msk (0x3ul << GP_MODE_MODE1_Pos) ÁGP_MODE_MODE2_Pos (4) ÂGP_MODE_MODE2_Msk (0x3ul << GP_MODE_MODE2_Pos) ÄGP_MODE_MODE3_Pos (6) ÅGP_MODE_MODE3_Msk (0x3ul << GP_MODE_MODE3_Pos) ÇGP_MODE_MODE4_Pos (8) ÈGP_MODE_MODE4_Msk (0x3ul << GP_MODE_MODE4_Pos) ÊGP_MODE_MODE5_Pos (10) ËGP_MODE_MODE5_Msk (0x3ul << GP_MODE_MODE5_Pos) ÍGP_DINOFF_DINOFF0_Pos (16) ÎGP_DINOFF_DINOFF0_Msk (0x1ul << GP_DINOFF_DINOFF0_Pos) ÐGP_DINOFF_DINOFF1_Pos (17) ÑGP_DINOFF_DINOFF1_Msk (0x1ul << GP_DINOFF_DINOFF1_Pos) ÓGP_DINOFF_DINOFF2_Pos (18) ÔGP_DINOFF_DINOFF2_Msk (0x1ul << GP_DINOFF_DINOFF2_Pos) ÖGP_DINOFF_DINOFF3_Pos (19) ×GP_DINOFF_DINOFF3_Msk (0x1ul << GP_DINOFF_DINOFF3_Pos) ÙGP_DINOFF_DINOFF4_Pos (20) ÚGP_DINOFF_DINOFF4_Msk (0x1ul << GP_DINOFF_DINOFF4_Pos) ÜGP_DINOFF_DINOFF5_Pos (21) ÝGP_DINOFF_DINOFF5_Msk (0x1ul << GP_DINOFF_DINOFF5_Pos) ßGP_DINOFF_DINOFF6_Pos (22) àGP_DINOFF_DINOFF6_Msk (0x1ul << GP_DINOFF_DINOFF6_Pos) âGP_DINOFF_DINOFF7_Pos (23) ãGP_DINOFF_DINOFF7_Msk (0x1ul << GP_DINOFF_DINOFF7_Pos) åGP_DOUT_DOUT0_Pos (0) æGP_DOUT_DOUT0_Msk (0x1ul << GP_DOUT_DOUT0_Pos) èGP_DOUT_DOUT1_Pos (1) éGP_DOUT_DOUT1_Msk (0x1ul << GP_DOUT_DOUT1_Pos) ëGP_DOUT_DOUT2_Pos (2) ìGP_DOUT_DOUT2_Msk (0x1ul << GP_DOUT_DOUT2_Pos) îGP_DOUT_DOUT3_Pos (3) ïGP_DOUT_DOUT3_Msk (0x1ul << GP_DOUT_DOUT3_Pos) ñGP_DOUT_DOUT4_Pos (4) òGP_DOUT_DOUT4_Msk (0x1ul << GP_DOUT_DOUT4_Pos) ôGP_DOUT_DOUT5_Pos (5) õGP_DOUT_DOUT5_Msk (0x1ul << GP_DOUT_DOUT5_Pos) ÷GP_DOUT_DOUT6_Pos (6) øGP_DOUT_DOUT6_Msk (0x1ul << GP_DOUT_DOUT6_Pos) úGP_DOUT_DOUT7_Pos (7) ûGP_DOUT_DOUT7_Msk (0x1ul << GP_DOUT_DOUT7_Pos) ýGP_DATMSK_DATMSK0_Pos (0) þGP_DATMSK_DATMSK0_Msk (0x1ul << GP_DATMSK_DATMSK0_Pos) GP_DATMSK_DATMSK1_Pos (1) GP_DATMSK_DATMSK1_Msk (0x1ul << GP_DATMSK_DATMSK1_Pos) GP_DATMSK_DATMSK2_Pos (2) GP_DATMSK_DATMSK2_Msk (0x1ul << GP_DATMSK_DATMSK2_Pos) GP_DATMSK_DATMSK3_Pos (3) GP_DATMSK_DATMSK3_Msk (0x1ul << GP_DATMSK_DATMSK3_Pos) GP_DATMSK_DATMSK4_Pos (4) GP_DATMSK_DATMSK4_Msk (0x1ul << GP_DATMSK_DATMSK4_Pos) GP_DATMSK_DATMSK5_Pos (5) GP_DATMSK_DATMSK5_Msk (0x1ul << GP_DATMSK_DATMSK5_Pos) GP_DATMSK_DATMSK6_Pos (6) GP_DATMSK_DATMSK6_Msk (0x1ul << GP_DATMSK_DATMSK6_Pos) GP_DATMSK_DATMSK7_Pos (7) GP_DATMSK_DATMSK7_Msk (0x1ul << GP_DATMSK_DATMSK7_Pos) GP_PIN_PIN0_Pos (0) GP_PIN_PIN0_Msk (0x1ul << GP_PIN_PIN0_Pos) GP_PIN_PIN1_Pos (1) GP_PIN_PIN1_Msk (0x1ul << GP_PIN_PIN1_Pos) GP_PIN_PIN2_Pos (2) GP_PIN_PIN2_Msk (0x1ul << GP_PIN_PIN2_Pos) GP_PIN_PIN3_Pos (3) GP_PIN_PIN3_Msk (0x1ul << GP_PIN_PIN3_Pos) ¡GP_PIN_PIN4_Pos (4) ¢GP_PIN_PIN4_Msk (0x1ul << GP_PIN_PIN4_Pos) ¤GP_PIN_PIN5_Pos (5) ¥GP_PIN_PIN5_Msk (0x1ul << GP_PIN_PIN5_Pos) §GP_PIN_PIN6_Pos (6) ¨GP_PIN_PIN6_Msk (0x1ul << GP_PIN_PIN6_Pos) ªGP_PIN_PIN7_Pos (7) «GP_PIN_PIN7_Msk (0x1ul << GP_PIN_PIN7_Pos) GP_DBEN_DBEN0_Pos (0) ®GP_DBEN_DBEN0_Msk (0x1ul << GP_DBEN_DBEN0_Pos) °GP_DBEN_DBEN1_Pos (1) ±GP_DBEN_DBEN1_Msk (0x1ul << GP_DBEN_DBEN1_Pos) ³GP_DBEN_DBEN2_Pos (2) ´GP_DBEN_DBEN2_Msk (0x1ul << GP_DBEN_DBEN2_Pos) ¶GP_DBEN_DBEN3_Pos (3) ·GP_DBEN_DBEN3_Msk (0x1ul << GP_DBEN_DBEN3_Pos) ¹GP_DBEN_DBEN4_Pos (4) ºGP_DBEN_DBEN4_Msk (0x1ul << GP_DBEN_DBEN4_Pos) ¼GP_DBEN_DBEN5_Pos (5) ½GP_DBEN_DBEN5_Msk (0x1ul << GP_DBEN_DBEN5_Pos) ¿GP_DBEN_DBEN6_Pos (6) ÀGP_DBEN_DBEN6_Msk (0x1ul << GP_DBEN_DBEN6_Pos) ÂGP_DBEN_DBEN7_Pos (7) ÃGP_DBEN_DBEN7_Msk (0x1ul << GP_DBEN_DBEN7_Pos) ÅGP_INTTYPE_TYPE0_Pos (0) ÆGP_INTTYPE_TYPE0_Msk (0x1ul << GP_INTTYPE_TYPE0_Pos) ÈGP_INTTYPE_TYPE1_Pos (1) ÉGP_INTTYPE_TYPE1_Msk (0x1ul << GP_INTTYPE_TYPE1_Pos) ËGP_INTTYPE_TYPE2_Pos (2) ÌGP_INTTYPE_TYPE2_Msk (0x1ul << GP_INTTYPE_TYPE2_Pos) ÎGP_INTTYPE_TYPE3_Pos (3) ÏGP_INTTYPE_TYPE3_Msk (0x1ul << GP_INTTYPE_TYPE3_Pos) ÑGP_INTTYPE_TYPE4_Pos (4) ÒGP_INTTYPE_TYPE4_Msk (0x1ul << GP_INTTYPE_TYPE4_Pos) ÔGP_INTTYPE_TYPE5_Pos (5) ÕGP_INTTYPE_TYPE5_Msk (0x1ul << GP_INTTYPE_TYPE5_Pos) ×GP_INTTYPE_TYPE6_Pos (6) ØGP_INTTYPE_TYPE6_Msk (0x1ul << GP_INTTYPE_TYPE6_Pos) ÚGP_INTTYPE_TYPE7_Pos (7) ÛGP_INTTYPE_TYPE7_Msk (0x1ul << GP_INTTYPE_TYPE7_Pos) ÝGP_INTEN_FLIEN0_Pos (0) ÞGP_INTEN_FLIEN0_Msk (0x1ul << GP_INTEN_FLIEN0_Pos) àGP_INTEN_FLIEN1_Pos (1) áGP_INTEN_FLIEN1_Msk (0x1ul << GP_INTEN_FLIEN1_Pos) ãGP_INTEN_FLIEN2_Pos (2) äGP_INTEN_FLIEN2_Msk (0x1ul << GP_INTEN_FLIEN2_Pos) æGP_INTEN_FLIEN3_Pos (3) çGP_INTEN_FLIEN3_Msk (0x1ul << GP_INTEN_FLIEN3_Pos) éGP_INTEN_FLIEN4_Pos (4) êGP_INTEN_FLIEN4_Msk (0x1ul << GP_INTEN_FLIEN4_Pos) ìGP_INTEN_FLIEN5_Pos (5) íGP_INTEN_FLIEN5_Msk (0x1ul << GP_INTEN_FLIEN5_Pos) ïGP_INTEN_FLIEN6_Pos (6) ðGP_INTEN_FLIEN6_Msk (0x1ul << GP_INTEN_FLIEN6_Pos) òGP_INTEN_FLIEN7_Pos (7) óGP_INTEN_FLIEN7_Msk (0x1ul << GP_INTEN_FLIEN7_Pos) õGP_INTEN_RHIEN0_Pos (16) öGP_INTEN_RHIEN0_Msk (0x1ul << GP_INTEN_RHIEN0_Pos) øGP_INTEN_RHIEN1_Pos (17) ùGP_INTEN_RHIEN1_Msk (0x1ul << GP_INTEN_RHIEN1_Pos) ûGP_INTEN_RHIEN2_Pos (18) üGP_INTEN_RHIEN2_Msk (0x1ul << GP_INTEN_RHIEN2_Pos) þGP_INTEN_RHIEN3_Pos (19) ÿGP_INTEN_RHIEN3_Msk (0x1ul << GP_INTEN_RHIEN3_Pos) GP_INTEN_RHIEN4_Pos (20) GP_INTEN_RHIEN4_Msk (0x1ul << GP_INTEN_RHIEN4_Pos) GP_INTEN_RHIEN5_Pos (21)
GP_INTEN_RHIEN5_Msk (0x1ul << GP_INTEN_RHIEN5_Pos) GP_INTEN_RHIEN6_Pos (22) GP_INTEN_RHIEN6_Msk (0x1ul << GP_INTEN_RHIEN6_Pos) GP_INTEN_RHIEN7_Pos (23) GP_INTEN_RHIEN7_Msk (0x1ul << GP_INTEN_RHIEN7_Pos) GP_INTSRC_INTSRC0_Pos (0) GP_INTSRC_INTSRC0_Msk (0x1ul << GP_INTSRC_INTSRC0_Pos) GP_INTSRC_INTSRC1_Pos (1) GP_INTSRC_INTSRC1_Msk (0x1ul << GP_INTSRC_INTSRC1_Pos) GP_INTSRC_INTSRC2_Pos (2) GP_INTSRC_INTSRC2_Msk (0x1ul << GP_INTSRC_INTSRC2_Pos) GP_INTSRC_INTSRC3_Pos (3) GP_INTSRC_INTSRC3_Msk (0x1ul << GP_INTSRC_INTSRC3_Pos) GP_INTSRC_INTSRC4_Pos (4) GP_INTSRC_INTSRC4_Msk (0x1ul << GP_INTSRC_INTSRC4_Pos) GP_INTSRC_INTSRC5_Pos (5) GP_INTSRC_INTSRC5_Msk (0x1ul << GP_INTSRC_INTSRC5_Pos) GP_INTSRC_INTSRC6_Pos (6) GP_INTSRC_INTSRC6_Msk (0x1ul << GP_INTSRC_INTSRC6_Pos) ¢GP_INTSRC_INTSRC7_Pos (7) £GP_INTSRC_INTSRC7_Msk (0x1ul << GP_INTSRC_INTSRC7_Pos) ¥GP_INTSRC_INTSRC8_Pos (8) ¦GP_INTSRC_INTSRC8_Msk (0x1ul << GP_INTSRC_INTSRC8_Pos) ¨GP_INTSRC_INTSRC9_Pos (9) ©GP_INTSRC_INTSRC9_Msk (0x1ul << GP_INTSRC_INTSRC9_Pos) «GP_INTSRC_INTSRC10_Pos (10) ¬GP_INTSRC_INTSRC10_Msk (0x1ul << GP_INTSRC_INTSRC10_Pos) ®GP_INTSRC_INTSRC11_Pos (11) ¯GP_INTSRC_INTSRC11_Msk (0x1ul << GP_INTSRC_INTSRC11_Pos) ±GP_INTSRC_INTSRC12_Pos (12) ²GP_INTSRC_INTSRC12_Msk (0x1ul << GP_INTSRC_INTSRC12_Pos) ´GP_INTSRC_INTSRC13_Pos (13) µGP_INTSRC_INTSRC13_Msk (0x1ul << GP_INTSRC_INTSRC13_Pos) ·GP_INTSRC_INTSRC14_Pos (14) ¸GP_INTSRC_INTSRC14_Msk (0x1ul << GP_INTSRC_INTSRC14_Pos) ºGP_INTSRC_INTSRC15_Pos (15) »GP_INTSRC_INTSRC15_Msk (0x1ul << GP_INTSRC_INTSRC15_Pos) ½GP_MODE_MODE0_Pos (0) ¾GP_MODE_MODE0_Msk (0x3ul << GP_MODE_MODE0_Pos) ÀGP_MODE_MODE1_Pos (2) ÁGP_MODE_MODE1_Msk (0x3ul << GP_MODE_MODE1_Pos) ÃGP_MODE_MODE2_Pos (4) ÄGP_MODE_MODE2_Msk (0x3ul << GP_MODE_MODE2_Pos) ÆGP_MODE_MODE3_Pos (6) ÇGP_MODE_MODE3_Msk (0x3ul << GP_MODE_MODE3_Pos) ÉGP_MODE_MODE4_Pos (8) ÊGP_MODE_MODE4_Msk (0x3ul << GP_MODE_MODE4_Pos) ÌGP_MODE_MODE5_Pos (10) ÍGP_MODE_MODE5_Msk (0x3ul << GP_MODE_MODE5_Pos) ÏGP_DINOFF_DINOFF0_Pos (16) ÐGP_DINOFF_DINOFF0_Msk (0x1ul << GP_DINOFF_DINOFF0_Pos) ÒGP_DINOFF_DINOFF1_Pos (17) ÓGP_DINOFF_DINOFF1_Msk (0x1ul << GP_DINOFF_DINOFF1_Pos) ÕGP_DINOFF_DINOFF2_Pos (18) ÖGP_DINOFF_DINOFF2_Msk (0x1ul << GP_DINOFF_DINOFF2_Pos) ØGP_DINOFF_DINOFF3_Pos (19) ÙGP_DINOFF_DINOFF3_Msk (0x1ul << GP_DINOFF_DINOFF3_Pos) ÛGP_DINOFF_DINOFF4_Pos (20) ÜGP_DINOFF_DINOFF4_Msk (0x1ul << GP_DINOFF_DINOFF4_Pos) ÞGP_DINOFF_DINOFF5_Pos (21) ßGP_DINOFF_DINOFF5_Msk (0x1ul << GP_DINOFF_DINOFF5_Pos) áGP_DINOFF_DINOFF6_Pos (22) âGP_DINOFF_DINOFF6_Msk (0x1ul << GP_DINOFF_DINOFF6_Pos) äGP_DINOFF_DINOFF7_Pos (23) åGP_DINOFF_DINOFF7_Msk (0x1ul << GP_DINOFF_DINOFF7_Pos) çGP_DOUT_DOUT0_Pos (0) èGP_DOUT_DOUT0_Msk (0x1ul << GP_DOUT_DOUT0_Pos) êGP_DOUT_DOUT1_Pos (1) ëGP_DOUT_DOUT1_Msk (0x1ul << GP_DOUT_DOUT1_Pos) íGP_DOUT_DOUT2_Pos (2) îGP_DOUT_DOUT2_Msk (0x1ul << GP_DOUT_DOUT2_Pos) ðGP_DOUT_DOUT3_Pos (3) ñGP_DOUT_DOUT3_Msk (0x1ul << GP_DOUT_DOUT3_Pos) óGP_DOUT_DOUT4_Pos (4) ôGP_DOUT_DOUT4_Msk (0x1ul << GP_DOUT_DOUT4_Pos) öGP_DOUT_DOUT5_Pos (5) ÷GP_DOUT_DOUT5_Msk (0x1ul << GP_DOUT_DOUT5_Pos) ùGP_DOUT_DOUT6_Pos (6) úGP_DOUT_DOUT6_Msk (0x1ul << GP_DOUT_DOUT6_Pos) üGP_DOUT_DOUT7_Pos (7) ýGP_DOUT_DOUT7_Msk (0x1ul << GP_DOUT_DOUT7_Pos) ÿGP_DATMSK_DATMSK0_Pos (0) GP_DATMSK_DATMSK0_Msk (0x1ul << GP_DATMSK_DATMSK0_Pos) GP_DATMSK_DATMSK1_Pos (1) GP_DATMSK_DATMSK1_Msk (0x1ul << GP_DATMSK_DATMSK1_Pos)
GP_DATMSK_DATMSK2_Pos (2) GP_DATMSK_DATMSK2_Msk (0x1ul << GP_DATMSK_DATMSK2_Pos) GP_DATMSK_DATMSK3_Pos (3) GP_DATMSK_DATMSK3_Msk (0x1ul << GP_DATMSK_DATMSK3_Pos) GP_DATMSK_DATMSK4_Pos (4) GP_DATMSK_DATMSK4_Msk (0x1ul << GP_DATMSK_DATMSK4_Pos) GP_DATMSK_DATMSK5_Pos (5) GP_DATMSK_DATMSK5_Msk (0x1ul << GP_DATMSK_DATMSK5_Pos) GP_DATMSK_DATMSK6_Pos (6) GP_DATMSK_DATMSK6_Msk (0x1ul << GP_DATMSK_DATMSK6_Pos) GP_DATMSK_DATMSK7_Pos (7) GP_DATMSK_DATMSK7_Msk (0x1ul << GP_DATMSK_DATMSK7_Pos) GP_PIN_PIN0_Pos (0) GP_PIN_PIN0_Msk (0x1ul << GP_PIN_PIN0_Pos) GP_PIN_PIN1_Pos (1) GP_PIN_PIN1_Msk (0x1ul << GP_PIN_PIN1_Pos) GP_PIN_PIN2_Pos (2) GP_PIN_PIN2_Msk (0x1ul << GP_PIN_PIN2_Pos) GP_PIN_PIN3_Pos (3) ¡GP_PIN_PIN3_Msk (0x1ul << GP_PIN_PIN3_Pos) £GP_PIN_PIN4_Pos (4) ¤GP_PIN_PIN4_Msk (0x1ul << GP_PIN_PIN4_Pos) ¦GP_PIN_PIN5_Pos (5) §GP_PIN_PIN5_Msk (0x1ul << GP_PIN_PIN5_Pos) ©GP_PIN_PIN6_Pos (6) ªGP_PIN_PIN6_Msk (0x1ul << GP_PIN_PIN6_Pos) ¬GP_PIN_PIN7_Pos (7) GP_PIN_PIN7_Msk (0x1ul << GP_PIN_PIN7_Pos) ¯GP_DBEN_DBEN0_Pos (0) °GP_DBEN_DBEN0_Msk (0x1ul << GP_DBEN_DBEN0_Pos) ²GP_DBEN_DBEN1_Pos (1) ³GP_DBEN_DBEN1_Msk (0x1ul << GP_DBEN_DBEN1_Pos) µGP_DBEN_DBEN2_Pos (2) ¶GP_DBEN_DBEN2_Msk (0x1ul << GP_DBEN_DBEN2_Pos) ¸GP_DBEN_DBEN3_Pos (3) ¹GP_DBEN_DBEN3_Msk (0x1ul << GP_DBEN_DBEN3_Pos) »GP_DBEN_DBEN4_Pos (4) ¼GP_DBEN_DBEN4_Msk (0x1ul << GP_DBEN_DBEN4_Pos) ¾GP_DBEN_DBEN5_Pos (5) ¿GP_DBEN_DBEN5_Msk (0x1ul << GP_DBEN_DBEN5_Pos) ÁGP_DBEN_DBEN6_Pos (6) ÂGP_DBEN_DBEN6_Msk (0x1ul << GP_DBEN_DBEN6_Pos) ÄGP_DBEN_DBEN7_Pos (7) ÅGP_DBEN_DBEN7_Msk (0x1ul << GP_DBEN_DBEN7_Pos) ÇGP_INTTYPE_TYPE0_Pos (0) ÈGP_INTTYPE_TYPE0_Msk (0x1ul << GP_INTTYPE_TYPE0_Pos) ÊGP_INTTYPE_TYPE1_Pos (1) ËGP_INTTYPE_TYPE1_Msk (0x1ul << GP_INTTYPE_TYPE1_Pos) ÍGP_INTTYPE_TYPE2_Pos (2) ÎGP_INTTYPE_TYPE2_Msk (0x1ul << GP_INTTYPE_TYPE2_Pos) ÐGP_INTTYPE_TYPE3_Pos (3) ÑGP_INTTYPE_TYPE3_Msk (0x1ul << GP_INTTYPE_TYPE3_Pos) ÓGP_INTTYPE_TYPE4_Pos (4) ÔGP_INTTYPE_TYPE4_Msk (0x1ul << GP_INTTYPE_TYPE4_Pos) ÖGP_INTTYPE_TYPE5_Pos (5) ×GP_INTTYPE_TYPE5_Msk (0x1ul << GP_INTTYPE_TYPE5_Pos) ÙGP_INTTYPE_TYPE6_Pos (6) ÚGP_INTTYPE_TYPE6_Msk (0x1ul << GP_INTTYPE_TYPE6_Pos) ÜGP_INTTYPE_TYPE7_Pos (7) ÝGP_INTTYPE_TYPE7_Msk (0x1ul << GP_INTTYPE_TYPE7_Pos) ßGP_INTEN_FLIEN0_Pos (0) àGP_INTEN_FLIEN0_Msk (0x1ul << GP_INTEN_FLIEN0_Pos) âGP_INTEN_FLIEN1_Pos (1) ãGP_INTEN_FLIEN1_Msk (0x1ul << GP_INTEN_FLIEN1_Pos) åGP_INTEN_FLIEN2_Pos (2) æGP_INTEN_FLIEN2_Msk (0x1ul << GP_INTEN_FLIEN2_Pos) èGP_INTEN_FLIEN3_Pos (3) éGP_INTEN_FLIEN3_Msk (0x1ul << GP_INTEN_FLIEN3_Pos) ëGP_INTEN_FLIEN4_Pos (4) ìGP_INTEN_FLIEN4_Msk (0x1ul << GP_INTEN_FLIEN4_Pos) îGP_INTEN_FLIEN5_Pos (5) ïGP_INTEN_FLIEN5_Msk (0x1ul << GP_INTEN_FLIEN5_Pos) ñGP_INTEN_FLIEN6_Pos (6) òGP_INTEN_FLIEN6_Msk (0x1ul << GP_INTEN_FLIEN6_Pos) ôGP_INTEN_FLIEN7_Pos (7) õGP_INTEN_FLIEN7_Msk (0x1ul << GP_INTEN_FLIEN7_Pos) ÷GP_INTEN_RHIEN0_Pos (16) øGP_INTEN_RHIEN0_Msk (0x1ul << GP_INTEN_RHIEN0_Pos) úGP_INTEN_RHIEN1_Pos (17) ûGP_INTEN_RHIEN1_Msk (0x1ul << GP_INTEN_RHIEN1_Pos) ýGP_INTEN_RHIEN2_Pos (18) þGP_INTEN_RHIEN2_Msk (0x1ul << GP_INTEN_RHIEN2_Pos) GP_INTEN_RHIEN3_Pos (19) GP_INTEN_RHIEN3_Msk (0x1ul << GP_INTEN_RHIEN3_Pos) GP_INTEN_RHIEN4_Pos (20) GP_INTEN_RHIEN4_Msk (0x1ul << GP_INTEN_RHIEN4_Pos) GP_INTEN_RHIEN5_Pos (21) GP_INTEN_RHIEN5_Msk (0x1ul << GP_INTEN_RHIEN5_Pos) GP_INTEN_RHIEN6_Pos (22) GP_INTEN_RHIEN6_Msk (0x1ul << GP_INTEN_RHIEN6_Pos) GP_INTEN_RHIEN7_Pos (23) GP_INTEN_RHIEN7_Msk (0x1ul << GP_INTEN_RHIEN7_Pos) GP_INTSRC_INTSRC0_Pos (0) GP_INTSRC_INTSRC0_Msk (0x1ul << GP_INTSRC_INTSRC0_Pos) GP_INTSRC_INTSRC1_Pos (1) GP_INTSRC_INTSRC1_Msk (0x1ul << GP_INTSRC_INTSRC1_Pos) GP_INTSRC_INTSRC2_Pos (2) GP_INTSRC_INTSRC2_Msk (0x1ul << GP_INTSRC_INTSRC2_Pos) GP_INTSRC_INTSRC3_Pos (3) GP_INTSRC_INTSRC3_Msk (0x1ul << GP_INTSRC_INTSRC3_Pos) GP_INTSRC_INTSRC4_Pos (4) GP_INTSRC_INTSRC4_Msk (0x1ul << GP_INTSRC_INTSRC4_Pos) GP_INTSRC_INTSRC5_Pos (5) GP_INTSRC_INTSRC5_Msk (0x1ul << GP_INTSRC_INTSRC5_Pos) ¡GP_INTSRC_INTSRC6_Pos (6) ¢GP_INTSRC_INTSRC6_Msk (0x1ul << GP_INTSRC_INTSRC6_Pos) ¤GP_INTSRC_INTSRC7_Pos (7) ¥GP_INTSRC_INTSRC7_Msk (0x1ul << GP_INTSRC_INTSRC7_Pos) §GP_INTSRC_INTSRC8_Pos (8) ¨GP_INTSRC_INTSRC8_Msk (0x1ul << GP_INTSRC_INTSRC8_Pos) ªGP_INTSRC_INTSRC9_Pos (9) «GP_INTSRC_INTSRC9_Msk (0x1ul << GP_INTSRC_INTSRC9_Pos) GP_INTSRC_INTSRC10_Pos (10) ®GP_INTSRC_INTSRC10_Msk (0x1ul << GP_INTSRC_INTSRC10_Pos) °GP_INTSRC_INTSRC11_Pos (11) ±GP_INTSRC_INTSRC11_Msk (0x1ul << GP_INTSRC_INTSRC11_Pos) ³GP_INTSRC_INTSRC12_Pos (12) ´GP_INTSRC_INTSRC12_Msk (0x1ul << GP_INTSRC_INTSRC12_Pos) ¶GP_INTSRC_INTSRC13_Pos (13) ·GP_INTSRC_INTSRC13_Msk (0x1ul << GP_INTSRC_INTSRC13_Pos) ¹GP_INTSRC_INTSRC14_Pos (14) ºGP_INTSRC_INTSRC14_Msk (0x1ul << GP_INTSRC_INTSRC14_Pos) ¼GP_INTSRC_INTSRC15_Pos (15) ½GP_INTSRC_INTSRC15_Msk (0x1ul << GP_INTSRC_INTSRC15_Pos) ¿GP_MODE_MODE0_Pos (0) ÀGP_MODE_MODE0_Msk (0x3ul << GP_MODE_MODE0_Pos) ÂGP_MODE_MODE1_Pos (2) ÃGP_MODE_MODE1_Msk (0x3ul << GP_MODE_MODE1_Pos) ÅGP_MODE_MODE2_Pos (4) ÆGP_MODE_MODE2_Msk (0x3ul << GP_MODE_MODE2_Pos) ÈGP_MODE_MODE3_Pos (6) ÉGP_MODE_MODE3_Msk (0x3ul << GP_MODE_MODE3_Pos) ËGP_MODE_MODE4_Pos (8) ÌGP_MODE_MODE4_Msk (0x3ul << GP_MODE_MODE4_Pos) ÎGP_MODE_MODE5_Pos (10) ÏGP_MODE_MODE5_Msk (0x3ul << GP_MODE_MODE5_Pos) ÑGP_DINOFF_DINOFF0_Pos (16) ÒGP_DINOFF_DINOFF0_Msk (0x1ul << GP_DINOFF_DINOFF0_Pos) ÔGP_DINOFF_DINOFF1_Pos (17) ÕGP_DINOFF_DINOFF1_Msk (0x1ul << GP_DINOFF_DINOFF1_Pos) ×GP_DINOFF_DINOFF2_Pos (18) ØGP_DINOFF_DINOFF2_Msk (0x1ul << GP_DINOFF_DINOFF2_Pos) ÚGP_DINOFF_DINOFF3_Pos (19) ÛGP_DINOFF_DINOFF3_Msk (0x1ul << GP_DINOFF_DINOFF3_Pos) ÝGP_DINOFF_DINOFF4_Pos (20) ÞGP_DINOFF_DINOFF4_Msk (0x1ul << GP_DINOFF_DINOFF4_Pos) àGP_DINOFF_DINOFF5_Pos (21) áGP_DINOFF_DINOFF5_Msk (0x1ul << GP_DINOFF_DINOFF5_Pos) ãGP_DINOFF_DINOFF6_Pos (22) äGP_DINOFF_DINOFF6_Msk (0x1ul << GP_DINOFF_DINOFF6_Pos) æGP_DINOFF_DINOFF7_Pos (23) çGP_DINOFF_DINOFF7_Msk (0x1ul << GP_DINOFF_DINOFF7_Pos) éGP_DOUT_DOUT0_Pos (0) êGP_DOUT_DOUT0_Msk (0x1ul << GP_DOUT_DOUT0_Pos) ìGP_DOUT_DOUT1_Pos (1) íGP_DOUT_DOUT1_Msk (0x1ul << GP_DOUT_DOUT1_Pos) ïGP_DOUT_DOUT2_Pos (2) ðGP_DOUT_DOUT2_Msk (0x1ul << GP_DOUT_DOUT2_Pos) òGP_DOUT_DOUT3_Pos (3) óGP_DOUT_DOUT3_Msk (0x1ul << GP_DOUT_DOUT3_Pos) õGP_DOUT_DOUT4_Pos (4) öGP_DOUT_DOUT4_Msk (0x1ul << GP_DOUT_DOUT4_Pos) øGP_DOUT_DOUT5_Pos (5) ùGP_DOUT_DOUT5_Msk (0x1ul << GP_DOUT_DOUT5_Pos) ûGP_DOUT_DOUT6_Pos (6) üGP_DOUT_DOUT6_Msk (0x1ul << GP_DOUT_DOUT6_Pos) þGP_DOUT_DOUT7_Pos (7) ÿGP_DOUT_DOUT7_Msk (0x1ul << GP_DOUT_DOUT7_Pos) GP_DATMSK_DATMSK0_Pos (0) GP_DATMSK_DATMSK0_Msk (0x1ul << GP_DATMSK_DATMSK0_Pos) GP_DATMSK_DATMSK1_Pos (1)
GP_DATMSK_DATMSK1_Msk (0x1ul << GP_DATMSK_DATMSK1_Pos) GP_DATMSK_DATMSK2_Pos (2) GP_DATMSK_DATMSK2_Msk (0x1ul << GP_DATMSK_DATMSK2_Pos) GP_DATMSK_DATMSK3_Pos (3) GP_DATMSK_DATMSK3_Msk (0x1ul << GP_DATMSK_DATMSK3_Pos) GP_DATMSK_DATMSK4_Pos (4) GP_DATMSK_DATMSK4_Msk (0x1ul << GP_DATMSK_DATMSK4_Pos) GP_DATMSK_DATMSK5_Pos (5) GP_DATMSK_DATMSK5_Msk (0x1ul << GP_DATMSK_DATMSK5_Pos) GP_DATMSK_DATMSK6_Pos (6) GP_DATMSK_DATMSK6_Msk (0x1ul << GP_DATMSK_DATMSK6_Pos) GP_DATMSK_DATMSK7_Pos (7) GP_DATMSK_DATMSK7_Msk (0x1ul << GP_DATMSK_DATMSK7_Pos) GP_PIN_PIN0_Pos (0) GP_PIN_PIN0_Msk (0x1ul << GP_PIN_PIN0_Pos) GP_PIN_PIN1_Pos (1) GP_PIN_PIN1_Msk (0x1ul << GP_PIN_PIN1_Pos) GP_PIN_PIN2_Pos (2) GP_PIN_PIN2_Msk (0x1ul << GP_PIN_PIN2_Pos) ¢GP_PIN_PIN3_Pos (3) £GP_PIN_PIN3_Msk (0x1ul << GP_PIN_PIN3_Pos) ¥GP_PIN_PIN4_Pos (4) ¦GP_PIN_PIN4_Msk (0x1ul << GP_PIN_PIN4_Pos) ¨GP_PIN_PIN5_Pos (5) ©GP_PIN_PIN5_Msk (0x1ul << GP_PIN_PIN5_Pos) «GP_PIN_PIN6_Pos (6) ¬GP_PIN_PIN6_Msk (0x1ul << GP_PIN_PIN6_Pos) ®GP_PIN_PIN7_Pos (7) ¯GP_PIN_PIN7_Msk (0x1ul << GP_PIN_PIN7_Pos) ±GP_DBEN_DBEN0_Pos (0) ²GP_DBEN_DBEN0_Msk (0x1ul << GP_DBEN_DBEN0_Pos) ´GP_DBEN_DBEN1_Pos (1) µGP_DBEN_DBEN1_Msk (0x1ul << GP_DBEN_DBEN1_Pos) ·GP_DBEN_DBEN2_Pos (2) ¸GP_DBEN_DBEN2_Msk (0x1ul << GP_DBEN_DBEN2_Pos) ºGP_DBEN_DBEN3_Pos (3) »GP_DBEN_DBEN3_Msk (0x1ul << GP_DBEN_DBEN3_Pos) ½GP_DBEN_DBEN4_Pos (4) ¾GP_DBEN_DBEN4_Msk (0x1ul << GP_DBEN_DBEN4_Pos) ÀGP_DBEN_DBEN5_Pos (5) ÁGP_DBEN_DBEN5_Msk (0x1ul << GP_DBEN_DBEN5_Pos) ÃGP_DBEN_DBEN6_Pos (6) ÄGP_DBEN_DBEN6_Msk (0x1ul << GP_DBEN_DBEN6_Pos) ÆGP_DBEN_DBEN7_Pos (7) ÇGP_DBEN_DBEN7_Msk (0x1ul << GP_DBEN_DBEN7_Pos) ÉGP_INTTYPE_TYPE0_Pos (0) ÊGP_INTTYPE_TYPE0_Msk (0x1ul << GP_INTTYPE_TYPE0_Pos) ÌGP_INTTYPE_TYPE1_Pos (1) ÍGP_INTTYPE_TYPE1_Msk (0x1ul << GP_INTTYPE_TYPE1_Pos) ÏGP_INTTYPE_TYPE2_Pos (2) ÐGP_INTTYPE_TYPE2_Msk (0x1ul << GP_INTTYPE_TYPE2_Pos) ÒGP_INTTYPE_TYPE3_Pos (3) ÓGP_INTTYPE_TYPE3_Msk (0x1ul << GP_INTTYPE_TYPE3_Pos) ÕGP_INTTYPE_TYPE4_Pos (4) ÖGP_INTTYPE_TYPE4_Msk (0x1ul << GP_INTTYPE_TYPE4_Pos) ØGP_INTTYPE_TYPE5_Pos (5) ÙGP_INTTYPE_TYPE5_Msk (0x1ul << GP_INTTYPE_TYPE5_Pos) ÛGP_INTTYPE_TYPE6_Pos (6) ÜGP_INTTYPE_TYPE6_Msk (0x1ul << GP_INTTYPE_TYPE6_Pos) ÞGP_INTTYPE_TYPE7_Pos (7) ßGP_INTTYPE_TYPE7_Msk (0x1ul << GP_INTTYPE_TYPE7_Pos) áGP_INTEN_FLIEN0_Pos (0) âGP_INTEN_FLIEN0_Msk (0x1ul << GP_INTEN_FLIEN0_Pos) äGP_INTEN_FLIEN1_Pos (1) åGP_INTEN_FLIEN1_Msk (0x1ul << GP_INTEN_FLIEN1_Pos) çGP_INTEN_FLIEN2_Pos (2) èGP_INTEN_FLIEN2_Msk (0x1ul << GP_INTEN_FLIEN2_Pos) êGP_INTEN_FLIEN3_Pos (3) ëGP_INTEN_FLIEN3_Msk (0x1ul << GP_INTEN_FLIEN3_Pos) íGP_INTEN_FLIEN4_Pos (4) îGP_INTEN_FLIEN4_Msk (0x1ul << GP_INTEN_FLIEN4_Pos) ðGP_INTEN_FLIEN5_Pos (5) ñGP_INTEN_FLIEN5_Msk (0x1ul << GP_INTEN_FLIEN5_Pos) óGP_INTEN_FLIEN6_Pos (6) ôGP_INTEN_FLIEN6_Msk (0x1ul << GP_INTEN_FLIEN6_Pos) öGP_INTEN_FLIEN7_Pos (7) ÷GP_INTEN_FLIEN7_Msk (0x1ul << GP_INTEN_FLIEN7_Pos) ùGP_INTEN_RHIEN0_Pos (16) úGP_INTEN_RHIEN0_Msk (0x1ul << GP_INTEN_RHIEN0_Pos) üGP_INTEN_RHIEN1_Pos (17) ýGP_INTEN_RHIEN1_Msk (0x1ul << GP_INTEN_RHIEN1_Pos) ÿGP_INTEN_RHIEN2_Pos (18) GP_INTEN_RHIEN2_Msk (0x1ul << GP_INTEN_RHIEN2_Pos) GP_INTEN_RHIEN3_Pos (19) GP_INTEN_RHIEN3_Msk (0x1ul << GP_INTEN_RHIEN3_Pos)
GP_INTEN_RHIEN4_Pos (20) GP_INTEN_RHIEN4_Msk (0x1ul << GP_INTEN_RHIEN4_Pos) GP_INTEN_RHIEN5_Pos (21) GP_INTEN_RHIEN5_Msk (0x1ul << GP_INTEN_RHIEN5_Pos) GP_INTEN_RHIEN6_Pos (22) GP_INTEN_RHIEN6_Msk (0x1ul << GP_INTEN_RHIEN6_Pos) GP_INTEN_RHIEN7_Pos (23) GP_INTEN_RHIEN7_Msk (0x1ul << GP_INTEN_RHIEN7_Pos) GP_INTSRC_INTSRC0_Pos (0) GP_INTSRC_INTSRC0_Msk (0x1ul << GP_INTSRC_INTSRC0_Pos) GP_INTSRC_INTSRC1_Pos (1) GP_INTSRC_INTSRC1_Msk (0x1ul << GP_INTSRC_INTSRC1_Pos) GP_INTSRC_INTSRC2_Pos (2) GP_INTSRC_INTSRC2_Msk (0x1ul << GP_INTSRC_INTSRC2_Pos) GP_INTSRC_INTSRC3_Pos (3) GP_INTSRC_INTSRC3_Msk (0x1ul << GP_INTSRC_INTSRC3_Pos) GP_INTSRC_INTSRC4_Pos (4) GP_INTSRC_INTSRC4_Msk (0x1ul << GP_INTSRC_INTSRC4_Pos) GP_INTSRC_INTSRC5_Pos (5) ¡GP_INTSRC_INTSRC5_Msk (0x1ul << GP_INTSRC_INTSRC5_Pos) £GP_INTSRC_INTSRC6_Pos (6) ¤GP_INTSRC_INTSRC6_Msk (0x1ul << GP_INTSRC_INTSRC6_Pos) ¦GP_INTSRC_INTSRC7_Pos (7) §GP_INTSRC_INTSRC7_Msk (0x1ul << GP_INTSRC_INTSRC7_Pos) ©GP_INTSRC_INTSRC8_Pos (8) ªGP_INTSRC_INTSRC8_Msk (0x1ul << GP_INTSRC_INTSRC8_Pos) ¬GP_INTSRC_INTSRC9_Pos (9) GP_INTSRC_INTSRC9_Msk (0x1ul << GP_INTSRC_INTSRC9_Pos) ¯GP_INTSRC_INTSRC10_Pos (10) °GP_INTSRC_INTSRC10_Msk (0x1ul << GP_INTSRC_INTSRC10_Pos) ²GP_INTSRC_INTSRC11_Pos (11) ³GP_INTSRC_INTSRC11_Msk (0x1ul << GP_INTSRC_INTSRC11_Pos) µGP_INTSRC_INTSRC12_Pos (12) ¶GP_INTSRC_INTSRC12_Msk (0x1ul << GP_INTSRC_INTSRC12_Pos) ¸GP_INTSRC_INTSRC13_Pos (13) ¹GP_INTSRC_INTSRC13_Msk (0x1ul << GP_INTSRC_INTSRC13_Pos) »GP_INTSRC_INTSRC14_Pos (14) ¼GP_INTSRC_INTSRC14_Msk (0x1ul << GP_INTSRC_INTSRC14_Pos) ¾GP_INTSRC_INTSRC15_Pos (15) ¿GP_INTSRC_INTSRC15_Msk (0x1ul << GP_INTSRC_INTSRC15_Pos) ÁGP_MODE_MODE0_Pos (0) ÂGP_MODE_MODE0_Msk (0x3ul << GP_MODE_MODE0_Pos) ÄGP_MODE_MODE1_Pos (2) ÅGP_MODE_MODE1_Msk (0x3ul << GP_MODE_MODE1_Pos) ÇGP_MODE_MODE2_Pos (4) ÈGP_MODE_MODE2_Msk (0x3ul << GP_MODE_MODE2_Pos) ÊGP_MODE_MODE3_Pos (6) ËGP_MODE_MODE3_Msk (0x3ul << GP_MODE_MODE3_Pos) ÍGP_MODE_MODE4_Pos (8) ÎGP_MODE_MODE4_Msk (0x3ul << GP_MODE_MODE4_Pos) ÐGP_MODE_MODE5_Pos (10) ÑGP_MODE_MODE5_Msk (0x3ul << GP_MODE_MODE5_Pos) ÓGP_DINOFF_DINOFF0_Pos (16) ÔGP_DINOFF_DINOFF0_Msk (0x1ul << GP_DINOFF_DINOFF0_Pos) ÖGP_DINOFF_DINOFF1_Pos (17) ×GP_DINOFF_DINOFF1_Msk (0x1ul << GP_DINOFF_DINOFF1_Pos) ÙGP_DINOFF_DINOFF2_Pos (18) ÚGP_DINOFF_DINOFF2_Msk (0x1ul << GP_DINOFF_DINOFF2_Pos) ÜGP_DINOFF_DINOFF3_Pos (19) ÝGP_DINOFF_DINOFF3_Msk (0x1ul << GP_DINOFF_DINOFF3_Pos) ßGP_DINOFF_DINOFF4_Pos (20) àGP_DINOFF_DINOFF4_Msk (0x1ul << GP_DINOFF_DINOFF4_Pos) âGP_DINOFF_DINOFF5_Pos (21) ãGP_DINOFF_DINOFF5_Msk (0x1ul << GP_DINOFF_DINOFF5_Pos) åGP_DINOFF_DINOFF6_Pos (22) æGP_DINOFF_DINOFF6_Msk (0x1ul << GP_DINOFF_DINOFF6_Pos) èGP_DINOFF_DINOFF7_Pos (23) éGP_DINOFF_DINOFF7_Msk (0x1ul << GP_DINOFF_DINOFF7_Pos) ëGP_DOUT_DOUT0_Pos (0) ìGP_DOUT_DOUT0_Msk (0x1ul << GP_DOUT_DOUT0_Pos) îGP_DOUT_DOUT1_Pos (1) ïGP_DOUT_DOUT1_Msk (0x1ul << GP_DOUT_DOUT1_Pos) ñGP_DOUT_DOUT2_Pos (2) òGP_DOUT_DOUT2_Msk (0x1ul << GP_DOUT_DOUT2_Pos) ôGP_DOUT_DOUT3_Pos (3) õGP_DOUT_DOUT3_Msk (0x1ul << GP_DOUT_DOUT3_Pos) ÷GP_DOUT_DOUT4_Pos (4) øGP_DOUT_DOUT4_Msk (0x1ul << GP_DOUT_DOUT4_Pos) úGP_DOUT_DOUT5_Pos (5) ûGP_DOUT_DOUT5_Msk (0x1ul << GP_DOUT_DOUT5_Pos) ýGP_DOUT_DOUT6_Pos (6) þGP_DOUT_DOUT6_Msk (0x1ul << GP_DOUT_DOUT6_Pos) GP_DOUT_DOUT7_Pos (7) GP_DOUT_DOUT7_Msk (0x1ul << GP_DOUT_DOUT7_Pos) GP_DATMSK_DATMSK0_Pos (0) GP_DATMSK_DATMSK0_Msk (0x1ul << GP_DATMSK_DATMSK0_Pos) GP_DATMSK_DATMSK1_Pos (1) GP_DATMSK_DATMSK1_Msk (0x1ul << GP_DATMSK_DATMSK1_Pos) GP_DATMSK_DATMSK2_Pos (2) GP_DATMSK_DATMSK2_Msk (0x1ul << GP_DATMSK_DATMSK2_Pos) GP_DATMSK_DATMSK3_Pos (3) GP_DATMSK_DATMSK3_Msk (0x1ul << GP_DATMSK_DATMSK3_Pos) GP_DATMSK_DATMSK4_Pos (4) GP_DATMSK_DATMSK4_Msk (0x1ul << GP_DATMSK_DATMSK4_Pos) GP_DATMSK_DATMSK5_Pos (5) GP_DATMSK_DATMSK5_Msk (0x1ul << GP_DATMSK_DATMSK5_Pos) GP_DATMSK_DATMSK6_Pos (6) GP_DATMSK_DATMSK6_Msk (0x1ul << GP_DATMSK_DATMSK6_Pos) GP_DATMSK_DATMSK7_Pos (7) GP_DATMSK_DATMSK7_Msk (0x1ul << GP_DATMSK_DATMSK7_Pos) GP_PIN_PIN0_Pos (0) GP_PIN_PIN0_Msk (0x1ul << GP_PIN_PIN0_Pos) GP_PIN_PIN1_Pos (1) GP_PIN_PIN1_Msk (0x1ul << GP_PIN_PIN1_Pos) ¡GP_PIN_PIN2_Pos (2) ¢GP_PIN_PIN2_Msk (0x1ul << GP_PIN_PIN2_Pos) ¤GP_PIN_PIN3_Pos (3) ¥GP_PIN_PIN3_Msk (0x1ul << GP_PIN_PIN3_Pos) §GP_PIN_PIN4_Pos (4) ¨GP_PIN_PIN4_Msk (0x1ul << GP_PIN_PIN4_Pos) ªGP_PIN_PIN5_Pos (5) «GP_PIN_PIN5_Msk (0x1ul << GP_PIN_PIN5_Pos) GP_PIN_PIN6_Pos (6) ®GP_PIN_PIN6_Msk (0x1ul << GP_PIN_PIN6_Pos) °GP_PIN_PIN7_Pos (7) ±GP_PIN_PIN7_Msk (0x1ul << GP_PIN_PIN7_Pos) ³GP_DBEN_DBEN0_Pos (0) ´GP_DBEN_DBEN0_Msk (0x1ul << GP_DBEN_DBEN0_Pos) ¶GP_DBEN_DBEN1_Pos (1) ·GP_DBEN_DBEN1_Msk (0x1ul << GP_DBEN_DBEN1_Pos) ¹GP_DBEN_DBEN2_Pos (2) ºGP_DBEN_DBEN2_Msk (0x1ul << GP_DBEN_DBEN2_Pos) ¼GP_DBEN_DBEN3_Pos (3) ½GP_DBEN_DBEN3_Msk (0x1ul << GP_DBEN_DBEN3_Pos) ¿GP_DBEN_DBEN4_Pos (4) ÀGP_DBEN_DBEN4_Msk (0x1ul << GP_DBEN_DBEN4_Pos) ÂGP_DBEN_DBEN5_Pos (5) ÃGP_DBEN_DBEN5_Msk (0x1ul << GP_DBEN_DBEN5_Pos) ÅGP_DBEN_DBEN6_Pos (6) ÆGP_DBEN_DBEN6_Msk (0x1ul << GP_DBEN_DBEN6_Pos) ÈGP_DBEN_DBEN7_Pos (7) ÉGP_DBEN_DBEN7_Msk (0x1ul << GP_DBEN_DBEN7_Pos) ËGP_INTTYPE_TYPE0_Pos (0) ÌGP_INTTYPE_TYPE0_Msk (0x1ul << GP_INTTYPE_TYPE0_Pos) ÎGP_INTTYPE_TYPE1_Pos (1) ÏGP_INTTYPE_TYPE1_Msk (0x1ul << GP_INTTYPE_TYPE1_Pos) ÑGP_INTTYPE_TYPE2_Pos (2) ÒGP_INTTYPE_TYPE2_Msk (0x1ul << GP_INTTYPE_TYPE2_Pos) ÔGP_INTTYPE_TYPE3_Pos (3) ÕGP_INTTYPE_TYPE3_Msk (0x1ul << GP_INTTYPE_TYPE3_Pos) ×GP_INTTYPE_TYPE4_Pos (4) ØGP_INTTYPE_TYPE4_Msk (0x1ul << GP_INTTYPE_TYPE4_Pos) ÚGP_INTTYPE_TYPE5_Pos (5) ÛGP_INTTYPE_TYPE5_Msk (0x1ul << GP_INTTYPE_TYPE5_Pos) ÝGP_INTTYPE_TYPE6_Pos (6) ÞGP_INTTYPE_TYPE6_Msk (0x1ul << GP_INTTYPE_TYPE6_Pos) àGP_INTTYPE_TYPE7_Pos (7) áGP_INTTYPE_TYPE7_Msk (0x1ul << GP_INTTYPE_TYPE7_Pos) ãGP_INTEN_FLIEN0_Pos (0) äGP_INTEN_FLIEN0_Msk (0x1ul << GP_INTEN_FLIEN0_Pos) æGP_INTEN_FLIEN1_Pos (1) çGP_INTEN_FLIEN1_Msk (0x1ul << GP_INTEN_FLIEN1_Pos) éGP_INTEN_FLIEN2_Pos (2) êGP_INTEN_FLIEN2_Msk (0x1ul << GP_INTEN_FLIEN2_Pos) ìGP_INTEN_FLIEN3_Pos (3) íGP_INTEN_FLIEN3_Msk (0x1ul << GP_INTEN_FLIEN3_Pos) ïGP_INTEN_FLIEN4_Pos (4) ðGP_INTEN_FLIEN4_Msk (0x1ul << GP_INTEN_FLIEN4_Pos) òGP_INTEN_FLIEN5_Pos (5) óGP_INTEN_FLIEN5_Msk (0x1ul << GP_INTEN_FLIEN5_Pos) õGP_INTEN_FLIEN6_Pos (6) öGP_INTEN_FLIEN6_Msk (0x1ul << GP_INTEN_FLIEN6_Pos) øGP_INTEN_FLIEN7_Pos (7) ùGP_INTEN_FLIEN7_Msk (0x1ul << GP_INTEN_FLIEN7_Pos) ûGP_INTEN_RHIEN0_Pos (16) üGP_INTEN_RHIEN0_Msk (0x1ul << GP_INTEN_RHIEN0_Pos) þGP_INTEN_RHIEN1_Pos (17) ÿGP_INTEN_RHIEN1_Msk (0x1ul << GP_INTEN_RHIEN1_Pos) GP_INTEN_RHIEN2_Pos (18) GP_INTEN_RHIEN2_Msk (0x1ul << GP_INTEN_RHIEN2_Pos) GP_INTEN_RHIEN3_Pos (19)
GP_INTEN_RHIEN3_Msk (0x1ul << GP_INTEN_RHIEN3_Pos) GP_INTEN_RHIEN4_Pos (20) GP_INTEN_RHIEN4_Msk (0x1ul << GP_INTEN_RHIEN4_Pos) GP_INTEN_RHIEN5_Pos (21) GP_INTEN_RHIEN5_Msk (0x1ul << GP_INTEN_RHIEN5_Pos) GP_INTEN_RHIEN6_Pos (22) GP_INTEN_RHIEN6_Msk (0x1ul << GP_INTEN_RHIEN6_Pos) GP_INTEN_RHIEN7_Pos (23) GP_INTEN_RHIEN7_Msk (0x1ul << GP_INTEN_RHIEN7_Pos) GP_INTSRC_INTSRC0_Pos (0) GP_INTSRC_INTSRC0_Msk (0x1ul << GP_INTSRC_INTSRC0_Pos) GP_INTSRC_INTSRC1_Pos (1) GP_INTSRC_INTSRC1_Msk (0x1ul << GP_INTSRC_INTSRC1_Pos) GP_INTSRC_INTSRC2_Pos (2) GP_INTSRC_INTSRC2_Msk (0x1ul << GP_INTSRC_INTSRC2_Pos) GP_INTSRC_INTSRC3_Pos (3) GP_INTSRC_INTSRC3_Msk (0x1ul << GP_INTSRC_INTSRC3_Pos) GP_INTSRC_INTSRC4_Pos (4) GP_INTSRC_INTSRC4_Msk (0x1ul << GP_INTSRC_INTSRC4_Pos) ¢GP_INTSRC_INTSRC5_Pos (5) £GP_INTSRC_INTSRC5_Msk (0x1ul << GP_INTSRC_INTSRC5_Pos) ¥GP_INTSRC_INTSRC6_Pos (6) ¦GP_INTSRC_INTSRC6_Msk (0x1ul << GP_INTSRC_INTSRC6_Pos) ¨GP_INTSRC_INTSRC7_Pos (7) ©GP_INTSRC_INTSRC7_Msk (0x1ul << GP_INTSRC_INTSRC7_Pos) «GP_INTSRC_INTSRC8_Pos (8) ¬GP_INTSRC_INTSRC8_Msk (0x1ul << GP_INTSRC_INTSRC8_Pos) ®GP_INTSRC_INTSRC9_Pos (9) ¯GP_INTSRC_INTSRC9_Msk (0x1ul << GP_INTSRC_INTSRC9_Pos) ±GP_INTSRC_INTSRC10_Pos (10) ²GP_INTSRC_INTSRC10_Msk (0x1ul << GP_INTSRC_INTSRC10_Pos) ´GP_INTSRC_INTSRC11_Pos (11) µGP_INTSRC_INTSRC11_Msk (0x1ul << GP_INTSRC_INTSRC11_Pos) ·GP_INTSRC_INTSRC12_Pos (12) ¸GP_INTSRC_INTSRC12_Msk (0x1ul << GP_INTSRC_INTSRC12_Pos) ºGP_INTSRC_INTSRC13_Pos (13) »GP_INTSRC_INTSRC13_Msk (0x1ul << GP_INTSRC_INTSRC13_Pos) ½GP_INTSRC_INTSRC14_Pos (14) ¾GP_INTSRC_INTSRC14_Msk (0x1ul << GP_INTSRC_INTSRC14_Pos) ÀGP_INTSRC_INTSRC15_Pos (15) ÁGP_INTSRC_INTSRC15_Msk (0x1ul << GP_INTSRC_INTSRC15_Pos) ÃGP_DBCTL_DBCLKSEL_Pos (0) ÄGP_DBCTL_DBCLKSEL_Msk (0xful << GP_DBCTL_DBCLKSEL_Pos) ÆGP_DBCTL_DBCLKSRC_Pos (4) ÇGP_DBCTL_DBCLKSRC_Msk (0x1ul << GP_DBCTL_DBCLKSRC_Pos) ÉGP_DBCTL_ICLKON_Pos (5) ÊGP_DBCTL_ICLKON_Msk (0x1ul << GP_DBCTL_ICLKON_Pos) Ç ADC_DAT_RESULT_Pos (0) È ADC_DAT_RESULT_Msk (0xfffful << ADC_DAT_RESULT_Pos) É ADC_DAT_OV_Pos (16) Ê ADC_DAT_OV_Msk (0x1ul << ADC_DAT_OV_Pos) Ë ADC_DAT_VALID_Pos (17) Ì ADC_DAT_VALID_Msk (0x1ul << ADC_DAT_VALID_Pos) Î ADC_CTL_ADCEN_Pos (0) Ï ADC_CTL_ADCEN_Msk (0x1ul << ADC_CTL_ADCEN_Pos) Ð ADC_CTL_ADCIEN_Pos (1) Ñ ADC_CTL_ADCIEN_Msk (0x1ul << ADC_CTL_ADCIEN_Pos) Ò ADC_CTL_HWTRGSEL_Pos (4) Ó ADC_CTL_HWTRGSEL_Msk (0x3ul << ADC_CTL_HWTRGSEL_Pos) Ô ADC_CTL_HWTRGCOND_Pos (6) Õ ADC_CTL_HWTRGCOND_Msk (0x1ul << ADC_CTL_HWTRGCOND_Pos) Ö ADC_CTL_HWTRGEN_Pos (8) × ADC_CTL_HWTRGEN_Msk (0x1ul << ADC_CTL_HWTRGEN_Pos) Ø ADC_CTL_FIFO_EN_Pos (9) Ù ADC_CTL_FIFO_EN_Msk (0x1ul << ADC_CTL_FIFO_EN_Pos) Ú ADC_CTL_FIFO_THRE_STATE_Pos (10) Û ADC_CTL_FIFO_THRE_STATE_Msk (0x1ul << ADC_CTL_FIFO_THRE_STATE_Pos) Ü ADC_CTL_SWTRG_Pos (11) Ý ADC_CTL_SWTRG_Msk (0x1ul << ADC_CTL_SWTRG_Pos) Þ ADC_CTL_SWTRG_Pos (11) ß ADC_CTL_SWTRG_Msk (0x1ul << ADC_CTL_SWTRG_Pos) à ADC_CTL_SWTRG_Pos (11) á ADC_CTL_SWTRG_Msk (0x1ul << ADC_CTL_SWTRG_Pos) â ADC_CTL_LEFT_SHIFT_EN_Pos (12) ã ADC_CTL_LEFT_SHIFT_EN_Msk (0x1ul << ADC_CTL_LEFT_SHIFT_EN_Pos) ä ADC_CTL_SUB_BIAS_EN_Pos (13) å ADC_CTL_SUB_BIAS_EN_Msk (0x1ul << ADC_CTL_SUB_BIAS_EN_Pos) æ ADC_CTL_BIAS_VALUE_Pos (16) ç ADC_CTL_BIAS_VALUE_Msk (0xffful << ADC_CTL_BIAS_VALUE_Pos) ê ADC_CHEN_CHEN0_Pos (0) ë ADC_CHEN_CHEN0_Msk (0x1ul << ADC_CHEN_CHEN0_Pos) ì ADC_CHEN_CHEN1_Pos (1) í ADC_CHEN_CHEN1_Msk (0x1ul << ADC_CHEN_CHEN1_Pos) î ADC_CHEN_CHEN2_Pos (2) ï ADC_CHEN_CHEN2_Msk (0x1ul << ADC_CHEN_CHEN2_Pos) ð ADC_CHEN_CHEN3_Pos (3) ñ ADC_CHEN_CHEN3_Msk (0x1ul << ADC_CHEN_CHEN3_Pos) ò ADC_CHEN_CHEN4_Pos (4) ó ADC_CHEN_CHEN4_Msk (0x1ul << ADC_CHEN_CHEN4_Pos) ô ADC_CHEN_CHEN5_Pos (5) õ ADC_CHEN_CHEN5_Msk (0x1ul << ADC_CHEN_CHEN5_Pos) ö ADC_CHEN_CHEN6_Pos (6) ÷ ADC_CHEN_CHEN6_Msk (0x1ul << ADC_CHEN_CHEN6_Pos) ø ADC_CHEN_CHEN7_Pos (7) ù ADC_CHEN_CHEN7_Msk (0x1ul << ADC_CHEN_CHEN7_Pos) ú ADC_CHEN_CHEN8_VBG_Pos (8) û ADC_CHEN_CHEN8_VBG_Msk (0x1ul << ADC_CHEN_CHEN8_VBG_Pos) ü ADC_CHEN_CH9_TMP_Pos (9) ý ADC_CHEN_CH9_TMP_Msk (0x1ul << ADC_CHEN_CH9_TMP_Pos) þ ADC_CHEN_CH10_VDD_4_Pos (10) ÿ ADC_CHEN_CH10_VDD_4_Msk (0x1ul << ADC_CHEN_CH10_VDD_4_Pos) ADC_CHEN_CH11_VBG_2_Pos (11) ADC_CHEN_CH11_VBG_2_Msk (0x1ul << ADC_CHEN_CH11_VBG_2_Pos) ADC_CHEN_ALL_Msk (0xFFFul) ADC_CMP0_ADCMPEN_Pos (0)
ADC_CMP0_ADCMPEN_Msk (0x1ul << ADC_CMP0_ADCMPEN_Pos) ADC_CMP0_ADCMPIE_Pos (1) ADC_CMP0_ADCMPIE_Msk (0x1ul << ADC_CMP0_ADCMPIE_Pos) ADC_CMP0_CMPCOND_Pos (2) ADC_CMP0_CMPCOND_Msk (0x1ul << ADC_CMP0_CMPCOND_Pos) ADC_CMP0_CMPCH_Pos (3) ADC_CMP0_CMPCH_Msk (0x7ul << ADC_CMP0_CMPCH_Pos) ADC_CMP0_CMPMCNT_Pos (8) ADC_CMP0_CMPMCNT_Msk (0xful << ADC_CMP0_CMPMCNT_Pos) ADC_CMP0_CMPDAT_Pos (16) ADC_CMP0_CMPDAT_Msk (0xffful << ADC_CMP0_CMPDAT_Pos) ADC_CMP1_ADCMPEN_Pos (0) ADC_CMP1_ADCMPEN_Msk (0x1ul << ADC_CMP1_ADCMPEN_Pos) ADC_CMP1_ADCMPIE_Pos (1) ADC_CMP1_ADCMPIE_Msk (0x1ul << ADC_CMP1_ADCMPIE_Pos) ADC_CMP1_CMPCOND_Pos (2) ADC_CMP1_CMPCOND_Msk (0x1ul << ADC_CMP1_CMPCOND_Pos) ADC_CMP1_CMPCH_Pos (3) ADC_CMP1_CMPCH_Msk (0x7ul << ADC_CMP1_CMPCH_Pos) ADC_CMP1_CMPMCNT_Pos (8) ADC_CMP1_CMPMCNT_Msk (0xful << ADC_CMP1_CMPMCNT_Pos) ADC_CMP1_CMPDAT_Pos (16) ADC_CMP1_CMPDAT_Msk (0xffful << ADC_CMP1_CMPDAT_Pos) ADC_STATUS_ADIF_Pos (0) ADC_STATUS_ADIF_Msk (0x1ul << ADC_STATUS_ADIF_Pos) ADC_STATUS_ADCMPIF0_Pos (1) ¡ ADC_STATUS_ADCMPIF0_Msk (0x1ul << ADC_STATUS_ADCMPIF0_Pos) ¢ ADC_STATUS_ADCMPIF1_Pos (2) £ ADC_STATUS_ADCMPIF1_Msk (0x1ul << ADC_STATUS_ADCMPIF1_Pos) ¤ ADC_STATUS_BUSY_Pos (3) ¥ ADC_STATUS_BUSY_Msk (0x1ul << ADC_STATUS_BUSY_Pos) ¦ ADC_STATUS_CHANNEL_Pos (4) § ADC_STATUS_CHANNEL_Msk (0x7ul << ADC_STATUS_CHANNEL_Pos) ¨ ADC_STATUS_VALID_Pos (8) © ADC_STATUS_VALID_Msk (0x1ul << ADC_STATUS_VALID_Pos) ª ADC_STATUS_INTMSK_FULL_Pos (9) « ADC_STATUS_INTMSK_FULL_Msk (0x1ul << ADC_STATUS_INTMSK_FULL_Pos) ¬ ADC_STATUS_INTMSK_EMPTY_Pos (10) ADC_STATUS_INTMSK_EMPTY_Msk (0x1ul << ADC_STATUS_INTMSK_EMPTY_Pos) ® ADC_STATUS_INTMSK_OVER_Pos (11) ¯ ADC_STATUS_INTMSK_OVER_Msk (0x1ul << ADC_STATUS_INTMSK_OVER_Pos) ° ADC_STATUS_INTMSK_HALF_Pos (12) ± ADC_STATUS_INTMSK_HALF_Msk (0x1ul << ADC_STATUS_INTMSK_HALF_Pos) ² ADC_STATUS_INTMSK_AD_Pos (13) ³ ADC_STATUS_INTMSK_AD_Msk (0x1ul << ADC_STATUS_INTMSK_AD_Pos) ´ ADC_STATUS_INTMSK_CMP0_Pos (14) µ ADC_STATUS_INTMSK_CMP0_Msk (0x1ul << ADC_STATUS_INTMSK_CMP0_Pos) ¶ ADC_STATUS_INTMSK_CMP1_Pos (15) · ADC_STATUS_INTMSK_CMP1_Msk (0x1ul << ADC_STATUS_INTMSK_CMP1_Pos) ¸ ADC_STATUS_OV_Pos (16) ¹ ADC_STATUS_OV_Msk (0x1ul << ADC_STATUS_OV_Pos) º ADC_STATUS_ONE_CH_CLR_SEL_Pos (17) » ADC_STATUS_ONE_CH_CLR_SEL_Msk (0x1ul << ADC_STATUS_ONE_CH_CLR_SEL_Pos) ¼ ADC_STATUS_ONE_CH_FLAG_Pos (18) ½ ADC_STATUS_ONE_CH_FLAG_Msk (0x1ul << ADC_STATUS_ONE_CH_FLAG_Pos) ¾ ADC_STATUS_INTFLG_FULL_Pos (19) ¿ ADC_STATUS_INTFLG_FULL_Msk (0x1ul << ADC_STATUS_INTFLG_FULL_Pos) À ADC_STATUS_INTFLG_EMPTY_Pos (20) Á ADC_STATUS_INTFLG_EMPTY_Msk (0x1ul << ADC_STATUS_INTFLG_EMPTY_Pos) Â ADC_STATUS_INTFLG_OVER_Pos (21) Ã ADC_STATUS_INTFLG_OVER_Msk (0x1ul << ADC_STATUS_INTFLG_OVER_Pos) Ä ADC_STATUS_INTFLG_HALF_Pos (22) Å ADC_STATUS_INTFLG_HALF_Msk (0x1ul << ADC_STATUS_INTFLG_HALF_Pos) Æ ADC_STATUS_ADCF_Pos (24) Ç ADC_STATUS_ADCF_Msk (0x1ul << ADC_STATUS_ADCF_Pos) È ADC_STATUS_ADCMPF0_Pos (25) É ADC_STATUS_ADCMPF0_Msk (0x1ul << ADC_STATUS_ADCMPF0_Pos) Ê ADC_STATUS_ADCMPF1_Pos (26) Ë ADC_STATUS_ADCMPF1_Msk (0x1ul << ADC_STATUS_ADCMPF1_Pos) Ì ADC_STATUS_FLAG_FULL_Pos (27) Í ADC_STATUS_FLAG_FULL_Msk (0x1ul << ADC_STATUS_FLAG_FULL_Pos) Î ADC_STATUS_FLAG_EMPTY_Pos (28) Ï ADC_STATUS_FLAG_EMPTY_Msk (0x1ul << ADC_STATUS_FLAG_EMPTY_Pos) Ð ADC_STATUS_FLAG_OVER_Pos (29) Ñ ADC_STATUS_FLAG_OVER_Msk (0x1ul << ADC_STATUS_FLAG_OVER_Pos) Ò ADC_STATUS_FLAG_HALF_Pos (30) Ó ADC_STATUS_FLAG_HALF_Msk (0x1ul << ADC_STATUS_FLAG_HALF_Pos) Õ ADC_TRGDLY_DELAY_Pos (0) Ö ADC_TRGDLY_DELAY_Msk (0xfful << ADC_TRGDLY_DELAY_Pos) Ø ADC_EXTSMPT_EXTSMPT_Pos (0) Ù ADC_EXTSMPT_EXTSMPT_Msk (0x3fful << ADC_EXTSMPT_EXTSMPT_Pos) Û ADC_SEQCTL_SEQEN_Pos (0) Ü ADC_SEQCTL_SEQEN_Msk (0x1ul << ADC_SEQCTL_SEQEN_Pos) Ý ADC_SEQCTL_SEQTYPE_Pos (1) Þ ADC_SEQCTL_SEQTYPE_Msk (0x1ul << ADC_SEQCTL_SEQTYPE_Pos) ß ADC_SEQCTL_MODESEL_Pos (2) à ADC_SEQCTL_MODESEL_Msk (0x3ul << ADC_SEQCTL_MODESEL_Pos) á ADC_SEQCTL_DELAY_EN_Pos (4) â ADC_SEQCTL_DELAY_EN_Msk (0x1ul << ADC_SEQCTL_DELAY_EN_Pos) ã ADC_SEQCTL_TRG_SEL_Pos (5) ä ADC_SEQCTL_TRG_SEL_Msk (0x1ul << ADC_SEQCTL_TRG_SEL_Pos) å ADC_SEQCTL_ONE_CH_EN_Pos (6) æ ADC_SEQCTL_ONE_CH_EN_Msk (0x1ul << ADC_SEQCTL_ONE_CH_EN_Pos) ç ADC_SEQCTL_TRG1CTL_Pos (8) è ADC_SEQCTL_TRG1CTL_Msk (0xful << ADC_SEQCTL_TRG1CTL_Pos) é ADC_SEQCTL_TRG2CTL_Pos (16) ê ADC_SEQCTL_TRG2CTL_Msk (0xful << ADC_SEQCTL_TRG2CTL_Pos) ì ADC_SEQDAT1_RESULT_Pos (0) í ADC_SEQDAT1_RESULT_Msk (0x3fful << ADC_SEQDAT1_RESULT_Pos) î ADC_SEQDAT1_OV_Pos (16) ï ADC_SEQDAT1_OV_Msk (0x1ul << ADC_SEQDAT1_OV_Pos) ð ADC_SEQDAT1_VALID_Pos (17) ñ ADC_SEQDAT1_VALID_Msk (0x1ul << ADC_SEQDAT1_VALID_Pos) ó ADC_SEQDAT2_RESULT_Pos (0) ô ADC_SEQDAT2_RESULT_Msk (0x3fful << ADC_SEQDAT2_RESULT_Pos) õ ADC_SEQDAT2_OV_Pos (16) ö ADC_SEQDAT2_OV_Msk (0x1ul << ADC_SEQDAT2_OV_Pos) ÷ ADC_SEQDAT2_VALID_Pos (17) ø ADC_SEQDAT2_VALID_Msk (0x1ul << ADC_SEQDAT2_VALID_Pos) ú ADC_CTL2_TESTMODE_Pos (0) û ADC_CTL2_TESTMODE_Msk (0x1ul << ADC_CTL2_TESTMODE_Pos) ü ADC_CTL2_SHSEL_Pos (1) ý ADC_CTL2_SHSEL_Msk (0x1ul << ADC_CTL2_SHSEL_Pos) þ ADC_CTL2_DMA_EN_Pos (2) ÿ ADC_CTL2_DMA_EN_Msk (0x1ul << ADC_CTL2_DMA_EN_Pos) ADC_CTL2_CLKDIV_Pos (8) ADC_CTL2_CLKDIV_Msk (0x7ul << ADC_CTL2_CLKDIV_Pos) ADC_SEL_VREF_Pos (17) ADC_SEL_VREF_Msk (0x1ul << ADC_SEL_VREF_Pos) ADC_CTL2_CMPCTL_Pos (24)
ADC_CTL2_CMPCTL_Msk (0x3ul << ADC_CTL2_CMPCTL_Pos) ADC_CTL2_DRVCTL_Pos (26) ADC_CTL2_DRVCTL_Msk (0x3ul << ADC_CTL2_DRVCTL_Pos) « SYS_P0_MFP_MFP_Pos (0) ¬ SYS_P0_MFP_MFP_Msk (0xfful << SYS_P0_MFP_MFP_Pos) ® SYS_P0_MFP_ALT0_Pos (8) ¯ SYS_P0_MFP_ALT0_Msk (0x1ul << SYS_P0_MFP_ALT0_Pos) ± SYS_P0_MFP_ALT1_Pos (9) ² SYS_P0_MFP_ALT1_Msk (0x1ul << SYS_P0_MFP_ALT1_Pos) ´ SYS_P0_MFP_ALT2_Pos (10) µ SYS_P0_MFP_ALT2_Msk (0x1ul << SYS_P0_MFP_ALT2_Pos) · SYS_P0_MFP_ALT3_Pos (11) ¸ SYS_P0_MFP_ALT3_Msk (0x1ul << SYS_P0_MFP_ALT3_Pos) º SYS_P0_MFP_ALT4_Pos (12) » SYS_P0_MFP_ALT4_Msk (0x1ul << SYS_P0_MFP_ALT4_Pos) ½ SYS_P0_MFP_ALT5_Pos (13) ¾ SYS_P0_MFP_ALT5_Msk (0x1ul << SYS_P0_MFP_ALT5_Pos) À SYS_P0_MFP_ALT6_Pos (14) Á SYS_P0_MFP_ALT6_Msk (0x1ul << SYS_P0_MFP_ALT6_Pos) Ã SYS_P0_MFP_ALT7_Pos (15) Ä SYS_P0_MFP_ALT7_Msk (0x1ul << SYS_P0_MFP_ALT7_Pos) Æ SYS_P1_MFP_MFP_Pos (0) Ç SYS_P1_MFP_MFP_Msk (0xfful << SYS_P1_MFP_MFP_Pos) É SYS_P1_MFP_ALT0_Pos (8) Ê SYS_P1_MFP_ALT0_Msk (0x1ul << SYS_P1_MFP_ALT0_Pos) Ì SYS_P1_MFP_ALT1_Pos (9) Í SYS_P1_MFP_ALT1_Msk (0x1ul << SYS_P1_MFP_ALT1_Pos) Ï SYS_P1_MFP_ALT2_Pos (10) Ð SYS_P1_MFP_ALT2_Msk (0x1ul << SYS_P1_MFP_ALT2_Pos) Ò SYS_P1_MFP_ALT3_Pos (11) Ó SYS_P1_MFP_ALT3_Msk (0x1ul << SYS_P1_MFP_ALT3_Pos) Õ SYS_P1_MFP_ALT4_Pos (12) Ö SYS_P1_MFP_ALT4_Msk (0x1ul << SYS_P1_MFP_ALT4_Pos) Ø SYS_P1_MFP_ALT5_Pos (13) Ù SYS_P1_MFP_ALT5_Msk (0x1ul << SYS_P1_MFP_ALT5_Pos) Û SYS_P1_MFP_ALT6_Pos (14) Ü SYS_P1_MFP_ALT6_Msk (0x1ul << SYS_P1_MFP_ALT6_Pos) Þ SYS_P1_MFP_ALT7_Pos (15) ß SYS_P1_MFP_ALT7_Msk (0x1ul << SYS_P1_MFP_ALT7_Pos) á SYS_P1_MFP_TYPE_Pos (16) â SYS_P1_MFP_TYPE_Msk (0xfful << SYS_P1_MFP_TYPE_Pos) ä SYS_P1_MFP_P12EXT_Pos (26) å SYS_P1_MFP_P12EXT_Msk (0x1ul << SYS_P1_MFP_P12EXT_Pos) ç SYS_P1_MFP_P13EXT_Pos (27) è SYS_P1_MFP_P13EXT_Msk (0x1ul << SYS_P1_MFP_P13EXT_Pos) ê SYS_P1_MFP_P14EXT_Pos (28) ë SYS_P1_MFP_P14EXT_Msk (0x1ul << SYS_P1_MFP_P14EXT_Pos) î SYS_P2_MFP_ALT0_Pos (8) ï SYS_P2_MFP_ALT0_Msk (0x1ul << SYS_P2_MFP_ALT0_Pos) ñ SYS_P2_MFP_ALT1_Pos (9) ò SYS_P2_MFP_ALT1_Msk (0x1ul << SYS_P2_MFP_ALT1_Pos) õ SYS_P2_MFP_ALT2_Pos (10) ö SYS_P2_MFP_ALT2_Msk (0x1ul << SYS_P2_MFP_ALT2_Pos) ø SYS_P2_MFP_ALT3_Pos (11) ù SYS_P2_MFP_ALT3_Msk (0x1ul << SYS_P2_MFP_ALT3_Pos) û SYS_P2_MFP_ALT4_Pos (12) ü SYS_P2_MFP_ALT4_Msk (0x1ul << SYS_P2_MFP_ALT4_Pos) þ SYS_P2_MFP_ALT5_Pos (13) ÿ SYS_P2_MFP_ALT5_Msk (0x1ul << SYS_P2_MFP_ALT5_Pos) SYS_P2_MFP_ALT6_Pos (14) SYS_P2_MFP_ALT6_Msk (0x1ul << SYS_P2_MFP_ALT6_Pos)
SYS_P2_MFP_ALT7_Pos (15) SYS_P2_MFP_ALT7_Msk (0x1ul << SYS_P2_MFP_ALT7_Pos) SYS_P3_MFP_MFP_Pos (0) SYS_P3_MFP_MFP_Msk (0xfful << SYS_P3_MFP_MFP_Pos) SYS_P3_MFP_ALT0_Pos (8) SYS_P3_MFP_ALT0_Msk (0x1ul << SYS_P3_MFP_ALT0_Pos) SYS_P3_MFP_ALT1_Pos (9) SYS_P3_MFP_ALT1_Msk (0x1ul << SYS_P3_MFP_ALT1_Pos) SYS_P3_MFP_ALT2_Pos (10) SYS_P3_MFP_ALT2_Msk (0x1ul << SYS_P3_MFP_ALT2_Pos) SYS_P3_MFP_ALT4_Pos (12) SYS_P3_MFP_ALT4_Msk (0x1ul << SYS_P3_MFP_ALT4_Pos) SYS_P3_MFP_ALT5_Pos (13) SYS_P3_MFP_ALT5_Msk (0x1ul << SYS_P3_MFP_ALT5_Pos) SYS_P3_MFP_ALT6_Pos (14) SYS_P3_MFP_ALT6_Msk (0x1ul << SYS_P3_MFP_ALT6_Pos) SYS_P3_MFP_P32EXT_Pos (26) SYS_P3_MFP_P32EXT_Msk (0x1ul << SYS_P3_MFP_P32EXT_Pos) ¡ SYS_P4_MFP_MFP_Pos (0) ¢ SYS_P4_MFP_MFP_Msk (0xfful << SYS_P4_MFP_MFP_Pos) ¤ SYS_P4_MFP_ALT6_Pos (14) ¥ SYS_P4_MFP_ALT6_Msk (0x1ul << SYS_P4_MFP_ALT6_Pos) § SYS_P4_MFP_ALT7_Pos (15) ¨ SYS_P4_MFP_ALT7_Msk (0x1ul << SYS_P4_MFP_ALT7_Pos) ª SYS_P5_MFP_MFP_Pos (0) « SYS_P5_MFP_MFP_Msk (0xfful << SYS_P5_MFP_MFP_Pos) SYS_P5_MFP_ALT0_Pos (8) ® SYS_P5_MFP_ALT0_Msk (0x1ul << SYS_P5_MFP_ALT0_Pos) ° SYS_P5_MFP_ALT1_Pos (9) ± SYS_P5_MFP_ALT1_Msk (0x1ul << SYS_P5_MFP_ALT1_Pos) ³ SYS_P5_MFP_ALT2_Pos (10) ´ SYS_P5_MFP_ALT2_Msk (0x1ul << SYS_P5_MFP_ALT2_Pos) ¶ SYS_P5_MFP_ALT3_Pos (11) · SYS_P5_MFP_ALT3_Msk (0x1ul << SYS_P5_MFP_ALT3_Pos) ¹ SYS_P5_MFP_ALT4_Pos (12) º SYS_P5_MFP_ALT4_Msk (0x1ul << SYS_P5_MFP_ALT4_Pos) ¼ SYS_P5_MFP_ALT5_Pos (13) ½ SYS_P5_MFP_ALT5_Msk (0x1ul << SYS_P5_MFP_ALT5_Pos) ¿ SYS_P5_MFP_ALT6_Pos (14) À SYS_P5_MFP_ALT6_Msk (0x1ul << SYS_P5_MFP_ALT5_Pos) Â SYS_P5_MFP_ALT7_Pos (15) Ã SYS_P5_MFP_ALT7_Msk (0x1ul << SYS_P5_MFP_ALT5_Pos) Å SYS_P5_MFP_P50EXT_Pos (24) Æ SYS_P5_MFP_P50EXT_Msk (0x1ul << SYS_P5_MFP_P50EXT_Pos) È SYS_P5_MFP_P51EXT_Pos (25) É SYS_P5_MFP_P51EXT_Msk (0x1ul << SYS_P5_MFP_P51EXT_Pos) Ë SYS_REGLCTL_REGLCTL_Pos (0) Ì SYS_REGLCTL_REGLCTL_Msk (0xfful << SYS_REGLCTL_REGLCTL_Pos) õ CLK_RSTSTS_CHIPRF_Pos (0) ö CLK_RSTSTS_CHIPRF_Msk (0x1ul << CLK_RSTSTS_CHIPRF_Pos) ÷ CLK_RSTSTS_PINRF_Pos (1) ø CLK_RSTSTS_PINRF_Msk (0x1ul << CLK_RSTSTS_PINRF_Pos) ù CLK_RSTSTS_WDTRF_Pos (2) ú CLK_RSTSTS_WDTRF_Msk (0x1ul << CLK_RSTSTS_WDTRF_Pos) û CLK_RSTSTS_LVRRF_Pos (3) ü CLK_RSTSTS_LVRRF_Msk (0x1ul << CLK_RSTSTS_LVRRF_Pos) ý CLK_RSTSTS_BODRF_Pos (4) þ CLK_RSTSTS_BODRF_Msk (0x1ul << CLK_RSTSTS_BODRF_Pos) ÿ CLK_RSTSTS_SYSRF_Pos (5) !CLK_RSTSTS_SYSRF_Msk (0x1ul << CLK_RSTSTS_SYSRF_Pos) !CLK_RSTSTS_PORRF_Pos (6) !CLK_RSTSTS_PORRF_Msk (0x1ul << CLK_RSTSTS_PORRF_Pos) !CLK_RSTSTS_CPURF_Pos (7) !CLK_RSTSTS_CPURF_Msk (0x1ul << CLK_RSTSTS_CPURF_Pos) !CLK_IPRST0_CHIPRST_Pos (0) !CLK_IPRST0_CHIPRST_Msk (0x1ul << CLK_IPRST0_CHIPRST_Pos) !CLK_IPRST0_CPURST_Pos (1) !CLK_IPRST0_CPURST_Msk (0x1ul << CLK_IPRST0_CPURST_Pos) !CLK_IPRST0_DMARST_Pos (2) !CLK_IPRST0_DMARST_Msk (0x1ul << CLK_IPRST0_DMARST_Pos) !CLK_IPRST0_RFRST_Pos (3) !CLK_IPRST0_RFRST_Msk (0x1ul << CLK_IPRST0_RFRST_Pos) !CLK_IPRST0_EFUSERST_Pos (4) !CLK_IPRST0_EFUSERST_Msk (0x1ul << CLK_IPRST0_EFUSERST_Pos) !CLK_IPRST0_USBRST_Pos (6) !CLK_IPRST0_USBRST_Msk (0x1ul << CLK_IPRST0_USBRST_Pos) !CLK_IPRST0_MDMSTDBYRST_Pos (7) !CLK_IPRST0_MDMSTDBYRST_Msk (0x1ul << CLK_IPRST0_MDMSTDBYRST_Pos) !CLK_IPRST0_MDMRST_Pos (8) !CLK_IPRST0_MDMRST_Msk (0x1ul << CLK_IPRST0_MDMRST_Pos) !CLK_IPRST0_CHIPSCOPEEN_Pos (9) !CLK_IPRST0_CHIPSCOPEEN_Msk (0x1ul << CLK_IPRST0_CHIPSCOPEEN_Pos) !CLK_IPRST0_FTORRST_Pos (10) !CLK_IPRST0_FTORRST_Msk (0x1ul << CLK_IPRST0_FTORRST_Pos) !CLK_IPRST1_I2C0RST_Pos (0) !CLK_IPRST1_I2C0RST_Msk (0x1ul << CLK_IPRST1_I2C0RST_Pos) !CLK_IPRST1_SPI0RST_Pos (2) !CLK_IPRST1_SPI0RST_Msk (0x1ul << CLK_IPRST1_SPI0RST_Pos) ¡!CLK_IPRST1_SPI1RST_Pos (3) ¢!CLK_IPRST1_SPI1RST_Msk (0x1ul << CLK_IPRST1_SPI1RST_Pos) £!CLK_IPRST1_UART0RST_Pos (6) ¤!CLK_IPRST1_UART0RST_Msk (0x1ul << CLK_IPRST1_UART0RST_Pos) ¥!CLK_IPRST1_UART1RST_Pos (7) ¦!CLK_IPRST1_UART1RST_Msk (0x1ul << CLK_IPRST1_UART1RST_Pos) §!CLK_IPRST1_PWM0RST_Pos (8) ¨!CLK_IPRST1_PWM0RST_Msk (0x1ul << CLK_IPRST1_PWM0RST_Pos) ©!CLK_IPRST1_ADCRST_Pos (9) ª!CLK_IPRST1_ADCRST_Msk (0x1ul << CLK_IPRST1_ADCRST_Pos) «!CLK_IPRST1_WDTRST_Pos (10) ¬!CLK_IPRST1_WDTRST_Msk (0x1ul << CLK_IPRST1_WDTRST_Pos) !CLK_IPRST1_WWDTRST_Pos (11) ®!CLK_IPRST1_WWDTRST_Msk (0x1ul << CLK_IPRST1_WWDTRST_Pos) ¯!CLK_IPRST1_TMR0RST_Pos (12) °!CLK_IPRST1_TMR0RST_Msk (0x1ul << CLK_IPRST1_TMR0RST_Pos) ±!CLK_IPRST1_TMR1RST_Pos (13) ²!CLK_IPRST1_TMR1RST_Msk (0x1ul << CLK_IPRST1_TMR1RST_Pos) ³!CLK_IPRST1_TMR2RST_Pos (14) ´!CLK_IPRST1_TMR2RST_Msk (0x1ul << CLK_IPRST1_TMR2RST_Pos) µ!CLK_IPRST1_GPIORST_Pos (15) ¶!CLK_IPRST1_GPIORST_Msk (0x1ul << CLK_IPRST1_GPIORST_Pos) ·!CLK_IPRST1_TRIMRST_Pos (16) ¸!CLK_IPRST1_TRIMRST_Msk (0x1ul << CLK_IPRST1_TRIMRST_Pos) »!CLK_BODCTL_BODRSTEN_Pos_3v (3) ¼!CLK_BODCTL_BODRSTEN_Msk_3v (0x1ul << CLK_BODCTL_BODRSTEN_Pos_3v) ½!CLK_BODCTL_BODIF_Pos (4) ¾!CLK_BODCTL_BODIF_Msk (0x1ul << CLK_BODCTL_BODIF_Pos) ¿!CLK_BODCTL_BODOUT_Pos (6) À!CLK_BODCTL_BODOUT_Msk (0x1ul << CLK_BODCTL_BODOUT_Pos) Á!CLK_BODCTL_LVREN_Pos_3v (16) Â!CLK_BODCTL_LVREN_Msk_3v (0x1ul << CLK_BODCTL_LVREN_Pos_3v) Ã!CLK_BODCTL_BODEN_Pos_3v (17) Ä!CLK_BODCTL_BODEN_Msk_3v (0x1ul << CLK_BODCTL_BODEN_Pos_3v) Å!CLK_BODCTL_BODSEL_Pos_3v (18) Æ!CLK_BODCTL_BODSEL_Msk_3v (0x7ul << CLK_BODCTL_BODSEL_Pos_3v) Ç!CLK_BODCTL_LVR_TEST_Pos_3v (21) È!CLK_BODCTL_LVR_TEST_Msk_3v (0x1ul << CLK_BODCTL_LVR_TEST_Pos_3v) É!CLK_BODCTL_BOD_TEST_Pos_3v (22) Ê!CLK_BODCTL_BOD_TEST_Msk_3v (0x1ul << CLK_BODCTL_BOD_TEST_Pos_3v) Í!CLK_BLDBCTL_LVRDB_SEL_Pos_3v (8) Î!CLK_BLDBCTL_LVRDB_SEL_Msk_3v (0x3Ful << CLK_BLDBCTL_LVRDB_SEL_Pos_3v) Ï!CLK_BLDBCTL_BODDB_SEL_Pos_3v (0) Ð!CLK_BLDBCTL_BODDB_SEL_Msk_3v (0x3Ful << CLK_BLDBCTL_BODDB_SEL_Pos_3v) Ó!CLK_TOPCTL_RSICV_SYSCNT_EN_Pos (0) Ô!CLK_TOPCTL_RSICV_SYSCNT_EN_Msk (0x1ul << CLK_TOPCTL_RSICV_SYSCNT_EN_Pos) Õ!CLK_TOPCTL_SYS_CLK_SEL_Pos (8) Ö!CLK_TOPCTL_SYS_CLK_SEL_Msk (0x3ul << CLK_TOPCTL_SYS_CLK_SEL_Pos) ×!CLK_TOPCTL_32K_CLK_SEL_Pos_3v (10) Ø!CLK_TOPCTL_32K_CLK_SEL_Msk_3v (0x1ul << CLK_TOPCTL_32K_CLK_SEL_Pos_3v) Ù!CLK_TOPCTL_AHB_DIV_Pos (12) Ú!CLK_TOPCTL_AHB_DIV_Msk (0xFul << CLK_TOPCTL_AHB_DIV_Pos) Û!CLK_TOPCTL_APB1_DIV_Pos (16) Ü!CLK_TOPCTL_APB1_DIV_Msk (0xFul << CLK_TOPCTL_APB1_DIV_Pos) Ý!CLK_TOPCTL_APB2_DIV_Pos (20) Þ!CLK_TOPCTL_APB2_DIV_Msk (0xFul << CLK_TOPCTL_APB2_DIV_Pos) á!CLK_RCLCTL_RC32K_EN_Pos_3v (0) â!CLK_RCLCTL_RC32K_EN_Msk_3v (0x1ul << CLK_RCLCTL_RC32K_EN_Pos_3v) ã!CLK_RCLCTL_RC32K_TST_EN_Pos (1) ä!CLK_RCLCTL_RC32K_TST_EN_Msk (0x1ul << CLK_RCLCTL_RC32K_TST_EN_Pos) å!CLK_RCLCTL_CLK_SEL_Pos_3v (2) æ!CLK_RCLCTL_CLK_SEL_Msk_3v (0x1ul << CLK_RCLCTL_CLK_SEL_Pos_3v) ç!CLK_RCLCTL_RC32K_COARSE_Pos_3v (4) è!CLK_RCLCTL_RC32K_COARSE_Msk_3v (0xFul << CLK_RCLCTL_RC32K_COARSE_Pos_3v) é!CLK_RCLCTL_RC32K_FINE_Pos_3v (8) ê!CLK_RCLCTL_RC32K_FINE_Msk_3v (0xFFul << CLK_RCLCTL_RC32K_FINE_Pos_3v) ë!CLK_RCLCTL_RC32K_DELAY_Pos_3v (16) ì!CLK_RCLCTL_RC32K_DELAY_Msk_3v (0x3ul << CLK_RCLCTL_RC32K_DELAY_Pos_3v) í!CLK_RCLCTL_STABLE_Pos (24) î!CLK_RCLCTL_STABLE_Msk (0x1ul << CLK_RCLCTL_STABLE_Pos) ñ!CLK_RCHCTL_RCH_EN_Pos (0) ò!CLK_RCHCTL_RCH_EN_Msk (0x1ul << CLK_RCHCTL_RCH_EN_Pos) ó!CLK_RCHCTL_RCH_TST_EN_Pos (1) ô!CLK_RCHCTL_RCH_TST_EN_Msk (0x1ul << CLK_RCHCTL_RCH_TST_EN_Pos) õ!CLK_RCHCTL_CLK_SEL_Pos (2) ö!CLK_RCHCTL_CLK_SEL_Msk (0x1ul << CLK_RCHCTL_CLK_SEL_Pos) ÷!CLK_RCHCTL_BIAS_Pos (4) ø!CLK_RCHCTL_BIAS_Msk (0x3ul << CLK_RCHCTL_BIAS_Pos) ù!CLK_RCHCTL_RCH_FREQ_Pos (8) ú!CLK_RCHCTL_RCH_FREQ_Msk (0xFFul << CLK_RCHCTL_RCH_FREQ_Pos) û!CLK_RCHCTL_DELAY_Pos (16) ü!CLK_RCHCTL_DELAY_Msk (0x3ul << CLK_RCHCTL_DELAY_Pos) ý!CLK_RCHCTL_STABLE_Pos (24) þ!CLK_RCHCTL_STABLE_Msk (0x1ul << CLK_RCHCTL_STABLE_Pos) "CLK_XTLCTL_XTL_EN_Pos_3v (0) "CLK_XTLCTL_XTL_EN_Msk_3v (0x1ul << CLK_XTLCTL_XTL_EN_Pos_3v) "CLK_XTLCTL_XTL_TST_EN_Pos (1) "CLK_XTLCTL_XTL_TST_EN_Msk (0x1ul << CLK_XTLCTL_XTL_TST_EN_Pos)
"CLK_XTLCTL_CORE_BIAS_Pos_3v (4) "CLK_XTLCTL_CORE_BIAS_Msk_3v (0x7ul << CLK_XTLCTL_CORE_BIAS_Pos_3v) "CLK_XTLCTL_XTL_TRIM_Pos_3v (7) "CLK_XTLCTL_XTL_TRIM_Msk_3v (0x3Ful << CLK_XTLCTL_XTL_TRIM_Pos_3v) "CLK_XTLCTL_XTL_CAP_EN_Pos_3v (13) "CLK_XTLCTL_XTL_CAP_EN_Msk_3v (0x1ul << CLK_XTLCTL_XTL_CAP_EN_Pos_3v) "CLK_XTLCTL_DELAY_Pos_3v (16) "CLK_XTLCTL_DELAY_Msk_3v (0x3ul << CLK_XTLCTL_DELAY_Pos_3v) "CLK_XTLCTL_STABLE_Pos (24) "CLK_XTLCTL_STABLE_Msk (0x1ul << CLK_XTLCTL_STABLE_Pos) "CLK_XTHCTL_XTH_EN_Pos (0) "CLK_XTHCTL_XTH_EN_Msk (0x1ul << CLK_XTHCTL_XTH_EN_Pos) "CLK_XTHCTL_XTH_TST_EN_Pos (1) "CLK_XTHCTL_XTH_TST_EN_Msk (0x1ul << CLK_XTHCTL_XTH_TST_EN_Pos) "CLK_XTHCTL_START_FAST_Pos (2) "CLK_XTHCTL_START_FAST_Msk (0x1ul << CLK_XTHCTL_START_FAST_Pos) "CLK_XTHCTL_DEGLITCH_EN_Pos (3) "CLK_XTHCTL_DEGLITCH_EN_Msk (0x1ul << CLK_XTHCTL_DEGLITCH_EN_Pos) "CLK_XTHCTL_XO_CAP_SEL_Pos (4) "CLK_XTHCTL_XO_CAP_SEL_Msk (0x3ful << CLK_XTHCTL_XO_CAP_SEL_Pos) "CLK_XTHCTL_DELAY_Pos (16) "CLK_XTHCTL_DELAY_Msk (0x1ul << CLK_XTHCTL_DELAY_Pos) "CLK_XTHCTL_STABLE_Pos (24) "CLK_XTHCTL_STABLE_Msk (0x1ul << CLK_XTHCTL_STABLE_Pos) ¡"CLK_DPLLCTL_DPLL_EN_Pos (0) ¢"CLK_DPLLCTL_DPLL_EN_Msk (0x1ul << CLK_DPLLCTL_DPLL_EN_Pos) £"CLK_DPLLCTL_DPLL_TST_EN_Pos (1) ¤"CLK_DPLLCTL_DPLL_TST_EN_Msk (0x1ul << CLK_DPLLCTL_DPLL_TST_EN_Pos) ¥"CLK_DPLLCTL_FREQ_OUT_Pos (2) ¦"CLK_DPLLCTL_FREQ_OUT_Msk (0x1ul << CLK_DPLLCTL_FREQ_OUT_Pos) §"CLK_DPLLCTL_RCLK_SEL_Pos (3) ¨"CLK_DPLLCTL_RCLK_SEL_Msk (0x1ul << CLK_DPLLCTL_RCLK_SEL_Pos) ©"CLK_DPLLCTL_ICP_BIAS_Pos (4) ª"CLK_DPLLCTL_ICP_BIAS_Msk (0x3ul << CLK_DPLLCTL_ICP_BIAS_Pos) «"CLK_DPLLCTL_ICP_CTRL_Pos (6) ¬"CLK_DPLLCTL_ICP_CTRL_Msk (0x3ul << CLK_DPLLCTL_ICP_CTRL_Pos) "CLK_DPLLCTL_KVCO_CTRL_Pos (8) ®"CLK_DPLLCTL_KVCO_CTRL_Msk (0x7ul << CLK_DPLLCTL_KVCO_CTRL_Pos) ¯"CLK_DPLLCTL_VCO_FREQ_TRIM_Pos (11) °"CLK_DPLLCTL_VCO_FREQ_TRIM_Msk (0x3ul << CLK_DPLLCTL_VCO_FREQ_TRIM_Pos) ±"CLK_DPLLCTL_DIV_SEL_Pos (13) ²"CLK_DPLLCTL_DIV_SEL_Msk (0x1ul << CLK_DPLLCTL_DIV_SEL_Pos) ³"CLK_DPLLCTL_DELAY_Pos (16) ´"CLK_DPLLCTL_DELAY_Msk (0x3ul << CLK_DPLLCTL_STARTUP_Pos) µ"CLK_DPLLCTL_STABLE_Pos (24) ¶"CLK_DPLLCTL_STABLE_Msk (0x1ul << CLK_DPLLCTL_STABLE_Pos) ¹"CLK_AHBCLK_DMAEN_Pos (0) º"CLK_AHBCLK_DMAEN_Msk (0x1ul << CLK_AHBCLK_DMAEN_Pos) »"CLK_AHBCLK_GPIOEN_Pos (1) ¼"CLK_AHBCLK_GPIOEN_Msk (0x1ul << CLK_AHBCLK_GPIOEN_Pos) ½"CLK_AHBCLK_SYSTICK_EN_Pos (2) ¾"CLK_AHBCLK_SYSTICK_EN_Msk (0x1ul << CLK_AHBCLK_SYSTICK_EN_Pos) ¿"CLK_AHBCLK_APB1EN_Pos (3) À"CLK_AHBCLK_APB1EN_Msk (0x1ul << CLK_AHBCLK_APB1EN_Pos) Á"CLK_AHBCLK_APB2EN_Pos (4) Â"CLK_AHBCLK_APB2EN_Msk (0x1ul << CLK_AHBCLK_APB2EN_Pos) Ã"CLK_AHBCLK_AHBEN_Pos (5) Ä"CLK_AHBCLK_AHBEN_Msk (0x1ul << CLK_AHBCLK_AHBEN_Pos) Å"CLK_AHBCLK_BLE32M_EN_Pos (6) Æ"CLK_AHBCLK_BLE32M_EN_Msk (0x1ul << CLK_AHBCLK_BLE32M_EN_Pos) Ç"CLK_AHBCLK_BLE32K_EN_Pos (7) È"CLK_AHBCLK_BLE32K_EN_Msk (0x1ul << CLK_AHBCLK_BLE32K_EN_Pos) É"CLK_AHBCLK_BLE32M_SEL_Pos (8) Ê"CLK_AHBCLK_BLE32M_SEL_Msk (0x3ul << CLK_AHBCLK_BLE32M_SEL_Pos) Ë"CLK_AHBCLK_ROM_CLK_EN_Pos (10) Ì"CLK_AHBCLK_ROM_CLK_EN_Msk (0x1ul << CLK_AHBCLK_ROM_CLK_EN_Pos) Í"CLK_AHBCLK_EFUSE_CLK_EN_Pos (11) Î"CLK_AHBCLK_EFUSE_CLK_EN_Msk (0x1ul << CLK_AHBCLK_EFUSE_CLK_EN_Pos) Ï"CLK_AHBCLK_USB_AHB_CLK_EN_Pos (13) Ð"CLK_AHBCLK_USB_AHB_CLK_EN_Msk (0x1ul << CLK_AHBCLK_USB_AHB_CLK_EN_Pos) Ñ"CLK_AHBCLK_USB_48M_CLK_EN_Pos (14) Ò"CLK_AHBCLK_USB_48M_CLK_EN_Msk (0x1ul << CLK_AHBCLK_USB_48M_CLK_EN_Pos) Ó"CLK_AHBCLK_SPI_FLASH_DIV_Pos (16) Ô"CLK_AHBCLK_SPI_FLASH_DIV_Msk (0xFul << CLK_AHBCLK_SPI_FLASH_DIV_Pos) Õ"CLK_AHBCLK_SPI_FLASH_CLK_SEL_Pos (20) Ö"CLK_AHBCLK_SPI_FLASH_CLK_SEL_Msk (0x1ul << CLK_AHBCLK_SPI_FLASH_CLK_SEL_Pos) ×"CLK_AHBCLK_DPLL_CLK_TST_EN_Pos (21) Ø"CLK_AHBCLK_DPLL_CLK_TST_EN_Msk (0x1ul << CLK_AHBCLK_DPLL_CLK_TST_EN_Pos) Ù"CLK_AHBCLK_SPI_CLK_SEL_FPGA_Pos (24) Ú"CLK_AHBCLK_SPI_CLK_SEL_FPGA_Msk (0x1ul << CLK_AHBCLK_SPI_CLK_SEL_FPGA_Pos) Ý"CLK_APB1CLK_WDTSRC_SEL_Pos (16) Þ"CLK_APB1CLK_WDTSRC_SEL_Msk (0x1ul << CLK_APB1CLK_WDTSRC_SEL_Pos) ß"CLK_APB1CLK_WWDTSRC_SEL_Pos (17) à"CLK_APB1CLK_WWDTSRC_SEL_Msk (0x1ul << CLK_APB1CLK_WWDTSRC_SEL_Pos) á"CLK_APB1CLK_TMR0SRC_SEL_Pos (18) â"CLK_APB1CLK_TMR0SRC_SEL_Msk (0x3ul << CLK_APB1CLK_TMR0SRC_SEL_Pos) ã"CLK_APB1CLK_PWM01_CLK_SEL_Pos (20) ä"CLK_APB1CLK_PWM01_CLK_SEL_Msk (0x1ul << CLK_APB1CLK_PWM01_CLK_SEL_Pos) å"CLK_APB1CLK_PWM23_CLK_SEL_Pos (21) æ"CLK_APB1CLK_PWM23_CLK_SEL_Msk (0x1ul << CLK_APB1CLK_PWM23_CLK_SEL_Pos) ç"CLK_APB1CLK_PWM45_CLK_SEL_Pos (22) è"CLK_APB1CLK_PWM45_CLK_SEL_Msk (0x1ul << CLK_APB1CLK_PWM45_CLK_SEL_Pos) é"CLK_APB1CLK_PWM67_CLK_SEL_Pos (23) ê"CLK_APB1CLK_PWM67_CLK_SEL_Msk (0x1ul << CLK_APB1CLK_PWM67_CLK_SEL_Pos) ë"CLK_APB1CLK_ADC_CLK_SEL_Pos (24) ì"CLK_APB1CLK_ADC_CLK_SEL_Msk (0x1ul << CLK_APB1CLK_ADC_CLK_SEL_Pos) ï"CLK_APB2CLK_TMR1SRC_SEL_Pos (8) ð"CLK_APB2CLK_TMR1SRC_SEL_Msk (0x3ul << CLK_APB2CLK_TMR1SRC_SEL_Pos) ñ"CLK_APB2CLK_TMR2SRC_SEL_Pos (10) ò"CLK_APB2CLK_TMR2SRC_SEL_Msk (0x3ul << CLK_APB2CLK_TMR2SRC_SEL_Pos) ö"CLK_MEASCLK_TRIM_CLK_EN_Pos (1) ÷"CLK_MEASCLK_TRIM_CLK_EN_Msk (0x1ul << CLK_MEASCLK_TRIM_CLK_EN_Pos) ø"CLK_MEASCLK_TRIM_CLK_SEL_Pos (2) ù"CLK_MEASCLK_TRIM_CLK_SEL_Msk (0x1ul << CLK_MEASCLK_TRIM_CLK_SEL_Pos) ú"CLK_MEASCLK_TRIM_CLK_DIV_Pos (4) û"CLK_MEASCLK_TRIM_CLK_DIV_Msk (0x1fful << CLK_MEASCLK_TRIM_CLK_DIV_Pos) ü"CLK_MEASCLK_XTL_QUICK_EN_Pos (14) ý"CLK_MEASCLK_XTL_QUICK_EN_Msk (0x1ul << CLK_MEASCLK_XTL_QUICK_EN_Pos) þ"CLK_MEASCLK_XTH_DIV_Pos (15) ÿ"CLK_MEASCLK_XTH_DIV_Msk (0x1fful << CLK_MEASCLK_XTH_DIV_Pos) ó#WDT_CTL_RSTCNT_Pos (0) ô#WDT_CTL_RSTCNT_Msk (0x1ul << WDT_CTL_RSTCNT_Pos) ö#WDT_CTL_RSTEN_Pos (1) ÷#WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos) ù#WDT_CTL_RSTF_Pos (2) ú#WDT_CTL_RSTF_Msk (0x1ul << WDT_CTL_RSTF_Pos) ü#WDT_CTL_IF_Pos (3) ý#WDT_CTL_IF_Msk (0x1ul << WDT_CTL_IF_Pos) ÿ#WDT_CTL_WKEN_Pos (4) $WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos) $WDT_CTL_WKF_Pos (5) $WDT_CTL_WKF_Msk (0x1ul << WDT_CTL_WKF_Pos)
$WDT_CTL_INTEN_Pos (6) $WDT_CTL_INTEN_Msk (0x1ul << WDT_CTL_INTEN_Pos) $WDT_CTL_WDTEN_Pos (7) $WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos) $WDT_CTL_TOUTSEL_Pos (8) $WDT_CTL_TOUTSEL_Msk (0xful << WDT_CTL_TOUTSEL_Pos) $WDT_CTL_RST_REGION_SEL_Pos (12) $WDT_CTL_RST_REGION_SEL_Msk (0x1ul << WDT_CTL_RST_REGION_SEL_Pos) $WDT_CTL_TOF_Pos (16) $WDT_CTL_TOF_Msk (0x1ul << WDT_CTL_TOF_Pos) $WDT_CTL_ICEDEBUG_Pos (31) $WDT_CTL_ICEDEBUG_Msk (0x1ul << WDT_CTL_ICEDEBUG_Pos) $WDT_ALTCTL_RSTDSEL_Pos (0) $WDT_ALTCTL_RSTDSEL_Msk (0x3ul << WDT_ALTCTL_RSTDSEL_Pos) %WWDT_RLDCNT_RLDCNT_Pos (0) %WWDT_RLDCNT_RLDCNT_Msk (0xfffffffful << WWDT_RLDCNT_RLDCNT_Pos) %WWDT_CTL_WWDTEN_Pos (0) %WWDT_CTL_WWDTEN_Msk (0x1ul << WWDT_CTL_WWDTEN_Pos) %WWDT_CTL_INTEN_Pos (1) %WWDT_CTL_INTEN_Msk (0x1ul << WWDT_CTL_INTEN_Pos) %WWDT_CTL_PSCSEL_Pos (8) %WWDT_CTL_PSCSEL_Msk (0xful << WWDT_CTL_PSCSEL_Pos) ¡%WWDT_CTL_CMPDAT_Pos (16) ¢%WWDT_CTL_CMPDAT_Msk (0x3ful << WWDT_CTL_CMPDAT_Pos) ¤%WWDT_CTL_ICEDEBUG_Pos (31) ¥%WWDT_CTL_ICEDEBUG_Msk (0x1ul << WWDT_CTL_ICEDEBUG_Pos) §%WWDT_STATUS_WWDTIF_Pos (0) ¨%WWDT_STATUS_WWDTIF_Msk (0x1ul << WWDT_STATUS_WWDTIF_Pos) ª%WWDT_STATUS_WWDTRF_Pos (1) «%WWDT_STATUS_WWDTRF_Msk (0x1ul << WWDT_STATUS_WWDTRF_Pos) %WWDT_STATUS_WWDTF_Pos (2) ®%WWDT_STATUS_WWDTF_Msk (0x1ul << WWDT_STATUS_WWDTF_Pos) °%WWDT_CNT_CNTDAT_Pos (0) ±%WWDT_CNT_CNTDAT_Msk (0x3ful << WWDT_CNT_CNTDAT_Pos) ¹.PWM_CLKPSC_CLKPSC01_Pos (0) º.PWM_CLKPSC_CLKPSC01_Msk (0xfful << PWM_CLKPSC_CLKPSC01_Pos) ¼.PWM_CLKPSC_CLKPSC23_Pos (8) ½.PWM_CLKPSC_CLKPSC23_Msk (0xfful << PWM_CLKPSC_CLKPSC23_Pos) ¿.PWM_CLKPSC_CLKPSC45_Pos (16) À.PWM_CLKPSC_CLKPSC45_Msk (0xfful << PWM_CLKPSC_CLKPSC45_Pos) Â.PWM_CLKPSC_CLKPSC67_Pos (24) Ã.PWM_CLKPSC_CLKPSC67_Msk (0xfful << PWM_CLKPSC_CLKPSC67_Pos) Å.PWM_CLKDIV_CLKDIV0_Pos (0) Æ.PWM_CLKDIV_CLKDIV0_Msk (0x7ul << PWM_CLKDIV_CLKDIV0_Pos) È.PWM_CLKDIV_CLKDIV1_Pos (4) É.PWM_CLKDIV_CLKDIV1_Msk (0x7ul << PWM_CLKDIV_CLKDIV1_Pos) Ë.PWM_CLKDIV_CLKDIV2_Pos (8) Ì.PWM_CLKDIV_CLKDIV2_Msk (0x7ul << PWM_CLKDIV_CLKDIV2_Pos) Î.PWM_CLKDIV_CLKDIV3_Pos (12) Ï.PWM_CLKDIV_CLKDIV3_Msk (0x7ul << PWM_CLKDIV_CLKDIV3_Pos) Ñ.PWM_CLKDIV_CLKDIV4_Pos (16) Ò.PWM_CLKDIV_CLKDIV4_Msk (0x7ul << PWM_CLKDIV_CLKDIV4_Pos) Ô.PWM_CLKDIV_CLKDIV5_Pos (20) Õ.PWM_CLKDIV_CLKDIV5_Msk (0x7ul << PWM_CLKDIV_CLKDIV5_Pos) Ø.PWM_CLKDIV_CLKDIV6_Pos (24) Ù.PWM_CLKDIV_CLKDIV6_Msk (0x7ul << PWM_CLKDIV_CLKDIV6_Pos) Û.PWM_CLKDIV_CLKDIV7_Pos (28) Ü.PWM_CLKDIV_CLKDIV7_Msk (0x7ul << PWM_CLKDIV_CLKDIV7_Pos) Þ.PWM_CTL_CNTEN0_Pos (0) ß.PWM_CTL_CNTEN0_Msk (0x1ul << PWM_CTL_CNTEN0_Pos) á.PWM_CTL_PINV0_Pos (2) â.PWM_CTL_PINV0_Msk (0x1ul << PWM_CTL_PINV0_Pos) ä.PWM_CTL_CNTMODE0_Pos (3) å.PWM_CTL_CNTMODE0_Msk (0x1ul << PWM_CTL_CNTMODE0_Pos) ç.PWM_CTL_CNTEN1_Pos (4) è.PWM_CTL_CNTEN1_Msk (0x1ul << PWM_CTL_CNTEN1_Pos) ê.PWM_CTL_HCUPDT_Pos (5) ë.PWM_CTL_HCUPDT_Msk (0x1ul << PWM_CTL_HCUPDT_Pos) í.PWM_CTL_PINV1_Pos (6) î.PWM_CTL_PINV1_Msk (0x1ul << PWM_CTL_PINV1_Pos) ð.PWM_CTL_CNTMODE1_Pos (7) ñ.PWM_CTL_CNTMODE1_Msk (0x1ul << PWM_CTL_CNTMODE1_Pos) ó.PWM_CTL_CNTEN2_Pos (8) ô.PWM_CTL_CNTEN2_Msk (0x1ul << PWM_CTL_CNTEN2_Pos) ö.PWM_CTL_PINV2_Pos (10) ÷.PWM_CTL_PINV2_Msk (0x1ul << PWM_CTL_PINV2_Pos) ù.PWM_CTL_CNTMODE2_Pos (11) ú.PWM_CTL_CNTMODE2_Msk (0x1ul << PWM_CTL_CNTMODE2_Pos) ü.PWM_CTL_CNTEN3_Pos (12) ý.PWM_CTL_CNTEN3_Msk (0x1ul << PWM_CTL_CNTEN3_Pos) ÿ.PWM_CTL_PINV3_Pos (14) /PWM_CTL_PINV3_Msk (0x1ul << PWM_CTL_PINV3_Pos) /PWM_CTL_CNTMODE3_Pos (15) /PWM_CTL_CNTMODE3_Msk (0x1ul << PWM_CTL_CNTMODE3_Pos)
/PWM_CTL_CNTEN4_Pos (16) /PWM_CTL_CNTEN4_Msk (0x1ul << PWM_CTL_CNTEN4_Pos) /PWM_CTL_PINV4_Pos (18) /PWM_CTL_PINV4_Msk (0x1ul << PWM_CTL_PINV4_Pos) /PWM_CTL_CNTMODE4_Pos (19) /PWM_CTL_CNTMODE4_Msk (0x1ul << PWM_CTL_CNTMODE4_Pos) /PWM_CTL_CNTEN5_Pos (20) /PWM_CTL_CNTEN5_Msk (0x1ul << PWM_CTL_CNTEN5_Pos) /PWM_CTL_ASYMEN_Pos (21) /PWM_CTL_ASYMEN_Msk (0x1ul << PWM_CTL_ASYMEN_Pos) /PWM_CTL_PINV5_Pos (22) /PWM_CTL_PINV5_Msk (0x1ul << PWM_CTL_PINV5_Pos) /PWM_CTL_CNTMODE5_Pos (23) /PWM_CTL_CNTMODE5_Msk (0x1ul << PWM_CTL_CNTMODE5_Pos) /PWM_CTL_CNTEN6_Pos (24) /PWM_CTL_CNTEN6_Msk (0x1ul << PWM_CTL_CNTEN6_Pos) /PWM_CTL_PINV6_Pos (26) /PWM_CTL_PINV6_Msk (0x1ul << PWM_CTL_PINV6_Pos) /PWM_CTL_CNTMODE6_Pos (27) ¡/PWM_CTL_CNTMODE6_Msk (0x1ul << PWM_CTL_CNTMODE6_Pos) £/PWM_CTL_CNTEN7_Pos (28) ¤/PWM_CTL_CNTEN7_Msk (0x1ul << PWM_CTL_CNTEN7_Pos) ¦/PWM_CTL_PINV7_Pos (30) §/PWM_CTL_PINV7_Msk (0x1ul << PWM_CTL_PINV7_Pos) ©/PWM_CTL_CNTMODE7_Pos (31) ª/PWM_CTL_CNTMODE7_Msk (0x1ul << PWM_CTL_CNTMODE7_Pos) ¬/PWM_PERIOD0_PERIOD0_Pos (0) /PWM_PERIOD0_PERIOD0_Msk (0xfffful << PWM_PERIOD0_PERIOD0_Pos) ¯/PWM_PERIOD0_PERIOD1_Pos (0) °/PWM_PERIOD0_PERIOD1_Msk (0xfffful << PWM_PERIOD0_PERIOD1_Pos) ²/PWM_PERIOD0_PERIOD2_Pos (0) ³/PWM_PERIOD0_PERIOD2_Msk (0xfffful << PWM_PERIOD0_PERIOD2_Pos) µ/PWM_PERIOD0_PERIOD3_Pos (0) ¶/PWM_PERIOD0_PERIOD3_Msk (0xfffful << PWM_PERIOD0_PERIOD3_Pos) ¸/PWM_PERIOD0_PERIOD4_Pos (0) ¹/PWM_PERIOD0_PERIOD4_Msk (0xfffful << PWM_PERIOD0_PERIOD4_Pos) »/PWM_PERIOD0_PERIOD5_Pos (0) ¼/PWM_PERIOD0_PERIOD5_Msk (0xfffful << PWM_PERIOD0_PERIOD5_Pos) ¾/PWM_PERIOD0_PERIOD6_Pos (0) ¿/PWM_PERIOD0_PERIOD6_Msk (0xfffful << PWM_PERIOD0_PERIOD6_Pos) Á/PWM_PERIOD0_PERIOD7_Pos (0) Â/PWM_PERIOD0_PERIOD7_Msk (0xfffful << PWM_PERIOD0_PERIOD7_Pos) Ä/PWM_PERIOD1_PERIOD0_Pos (0) Å/PWM_PERIOD1_PERIOD0_Msk (0xfffful << PWM_PERIOD1_PERIOD0_Pos) Ç/PWM_PERIOD1_PERIOD1_Pos (0) È/PWM_PERIOD1_PERIOD1_Msk (0xfffful << PWM_PERIOD1_PERIOD1_Pos) Ê/PWM_PERIOD1_PERIOD2_Pos (0) Ë/PWM_PERIOD1_PERIOD2_Msk (0xfffful << PWM_PERIOD1_PERIOD2_Pos) Í/PWM_PERIOD1_PERIOD3_Pos (0) Î/PWM_PERIOD1_PERIOD3_Msk (0xfffful << PWM_PERIOD1_PERIOD3_Pos) Ð/PWM_PERIOD1_PERIOD4_Pos (0) Ñ/PWM_PERIOD1_PERIOD4_Msk (0xfffful << PWM_PERIOD1_PERIOD4_Pos) Ó/PWM_PERIOD1_PERIOD5_Pos (0) Ô/PWM_PERIOD1_PERIOD5_Msk (0xfffful << PWM_PERIOD1_PERIOD5_Pos) Ö/PWM_PERIOD1_PERIOD6_Pos (0) ×/PWM_PERIOD1_PERIOD6_Msk (0xfffful << PWM_PERIOD1_PERIOD6_Pos) Ù/PWM_PERIOD1_PERIOD7_Pos (0) Ú/PWM_PERIOD1_PERIOD7_Msk (0xfffful << PWM_PERIOD1_PERIOD7_Pos) Ü/PWM_PERIOD2_PERIOD0_Pos (0) Ý/PWM_PERIOD2_PERIOD0_Msk (0xfffful << PWM_PERIOD2_PERIOD0_Pos) ß/PWM_PERIOD2_PERIOD1_Pos (0) à/PWM_PERIOD2_PERIOD1_Msk (0xfffful << PWM_PERIOD2_PERIOD1_Pos) â/PWM_PERIOD2_PERIOD2_Pos (0) ã/PWM_PERIOD2_PERIOD2_Msk (0xfffful << PWM_PERIOD2_PERIOD2_Pos) å/PWM_PERIOD2_PERIOD3_Pos (0) æ/PWM_PERIOD2_PERIOD3_Msk (0xfffful << PWM_PERIOD2_PERIOD3_Pos) è/PWM_PERIOD2_PERIOD4_Pos (0) é/PWM_PERIOD2_PERIOD4_Msk (0xfffful << PWM_PERIOD2_PERIOD4_Pos) ë/PWM_PERIOD2_PERIOD5_Pos (0) ì/PWM_PERIOD2_PERIOD5_Msk (0xfffful << PWM_PERIOD2_PERIOD5_Pos) î/PWM_PERIOD2_PERIOD6_Pos (0) ï/PWM_PERIOD2_PERIOD6_Msk (0xfffful << PWM_PERIOD2_PERIOD6_Pos) ñ/PWM_PERIOD2_PERIOD7_Pos (0) ò/PWM_PERIOD2_PERIOD7_Msk (0xfffful << PWM_PERIOD2_PERIOD7_Pos) ô/PWM_PERIOD3_PERIOD0_Pos (0) õ/PWM_PERIOD3_PERIOD0_Msk (0xfffful << PWM_PERIOD3_PERIOD0_Pos) ÷/PWM_PERIOD3_PERIOD1_Pos (0) ø/PWM_PERIOD3_PERIOD1_Msk (0xfffful << PWM_PERIOD3_PERIOD1_Pos) ú/PWM_PERIOD3_PERIOD2_Pos (0) û/PWM_PERIOD3_PERIOD2_Msk (0xfffful << PWM_PERIOD3_PERIOD2_Pos) ý/PWM_PERIOD3_PERIOD3_Pos (0) þ/PWM_PERIOD3_PERIOD3_Msk (0xfffful << PWM_PERIOD3_PERIOD3_Pos) 0PWM_PERIOD3_PERIOD4_Pos (0) 0PWM_PERIOD3_PERIOD4_Msk (0xfffful << PWM_PERIOD3_PERIOD4_Pos) 0PWM_PERIOD3_PERIOD5_Pos (0) 0PWM_PERIOD3_PERIOD5_Msk (0xfffful << PWM_PERIOD3_PERIOD5_Pos) 0PWM_PERIOD3_PERIOD6_Pos (0) 0PWM_PERIOD3_PERIOD6_Msk (0xfffful << PWM_PERIOD3_PERIOD6_Pos) 0PWM_PERIOD3_PERIOD7_Pos (0) 0PWM_PERIOD3_PERIOD7_Msk (0xfffful << PWM_PERIOD3_PERIOD7_Pos) 0PWM_PERIOD4_PERIOD0_Pos (0) 0PWM_PERIOD4_PERIOD0_Msk (0xfffful << PWM_PERIOD4_PERIOD0_Pos) 0PWM_PERIOD4_PERIOD1_Pos (0) 0PWM_PERIOD4_PERIOD1_Msk (0xfffful << PWM_PERIOD4_PERIOD1_Pos) 0PWM_PERIOD4_PERIOD2_Pos (0) 0PWM_PERIOD4_PERIOD2_Msk (0xfffful << PWM_PERIOD4_PERIOD2_Pos) 0PWM_PERIOD4_PERIOD3_Pos (0) 0PWM_PERIOD4_PERIOD3_Msk (0xfffful << PWM_PERIOD4_PERIOD3_Pos) 0PWM_PERIOD4_PERIOD4_Pos (0) 0PWM_PERIOD4_PERIOD4_Msk (0xfffful << PWM_PERIOD4_PERIOD4_Pos) 0PWM_PERIOD4_PERIOD5_Pos (0) 0PWM_PERIOD4_PERIOD5_Msk (0xfffful << PWM_PERIOD4_PERIOD5_Pos) 0PWM_PERIOD4_PERIOD6_Pos (0) 0PWM_PERIOD4_PERIOD6_Msk (0xfffful << PWM_PERIOD4_PERIOD6_Pos) ¡0PWM_PERIOD4_PERIOD7_Pos (0) ¢0PWM_PERIOD4_PERIOD7_Msk (0xfffful << PWM_PERIOD4_PERIOD7_Pos) ¤0PWM_PERIOD5_PERIOD0_Pos (0) ¥0PWM_PERIOD5_PERIOD0_Msk (0xfffful << PWM_PERIOD5_PERIOD0_Pos) §0PWM_PERIOD5_PERIOD1_Pos (0) ¨0PWM_PERIOD5_PERIOD1_Msk (0xfffful << PWM_PERIOD5_PERIOD1_Pos) ª0PWM_PERIOD5_PERIOD2_Pos (0) «0PWM_PERIOD5_PERIOD2_Msk (0xfffful << PWM_PERIOD5_PERIOD2_Pos) 0PWM_PERIOD5_PERIOD3_Pos (0) ®0PWM_PERIOD5_PERIOD3_Msk (0xfffful << PWM_PERIOD5_PERIOD3_Pos) °0PWM_PERIOD5_PERIOD4_Pos (0) ±0PWM_PERIOD5_PERIOD4_Msk (0xfffful << PWM_PERIOD5_PERIOD4_Pos) ³0PWM_PERIOD5_PERIOD5_Pos (0) ´0PWM_PERIOD5_PERIOD5_Msk (0xfffful << PWM_PERIOD5_PERIOD5_Pos) ¶0PWM_PERIOD5_PERIOD6_Pos (0) ·0PWM_PERIOD5_PERIOD6_Msk (0xfffful << PWM_PERIOD6_PERIOD6_Pos) ¹0PWM_PERIOD5_PERIOD7_Pos (0) º0PWM_PERIOD5_PERIOD7_Msk (0xfffful << PWM_PERIOD6_PERIOD7_Pos) ¼0PWM_PERIOD6_PERIOD0_Pos (0) ½0PWM_PERIOD6_PERIOD0_Msk (0xfffful << PWM_PERIOD6_PERIOD0_Pos) ¿0PWM_PERIOD6_PERIOD1_Pos (0) À0PWM_PERIOD6_PERIOD1_Msk (0xfffful << PWM_PERIOD6_PERIOD1_Pos) Â0PWM_PERIOD6_PERIOD2_Pos (0) Ã0PWM_PERIOD6_PERIOD2_Msk (0xfffful << PWM_PERIOD6_PERIOD2_Pos) Å0PWM_PERIOD6_PERIOD3_Pos (0) Æ0PWM_PERIOD6_PERIOD3_Msk (0xfffful << PWM_PERIOD6_PERIOD3_Pos) È0PWM_PERIOD6_PERIOD4_Pos (0) É0PWM_PERIOD6_PERIOD4_Msk (0xfffful << PWM_PERIOD6_PERIOD4_Pos) Ë0PWM_PERIOD6_PERIOD5_Pos (0) Ì0PWM_PERIOD6_PERIOD5_Msk (0xfffful << PWM_PERIOD6_PERIOD5_Pos) Î0PWM_PERIOD6_PERIOD6_Pos (0) Ï0PWM_PERIOD6_PERIOD6_Msk (0xfffful << PWM_PERIOD6_PERIOD6_Pos) Ñ0PWM_PERIOD6_PERIOD7_Pos (0) Ò0PWM_PERIOD6_PERIOD7_Msk (0xfffful << PWM_PERIOD6_PERIOD7_Pos) Ô0PWM_PERIOD7_PERIOD0_Pos (0) Õ0PWM_PERIOD7_PERIOD0_Msk (0xfffful << PWM_PERIOD7_PERIOD0_Pos) ×0PWM_PERIOD7_PERIOD1_Pos (0) Ø0PWM_PERIOD7_PERIOD1_Msk (0xfffful << PWM_PERIOD7_PERIOD1_Pos) Ú0PWM_PERIOD7_PERIOD2_Pos (0) Û0PWM_PERIOD7_PERIOD2_Msk (0xfffful << PWM_PERIOD7_PERIOD2_Pos) Ý0PWM_PERIOD7_PERIOD3_Pos (0) Þ0PWM_PERIOD7_PERIOD3_Msk (0xfffful << PWM_PERIOD7_PERIOD3_Pos) à0PWM_PERIOD7_PERIOD4_Pos (0) á0PWM_PERIOD7_PERIOD4_Msk (0xfffful << PWM_PERIOD7_PERIOD4_Pos) ã0PWM_PERIOD7_PERIOD5_Pos (0) ä0PWM_PERIOD7_PERIOD5_Msk (0xfffful << PWM_PERIOD7_PERIOD5_Pos) æ0PWM_PERIOD7_PERIOD6_Pos (0) ç0PWM_PERIOD7_PERIOD6_Msk (0xfffful << PWM_PERIOD7_PERIOD6_Pos) é0PWM_PERIOD7_PERIOD7_Pos (0) ê0PWM_PERIOD7_PERIOD7_Msk (0xfffful << PWM_PERIOD7_PERIOD7_Pos) ì0PWM_CMPDAT0_CMP0_Pos (0) í0PWM_CMPDAT0_CMP0_Msk (0xfffful << PWM_CMPDAT0_CMP0_Pos) ï0PWM_CMPDAT0_CMP1_Pos (0) ð0PWM_CMPDAT0_CMP1_Msk (0xfffful << PWM_CMPDAT0_CMP1_Pos) ò0PWM_CMPDAT0_CMP2_Pos (0) ó0PWM_CMPDAT0_CMP2_Msk (0xfffful << PWM_CMPDAT0_CMP2_Pos) õ0PWM_CMPDAT0_CMP3_Pos (0) ö0PWM_CMPDAT0_CMP3_Msk (0xfffful << PWM_CMPDAT0_CMP3_Pos) ø0PWM_CMPDAT0_CMP4_Pos (0) ù0PWM_CMPDAT0_CMP4_Msk (0xfffful << PWM_CMPDAT0_CMP4_Pos) û0PWM_CMPDAT0_CMP5_Pos (0) ü0PWM_CMPDAT0_CMP5_Msk (0xfffful << PWM_CMPDAT0_CMP5_Pos) þ0PWM_CMPDAT0_CMP6_Pos (0) ÿ0PWM_CMPDAT0_CMP6_Msk (0xfffful << PWM_CMPDAT0_CMP6_Pos) 1PWM_CMPDAT0_CMP7_Pos (0) 1PWM_CMPDAT0_CMP7_Msk (0xfffful << PWM_CMPDAT0_CMP7_Pos) 1PWM_CMPDAT0_CMPD0_Pos (16)
1PWM_CMPDAT0_CMPD0_Msk (0xfffful << PWM_CMPDAT0_CMPD0_Pos) 1PWM_CMPDAT0_CMPD1_Pos (16) 1PWM_CMPDAT0_CMPD1_Msk (0xfffful << PWM_CMPDAT0_CMPD1_Pos) 1PWM_CMPDAT0_CMPD2_Pos (16) 1PWM_CMPDAT0_CMPD2_Msk (0xfffful << PWM_CMPDAT0_CMPD2_Pos) 1PWM_CMPDAT0_CMPD3_Pos (16) 1PWM_CMPDAT0_CMPD3_Msk (0xfffful << PWM_CMPDAT0_CMPD3_Pos) 1PWM_CMPDAT0_CMPD4_Pos (16) 1PWM_CMPDAT0_CMPD4_Msk (0xfffful << PWM_CMPDAT0_CMPD4_Pos) 1PWM_CMPDAT0_CMPD5_Pos (16) 1PWM_CMPDAT0_CMPD5_Msk (0xfffful << PWM_CMPDAT0_CMPD5_Pos) 1PWM_CMPDAT0_CMPD6_Pos (16) 1PWM_CMPDAT0_CMPD6_Msk (0xfffful << PWM_CMPDAT0_CMPD6_Pos) 1PWM_CMPDAT0_CMPD7_Pos (16) 1PWM_CMPDAT0_CMPD7_Msk (0xfffful << PWM_CMPDAT0_CMPD7_Pos) 1PWM_CMPDAT1_CMP0_Pos (0) 1PWM_CMPDAT1_CMP0_Msk (0xfffful << PWM_CMPDAT1_CMP0_Pos) 1PWM_CMPDAT1_CMP1_Pos (0) 1PWM_CMPDAT1_CMP1_Msk (0xfffful << PWM_CMPDAT1_CMP1_Pos) ¢1PWM_CMPDAT1_CMP2_Pos (0) £1PWM_CMPDAT1_CMP2_Msk (0xfffful << PWM_CMPDAT1_CMP2_Pos) ¥1PWM_CMPDAT1_CMP3_Pos (0) ¦1PWM_CMPDAT1_CMP3_Msk (0xfffful << PWM_CMPDAT1_CMP3_Pos) ¨1PWM_CMPDAT1_CMP4_Pos (0) ©1PWM_CMPDAT1_CMP4_Msk (0xfffful << PWM_CMPDAT1_CMP4_Pos) «1PWM_CMPDAT1_CMP5_Pos (0) ¬1PWM_CMPDAT1_CMP5_Msk (0xfffful << PWM_CMPDAT1_CMP5_Pos) ®1PWM_CMPDAT1_CMP6_Pos (0) ¯1PWM_CMPDAT1_CMP6_Msk (0xfffful << PWM_CMPDAT1_CMP6_Pos) ±1PWM_CMPDAT1_CMP7_Pos (0) ²1PWM_CMPDAT1_CMP7_Msk (0xfffful << PWM_CMPDAT1_CMP7_Pos) ´1PWM_CMPDAT1_CMPD0_Pos (16) µ1PWM_CMPDAT1_CMPD0_Msk (0xfffful << PWM_CMPDAT1_CMPD0_Pos) ·1PWM_CMPDAT1_CMPD1_Pos (16) ¸1PWM_CMPDAT1_CMPD1_Msk (0xfffful << PWM_CMPDAT1_CMPD1_Pos) º1PWM_CMPDAT1_CMPD2_Pos (16) »1PWM_CMPDAT1_CMPD2_Msk (0xfffful << PWM_CMPDAT1_CMPD2_Pos) ½1PWM_CMPDAT1_CMPD3_Pos (16) ¾1PWM_CMPDAT1_CMPD3_Msk (0xfffful << PWM_CMPDAT1_CMPD3_Pos) À1PWM_CMPDAT1_CMPD4_Pos (16) Á1PWM_CMPDAT1_CMPD4_Msk (0xfffful << PWM_CMPDAT1_CMPD4_Pos) Ã1PWM_CMPDAT1_CMPD5_Pos (16) Ä1PWM_CMPDAT1_CMPD5_Msk (0xfffful << PWM_CMPDAT1_CMPD5_Pos) Æ1PWM_CMPDAT1_CMPD6_Pos (16) Ç1PWM_CMPDAT1_CMPD6_Msk (0xfffful << PWM_CMPDAT1_CMPD6_Pos) É1PWM_CMPDAT1_CMPD7_Pos (16) Ê1PWM_CMPDAT1_CMPD7_Msk (0xfffful << PWM_CMPDAT1_CMPD7_Pos) Ì1PWM_CMPDAT2_CMP0_Pos (0) Í1PWM_CMPDAT2_CMP0_Msk (0xfffful << PWM_CMPDAT2_CMP0_Pos) Ï1PWM_CMPDAT2_CMP1_Pos (0) Ð1PWM_CMPDAT2_CMP1_Msk (0xfffful << PWM_CMPDAT2_CMP1_Pos) Ò1PWM_CMPDAT2_CMP2_Pos (0) Ó1PWM_CMPDAT2_CMP2_Msk (0xfffful << PWM_CMPDAT2_CMP2_Pos) Õ1PWM_CMPDAT2_CMP3_Pos (0) Ö1PWM_CMPDAT2_CMP3_Msk (0xfffful << PWM_CMPDAT2_CMP3_Pos) Ø1PWM_CMPDAT2_CMP4_Pos (0) Ù1PWM_CMPDAT2_CMP4_Msk (0xfffful << PWM_CMPDAT2_CMP4_Pos) Û1PWM_CMPDAT2_CMP5_Pos (0) Ü1PWM_CMPDAT2_CMP5_Msk (0xfffful << PWM_CMPDAT2_CMP5_Pos) Þ1PWM_CMPDAT2_CMP6_Pos (0) ß1PWM_CMPDAT2_CMP6_Msk (0xfffful << PWM_CMPDAT2_CMP6_Pos) á1PWM_CMPDAT2_CMP7_Pos (0) â1PWM_CMPDAT2_CMP7_Msk (0xfffful << PWM_CMPDAT2_CMP7_Pos) ä1PWM_CMPDAT2_CMPD0_Pos (16) å1PWM_CMPDAT2_CMPD0_Msk (0xfffful << PWM_CMPDAT2_CMPD0_Pos) ç1PWM_CMPDAT2_CMPD1_Pos (16) è1PWM_CMPDAT2_CMPD1_Msk (0xfffful << PWM_CMPDAT2_CMPD1_Pos) ê1PWM_CMPDAT2_CMPD2_Pos (16) ë1PWM_CMPDAT2_CMPD2_Msk (0xfffful << PWM_CMPDAT2_CMPD2_Pos) í1PWM_CMPDAT2_CMPD3_Pos (16) î1PWM_CMPDAT2_CMPD3_Msk (0xfffful << PWM_CMPDAT2_CMPD3_Pos) ð1PWM_CMPDAT2_CMPD4_Pos (16) ñ1PWM_CMPDAT2_CMPD4_Msk (0xfffful << PWM_CMPDAT2_CMPD4_Pos) ó1PWM_CMPDAT2_CMPD5_Pos (16) ô1PWM_CMPDAT2_CMPD5_Msk (0xfffful << PWM_CMPDAT2_CMPD5_Pos) ö1PWM_CMPDAT2_CMPD6_Pos (16) ÷1PWM_CMPDAT2_CMPD6_Msk (0xfffful << PWM_CMPDAT2_CMPD6_Pos) ù1PWM_CMPDAT2_CMPD7_Pos (16) ú1PWM_CMPDAT2_CMPD7_Msk (0xfffful << PWM_CMPDAT2_CMPD7_Pos) ü1PWM_CMPDAT3_CMP0_Pos (0) ý1PWM_CMPDAT3_CMP0_Msk (0xfffful << PWM_CMPDAT3_CMP0_Pos) ÿ1PWM_CMPDAT3_CMP1_Pos (0) 2PWM_CMPDAT3_CMP1_Msk (0xfffful << PWM_CMPDAT3_CMP1_Pos) 2PWM_CMPDAT3_CMP2_Pos (0) 2PWM_CMPDAT3_CMP2_Msk (0xfffful << PWM_CMPDAT3_CMP2_Pos)
2PWM_CMPDAT3_CMP3_Pos (0) 2PWM_CMPDAT3_CMP3_Msk (0xfffful << PWM_CMPDAT3_CMP3_Pos) 2PWM_CMPDAT3_CMP4_Pos (0) 2PWM_CMPDAT3_CMP4_Msk (0xfffful << PWM_CMPDAT3_CMP4_Pos) 2PWM_CMPDAT3_CMP5_Pos (0) 2PWM_CMPDAT3_CMP5_Msk (0xfffful << PWM_CMPDAT3_CMP5_Pos) 2PWM_CMPDAT3_CMP6_Pos (0) 2PWM_CMPDAT3_CMP6_Msk (0xfffful << PWM_CMPDAT3_CMP6_Pos) 2PWM_CMPDAT3_CMP7_Pos (0) 2PWM_CMPDAT3_CMP7_Msk (0xfffful << PWM_CMPDAT3_CMP7_Pos) 2PWM_CMPDAT3_CMPD0_Pos (16) 2PWM_CMPDAT3_CMPD0_Msk (0xfffful << PWM_CMPDAT3_CMPD0_Pos) 2PWM_CMPDAT3_CMPD1_Pos (16) 2PWM_CMPDAT3_CMPD1_Msk (0xfffful << PWM_CMPDAT3_CMPD1_Pos) 2PWM_CMPDAT3_CMPD2_Pos (16) 2PWM_CMPDAT3_CMPD2_Msk (0xfffful << PWM_CMPDAT3_CMPD2_Pos) 2PWM_CMPDAT3_CMPD3_Pos (16) 2PWM_CMPDAT3_CMPD3_Msk (0xfffful << PWM_CMPDAT3_CMPD3_Pos) 2PWM_CMPDAT3_CMPD4_Pos (16) ¡2PWM_CMPDAT3_CMPD4_Msk (0xfffful << PWM_CMPDAT3_CMPD4_Pos) £2PWM_CMPDAT3_CMPD5_Pos (16) ¤2PWM_CMPDAT3_CMPD5_Msk (0xfffful << PWM_CMPDAT3_CMPD5_Pos) ¦2PWM_CMPDAT3_CMPD6_Pos (16) §2PWM_CMPDAT3_CMPD6_Msk (0xfffful << PWM_CMPDAT3_CMPD4_Pos) ©2PWM_CMPDAT3_CMPD7_Pos (16) ª2PWM_CMPDAT3_CMPD7_Msk (0xfffful << PWM_CMPDAT3_CMPD7_Pos) ¬2PWM_CMPDAT4_CMP0_Pos (0) 2PWM_CMPDAT4_CMP0_Msk (0xfffful << PWM_CMPDAT4_CMP0_Pos) ¯2PWM_CMPDAT4_CMP1_Pos (0) °2PWM_CMPDAT4_CMP1_Msk (0xfffful << PWM_CMPDAT4_CMP1_Pos) ²2PWM_CMPDAT4_CMP2_Pos (0) ³2PWM_CMPDAT4_CMP2_Msk (0xfffful << PWM_CMPDAT4_CMP2_Pos) µ2PWM_CMPDAT4_CMP3_Pos (0) ¶2PWM_CMPDAT4_CMP3_Msk (0xfffful << PWM_CMPDAT4_CMP3_Pos) ¸2PWM_CMPDAT4_CMP4_Pos (0) ¹2PWM_CMPDAT4_CMP4_Msk (0xfffful << PWM_CMPDAT4_CMP4_Pos) »2PWM_CMPDAT4_CMP5_Pos (0) ¼2PWM_CMPDAT4_CMP5_Msk (0xfffful << PWM_CMPDAT4_CMP5_Pos) ¾2PWM_CMPDAT4_CMP6_Pos (0) ¿2PWM_CMPDAT4_CMP6_Msk (0xfffful << PWM_CMPDAT4_CMP6_Pos) Á2PWM_CMPDAT4_CMP7_Pos (0) Â2PWM_CMPDAT4_CMP7_Msk (0xfffful << PWM_CMPDAT4_CMP7_Pos) Ä2PWM_CMPDAT4_CMPD0_Pos (16) Å2PWM_CMPDAT4_CMPD0_Msk (0xfffful << PWM_CMPDAT4_CMPD0_Pos) Ç2PWM_CMPDAT4_CMPD1_Pos (16) È2PWM_CMPDAT4_CMPD1_Msk (0xfffful << PWM_CMPDAT4_CMPD1_Pos) Ê2PWM_CMPDAT4_CMPD2_Pos (16) Ë2PWM_CMPDAT4_CMPD2_Msk (0xfffful << PWM_CMPDAT4_CMPD2_Pos) Í2PWM_CMPDAT4_CMPD3_Pos (16) Î2PWM_CMPDAT4_CMPD3_Msk (0xfffful << PWM_CMPDAT4_CMPD3_Pos) Ð2PWM_CMPDAT4_CMPD4_Pos (16) Ñ2PWM_CMPDAT4_CMPD4_Msk (0xfffful << PWM_CMPDAT4_CMPD4_Pos) Ó2PWM_CMPDAT4_CMPD5_Pos (16) Ô2PWM_CMPDAT4_CMPD5_Msk (0xfffful << PWM_CMPDAT4_CMPD5_Pos) Ö2PWM_CMPDAT4_CMPD6_Pos (16) ×2PWM_CMPDAT4_CMPD6_Msk (0xfffful << PWM_CMPDAT4_CMPD6_Pos) Ù2PWM_CMPDAT4_CMPD7_Pos (16) Ú2PWM_CMPDAT4_CMPD7_Msk (0xfffful << PWM_CMPDAT4_CMPD7_Pos) Ü2PWM_CMPDAT5_CMP0_Pos (0) Ý2PWM_CMPDAT5_CMP0_Msk (0xfffful << PWM_CMPDAT5_CMP0_Pos) ß2PWM_CMPDAT5_CMP1_Pos (0) à2PWM_CMPDAT5_CMP1_Msk (0xfffful << PWM_CMPDAT5_CMP1_Pos) â2PWM_CMPDAT5_CMP2_Pos (0) ã2PWM_CMPDAT5_CMP2_Msk (0xfffful << PWM_CMPDAT5_CMP2_Pos) å2PWM_CMPDAT5_CMP3_Pos (0) æ2PWM_CMPDAT5_CMP3_Msk (0xfffful << PWM_CMPDAT5_CMP3_Pos) è2PWM_CMPDAT5_CMP4_Pos (0) é2PWM_CMPDAT5_CMP4_Msk (0xfffful << PWM_CMPDAT5_CMP4_Pos) ë2PWM_CMPDAT5_CMP5_Pos (0) ì2PWM_CMPDAT5_CMP5_Msk (0xfffful << PWM_CMPDAT5_CMP5_Pos) î2PWM_CMPDAT5_CMP6_Pos (0) ï2PWM_CMPDAT5_CMP6_Msk (0xfffful << PWM_CMPDAT5_CMP6_Pos) ñ2PWM_CMPDAT5_CMP7_Pos (0) ò2PWM_CMPDAT5_CMP7_Msk (0xfffful << PWM_CMPDAT5_CMP7_Pos) ô2PWM_CMPDAT5_CMPD0_Pos (16) õ2PWM_CMPDAT5_CMPD0_Msk (0xfffful << PWM_CMPDAT5_CMPD0_Pos) ÷2PWM_CMPDAT5_CMPD1_Pos (16) ø2PWM_CMPDAT5_CMPD1_Msk (0xfffful << PWM_CMPDAT5_CMPD1_Pos) ú2PWM_CMPDAT5_CMPD2_Pos (16) û2PWM_CMPDAT5_CMPD2_Msk (0xfffful << PWM_CMPDAT5_CMPD2_Pos) ý2PWM_CMPDAT5_CMPD3_Pos (16) þ2PWM_CMPDAT5_CMPD3_Msk (0xfffful << PWM_CMPDAT5_CMPD3_Pos) 3PWM_CMPDAT5_CMPD4_Pos (16) 3PWM_CMPDAT5_CMPD4_Msk (0xfffful << PWM_CMPDAT5_CMPD4_Pos) 3PWM_CMPDAT5_CMPD5_Pos (16) 3PWM_CMPDAT5_CMPD5_Msk (0xfffful << PWM_CMPDAT5_CMPD5_Pos) 3PWM_CMPDAT5_CMPD6_Pos (16) 3PWM_CMPDAT5_CMPD6_Msk (0xfffful << PWM_CMPDAT5_CMPD6_Pos) 3PWM_CMPDAT5_CMPD7_Pos (16) 3PWM_CMPDAT5_CMPD7_Msk (0xfffful << PWM_CMPDAT5_CMPD7_Pos) 3PWM_CMPDAT6_CMP0_Pos (0) 3PWM_CMPDAT6_CMP0_Msk (0xfffful << PWM_CMPDAT6_CMP0_Pos) 3PWM_CMPDAT6_CMP1_Pos (0) 3PWM_CMPDAT6_CMP1_Msk (0xfffful << PWM_CMPDAT6_CMP1_Pos) 3PWM_CMPDAT6_CMP2_Pos (0) 3PWM_CMPDAT6_CMP2_Msk (0xfffful << PWM_CMPDAT6_CMP2_Pos) 3PWM_CMPDAT6_CMP3_Pos (0) 3PWM_CMPDAT6_CMP3_Msk (0xfffful << PWM_CMPDAT6_CMP3_Pos) 3PWM_CMPDAT6_CMP4_Pos (0) 3PWM_CMPDAT6_CMP4_Msk (0xfffful << PWM_CMPDAT6_CMP4_Pos) 3PWM_CMPDAT6_CMP5_Pos (0) 3PWM_CMPDAT6_CMP5_Msk (0xfffful << PWM_CMPDAT6_CMP5_Pos) 3PWM_CMPDAT6_CMP6_Pos (0) 3PWM_CMPDAT6_CMP6_Msk (0xfffful << PWM_CMPDAT6_CMP6_Pos) ¡3PWM_CMPDAT6_CMP7_Pos (0) ¢3PWM_CMPDAT6_CMP7_Msk (0xfffful << PWM_CMPDAT6_CMP7_Pos) ¤3PWM_CMPDAT6_CMPD0_Pos (16) ¥3PWM_CMPDAT6_CMPD0_Msk (0xfffful << PWM_CMPDAT6_CMPD0_Pos) §3PWM_CMPDAT6_CMPD1_Pos (16) ¨3PWM_CMPDAT6_CMPD1_Msk (0xfffful << PWM_CMPDAT6_CMPD1_Pos) ª3PWM_CMPDAT6_CMPD2_Pos (16) «3PWM_CMPDAT6_CMPD2_Msk (0xfffful << PWM_CMPDAT6_CMPD2_Pos) 3PWM_CMPDAT6_CMPD3_Pos (16) ®3PWM_CMPDAT6_CMPD3_Msk (0xfffful << PWM_CMPDAT6_CMPD3_Pos) °3PWM_CMPDAT6_CMPD4_Pos (16) ±3PWM_CMPDAT6_CMPD4_Msk (0xfffful << PWM_CMPDAT6_CMPD4_Pos) ³3PWM_CMPDAT6_CMPD5_Pos (16) ´3PWM_CMPDAT6_CMPD5_Msk (0xfffful << PWM_CMPDAT6_CMPD5_Pos) ¶3PWM_CMPDAT6_CMPD6_Pos (16) ·3PWM_CMPDAT6_CMPD6_Msk (0xfffful << PWM_CMPDAT6_CMPD6_Pos) ¹3PWM_CMPDAT6_CMPD7_Pos (16) º3PWM_CMPDAT6_CMPD7_Msk (0xfffful << PWM_CMPDAT6_CMPD7_Pos) ¼3PWM_CMPDAT7_CMP0_Pos (0) ½3PWM_CMPDAT7_CMP0_Msk (0xfffful << PWM_CMPDAT7_CMP0_Pos) ¿3PWM_CMPDAT7_CMP1_Pos (0) À3PWM_CMPDAT7_CMP1_Msk (0xfffful << PWM_CMPDAT7_CMP1_Pos) Â3PWM_CMPDAT7_CMP2_Pos (0) Ã3PWM_CMPDAT7_CMP2_Msk (0xfffful << PWM_CMPDAT7_CMP2_Pos) Å3PWM_CMPDAT7_CMP3_Pos (0) Æ3PWM_CMPDAT7_CMP3_Msk (0xfffful << PWM_CMPDAT7_CMP3_Pos) È3PWM_CMPDAT7_CMP4_Pos (0) É3PWM_CMPDAT7_CMP4_Msk (0xfffful << PWM_CMPDAT7_CMP4_Pos) Ë3PWM_CMPDAT7_CMP5_Pos (0) Ì3PWM_CMPDAT7_CMP5_Msk (0xfffful << PWM_CMPDAT7_CMP5_Pos) Î3PWM_CMPDAT7_CMP6_Pos (0) Ï3PWM_CMPDAT7_CMP6_Msk (0xfffful << PWM_CMPDAT7_CMP6_Pos) Ñ3PWM_CMPDAT7_CMP7_Pos (0) Ò3PWM_CMPDAT7_CMP7_Msk (0xfffful << PWM_CMPDAT7_CMP7_Pos) Ô3PWM_CMPDAT7_CMPD0_Pos (16) Õ3PWM_CMPDAT7_CMPD0_Msk (0xfffful << PWM_CMPDAT7_CMPD0_Pos) ×3PWM_CMPDAT7_CMPD1_Pos (16) Ø3PWM_CMPDAT7_CMPD1_Msk (0xfffful << PWM_CMPDAT7_CMPD1_Pos) Ú3PWM_CMPDAT7_CMPD2_Pos (16) Û3PWM_CMPDAT7_CMPD2_Msk (0xfffful << PWM_CMPDAT7_CMPD2_Pos) Ý3PWM_CMPDAT7_CMPD3_Pos (16) Þ3PWM_CMPDAT7_CMPD3_Msk (0xfffful << PWM_CMPDAT7_CMPD3_Pos) à3PWM_CMPDAT7_CMPD4_Pos (16) á3PWM_CMPDAT7_CMPD4_Msk (0xfffful << PWM_CMPDAT7_CMPD4_Pos) ã3PWM_CMPDAT7_CMPD5_Pos (16) ä3PWM_CMPDAT7_CMPD5_Msk (0xfffful << PWM_CMPDAT7_CMPD5_Pos) æ3PWM_CMPDAT7_CMPD6_Pos (16) ç3PWM_CMPDAT7_CMPD6_Msk (0xfffful << PWM_CMPDAT7_CMPD6_Pos) é3PWM_CMPDAT7_CMPD7_Pos (16) ê3PWM_CMPDAT7_CMPD7_Msk (0xfffful << PWM_CMPDAT7_CMPD7_Pos) ì3PWM_CTL2_BRKIEN_Pos (16) í3PWM_CTL2_BRKIEN_Msk (0x1ul << PWM_CTL2_BRKIEN_Pos) ï3PWM_CTL2_PINTTYPE_Pos (17) ð3PWM_CTL2_PINTTYPE_Msk (0x1ul << PWM_CTL2_PINTTYPE_Pos) ò3PWM_CTL2_DTCNT01_Pos (24) ó3PWM_CTL2_DTCNT01_Msk (0x1ul << PWM_CTL2_DTCNT01_Pos) õ3PWM_CTL2_DTCNT23_Pos (25) ö3PWM_CTL2_DTCNT23_Msk (0x1ul << PWM_CTL2_DTCNT23_Pos) ø3PWM_CTL2_DTCNT45_Pos (26) ù3PWM_CTL2_DTCNT45_Msk (0x1ul << PWM_CTL2_DTCNT45_Pos) û3PWM_CTL2_DTCNT67_Pos (27) ü3PWM_CTL2_DTCNT67_Msk (0x1ul << PWM_CTL2_DTCNT67_Pos) þ3PWM_CTL2_CNTCLR_Pos (27) ÿ3PWM_CTL2_CNTCLR_Msk (0x1ul << PWM_CTL2_CNTCLR_Pos) 4PWM_CTL2_MODE_Pos (28) 4PWM_CTL2_MODE_Msk (0x3ul << PWM_CTL2_MODE_Pos) 4PWM_CTL2_GROUPEN_Pos (30)
4PWM_CTL2_GROUPEN_Msk (0x1ul << PWM_CTL2_GROUPEN_Pos) 4PWM_CTL2_CNTTYPE_Pos (31) 4PWM_CTL2_CNTTYPE_Msk (0x1ul << PWM_CTL2_CNTTYPE_Pos) 4PWM_FLAG_ZF0_Pos (0) 4PWM_FLAG_ZF0_Msk (0x1ul << PWM_FLAG_ZF0_Pos) 4PWM_FLAG_ZF1_Pos (1) 4PWM_FLAG_ZF1_Msk (0x1ul << PWM_FLAG_ZF1_Pos) 4PWM_FLAG_ZF2_Pos (2) 4PWM_FLAG_ZF2_Msk (0x1ul << PWM_FLAG_ZF2_Pos) 4PWM_FLAG_ZF3_Pos (3) 4PWM_FLAG_ZF3_Msk (0x1ul << PWM_FLAG_ZF3_Pos) 4PWM_FLAG_ZF4_Pos (4) 4PWM_FLAG_ZF4_Msk (0x1ul << PWM_FLAG_ZF4_Pos) 4PWM_FLAG_ZF5_Pos (5) 4PWM_FLAG_ZF5_Msk (0x1ul << PWM_FLAG_ZF5_Pos) 4PWM_FLAG_ZF6_Pos (6) 4PWM_FLAG_ZF6_Msk (0x1ul << PWM_FLAG_ZF6_Pos) 4PWM_FLAG_ZF7_Pos (7) 4PWM_FLAG_ZF7_Msk (0x1ul << PWM_FLAG_ZF7_Pos) ¢4PWM_FLAG_CMPDF0_Pos (8) £4PWM_FLAG_CMPDF0_Msk (0x1ul << PWM_FLAG_CMPDF0_Pos) ¥4PWM_FLAG_CMPDF1_Pos (9) ¦4PWM_FLAG_CMPDF1_Msk (0x1ul << PWM_FLAG_CMPDF1_Pos) ¨4PWM_FLAG_CMPDF2_Pos (10) ©4PWM_FLAG_CMPDF2_Msk (0x1ul << PWM_FLAG_CMPDF2_Pos) «4PWM_FLAG_CMPDF3_Pos (11) ¬4PWM_FLAG_CMPDF3_Msk (0x1ul << PWM_FLAG_CMPDF3_Pos) ®4PWM_FLAG_CMPDF4_Pos (12) ¯4PWM_FLAG_CMPDF4_Msk (0x1ul << PWM_FLAG_CMPDF4_Pos) ±4PWM_FLAG_CMPDF5_Pos (13) ²4PWM_FLAG_CMPDF5_Msk (0x1ul << PWM_FLAG_CMPDF5_Pos) ´4PWM_FLAG_CMPDF6_Pos (14) µ4PWM_FLAG_CMPDF6_Msk (0x1ul << PWM_FLAG_CMPDF6_Pos) ·4PWM_FLAG_CMPDF7_Pos (15) ¸4PWM_FLAG_CMPDF7_Msk (0x1ul << PWM_FLAG_CMPDF7_Pos) º4PWM_FLAG_PF0_Pos (16) »4PWM_FLAG_PF0_Msk (0x1ul << PWM_FLAG_PF0_Pos) ½4PWM_FLAG_PF1_Pos (17) ¾4PWM_FLAG_PF1_Msk (0x1ul << PWM_FLAG_PF1_Pos) À4PWM_FLAG_PF2_Pos (18) Á4PWM_FLAG_PF2_Msk (0x1ul << PWM_FLAG_PF2_Pos) Ã4PWM_FLAG_PF3_Pos (19) Ä4PWM_FLAG_PF3_Msk (0x1ul << PWM_FLAG_PF3_Pos) Æ4PWM_FLAG_PF4_Pos (20) Ç4PWM_FLAG_PF4_Msk (0x1ul << PWM_FLAG_PF4_Pos) É4PWM_FLAG_PF5_Pos (21) Ê4PWM_FLAG_PF5_Msk (0x1ul << PWM_FLAG_PF5_Pos) Ì4PWM_FLAG_PF6_Pos (22) Í4PWM_FLAG_PF6_Msk (0x1ul << PWM_FLAG_PF6_Pos) Ï4PWM_FLAG_PF7_Pos (23) Ð4PWM_FLAG_PF7_Msk (0x1ul << PWM_FLAG_PF7_Pos) Ò4PWM_FLAG_CMPUF0_Pos (24) Ó4PWM_FLAG_CMPUF0_Msk (0x1ul << PWM_FLAG_CMPUF0_Pos) Õ4PWM_FLAG_CMPUF1_Pos (25) Ö4PWM_FLAG_CMPUF1_Msk (0x1ul << PWM_FLAG_CMPUF1_Pos) Ø4PWM_FLAG_CMPUF2_Pos (26) Ù4PWM_FLAG_CMPUF2_Msk (0x1ul << PWM_FLAG_CMPUF2_Pos) Û4PWM_FLAG_CMPUF3_Pos (27) Ü4PWM_FLAG_CMPUF3_Msk (0x1ul << PWM_FLAG_CMPUF3_Pos) Þ4PWM_FLAG_CMPUF4_Pos (28) ß4PWM_FLAG_CMPUF4_Msk (0x1ul << PWM_FLAG_CMPUF4_Pos) á4PWM_FLAG_CMPUF5_Pos (29) â4PWM_FLAG_CMPUF5_Msk (0x1ul << PWM_FLAG_CMPUF5_Pos) ä4PWM_FLAG_CMPUF6_Pos (30) å4PWM_FLAG_CMPUF6_Msk (0x1ul << PWM_FLAG_CMPUF6_Pos) ç4PWM_FLAG_CMPUF7_Pos (31) è4PWM_FLAG_CMPUF7_Msk (0x1ul << PWM_FLAG_CMPUF7_Pos) ê4PWM_INTEN_ZIEN0_Pos (0) ë4PWM_INTEN_ZIEN0_Msk (0x1ul << PWM_INTEN_ZIEN0_Pos) í4PWM_INTEN_ZIEN1_Pos (1) î4PWM_INTEN_ZIEN1_Msk (0x1ul << PWM_INTEN_ZIEN1_Pos) ð4PWM_INTEN_ZIEN2_Pos (2) ñ4PWM_INTEN_ZIEN2_Msk (0x1ul << PWM_INTEN_ZIEN2_Pos) ó4PWM_INTEN_ZIEN3_Pos (3) ô4PWM_INTEN_ZIEN3_Msk (0x1ul << PWM_INTEN_ZIEN3_Pos) ö4PWM_INTEN_ZIEN4_Pos (4) ÷4PWM_INTEN_ZIEN4_Msk (0x1ul << PWM_INTEN_ZIEN4_Pos) ù4PWM_INTEN_ZIEN5_Pos (5) ú4PWM_INTEN_ZIEN5_Msk (0x1ul << PWM_INTEN_ZIEN5_Pos) ý4PWM_INTEN_ZIEN6_Pos (6) þ4PWM_INTEN_ZIEN6_Msk (0x1ul << PWM_INTEN_ZIEN6_Pos) 5PWM_INTEN_ZIEN7_Pos (7) 5PWM_INTEN_ZIEN7_Msk (0x1ul << PWM_INTEN_ZIEN7_Pos) 5PWM_INTEN_CMPDIEN0_Pos (8)
5PWM_INTEN_CMPDIEN0_Msk (0x1ul << PWM_INTEN_CMPDIEN0_Pos) 5PWM_INTEN_CMPDIEN1_Pos (9) 5PWM_INTEN_CMPDIEN1_Msk (0x1ul << PWM_INTEN_CMPDIEN1_Pos) 5PWM_INTEN_CMPDIEN2_Pos (10) 5PWM_INTEN_CMPDIEN2_Msk (0x1ul << PWM_INTEN_CMPDIEN2_Pos) 5PWM_INTEN_CMPDIEN3_Pos (11) 5PWM_INTEN_CMPDIEN3_Msk (0x1ul << PWM_INTEN_CMPDIEN3_Pos) 5PWM_INTEN_CMPDIEN4_Pos (12) 5PWM_INTEN_CMPDIEN4_Msk (0x1ul << PWM_INTEN_CMPDIEN4_Pos) 5PWM_INTEN_CMPDIEN5_Pos (13) 5PWM_INTEN_CMPDIEN5_Msk (0x1ul << PWM_INTEN_CMPDIEN5_Pos) 5PWM_INTEN_CMPDIEN6_Pos (14) 5PWM_INTEN_CMPDIEN6_Msk (0x1ul << PWM_INTEN_CMPDIEN6_Pos) 5PWM_INTEN_CMPDIEN7_Pos (15) 5PWM_INTEN_CMPDIEN7_Msk (0x1ul << PWM_INTEN_CMPDIEN7_Pos) 5PWM_INTEN_PIEN0_Pos (16) 5PWM_INTEN_PIEN0_Msk (0x1ul << PWM_INTEN_PIEN0_Pos) 5PWM_INTEN_PIEN1_Pos (17) ¡5PWM_INTEN_PIEN1_Msk (0x1ul << PWM_INTEN_PIEN1_Pos) £5PWM_INTEN_PIEN2_Pos (18) ¤5PWM_INTEN_PIEN2_Msk (0x1ul << PWM_INTEN_PIEN2_Pos) ¦5PWM_INTEN_PIEN3_Pos (19) §5PWM_INTEN_PIEN3_Msk (0x1ul << PWM_INTEN_PIEN3_Pos) ©5PWM_INTEN_PIEN4_Pos (20) ª5PWM_INTEN_PIEN4_Msk (0x1ul << PWM_INTEN_PIEN4_Pos) ¬5PWM_INTEN_PIEN5_Pos (21) 5PWM_INTEN_PIEN5_Msk (0x1ul << PWM_INTEN_PIEN5_Pos) °5PWM_INTEN_PIEN6_Pos (22) ±5PWM_INTEN_PIEN6_Msk (0x1ul << PWM_INTEN_PIEN6_Pos) ´5PWM_INTEN_PIEN7_Pos (23) µ5PWM_INTEN_PIEN7_Msk (0x1ul << PWM_INTEN_PIEN7_Pos) ·5PWM_INTEN_CMPUIEN0_Pos (24) ¸5PWM_INTEN_CMPUIEN0_Msk (0x1ul << PWM_INTEN_CMPUIEN0_Pos) º5PWM_INTEN_CMPUIEN1_Pos (25) »5PWM_INTEN_CMPUIEN1_Msk (0x1ul << PWM_INTEN_CMPUIEN1_Pos) ½5PWM_INTEN_CMPUIEN2_Pos (26) ¾5PWM_INTEN_CMPUIEN2_Msk (0x1ul << PWM_INTEN_CMPUIEN2_Pos) À5PWM_INTEN_CMPUIEN3_Pos (27) Á5PWM_INTEN_CMPUIEN3_Msk (0x1ul << PWM_INTEN_CMPUIEN3_Pos) Ã5PWM_INTEN_CMPUIEN4_Pos (28) Ä5PWM_INTEN_CMPUIEN4_Msk (0x1ul << PWM_INTEN_CMPUIEN4_Pos) Æ5PWM_INTEN_CMPUIEN5_Pos (29) Ç5PWM_INTEN_CMPUIEN5_Msk (0x1ul << PWM_INTEN_CMPUIEN5_Pos) É5PWM_INTEN_CMPUIEN6_Pos (30) Ê5PWM_INTEN_CMPUIEN6_Msk (0x1ul << PWM_INTEN_CMPUIEN6_Pos) Ì5PWM_INTEN_CMPUIEN7_Pos (31) Í5PWM_INTEN_CMPUIEN7_Msk (0x1ul << PWM_INTEN_CMPUIEN7_Pos) Ï5PWM_INTSTS_ZIF0_Pos (0) Ð5PWM_INTSTS_ZIF0_Msk (0x1ul << PWM_INTSTS_ZIF0_Pos) Ò5PWM_INTSTS_ZIF1_Pos (1) Ó5PWM_INTSTS_ZIF1_Msk (0x1ul << PWM_INTSTS_ZIF1_Pos) Õ5PWM_INTSTS_ZIF2_Pos (2) Ö5PWM_INTSTS_ZIF2_Msk (0x1ul << PWM_INTSTS_ZIF2_Pos) Ø5PWM_INTSTS_ZIF3_Pos (3) Ù5PWM_INTSTS_ZIF3_Msk (0x1ul << PWM_INTSTS_ZIF3_Pos) Û5PWM_INTSTS_ZIF4_Pos (4) Ü5PWM_INTSTS_ZIF4_Msk (0x1ul << PWM_INTSTS_ZIF4_Pos) Þ5PWM_INTSTS_ZIF5_Pos (5) ß5PWM_INTSTS_ZIF5_Msk (0x1ul << PWM_INTSTS_ZIF5_Pos) á5PWM_INTSTS_ZIF6_Pos (6) â5PWM_INTSTS_ZIF6_Msk (0x1ul << PWM_INTSTS_ZIF6_Pos) ä5PWM_INTSTS_ZIF7_Pos (7) å5PWM_INTSTS_ZIF7_Msk (0x1ul << PWM_INTSTS_ZIF7_Pos) ç5PWM_INTSTS_CMPDIF0_Pos (8) è5PWM_INTSTS_CMPDIF0_Msk (0x1ul << PWM_INTSTS_CMPDIF0_Pos) ê5PWM_INTSTS_CMPDIF1_Pos (9) ë5PWM_INTSTS_CMPDIF1_Msk (0x1ul << PWM_INTSTS_CMPDIF1_Pos) í5PWM_INTSTS_CMPDIF2_Pos (10) î5PWM_INTSTS_CMPDIF2_Msk (0x1ul << PWM_INTSTS_CMPDIF2_Pos) ð5PWM_INTSTS_CMPDIF3_Pos (11) ñ5PWM_INTSTS_CMPDIF3_Msk (0x1ul << PWM_INTSTS_CMPDIF3_Pos) ó5PWM_INTSTS_CMPDIF4_Pos (12) ô5PWM_INTSTS_CMPDIF4_Msk (0x1ul << PWM_INTSTS_CMPDIF4_Pos) ö5PWM_INTSTS_CMPDIF5_Pos (13) ÷5PWM_INTSTS_CMPDIF5_Msk (0x1ul << PWM_INTSTS_CMPDIF5_Pos) ù5PWM_INTSTS_CMPDIF6_Pos (14) ú5PWM_INTSTS_CMPDIF6_Msk (0x1ul << PWM_INTSTS_CMPDIF6_Pos) ü5PWM_INTSTS_CMPDIF7_Pos (15) ý5PWM_INTSTS_CMPDIF7_Msk (0x1ul << PWM_INTSTS_CMPDIF7_Pos) ÿ5PWM_INTSTS_PIF0_Pos (16) 6PWM_INTSTS_PIF0_Msk (0x1ul << PWM_INTSTS_PIF0_Pos) 6PWM_INTSTS_PIF1_Pos (17) 6PWM_INTSTS_PIF1_Msk (0x1ul << PWM_INTSTS_PIF1_Pos)
6PWM_INTSTS_PIF2_Pos (18) 6PWM_INTSTS_PIF2_Msk (0x1ul << PWM_INTSTS_PIF2_Pos) 6PWM_INTSTS_PIF3_Pos (19) 6PWM_INTSTS_PIF3_Msk (0x1ul << PWM_INTSTS_PIF3_Pos) 6PWM_INTSTS_PIF4_Pos (20) 6PWM_INTSTS_PIF4_Msk (0x1ul << PWM_INTSTS_PIF4_Pos) 6PWM_INTSTS_PIF5_Pos (21) 6PWM_INTSTS_PIF5_Msk (0x1ul << PWM_INTSTS_PIF5_Pos) 6PWM_INTSTS_PIF6_Pos (22) 6PWM_INTSTS_PIF6_Msk (0x1ul << PWM_INTSTS_PIF6_Pos) 6PWM_INTSTS_PIF7_Pos (23) 6PWM_INTSTS_PIF7_Msk (0x1ul << PWM_INTSTS_PIF7_Pos) 6PWM_INTSTS_CMPUIF0_Pos (24) 6PWM_INTSTS_CMPUIF0_Msk (0x1ul << PWM_INTSTS_CMPUIF0_Pos) 6PWM_INTSTS_CMPUIF1_Pos (25) 6PWM_INTSTS_CMPUIF1_Msk (0x1ul << PWM_INTSTS_CMPUIF1_Pos) 6PWM_INTSTS_CMPUIF2_Pos (26) 6PWM_INTSTS_CMPUIF2_Msk (0x1ul << PWM_INTSTS_CMPUIF2_Pos) 6PWM_INTSTS_CMPUIF3_Pos (27) ¡6PWM_INTSTS_CMPUIF3_Msk (0x1ul << PWM_INTSTS_CMPUIF3_Pos) £6PWM_INTSTS_CMPUIF4_Pos (28) ¤6PWM_INTSTS_CMPUIF4_Msk (0x1ul << PWM_INTSTS_CMPUIF4_Pos) ¦6PWM_INTSTS_CMPUIF5_Pos (29) §6PWM_INTSTS_CMPUIF5_Msk (0x1ul << PWM_INTSTS_CMPUIF5_Pos) ©6PWM_INTSTS_CMPUIF6_Pos (30) ª6PWM_INTSTS_CMPUIF6_Msk (0x1ul << PWM_INTSTS_CMPUIF6_Pos) ¬6PWM_INTSTS_CMPUIF7_Pos (31) 6PWM_INTSTS_CMPUIF7_Msk (0x1ul << PWM_INTSTS_CMPUIF7_Pos) ¯6PWM_POEN_POEN0_Pos (0) °6PWM_POEN_POEN0_Msk (0x1ul << PWM_POEN_POEN0_Pos) ²6PWM_POEN_POEN1_Pos (1) ³6PWM_POEN_POEN1_Msk (0x1ul << PWM_POEN_POEN1_Pos) µ6PWM_POEN_POEN2_Pos (2) ¶6PWM_POEN_POEN2_Msk (0x1ul << PWM_POEN_POEN2_Pos) ¸6PWM_POEN_POEN3_Pos (3) ¹6PWM_POEN_POEN3_Msk (0x1ul << PWM_POEN_POEN3_Pos) »6PWM_POEN_POEN4_Pos (4) ¼6PWM_POEN_POEN4_Msk (0x1ul << PWM_POEN_POEN4_Pos) ¾6PWM_POEN_POEN5_Pos (5) ¿6PWM_POEN_POEN5_Msk (0x1ul << PWM_POEN_POEN5_Pos) Á6PWM_POEN_POEN6_Pos (6) Â6PWM_POEN_POEN6_Msk (0x1ul << PWM_POEN_POEN4_Pos) Ä6PWM_POEN_POEN7_Pos (7) Å6PWM_POEN_POEN7_Msk (0x1ul << PWM_POEN_POEN7_Pos) Ç6PWM_BRKCTL_BRK0EN_Pos (0) È6PWM_BRKCTL_BRK0EN_Msk (0x1ul << PWM_BRKCTL_BRK0EN_Pos) Ê6PWM_BRKCTL_BRK1EN_Pos (1) Ë6PWM_BRKCTL_BRK1EN_Msk (0x1ul << PWM_BRKCTL_BRK1EN_Pos) Í6PWM_BRKCTL_BRK0SEL_Pos (2) Î6PWM_BRKCTL_BRK0SEL_Msk (0x1ul << PWM_BRKCTL_BRK0SEL_Pos) Ð6PWM_BRKCTL_BRK1SEL_Pos (3) Ñ6PWM_BRKCTL_BRK1SEL_Msk (0x1ul << PWM_BRKCTL_BRK1SEL_Pos) Ó6PWM_BRKCTL_BRKSTS_Pos (7) Ô6PWM_BRKCTL_BRKSTS_Msk (0x1ul << PWM_BRKCTL_BRKSTS_Pos) Ö6PWM_BRKCTL_BRKACT_Pos (8) ×6PWM_BRKCTL_BRKACT_Msk (0x1ul << PWM_BRKCTL_BRKACT_Pos) Ù6PWM_BRKCTL_SWBRK_Pos (9) Ú6PWM_BRKCTL_SWBRK_Msk (0x1ul << PWM_BRKCTL_SWBRK_Pos) Ü6PWM_BRKCTL_BRKIF0_Pos (16) Ý6PWM_BRKCTL_BRKIF0_Msk (0x1ul << PWM_BRKCTL_BRKIF0_Pos) ß6PWM_BRKCTL_BRKIF1_Pos (17) à6PWM_BRKCTL_BRKIF1_Msk (0x1ul << PWM_BRKCTL_BRKIF1_Pos) â6PWM_BRKCTL_BRKF0_Pos (18) ã6PWM_BRKCTL_BRKF0_Msk (0x1ul << PWM_BRKCTL_BRKF0_Pos) å6PWM_BRKCTL_BRKF1_Pos (19) æ6PWM_BRKCTL_BRKF1_Msk (0x1ul << PWM_BRKCTL_BRKF1_Pos) è6PWM_BRKCTL_BKOD0_Pos (24) é6PWM_BRKCTL_BKOD0_Msk (0x1ul << PWM_BRKCTL_BKOD0_Pos) ë6PWM_BRKCTL_BKOD1_Pos (25) ì6PWM_BRKCTL_BKOD1_Msk (0x1ul << PWM_BRKCTL_BKOD1_Pos) î6PWM_BRKCTL_BKOD2_Pos (26) ï6PWM_BRKCTL_BKOD2_Msk (0x1ul << PWM_BRKCTL_BKOD2_Pos) ñ6PWM_BRKCTL_BKOD3_Pos (27) ò6PWM_BRKCTL_BKOD3_Msk (0x1ul << PWM_BRKCTL_BKOD3_Pos) ô6PWM_BRKCTL_BKOD4_Pos (28) õ6PWM_BRKCTL_BKOD4_Msk (0x1ul << PWM_BRKCTL_BKOD4_Pos) ÷6PWM_BRKCTL_BKOD5_Pos (29) ø6PWM_BRKCTL_BKOD5_Msk (0x1ul << PWM_BRKCTL_BKOD5_Pos) ú6PWM_BRKCTL_D6BKOD_Pos (30) û6PWM_BRKCTL_D6BKOD_Msk (0x1ul << PWM_BRKCTL_D6BKOD_Pos) ý6PWM_BRKCTL_D7BKOD_Pos (31) þ6PWM_BRKCTL_D7BKOD_Msk (0x1ul << PWM_BRKCTL_D7BKOD_Pos) 7PWM_DTCTL_DTI01_Pos (0) 7PWM_DTCTL_DTI01_Msk (0xfful << PWM_DTCTL_DTI01_Pos) 7PWM_DTCTL_DTI23_Pos (8) 7PWM_DTCTL_DTI23_Msk (0xfful << PWM_DTCTL_DTI23_Pos) 7PWM_DTCTL_DTI45_Pos (16) 7PWM_DTCTL_DTI45_Msk (0xfful << PWM_DTCTL_DTI45_Pos) 7PWM_DTCTL_DTI67_Pos (24) 7PWM_DTCTL_DTI67_Msk (0xfful << PWM_DTCTL_DTI67_Pos) 7PWM_ADCTCTL0_CUTRGEN0_Pos (0) 7PWM_ADCTCTL0_CUTRGEN0_Msk (0x1ul << PWM_ADCTCTL0_CUTRGEN0_Pos) 7PWM_ADCTCTL0_CPTRGEN0_Pos (1) 7PWM_ADCTCTL0_CPTRGEN0_Msk (0x1ul << PWM_ADCTCTL0_CPTRGEN0_Pos) 7PWM_ADCTCTL0_CDTRGEN0_Pos (2) 7PWM_ADCTCTL0_CDTRGEN0_Msk (0x1ul << PWM_ADCTCTL0_CDTRGEN0_Pos) 7PWM_ADCTCTL0_ZPTRGEN0_Pos (3) 7PWM_ADCTCTL0_ZPTRGEN0_Msk (0x1ul << PWM_ADCTCTL0_ZPTRGEN0_Pos) 7PWM_ADCTCTL0_CUTRGEN1_Pos (8) 7PWM_ADCTCTL0_CUTRGEN1_Msk (0x1ul << PWM_ADCTCTL0_CUTRGEN1_Pos) 7PWM_ADCTCTL0_CPTRGEN1_Pos (9) 7PWM_ADCTCTL0_CPTRGEN1_Msk (0x1ul << PWM_ADCTCTL0_CPTRGEN1_Pos) 7PWM_ADCTCTL0_CDTRGEN1_Pos (10) 7PWM_ADCTCTL0_CDTRGEN1_Msk (0x1ul << PWM_ADCTCTL0_CDTRGEN1_Pos) ¡7PWM_ADCTCTL0_ZPTRGEN1_Pos (11) ¢7PWM_ADCTCTL0_ZPTRGEN1_Msk (0x1ul << PWM_ADCTCTL0_ZPTRGEN1_Pos) ¤7PWM_ADCTCTL0_CUTRGEN2_Pos (16) ¥7PWM_ADCTCTL0_CUTRGEN2_Msk (0x1ul << PWM_ADCTCTL0_CUTRGEN2_Pos) §7PWM_ADCTCTL0_CPTRGEN2_Pos (17) ¨7PWM_ADCTCTL0_CPTRGEN2_Msk (0x1ul << PWM_ADCTCTL0_CPTRGEN2_Pos) ª7PWM_ADCTCTL0_CDTRGEN2_Pos (18) «7PWM_ADCTCTL0_CDTRGEN2_Msk (0x1ul << PWM_ADCTCTL0_CDTRGEN2_Pos) 7PWM_ADCTCTL0_ZPTRGEN2_Pos (19) ®7PWM_ADCTCTL0_ZPTRGEN2_Msk (0x1ul << PWM_ADCTCTL0_ZPTRGEN2_Pos) °7PWM_ADCTCTL0_CUTRGEN3_Pos (24) ±7PWM_ADCTCTL0_CUTRGEN3_Msk (0x1ul << PWM_ADCTCTL0_CUTRGEN3_Pos) ³7PWM_ADCTCTL0_CPTRGEN3_Pos (25) ´7PWM_ADCTCTL0_CPTRGEN3_Msk (0x1ul << PWM_ADCTCTL0_CPTRGEN3_Pos) ¶7PWM_ADCTCTL0_CDTRGEN3_Pos (26) ·7PWM_ADCTCTL0_CDTRGEN3_Msk (0x1ul << PWM_ADCTCTL0_CDTRGEN3_Pos) ¹7PWM_ADCTCTL0_ZPTRGEN3_Pos (27) º7PWM_ADCTCTL0_ZPTRGEN3_Msk (0x1ul << PWM_ADCTCTL0_ZPTRGEN3_Pos) ¼7PWM_ADCTCTL1_CUTRGEN4_Pos (0) ½7PWM_ADCTCTL1_CUTRGEN4_Msk (0x1ul << PWM_ADCTCTL1_CUTRGEN4_Pos) ¿7PWM_ADCTCTL1_CPTRGEN4_Pos (1) À7PWM_ADCTCTL1_CPTRGEN4_Msk (0x1ul << PWM_ADCTCTL1_CPTRGEN4_Pos) Â7PWM_ADCTCTL1_CDTRGEN4_Pos (2) Ã7PWM_ADCTCTL1_CDTRGEN4_Msk (0x1ul << PWM_ADCTCTL1_CDTRGEN4_Pos) Å7PWM_ADCTCTL1_ZPTRGEN4_Pos (3) Æ7PWM_ADCTCTL1_ZPTRGEN4_Msk (0x1ul << PWM_ADCTCTL1_ZPTRGEN4_Pos) È7PWM_ADCTCTL1_CUTRGEN5_Pos (8) É7PWM_ADCTCTL1_CUTRGEN5_Msk (0x1ul << PWM_ADCTCTL1_CUTRGEN5_Pos) Ë7PWM_ADCTCTL1_CPTRGEN5_Pos (9) Ì7PWM_ADCTCTL1_CPTRGEN5_Msk (0x1ul << PWM_ADCTCTL1_CPTRGEN5_Pos) Î7PWM_ADCTCTL1_CDTRGEN5_Pos (10) Ï7PWM_ADCTCTL1_CDTRGEN5_Msk (0x1ul << PWM_ADCTCTL1_CDTRGEN5_Pos) Ñ7PWM_ADCTCTL1_ZPTRGEN5_Pos (11) Ò7PWM_ADCTCTL1_ZPTRGEN5_Msk (0x1ul << PWM_ADCTCTL1_ZPTRGEN5_Pos) Ô7PWM_ADCTCTL1_CUTRGEN6_Pos (16) Õ7PWM_ADCTCTL1_CUTRGEN6_Msk (0x1ul << PWM_ADCTCTL1_CUTRGEN2_Pos) ×7PWM_ADCTCTL1_CPTRGEN6_Pos (17) Ø7PWM_ADCTCTL1_CPTRGEN6_Msk (0x1ul << PWM_ADCTCTL1_CPTRGEN2_Pos) Ú7PWM_ADCTCTL1_CDTRGEN6_Pos (18) Û7PWM_ADCTCTL1_CDTRGEN6_Msk (0x1ul << PWM_ADCTCTL1_CDTRGEN2_Pos) Ý7PWM_ADCTCTL1_ZPTRGEN6_Pos (19) Þ7PWM_ADCTCTL1_ZPTRGEN6_Msk (0x1ul << PWM_ADCTCTL1_ZPTRGEN2_Pos) à7PWM_ADCTCTL1_CUTRGEN7_Pos (24) á7PWM_ADCTCTL1_CUTRGEN7_Msk (0x1ul << PWM_ADCTCTL1_CUTRGEN7_Pos) ã7PWM_ADCTCTL1_CPTRGEN7_Pos (25) ä7PWM_ADCTCTL1_CPTRGEN7_Msk (0x1ul << PWM_ADCTCTL1_CPTRGEN7_Pos) æ7PWM_ADCTCTL1_CDTRGEN7_Pos (26) ç7PWM_ADCTCTL1_CDTRGEN7_Msk (0x1ul << PWM_ADCTCTL1_CDTRGEN7_Pos) é7PWM_ADCTCTL1_ZPTRGEN7_Pos (27) ê7PWM_ADCTCTL1_ZPTRGEN7_Msk (0x1ul << PWM_ADCTCTL1_ZPTRGEN7_Pos) ì7PWM_ADCTSTS0_CUTRGF0_Pos (0) í7PWM_ADCTSTS0_CUTRGF0_Msk (0x1ul << PWM_ADCTSTS0_CUTRGF0_Pos) ï7PWM_ADCTSTS0_CPTRGF0_Pos (1) ð7PWM_ADCTSTS0_CPTRGF0_Msk (0x1ul << PWM_ADCTSTS0_CPTRGF0_Pos) ò7PWM_ADCTSTS0_CDTRGF0_Pos (2) ó7PWM_ADCTSTS0_CDTRGF0_Msk (0x1ul << PWM_ADCTSTS0_CDTRGF0_Pos) õ7PWM_ADCTSTS0_ZPTRGF0_Pos (3) ö7PWM_ADCTSTS0_ZPTRGF0_Msk (0x1ul << PWM_ADCTSTS0_ZPTRGF0_Pos) ø7PWM_ADCTSTS0_CUTRGF1_Pos (8) ù7PWM_ADCTSTS0_CUTRGF1_Msk (0x1ul << PWM_ADCTSTS0_CUTRGF1_Pos) û7PWM_ADCTSTS0_CPTRGF1_Pos (9) ü7PWM_ADCTSTS0_CPTRGF1_Msk (0x1ul << PWM_ADCTSTS0_CPTRGF1_Pos) þ7PWM_ADCTSTS0_CDTRGF1_Pos (10) ÿ7PWM_ADCTSTS0_CDTRGF1_Msk (0x1ul << PWM_ADCTSTS0_CDTRGF1_Pos) 8PWM_ADCTSTS0_ZPTRGF1_Pos (11) 8PWM_ADCTSTS0_ZPTRGF1_Msk (0x1ul << PWM_ADCTSTS0_ZPTRGF1_Pos) 8PWM_ADCTSTS0_CUTRGF2_Pos (16)
8PWM_ADCTSTS0_CUTRGF2_Msk (0x1ul << PWM_ADCTSTS0_CUTRGF2_Pos) 8PWM_ADCTSTS0_CPTRGF2_Pos (17) 8PWM_ADCTSTS0_CPTRGF2_Msk (0x1ul << PWM_ADCTSTS0_CPTRGF2_Pos) 8PWM_ADCTSTS0_CDTRGF2_Pos (18) 8PWM_ADCTSTS0_CDTRGF2_Msk (0x1ul << PWM_ADCTSTS0_CDTRGF2_Pos) 8PWM_ADCTSTS0_ZPTRGF2_Pos (19) 8PWM_ADCTSTS0_ZPTRGF2_Msk (0x1ul << PWM_ADCTSTS0_ZPTRGF2_Pos) 8PWM_ADCTSTS0_CUTRGF3_Pos (24) 8PWM_ADCTSTS0_CUTRGF3_Msk (0x1ul << PWM_ADCTSTS0_CUTRGF3_Pos) 8PWM_ADCTSTS0_CPTRGF3_Pos (25) 8PWM_ADCTSTS0_CPTRGF3_Msk (0x1ul << PWM_ADCTSTS0_CPTRGF3_Pos) 8PWM_ADCTSTS0_CDTRGF3_Pos (26) 8PWM_ADCTSTS0_CDTRGF3_Msk (0x1ul << PWM_ADCTSTS0_CDTRGF3_Pos) 8PWM_ADCTSTS0_ZPTRGF3_Pos (27) 8PWM_ADCTSTS0_ZPTRGF3_Msk (0x1ul << PWM_ADCTSTS0_ZPTRGF3_Pos) 8PWM_ADCTSTS1_CUTRGF4_Pos (0) 8PWM_ADCTSTS1_CUTRGF4_Msk (0x1ul << PWM_ADCTSTS1_CUTRGF4_Pos) 8PWM_ADCTSTS1_CPTRGF4_Pos (1) 8PWM_ADCTSTS1_CPTRGF4_Msk (0x1ul << PWM_ADCTSTS1_CPTRGF4_Pos) ¢8PWM_ADCTSTS1_CDTRGF4_Pos (2) £8PWM_ADCTSTS1_CDTRGF4_Msk (0x1ul << PWM_ADCTSTS1_CDTRGF4_Pos) ¥8PWM_ADCTSTS1_ZPTRGF4_Pos (3) ¦8PWM_ADCTSTS1_ZPTRGF4_Msk (0x1ul << PWM_ADCTSTS1_ZPTRGF4_Pos) ¨8PWM_ADCTSTS1_CUTRGF5_Pos (8) ©8PWM_ADCTSTS1_CUTRGF5_Msk (0x1ul << PWM_ADCTSTS1_CUTRGF5_Pos) «8PWM_ADCTSTS1_CPTRGF5_Pos (9) ¬8PWM_ADCTSTS1_CPTRGF5_Msk (0x1ul << PWM_ADCTSTS1_CPTRGF5_Pos) ®8PWM_ADCTSTS1_CDTRGF5_Pos (10) ¯8PWM_ADCTSTS1_CDTRGF5_Msk (0x1ul << PWM_ADCTSTS1_CDTRGF5_Pos) ±8PWM_ADCTSTS1_ZPTRGF5_Pos (11) ²8PWM_ADCTSTS1_ZPTRGF5_Msk (0x1ul << PWM_ADCTSTS1_ZPTRGF5_Pos) µ8PWM_ADCTSTS1_CUTRGF6_Pos (16) ¶8PWM_ADCTSTS1_CUTRGF6_Msk (0x1ul << PWM_ADCTSTS7_CUTRGF6_Pos) ¸8PWM_ADCTSTS1_CPTRGF6_Pos (17) ¹8PWM_ADCTSTS1_CPTRGF6_Msk (0x1ul << PWM_ADCTSTS7_CPTRGF6_Pos) »8PWM_ADCTSTS1_CDTRGF6_Pos (18) ¼8PWM_ADCTSTS1_CDTRGF6_Msk (0x1ul << PWM_ADCTSTS7_CDTRGF6_Pos) ¾8PWM_ADCTSTS1_ZPTRGF6_Pos (19) ¿8PWM_ADCTSTS1_ZPTRGF6_Msk (0x1ul << PWM_ADCTSTS7_ZPTRGF6_Pos) Á8PWM_ADCTSTS1_CUTRGF7_Pos (24) Â8PWM_ADCTSTS1_CUTRGF7_Msk (0x1ul << PWM_ADCTSTS7_CUTRGF7_Pos) Ä8PWM_ADCTSTS1_CPTRGF7_Pos (25) Å8PWM_ADCTSTS1_CPTRGF7_Msk (0x1ul << PWM_ADCTSTS7_CPTRGF7_Pos) Ç8PWM_ADCTSTS1_CDTRGF7_Pos (26) È8PWM_ADCTSTS1_CDTRGF7_Msk (0x1ul << PWM_ADCTSTS7_CDTRGF7_Pos) Ê8PWM_ADCTSTS1_ZPTRGF7_Pos (27) Ë8PWM_ADCTSTS1_ZPTRGF7_Msk (0x1ul << PWM_ADCTSTS7_ZPTRGF7_Pos) Í8PWM_PCACTL_PCAEN_Pos (0) Î8PWM_PCACTL_PCAEN_Msk (0x1ul << PWM_PCACTL_PCAEN_Pos) ÷8FLCTL_CTL_BYTES_NUM_R_Pos (8) ø8FLCTL_CTL_BYTES_NUM_R_Msk (0xFFFFFFul << FLCTL_CTL_BYTES_NUM_R_Pos) ù8FLCTL_CTL_BYTES_NUM_W_Pos (0) ú8FLCTL_CTL_BYTES_NUM_W_Msk (0x7ul << FLCTL_CTL_BYTES_NUM_W_Pos) ý8FLCTL_TRIG_TRG_Pos (0) þ8FLCTL_TRIG_TRG_Msk (0x1ul << FLCTL_TRIG_TRG_Pos) 9FLCTL_CONFIG_FLASH_CAP_Pos (3) 9FLCTL_CONFIG_FLASH_CAP_Msk (0x7ul << FLCTL_CONFIG_FLASH_CAP_Pos) 9FLCTL_CONFIG_TX_ADDR_TRANS_Pos (2) 9FLCTL_CONFIG_TX_ADDR_TRANS_Msk (0x1ul << FLCTL_CONFIG_TX_ADDR_TRANS_Pos)
9FLCTL_CONFIG_INFO_EN_Pos (1) 9FLCTL_CONFIG_INFO_EN_Msk (0x1ul << FLCTL_CONFIG_INFO_EN_Pos) 9FLCTL_CONFIG_PP_ACTIVE_Pos (0) 9FLCTL_CONFIG_PP_ACTIVE_Msk (0x1ul << FLCTL_CONFIG_PP_ACTIVE_Pos) 9FLCTL_W_DATA_Pos (0) 9FLCTL_W_DATA_Msk (0xFFul << FLCTL_W_DATA_Pos) 9FLCTL_X_MODE_TIMEOUT_CNT_Pos (26) 9FLCTL_X_MODE_TIMEOUT_CNT_Msk (0x3Ful << FLCTL_X_MODE_TIMEOUT_CNT_Pos) 9FLCTL_X_MODE_RESUME_EN_Pos (25) 9FLCTL_X_MODE_RESUME_EN_Msk (0x1ul << FLCTL_X_MODE_RESUME_EN_Pos) 9FLCTL_X_MODE_SUS_SUCCESS_Pos (24) 9FLCTL_X_MODE_SUS_SUCCESS_Msk (0x1ul << FLCTL_X_MODE_SUS_SUCCESS_Pos) 9FLCTL_X_MODE_CLK_DLY_Pos (21) 9FLCTL_X_MODE_CLK_DLY_Msk (0x7ul << FLCTL_X_MODE_CLK_DLY_Pos) 9FLCTL_X_MODE_RX_NEG_Pos (20) 9FLCTL_X_MODE_RX_NEG_Msk (0x1ul << FLCTL_X_MODE_RX_NEG_Pos) 9FLCTL_X_MODE_CRC32_EN_Pos (19) 9FLCTL_X_MODE_CRC32_EN_Msk (0x1ul << FLCTL_X_MODE_CRC32_EN_Pos) 9FLCTL_X_MODE_ENHANCE_MODE_Pos (18) 9FLCTL_X_MODE_ENHANCE_MODE_Msk (0x1ul << FLCTL_X_MODE_ENHANCE_MODE_Pos) 9FLCTL_X_MODE_LONG_TIME_OP_Pos (17) 9FLCTL_X_MODE_LONG_TIME_OP_Msk (0x1ul << FLCTL_X_MODE_LONG_TIME_OP_Pos) 9FLCTL_X_MODE_EN_BURST_WRAP_Pos (16) ¡9FLCTL_X_MODE_EN_BURST_WRAP_Msk (0x1ul << FLCTL_X_MODE_EN_BURST_WRAP_Pos) ¢9FLCTL_X_MODE_CS_IDLE_CYCLE_Pos (8) £9FLCTL_X_MODE_CS_IDLE_CYCLE_Msk (0xFFul << FLCTL_X_MODE_CS_IDLE_CYCLE_Pos) ¤9FLCTL_X_MODE_X_MODE_Pos (0) ¥9FLCTL_X_MODE_X_MODE_Msk (0x3ul << FLCTL_X_MODE_X_MODE_Pos) ¨9FLCTL_X2_CMD_Pos (0) ©9FLCTL_X2_CMD_Msk (0xFFul << FLCTL_X2_CMD_Pos) ¬9FLCTL_X4_CMD_Pos (0) 9FLCTL_X4_CMD_Msk (0xFFul << FLCTL_X4_CMD_Pos) °9FLCTL_DP_CMD_Pos (0) ±9FLCTL_DP_CMD_Msk (0xFFul << FLCTL_DP_CMD_Pos) ´9FLCTL_RDP_CMD_Pos (0) µ9FLCTL_RDP_CMD_Msk (0xFFul << FLCTL_RDP_CMD_Pos) ¸9FLCTL_REMAP_ADDR_Pos (0) ¹9FLCTL_REMAP_ADDR_Msk (0xFFul << FLCTL_REMAP_ADDR_Pos) ¼9FLCTL_DP_CTL_RDP_WT_CNT_Pos (16) ½9FLCTL_DP_CTL_RDP_WT_CNT_Msk (0xFFFFul << FLCTL_DP_CTL_RDP_WT_CNT_Pos) ¾9FLCTL_DP_CTL_DP_WT_CNT_Pos (4) ¿9FLCTL_DP_CTL_DP_WT_CNT_Msk (0xFFFul << FLCTL_DP_CTL_DP_WT_CNT_Pos) À9FLCTL_DP_CTL_DP_EN_Pos (0) Á9FLCTL_DP_CTL_DP_EN_Msk (0x1ul << FLCTL_DP_CTL_DP_EN_Pos) Ä9FLCTL_PROGRAM_SUS_CMD_Pos (24) Å9FLCTL_PROGRAM_SUS_CMD_Msk (0xFFul << FLCTL_PROGRAM_SUS_CMD_Pos) Æ9FLCTL_PROGRAM_RESUME_CMD_Pos (16) Ç9FLCTL_PROGRAM_RESUME_CMD_Msk (0xFFul << FLCTL_PROGRAM_RESUME_CMD_Pos) È9FLCTL_ERASE_SUS_CMD_Pos (8) É9FLCTL_ERASE_SUS_CMD_Msk (0xFFul << FLCTL_ERASE_SUS_CMD_Pos) Ê9FLCTL_ERASE_RESUME_CMD_Pos (0) Ë9FLCTL_ERASE_RESUME_CMD_Msk (0xFFul << FLCTL_ERASE_RESUME_CMD_Pos) ò9SPI_CR0_SCR_Pos (8) ó9SPI_CR0_SCR_Msk (0xFFul << SPI_CR0_SCR_Pos) õ9SPI_CR0_SPH_Pos (7) ö9SPI_CR0_SPH_Msk (0x1ul << SPI_CR0_SPH_Pos) ø9SPI_CR0_SPO_Pos (6) ù9SPI_CR0_SPO_Msk (0x1ul << SPI_CR0_SPO_Pos) û9SPI_CR0_FRF_Pos (4) ü9SPI_CR0_FRF_Msk (0x3ul << SPI_CR0_FRF_Pos) þ9SPI_CR0_DSS_Pos (0) ÿ9SPI_CR0_DSS_Msk (0xFul << SPI_CR0_DSS_Pos) :SPI_CR1_SPI_MODE_SEL_Pos (10) :SPI_CR1_SPI_MODE_SEL_Msk (0x1ul << SPI_CR1_SPI_MODE_SEL_Pos) :SPI_CR1_CMD_DAT_EN_Pos (9) :SPI_CR1_CMD_DAT_EN_Msk (0x1ul << SPI_CR1_CMD_DAT_EN_Pos)
:SPI_CR1_CMD_DAT_CTRL_Pos (8) :SPI_CR1_CMD_DAT_CTRL_Msk (0x1ul << SPI_CR1_CMD_DAT_CTRL_Pos) :SPI_CR1_WR_CTRL_Pos (7) :SPI_CR1_WR_CTRL_Msk (0x1ul << SPI_CR1_WR_CTRL_Pos) :SPI_CR1_RX_LSB_EN_Pos (5) :SPI_CR1_RX_LSB_EN_Msk (0x1ul << SPI_CR1_RX_LSB_EN_Pos) :SPI_CR1_TX_LSB_EN_Pos (4) :SPI_CR1_TX_LSB_EN_Msk (0x1ul << SPI_CR1_TX_LSB_EN_Pos) :SPI_CR1_SOD_Pos (3) :SPI_CR1_SOD_Msk (0x1ul << SPI_CR1_SOD_Pos) :SPI_CR1_MS_Pos (2) :SPI_CR1_MS_Msk (0x1ul << SPI_CR1_MS_Pos) :SPI_CR1_SSE_Pos (1) :SPI_CR1_SSE_Msk (0x1ul << SPI_CR1_SSE_Pos) :SPI_CR1_LBM_Pos (0) :SPI_CR1_LBM_Msk (0x1ul << SPI_CR1_LBM_Pos) :SPI_DR_Pos (0) :SPI_DR_Msk (0xFFul << SPI_DR_Pos) :SPI_SR_BUSY_Pos (4) ¡:SPI_SR_BUSY_Msk (0x1ul << SPI_SR_BUSY_Pos) £:SPI_SR_RFF_Pos (3) ¤:SPI_SR_RFF_Msk (0x1ul << SPI_SR_RFF_Pos) ¦:SPI_SR_RFNE_Pos (2) §:SPI_SR_RFNE_Msk (0x1ul << SPI_SR_RFNE_Pos) ©:SPI_SR_TFNF_Pos (1) ª:SPI_SR_TFNF_Msk (0x1ul << SPI_SR_TFNF_Pos) ¬:SPI_SR_TFE_Pos (0) :SPI_SR_TFE_Msk (0x1ul << SPI_SR_TFE_Pos) °:SPI_CPSR_DIV_Pos (0) ±:SPI_CPSR_DIV_Msk (0xFul << SPI_CPSR_DIV_Pos) ´:SPI_IMSC_TXIM_Pos (3) µ:SPI_IMSC_TXIM_Msk (0x1ul << SPI_IMSC_TXIM_Pos) ·:SPI_IMSC_RXIM_Pos (2) ¸:SPI_IMSC_RXIM_Msk (0x1ul << SPI_IMSC_RXIM_Pos) º:SPI_IMSC_RTIM_Pos (1) »:SPI_IMSC_RTIM_Msk (0x1ul << SPI_IMSC_RTIM_Pos) ¾:SPI_RIS_TXIS_Pos (3) ¿:SPI_RIS_TXIS_Msk (0x1ul << SPI_RIS_TXIS_Pos) Á:SPI_RIS_RXIS_Pos (2) Â:SPI_RIS_RXIS_Msk (0x1ul << SPI_RIS_RXIS_Pos) Ä:SPI_RIS_RTIS_Pos (1) Å:SPI_RIS_RTIS_Msk (0x1ul << SPI_RIS_RTIS_Pos) Ç:SPI_RIS_RORIS_Pos (0) È:SPI_RIS_RORIS_Msk (0x1ul << SPI_RIS_RORIS_Pos) Ê:SPI_MIS_TXMIS_Pos (3) Ë:SPI_MIS_TXMIS_Msk (0x1ul << SPI_MIS_TXMIS_Pos) Í:SPI_MIS_RXMIS_Pos (2) Î:SPI_MIS_RXMIS_Msk (0x1ul << SPI_MIS_RXMIS_Pos) Ð:SPI_MIS_RTMIS_Pos (1) Ñ:SPI_MIS_RTMIS_Msk (0x1ul << SPI_MIS_RTMIS_Pos) Ó:SPI_MIS_RORMIS_Pos (0) Ô:SPI_MIS_RORMIS_Msk (0x1ul << SPI_MIS_RORMIS_Pos) ×:SPI_ICR_RTICR_Pos (1) Ø:SPI_ICR_RTICR_Msk (0x1ul << SPI_ICR_RTICR_Pos) Ú:SPI_ICR_RORICR_Pos (0) Û:SPI_ICR_RORICR_Msk (0x1ul << SPI_ICR_RORICR_Pos) Þ:SPI_DMACR_TDMAE_Pos (1) ß:SPI_DMACR_TDMAE_Msk (0x1ul << SPI_DMACR_TDMAE_Pos) á:SPI_DMACR_RDMAE_Pos (0) â:SPI_DMACR_RDMAE_Msk (0x1ul << SPI_DMACR_RDMAE_Pos) >UART_RBR_MSB9_Pos (8) >UART_RBR_MSB9_Msk (0x1ul << UART_RBR_MSB9_Pos) >UART_RBR_DAT_Pos (0) >UART_RBR_DAT_Msk (0xfful << UART_RBR_DAT_Pos) >UART_THR_MSB9_Pos (8) >UART_THR_MSB9_Msk (0x1ul << UART_THR_MSB9_Pos) >UART_THR_DAT_Pos (0) >UART_THR_DAT_Msk (0xfful << UART_THR_DAT_Pos) >UART_DLH_Pos (0) ¡>UART_DLH_Msk (0xfful << UART_DLH_Pos) £>UART_DLL_Pos (0) ¤>UART_DLL_Msk (0xfful << UART_DLL_Pos) ¦>UART_IER_EPTI_Pos (7) §>UART_IER_EPTI_Msk (0x1ul << UART_IER_EPTI_Pos) ©>UART_IER_EMSI_Pos (3) ª>UART_IER_EMSI_Msk (0x1ul << UART_IER_EMSI_Pos) «>UART_IER_ERLSI_Pos (2) ¬>UART_IER_ERLSI_Msk (0x1ul << UART_IER_ERLSI_Pos) >UART_IER_ETHREI_Pos (1) ®>UART_IER_ETHREI_Msk (0x1ul << UART_IER_ETHREI_Pos) ¯>UART_IER_ERDAI_Pos (0) °>UART_IER_ERDAI_Msk (0x1ul << UART_IER_ERDAI_Pos) ²>UART_IER_ALL_IRQ_Pos (0) ³>UART_IER_ALL_IRQ_Msk (0xful << UART_IER_ALL_IRQ_Pos) µ>UART_IIR_FIFOSE_Pos (6) ¶>UART_IIR_FIFOSE_Msk (0x3ul << UART_IIR_FIFOSE_Pos) ¸>UART_IIR_IID_Pos (0) ¹>UART_IIR_IID_Msk (0xful << UART_IIR_IID_Pos) ¼>UART_FCR_RT_Pos (6) ½>UART_FCR_RT_Msk (0x3ul << UART_FCR_RT_Pos) ¾>UART_FCR_TET_Pos (4) ¿>UART_FCR_TET_Msk (0x3ul << UART_FCR_TET_Pos) À>UART_FCR_DMAM_Pos (3) Á>UART_FCR_DMAM_Msk (0x1ul << UART_FCR_DMAM_Pos) Â>UART_FCR_XFIFOR_Pos (2) Ã>UART_FCR_XFIFOR_Msk (0x1ul << UART_FCR_XFIFOR_Pos) Ä>UART_FCR_RFIFOR_Pos (1) Å>UART_FCR_RFIFOR_Msk (0x1ul << UART_FCR_RFIFOR_Pos) Æ>UART_FCR_FIFOE_Pos (0) Ç>UART_FCR_FIFOE_Msk (0x1ul << UART_FCR_FIFOE_Pos) Ê>UART_LCR_DLAB_Pos (7) Ë>UART_LCR_DLAB_Msk (0x1ul << UART_LCR_DLAB_Pos) Ì>UART_LCR_BC_Pos (6) Í>UART_LCR_BC_Msk (0x1ul << UART_LCR_BC_Pos) Î>UART_LCR_SP_Pos (5) Ï>UART_LCR_SP_Msk (0x1ul << UART_LCR_SP_Pos) Ð>UART_LCR_EPS_Pos (4) Ñ>UART_LCR_EPS_Msk (0x1ul << UART_LCR_EPS_Pos) Ò>UART_LCR_PEN_Pos (3) Ó>UART_LCR_PEN_Msk (0x1ul << UART_LCR_PEN_Pos) Ô>UART_LCR_STOP_Pos (2) Õ>UART_LCR_STOP_Msk (0x1ul << UART_LCR_STOP_Pos) Ö>UART_LCR_DLS_Pos (0) ×>UART_LCR_DLS_Msk (0x3ul << UART_LCR_DLS_Pos) Ú>UART_MCR_SIRE_Pos (6) Û>UART_MCR_SIRE_Msk (0x1ul << UART_MCR_SIRE_Pos) Ü>UART_MCR_AFCE_Pos (5) Ý>UART_MCR_AFCE_Msk (0x1ul << UART_MCR_AFCE_Pos) Þ>UART_MCR_LB_Pos (4) ß>UART_MCR_LB_Msk (0x1ul << UART_MCR_LB_Pos) à>UART_MCR_OUT2_Pos (3) á>UART_MCR_OUT2_Msk (0x1ul << UART_MCR_OUT2_Pos) â>UART_MCR_OUT1_Pos (2) ã>UART_MCR_OUT1_Msk (0x1ul << UART_MCR_OUT1_Pos) ä>UART_MCR_RTS_Pos (1) å>UART_MCR_RTS_Msk (0x1ul << UART_MCR_RTS_Pos) æ>UART_MCR_DTR_Pos (0) ç>UART_MCR_DTR_Msk (0x1ul << UART_MCR_DTR_Pos) ê>UART_LSR_ADDR_RCVD_Pos (8) ë>UART_LSR_ADDR_RCVD_Msk (0x1ul << UART_LSR_ADDR_RCVD_Pos) ì>UART_LSR_RFE_Pos (7) í>UART_LSR_RFE_Msk (0x1ul << UART_LSR_RFE_Pos) î>UART_LSR_TEMT_Pos (6) ï>UART_LSR_TEMT_Msk (0x1ul << UART_LSR_TEMT_Pos) ð>UART_LSR_THRE_Pos (5) ñ>UART_LSR_THRE_Msk (0x1ul << UART_LSR_THRE_Pos) ò>UART_LSR_BI_Pos (4) ó>UART_LSR_BI_Msk (0x1ul << UART_LSR_BI_Pos) ô>UART_LSR_FE_Pos (3) õ>UART_LSR_FE_Msk (0x1ul << UART_LSR_FE_Pos) ö>UART_LSR_PE_Pos (2) ÷>UART_LSR_PE_Msk (0x1ul << UART_LSR_PE_Pos) ø>UART_LSR_OE_Pos (1) ù>UART_LSR_OE_Msk (0x1ul << UART_LSR_OE_Pos) ú>UART_LSR_DR_Pos (0) û>UART_LSR_DR_Msk (0x1ul << UART_LSR_DR_Pos) ý>UART_LSR_LINE_STATUS_Pos (0) þ>UART_LSR_LINE_STATUS_Msk (0x1FFul << UART_LSR_LINE_STATUS_Pos) ?UART_MSR_DCD_Pos (7) ?UART_MSR_DCD_Msk (0x1ul << UART_MSR_DCD_Pos) ?UART_MSR_RI_Pos (6) ?UART_MSR_RI_Msk (0x1ul << UART_MSR_RI_Pos)
?UART_MSR_DSR_Pos (5) ?UART_MSR_DSR_Msk (0x1ul << UART_MSR_DSR_Pos) ?UART_MSR_CTS_Pos (4) ?UART_MSR_CTS_Msk (0x1ul << UART_MSR_CTS_Pos) ?UART_MSR_DDCD_Pos (3) ?UART_MSR_DDCD_Msk (0x1ul << UART_MSR_DDCD_Pos) ?UART_MSR_TERI_Pos (2) ?UART_MSR_TERI_Msk (0x1ul << UART_MSR_TERI_Pos) ?UART_MSR_DDSR_Pos (1) ?UART_MSR_DDSR_Msk (0x1ul << UART_MSR_DDSR_Pos) ?UART_MSR_DCTS_Pos (0) ?UART_MSR_DCTS_Msk (0x1ul << UART_MSR_DCTS_Pos) ?UART_MSR_MODEM_STATUS_Pos (0) ?UART_MSR_MODEM_STATUS_Msk (0xFFul << UART_MSR_MODEM_STATUS_Pos) ?UART_SCR_Pos (0) ?UART_SCR_Msk (0xFFFFFFFFul << UART_SCR_Pos) ?UART_LPDLL_Pos (0) ?UART_LPDLL_Msk (0xFFul << UART_LPDLL_Pos) ?UART_LPDLH_Pos (0) ?UART_LPDLH_Msk (0xFFul << UART_LPDLH_Pos) ¢?UART_USR_RFF_Pos (4) £?UART_USR_RFF_Msk (0x1ul << UART_USR_RFF_Pos) ¤?UART_USR_RFNE_Pos (3) ¥?UART_USR_RFNE_Msk (0x1ul << UART_USR_RFNE_Pos) ¦?UART_USR_TFE_Pos (2) §?UART_USR_TFE_Msk (0x1ul << UART_USR_TFE_Pos) ¨?UART_USR_TFNF_Pos (1) ©?UART_USR_TFNF_Msk (0x1ul << UART_USR_TFNF_Pos) ¬?UART_TFL_Pos (0) ?UART_TFL_Msk (0x1Ful << UART_TFL_Pos) °?UART_RFL_Pos (0) ±?UART_RFL_Msk (0x1Ful << UART_RFL_Pos) ´?UART_DMASA_Pos (0) µ?UART_DMASA_Msk (0x1ul << UART_DMASA_Pos) ¸?UART_DLF_Pos (0) ¹?UART_DLF_Msk (0xFul << UART_DLF_Pos) ¼?UART_RAR_Pos (0) ½?UART_RAR_Msk (0xFFul << UART_RAR_Pos) À?UART_TAR_Pos (0) Á?UART_TAR_Msk (0xFFul << UART_TAR_Pos) Æ?UART_LCR_EXT_TRANSMIT_MODE_Pos (3) Ç?UART_LCR_EXT_TRANSMIT_MODE_Msk (0x1ul << UART_LCR_EXT_TRANSMIT_MODE_Pos) È?UART_LCR_EXT_SEND_ADDR_Pos (2) É?UART_LCR_EXT_SEND_ADDR_Msk (0x1ul << UART_LCR_EXT_SEND_ADDR_Pos) Ê?UART_LCR_EXT_ADDR_MATCH_Pos (1) Ë?UART_LCR_EXT_ADDR_MATCH_Msk (0x1ul << UART_LCR_EXT_ADDR_MATCH_Pos) Ì?UART_LCR_EXT_DLS_E_Pos (0) Í?UART_LCR_EXT_DLS_E_Msk (0x1ul << UART_LCR_EXT_DLS_E_Pos) Ø?UART_DR_OE ((uint32_t)0x00000800) Ù?UART_DR_BE ((uint32_t)0x00000400) Ú?UART_DR_PE ((uint32_t)0x00000200) Û?UART_DR_FE ((uint32_t)0x00000100) Ü?UART_DR_DATA ((uint32_t)0x000000FF) à?UART_RSCR_OE ((uint32_t)0x00000008) á?UART_RSCR_BE ((uint32_t)0x00000004) â?UART_RSCR_PE ((uint32_t)0x00000002) ã?UART_RSCR_FE ((uint32_t)0x00000001) å?UART_RSCR_CLR_ERR ((uint32_t)0x000000ff) ê?UART_STATUS_RI ((uint32_t)0x00000100) ë?UART_STATUS_TXFE ((uint32_t)0x00000080) ì?UART_STATUS_RXFF ((uint32_t)0x00000040) í?UART_STATUS_TXFF ((uint32_t)0x00000020) î?UART_STATUS_RXFE ((uint32_t)0x00000010) ï?UART_STATUS_BUSY ((uint32_t)0x00000008) ð?UART_STATUS_DCD ((uint32_t)0x00000004) ñ?UART_STATUS_DSR ((uint32_t)0x00000002) ò?UART_STATUS_CTS ((uint32_t)0x00000001) õ?UART_IRDA_LP_DIV ((uint32_t)0x000000FF) ø?UART_BRD_IBRD ((uint32_t)0x0000FFFF) û?UART_BRD_FBRD ((uint32_t)0x0000003F) þ?UART_LC_CLEAR_MSK ((uint32_t)0x000000FF) @UART_LC_SPS ((uint32_t)0x00000080) @UART_LC_WLEN ((uint32_t)0x00000060) @UART_LC_FEN ((uint32_t)0x00000010) @UART_LC_STP2 ((uint32_t)0x00000008) @UART_LC_EPS ((uint32_t)0x00000004)
@UART_LC_PEN ((uint32_t)0x00000002) @UART_LC_BRK ((uint32_t)0x00000001) @UART_CR_CLEAR_MSK ((uint32_t)0x0000FF87) @UART_CR_CTSEN ((uint32_t)0x00008000) @UART_CR_RTSEN ((uint32_t)0x00004000) @UART_CR_OUT2 ((uint32_t)0x00002000) @UART_CR_OUT1 ((uint32_t)0x00001000) @UART_CR_RTS ((uint32_t)0x00000800) @UART_CR_DTR ((uint32_t)0x00000400) @UART_CR_RXE ((uint32_t)0x00000200) @UART_CR_TXE ((uint32_t)0x00000100) @UART_CR_LBE ((uint32_t)0x00000080) @UART_CR_SIRLP ((uint32_t)0x00000004) @UART_CR_SIREN ((uint32_t)0x00000002) @UART_CR_UARTEN ((uint32_t)0x00000001) @UART_INT_FIFO_RXIFLSEL ((uint32_t)0x00000038) @UART_INT_FIFO_TXIFLSEL ((uint32_t)0x00000007) @UART_INT_MSK_OEIM ((uint32_t)0x00000400) @UART_INT_MSK_BEIM ((uint32_t)0x00000200) @UART_INT_MSK_PEIM ((uint32_t)0x00000100) @UART_INT_MSK_FEIM ((uint32_t)0x00000080) ¡@UART_INT_MSK_RTIM ((uint32_t)0x00000040) ¢@UART_INT_MSK_TXIM ((uint32_t)0x00000020) £@UART_INT_MSK_RXIM ((uint32_t)0x00000010) ¤@UART_INT_MSK_DSRMIM ((uint32_t)0x00000008) ¥@UART_INT_MSK_DCDMIM ((uint32_t)0x00000004) ¦@UART_INT_MSK_CTSMIM ((uint32_t)0x00000002) §@UART_INT_MSK_RIMIM ((uint32_t)0x00000001) ª@UART_RAW_INT_MSK_OEIM ((uint32_t)0x00000400) «@UART_RAW_INT_MSK_BEIM ((uint32_t)0x00000200) ¬@UART_RAW_INT_MSK_PEIM ((uint32_t)0x00000100) @UART_RAW_INT_MSK_FEIM ((uint32_t)0x00000080) ®@UART_RAW_INT_MSK_RTIM ((uint32_t)0x00000040) ¯@UART_RAW_INT_MSK_TXIM ((uint32_t)0x00000020) °@UART_RAW_INT_MSK_RXIM ((uint32_t)0x00000010) ±@UART_RAW_INT_MSK_DSRMIM ((uint32_t)0x00000008) ²@UART_RAW_INT_MSK_DCDMIM ((uint32_t)0x00000004) ³@UART_RAW_INT_MSK_CTSMIM ((uint32_t)0x00000002) ´@UART_RAW_INT_MSK_RIMIM ((uint32_t)0x00000001) ·@UART_MASKED_INT_STAT_OEIM ((uint32_t)0x00000400) ¸@UART_MASKED_INT_STAT_BEIM ((uint32_t)0x00000200) ¹@UART_MASKED_INT_STAT_PEIM ((uint32_t)0x00000100) º@UART_MASKED_INT_STAT_FEIM ((uint32_t)0x00000080) »@UART_MASKED_INT_STAT_RTIM ((uint32_t)0x00000040) ¼@UART_MASKED_INT_STAT_TXIM ((uint32_t)0x00000020) ½@UART_MASKED_INT_STAT_RXIM ((uint32_t)0x00000010) ¾@UART_MASKED_INT_STAT_DSRMIM ((uint32_t)0x00000008) ¿@UART_MASKED_INT_STAT_DCDMIM ((uint32_t)0x00000004) À@UART_MASKED_INT_STAT_CTSMIM ((uint32_t)0x00000002) Á@UART_MASKED_INT_STAT_RIMIM ((uint32_t)0x00000001) Ä@UART_CLR_INT_OEIM ((uint32_t)0x00000400) Å@UART_CLR_INT_BEIM ((uint32_t)0x00000200) Æ@UART_CLR_INT_PEIM ((uint32_t)0x00000100) Ç@UART_CLR_INT_FEIM ((uint32_t)0x00000080) È@UART_CLR_INT_RTIM ((uint32_t)0x00000040) É@UART_CLR_INT_TXIM ((uint32_t)0x00000020) Ê@UART_CLR_INT_RXIM ((uint32_t)0x00000010) Ë@UART_CLR_INT_DSRMIM ((uint32_t)0x00000008) Ì@UART_CLR_INT_DCDMIM ((uint32_t)0x00000004) Í@UART_CLR_INT_CTSMIM ((uint32_t)0x00000002) Î@UART_CLR_INT_RIMIM ((uint32_t)0x00000001) Ñ@UART_DMA_CR_DMAONERR ((uint32_t)0x00000004) Ò@UART_DMA_CR_TXDMAE ((uint32_t)0x00000002) Ó@UART_DMA_CR_RXDMAE ((uint32_t)0x00000001) ÎADMAC_DMACFGREG_L_DMA_EN_Pos (0) ÏADMAC_DMACFGREG_L_DMA_EN_Msk (0x1ul << DMAC_DMACFGREG_L_DMA_EN_Pos) ÑADMAC_CHENREG_L_CH_EN_Pos(ch) (ch) ÒADMAC_CHENREG_L_CH_EN_Msk(ch) (0x1ul << DMAC_CHENREG_L_CH_EN_Pos(ch)) ÔADMAC_CHENREG_L_CH_EN_ALL_Pos (0) ÕADMAC_CHENREG_L_CH_EN_ALL_Msk (0xfful << DMAC_CHENREG_L_CH_EN_ALL_Pos) ×ADMAC_CHENREG_L_CH_EN_WE_Pos(ch) ((ch)+8) ØADMAC_CHENREG_L_CH_EN_WE_Msk(ch) (0x1ul << DMAC_CHENREG_L_CH_EN_WE_Pos(ch)) ÚADMAC_CHENREG_L_CH_EN_WE_ALL_Pos (8) ÛADMAC_CHENREG_L_CH_EN_WE_ALL_Msk (0xfful << DMAC_CHENREG_L_CH_EN_WE_ALL_Pos) ÝADMAC_SAR_L_SAR_Pos (0) ÞADMAC_SAR_L_SAR_Msk (0xfffffffful << DMAC_SAR_L_SAR_Pos) àADMAC_DAR_L_DAR_Pos (0) áADMAC_DAR_L_DAR_Msk (0xfffffffful << DMAC_DAR_L_DAR_Pos) ãADMAC_CTL_L_INT_EN_Pos (0) äADMAC_CTL_L_INT_EN_Msk (0x1ul << DMAC_CTL_L_INT_EN_Pos) æADMAC_CTL_L_DST_TR_WIDTH_Pos (1) çADMAC_CTL_L_DST_TR_WIDTH_Msk (0x3ul << DMAC_CTL_L_DST_TR_WIDTH_Pos) éADMAC_CTL_L_SRC_TR_WIDTH_Pos (4) êADMAC_CTL_L_SRC_TR_WIDTH_Msk (0x3ul << DMAC_CTL_L_SRC_TR_WIDTH_Pos) ìADMAC_CTL_L_DINC_Pos (7) íADMAC_CTL_L_DINC_Msk (0x3ul << DMAC_CTL_L_DINC_Pos) ïADMAC_CTL_L_SINC_Pos (9) ðADMAC_CTL_L_SINC_Msk (0x3ul << DMAC_CTL_L_SINC_Pos) òADMAC_CTL_L_DEST_MSIZE_Pos (11) óADMAC_CTL_L_DEST_MSIZE_Msk (0x7ul << DMAC_CTL_L_DEST_MSIZE_Pos) õADMAC_CTL_L_SRC_MSIZE_Pos (14) öADMAC_CTL_L_SRC_MSIZE_Msk (0x7ul << DMAC_CTL_L_SRC_MSIZE_Pos) øADMAC_CTL_L_TT_FC_Pos (20) ùADMAC_CTL_L_TT_FC_Msk (0x7ul << DMAC_CTL_L_TT_FC_Pos) ûADMAC_CTL_H_BLOCK_TS_Pos (0) üADMAC_CTL_H_BLOCK_TS_Msk (0xffful << DMAC_CTL_H_BLOCK_TS_Pos) þADMAC_CTL_H_DONE_Pos (12) ÿADMAC_CTL_H_DONE_Msk (0x1ul << DMAC_CTL_H_DONE_Pos) BDMAC_CFG_L_CH_PRIOR_Pos (5) BDMAC_CFG_L_CH_PRIOR_Msk (0x7 << DMAC_CFG_L_CH_PRIOR_Pos) BDMAC_CFG_L_CH_SUSP_Pos (8)
BDMAC_CFG_L_CH_SUSP_Msk (0x1ul << DMAC_CFG_L_CH_SUSP_Pos) BDMAC_CFG_L_FIFO_EMPTY_Pos (9) BDMAC_CFG_L_FIFO_EMPTY_Msk (0x1ul << DMAC_CFG_L_FIFO_EMPTY_Pos) BDMAC_CFG_L_HS_SEL_DST_Pos (10) BDMAC_CFG_L_HS_SEL_DST_Msk (0x1ul << DMAC_CFG_L_HS_SEL_DST_Pos) BDMAC_CFG_L_HS_SEL_SRC_Pos (11) BDMAC_CFG_L_HS_SEL_SRC_Msk (0x1ul << DMAC_CFG_L_HS_SEL_SRC_Pos) BDMAC_CFG_L_DST_HS_POL_Pos (18) BDMAC_CFG_L_DST_HS_POL_Msk (0x1ul << DMAC_CFG_L_DST_HS_POL_Pos) BDMAC_CFG_L_SRC_HS_POL_Pos (19) BDMAC_CFG_L_SRC_HS_POL_Msk (0x1ul << DMAC_CFG_L_SRC_HS_POL_Pos) BDMAC_CFG_H_FCMODE_Pos (0) BDMAC_CFG_H_FCMODE_Msk (0x1ul << DMAC_CFG_H_FCMODE_Pos) BDMAC_CFG_H_FIFO_MODE_Pos (1) BDMAC_CFG_H_FIFO_MODE_Msk (0x1ul << DMAC_CFG_H_FIFO_MODE_Pos) BDMAC_CFG_H_PROTCTL_Pos (2) BDMAC_CFG_H_PROTCTL_Msk (0x7ul << DMAC_CFG_H_PROTCTL_Pos) ¢BDMAC_CFG_H_SRC_PER_Pos (7) £BDMAC_CFG_H_SRC_PER_Msk (0xful << DMAC_CFG_H_SRC_PER_Pos) ¥BDMAC_CFG_H_DEST_PER_Pos (11) ¦BDMAC_CFG_H_DEST_PER_Msk (0xful << DMAC_CFG_H_DEST_PER_Pos) ¨BDMAC_INT_RAW_STAT_CLR_Pos(ch) (ch) ©BDMAC_INT_RAW_STAT_CLR_Msk(ch) (0x1ul << DMAC_INT_RAW_STAT_CLR_Pos(ch)) «BDMAC_INT_RAW_STAT_CLR_ALL_Pos (0) ¬BDMAC_INT_RAW_STAT_CLR_ALL_Msk (0xfful << DMAC_INT_RAW_STAT_CLR_ALL_Pos) ®BDMAC_INT_MASK_L_Pos(ch) (ch) ¯BDMAC_INT_MASK_L_Msk(ch) (0x1ul << DMAC_INT_MASK_L_Pos(ch)) ±BDMAC_INT_MASK_L_ALL_Pos (0) ²BDMAC_INT_MASK_L_ALL_Msk (0xfful << DMAC_INT_MASK_L_ALL_Pos) ´BDMAC_INT_MASK_L_WE_Pos(ch) ((ch)+8) µBDMAC_INT_MASK_L_WE_Msk(ch) (0x1ul << DMAC_INT_MASK_L_WE_Pos(ch)) ·BDMAC_INT_MASK_L_WE_ALL_Pos (8) ¸BDMAC_INT_MASK_L_WE_ALL_Msk (0xfful << DMAC_INT_MASK_L_WE_ALL_Pos) ºBDMAC_STATUSINT_L_TFR_Pos (0) »BDMAC_STATUSINT_L_TFR_Msk (0x1ul << DMAC_STATUSINT_L_TFR_Pos) ½BDMAC_STATUSINT_L_BLOCK_Pos (1) ¾BDMAC_STATUSINT_L_BLOCK_Msk (0x1ul << DMAC_STATUSINT_L_BLOCK_Pos) ÀBDMAC_STATUSINT_L_SRCTRAN_Pos (2) ÁBDMAC_STATUSINT_L_SRCTRAN_Msk (0x1ul << DMAC_STATUSINT_L_SRCTRAN_Pos) ÃBDMAC_STATUSINT_L_DSTTRAN_Pos (3) ÄBDMAC_STATUSINT_L_DSTTRAN_Msk (0x1ul << DMAC_STATUSINT_L_DSTTRAN_Pos) ÆBDMAC_STATUSINT_L_ERR_Pos (4) ÇBDMAC_STATUSINT_L_ERR_Msk (0x1ul << DMAC_STATUSINT_L_ERR_Pos) CI2C_CON_MASTER_MODE ((uint16_t)0x0001) CI2C_CON_SPEED ((uint16_t)0x0006) CI2C_CON_SPEED_0 ((uint16_t)0x0002) CI2C_CON_SPEED_1 ((uint16_t)0x0004) CI2C_CON_IC_10BITADDR_SLAVE ((uint16_t)0x0008) CI2C_CON_IC_10BITADDR_MASTER ((uint16_t)0x0010) CI2C_CON_IC_RESTART_EN ((uint16_t)0x0020) CI2C_CON_IC_SLAVE_DISABLE ((uint16_t)0x0040) CI2C_CON_STOP_DET_IFADDRESSED ((uint16_t)0x0080) CI2C_CON_TX_EMPTY_CTRL ((uint16_t)0x0100) CI2C_TAR_TAR ((uint16_t)0x03ff) CI2C_TAR_IC_TAR_0 ((uint16_t)0x0001) CI2C_TAR_IC_TAR_1 ((uint16_t)0x0002) CI2C_TAR_IC_TAR_2 ((uint16_t)0x0004) CI2C_TAR_IC_TAR_3 ((uint16_t)0x0008) CI2C_TAR_IC_TAR_4 ((uint16_t)0x0010) CI2C_TAR_IC_TAR_5 ((uint16_t)0x0020) CI2C_TAR_IC_TAR_6 ((uint16_t)0x0040) CI2C_TAR_IC_TAR_7 ((uint16_t)0x0080) CI2C_TAR_IC_TAR_8 ((uint16_t)0x0100) ¡CI2C_TAR_IC_TAR_9 ((uint16_t)0x0200) £CI2C_TAR_GC_OR_START ((uint16_t)0x0400) ¤CI2C_TAR_SPECIAL ((uint16_t)0x0800) ¥CI2C_TAR_IC_10BITADDR_MASTER ((uint16_t)0x1000) ¨CI2C_SAR_IC_SAR ((uint16_t)0x03ff) ªCI2C_HS_MADDR_IC_HS_MAR ((uint16_t)0x0007) ¬CI2C_DATA_CMD_DAT ((uint16_t)0x00ff) CI2C_DATA_CMD_CMD_R ((uint16_t)0x0100) ®CI2C_DATA_CMD_STOP ((uint16_t)0x0200) ¯CI2C_DATA_CMD_RESTART ((uint16_t)0x0400) ²CI2C_SS_SCL_HCNT ((uint16_t)0xffff) µCI2C_SS_SCL_LCNT ((uint16_t)0xffff) ¸CI2C_FS_SCL_HCNT ((uint16_t)0xffff) »CI2C_FS_SCL_LCNT ((uint16_t)0xffff) ¾CI2C_HS_SCL_HCNT ((uint16_t)0xffff) ÁCI2C_HS_SCL_LCNT ((uint16_t)0xffff) ÄCI2C_INTR_STAT_R_RX_UNDER ((uint16_t)0x0001) ÅCI2C_INTR_STAT_R_RX_OVER ((uint16_t)0x0002) ÆCI2C_INTR_STAT_R_RX_FULL ((uint16_t)0x0004) ÇCI2C_INTR_STAT_R_TX_OVER ((uint16_t)0x0008) ÈCI2C_INTR_STAT_R_TX_EMPTY ((uint16_t)0x0010) ÉCI2C_INTR_STAT_R_RD_REQ ((uint16_t)0x0020) ÊCI2C_INTR_STAT_R_TX_ABRT ((uint16_t)0x0040) ËCI2C_INTR_STAT_R_RX_DONE ((uint16_t)0x0080) ÌCI2C_INTR_STAT_R_ACTIVITY ((uint16_t)0x0100) ÍCI2C_INTR_STAT_R_STOP_DET ((uint16_t)0x0200) ÎCI2C_INTR_STAT_R_START_DET ((uint16_t)0x0400) ÏCI2C_INTR_STAT_R_GEN_CALL ((uint16_t)0x0800) ÐCI2C_INTR_STAT_R_RESTART_DET ((uint16_t)0x1000) ÑCI2C_INTR_STAT_R_MST_ON_HOLD ((uint16_t)0x2000) ÕCI2C_INTR_MASK_M_RX_UNDER ((uint16_t)0x0001) ÖCI2C_INTR_MASK_M_RX_OVER ((uint16_t)0x0002) ×CI2C_INTR_MASK_M_RX_FULL ((uint16_t)0x0004) ØCI2C_INTR_MASK_M_TX_OVER ((uint16_t)0x0008) ÙCI2C_INTR_MASK_M_TX_EMPTY ((uint16_t)0x0010) ÚCI2C_INTR_MASK_M_RD_REQ ((uint16_t)0x0020) ÛCI2C_INTR_MASK_M_TX_ABRT ((uint16_t)0x0040) ÜCI2C_INTR_MASK_M_RX_DONE ((uint16_t)0x0080) ÝCI2C_INTR_MASK_M_ACTIVITY ((uint16_t)0x0100) ÞCI2C_INTR_MASK_M_STOP_DET ((uint16_t)0x0200) ßCI2C_INTR_MASK_M_START_DET ((uint16_t)0x0400) àCI2C_INTR_MASK_M_GEN_CALL ((uint16_t)0x0800) áCI2C_INTR_MASK_M_RESTART_DET ((uint16_t)0x1000) âCI2C_INTR_MASK_M_MST_ON_HOLD ((uint16_t)0x2000) åCI2C_RAW_INTR_STAT_RX_UNDER ((uint16_t)0x0001) æCI2C_RAW_INTR_STAT_RX_OVER ((uint16_t)0x0002) çCI2C_RAW_INTR_STAT_RX_FULL ((uint16_t)0x0004) èCI2C_RAW_INTR_STAT_TX_OVER ((uint16_t)0x0008) éCI2C_RAW_INTR_STAT_TX_EMPTY ((uint16_t)0x0010) êCI2C_RAW_INTR_STAT_RD_REQ ((uint16_t)0x0020) ëCI2C_RAW_INTR_STAT_TX_ABRT ((uint16_t)0x0040) ìCI2C_RAW_INTR_STAT_RX_DONE ((uint16_t)0x0080) íCI2C_RAW_INTR_STAT_ACTIVITY ((uint16_t)0x0100) îCI2C_RAW_INTR_STAT_STOP_DET ((uint16_t)0x0200) ïCI2C_RAW_INTR_STAT_START_DET ((uint16_t)0x0400) ðCI2C_RAW_INTR_STAT_GEN_CALL ((uint16_t)0x0800) ñCI2C_RAW_INTR_STAT_RESTART_DET ((uint16_t)0x1000) òCI2C_RAW_INTR_STAT_MST_ON_HOLD ((uint16_t)0x2000) õCI2C_RX_TL ((uint16_t)0x00ff) øCI2C_TX_TL ((uint16_t)0x00ff) ûCI2C_CLR_INTR ((uint16_t)0x0001) þCI2C_CLR_RX_UNDER ((uint16_t)0x0001) DI2C_CLR_RX_UNDER ((uint16_t)0x0001) DI2C_CLR_TX_OVER ((uint16_t)0x0001) DI2C_CLR_RD_REQ ((uint16_t)0x0001) DI2C_CLR_TX_ABORT ((uint16_t)0x0001) DI2C_CLR_RX_DONE ((uint16_t)0x0001) DI2C_CLR_ACTIVITY ((uint16_t)0x0001) DI2C_CLR_STOP_DET ((uint16_t)0x0001) DI2C_CLR_START_DET ((uint16_t)0x0001) DI2C_CLR_GEN_CALL ((uint16_t)0x0001) DI2C_CLR_RESTART_DET ((uint16_t)0x0001) DI2C_CLR_MST_ON_HOLD ((uint16_t)0x0001) ¡DI2C_ENABLE_ENABLE ((uint16_t)0x0001) ¢DI2C_ENABLE_ABORT ((uint16_t)0x0002) ¤DI2C_STATUS_ACTIVITY ((uint16_t)0x0001) ¥DI2C_STATUS_TFNF ((uint16_t)0x0002) ¦DI2C_STATUS_TFE ((uint16_t)0x0004) §DI2C_STATUS_RFNE ((uint16_t)0x0008) ¨DI2C_STATUS_RFE ((uint16_t)0x0010) ©DI2C_STATUS_MST_ACTIVITY ((uint16_t)0x0020) ªDI2C_STATUS_SLV_ACTIVITY ((uint16_t)0x0040) DI2C_TXFLR ((uint32_t)0x0000000f) °DI2C_RXFLR ((uint32_t)0x0000000f) ³DI2C_SDA_HOLD ((uint32_t)0x0000ffff) ¶DI2C_TX_ABRT_SOURCE_7B_ADDR_NOACK ((uint32_t)0x00000001) ·DI2C_TX_ABRT_SOURCE_10ADDR1_NOACK ((uint32_t)0x00000002) ¸DI2C_TX_ABRT_SOURCE_10ADDR2_NOACK ((uint32_t)0x00000004) ¹DI2C_TX_ABRT_SOURCE_TXDATA_NOACK ((uint32_t)0x00000008) ºDI2C_TX_ABRT_SOURCE_GCALL_NOACK ((uint32_t)0x00000010) »DI2C_TX_ABRT_SOURCE_GCALL_READ ((uint32_t)0x00000020) ¼DI2C_TX_ABRT_SOURCE_HS_ACKDET ((uint32_t)0x00000040) ½DI2C_TX_ABRT_SOURCE_SBYTE_ACKDET ((uint32_t)0x00000080) ¾DI2C_TX_ABRT_SOURCE_HS_NORSTRT ((uint32_t)0x00000100) ¿DI2C_TX_ABRT_SOURCE_SBYTE_NORSTRT ((uint32_t)0x00000200) ÀDI2C_TX_ABRT_SOURCE_10B_RD_NORSTRT ((uint32_t)0x00000400) ÁDI2C_TX_ABRT_SOURCE_MASTER_DIS ((uint32_t)0x00000800) ÂDI2C_TX_ABRT_SOURCE_ARB_LOST ((uint32_t)0x00001000) ÃDI2C_TX_ABRT_SOURCE_SLVFLUSH_TXFIFO ((uint32_t)0x00002000) ÄDI2C_TX_ABRT_SOURCE_SLV_ARBLOST ((uint32_t)0x00004000) ÅDI2C_TX_ABRT_SOURCE_SLVRD_INTX ((uint32_t)0x00008000) ÆDI2C_TX_ABRT_SOURCE_USER_ABRT ((uint32_t)0x00010000) ÈDI2C_TX_ABRT_SOURCE_TX_FLUSH_CNT ((uint32_t)0xff000000) ËDI2C_SLV_DATA_NACK_ONLY ((uint32_t)0x00000001) ÎDI2C_DMA_CR_RDMAE ((uint32_t)0x00000001) ÏDI2C_DMA_CR_TDMAE ((uint32_t)0x00000002) ÒDI2C_DMA_TDLR ((uint32_t)0x00000007) ÕDI2C_DMA_RDLR ((uint32_t)0x00000007) ØDI2C_SDA_SETUP ((uint32_t)0x000000ff) ÛDI2C_ACK_GENERAL_CALL ((uint32_t)0x00000001) ÞDI2C_ENABLE_STATUS_IC_EN ((uint32_t)0x00000001) ßDI2C_ENABLE_STATUS_SLV_RX_ABORTED ((uint32_t)0x00000002) àDI2C_ENABLE_STATUS_SLV_FIFO_FILLED_AND_FLUSHED ((uint32_t)0x00000004) ãDI2C_FS_SPKLEN ((uint32_t)0x0000000ff) æDI2C_HS_SPKLEN ((uint32_t)0x0000000ff) éDI2C_COMP_PARAM1_APB_DATA_WIDTH ((uint32_t)0x000000003) êDI2C_COMP_PARAM1_MAX_SPEED_MODE ((uint32_t)0x000000006) ëDI2C_COMP_PARAM1_HC_COUNT_VALUES ((uint32_t)0x000000010) ìDI2C_COMP_PARAM1_INTR_IO ((uint32_t)0x000000020) íDI2C_COMP_PARAM1_HAS_DMA ((uint32_t)0x000000040) îDI2C_COMP_PARAM1_ADD_ENCODED_PARAMS ((uint32_t)0x000000080) ïDI2C_COMP_PARAM1_RX_BUFFER_DEPTH ((uint32_t)0x00000ff00) ðDI2C_COMP_PARAM1_TX_BUFFER_DEPTH ((uint32_t)0x000ff0000) óDI2C_COMP_VERSION ((uint32_t)0xffffffffff) öDI2C_COMP_TYPE ((uint32_t)0xffffffffff) EANAC_LP_REG_SYNC_3V_Pos (0) EANAC_LP_REG_SYNC_3V_Msk (0x1ul << ANAC_LP_REG_SYNC_3V_Pos) EANAC_LP_REG_SYNC_3V_TRG_Pos (1) EANAC_LP_REG_SYNC_3V_TRG_Msk (0x1ul << ANAC_LP_REG_SYNC_3V_TRG_Pos) EANAC_FL_SLEEP_MODE_SEL_Pos (0) EANAC_FL_SLEEP_MODE_SEL_Msk (0x3ul << ANAC_FL_SLEEP_MODE_SEL_Pos) EANAC_FL_EXT_WAKEUP_SEL_Pos_3v (2) EANAC_FL_EXT_WAKEUP_SEL_Msk_3v (0x1ul << ANAC_FL_EXT_WAKEUP_SEL_Pos_3v) EANAC_FL_SLEEP_CNT_EN_Pos (3) EANAC_FL_SLEEP_CNT_EN_Msk (0x1ul << ANAC_FL_SLEEP_CNT_EN_Pos) ¡EANAC_FL_CPU_RETENTION_EN_Pos (4) ¢EANAC_FL_CPU_RETENTION_EN_Msk (0x1ul << ANAC_FL_CPU_RETENTION_EN_Pos) £EANAC_FL_LDO_ISOLATE_EN_Pos (5) ¤EANAC_FL_LDO_ISOLATE_EN_Msk (0x1ul << ANAC_FL_LDO_ISOLATE_EN_Pos) ¥EANAC_FL_RCL_GATE_EN_Pos (6) ¦EANAC_FL_RCL_GATE_EN_Msk (0x1ul << ANAC_FL_RCL_GATE_EN_Pos) §EANAC_FL_PWR_CTL_EN_Pos (7) ¨EANAC_FL_PWR_CTL_EN_Msk (0x1ul << ANAC_FL_PWR_CTL_EN_Pos) ©EANAC_FL_FLASH_BP_EN_Pos (12) ªEANAC_FL_FLASH_BP_EN_Msk (0x1ul << ANAC_FL_FLASH_BP_EN_Pos) «EANAC_FL_FLASH_LP_EN_Pos (13) ¬EANAC_FL_FLASH_LP_EN_Msk (0x1ul << ANAC_FL_FLASH_LP_EN_Pos) EANAC_FL_BUCK_BP_EN_Pos (14) ®EANAC_FL_BUCK_BP_EN_Msk (0x1ul << ANAC_FL_BUCK_BP_EN_Pos) ¯EANAC_FL_BUCK_EN_Pos (15) °EANAC_FL_BUCK_EN_Msk (0x1ul << ANAC_FL_BUCK_EN_Pos) ±EANAC_FL_DPLL_EN_Pos (16) ²EANAC_FL_DPLL_EN_Msk (0x1ul << ANAC_FL_DPLL_EN_Pos) ³EANAC_FL_RCH_EN_Pos (17) ´EANAC_FL_RCH_EN_Msk (0x1ul << ANAC_FL_RCH_EN_Pos) µEANAC_FL_XTH_EN_Pos (18) ¶EANAC_FL_XTH_EN_Msk (0x1ul << ANAC_FL_XTH_EN_Pos) ·EANAC_FL_XTAL32K_EN_Pos_3v (19) ¸EANAC_FL_XTAL32K_EN_Msk_3v (0x1ul << ANAC_FL_XTAL32K_EN_Pos_3v) ¹EANAC_FL_RC32K_EN_Pos_3v (20) ºEANAC_FL_RC32K_EN_Msk_3v (0x1ul << ANAC_FL_RC32K_EN_Pos_3v) »EANAC_FL_LDO_HP_EN_Pos (22) ¼EANAC_FL_LDO_HP_EN_Msk (0x1ul << ANAC_FL_LDO_HP_EN_Pos) ½EANAC_FL_PMU_EN_Pos (23) ¾EANAC_FL_PMU_EN_Msk (0x1ul << ANAC_FL_PMU_EN_Pos) ¿EANAC_SRAM0_POWER_CTL_Pos (24) ÀEANAC_SRAM0_POWER_CTL_Msk (0x1ul << ANAC_SRAM0_POWER_CTL_Pos) ÁEANAC_SRAM1_POWER_CTL_Pos (25) ÂEANAC_SRAM1_POWER_CTL_Msk (0x1ul << ANAC_SRAM1_POWER_CTL_Pos) ÃEANAC_CPU_POWER_CTL_Pos (26) ÄEANAC_CPU_POWER_CTL_Msk (0x1ul << ANAC_CPU_POWER_CTL_Pos) ÅEANAC_PHY_POWER_CTL_Pos (27) ÆEANAC_PHY_POWER_CTL_Msk (0x1ul << ANAC_PHY_POWER_CTL_Pos) ÇEANAC_LL_SRAM_POWER_CTL_Pos (28) ÈEANAC_LL_SRAM_POWER_CTL_Msk (0x1ul << ANAC_LL_SRAM_POWER_CTL_Pos) ÉEANAC_FLASH_POWER_CTL_Pos (29) ÊEANAC_FLASH_POWER_CTL_Msk (0x1ul << ANAC_FLASH_POWER_CTL_Pos) ËEANAC_LDO_POWER_CTL_Pos (30) ÌEANAC_LDO_POWER_CTL_Msk (0x1ul << ANAC_LDO_POWER_CTL_Pos) ÍEANAC_LDOL_POWER_CTL_Pos (31) ÎEANAC_LDOL_POWER_CTL_Msk (0x1ul << ANAC_LDOL_POWER_CTL_Pos) ÒEANAC_INT_LP_INT_EN_Pos (0) ÓEANAC_INT_LP_INT_EN_Msk (0x1ul << ANAC_INT_LP_INT_EN_Pos) ÔEANAC_INT_DP_FLAG_Pos (1) ÕEANAC_INT_DP_FLAG_Msk (0x1ul << ANAC_INT_DP_FLAG_Pos) ÖEANAC_INT_STANDBY_M1_FLAG_Pos (2) ×EANAC_INT_STANDBY_M1_FLAG_Msk (0x1ul << ANAC_INT_STANDBY_M1_FLAG_Pos) ØEANAC_INT_STANDBY_M0_FLAG_Pos (3) ÙEANAC_INT_STANDBY_M0_FLAG_Msk (0x1ul << ANAC_INT_STANDBY_M0_FLAG_Pos) ÚEANAC_INT_SRAM_RET_FLAG_Pos (4) ÛEANAC_INT_SRAM_RET_FLAG_Msk (0x1ul << ANAC_INT_SRAM_RET_FLAG_Pos) ÜEANAC_INT_SLEEP_TMR_INT_EN_Pos (16) ÝEANAC_INT_SLEEP_TMR_INT_EN_Msk (0x1ul << ANAC_INT_SLEEP_TMR_INT_EN_Pos) ÞEANAC_INT_SLEEP_TMR0_Pos (17) ßEANAC_INT_SLEEP_TMR0_Msk (0x1ul << ANAC_INT_SLEEP_TMR0_Pos) àEANAC_INT_SLEEP_TMR1_Pos (18) áEANAC_INT_SLEEP_TMR1_Msk (0x1ul << ANAC_INT_SLEEP_TMR1_Pos) âEANAC_INT_SLEEP_TMR2_Pos (19) ãEANAC_INT_SLEEP_TMR2_Msk (0x1ul << ANAC_INT_SLEEP_TMR2_Pos) äEANAC_INT_SLEEP_TMR_WK_EN_Pos (20) åEANAC_INT_SLEEP_TMR_WK_EN_Msk (0x1ul << ANAC_INT_SLEEP_TMR_WK_EN_Pos) èEANAC_32KCLK_DLY_TIME_Pos (0) éEANAC_32KCLK_DLY_TIME_Msk (0x3FFul << ANAC_32KCLK_DLY_TIME_Pos) êEANAC_32KCLK_DLY_EN_Pos (10) ëEANAC_32KCLK_DLY_EN_Msk (0x1ul << ANAC_32KCLK_DLY_EN_Pos) ìEANAC_HPLDO_RDY_BYPASS_Pos (11) íEANAC_HPLDO_RDY_BYPASS_Msk (0x1ul << ANAC_HPLDO_RDY_BYPASS_Pos) îEANAC_LPLDOH_DLY_TIME_Pos_3v (16) ïEANAC_LPLDOH_DLY_TIME_Msk_3v (0x3FFul << ANAC_LPLDOH_DLY_TIME_Pos_3v) òEANAC_PTAT_CORE_EN_Pos (0) óEANAC_PTAT_CORE_EN_Msk (0x1ul << ANAC_PTAT_CORE_EN_Pos) ôEANAC_PTAT_TMP_TRIM_Pos (1) õEANAC_PTAT_TMP_TRIM_Msk (0x3ul << ANAC_PTAT_TMP_TRIM_Pos) öEANAC_PTAT_TRIM_Pos (3) ÷EANAC_PTAT_TRIM_Msk (0x7ul << ANAC_PTAT_TRIM_Pos) øEANAC_PTAT_FLT_SHIFT_EN_Pos (6) ùEANAC_PTAT_FLT_SHIFT_EN_Msk (0x1ul << ANAC_PTAT_FLT_SHIFT_EN_Pos) úEANAC_PTAT_FLT_ACT_EN_Pos (7) ûEANAC_PTAT_FLT_ACT_EN_Msk (0x1ul << ANAC_PTAT_FLT_ACT_EN_Pos) üEANAC_POLY_EN_Pos (8) ýEANAC_POLY_EN_Msk (0x1ul << ANAC_POLY_EN_Pos) þEANAC_IPOLY_TRIM_Pos (16) ÿEANAC_IPOLY_TRIM_Msk (0x3ul << ANAC_IPOLY_TRIM_Pos) FANAC_HPLDO_EN_Pos (0) FANAC_HPLDO_EN_Msk (0x1ul << ANAC_HPLDO_EN_Pos) FANAC_HPLDO_BYPASS_Pos (2)
FANAC_HPLDO_BYPASS_Msk (0x1ul << ANAC_HPLDO_BYPASS_Pos) FANAC_HPLDO_TRIM_Pos (3) FANAC_HPLDO_TRIM_Msk (0xFul << ANAC_HPLDO_TRIM_Pos) FANAC_HPLDO_SEL_Pos (9) FANAC_HPLDO_SEL_Msk (0x1ul << ANAC_HPLDO_SEL_Pos) FANAC_HPLDO_FLASHLDO_BP_Pos_3v (16) FANAC_HPLDO_FLASHLDO_BP_Msk_3v (0x1ul << ANAC_HPLDO_FLASHLDO_BP_Pos_3v) FANAC_HPLDO_FLASHLDO_EN_Pos_3v (17) FANAC_HPLDO_FLASHLDO_EN_Msk_3v (0x1ul << ANAC_HPLDO_FLASHLDO_EN_Pos_3v) FANAC_HPLDO_FLASHLDO_LP_EN_Pos (18) FANAC_HPLDO_FLASHLDO_LP_EN_Msk (0x1ul << ANAC_HPLDO_FLASHLDO_LP_EN_Pos) FANAC_HPLDO_FLASHLDO_CAP_SEL_Pos (19) FANAC_HPLDO_FLASHLDO_CAP_SEL_Msk (0x1ul << ANAC_HPLDO_FLASHLDO_CAP_SEL_Pos) FANAC_HPLDO_FLASHLDO_TRIM_Pos (20) FANAC_HPLDO_FLASHLDO_TRIM_Msk (0x7ul << ANAC_HPLDO_FLASHLDO_TRIM_Pos) FANAC_LPLDO_L_EN_Pos (0) FANAC_LPLDO_L_EN_Msk (0x1ul << ANAC_LPLDO_L_EN_Pos) FANAC_LPLDO_L_DVDD_SEL_Pos (1) FANAC_LPLDO_L_DVDD_SEL_Msk (0xFul << ANAC_LPLDO_L_DVDD_SEL_Pos) FANAC_LPLDO_H_EN_Pos_3v (16) FANAC_LPLDO_H_EN_Msk_3v (0x1ul << ANAC_LPLDO_H_EN_Pos_3v) FANAC_LPLDO_H_DVDD_SEL_Pos_3v (17) FANAC_LPLDO_H_DVDD_SEL_Msk_3v (0xFul << ANAC_LPLDO_H_DVDD_SEL_Pos_3v) FANAC_LPLDO_H_REF_TRIM_Pos_3v (21) FANAC_LPLDO_H_REF_TRIM_Msk_3v (0x7ul << ANAC_LPLDO_H_REF_TRIM_Pos_3v) FANAC_LPLDO_H_MODE_SEL_Pos_3v (24) FANAC_LPLDO_H_MODE_SEL_Msk_3v (0x1ul << ANAC_LPLDO_H_MODE_SEL_Pos_3v) £FANAC_ANA_LDO_EN_Pos (0) ¤FANAC_ANA_LDO_EN_Msk (0x1ul << ANAC_ANA_LDO_EN_Pos) ¥FANAC_ANA_LDO_TRIM_Pos (3) ¦FANAC_ANA_LDO_TRIM_Msk (0xFul << ANAC_ANA_LDO_TRIM_Pos) ¨FANAC_FSYN_LDO_EN_Pos (0) ©FANAC_FSYN_LDO_EN_Msk (0x1ul << ANAC_FSYN_LDO_EN_Pos) ªFANAC_FSYN_LDO_TRIM_Pos (3) «FANAC_FSYN_LDO_TRIM_Msk (0xFul << ANAC_FSYN_LDO_TRIM_Pos) FANAC_HP_DVDD_PD_Pos (0) ®FANAC_HP_DVDD_PD_Msk (0x1ul << ANAC_HP_DVDD_PD_Pos) ¯FANAC_HP_DVDD_EN_Pos (1) °FANAC_HP_DVDD_EN_Msk (0x1ul << ANAC_HP_DVDD_EN_Pos) ±FANAC_DVDD_SRAM0_EN_Pos (2) ²FANAC_DVDD_SRAM0_EN_Msk (0x1ul << ANAC_DVDD_SRAM0_EN_Pos) ³FANAC_DVDD_SRAM1_EN_Pos (3) ´FANAC_DVDD_SRAM1_EN_Msk (0x1ul << ANAC_DVDD_SRAM1_EN_Pos) µFANAC_DVDD_LPLDO_EN_Pos (4) ¶FANAC_DVDD_LPLDO_EN_Msk (0x1ul << ANAC_DVDD_LPLDO_EN_Pos) ·FANAC_VDD_FLASH_EN_Pos (5) ¸FANAC_VDD_FLASH_EN_Msk (0x1ul << ANAC_VDD_FLASH_EN_Pos) ¹FANAC_DVDD_DLL_EN_Pos (6) ºFANAC_DVDD_DLL_EN_Msk (0x1ul << ANAC_DVDD_DLL_EN_Pos) »FANAC_DVDD_PHY_EN_Pos (7) ¼FANAC_DVDD_PHY_EN_Msk (0x1ul << ANAC_DVDD_PHY_EN_Pos) ½FANAC_DVDD_CPU_EN_Pos (8) ¾FANAC_DVDD_CPU_EN_Msk (0x1ul << ANAC_DVDD_CPU_EN_Pos) ÁFANAC_BUCK_BYPASS_EN_Pos_3v (0) ÂFANAC_BUCK_BYPASS_EN_Msk_3v (0x1ul << ANAC_BUCK_BYPASS_EN_Pos_3v) ÃFANAC_BUCK_EN_Pos_3v (1) ÄFANAC_BUCK_EN_Msk_3v (0x1ul << ANAC_BUCK_EN_Pos_3v) ÅFANAC_BUCK_VOUT_Pos_3v (2) ÆFANAC_BUCK_VOUT_Msk_3v (0xful << ANAC_BUCK_VOUT_Pos_3v) ÇFANAC_BUCK_IMAX_Pos_3v (6) ÈFANAC_BUCK_IMAX_Msk_3v (0x7ul << ANAC_BUCK_IMAX_Pos_3v) ÉFANAC_BUCK_IMAX_CAL_Pos_3v (9) ÊFANAC_BUCK_IMAX_CAL_Msk_3v (0x1Ful << ANAC_BUCK_IMAX_CAL_Pos_3v) ËFANAC_BUCK_ZERO_CAL_Pos_3v (14) ÌFANAC_BUCK_ZERO_CAL_Msk_3v (0x1Ful << ANAC_BUCK_ZERO_CAL_Pos_3v) ÍFANAC_BUCK_DLY_MODE_EN_Pos_3v (19) ÎFANAC_BUCK_DLY_MODE_EN_Msk_3v (0x1ul << ANAC_BUCK_DLY_MODE_EN_Pos_3v) ÏFANAC_BUCK_TEST_EN_Pos (20) ÐFANAC_BUCK_TEST_EN_Msk (0x1ul << ANAC_BUCK_TEST_EN_Pos) ÑFANAC_BUCK_DEBOUNCE_EN_Pos_3v (21) ÒFANAC_BUCK_DEBOUNCE_EN_Msk_3v (0x1ul << ANAC_BUCK_DEBOUNCE_EN_Pos_3v) ÓFANAC_BUCK_CAL_EN_Pos_3v (22) ÔFANAC_BUCK_CAL_EN_Msk_3v (0x3ul << ANAC_BUCK_CAL_EN_Pos_3v) ÕFANAC_BUCK_CAL_OUT_Pos (24) ÖFANAC_BUCK_CAL_OUT_Msk (0x1ul << ANAC_BUCK_CAL_OUT_Pos) ×FANAC_BUCK_VOL_LIMIT_EN_Pos_3v (25) ØFANAC_BUCK_VOL_LIMIT_EN_Msk_3v (0x1ul << ANAC_BUCK_VOL_LIMIT_EN_Pos_3v) ÛFANAC_ADC_LDO_EN_Pos (0) ÜFANAC_ADC_LDO_EN_Msk (0x1ul << ANAC_ADC_LDO_EN_Pos) ÝFANAC_ADC_LDO_TRIM_Pos (3) ÞFANAC_ADC_LDO_TRIM_Msk (0xFul << ANAC_ADC_LDO_TRIM_Pos) áFANAC_RFFE_LDO_EN_Pos (0) âFANAC_RFFE_LDO_EN_Msk (0x1ul << ANAC_RFFE_LDO_EN_Pos) ãFANAC_RFFE_LDO_TRIM_Pos (3) äFANAC_RFFE_LDO_TRIM_Msk (0xFul << ANAC_RFFE_LDO_TRIM_Pos) æFANAC_VCO_LDO_EN_Pos (0) çFANAC_VCO_LDO_EN_Msk (0x1ul << ANAC_VCO_LDO_EN_Pos) èFANAC_VCO_LDO_TRIM_Pos (3) éFANAC_VCO_LDO_TRIM_Msk (0xFul << ANAC_VCO_LDO_TRIM_Pos) ìFANAC_DFT_BUF_BYPASS_Pos (0) íFANAC_DFT_BUF_BYPASS_Msk (0x1ul << ANAC_DFT_BUF_BYPASS_Pos) îFANAC_DFT_FLAG_SEL_Pos (1) ïFANAC_DFT_FLAG_SEL_Msk (0x3ul << ANAC_DFT_FLAG_SEL_Pos) ðFANAC_DFT_CLK_SEL_Pos (3) ñFANAC_DFT_CLK_SEL_Msk (0x7ul << ANAC_DFT_CLK_SEL_Pos) òFANAC_DFT_I_SEL_Pos (6) óFANAC_DFT_I_SEL_Msk (0x1ul << ANAC_DFT_I_SEL_Pos) ôFANAC_DFT_V_SEL_Pos (7) õFANAC_DFT_V_SEL_Msk (0xFul << ANAC_DFT_V_SEL_Pos) öFANAC_DFT_FLAG_OUTPUT_EN_Pos (11) ÷FANAC_DFT_FLAG_OUTPUT_EN_Msk (0x1ul << ANAC_DFT_FLAG_OUTPUT_EN_Pos) øFANAC_DFT_CLK_OUTPUT_EN_Pos (12) ùFANAC_DFT_CLK_OUTPUT_EN_Msk (0x1ul << ANAC_DFT_CLK_OUTPUT_EN_Pos) úFANAC_DFT_I_OUTPUT_EN_Pos (13) ûFANAC_DFT_I_OUTPUT_EN_Msk (0x1ul << ANAC_DFT_I_OUTPUT_EN_Pos) üFANAC_DFT_V_OUTPUT_EN_Pos (14) ýFANAC_DFT_V_OUTPUT_EN_Msk (0x1ul << ANAC_DFT_V_OUTPUT_EN_Pos) þFANAC_DFT_PAD_TEST_SEL_Pos (15) ÿFANAC_DFT_PAD_TEST_SEL_Msk (0x3ul << ANAC_DFT_PAD_TEST_SEL_Pos) GANAC_DFT_BATTERY_TEST_EN_Pos (22) GANAC_DFT_BATTERY_TEST_EN_Msk (0x1ul << ANAC_DFT_BATTERY_TEST_EN_Pos) GANAC_DFT_BATTERY_TEST_SEL_Pos (23) GANAC_DFT_BATTERY_TEST_SEL_Msk (0x1ul << ANAC_DFT_BATTERY_TEST_SEL_Pos) GANAC_DFT_BATTERY_TEST_TRIM_Pos (24)
GANAC_DFT_BATTERY_TEST_TRIM_Msk (0xfful << ANAC_DFT_BATTERY_TEST_TRIM_Pos) GANAC_MISC_RST_VREF_TRIM_Pos_3v (0) GANAC_MISC_RST_VREF_TRIM_Msk_3v (0x7ul << ANAC_MISC_RST_VREF_TRIM_Pos_3v) GANAC_MISC_PMU_LDO_TST_Pos (3) GANAC_MISC_PMU_LDO_TST_Msk (0x1ul << ANAC_MISC_PMU_LDO_TST_Pos) GANAC_MISC_PMU_VBG_BUF_EN_Pos (4) GANAC_MISC_PMU_VBG_BUF_EN_Msk (0x1ul << ANAC_MISC_PMU_VBG_BUF_EN_Pos) GANAC_MISC_LPLDO_LEVEL_SHIFT_EN_Pos_3v (6) GANAC_MISC_LPLDO_LEVEL_SHIFT_EN_Msk_3v (0x1ul << ANAC_MISC_LPLDO_LEVEL_SHIFT_EN_Pos_3v) GANAC_MISC_HPLDO_LEVEL_SHIFT_EN_Pos (7) GANAC_MISC_HPLDO_LEVEL_SHIFT_EN_Msk (0x1ul << ANAC_MISC_HPLDO_LEVEL_SHIFT_EN_Pos) GANAC_MISC_FLASH_PAD_PUEN_Pos (14) GANAC_MISC_FLASH_PAD_PUEN_Msk (0x3Ful << ANAC_MISC_FLASH_PAD_PUEN_Pos) GANAC_MISC_FLASH_PAD_PDEN_Pos (20) GANAC_MISC_FLASH_PAD_PDEN_Msk (0x3Ful << ANAC_MISC_FLASH_PAD_PDEN_Pos) GANAC_MISC_USB_EN_Pos (26) GANAC_MISC_USB_EN_Msk (0x1ul << ANAC_MISC_USB_EN_Pos) GANAC_MISC_USB_DP_PU_Pos (27) GANAC_MISC_USB_DP_PU_Msk (0x1ul << ANAC_MISC_USB_DP_PU_Pos) GANAC_MISC_USB_DM_PU_Pos (28) GANAC_MISC_USB_DM_PU_Msk (0x1ul << ANAC_MISC_USB_DM_PU_Pos) GANAC_ACT_32K_EN_Pos (0) GANAC_ACT_32K_EN_Msk (0x1ul << ANAC_ACT_32K_EN_Pos) ¡GANAC_ACT_32K_SEL_Pos (1) ¢GANAC_ACT_32K_SEL_Msk (0x1ul << ANAC_ACT_32K_SEL_Pos) £GANAC_ACT_32K_UP_DONE_Pos (3) ¤GANAC_ACT_32K_UP_DONE_Msk (0x1ul << ANAC_ACT_32K_UP_DONE_Pos) ¥GANAC_ACT_32K_FINE_OFFSET_Pos (12) ¦GANAC_ACT_32K_FINE_OFFSET_Msk (0x3FFul << ANAC_ACT_32K_FINE_OFFSET_Pos) §GANAC_ACT_32K_FINE_CORRECT_Pos (22) ¨GANAC_ACT_32K_FINE_CORRECT_Msk (0x3FFul << ANAC_ACT_32K_FINE_CORRECT_Pos) «GANAC_CPU_REMAP_ADR_Pos (0) ¬GANAC_CPU_REMAP_ADR_Msk (0xFFFFFFul << ANAC_CPU_REMAP_ADR_Pos) GANAC_CPU_ADR_REMAP_EN_Pos (31) ®GANAC_CPU_ADR_REMAP_EN_Msk (0x1ul << ANAC_CPU_ADR_REMAP_EN_Pos) ±GANAC_RCL_HW_CAL_TIME_Pos (0) ²GANAC_RCL_HW_CAL_TIME_Msk (0xFFul << ANAC_RCL_HW_CAL_TIME_Pos) ³GANAC_RCL_HW_CAL_EN_Pos (8) ´GANAC_RCL_HW_CAL_EN_Msk (0x1ul << ANAC_RCL_HW_CAL_EN_Pos) µGANAC_RCL_HW_CAL_BUSY_Pos (9) ¶GANAC_RCL_HW_CAL_BUSY_Msk (0x1ul << ANAC_RCL_HW_CAL_BUSY_Pos) ÒGEFUSE_CTL_EFUSE_EN_Pos (0) ÓGEFUSE_CTL_EFUSE_EN_Msk (0x1ul << EFUSE_CTL_EFUSE_EN_Pos) ÕGEFUSE_CTL_THR_DVDD_Pos (1) ÖGEFUSE_CTL_THR_DVDD_Msk (0x1ul << EFUSE_CTL_THR_DVDD_Pos) ØGEFUSE_CTL_TAEN_RD_CTL_Pos (2) ÙGEFUSE_CTL_TAEN_RD_CTL_Msk (0x1ul << EFUSE_CTL_TAEN_RD_CTL_Pos) ÛGEFUSE_CTL_THR_RD_CTL_Pos (3) ÜGEFUSE_CTL_THR_RD_CTL_Msk (0x1ul << EFUSE_CTL_THR_RD_CTL_Pos) ÞGEFUSE_CTL_TRD_CTL_Pos (4) ßGEFUSE_CTL_TRD_CTL_Msk (0x1ul << EFUSE_CTL_TRD_CTL_Pos) áGEFUSE_CTL_TSR_RD_CTL_Pos (5) âGEFUSE_CTL_TSR_RD_CTL_Msk (0x1ul << EFUSE_CTL_TSR_RD_CTL_Pos) äGEFUSE_CTL_TSR_DVDD_CTL_Pos (6) åGEFUSE_CTL_TSR_DVDD_CTL_Msk (0x1ul << EFUSE_CTL_TSR_DVDD_CTL_Pos) çGEFUSE_CTL_THP_RD_CTL_Pos (7) èGEFUSE_CTL_THP_RD_CTL_Msk (0x1ul << EFUSE_CTL_THP_RD_CTL_Pos) êGEFUSE_CTL_THP_PG_AVDD_CTL_Pos (8) ëGEFUSE_CTL_THP_PG_AVDD_CTL_Msk (0x1ul << EFUSE_CTL_THP_PG_AVDD_CTL_Pos) íGEFUSE_CTL_TAEN_PGM_CTL_Pos (9) îGEFUSE_CTL_TAEN_PGM_CTL_Msk (0x1ul << EFUSE_CTL_TAEN_PGM_CTL_Pos) ðGEFUSE_CTL_THP_PGM_CTL_Pos (10) ñGEFUSE_CTL_THP_PGM_CTL_Msk (0x1ul << EFUSE_CTL_THP_PGM_CTL_Pos) óGEFUSE_CTL_TPGM_CTL_Pos (11) ôGEFUSE_CTL_TPGM_CTL_Msk (0x1ul << EFUSE_CTL_TPGM_CTL_Pos) öGEFUSE_CTL_TSP_PGM_CTL_Pos (12) ÷GEFUSE_CTL_TSP_PGM_CTL_Msk (0x1ul << EFUSE_CTL_TSP_PGM_CTL_Pos) ùGEFUSE_CTL_TSP_PG_AVDD_CTL_Pos (13) úGEFUSE_CTL_TSP_PG_AVDD_CTL_Msk (0x1ul << EFUSE_CTL_TSP_PG_AVDD_CTL_Pos) üGEFUSE_CTL_TSP_RD_CTL_Pos (14) ýGEFUSE_CTL_TSP_TSP_RD_CTL_Msk (0x1ul << EFUSE_CTL_TSP_RD_CTL_Pos) HEFUSE_ADDR_EFUSEADDR_ADR_Pos (0) HEFUSE_ADDR_EFUSEADDR_ADR_Msk (0xfful << EFUSE_ADDR_EFUSEADDR_ADR_Pos) HEFUSE_DAT_EFUSEDAT_DAT_Pos (0)
HEFUSE_DAT_EFUSEDAT_DAT_Msk (0xfful << EFUSE_DAT_EFUSEDAT_DAT_Pos) HEFUSE_DAT_EFUSEDAT_DAT_CONFIRM_Pos (8) HEFUSE_DAT_EFUSEDAT_DAT_CONFIRM_Msk (0xfful << EFUSE_DAT_EFUSEDAT_DAT_CONFIRM_Pos) HEFUSE_VDD_DVDD_REG_Pos (0) HEFUSE_VDD_DVDD_REG_Msk (0x1ul << EFUSE_VDD_DVDD_REG_Pos) HEFUSE_VDD_AVDD_REG_Pos (1) HEFUSE_VDD_AVDD_REG_Msk (0x1ul << EFUSE_VDD_AVDD_REG_Pos) HEFUSE_CMD_EFUSECMD_CMD_Pos (0) HEFUSE_CMD_EFUSECMD_CMD_Msk (0x3ul << EFUSE_CMD_EFUSECMD_CMD_Pos) HEFUSE_TRG_EFUSETRG_GO_Pos (0) HEFUSE_TRG_EFUSETRG_GO_Msk (0x1ul << EFUSE_TRG_EFUSETRG_GO_Pos) HEFUSE_PROG_TIMING1_TSP_RD_SET_Pos (0) HEFUSE_PROG_TIMING1_TSP_RD_SET_Msk (0x1fful << EFUSE_PROG_TIMING1_TSP_RD_SET_Pos) HEFUSE_PROG_TIMING1_TSP_PG_AVDD_SET_Pos (9) HEFUSE_PROG_TIMING1_TSP_PG_AVDD_SET_Msk (0x1fful << EFUSE_PROG_TIMING1_TSP_PG_AVDD_SET_Pos) HEFUSE_PROG_TIMING1_TSP_PGM_SET_Pos (18) ¡HEFUSE_PROG_TIMING1_TSP_PGM_SET_Msk (0x1fful << EFUSE_PROG_TIMING1_TSP_PGM_SET_Pos) ¤HEFUSE_PROG_TIMING2_TPGM_SET_Pos (0) ¥HEFUSE_PROG_TIMING2_TPGM_SET_Msk (0x1fful << EFUSE_PROG_TIMING2_TPGM_SET_Pos) §HEFUSE_PROG_TIMING2_THP_PGM_SET_Pos (9) ¨HEFUSE_PROG_TIMING2_THP_PGM_SET_Msk (0x1fful << EFUSE_PROG_TIMING2_THP_PGM_SET_Pos) ªHEFUSE_PROG_TIMING2_TAEN_PGM_SET_Pos (18) «HEFUSE_PROG_TIMING2_TAEN_PGM_SET_Msk (0x1fful << EFUSE_PROG_TIMING2_TAEN_PGM_SET_Pos) ®HEFUSE_PROG_TIMING3_THP_PG_AVDD_SET_Pos (0) ¯HEFUSE_PROG_TIMING3_THP_PG_AVDD_SET_Msk (0x1fful << EFUSE_PROG_TIMING3_THP_PG_AVDD_SET_Pos) ±HEFUSE_PROG_TIMING3_THP_RD_SET_Pos (9) ²HEFUSE_PROG_TIMING3_THP_RD_SET_Msk (0x1fful << EFUSE_PROG_TIMING3_THP_RD_SET_Pos) µHEFUSE_READ_TIMING4_TSR_DVDD_SET_Pos (0) ¶HEFUSE_READ_TIMING4_TSR_DVDD_SET_Msk (0x1fful << EFUSE_READ_TIMING4_TSR_DVDD_SET_Pos) ¸HEFUSE_READ_TIMING4_TSR_RD_SET_Pos (9) ¹HEFUSE_READ_TIMING4_TSR_RD_SET_Msk (0x1fful << EFUSE_READ_TIMING4_TSR_RD_SET_Pos) »HEFUSE_READ_TIMING4_TRD_SET_Pos (18) ¼HEFUSE_READ_TIMING4_TRD_SET_Msk (0x1fful << EFUSE_READ_TIMING4_TRD_SET_Pos) ¿HEFUSE_READ_TIMING5_THR_RD_SET_Pos (0) ÀHEFUSE_READ_TIMING5_THR_RD_SET_Msk (0x1fful << EFUSE_READ_TIMING5_THR_RD_SET_Pos) ÂHEFUSE_READ_TIMING5_TAEN_RD_SET_Pos (9) ÃHEFUSE_READ_TIMING5_TAEN_RD_SET_Msk (0x1fful << EFUSE_READ_TIMING5_TAEN_RD_SET_Pos) ÅHEFUSE_READ_TIMING5_THR_DVDD_SET_Pos (18) ÆHEFUSE_READ_TIMING5_THR_DVDD_SET_Msk (0x1fful << EFUSE_READ_TIMING5_THR_DVDD_SET_Pos) ÉHEFUSE_OP_ERROR_OP_ERROR_Pos (0) ÊHEFUSE_OP_ERROR_OP_ERROR_Msk (0x1ul << EFUSE_OP_ERROR_OP_ERROR_Pos) ÍHEFUSE_VERIFY_DEBUG1_VERIFY_DBG_KEY1_Pos (0) ÎHEFUSE_VERIFY_DEBUG1_VERIFY_DBG_KEY1_Msk (0xfffffffful << EFUSE_VERIFY_DEBUG1_VERIFY_DBG_KEY1_Pos) ÑHEFUSE_VERIFY_DEBUG2_VERIFY_DBG_KEY2_Pos (0) ÒHEFUSE_VERIFY_DEBUG2_VERIFY_DBG_KEY2_Msk (0xfffffffful << EFUSE_VERIFY_DEBUG2_VERIFY_DBG_KEY2_Pos) ÕHEFUSE_VERIFY_DEBUG3_VERIFY_DBG_KEY3_Pos (0) ÖHEFUSE_VERIFY_DEBUG3_VERIFY_DBG_KEY3_Msk (0xfffffffful << EFUSE_VERIFY_DEBUG3_VERIFY_DBG_KEY3_Pos) ÙHEFUSE_VERIFY_DEBUG4_VERIFY_DBG_KEY4_Pos (0) ÚHEFUSE_VERIFY_DEBUG4_VERIFY_DBG_KEY4_Msk (0xfffffffful << EFUSE_VERIFY_DEBUG4_VERIFY_DBG_KEY4_Pos) ÝHEFUSE_FLASH_PERMISSION_CTRL_Pos (0) ÞHEFUSE_FLASH_PERMISSION_CTRL_Msk (0x1ul << EFUSE_FLASH_PERMISSION_CTRL_Pos) IUSB_DMA_REQUEST_Pos (0) IUSB_DMA_REQUEST_Msk (0x1ul << USB_DMA_REQUEST_Pos) IUSB_DMA_DIRECTION_Pos (1) IUSB_DMA_DIRECTION_Msk (0x1ul << USB_DMA_DIRECTION_Pos) IUSB_DMA_MODE_SEL_Pos (2) IUSB_DMA_MODE_SEL_Msk (0x1ul << USB_DMA_MODE_SEL_Pos) IUSB_DMA_EP_NUM_Pos (4) IUSB_DMA_EP_NUM_Msk (0xful << USB_DMA_EP_NUM_Pos) àIFSM5_SM_STP_Pos 6 áIFSM5_SM_STP_Msk (0x1ul<<FSM5_SM_STP_Pos) âIFSM5_SM_TX_LATENCY_Pos 0 ãIFSM5_SM_TX_LATENCY_Msk (0x3ful<<FSM5_SM_TX_LATENCY_Pos) åIFSM6_SM_RX_LATENCY_Pos 0 æIFSM6_SM_RX_LATENCY_Msk (0xful<<FSM6_SM_RX_LATENCY_Pos) èIFSM13_SM_RX_PACKET_ADDR_1_Pos 16 éIFSM13_SM_RX_PACKET_ADDR_1_Msk (0xfffful<<FSM13_SM_RX_PACKET_ADDR_1_Pos) êIFSM13_SM_TX_PACKET_ADDR_1_Pos 0 ëIFSM13_SM_TX_PACKET_ADDR_1_Msk (0xfffful<<FSM13_SM_TX_PACKET_ADDR_1_Pos) íIFSM14_SM_RX_PACKET_ADDR_2_Pos 16 îIFSM14_SM_RX_PACKET_ADDR_2_Msk (0xfffful<<FSM14_SM_RX_PACKET_ADDR_2_Pos) ïIFSM14_SM_TX_PACKET_ADDR_2_Pos 0 ðIFSM14_SM_TX_PACKET_ADDR_2_Msk (0xfffful<<FSM14_SM_TX_PACKET_ADDR_2_Pos) òIFSM15_SM_RX_PACKET_ADDR_3_Pos 16 óIFSM15_SM_RX_PACKET_ADDR_3_Msk (0xfffful<<FSM15_SM_RX_PACKET_ADDR_3_Pos) ôIFSM15_SM_TX_PACKET_ADDR_3_Pos 0 õIFSM15_SM_TX_PACKET_ADDR_3_Msk (0xfffful<<FSM15_SM_TX_PACKET_ADDR_3_Pos) ÷IFSM16_SM_RX_PACKET_ADDR_4_Pos 16 øIFSM16_SM_RX_PACKET_ADDR_4_Msk (0xfffful<<FSM16_SM_RX_PACKET_ADDR_4_Pos) ùIFSM16_SM_TX_PACKET_ADDR_4_Pos 0 úIFSM16_SM_TX_PACKET_ADDR_4_Msk (0xfffful<<FSM16_SM_TX_PACKET_ADDR_4_Pos) üIFSM17_SM_RX_PACKET_ADDR_5_Pos 16 ýIFSM17_SM_RX_PACKET_ADDR_5_Msk (0xfffful<<FSM17_SM_RX_PACKET_ADDR_5_Pos) þIFSM17_SM_TX_PACKET_ADDR_5_Pos 0 ÿIFSM17_SM_TX_PACKET_ADDR_5_Msk (0xfffful<<FSM17_SM_TX_PACKET_ADDR_5_Pos) JFSM18_SM_RX_PACKET_ADDR_6_Pos 16 JFSM18_SM_RX_PACKET_ADDR_6_Msk (0xfffful<<FSM18_SM_RX_PACKET_ADDR_6_Pos) JFSM18_SM_TX_PACKET_ADDR_6_Pos 0 JFSM18_SM_TX_PACKET_ADDR_6_Msk (0xfffful<<FSM18_SM_TX_PACKET_ADDR_6_Pos) JFSM19_SM_RX_PACKET_ADDR_7_Pos 16 JFSM19_SM_RX_PACKET_ADDR_7_Msk (0xfffful<<FSM19_SM_RX_PACKET_ADDR_7_Pos) JFSM19_SM_TX_PACKET_ADDR_7_Pos 0 JFSM19_SM_TX_PACKET_ADDR_7_Msk (0xfffful<<FSM19_SM_TX_PACKET_ADDR_7_Pos) JPHY1_PHY_DRV_RSP_BUF_FULL_Pos 22 JPHY1_PHY_DRV_RSP_BUF_FULL_Msk (0x1ul<<PHY1_PHY_DRV_RSP_BUF_FULL_Pos) JPHY1_PHY_DRV_RSP_BUF_EMPTY_Pos 21 JPHY1_PHY_DRV_RSP_BUF_EMPTY_Msk (0x1ul<<PHY1_PHY_DRV_RSP_BUF_EMPTY_Pos) JPHY1_PHY_DRV_CFG_BUF_ERROR_Pos 20 JPHY1_PHY_DRV_CFG_BUF_ERROR_Msk (0x1ul<<PHY1_PHY_DRV_CFG_BUF_ERROR_Pos) JPHY1_PHY_DRV_CFG_BUF_FULL_Pos 19 JPHY1_PHY_DRV_CFG_BUF_FULL_Msk (0x1ul<<PHY1_PHY_DRV_CFG_BUF_FULL_Pos) JPHY1_PHY_DRV_CFG_BUF_EMPTY_Pos 18 JPHY1_PHY_DRV_CFG_BUF_EMPTY_Msk (0x1ul<<PHY1_PHY_DRV_CFG_BUF_EMPTY_Pos) JPHY1_IF_CLK_PRESCALE_Pos 13 JPHY1_IF_CLK_PRESCALE_Msk (0x1ful<<PHY1_IF_CLK_PRESCALE_Pos) JPHY1_PHY_DRV_RSSI_REG_ADDR_Pos 5 JPHY1_PHY_DRV_RSSI_REG_ADDR_Msk (0xfful<<PHY1_PHY_DRV_RSSI_REG_ADDR_Pos) JPHY1_PHY_DRV_CFG_TRG_Pos 4 JPHY1_PHY_DRV_CFG_TRG_Msk (0x1ul<<PHY1_PHY_DRV_CFG_TRG_Pos) JPHY1_PHY_DRV_CFG_REG_Pos 2 JPHY1_PHY_DRV_CFG_REG_Msk (0x3ul<<PHY1_PHY_DRV_CFG_REG_Pos) JPHY1_PHY_DRV_RSP_BUF_FLUSH_Pos 1 JPHY1_PHY_DRV_RSP_BUF_FLUSH_Msk (0x1ul<<PHY1_PHY_DRV_RSP_BUF_FLUSH_Pos) JPHY1_PHY_DRV_CFG_BUF_FLUSH_Pos 0 JPHY1_PHY_DRV_CFG_BUF_FLUSH_Msk (0x1ul<<PHY1_PHY_DRV_CFG_BUF_FLUSH_Pos) ¢JPHY2_PHY_DRV_RSP_BUF_ERROR_Pos 28 £JPHY2_PHY_DRV_RSP_BUF_ERROR_Msk (0x1ul<<PHY2_PHY_DRV_RSP_BUF_ERROR_Pos) ¤JPHY2_PHY_DRV_SEQ_RX_END_ADDR_Pos 21 ¥JPHY2_PHY_DRV_SEQ_RX_END_ADDR_Msk (0x7ful<<PHY2_PHY_DRV_SEQ_RX_END_ADDR_Pos) ¦JPHY2_PHY_DRV_SEQ_TX_END_ADDR_Pos 14 §JPHY2_PHY_DRV_SEQ_TX_END_ADDR_Msk (0x7ful<<PHY2_PHY_DRV_SEQ_TX_END_ADDR_Pos) ¨JPHY2_PHY_DRV_SEQ_RX_STRT_ADDR_Pos 7 ©JPHY2_PHY_DRV_SEQ_RX_STRT_ADDR_Msk (0x7ful<<PHY2_PHY_DRV_SEQ_RX_STRT_ADDR_Pos) ªJPHY2_PHY_DRV_SEQ_TX_STRT_ADDR_Pos 0 «JPHY2_PHY_DRV_SEQ_TX_STRT_ADDR_Msk (0x7ful<<PHY2_PHY_DRV_SEQ_TX_STRT_ADDR_Pos) JPHY3_PHY_DRV_CFG_BUF_DIN_Pos 0 ®JPHY3_PHY_DRV_CFG_BUF_DIN_Msk (0xfffffffful<<PHY3_PHY_DRV_CFG_BUF_DIN_Pos) °JPHY4_PHY_DRV_RSP_BUF_DOUT_Pos 0 ±JPHY4_PHY_DRV_RSP_BUF_DOUT_Msk (0xfffffffful<<PHY4_PHY_DRV_RSP_BUF_DOUT_Pos) ³JPHY5_PHY_DRV_SET_CHAN_REG_ADDR_Pos 0 ´JPHY5_PHY_DRV_SET_CHAN_REG_ADDR_Msk (0xfful<<PHY5_PHY_DRV_SET_CHAN_REG_ADDR_Pos) ¶JINTR1_IC_RNG_DONE_Pos 3 ·JINTR1_IC_RNG_DONE_Msk (0x1ul<<INTR1_IC_RNG_DONE_Pos) ¸JINTR1_IC_SEC_DONE_Pos 2 ¹JINTR1_IC_SEC_DONE_Msk (0x1ul<<INTR1_IC_SEC_DONE_Pos) ºJINTR1_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_Pos 1 »JINTR1_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_Msk (0x1ul<<INTR1_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_Pos) ¼JINTR1_IC_PHY_DRV_CFG_DONE_Pos 0 ½JINTR1_IC_PHY_DRV_CFG_DONE_Msk (0x1ul<<INTR1_IC_PHY_DRV_CFG_DONE_Pos) ¿JINTCLR_IC_RNG_DONE_CLR_Pos 3 ÀJINTCLR_IC_RNG_DONE_CLR_Msk (0x1ul<<INTCLR_IC_RNG_DONE_CLR_Pos) ÁJINTCLR_IC_SEC_DONE_CLR_Pos 2 ÂJINTCLR_IC_SEC_DONE_CLR_Msk (0x1ul<<INTCLR_IC_SEC_DONE_CLR_Pos) ÃJINTCLR_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_CLR_Pos 1 ÄJINTCLR_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_CLR_Msk (0x1ul<<INTCLR_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_CLR_Pos) ÅJINTCLR_IC_PHY_DRV_CFG_DONE_CLR_Pos 0 ÆJINTCLR_IC_PHY_DRV_CFG_DONE_CLR_Msk (0x1ul<<INTCLR_IC_PHY_DRV_CFG_DONE_CLR_Pos) ÈJINTMSK_IC_RNG_DONE_MASK_Pos 3 ÉJINTMSK_IC_RNG_DONE_MASK_Msk (0x1ul<<INTMSK_IC_RNG_DONE_MASK_Pos) ÊJINTMSK_IC_SEC_DONE_MASK_Pos 2 ËJINTMSK_IC_SEC_DONE_MASK_Msk (0x1ul<<INTMSK_IC_SEC_DONE_MASK_Pos) ÌJINTMSK_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_MASK_Pos 1 ÍJINTMSK_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_MASK_Msk (0x1ul<<INTMSK_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_MASK_Pos) ÎJINTMSK_IC_PHY_DRV_CFG_DONE_MASK_Pos 0 ÏJINTMSK_IC_PHY_DRV_CFG_DONE_MASK_Msk (0x1ul<<INTMSK_IC_PHY_DRV_CFG_DONE_MASK_Pos) ÑJINTR4_IC_CLR_IRQ_Pos 6 ÒJINTR4_IC_CLR_IRQ_Msk (0x1ul<<INTR4_IC_CLR_IRQ_Pos) ÓJINTR4_IC_ONE_PULSE_FLAG_IRQ_Pos 5 ÔJINTR4_IC_ONE_PULSE_FLAG_IRQ_Msk (0x1ul<<INTR4_IC_ONE_PULSE_FLAG_IRQ_Pos) ÕJINTR4_IC_MODE_IRQ_Pos 4 ÖJINTR4_IC_MODE_IRQ_Msk (0x1ul<<INTR4_IC_MODE_IRQ_Pos) ×JINTR4_IC_PULSE_CNT_Pos 0 ØJINTR4_IC_PULSE_CNT_Msk (0xful<<INTR4_IC_PULSE_CNT_Pos) ÚJACTTMR1_ACTTMR_CMPR_MAX_EVENT_DIN_Pos 0 ÛJACTTMR1_ACTTMR_CMPR_MAX_EVENT_DIN_Msk (0xfffffffful<<ACTTMR1_ACTTMR_CMPR_MAX_EVENT_DIN_Pos) ÝJACTTMR2_ACTTMR_DISABLE_FLG_Pos 2 ÞJACTTMR2_ACTTMR_DISABLE_FLG_Msk (0x1ul<<ACTTMR2_ACTTMR_DISABLE_FLG_Pos) ßJACTTMR2_ACT_CLK_ACCUR_FLG_Pos 1 àJACTTMR2_ACT_CLK_ACCUR_FLG_Msk (0x1ul<<ACTTMR2_ACT_CLK_ACCUR_FLG_Pos) áJACTTMR2_ACTTMR_CMPR_MAX_EVENT_EN_Pos 0 âJACTTMR2_ACTTMR_CMPR_MAX_EVENT_EN_Msk (0x1ul<<ACTTMR2_ACTTMR_CMPR_MAX_EVENT_EN_Pos) äJACTTMR6_ACTTMR_CMPR_STRT_EVENT_DIN_Pos 0 åJACTTMR6_ACTTMR_CMPR_STRT_EVENT_DIN_Msk (0xfffffffful<<ACTTMR6_ACTTMR_CMPR_STRT_EVENT_DIN_Pos) çJACTTMR7_ACTTMR_CPTUR_BUS_DOUT_Pos 0 èJACTTMR7_ACTTMR_CPTUR_BUS_DOUT_Msk (0xfffffffful<<ACTTMR7_ACTTMR_CPTUR_BUS_DOUT_Pos) êJSECURE1_SEC_DECRYPT_EN_Pos 26 ëJSECURE1_SEC_DECRYPT_EN_Msk (0x1ul<<SECURE1_SEC_DECRYPT_EN_Pos) ìJSECURE1_SEC_AD_LEN_Pos 19 íJSECURE1_SEC_AD_LEN_Msk (0x7ful<<SECURE1_SEC_AD_LEN_Pos) îJSECURE1_SEC_MIC_LEN_Pos 17 ïJSECURE1_SEC_MIC_LEN_Msk (0x3ul<<SECURE1_SEC_MIC_LEN_Pos) ðJSECURE1_SEC_VLD_MAC_Pos 10 ñJSECURE1_SEC_VLD_MAC_Msk (0x7ful<<SECURE1_SEC_VLD_MAC_Pos) òJSECURE1_SEC_PKT_ENABLES_Pos 3 óJSECURE1_SEC_PKT_ENABLES_Msk (0x7ful<<SECURE1_SEC_PKT_ENABLES_Pos) ôJSECURE1_SEC_MODE_Pos 1 õJSECURE1_SEC_MODE_Msk (0x3ul<<SECURE1_SEC_MODE_Pos) öJSECURE1_SEC_ENABLE_Pos 0 ÷JSECURE1_SEC_ENABLE_Msk (0x1ul<<SECURE1_SEC_ENABLE_Pos) ùJSECURE2_SEC_IV3_Pos 24 úJSECURE2_SEC_IV3_Msk (0xfful<<SECURE2_SEC_IV3_Pos) ûJSECURE2_SEC_IV2_Pos 16 üJSECURE2_SEC_IV2_Msk (0xfful<<SECURE2_SEC_IV2_Pos) ýJSECURE2_SEC_IV1_Pos 8 þJSECURE2_SEC_IV1_Msk (0xfful<<SECURE2_SEC_IV1_Pos) ÿJSECURE2_SEC_IV0_Pos 0 KSECURE2_SEC_IV0_Msk (0xfful<<SECURE2_SEC_IV0_Pos) KSECURE3_SEC_IV7_Pos 24 KSECURE3_SEC_IV7_Msk (0xfful<<SECURE3_SEC_IV7_Pos) KSECURE3_SEC_IV6_Pos 16
KSECURE3_SEC_IV6_Msk (0xfful<<SECURE3_SEC_IV6_Pos) KSECURE3_SEC_IV5_Pos 8 KSECURE3_SEC_IV5_Msk (0xfful<<SECURE3_SEC_IV5_Pos) KSECURE3_SEC_IV4_Pos 0 KSECURE3_SEC_IV4_Msk (0xfful<<SECURE3_SEC_IV4_Pos) KSECURE4_SEC_KEY2_RX_ADDR_Pos 16 KSECURE4_SEC_KEY2_RX_ADDR_Msk (0xfffful<<SECURE4_SEC_KEY2_RX_ADDR_Pos) KSECURE4_SEC_KEY1_RX_ADDR_Pos 0 KSECURE4_SEC_KEY1_RX_ADDR_Msk (0xfffful<<SECURE4_SEC_KEY1_RX_ADDR_Pos) KSECURE5_SEC_KEY4_RX_ADDR_Pos 16 KSECURE5_SEC_KEY4_RX_ADDR_Msk (0xfffful<<SECURE5_SEC_KEY4_RX_ADDR_Pos) KSECURE5_SEC_KEY3_RX_ADDR_Pos 0 KSECURE5_SEC_KEY3_RX_ADDR_Msk (0xfffful<<SECURE5_SEC_KEY3_RX_ADDR_Pos) KSECURE6_SEC_KEY6_RX_ADDR_Pos 16 KSECURE6_SEC_KEY6_RX_ADDR_Msk (0xfffful<<SECURE6_SEC_KEY6_RX_ADDR_Pos) KSECURE6_SEC_KEY5_RX_ADDR_Pos 0 KSECURE6_SEC_KEY5_RX_ADDR_Msk (0xfffful<<SECURE6_SEC_KEY5_RX_ADDR_Pos) KSECURE7_SEC_MD_LEN_Pos 24 KSECURE7_SEC_MD_LEN_Msk (0x7ful<<SECURE7_SEC_MD_LEN_Pos) KSECURE7_SEC_KEY7_RX_ADDR_Pos 8 KSECURE7_SEC_KEY7_RX_ADDR_Msk (0xfffful<<SECURE7_SEC_KEY7_RX_ADDR_Pos) KSECURE7_SEC_PKT_CNT_TX_MSB_Pos 0 KSECURE7_SEC_PKT_CNT_TX_MSB_Msk (0xfful<<SECURE7_SEC_PKT_CNT_TX_MSB_Pos) ¡KSECURE8_SEC_PKT_CNT_TX_LSB_Pos 0 ¢KSECURE8_SEC_PKT_CNT_TX_LSB_Msk (0xfffffffful<<SECURE8_SEC_PKT_CNT_TX_LSB_Pos) ¤KSECURE9_SEC_PKT_CNT_RX_MSB_Pos 0 ¥KSECURE9_SEC_PKT_CNT_RX_MSB_Msk (0xfful<<SECURE9_SEC_PKT_CNT_RX_MSB_Pos) §KSECURE10_SEC_PKT_CNT_RX_LSB_Pos 0 ¨KSECURE10_SEC_PKT_CNT_RX_LSB_Msk (0xfffffffful<<SECURE10_SEC_PKT_CNT_RX_LSB_Pos) ªKTEST_MUX00_TST_MUX_SELECT_03_Pos 18 «KTEST_MUX00_TST_MUX_SELECT_03_Msk (0x3ful<<TEST_MUX00_TST_MUX_SELECT_03_Pos) ¬KTEST_MUX00_TST_MUX_SELECT_02_Pos 12 KTEST_MUX00_TST_MUX_SELECT_02_Msk (0x3ful<<TEST_MUX00_TST_MUX_SELECT_02_Pos) ®KTEST_MUX00_TST_MUX_SELECT_01_Pos 6 ¯KTEST_MUX00_TST_MUX_SELECT_01_Msk (0x3ful<<TEST_MUX00_TST_MUX_SELECT_01_Pos) °KTEST_MUX00_TST_MUX_SELECT_00_Pos 0 ±KTEST_MUX00_TST_MUX_SELECT_00_Msk (0x3ful<<TEST_MUX00_TST_MUX_SELECT_00_Pos) ³KRNG1_RNG_RING_SCRMB_SEL_Pos 1 ´KRNG1_RNG_RING_SCRMB_SEL_Msk (0x1ul<<RNG1_RNG_RING_SCRMB_SEL_Pos) µKRNG1_RNG_EN_Pos 0 ¶KRNG1_RNG_EN_Msk (0x1ul<<RNG1_RNG_EN_Pos) ¸KRNG2_RNG_DATA_Pos 0 ¹KRNG2_RNG_DATA_Msk (0xfffffffful<<RNG2_RNG_DATA_Pos) »KLL_MAC_CTRL_CTRL_LL_EN_Pos 0 ¼KLL_MAC_CTRL_CTRL_LL_EN_Msk (0x1ul<<LL_MAC_CTRL_CTRL_LL_EN_Pos) ¾KTEST_MUX01_TST_MUX_SELECT_07_Pos 18 ¿KTEST_MUX01_TST_MUX_SELECT_07_Msk (0x3ful<<TEST_MUX01_TST_MUX_SELECT_07_Pos) ÀKTEST_MUX01_TST_MUX_SELECT_06_Pos 12 ÁKTEST_MUX01_TST_MUX_SELECT_06_Msk (0x3ful<<TEST_MUX01_TST_MUX_SELECT_06_Pos) ÂKTEST_MUX01_TST_MUX_SELECT_05_Pos 6 ÃKTEST_MUX01_TST_MUX_SELECT_05_Msk (0x3ful<<TEST_MUX01_TST_MUX_SELECT_05_Pos) ÄKTEST_MUX01_TST_MUX_SELECT_04_Pos 0 ÅKTEST_MUX01_TST_MUX_SELECT_04_Msk (0x3ful<<TEST_MUX01_TST_MUX_SELECT_04_Pos) ÇKTEST_MUX02_TST_MUX_SELECT_11_Pos 18 ÈKTEST_MUX02_TST_MUX_SELECT_11_Msk (0x3ful<<TEST_MUX02_TST_MUX_SELECT_11_Pos) ÉKTEST_MUX02_TST_MUX_SELECT_10_Pos 12 ÊKTEST_MUX02_TST_MUX_SELECT_10_Msk (0x3ful<<TEST_MUX02_TST_MUX_SELECT_10_Pos) ËKTEST_MUX02_TST_MUX_SELECT_09_Pos 6 ÌKTEST_MUX02_TST_MUX_SELECT_09_Msk (0x3ful<<TEST_MUX02_TST_MUX_SELECT_09_Pos) ÍKTEST_MUX02_TST_MUX_SELECT_08_Pos 0 ÎKTEST_MUX02_TST_MUX_SELECT_08_Msk (0x3ful<<TEST_MUX02_TST_MUX_SELECT_08_Pos) ÐKTEST_MUX03_TST_MUX_SELECT_15_Pos 18 ÑKTEST_MUX03_TST_MUX_SELECT_15_Msk (0x3ful<<TEST_MUX03_TST_MUX_SELECT_15_Pos) ÒKTEST_MUX03_TST_MUX_SELECT_14_Pos 12 ÓKTEST_MUX03_TST_MUX_SELECT_14_Msk (0x3ful<<TEST_MUX03_TST_MUX_SELECT_14_Pos) ÔKTEST_MUX03_TST_MUX_SELECT_13_Pos 6 ÕKTEST_MUX03_TST_MUX_SELECT_13_Msk (0x3ful<<TEST_MUX03_TST_MUX_SELECT_13_Pos) ÖKTEST_MUX03_TST_MUX_SELECT_12_Pos 0 ×KTEST_MUX03_TST_MUX_SELECT_12_Msk (0x3ful<<TEST_MUX03_TST_MUX_SELECT_12_Pos) ÚKR00_CTL_TX_PAYLOAD_LEN_Pos 24 ÛKR00_CTL_TX_PAYLOAD_LEN_Msk (0xFFul<<R00_CTL_TX_PAYLOAD_LEN_Pos) ÜKR00_CTL_RX_PAYLOAD_LEN_Pos 16 ÝKR00_CTL_RX_PAYLOAD_LEN_Msk (0xFFul<<R00_CTL_RX_PAYLOAD_LEN_Pos) ÞKR00_CTL_CRC_ACCESS_ADR_Pos 15 ßKR00_CTL_CRC_ACCESS_ADR_Msk (0x1ul<<R00_CTL_CRC_ACCESS_ADR_Pos) àKR00_CTL_CRC24_EN_Pos 14 áKR00_CTL_CRC24_EN_Msk (0x1ul<<R00_CTL_CRC24_EN_Pos) âKR00_CTL_ADDR_BYTE_LEN_Pos 12 ãKR00_CTL_ADDR_BYTE_LEN_Msk (0x3ul<<R00_CTL_ADDR_BYTE_LEN_Pos) äKR00_CTL_DPY_EN_Pos 11 åKR00_CTL_DPY_EN_Msk (0x1ul<<R00_CTL_DPY_EN_Pos) æKR00_CTL_CRC_EN_Pos 10 çKR00_CTL_CRC_EN_Msk (0x1ul<<R00_CTL_CRC_EN_Pos) èKR00_CTL_CRC_SEL16_Pos 9 éKR00_CTL_CRC_SEL16_Msk (0x1ul<<R00_CTL_CRC_SEL16_Pos) êKR00_CTL_SCR_EN_Pos 8 ëKR00_CTL_SCR_EN_Msk (0x1ul<<R00_CTL_SCR_EN_Pos) ìKR00_CTL_NRF_ENHANCE_Pos 7 íKR00_CTL_NRF_ENHANCE_Msk (0x1ul<<R00_CTL_NRF_ENHANCE_Pos) îKR00_CTL_ENHANCE_Pos 6 ïKR00_CTL_ENHANCE_Msk (0x1ul<<R00_CTL_ENHANCE_Pos) ðKR00_CTL_BW_MODE_Pos 5 ñKR00_CTL_BW_MODE_Msk (0x1ul<<R00_CTL_BW_MODE_Pos) òKR00_CTL_CHIP_MODE_Pos 3 óKR00_CTL_CHIP_MODE_Msk (0x3ul<<R00_CTL_CHIP_MODE_Pos) ôKR00_CTL_RX_ACK_PAYLOAD_EN_Pos 2 õKR00_CTL_RX_ACK_PAYLOAD_EN_Msk (0x1ul<<R00_CTL_RX_ACK_PAYLOAD_EN_Pos) öKR00_CTL_TX_NOACK_EN_Pos 1 ÷KR00_CTL_TX_NOACK_EN_Msk (0x1ul<<R00_CTL_TX_NOACK_EN_Pos) øKR00_CTL_PRI_RX_Pos 0 ùKR00_CTL_PRI_RX_Msk (0x1ul<<R00_CTL_PRI_RX_Pos) ûKR01_INT_PRI_RX_PID_Pos 29 üKR01_INT_PRI_RX_PID_Msk (0x3ul<<R01_INT_PRI_RX_PID_Pos) ýKR01_INT_PRI_TX_PID_Pos 27 þKR01_INT_PRI_TX_PID_Msk (0x3ul<<R01_INT_PRI_TX_PID_Pos) ÿKR01_INT_RX_LENGTH_ERR_Pos 26 LR01_INT_RX_LENGTH_ERR_Msk (0x1ul<<R01_INT_RX_LENGTH_ERR_Pos) LR01_INT_RX_ACCADDR_ERR_Pos 25 LR01_INT_RX_ACCADDR_ERR_Msk (0x1ul<<R01_INT_RX_ACCADDR_ERR_Pos) LR01_INT_RX_ACCADDR_ERR_MASK_Pos 23 LR01_INT_RX_ACCADDR_ERR_MASK_Msk (0x1ul<<R01_INT_RX_ACCADDR_ERR_MASK_Pos)
LR01_INT_RX_LENGTH_ERR_MASK_Pos 22 LR01_INT_RX_LENGTH_ERR_MASK_Msk (0x1ul<<R01_INT_RX_LENGTH_ERR_MASK_Pos) LR01_INT_PRI_ENDIAN_Pos 21 LR01_INT_PRI_ENDIAN_Msk (0x1ul<<R01_INT_PRI_ENDIAN_Pos) LR01_INT_PRI_TX_DONE_IRQ_EN_Pos 20 LR01_INT_PRI_TX_DONE_IRQ_EN_Msk (0x1ul<<R01_INT_PRI_TX_DONE_IRQ_EN_Pos) LR01_INT_PRI_RX_DONE_IRQ_EN_Pos 19 LR01_INT_PRI_RX_DONE_IRQ_EN_Msk (0x1ul<<R01_INT_PRI_RX_DONE_IRQ_EN_Pos) LR01_INT_PRI_RX_GOON_Pos 18 LR01_INT_PRI_RX_GOON_Msk (0x1ul<<R01_INT_PRI_RX_GOON_Pos) LR01_INT_PRI_RST_Pos 17 LR01_INT_PRI_RST_Msk (0x1ul<<R01_INT_PRI_RST_Pos) LR01_INT_EXIT_RX_Pos 16 LR01_INT_EXIT_RX_Msk (0x1ul<<R01_INT_EXIT_RX_Pos) LR01_INT_TX_DONE_IRQ_FLAG_Pos 15 LR01_INT_TX_DONE_IRQ_FLAG_Msk (0x1ul<<R01_INT_TX_DONE_IRQ_FLAG_Pos) LR01_INT_RX_DONE_IRQ_FLAG_Pos 14 LR01_INT_RX_DONE_IRQ_FLAG_Msk (0x1ul<<R01_INT_RX_DONE_IRQ_FLAG_Pos) LR01_INT_RX_PID_ERR_IRQ_FLAG_Pos 13 LR01_INT_RX_PID_ERR_IRQ_FLAG_Msk (0x1ul<<R01_INT_RX_PID_ERR_IRQ_FLAG_Pos) LR01_INT_RX_CRC_ERR_Pos 12 LR01_INT_RX_CRC_ERR_Msk (0x1ul<<R01_INT_RX_CRC_ERR_Pos) LR01_INT_TX_TIMEOUT_IRQ_Pos 11 LR01_INT_TX_TIMEOUT_IRQ_Msk (0x1ul<<R01_INT_TX_TIMEOUT_IRQ_Pos) LR01_INT_TX_IRQ_Pos 10 LR01_INT_TX_IRQ_Msk (0x1ul<<R01_INT_TX_IRQ_Pos) LR01_INT_RX_IRQ_Pos 9 LR01_INT_RX_IRQ_Msk (0x1ul<<R01_INT_RX_IRQ_Pos) ¡LR01_INT_IRQ_CLR_EN_Pos 8 ¢LR01_INT_IRQ_CLR_EN_Msk (0x1ul<<R01_INT_IRQ_CLR_EN_Pos) £LR01_INT_RX_CRC_ERR_MASK_Pos 7 ¤LR01_INT_RX_CRC_ERR_MASK_Msk (0x1ul<<R01_INT_RX_CRC_ERR_MASK_Pos) ¥LR01_INT_PID_ERR_MASK_Pos 6 ¦LR01_INT_PID_ERR_MASK_Msk (0x1ul<<R01_INT_PID_ERR_MASK_Pos) §LR01_INT_TX_TIMEOUT_IRQ_MASK_Pos 5 ¨LR01_INT_TX_TIMEOUT_IRQ_MASK_Msk (0x1ul<<R01_INT_TX_TIMEOUT_IRQ_MASK_Pos) ©LR01_INT_TX_IRQ_MASK_Pos 4 ªLR01_INT_TX_IRQ_MASK_Msk (0x1ul<<R01_INT_TX_IRQ_MASK_Pos) «LR01_INT_RX_IRQ_MASK_Pos 3 ¬LR01_INT_RX_IRQ_MASK_Msk (0x1ul<<R01_INT_RX_IRQ_MASK_Pos) LR01_INT_MULTI_RX_ACC_ADR_Pos 0 ®LR01_INT_MULTI_RX_ACC_ADR_Msk (0x7ul<<R01_INT_MULTI_RX_ACC_ADR_Pos) ±LR02_TMR_CTL_RX_WAIT_TIME_Pos 16 ²LR02_TMR_CTL_RX_WAIT_TIME_Msk (0xFFFFul<<R02_TMR_CTL_RX_WAIT_TIME_Pos) ³LR02_TMR_CTL_RX_WAIT_TIME_EN_Pos 15 ´LR02_TMR_CTL_RX_WAIT_TIME_EN_Msk (0X1ul<<R02_TMR_CTL_RX_WAIT_TIME_EN_Pos) µLR02_TMR_CTL_TRX_TRANS_WAIT_TIME_Pos 0 ¶LR02_TMR_CTL_TRX_TRANS_WAIT_TIME_Msk (0x7FFFul<<R02_TMR_CTL_TRX_TRANS_WAIT_TIME_Pos) ¸LR03_RX_ADDR_L_L32B_Pos 0 ¹LR03_RX_ADDR_L_L32B_Msk (0xFFFFFFFFul<<R03_RX_ADDR_L_L32B_Pos) ½LR04_RX_CTL_RX_HEADER1_Pos 24 ¾LR04_RX_CTL_RX_HEADER1_Msk (0xFFul<<R04_RX_CTL_RX_HEADER1_Pos) ¿LR04_RX_CTL_RX_HEADER_Pos 16 ÀLR04_RX_CTL_RX_HEADER_Msk (0xFFul<<R04_RX_CTL_RX_HEADER_Pos) ÁLR04_RX_CTL_RX_FEC_Pos 15 ÂLR04_RX_CTL_RX_FEC_Msk (0x1ul<<R04_RX_CTL_RX_FEC_Pos) ÃLR04_RX_CTL_TX_FEC_Pos 14 ÄLR04_RX_CTL_TX_FEC_Msk (0x1ul<<R04_RX_CTL_TX_FEC_Pos) ÅLR04_RX_CTL_CI_MODE_Pos 12 ÆLR04_RX_CTL_CI_MODE_Msk (0x3ul<<R04_RX_CTL_CI_MODE_Pos) ÇLR04_RX_CTL_NORMAL_M1_Pos 11 ÈLR04_RX_CTL_NORMAL_M1_Msk (0x1ul<<R04_RX_CTL_NORMAL_M1_Pos) ÉLR04_RX_CTL_HDR_LEN_NUMB_Pos 9 ÊLR04_RX_CTL_HDR_LEN_NUMB_Msk (0x3ul<<R04_RX_CTL_HDR_LEN_NUMB_Pos) ËLR04_RX_CTL_HDR_LEN_EXIST_Pos 8 ÌLR04_RX_CTL_HDR_LEN_EXIST_Msk (0x1ul<<R04_RX_CTL_HDR_LEN_EXIST_Pos) ÍLR04_RX_CTL_M8B_Pos 0 ÎLR04_RX_CTL_M8B_Msk (0xFFul<<R04_RX_CTL_M8B_Pos) ÐLR05_TX_ADDR_L_L32B_Pos 0 ÑLR05_TX_ADDR_L_L32B_Msk (0xFFFFFFFFul<<R05_TX_ADDR_L_L32B_Pos) ÓLR06_TX_CTL_RX_HEADER1_Pos 24 ÔLR06_TX_CTL_RX_HEADER1_Msk (0xFFul<<R06_TX_CTL_RX_HEADER1_Pos) ÕLR06_TX_CTL_RX_HEADER_Pos 16 ÖLR06_TX_CTL_RX_HEADER_Msk (0xFFul<<R06_TX_CTL_RX_HEADER_Pos) ×LR06_TX_CTL_MAX_LENGTH_EN_Pos 15 ØLR06_TX_CTL_MAX_LENGTH_EN_Msk (0x1ul<<R06_TX_CTL_MAX_LENGTH_EN_Pos) ÙLR06_TX_CTL_WHITENING_INIT_Pos 8 ÚLR06_TX_CTL_WHITENING_INIT_Msk (0x7Ful<<R06_TX_CTL_WHITENING_INIT_Pos) ÛLR06_TX_CTL_M8B_Pos 0 ÜLR06_TX_CTL_M8B_Msk (0xFFul<<R06_TX_CTL_M8B_Pos) ÞLR07_SRAM_CTL_RX_START_ADDR_Pos 17 ßLR07_SRAM_CTL_RX_START_ADDR_Msk (0x7FFul<<R07_SRAM_CTL_RX_START_ADDR_Pos) àLR07_SRAM_CTL_RX_READY_Pos 16 áLR07_SRAM_CTL_RX_READY_Msk (0x1ul<<R07_SRAM_CTL_RX_READY_Pos) âLR07_SRAM_CTL_TX_START_ADDR_Pos 1 ãLR07_SRAM_CTL_TX_START_ADDR_Msk (0x7FFul<<R07_SRAM_CTL_TX_START_ADDR_Pos) äLR07_SRAM_CTL_TX_READY_Pos 0 åLR07_SRAM_CTL_TX_READY_Msk (0x1<<R07_SRAM_CTL_TX_READY_Pos) èLR0F_RX_ADDR4_M8B_Pos 24 éLR0F_RX_ADDR4_M8B_Msk (0xFFul<<R0F_RX_ADDR4_M8B_Pos) êLR0F_RX_ADDR3_M8B_Pos 16 ëLR0F_RX_ADDR3_M8B_Msk (0xFFul<<R0F_RX_ADDR3_M8B_Pos) ìLR0F_RX_ADDR2_M8B_Pos 8 íLR0F_RX_ADDR2_M8B_Msk (0xFFul<<R0F_RX_ADDR2_M8B_Pos) îLR0F_RX_ADDR1_M8B_Pos 0 ïLR0F_RX_ADDR1_M8B_Msk (0xFFul<<R0F_RX_ADDR1_M8B_Pos) òLR10_RX_ADDR7_EN_Pos 31 óLR10_RX_ADDR7_EN_Msk (0x1ul<<R0F_RX_ADDR7_EN_Pos) ôLR10_RX_ADDR6_EN_Pos 30 õLR10_RX_ADDR6_EN_Msk (0x1ul<<R0F_RX_ADDR6_EN_Pos) öLR10_RX_ADDR5_EN_Pos 29 ÷LR10_RX_ADDR5_EN_Msk (0x1ul<<R0F_RX_ADDR5_EN_Pos) øLR10_RX_ADDR4_EN_Pos 28 ùLR10_RX_ADDR4_EN_Msk (0x1ul<<R0F_RX_ADDR4_EN_Pos) úLR10_RX_ADDR3_EN_Pos 27 ûLR10_RX_ADDR3_EN_Msk (0x1ul<<R0F_RX_ADDR3_EN_Pos) üLR10_RX_ADDR2_EN_Pos 26 ýLR10_RX_ADDR2_EN_Msk (0x1ul<<R0F_RX_ADDR2_EN_Pos) þLR10_RX_ADDR1_EN_Pos 25 ÿLR10_RX_ADDR1_EN_Msk (0x1ul<<R0F_RX_ADDR1_EN_Pos) MR10_RX_ADDR0_EN_Pos 24 MR10_RX_ADDR0_EN_Msk (0x1ul<<R0F_RX_ADDR0_EN_Pos) MR10_RX_ADDR7_M8B_Pos 16 MR10_RX_ADDR7_M8B_Msk (0xFFul<<R0F_RX_ADDR3_M8B_Pos) MR10_RX_ADDR6_M8B_Pos 8
MR10_RX_ADDR6_M8B_Msk (0xFFul<<R0F_RX_ADDR2_M8B_Pos) MR10_RX_ADDR5_M8B_Pos 0 MR10_RX_ADDR5_M8B_Msk (0xFFul<<R0F_RX_ADDR1_M8B_Pos) MR11_CFG_NRF_PRE_SEL_Pos 25 MR11_CFG_NRF_PRE_SEL_Msk (0x1ul<<R11_CFG_NRF_PRE_SEL_Pos) MR11_CFG_RX_DATA_REV_EN_Pos 24 MR11_CFG_RX_DATA_REV_EN_Msk (0x1ul<<R11_CFG_RX_DATA_REV_EN_Pos) MR11_CFG_PRE_SYNC_12B_EN_Pos 23 MR11_CFG_PRE_SYNC_12B_EN_Msk (0x1ul<<R11_CFG_PRE_SYNC_12B_EN_Pos) MR11_CFG_PRE_SYNC_8B_EN_Pos 22 MR11_CFG_PRE_SYNC_8B_EN_Msk (0x1ul<<R11_CFG_PRE_SYNC_8B_EN_Pos) MR11_CFG_PRE_SYNC_4B_EN_Pos 21 MR11_CFG_PRE_SYNC_4B_EN_Msk (0x1ul<<R11_CFG_PRE_SYNC_4B_EN_Pos) MR11_CFG_PRE_SYNC_EN_Pos 20 MR11_CFG_PRE_SYNC_EN_Msk (0x1ul<<R11_CFG_PRE_SYNC_EN_Pos) MR11_CFG_250K_MODE_EN_Pos 19 MR11_CFG_250K_MODE_EN_Msk (0x1ul<<R11_CFG_250K_MODE_EN_Pos) MR11_CFG_B250K_PRE_SEL_Pos 18 MR11_CFG_B250K_PRE_SEL_Msk (0x1ul<<R11_CFG_B250K_PRE_SEL_Pos) MR11_CFG_LQI_EN_Pos 17 MR11_CFG_LQI_EN_Msk (0x1ul<<R11_CFG_LQI_EN_Pos) MR11_CFG_RX_PID_MANUAL_Pos 15 MR11_CFG_RX_PID_MANUAL_Msk (0x3ul<<R11_CFG_RX_PID_MANUAL_Pos) MR11_CFG_TX_PID_MANUAL_Pos 13 MR11_CFG_TX_PID_MANUAL_Msk (0x3ul<<R11_CFG_TX_PID_MANUAL_Pos) ¡MR11_CFG_PREAM_2BYTE_EN_Pos 12 ¢MR11_CFG_PREAM_2BYTE_EN_Msk (0x1ul<<R11_CFG_PREAM_2BYTE_EN_Pos) £MR11_CFG_B250K_INVERT_EN_Pos 11 ¤MR11_CFG_B250K_INVERT_EN_Msk (0x1ul<<R11_CFG_B250K_INVERT_EN_Pos) ¥MR11_CFG_B250K_SCR_INIT_VALUE_Pos 9 ¦MR11_CFG_B250K_SCR_INIT_VALUE_Msk (0x3ul<<R11_CFG_B250K_SCR_INIT_VALUE_Pos) §MR11_CFG_B250K_PREAM_Pos 6 ¨MR11_CFG_B250K_PREAM_Msk (0x7ul<<R11_CFG_B250K_PREAM_Pos) ©MR11_CFG_B250K_MODE_Pos 5 ªMR11_CFG_B250K_MODE_Msk (0x1ul<<R11_CFG_B250K_MODE_Pos) «MR11_CFG_ADDR_ERR_THR_Pos 2 ¬MR11_CFG_ADDR_ERR_THR_Msk (0x7ul<<R11_CFG_ADDR_ERR_THR_Pos) MR11_CFG_PID_MANUAL_EN_Pos 1 ®MR11_CFG_PID_MANUAL_EN_Msk (0x1ul<<R11_CFG_PID_MANUAL_EN_Pos) ¯MR11_CFG_ADDR_SCR_DIS_Pos 0 °MR11_CFG_ADDR_SCR_DIS_Msk (0x1ul<<R11_CFG_ADDR_SCR_DIS_Pos) ºMCR_BASE (0x00400000Ul) »MSRAM_BASE (0x20000000UL) ½MAHB1_PERIPH_BASE (0x40000000UL) ÀMAPB1_PERIPH_BASE (0x40000000UL) ÁMAPB2_PERIPH_BASE (0x40010000UL) ÃMBLE_PERIPH_BASE (0x50020000UL) ÈMI2C0_BASE (APB1_PERIPH_BASE + 0x00000000UL) ÉMSPI0_BASE (APB1_PERIPH_BASE + 0x00001000UL) ÊMUART0_BASE (APB1_PERIPH_BASE + 0x00003000UL) ËMPWM_BASE (APB1_PERIPH_BASE + 0x00004000UL) ÌMADC_BASE (APB1_PERIPH_BASE + 0x00005000UL) ÍMWDT_BASE (APB1_PERIPH_BASE + 0x00006000UL) ÎMWWDT_BASE (APB1_PERIPH_BASE + 0x00007000UL) ÏMTIMER0_BASE (APB1_PERIPH_BASE + 0x00008000UL) ÓMSPI1_BASE (APB2_PERIPH_BASE + 0x00001000UL) ÔMUART1_BASE (APB2_PERIPH_BASE + 0x00003000UL) ÕMTIMER1_BASE (APB2_PERIPH_BASE + 0x00004000UL) ÖMTIMER2_BASE (APB2_PERIPH_BASE + 0x00005000UL) ×MTRIM_BASE (APB2_PERIPH_BASE + 0x00006000UL) ÜMGPIO_BASE (AHB1_PERIPH_BASE + 0x00020000UL) ÝMP0_BASE (GPIO_BASE + 0x00000000UL) ÞMP1_BASE (GPIO_BASE + 0x00000040UL) ßMP2_BASE (GPIO_BASE + 0x00000080UL) àMP3_BASE (GPIO_BASE + 0x000000C0UL) áMGPIO_DBNCECON_BASE (GPIO_BASE + 0x00000180UL) âMGPIOBIT0_BASE (GPIO_BASE + 0x00000200UL) ãMGPIOBIT1_BASE (GPIO_BASE + 0x00000220UL) äMGPIOBIT2_BASE (GPIO_BASE + 0x00000240UL) åMGPIOBIT3_BASE (GPIO_BASE + 0x00000260UL) çMSYS_BASE (AHB1_PERIPH_BASE + 0x00030000UL) èMCLK_BASE (AHB1_PERIPH_BASE + 0x00040000UL) éMFLCTL_BASE (AHB1_PERIPH_BASE + 0x00050000UL) êMFLCTL_BASE1 (AHB1_PERIPH_BASE + 0x00050400UL) ëMDMA_BASE (AHB1_PERIPH_BASE + 0x00060000UL) ìMANA_BASE (AHB1_PERIPH_BASE + 0x00070000UL) íMEFUSE_BASE (AHB1_PERIPH_BASE + 0x00080000UL) îMUSB_BASE (AHB1_PERIPH_BASE + 0x000A0000UL) ïMUSBDMA_BASE (AHB1_PERIPH_BASE + 0x000A0200UL) òMPRI_RF_BASE (BLE_PERIPH_BASE + 0X00000400UL) öMCR ((CR_T *) CR_BASE) ùMI2C0 ((I2C_T *) I2C0_BASE ) úMSPI0 ((SPI_T *) SPI0_BASE ) ûMUART0 ((UART_T *) UART0_BASE ) üMPWM ((PWM_T *) PWM_BASE ) ýMADC ((ADC_T *) ADC_BASE ) þMWDT ((WDT_T *) WDT_BASE ) ÿMWWDT ((WWDT_T *) WWDT_BASE ) NTIMER0 ((TIMER_T *) TIMER0_BASE ) NSPI1 ((SPI_T *) SPI1_BASE )
NUART1 ((UART_T *) UART1_BASE ) NTIMER1 ((TIMER_T *) TIMER1_BASE ) NTIMER2 ((TIMER_T *) TIMER2_BASE ) NTRIM ((TRIM_T *) TRIM_BASE ) NGPIO ((GPIO_T *) GPIO_BASE ) NP0 ((GPIO_T *) P0_BASE ) NP1 ((GPIO_T *) P1_BASE ) NP2 ((GPIO_T *) P2_BASE ) NP3 ((GPIO_T *) P3_BASE ) NGPIO_DB ((GPIO_DB_T *) GPIO_DBNCECON_BASE) NSYS ((SYS_T *) SYS_BASE ) NCLK ((CLK_T *) CLK_BASE ) NFLCTL ((FLCTL_T *) FLCTL_BASE ) NFLCTL_BUFF ((FLCTL_W_BUFF_T *)FLCTL_BASE1 ) NDMA ((DMA_T *) DMA_BASE ) NANA ((ANA_T *) ANA_BASE ) NEFUSE ((EFUSE_T *) EFUSE_BASE ) NUSB ((USB_T *) USB_BASE ) NUSBDMA ((USBDMA_T *) USBDMA_BASE ) NPRI_RF ((PRI_RF_T *) PRI_RF_BASE ) ¶NTRUE (1) ºNFALSE (0) ¾NBIT0 (0x00000001UL) ¿NBIT1 (0x00000002UL) ÀNBIT2 (0x00000004UL) ÁNBIT3 (0x00000008UL) ÂNBIT4 (0x00000010UL) ÃNBIT5 (0x00000020UL) ÄNBIT6 (0x00000040UL) ÅNBIT7 (0x00000080UL) ÆNBIT8 (0x00000100UL) ÇNBIT9 (0x00000200UL) ÈNBIT10 (0x00000400UL) ÉNBIT11 (0x00000800UL) ÊNBIT12 (0x00001000UL) ËNBIT13 (0x00002000UL) ÌNBIT14 (0x00004000UL) ÍNBIT15 (0x00008000UL) ÎNBIT16 (0x00010000UL) ÏNBIT17 (0x00020000UL) ÐNBIT18 (0x00040000UL) ÑNBIT19 (0x00080000UL) ÒNBIT20 (0x00100000UL) ÓNBIT21 (0x00200000UL) ÔNBIT22 (0x00400000UL) ÕNBIT23 (0x00800000UL) ÖNBIT24 (0x01000000UL) ×NBIT25 (0x02000000UL) ØNBIT26 (0x04000000UL) ÙNBIT27 (0x08000000UL) ÚNBIT28 (0x10000000UL) ÛNBIT29 (0x20000000UL) ÜNBIT30 (0x40000000UL) ÝNBIT31 (0x80000000UL) àNBIT(x) (0x1UL << (x)) äNBYTE0_Msk (0x000000FF) åNBYTE1_Msk (0x0000FF00) æNBYTE2_Msk (0x00FF0000) çNBYTE3_Msk (0xFF000000) éNGET_BYTE0(u32Param) ((u32Param & BYTE0_Msk) ) êNGET_BYTE1(u32Param) ((u32Param & BYTE1_Msk) >> 8) ëNGET_BYTE2(u32Param) ((u32Param & BYTE2_Msk) >> 16) ìNGET_BYTE3(u32Param) ((u32Param & BYTE3_Msk) >> 24) ïNSET_BIT(REG,BIT) ((REG) |= (BIT)) ñNCLEAR_BIT(REG,BIT) ((REG) &= ~(BIT)) óNREAD_BIT(REG,BIT) ((REG) & (BIT)) õNCLEAR_REG(REG) ((REG) = (0x0)) ÷NWRITE_REG(REG,VAL) ((REG) = (VAL)) ùNREAD_REG(REG) ((REG)) ûNMODIFY_REG(REG,CLEARMASK,SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) Oassert_param(expr) ((void)0) OFREQ_RCL 32000 OFREQ_XTL 32768 ONVIC_SystemReset ¤O ¥O
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¦O §O ¨O ©OªO«O¬OO®O¯O°O±O²O³O´OµO¶O·O Ô É ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\ C:\Keil_v5\ARM\ARMCC\Bin\..\include\ ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\ ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\ ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\radio\prf_lib\include\ PanSeries.h stdio.h stdlib.h stdint.h string.h core_cm0.h system_PanSeries.h stdbool.h pan_sys_log.h pan_sys.h pan_clk.h pan_adc.h pan_fmc.h pan_dmac.h pan_gpio.h pan_spi.h pan_uart.h pan_i2c.h pan_timer.h pan_pwm.h pan_wdt.h pan_wwdt.h pan_lp.h pan_efuse.h pan_pri_rf.h pan_clktrim.h pan_power.h pan_hal.h Ô
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..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\PanSeries.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil IRQn NonMaskableInt_IRQn rHardFault_IRQn sSVCall_IRQn {PendSV_IRQn ~SysTick_IRQn I2C0_IRQn SPI0_IRQn UART0_IRQn PWM_IRQn ADC_IRQn WDT_IRQn WWDT_IRQn TMR0_IRQn SPI1_IRQn
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LL_IRQn UART1_IRQn TMR1_IRQn TMR2_IRQn GPIO0_IRQn GPIO1_IRQn GPIO2_IRQn GPIO3_IRQn USBDMA_IRQn USB_IRQn TRIM_IRQn DMA_IRQn BOD_IRQn SLPTMR_IRQn LP_IRQn PIRQn_Type ?ªRESET SET PFlagStatus W(PITStatus W4æDISABLE ENABLE PFunctionalState ÌY/*ñ$ CTL q# CMP q# INTSTS q# CNT }# CAP }# EXTCTL q# EINTSTS q# CMP1 q# CMP2 q# tY Y twPTIMER_T ý±* TRIM_EN q# TRIM_CODE q# TRIM_CTRL q# TRIM_INT q# TRIM_CAL_CNT q# TRIM_IDEAL_CNT q# TRIM_REAL_CNT }# PTRIM_T ¤* $ MODE q# DINOFF q# DOUT q# DATMSK q# PIN q# DBEN q# INTTYPE q# INTEN q# INTSRC q# PGPIO_T %*À DBCTL q# PGPIO_DB_T ®¯*Ð p DAT }# ê } RESERVED0 á# CTL q# CHEN q#$ CMP0 q#( CMP1 q#, STATUS q#0Á
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} RESERVED1 8#4 TRGDLY q#D EXTSMPT q#H SEQCTL q#L SEQDAT1 }#P SEQDAT2 }#T CTL2 q#X° } RESERVED2 §#\ BV_CTL q#l PADC_T ÒÀ *ç P P0_MFP q# P1_MFP q# P2_MFP q# P3_MFP q# £ q RESV # REGLCTL q#@ STATUS q#D CTRL0 q#H CTRL1 q#L PSYS_T Þ£ *< RSTSTS q# IPRST0 q# IPRST1 q# BODCTL_3V q# BLDBCTL_3V q# CLK_TOP_CTRL_3V q# RCL_CTRL_3V q# RCH_CTRL q# XTL_CTRL_3V q# XTH_CTRL q#$ DPLL_CTRL q#( AHB_CLK_CTRL q#, APB1_CLK_CTRL q#0 APB2_CLK_CTRL q#4 MEAS_CLK_CTRL q#8 PCLK_T uò *´ CTL q# ALTCTL q# PWDT_T ì#*ù RLDCNT q# CTL q# STATUS q# CNT }# PWWDT_T Â%*ô CLKPSC q# CLKDIV q# CTL q# PERIOD0 q# PERIOD1 q# PERIOD2 q# PERIOD3 q# PERIOD4 q# PERIOD5 q# PERIOD6 q#$ PERIOD7 q#( CMPDAT0 q#, CMPDAT1 q#0 CMPDAT2 q#4 CMPDAT3 q#8 CMPDAT4 q#< CMPDAT5 q#@ CMPDAT6 q#D CMPDAT7 q#H CTL2 q#L FLAG q#P INTEN q#T INTSTS q#X POEN q#\ì} RESERVED0 c #` DTCTL q#d ADCTCTL0 q#h ADCTCTL1 q#l ADCTSTS0 q#p ADCTSTS1 q#tÓ} RESERVED1 Ê #x PCACTL q# PPWM_T ².*$ X_FL_CTL q# X_FL_TRIG
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# X_FL_CONFIG
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#Ã
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X_FL_WD :
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# X_FL_X_MODE q# X_FL_X2_CMD
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# X_FL_X4_CMD
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# X_FL_DP_CMD
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# X_FL_RDP_CMD
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# X_FL_REMAP_ADDR q# X_FL_DP_CTL q# X_FL_IRQ_CTL q# X_FL_SUS_RESU_CMD q# t: PFLCTL_T
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ë8*ï
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ÿ X_FL_BUFFER % # PFLCTL_W_BUFF_T ð8* X_CACHE_EN q# X_RESVR q# X_CACHE_INI q# PCR_T Z ×9*( CR0 q# CR1 q# DR q# SR q# CPSR q# IMSC q# RIS q# MIS q# ICR q# DMACR q#$ PSPI_T ë9*ìÐ RBR_THR_DLL q# IER_DLH q# IIR_FCR q# LCR q# MCR q# LSR q# MSR q# SCR q# LPDLL q# LPDLH q#$³} RESERVED0 ª #( USR q#| TFL q# RFL q#ð} RESERVED1 ç # HTX q#¤ DMASA q#¨¥} RESERVED2 #¬ DLF q#À RAR q#Ä TAR q#È LCR_EXT q#Ì PUART_T # >*Ð X SAR_L q# SAR_H q# DAR_L q# DAR_H q# ¼q RESERVED0 ³ # CTL_L q# CTL_H q# ðq RESERVED1 ç # CFG_L q#@ CFG_H q#D SGR_L q#H SGR_H q#L DSR_L q#P DSR_H q#T *Ô$¨Þ { CH U# RAW_TFR_L q#À RAW_TFR_H q#Ä RAW_BLOCK_L q#È RAW_BLOCK_H q#Ì RAW_SRCTRAN_L q#Ð RAW_SRCTRAN_H q#Ô RAW_DSTTRAN_L q#Ø RAW_DSTTRAN_H q#Ü RAW_ERR_L q#à RAW_ERR_H q#ä STATUS_TFR_L q#è STATUS_TFR_H q#ì STATUS_BLOCK_L q#ð STATUS_BLOCK_H q#ô STATUS_SRCTRAN_L q#ø STATUS_SRCTRAN_H q#ü STATUS_DSTTRAN_L q# STATUS_DSTTRAN_H q# STATUS_ERR_L q# STATUS_ERR_H q# MSK_TFR_L q# MSK_TFR_H q# MSK_BLOCK_L q# MSK_BLOCK_H q# MSK_SRCTRAN_L q# MSK_SRCTRAN_H q#¤ MSK_DSTTRAN_L q#¨ MSK_DSTTRAN_H q#¬ MSK_ERR_L q#° MSK_ERR_H q#´ CLEAR_TFR_L q#¸ CLEAR_TFR_H q#¼ CLEAR_BLOCK_L q#À CLEAR_BLOCK_H q#Ä CLEAR_SRCTRAN_L q#È CLEAR_SRCTRAN_H q#Ì CLEAR_DSTTRAN_L q#Ð CLEAR_DSTTRAN_H q#Ô CLEAR_ERR_L q#Ø CLEAR_ERR_H q#Ü STATUS_INT_L q#à STATUS_INT_H q#äí#q RESERVED3 ä#è DMA_CFG_REG_L q# DMA_CFG_REG_H q# CH_EN_REG_L q# CH_EN_REG_H q#¤ PDMA_T PËA*Û*¬ CON q# TAR q# SAR q# HS_MADDR q# DATACMD q# SS_SCL_HCNT q# SS_SCL_LCNT q# FS_SCL_HCNT q# FS_SCL_LCNT q# HS_SCL_HCNT q#$ HS_SCL_LCNT q#( INTR_STAT q#, INTR_MASK q#0 RAW_INTR_STAT q#4 RX_TL q#8 TX_TL q#< CLR_INTR q#@ CLR_RX_UND q#D CLR_RX_OVR q#H CLR_TX_OVR q#L CLR_RD_REQ q#P CLR_TX_ABRT q#T CLR_RX_DONE q#X CLR_ACTIVITY q#\ CLR_STOP_DET q#` CLR_START_DET q#d CLR_GEN_CALL q#h IC_ENABLE q#l STATUS q#p TXFLR q#t RXFLR q#x SDA_HOLD q#| TX_ABRT_SRC q# SLV_DATA_NACK q# DMA_CR q# DMA_TDLR q# DMA_RDLR q# SDA_SETUP q# ACK_GENERAL_CALL q# ENABLE_STATUS q# FS_SPKLEN q# HS_SPKLEN q#¤ CLR_RESTART_DET q#¨ PI2C_T bC*æ.d LP_REG_SYNC q# LP_FL_CTRL_3V q# LP_SPACING_TIME0 q# LP_SPACING_TIME1 q# LP_SPACING_TIME2 q# LP_SLPTMR }# LP_INT_CTRL q# LP_DLY_CTRL_3V q# LP_PTAT_POLY q# LP_HP_LDO q#$ LP_LP_LDO_3V q#( LP_ANA_LDO q#, LP_FSYN_LDO q#0 LP_SW q#4 LP_BUCK_3V q#8 ANA_ADC_LDO q#< ANA_RFFE_LDO q#@ ANA_VCO_LDO q#D ANA_DFT q#H ANA_MISC_3V q#L ANA_RESERVED_3V q#P ACT_32K_CTRL q#T ACT_32K_BASECORR q#X CPU_ADDR_REMAP_CTRL q#\ RCL_HW_CAL_CTRL q#` PANA_T iE*
2| EF_CTL q# EF_ADDR q# EF_DAT q# EF_RSV0 q# EF_VDD q# EF_RSV1 q# EF_CMD q# EF_TRG q# EF_PROG_TIMING1 q# EF_PROG_TIMING2 q#$ EF_PROG_TIMING3 q#( EF_READ_TIMING4 q#, EF_READ_TIMING5 q#0ç0q EF_RSV2 ^#4 EF_OP_ERROR q#d EF_VERIFY_DEBUG1 q#h EF_VERIFY_DEBUG2 q#l EF_VERIFY_DEBUG3 q#p EF_VERIFY_DEBUG4 q#t EF_FLASH_PERMISSION q#x PEFUSE_T tÎG*¦6- FADDR
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# POWER
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# INT_IN1
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# INT_IN2
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# INT_OUT1
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# INT_OUT2
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# INT_USB
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# INT_IN1E
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# INT_IN2E
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# INT_OUT1E
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# INT_OUT2E
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#
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INT_USBE
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# FRAME1
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# FRAME2
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# INDEX
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# REV
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# MAX_PKT_IN
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# CSR0_INCSR1
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# IN_CSR2
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# MAX_PKT_OUT
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# OUT_CSR1
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# OUT_CSR2
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# OUT_COUNT1
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# OUT_COUNT2
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#5
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REV0 # FIFO_EP0
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# ¿5
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REV1 ¶#! FIFO_EP1
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#$ä5
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REV2 Û#% FIFO_EP2
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#(6
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REV3 #) FIFO_EP3
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#, PUSB_T I*ñ6 DMA_INTR q# CNTL1 q# ADDR1 q# COUNT1 q# PUSBDMA_T 4I*¨? revs0 q# FSM5 q# FSM6 q# FSM13 q# FSM14 q# FSM15 q# FSM16 q# FSM17 q# FSM18 q# FSM19 q#$ PHY1 q#( PHY2 q#, PHY3 q#0 PHY4 q#4 PHY5 q#8Ì8q revs1 C #< INTR1 q#D INTCLR q#H INTMSK q#L INTR4 q#P revs2 q#T ACTTMR1 q#X ACTTMR2 q#\ ACTTMR6 q#` ACTTMR7 q#d revs3 q#h SECURE1 q#l SECURE2 q#p SECURE3 q#t SECURE4 q#x SECURE5 q#| SECURE6 q# SECURE7 q# SECURE8 q# SECURE9 q# SECURE10 q# revs4 q# TEST_MUX00 q# RNG1 q# RNG2 q# revs5 q#¤ LL_MAC_CTRL q#¨ TEST_MUX01 q#¬ TEST_MUX02 q#° TEST_MUX03 q#´ <q revs6 #¸ R00_CTL q#À R01_INT q#Ä R02_TMR_CTL q#È R03_RX_ADDR_L q#Ì R04_RX_CTL q#Ð R05_TX_ADDR_L q#Ô R06_TX_CTL q#Ø R07_SRAM_CTL q#Ü R08_RX_ADDR1_L q#à R09_RX_ADDR2_L q#ä R0A_RX_ADDR3_L q#è R0B_RX_ADDR4_L q#ì R0C_RX_ADDR5_L q#ð R0D_RX_ADDR6_L q#ô R0E_RX_ADDR7_L q#ø R0F_RX_ADDR_H q#ü R10_RX_ADDR_EN q# R11_CFG q# PPRI_RF_T ÝI<Ó?O'NVIC_SystemReset __PAN_PRI_RF_H__ PRI_RF_MODE_SEL_TX (0) !PRI_RF_MODE_SEL_RX (1) "PRI_RF_MODE_SEL_TRX (2) (PRI_RF_ADDR_BYTE_LEN_2 (0) )PRI_RF_ADDR_BYTE_LEN_3 (1) *PRI_RF_ADDR_BYTE_LEN_4 (2) +PRI_RF_ADDR_BYTE_LEN_5 (3) 1PRI_RF_CHIP_MODE_INVALID (0) 2PRI_RF_CHIP_MODE_BLE (1) 3PRI_RF_CHIP_MODE_297 (2) 4PRI_RF_CHIP_MODE_NORDIC (3) :REG_FILE_OFST 0x0000 ;SEQ_RAM_OFST 0x1000 <LIST_RAM_OFST 0x8000 =TX_RX_RAM_OFST 0x8200 >CTE_IQ_RAM_OFST 0xB7FC GLLHWC_READ32_REG(base_addr,reg_ofst) (*(volatile uint32_t *)((0x50020000) + (base_addr) + (reg_ofst))) PLLHWC_WRITE32_REG(base_addr,reg_ofst,data) (*(volatile uint32_t *)(((0x50020000) + (base_addr) + (reg_ofst))) = (data)) XREAD_4_BYTES(pckt,pos) (((uint32_t) (pckt)[pos]) | (((uint32_t) (pckt)[pos + 1]) << 8) | (((uint32_t) (pckt)[pos + 2]) << 16) | (((uint32_t) (pckt)[pos + 3]) << 24)) ePRI_RF_WRITE_REG_VALUE(base,Reg,Func,Value) (base->Reg = (base->Reg & ~(Reg ## _ ## Func ## _Msk)) | ((Value << Reg ## _ ## Func ## _Pos) & Reg ## _ ## Func ## _Msk)) nPRI_RF_READ_REG_VALUE(base,Reg,Func) ((base->Reg & (Reg ## _ ## Func ## _Msk)) >> Reg ## _ ## Func ## _Pos) xPRI_RF_SET_FUNC_ENABLE(base,Reg,Func,State) ((State == ENABLE) ? (base->Reg |= Reg ## _ ## Func ## _Msk) : (base->Reg &= ~Reg ## _ ## Func ## _Msk)) Ä » ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\radio\prf_lib\include\ ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\ pan_pri_rf.h PanSeries.h d
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..\..\..\modules\hal\panchip\panplat\pan1070\bsp\radio\prf_lib\include\pan_pri_rf.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil _Bool ;ÓÒPRI_RF_IntFlag $¸rf $Y msk a__result <
ÝPRI_RF_ForceExitRx $¸rf $æ NewState <»èPRI_RF_SetTrxTransWaitTime $¸rf $I time <üõPRI_RF_EnableRxPipeAdr $¸rf $I pipe $æ NewState <«ÿPRI_RF_SetRxGoon $¸rf $: en_flag <ÞPRI_RF_SetAddrMatchBit $¸rf $: value <PRI_RF_SetPayloadEndian $¸rf $: endian <ÉPRI_RF_MultiPreamble $¸rf $: pre_length <õPRI_RF_StopRx $¸rf $: en_flag <PRI_RF_RandomNumGenInit $¸rf <ÇPRI_RF_RandomNumGenReinit $¸rf ;£PRI_RF_GetRandomNum Y $¸rf a__result Y <¸PRI_RF_AutoAnlsPayloadEn $¸rf $æ NewState "¨ <ïPRI_RF_CrcCheckEn $¸rf $æ NewState <¡PRI_RF_Crc16Select $¸rf $æ NewState <Ñ PRI_RF_ScambleEn $¸rf $æ NewState < «PRI_RF_NordicEnhanceEn $¸rf $æ NewState ;à ´PRI_RF_IsNordicEnhance : $¸rf a__result : <ó ¾PRI_RF_EnhanceEn $¸rf $æ NewState ;©
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ÇPRI_RF_IsEnhance : $¸rf a__result : <Þ
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ÑPRI_RF_BandWidth2mSel $¸rf $æ NewState < àPRI_RF_ChipModeSel $¸rf $: modeSel ;Ç éPRI_RF_GetChipMode : $¸rf a__result : <õ ôPRI_RF_RxAckEn $¸rf $æ NewState ;« ýPRI_RF_IsRxAckEn : $¸rf a__result : <Û PRI_RF_TxNoAckEn $¸rf $æ NewState ; PRI_RF_IsTxNoAckEn : $¸rf a__result : <Ä PRI_RF_TrxFuncSel $¸rf $æ NewState ;ø §PRI_RF_IsRxSel : $¸rf a__result : <¬±PRI_RF_ClearAllIrqEn $¸rf $æ NewState <äÂPRI_RF_IntMask $¸rf $Y msk $æ NewState _PAN_CLKTRIM_H_ p e ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\ pan_clktrim.h 4
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..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_clktrim.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil _Bool ;×KTRIM_IsIntStatusOccured
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$Átrim $Y msk a__result
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<bTRIM_ClearIntStatusMsk $Átrim $Y msk <¸mTRIM_EnableInt $Átrim $æ NewState <ñxTRIM_SetRelationIncrease $Átrim $æ NewState <¬TRIM_SetEarlyTerminatinEn $Átrim $æ NewState <ÜTRIM_SetCoarseCode $Átrim $Y code ;TRIM_GetCoarseCode Y $Átrim a__result Y <ĤTRIM_SetFineCode $Átrim $Y code ;üTRIM_GetFineCode Y $Átrim a__result Y <«¸TRIM_SetBitWidth $Átrim $Y width ;ã¼TRIM_GetBitWidth Y $Átrim a__result Y <ÊTRIM_StartTuning $Átrim $Y function <Á TRIM_SetIdealCnt $Átrim $Y cnt " ;þ)TRIM_GetIdealCnt Y $Átrim a__result Y ;´3TRIM_GetRealCnt Y $Átrim a__result Y
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PAN_POWER__H_ | r ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\ pan_power.h PanSeries.h
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..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_power.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil *ê buck_out_trim : # lph_ldo_vref_trim : # lpl_ldo_trim : # hp_ldo_trim : # Ppower_param_t __PAN_HAL_H__ HAL_TIME_FOREVER 0xFFFFFFFFU HAL_ASSERT SYS_ASSERT !"#$%'( )
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* + PAN_IO_TIMING_TRACK_INIT_PIN(__VA_ARGS__...) PAN_IO_TIMING_TRACK_LEVEL(__VA_ARGS__...) PAN_IO_TIMING_TRACK_TOGGLE(__VA_ARGS__...) L B ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\ C:\Keil_v5\ARM\ARMCC\Bin\..\include\ pan_hal.h stdint.h pan_hal_gpio.h pan_hal_uart.h pan_hal_dmac.h pan_hal_spi.h pan_hal_i2c.h pan_hal_wdt.h pan_hal_wwdt.h pan_hal_pwm.h pan_hal_timer.h pan_hal_adc.h ä
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..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil HAL_SUCCESS HAL_INVALID_PARAMS HAL_IO_ERROR HAL_DEVICE_BUSY HAL_NO_MEM HAL_NO_HARDWARE_SOURCE HAL_UNKNOWN PHAL_Error ÒHAL_OK HAL_ERROR HAL_BUSY HAL_TIMEOUT PHAL_Status
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__PAN_HAL_DEF_H__ ü ó ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\ C:\Keil_v5\ARM\ARMCC\Bin\..\include\ ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\ pan_hal_def.h stdbool.h stdint.h PanSeries.h H
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..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_def.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil O%: "
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PDMAC_CallbackFunc µUART_CB_FLAG_TX_FINISH UART_CB_FLAG_RX_FINISH UART_CB_FLAG_RX_TIMEOUT UART_CB_FLAG_RX_BUFFFULL UART_CB_FLAG_DMA PUART_Cb_Flag_Opt 1ùI2C_CB_FLAG_STOP I2C_CB_FLAG_DMA # PI2C_Cb_Flag_Opt Í ¨ADC_CB_FLAG_DMA B PADC_Cb_Flag_Opt "êSPI_CB_FLAG_INT SPI_CB_FLAG_DMA # PSPI_CbFlagOpt ?'O%µ%%I ": "PUART_CallbackFunc )OÆ%ù%%I "´PI2C_CallbackFunc Æ*Oô%j%ô%I "I "âPSPI_CallbackFunc ú+O¨%(%(%I "Y "PADC_CallbackFunc .,
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__PAN_HAL_GPIO_H__ GPIO_P0_PIN_NUM 8 GPIO_P1_PIN_NUM 8 GPIO_P2_PIN_NUM 8 GPIO_P3_PIN_NUM 2 GPIO_INTEN_MASK_BASE 0x00010001UL GPIO_INTTYPE_MASK_BASE 0x00000001UL w ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\ pan_hal_gpio.h pan_hal_def.h
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..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_gpio.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil àP0_0 P0_1 P0_2 P0_3 P0_4 P0_5 P0_6 P0_7 P1_0 P1_1 P1_2 P1_3 P1_4 P1_5 P1_6 P1_7 P2_0 P2_1 !P2_2 "P2_3 #P2_4 $P2_5 %P2_6 &P2_7 'P3_0 0P3_1 1 PHAL_GPIO_PinId 9£HAL_GPIO_MODE_INPUT_DIGITAL HAL_GPIO_MODE_INPUT_ANALOG HAL_GPIO_MODE_OUTPUT_PUSHPULL HAL_GPIO_MODE_OUTPUT_OPENDRAIN HAL_GPIO_MODE_QUASI_BIDIRECTIONAL PHAL_GPIO_Mode öEHAL_GPIO_PULL_DISABLE HAL_GPIO_PULL_UP HAL_GPIO_PULL_DOWN PHAL_GPIO_Pull ¸OÇHAL_GPIO_LEVEL_LOW HAL_GPIO_LEVEL_HIGH PHAL_GPIO_Level XøHAL_GPIO_INT_RISING HAL_GPIO_INT_FALLING HAL_GPIO_INT_BOTH_EDGE HAL_GPIO_INT_HIGH HAL_GPIO_INT_LOW HAL_GPIO_INT_DISABLE PHAL_GPIO_IntMode ]eO%ø "PHAL_GPIO_CallbackFunc j*ã mode £# pull # level G# PHAL_GPIO_InitTypeDef 9}*¹ intMode ø# callbackFunc # debounce æ # PHAL_GPIO_IntInitTypeDef â qHAL_GPIO_CallbackArray Ù ) â HAL_GPIO_CallbackArray
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__PAN_HAL_UART_H__ ÆPAN_HAL_UART_INST_COUNT 2 ÇUART0_OBJ UART_Handle_Array[0] ÈUART1_OBJ UART_Handle_Array[1] w ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\ pan_hal_uart.h pan_hal_def.h T
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..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_uart.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil _Bool t PHAL_UART_EventOpt X PHAL_UART_IntModeOpt C(PHAL_UART_TxTrigOpt å0PHAL_UART_RxTrigOpt a8PHAL_UART_DmaDirOpt é>PHAL_UART_FormatOpt pPHAL_UART_HandleTypeDef *(PHAL_UART_CallbackFunc ³ PHAL_UART_InitTypeDef · PHAL_UART_IntTypeDef Ü ¥)Ì_HAL_UART_HandleTypeDef 4 pUartx L# initObj ñ# interruptObj # pTxBuffPtr # txXferSize I # txXferCount R# pRxBuffPtr # rxXferSize I #$ rxXferCount R#& isTxBusy #( isRxBusy #) txDmaCh : #* rxDmaCh : #+ dmaSrc Y #, dmaDst Y #0 "l tI ÃHAL_UART_EVT_TX_FINISH HAL_UART_EVT_RX_FINISH HAL_UART_EVT_CONTI_RX_TIMEOUT HAL_UART_EVT_CONTI_RX_BUFF_FULL HAL_UART_EVT_RX_ERR_PARITY HAL_UART_EVT_RX_ERR_FRAME HAL_UART_EVT_RX_ERR_OVERRUN HAL_UART_EVT_MAX å HAL_UART_INT_RECV_DATA_AVL HAL_UART_INT_THR_EMPTY HAL_UART_INT_LINE_STATUS HAL_UART_INT_MODEM_STATUS HAL_UART_INT_ALL HAL_UART_INT_DISABLE á
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HAL_UART_TX_FIFO_EMPTY HAL_UART_TX_FIFO_TWO_CHARS HAL_UART_TX_FIFO_QUARTER_FULL HAL_UART_TX_FIFO_HALF_FULL é HAL_UART_RX_FIFO_ONE_CHAR HAL_UART_RX_FIFO_QUARTER_FULL HAL_UART_RX_FIFO_HALF_FULL HAL_UART_RX_FIFO_TWO_LESS_THAN_FULL HAL_UART_DMA_TX HAL_UART_DMA_RX HAL_UART_FMT_5_N_1 HAL_UART_FMT_5_N_1_5 HAL_UART_FMT_5_E_1 HAL_UART_FMT_5_E_1_5 HAL_UART_FMT_5_O_1 HAL_UART_FMT_5_O_1_5 HAL_UART_FMT_5_S_1 8HAL_UART_FMT_5_S_1_5 <HAL_UART_FMT_5_M_1 (HAL_UART_FMT_5_M_1_5 ,HAL_UART_FMT_6_N_1 HAL_UART_FMT_6_N_2 HAL_UART_FMT_6_E_1 HAL_UART_FMT_6_E_2 HAL_UART_FMT_6_O_1 HAL_UART_FMT_6_O_2 HAL_UART_FMT_6_S_1 9HAL_UART_FMT_6_S_2 =HAL_UART_FMT_6_M_1 )HAL_UART_FMT_6_M_2 -HAL_UART_FMT_7_N_1 HAL_UART_FMT_7_N_2 HAL_UART_FMT_7_E_1 HAL_UART_FMT_7_E_2 HAL_UART_FMT_7_O_1
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HAL_UART_FMT_7_O_2 HAL_UART_FMT_7_S_1 :HAL_UART_FMT_7_S_2 >HAL_UART_FMT_7_M_1 *HAL_UART_FMT_7_M_2 .HAL_UART_FMT_8_N_1 HAL_UART_FMT_8_N_2 HAL_UART_FMT_8_E_1 HAL_UART_FMT_8_E_2 HAL_UART_FMT_8_O_1 HAL_UART_FMT_8_O_2 HAL_UART_FMT_8_S_1 ;HAL_UART_FMT_8_S_2 ?HAL_UART_FMT_8_M_1 +HAL_UART_FMT_8_M_2 / O©%© %% %I "´": " *Ü baudRate Y # format # *Ö txTrigLevel L# rxTrigLevel f# IRQn # IrqPriority : # continuousRxMode # callbackFunc Ó# __PAN_HAL_DMAC_H__ ;DMAC_CHANNEL_NUMS 2 =DMAC_Channel_0 DMAC_Channel_Array[0] >DMAC_Channel_1 DMAC_Channel_Array[1] w ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\ pan_hal_dmac.h pan_hal_def.h |
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..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_dmac.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil uvoid " "Y PDMAC_Peri_Mode_Opt O PDMAC_HandleTypeDef 9Ø5 qDMAC_Channel_Array Oqdma_uart2mem_config 8 qdma_mem2uart_config 8 qdma_spi2mem_config 8 qdma_mem2spi_config 8 qdma_mem2i2c_config 8 qdma_i2c2mem_config 8 qdma_adc2mem_config 8 qdma_mem2i2c_u16_config 8 DMAC_Peri_UART DMAC_Peri_I2C DMAC_Peri_SPI DMAC_Peri_ADC *ö8 dma v# periph # ConfigTmp 8 # Callback # CallbackUart # CallbackI2c Ê # CallbackSpi þ #$ CallbackAdc 2 #( PeriMode #, pBuffPtr #0 XferSize I #4 XferCount I #6 "T ã X DMAC_Channel_Array q dma_uart2mem_config dma_mem2uart_config © dma_spi2mem_config Ä dma_mem2spi_config ß dma_mem2i2c_config ú dma_i2c2mem_config dma_adc2mem_config 0 dma_mem2i2c_u16_config " # $ % _PAN_HAL_SPI_H_ SPI_RX_BUF_SIZE 256 SPI_TX_BUF_SIZE 256 oSPI0_OBJ spiHandleArray[0] vSPI1_OBJ spiHandleArray[1] v ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\ pan_hal_spi.h pan_hal_def.h
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..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_spi.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil * Mode Ë # PSPI_InterruptOptDef
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!®BAUDRATE_100K BAUDRATE_500K ¡ BAUDRATE_1M @B BAUDRATE_2M BAUDRATE_5M @KL BAUDRATE_10M PSPI_BaudRate 8-*³ role # dataSize C # clkPolarity # clkPhase # baudrateDiv À
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# format ê # PSPI_InitOptDef Â;SPI_STAT_NULL SPI_STAT_RX SPI_STAT_TX SPI_STAT_RXTX PSPI_XferStatOpt IC*É4 pSpix É# initObj 3# xferStat #
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interruptObj # pTxBuffPtr Ï# txXferSize I # txXferCount Õ# pRxBuffPtr Ï# rxXferSize I # rxXferCount Õ# IRQn # rxIntCallback þ # txIntCallback þ #$ dmaSrc Y #( dmaDst Y #, errorCode Û#0 " "I tI tY PSPI_HandleTypeDef ¥aá qspiHandleArray ú ! spiHandleArray ' ( ) __PAN_HAL_I2C_H v ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\ pan_hal_i2c.h pan_hal_def.h
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..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_i2c.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil ²I2C_ADDR_7BIT I2C_ADDR_10BIT PI2C_AddressMode_Opt
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÷I2C_ROLE_MASTER !I2C_ROLE_SLAVE PI2C_Role_Opt M'»I2C_DUTYCYCLE_16_9 @I2C_DUTYCYCLE_2 ÿ¿ PI2C_DutyCycle_Opt 2öI2C_DIR_TX I2C_DIR_RX PI2C_Direction_Opt Ô=ÁI2C_ACK_ADDR_7BIT @I2C_ACK_ADDR_10BIT À PI2C_AckAddr_Opt H×I2C_SPEED_100K I2C_SPEED_200K @ I2C_SPEED_400K I2C_SPEED_500K ¡ I2C_SPEED_1M @B I2C_SPEED_2M PI2C_ClockSpeed_Opt XW*Þ ClockSpeed ×# Role w# DutyCycle »# OwnAddress I # AckAddress A#
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AddressMode 2# PI2C_Init_Opt ñoI2C_Tx_Dir I2C_Rx_Dir PI2C_Xfer_Dir_Opt rt*¾ pass : # PI2C_Interrupt_Opt «y*ñ @ I2Cx ñ# I2C_InitObj ^# InterruptObj ¾# pTxBuffPtr ÷# TxXferSize I # TxXferCount ý# pRxBuffPtr ÷# RxXferSize I #$ RxXferCount ý#& IRQn #( RxIntCallback Ê #, TxIntCallback Ê #0 DMA_SRC Y #4 DMA_DST Y #8 StopFlag : #< "[ ": tI PI2C_HandleTypeDef × + , - __PAN_HAL_WDT_H v ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\ pan_hal_wdt.h pan_hal_def.h Ø
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..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_wdt.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil *ô Timeout ` # ResetDelay ñ # ClockSource Y # ResetSwitch Y # WakeupSwitch Y # PWDT_Init_Opt
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!O "PWDT_CallbackFunc &*Á CallbackFunc # PWDT_Interrupt_Opt ¨/ / 0 1 __PAN_HAL_WWDT_H w ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\ pan_hal_wwdt.h pan_hal_def.h ´
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..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_wwdt.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil O " PWWDT_CallbackFunc *ë Prescaler # ClockSource Y # CmpValue Y # PWWDT_Init_Opt ,$* CallbackFunc # PWWDT_Interrupt_Opt - 3 4 5 __PAN_HAL_PWM_H JHAL_PWM_PinConfiguration(port,bit,chId) (SYS->port ## _MFP = (SYS->port ## _MFP & ~SYS_MFP_ ## port ## bit ## _Msk) | SYS_MFP_ ## port ## bit ## _ ## chId) v ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\ pan_hal_pwm.h pan_hal_def.h
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..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_pwm.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil _Bool PPWM_ChId I#PPWM_ModeOpt ®0PPWM_InitOpt ?®PWM0_CH0 PWM0_CH1 PWM0_CH2 PWM0_CH3 PWM0_CH4 PWM0_CH5 PWM0_CH6 PWM0_CH7 PWM_MODE_INDEPENDENT PWM_MODE_COMPLEMENTARY PWM_MODE_SYNCHRONIZED PWM_MODE_GROUP *ÿ frequency Y # dutyCycle Y # operateType > # mode ##
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inverter
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# lowPowerEn
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# 7 8 9 : __PAN_HAL_TIMER_H _TIMER0_OBJ TIMER_Handle_Array[0] `TIMER1_OBJ TIMER_Handle_Array[1] aTIMER2_OBJ TIMER_Handle_Array[2] x ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\ pan_hal_timer.h pan_hal_def.h 8
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..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_timer.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil ÏTIMER_CB_FLAG_CNT TIMER_CB_FLAG_CAP TIMER_CB_FLAG_WK PTIMER_Cb_Flag_Opt !Oð%O "hPTIMER_CallbackFunc p(éTIMER_MODE_BASECNT TIMER_MODE_EVENTCNT TIMER_MODE_INCAP TIMER_MODE_WAKEUP PTIMER_Mode_Opt 5* pass : # PTIMER_Interrupt_Opt ÿ;*Û$ freq Y # mode é# cntMode É # capMode h # cmpValue Y # capEdge A # evtCntEdge ® # capSrc % # prescale Y # tmr0CmpSel ¦ # PTIMER_Init_Opt -N*Å0 TIMERx E# initObj Û# interruptObj #( IRQn #) callback t#, " PTIMER_HandleTypeDef ñ]ïK qTIMER_Handle_Array f;àeHAL_TIMER_US_TO_CNT Y $Y timeUs $i frequency a__result Y \cnt i ;¸lHAL_TIMER_MS_TO_CNT Y $Y timeMs $i frequency a__result Y \cnt i % < o TIMER_Handle_Array < = > __PAN_HAL_ADC_H v ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\ pan_hal_adc.h pan_hal_def.h L
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..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_adc.h Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil ñADC_MODE_CONV ADC_MODE_EXTRIG ADC_MODE_COMPARE ADC_MODE_PWMSEQ ADC_MODE_SGLCONVSEQ PADC_ModeOpt
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#àADC_CONV_MODE_BASE ADC_CONV_MODE_TEMP ADC_CONV_MODE_VBG ADC_CONV_MODE_VDD4 PADC_ConvertModeOpt 0ADC_CH0 ADC_CH1 ADC_CH2 ADC_CH3 ADC_CH4 ADC_CH5 ADC_CH6 ADC_CH7 ADC_CH_TEMP ADC_CH_BATTERY
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ADC_IDLE ÿ PADC_ChId úEÈADC_INPUT_RANGE_LOW ADC_INPUT_RANGE_HIGH PADC_InputRangeOpt R* InputRange È# Mode q# PADC_InitOpt á`*µ initOpt # id # PADC_HandleTypeDef l @ A B
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Ü Ñ ..\..\config\ ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\ soc_config.h pan_hal.h ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\src\pan_hal_uart.c p
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..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\src\pan_hal_uart.c Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] C:\Users\WXK\Desktop\pan1070-ndk-v0.8.0-rc3\pan1070-ndk-v0.8.0-rc3\01_SDK\nimble\mcu_boot\keil _Complex long_double _Complex double _Complex float uvoid )é__va_list __ap i# "HP__builtin_va_list N ´ ": 9Ô« UART_HandleLineStatus $© pUart \lineStatus Y 9Ä UART_HandleReceivedData $© pUart $ flag 9¿º UART_HandleTransmittingData $© pUart 9ñØ UART_HandleProc $© pUart \event D ! / ! I $ > % % % % %C
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K.1 L.< 4 I? M.< 4 ? NI O P I:;9 Q I4 R S T U V W 1 X4 I , Y4 I Z4 I [4 I, \4 I ]4 I 4 ^4 I ,4 _4 I4 `4 I,4 a4 I4 b4 1 , c4 1 d4 1, e4 1 f 1 g 1 h I i I j I k I 4 l I ,4 m I4 n 1 o 1 p4 I ? q4 I? < r4 I , s4 I t5 I u; v= w% x<% Component: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed] armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=9931,9931,6642 --cpu=Cortex-M0 --fpu=SoftVFP --output=.\objects\pan_hal_uart.o --vfemode=force
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Input Comments: p4418-3 Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec] armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M0 --fpu=SoftVFP --apcs=/interwork/interwork --no_divide pan_hal_uart.o Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] ArmCC --c99 --split_sections --debug -c --gnu -o.\objects\pan_hal_uart.o --depend=.\objects\pan_hal_uart.d --cpu=Cortex-M0 --apcs=interwork -O3 -Otime --diag_suppress=9931 --preinclude=soc_config.h -I..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include -I..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc -I..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include -I..\..\..\modules\hal\panchip\panplat\pan1070\bsp\radio\prf_lib\include -I..\..\..\modules\hal\panchip\panplat\pan1070\bsp\SEGGER_RTT\RTT -I..\..\os\freertos\include -I..\..\os\freertos\portable\RVDS\ARM_CM0 -I..\..\config -I..\..\component\app_log -I..\..\soc -I..\..\utilities -I.\configuration -I..\src -I.\RTE\_BootLoader -IC:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.0\Device\ARM\ARMCM0\Include -IC:\Keil_v5\ARM\CMSIS\Include -D__MICROLIB -D__UVISION_VERSION=530 -DARMCM0 -D_RTE_ -DIS_BOOTLOADER=1 -DCONFIG_FLASH_LINE_MODE=FLASH_X2_MODE -DBLE_EN=0 -DCONFIG_OS_EN=0 --omf_browse=.\objects\pan_hal_uart.crf ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\src\pan_hal_uart.c = = = = ¬ = = & = = Ö = = = 6 = = =
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ï 8 ï U è f è x ï è è è ¿ ï Ó è - Ç G Ç ¤ ï ª ï · ï Ð ï Û ï ü ï ï ï ( ï 3 ï Û Æ [ . Æ c 6 Ý ï ¸ Ý Ï ï ÷ Ý é 4 Ý Z Ý l é .ARM.attributes .strtab .shstrtab .rel.debug_pubnames .rel.debug_frame .rel.debug_line .rel.debug_info .reli.UART_HandleProc .reli.UART1_IRQHandlerOverlay .reli.UART1_IRQHandler .reli.UART0_IRQHandlerOverlay .reli.UART0_IRQHandler .reli.HAL_UART_SendData_DMA .reli.HAL_UART_SendDataAbort_DMA .reli.HAL_UART_SendData .reli.HAL_UART_ReceiveData_DMA .reli.HAL_UART_ReceiveDataAbort_DMA .reli.HAL_UART_ReceiveData .reli.HAL_UART_Init_DMA .reli.HAL_UART_Init .symtab .comment .arm_vfe_header __ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000 __ARM_grp.pan_hal_uart.c.2_sZM000_G6noGS_Tbh2_S00000 __ARM_grp.pan_hal_adc.h.2_QE0000_l6cLqksnPfe_300000 __ARM_grp.pan_hal_timer.h.2_p6w100_PBHYt_RH9A2_N10000 __ARM_grp.pan_hal_pwm.h.2_cbM000_cTGofbeQPX4_310000 __ARM_grp.pan_hal_wwdt.h.2_UA1000_o6sxBTEr8s0_g00000 __ARM_grp.pan_hal_wdt.h.2_8D1000_PC0CjfMIf$5_e00000 __ARM_grp.pan_hal_i2c.h.2_kEL000_1Dx_hXwFuM9_A00000 __ARM_grp.pan_hal_spi.h.2_l0x100_HjGLbyP5Xye_h20000 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__ARM_grp_.debug_frame$125 __ARM_grp_.debug_frame$118 __ARM_grp_.debug_frame$111 __ARM_grp_.debug_frame$104 __ARM_grp_.debug_frame$97 __ARM_grp_.debug_frame$90 __ARM_grp_.debug_frame$83 __ARM_grp_.debug_frame$76 __ARM_grp_.debug_frame$69 __ARM_grp_.debug_frame$62 __ARM_grp_.debug_frame$55 __ARM_grp_.debug_frame$48 __ARM_grp_.debug_frame$41 __ARM_grp_.debug_frame$34 __ARM_grp_.debug_frame$27 __ARM_grp_.debug_frame$20 .data i.UART_HandleReceivedData i.UART_HandleProc i.UART1_IRQHandlerOverlay i.UART1_IRQHandler i.UART0_IRQHandlerOverlay i.UART0_IRQHandler i.HAL_UART_SendData_INT i.HAL_UART_SendData_DMA i.HAL_UART_SendDataAbort_INT i.HAL_UART_SendDataAbort_DMA i.HAL_UART_SendData i.HAL_UART_ReceiveData_INT i.HAL_UART_ReceiveData_DMA i.HAL_UART_ReceiveDataContinuously_INT i.HAL_UART_ReceiveDataAbort_INT i.HAL_UART_ReceiveDataAbort_DMA i.HAL_UART_ReceiveData i.HAL_UART_Init_INT i.HAL_UART_Init_DMA BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OTIME$EBA8$REQ8$PRES8$EABIv2 i.HAL_UART_Init BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$EBA8$PRES8$EABIv2 ..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\src\pan_hal_uart.c .revsh_text .rev16_text ..\\..\\..\\modules\\hal\\panchip\\panplat\\pan1070\\bsp\\peripheral\\src\\pan_hal_uart.c $d.realdata $d $t A[ aeabi Cortex-M0 '
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