国产蓝牙芯片的仓库
blame | 历史 | 原始文档
WXK
2025-01-21 8f1a91a8ec98e430cfe4357bda099d495917198e 
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Ø    UÒYœÙ, ..\..\..\..\config\soc_config.h—ÿ’¼Ù).\configuration\sdk_config.h߄¸¼÷Ù9-C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.hÜ Íò$Ù/#..\..\..\..\config\nimble_syscfg.h—ÿ’¼<ÙMA..\..\..\..\host\nimble\porting\nimble\include\sysinit/sysinit.h—ÿ’¼ƒÙ9-C:\Keil_v5\ARM\ARMCC\Bin\..\include\assert.hÚ Íò*ÙH<..\..\..\..\host\nimble\porting\nimble\include\os/os_mbuf.h—ÿ’¼æÙC7..\..\..\..\host\nimble\porting\nimble\include\os/os.h—ÿ’¼ùÙ9-C:\Keil_v5\ARM\ARMCC\Bin\..\include\assert.hÚ Íò*ÙG;..\..\..\..\host\nimble\nimble\include\nimble/nimble_npl.h—ÿ’¼}Ù:.C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdbool.hÜ ÍòÁÙ9-C:\Keil_v5\ARM\ARMCC\Bin\..\include\stddef.hÜ Íò@ÙXL..\..\..\..\host\nimble\porting\npl\freertos\include\nimble/nimble_npl_os.h—ÿ’¼"Ù9-C:\Keil_v5\ARM\ARMCC\Bin\..\include\assert.hÚ Íò*Ù9-C:\Keil_v5\ARM\ARMCC\Bin\..\include\string.hÜ Íò#Ù7+..\..\..\..\os\freertos\include\FreeRTOS.h—ÿ’¼UÙ0$..\..\..\..\config\FreeRTOSConfig.h—ÿ’¼Ù^R..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\PanSeries.h—ÿ’¼rÙ8,C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.hÜ Íò™Ù9-C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdlib.hÜ Íò8Ù\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\core_cm0.h—ÿ’¼)ÙaU..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\cmsis_version.h—ÿ’¼£ÙbV..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\cmsis_compiler.h—ÿ’¼LÙ_S..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\cmsis_armcc.h—ÿ’¼§ÙeY..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\system_PanSeries.h—ÿ’¼`Ù`T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_sys_log.h—ÿ’¼ZÙ\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_sys.h—ÿ’¼Ù\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_clk.h—ÿ’¼(Ù\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_adc.h—ÿ’¼Ù\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_fmc.h—ÿ’¼úÙ]Q..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_dmac.h—ÿ’¼™Ù]Q..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_gpio.h—ÿ’¼Ù\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_spi.h—ÿ’¼äÙ]Q..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_uart.h—ÿ’¼rÙ\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_i2c.h—ÿ’¼2Ù^R..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_timer.h—ÿ’¼Ù\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_pwm.h—ÿ’¼ÜÙ\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_wdt.h—ÿ’¼áÙ]Q..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_wwdt.h—ÿ’¼hÙ[O..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_lp.h—ÿ’¼ˆÙ^R..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_efuse.h—ÿ’¼FÙfZ..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\radio\prf_lib\include\pan_pri_rf.h—ÿ’¼ÓÙ^R..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\PanSeries.h—ÿ’¼rÙ`T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_clktrim.h—ÿ’¼dÙ^R..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_power.h—ÿ’¼1Ù\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal.h—ÿ’¼ûÙaU..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_gpio.h—ÿ’¼ãÙ`T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_def.h—ÿ’¼eÙaU..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_uart.h—ÿ’¼ÖÙaU..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_dmac.h—ÿ’¼ýÙ`T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_spi.h—ÿ’¼HÙ`T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_i2c.h—ÿ’¼–Ù`T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_wdt.h—ÿ’¼EÙaU..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_wwdt.h—ÿ’¼ÌÙ`T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_pwm.h—ÿ’¼@ÙbV..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_timer.h—ÿ’¼oÙ`T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_adc.h—ÿ’¼lÙ7+..\..\..\..\os\freertos\include\projdefs.h—ÿ’¼ÂÙ7+..\..\..\..\os\freertos\include\portable.h—ÿ’¼ÆÙE9..\..\..\..\os\freertos\include\deprecated_definitions.h—ÿ’¼÷ÙF:..\..\..\..\os\freertos\portable\RVDS\ARM_CM0\portmacro.h—ÿ’¼¿Ù;/..\..\..\..\os\freertos\include\mpu_wrappers.h—ÿ’¼òÙ4(..\..\..\..\os\freertos\include\queue.h—ÿ’¼Ù3'..\..\..\..\os\freertos\include\task.h—ÿ’¼tÙ3'..\..\..\..\os\freertos\include\list.h—ÿ’¼kÙ5)..\..\..\..\os\freertos\include\semphr.h—ÿ’¼”Ù5)..\..\..\..\os\freertos\include\timers.h—ÿ’¼ÙWK..\..\..\..\host\nimble\porting\npl\freertos\include\nimble/npl_freertos.h—ÿ’¼rÙG;..\..\..\..\host\nimble\porting\nimble\include\os/endian.h—ÿ’¼dÙ;/C:\Keil_v5\ARM\ARMCC\Bin\..\include\inttypes.hÜ Íò6ÙF:..\..\..\..\host\nimble\porting\nimble\include\os/queue.h—ÿ’¼°ÙI=..\..\..\..\host\nimble\porting\nimble\include\os/os_error.h—ÿ’¼dÙC7..\..\..\..\host\nimble\porting\nimble\include\os/os.h—ÿ’¼ùÙH<..\..\..\..\host\nimble\porting\nimble\include\os/os_mbuf.h—ÿ’¼æÙK?..\..\..\..\host\nimble\porting\nimble\include\os/os_mempool.h—ÿ’¼‘Ù, ..\..\..\..\utilities\utility.h—ÿ’¼-Ù*..\..\..\..\utilities\bytes.h—ÿ’¼Ù/#..\..\..\..\utilities\os_wrapper.h—ÿ’¼ùÙPD..\..\..\..\host\nimble\porting\nimble\include\os/panchip_mempool.h—ÿ’¼†Ù@4..\..\..\..\host\nimble\nimble\include\nimble/ble.h—ÿ’¼xÙG;..\..\..\..\host\nimble\nimble\include\nimble/hci_common.h—ÿ’¼ÙPD..\..\..\..\host\nimble\nimble\transport\include\nimble/transport.h—ÿ’¼UÙUI..\..\..\..\host\nimble\nimble\transport\include\nimble/transport_impl.h—ÿ’¼:ÙXL..\..\..\..\host\nimble\nimble\transport\include\nimble/transport/monitor.h—ÿ’¼ÙE9..\..\..\..\host\nimble\nimble\transport\src\transport.c—ÿ’¼³ÚP_SOC_CONFIG_H_PÚP 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__regIPSRùÚ__get_APSRMÚ


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APSR_Type¸ÚPAPSR_N_PosCÚPAPSR_N_MskJÚPAPSR_Z_Pos7ÚPAPSR_Z_Msk>ÚPAPSR_C_PosNÚPAPSR_C_MskUÚPAPSR_V_Pos;ÚPAPSR_V_MskBÚ8


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<unnamed>QÚ 


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IPSR_Type°ÚP IPSR_ISR_Pos—ÚP IPSR_ISR_MskžÚ8


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"êNˆÚ "ébcÚ 


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xPSR_TypeÚPxPSR_N_PosÚPxPSR_N_MskÚPxPSR_Z_PosÚPxPSR_Z_MskÚPxPSR_C_PosÚPxPSR_C_MskÚPxPSR_V_PosÚPxPSR_V_MskÚPxPSR_T_PosÚPxPSR_T_Msk ÚP xPSR_ISR_PoshÚP xPSR_ISR_MskoÚ8


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<unnamed>QÚ 


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RESERVED0éÚ <"ŒICERØÚ <"|Œ


RESERVED1èÚ <"ŒISPR½Ú <"|Œ


RESERVED2çÚ <"ŒICPRÍÚ <"|Œ


RESERVED3æÚ <"€Œ


RESERVED4ÞÚ  <" ŒIPJÚ


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<unnamed>QÚ 


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RESERVED0‡Ú 


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RESERVED1†Ú <"˜SHPÚ 


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<unnamed>QÚ 


"ÕCTRL¯Ú 


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NVIC_BASEÚP    SCB_BASEiÚPSCBíÚPSysTickóÚ PNVIC“ÚPCMSIS_NVIC_VIRTUALÚ!PNVIC_SetPriorityGrouping3Ú!PNVIC_GetPriorityGrouping?ÚPNVIC_EnableIRQíÚPNVIC_GetEnableIRQÇÚPNVIC_DisableIRQ~ÚPNVIC_GetPendingIRQGÚPNVIC_SetPendingIRQ;ÚPNVIC_ClearPendingIRQ|ÚPNVIC_SetPriorityŽÚPNVIC_GetPriorityšÚPNVIC_SystemReset”ÚPCMSIS_VECTAB_VIRTUALˆÚPNVIC_SetVectorÚPNVIC_GetVectorÚPNVIC_USER_IRQ_OFFSETdÚPEXC_RETURN_HANDLER+ÚPEXC_RETURN_THREAD_MSPÚPEXC_RETURN_THREAD_PSPÚP_BIT_SHIFTœÚP    _SHP_IDX-ÚP_IP_IDXÚ#P__NVIC_SetPriorityGroupingqÚ#P__NVIC_GetPriorityGrouping}Ú__NVIC_EnableIRQTÚ,""Ž    IRQn¯Ú__memory_changedHÚ__NVIC_GetEnableIRQ.Ú,""‘    IRQn¬Ú__NVIC_DisableIRQåÚ,""“    IRQnªÚ__schedule_barriersÚ__dsbçÚ__isbâÚ__NVIC_GetPendingIRQ®Ú,""˜    IRQn¥Ú__NVIC_SetPendingIRQ¢Ú,""š    IRQn£Ú__NVIC_ClearPendingIRQãÚ,""œ    IRQn¡Ú__NVIC_SetPriorityõÚ,""ž    IRQnŸÚ,


"ž        priority„Ú__NVIC_GetPriorityÚ,""¡    IRQnœÚNVIC_EncodePriorityÚ,


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"²    vectorsÚ__NVIC_GetVectorôÚ,""¶    IRQn‡Ú


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adc_vbg_kPÚ "Ì    


adc_vbg_b[Ú ADC_VBG_KB_TDÚ8_otp_structûÚ <"€Р   d8ŸÚ8


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adc_vdd_kKÚ "Ò    


adc_vdd_b_Ú "Ò    


adc_vbg_kJÚ "Ò    


adc_vbg_bUÚ "Ò    adc_temp_voltqÚ "Ò    current_temp_value6Ú "Ò     battery_trimÇÚ# "Ò    pa_power_calib_trim_6dbm+Ú# "Ò    pa_power_calib_trim_0dbm1Ú <"Ò        mac_addrÚ <"    Ò    uidoÚ "Ò    


chip_info4Ú "Ò    cp_version©Ú "Ò    ft_version¢Ú "Ò     cp_pass_flagûÚ "Ò     ft_pass_flagôÚ "Ò    cp_checksumZÚ "Ò    ft_checksumSÚ <"Ò     user_rw_data¤Ú  "€Р   mñÚ8


<unnamed>QÚ <"


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rsvd1/Ú "


pmu_vbg_volt_l.Ú "


pmu_vbg_volt_h2Ú "


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hp_ldo_volt_lªÚ "


hp_ldo_volt_h®Ú "


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lph_ldo_volt_l<Ú "


lph_ldo_volt_h@Ú "


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lpl_ldo_volt_l8Ú "


lpl_ldo_volt_h<Ú "


flash_ldo_trimFÚ "


rsvd2.Ú "


flash_ldo_volt_lnÚ "


flash_ldo_volt_hrÚ "


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rffe_ldo_trim³Ú "


fsyn_ldo_trim–Ú "


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ipoly_trimÍÚ "


rsvd3-Ú "


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rsvd4,Ú "


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rsvd5+Ú "


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adc_vdd_b“Ú "


 


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<unnamed>QÚ 


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"ŽDINOFFmÚ 


"ŽDOUTëÚ 


"ŽDATMSK_Ú 


"ŽPINBÚ 


"ŽDBENÚ 


"ŽINTTYPEôÚ 


"ŽINTEN§Ú 


"ŽINTSRCPÚGPIO_TÚ8


<unnamed>QÚ 


"™DBCTL±Ú


GPIO_DB_T(ÚPGP_MODE_MODE0_PosIÚPGP_MODE_MODE0_MskPÚPGP_MODE_MODE1_PosHÚPGP_MODE_MODE1_MskOÚPGP_MODE_MODE2_PosGÚPGP_MODE_MODE2_MskNÚPGP_MODE_MODE3_PosFÚPGP_MODE_MODE3_MskMÚPGP_MODE_MODE4_PosEÚPGP_MODE_MODE4_MskLÚPGP_MODE_MODE5_PosDÚPGP_MODE_MODE5_MskKÚPGP_DINOFF_DINOFF0_PosÚPGP_DINOFF_DINOFF0_Msk&ÚPGP_DINOFF_DINOFF1_PosÚPGP_DINOFF_DINOFF1_Msk%ÚPGP_DINOFF_DINOFF2_PosÚPGP_DINOFF_DINOFF2_Msk$ÚPGP_DINOFF_DINOFF3_PosÚPGP_DINOFF_DINOFF3_Msk#ÚPGP_DINOFF_DINOFF4_PosÚPGP_DINOFF_DINOFF4_Msk"ÚPGP_DINOFF_DINOFF5_PosÚPGP_DINOFF_DINOFF5_Msk!ÚPGP_DINOFF_DINOFF6_PosÚPGP_DINOFF_DINOFF6_Msk ÚPGP_DINOFF_DINOFF7_PosÚPGP_DINOFF_DINOFF7_MskÚPGP_DOUT_DOUT0_PosÚPGP_DOUT_DOUT0_Msk"ÚPGP_DOUT_DOUT1_PosÚPGP_DOUT_DOUT1_Msk!ÚPGP_DOUT_DOUT2_PosÚPGP_DOUT_DOUT2_Msk ÚPGP_DOUT_DOUT3_PosÚPGP_DOUT_DOUT3_MskÚPGP_DOUT_DOUT4_PosÚPGP_DOUT_DOUT4_MskÚPGP_DOUT_DOUT5_PosÚPGP_DOUT_DOUT5_MskÚPGP_DOUT_DOUT6_PosÚPGP_DOUT_DOUT6_MskÚPGP_DOUT_DOUT7_PosÚPGP_DOUT_DOUT7_MskÚPGP_DATMSK_DATMSK0_PosÚPGP_DATMSK_DATMSK0_Msk


ÚPGP_DATMSK_DATMSK1_PosÚPGP_DATMSK_DATMSK1_Msk    ÚPGP_DATMSK_DATMSK2_PosÚPGP_DATMSK_DATMSK2_MskÚPGP_DATMSK_DATMSK3_PosÚPGP_DATMSK_DATMSK3_MskÚPGP_DATMSK_DATMSK4_PosÿÚPGP_DATMSK_DATMSK4_MskÚPGP_DATMSK_DATMSK5_PosþÚPGP_DATMSK_DATMSK5_MskÚPGP_DATMSK_DATMSK6_PosýÚPGP_DATMSK_DATMSK6_MskÚPGP_DATMSK_DATMSK7_PosüÚPGP_DATMSK_DATMSK7_MskÚPGP_PIN_PIN0_PosÉÚPGP_PIN_PIN0_MskÐÚPGP_PIN_PIN1_PosÈÚPGP_PIN_PIN1_MskÏÚPGP_PIN_PIN2_PosÇÚPGP_PIN_PIN2_MskÎÚPGP_PIN_PIN3_PosÆÚPGP_PIN_PIN3_MskÍÚPGP_PIN_PIN4_PosÅÚPGP_PIN_PIN4_MskÌÚPGP_PIN_PIN5_PosÄÚPGP_PIN_PIN5_MskËÚPGP_PIN_PIN6_PosÃÚPGP_PIN_PIN6_MskÊÚPGP_PIN_PIN7_PosÂÚPGP_PIN_PIN7_MskÉÚPGP_DBEN_DBEN0_PosaÚPGP_DBEN_DBEN0_MskhÚPGP_DBEN_DBEN1_Pos`ÚPGP_DBEN_DBEN1_MskgÚPGP_DBEN_DBEN2_Pos_ÚPGP_DBEN_DBEN2_MskfÚPGP_DBEN_DBEN3_Pos^ÚPGP_DBEN_DBEN3_MskeÚPGP_DBEN_DBEN4_Pos]ÚPGP_DBEN_DBEN4_MskdÚPGP_DBEN_DBEN5_Pos\ÚPGP_DBEN_DBEN5_MskcÚPGP_DBEN_DBEN6_Pos[ÚPGP_DBEN_DBEN6_MskbÚPGP_DBEN_DBEN7_PosZÚPGP_DBEN_DBEN7_MskaÚPGP_INTTYPE_TYPE0_PosÚPGP_INTTYPE_TYPE0_Msk%ÚPGP_INTTYPE_TYPE1_PosÚPGP_INTTYPE_TYPE1_Msk$ÚPGP_INTTYPE_TYPE2_PosÚPGP_INTTYPE_TYPE2_Msk#ÚPGP_INTTYPE_TYPE3_PosÚPGP_INTTYPE_TYPE3_Msk"ÚPGP_INTTYPE_TYPE4_PosÚPGP_INTTYPE_TYPE4_Msk!ÚPGP_INTTYPE_TYPE5_PosÚPGP_INTTYPE_TYPE5_Msk ÚPGP_INTTYPE_TYPE6_PosÚPGP_INTTYPE_TYPE6_MskÚPGP_INTTYPE_TYPE7_PosÚPGP_INTTYPE_TYPE7_MskÚPGP_INTEN_FLIEN0_Pos£ÚPGP_INTEN_FLIEN0_MskªÚPGP_INTEN_FLIEN1_Pos¢ÚPGP_INTEN_FLIEN1_Msk©ÚPGP_INTEN_FLIEN2_Pos¡ÚPGP_INTEN_FLIEN2_Msk¨ÚPGP_INTEN_FLIEN3_Pos ÚPGP_INTEN_FLIEN3_Msk§ÚPGP_INTEN_FLIEN4_PosŸÚPGP_INTEN_FLIEN4_Msk¦ÚPGP_INTEN_FLIEN5_PosžÚPGP_INTEN_FLIEN5_Msk¥ÚPGP_INTEN_FLIEN6_PosÚPGP_INTEN_FLIEN6_Msk¤ÚPGP_INTEN_FLIEN7_PosœÚPGP_INTEN_FLIEN7_Msk£ÚPGP_INTEN_RHIEN0_Pos›ÚPGP_INTEN_RHIEN0_Msk¢ÚPGP_INTEN_RHIEN1_PosšÚPGP_INTEN_RHIEN1_Msk¡ÚPGP_INTEN_RHIEN2_Pos™ÚPGP_INTEN_RHIEN2_Msk ÚPGP_INTEN_RHIEN3_Pos˜ÚPGP_INTEN_RHIEN3_MskŸÚPGP_INTEN_RHIEN4_Pos—ÚPGP_INTEN_RHIEN4_MskžÚPGP_INTEN_RHIEN5_Pos–ÚPGP_INTEN_RHIEN5_MskÚPGP_INTEN_RHIEN6_Pos•ÚPGP_INTEN_RHIEN6_MskœÚPGP_INTEN_RHIEN7_Pos”ÚPGP_INTEN_RHIEN7_Msk›ÚPGP_INTSRC_INTSRC0_PosåÚPGP_INTSRC_INTSRC0_MskìÚPGP_INTSRC_INTSRC1_PosäÚPGP_INTSRC_INTSRC1_MskëÚPGP_INTSRC_INTSRC2_PosãÚPGP_INTSRC_INTSRC2_MskêÚPGP_INTSRC_INTSRC3_PosâÚPGP_INTSRC_INTSRC3_MskéÚPGP_INTSRC_INTSRC4_PosáÚPGP_INTSRC_INTSRC4_MskèÚPGP_INTSRC_INTSRC5_PosàÚPGP_INTSRC_INTSRC5_MskçÚPGP_INTSRC_INTSRC6_PosßÚPGP_INTSRC_INTSRC6_MskæÚPGP_INTSRC_INTSRC7_PosÞÚPGP_INTSRC_INTSRC7_MskåÚPGP_INTSRC_INTSRC8_PosÝÚPGP_INTSRC_INTSRC8_MskäÚPGP_INTSRC_INTSRC9_PosÜÚPGP_INTSRC_INTSRC9_MskãÚPGP_INTSRC_INTSRC10_Pos²ÚPGP_INTSRC_INTSRC10_Msk¹ÚPGP_INTSRC_INTSRC11_Pos±ÚPGP_INTSRC_INTSRC11_Msk¸ÚPGP_INTSRC_INTSRC12_Pos°ÚPGP_INTSRC_INTSRC12_Msk·ÚPGP_INTSRC_INTSRC13_Pos¯ÚPGP_INTSRC_INTSRC13_Msk¶ÚPGP_INTSRC_INTSRC14_Pos®ÚPGP_INTSRC_INTSRC14_MskµÚPGP_INTSRC_INTSRC15_Pos­ÚPGP_INTSRC_INTSRC15_Msk´ÚPGP_DBCTL_DBCLKSEL_PosÚPGP_DBCTL_DBCLKSEL_MskÚPGP_DBCTL_DBCLKSRC_Pos


ÚPGP_DBCTL_DBCLKSRC_MskÚPGP_DBCTL_ICLKON_Pos–ÚPGP_DBCTL_ICLKON_MskÚ8


<unnamed>QÚ 


"Î DATÚ <"Î 


RESERVED0Ú 


"Î CTLÚ 


"Î CHENÈÚ 


"Î CMP0ÖÚ 


"Î CMP1ÕÚ 


"Î STATUSþÚ <"Î 


RESERVED1 Ú 


"Î TRGDLYÚ 


"Î EXTSMPT«Ú 


"Î SEQCTLÚ 


"Î SEQDAT1íÚ 


"Î SEQDAT2ìÚ 


"Î CTL2ÑÚ <"Î 


RESERVED2Ú 


"Î BV_CTLÚADC_T|ÚPADC_DAT_RESULT_PosØÚPADC_DAT_RESULT_MskßÚPADC_DAT_OV_PosÚPADC_DAT_OV_Msk!ÚPADC_DAT_VALID_PosIÚPADC_DAT_VALID_MskPÚPADC_CTL_ADCEN_PosTÚPADC_CTL_ADCEN_Msk[ÚPADC_CTL_ADCIEN_Pos    ÚPADC_CTL_ADCIEN_MskÚPADC_CTL_HWTRGSEL_Pos9ÚPADC_CTL_HWTRGSEL_Msk@ÚPADC_CTL_HWTRGCOND_Pos÷ÚPADC_CTL_HWTRGCOND_MskþÚPADC_CTL_HWTRGEN_PosŒÚPADC_CTL_HWTRGEN_Msk“ÚPADC_CTL_FIFO_EN_Pos•ÚPADC_CTL_FIFO_EN_MskœÚ$PADC_CTL_FIFO_THRE_STATE_PosÚ$PADC_CTL_FIFO_THRE_STATE_MskÚPADC_CTL_SWTRG_PosÚPADC_CTL_SWTRG_MskÚ"PADC_CTL_LEFT_SHIFT_EN_Pos¥Ú"PADC_CTL_LEFT_SHIFT_EN_Msk¬Ú PADC_CTL_SUB_BIAS_EN_PosIÚ PADC_CTL_SUB_BIAS_EN_MskPÚPADC_CTL_BIAS_VALUE_PosªÚPADC_CTL_BIAS_VALUE_Msk±ÚPADC_CHEN_CHEN0_Pos$ÚPADC_CHEN_CHEN0_Msk+ÚPADC_CHEN_CHEN1_Pos#ÚPADC_CHEN_CHEN1_Msk*ÚPADC_CHEN_CHEN2_Pos"ÚPADC_CHEN_CHEN2_Msk)ÚPADC_CHEN_CHEN3_Pos!ÚPADC_CHEN_CHEN3_Msk(ÚPADC_CHEN_CHEN4_Pos ÚPADC_CHEN_CHEN4_Msk'ÚPADC_CHEN_CHEN5_PosÚPADC_CHEN_CHEN5_Msk&ÚPADC_CHEN_CHEN6_PosÚPADC_CHEN_CHEN6_Msk%ÚPADC_CHEN_CHEN7_PosÚPADC_CHEN_CHEN7_Msk$ÚPADC_CHEN_CHEN8_VBG_PosÖÚPADC_CHEN_CHEN8_VBG_MskÝÚPADC_CHEN_CH9_TMP_PosZÚPADC_CHEN_CH9_TMP_MskaÚ PADC_CHEN_CH10_VDD_4_Pos¬Ú PADC_CHEN_CH10_VDD_4_Msk³Ú PADC_CHEN_CH11_VBG_2_Pos¬Ú PADC_CHEN_CH11_VBG_2_Msk³ÚPADC_CHEN_ALL_Msk¤ÚPADC_CMP0_ADCMPEN_Pos„ÚPADC_CMP0_ADCMPEN_Msk‹ÚPADC_CMP0_ADCMPIE_Pos‰ÚPADC_CMP0_ADCMPIE_MskÚPADC_CMP0_CMPCOND_PosxÚPADC_CMP0_CMPCOND_MskÚPADC_CMP0_CMPCH_PosÚPADC_CMP0_CMPCH_MskÚPADC_CMP0_CMPMCNT_PosjÚPADC_CMP0_CMPMCNT_MskqÚPADC_CMP0_CMPDAT_PosÅÚPADC_CMP0_CMPDAT_MskÌÚPADC_CMP1_ADCMPEN_PosƒÚPADC_CMP1_ADCMPEN_MskŠÚPADC_CMP1_ADCMPIE_PosˆÚPADC_CMP1_ADCMPIE_MskÚPADC_CMP1_CMPCOND_PoswÚPADC_CMP1_CMPCOND_Msk~ÚPADC_CMP1_CMPCH_PosÚPADC_CMP1_CMPCH_MskÚPADC_CMP1_CMPMCNT_PosiÚPADC_CMP1_CMPMCNT_MskpÚPADC_CMP1_CMPDAT_PosÄÚPADC_CMP1_CMPDAT_MskËÚPADC_STATUS_ADIF_Pos–ÚPADC_STATUS_ADIF_MskÚ PADC_STATUS_ADCMPIF0_Pos~Ú PADC_STATUS_ADCMPIF0_Msk…Ú PADC_STATUS_ADCMPIF1_Pos}Ú PADC_STATUS_ADCMPIF1_Msk„ÚPADC_STATUS_BUSY_PosgÚPADC_STATUS_BUSY_MsknÚPADC_STATUS_CHANNEL_Pos«ÚPADC_STATUS_CHANNEL_Msk²ÚPADC_STATUS_VALID_Pos8ÚPADC_STATUS_VALID_Msk?Ú#PADC_STATUS_INTMSK_FULL_Pos4Ú#PADC_STATUS_INTMSK_FULL_Msk;Ú$PADC_STATUS_INTMSK_EMPTY_PosÖÚ$PADC_STATUS_INTMSK_EMPTY_MskÝÚ#PADC_STATUS_INTMSK_OVER_Pos+Ú#PADC_STATUS_INTMSK_OVER_Msk2Ú#PADC_STATUS_INTMSK_HALF_PosLÚ#PADC_STATUS_INTMSK_HALF_MskSÚ!PADC_STATUS_INTMSK_AD_PosæÚ!PADC_STATUS_INTMSK_AD_MskíÚ#PADC_STATUS_INTMSK_CMP0_PosWÚ#PADC_STATUS_INTMSK_CMP0_Msk^Ú#PADC_STATUS_INTMSK_CMP1_PosVÚ#PADC_STATUS_INTMSK_CMP1_Msk]ÚPADC_STATUS_OV_Pos    ÚPADC_STATUS_OV_MskÚ&PADC_STATUS_ONE_CH_CLR_SEL_PosGÚ&PADC_STATUS_ONE_CH_CLR_SEL_MskNÚ#PADC_STATUS_ONE_CH_FLAG_PosWÚ#PADC_STATUS_ONE_CH_FLAG_Msk^Ú#PADC_STATUS_INTFLG_FULL_PosFÚ#PADC_STATUS_INTFLG_FULL_MskMÚ$PADC_STATUS_INTFLG_EMPTY_PosèÚ$PADC_STATUS_INTFLG_EMPTY_MskïÚ#PADC_STATUS_INTFLG_OVER_Pos=Ú#PADC_STATUS_INTFLG_OVER_MskDÚ#PADC_STATUS_INTFLG_HALF_Pos^Ú#PADC_STATUS_INTFLG_HALF_MskeÚPADC_STATUS_ADCF_PosœÚPADC_STATUS_ADCF_Msk£ÚPADC_STATUS_ADCMPF0_PosÉÚPADC_STATUS_ADCMPF0_MskÐÚPADC_STATUS_ADCMPF1_PosÈÚPADC_STATUS_ADCMPF1_MskÏÚ!PADC_STATUS_FLAG_FULL_PosôÚ!PADC_STATUS_FLAG_FULL_MskûÚ"PADC_STATUS_FLAG_EMPTY_Pos–Ú"PADC_STATUS_FLAG_EMPTY_MskÚ!PADC_STATUS_FLAG_OVER_PosëÚ!PADC_STATUS_FLAG_OVER_MskòÚ!PADC_STATUS_FLAG_HALF_PosÚ!PADC_STATUS_FLAG_HALF_MskÚPADC_TRGDLY_DELAY_PosGÚPADC_TRGDLY_DELAY_MskNÚ PADC_EXTSMPT_EXTSMPT_PosÚ PADC_EXTSMPT_EXTSMPT_Msk#ÚPADC_SEQCTL_SEQEN_PosDÚPADC_SEQCTL_SEQEN_MskKÚPADC_SEQCTL_SEQTYPE_Pos‘ÚPADC_SEQCTL_SEQTYPE_Msk˜ÚPADC_SEQCTL_MODESEL_Pos³ÚPADC_SEQCTL_MODESEL_MskºÚ PADC_SEQCTL_DELAY_EN_PosYÚ PADC_SEQCTL_DELAY_EN_Msk`ÚPADC_SEQCTL_TRG_SEL_PosŒÚPADC_SEQCTL_TRG_SEL_Msk“Ú!PADC_SEQCTL_ONE_CH_EN_PosúÚ!PADC_SEQCTL_ONE_CH_EN_MskÚPADC_SEQCTL_TRG1CTL_Pos»ÚPADC_SEQCTL_TRG1CTL_MskÂÚPADC_SEQCTL_TRG2CTL_PosºÚPADC_SEQCTL_TRG2CTL_MskÁÚPADC_SEQDAT1_RESULT_Pos¶ÚPADC_SEQDAT1_RESULT_Msk½ÚPADC_SEQDAT1_OV_PosøÚPADC_SEQDAT1_OV_MskÿÚPADC_SEQDAT1_VALID_Pos'ÚPADC_SEQDAT1_VALID_Msk.ÚPADC_SEQDAT2_RESULT_PosµÚPADC_SEQDAT2_RESULT_Msk¼ÚPADC_SEQDAT2_OV_Pos÷ÚPADC_SEQDAT2_OV_MskþÚPADC_SEQDAT2_VALID_Pos&ÚPADC_SEQDAT2_VALID_Msk-ÚPADC_CTL2_TESTMODE_PosÚPADC_CTL2_TESTMODE_MskÚPADC_CTL2_SHSEL_PosüÚPADC_CTL2_SHSEL_MskÚPADC_CTL2_DMA_EN_PosµÚPADC_CTL2_DMA_EN_Msk¼ÚPADC_CTL2_CLKDIV_Pos¼ÚPADC_CTL2_CLKDIV_MskÃÚPADC_SEL_VREF_Pos}ÚPADC_SEL_VREF_Msk„ÚPADC_CTL2_CMPCTL_Pos¶ÚPADC_CTL2_CMPCTL_Msk½ÚPADC_CTL2_DRVCTL_PosªÚPADC_CTL2_DRVCTL_Msk±Ú8


<unnamed>QÚ 


"‘P0_MFP[Ú 


"‘P1_MFPZÚ 


"‘P2_MFPYÚ 


"‘P3_MFPXÚ <"0‘RESVƒÚ 


"‘REGLCTLÚ 


"‘STATUS9Ú 


"‘CTRL0ºÚ 


"‘CTRL1¹ÚSYS_TEÚPSYS_P0_MFP_MFP_Pos´ÚPSYS_P0_MFP_MFP_Msk»ÚPSYS_P0_MFP_ALT0_Pos„ÚPSYS_P0_MFP_ALT0_Msk‹ÚPSYS_P0_MFP_ALT1_PosƒÚPSYS_P0_MFP_ALT1_MskŠÚPSYS_P0_MFP_ALT2_Pos‚ÚPSYS_P0_MFP_ALT2_Msk‰ÚPSYS_P0_MFP_ALT3_PosÚPSYS_P0_MFP_ALT3_MskˆÚPSYS_P0_MFP_ALT4_Pos€ÚPSYS_P0_MFP_ALT4_Msk‡ÚPSYS_P0_MFP_ALT5_PosÚPSYS_P0_MFP_ALT5_Msk†ÚPSYS_P0_MFP_ALT6_Pos~ÚPSYS_P0_MFP_ALT6_Msk…ÚPSYS_P0_MFP_ALT7_Pos}ÚPSYS_P0_MFP_ALT7_Msk„ÚPSYS_P1_MFP_MFP_Pos³ÚPSYS_P1_MFP_MFP_MskºÚPSYS_P1_MFP_ALT0_PosƒÚPSYS_P1_MFP_ALT0_MskŠÚPSYS_P1_MFP_ALT1_Pos‚ÚPSYS_P1_MFP_ALT1_Msk‰ÚPSYS_P1_MFP_ALT2_PosÚPSYS_P1_MFP_ALT2_MskˆÚPSYS_P1_MFP_ALT3_Pos€ÚPSYS_P1_MFP_ALT3_Msk‡ÚPSYS_P1_MFP_ALT4_PosÚPSYS_P1_MFP_ALT4_Msk†ÚPSYS_P1_MFP_ALT5_Pos~ÚPSYS_P1_MFP_ALT5_Msk…ÚPSYS_P1_MFP_ALT6_Pos}ÚPSYS_P1_MFP_ALT6_Msk„ÚPSYS_P1_MFP_ALT7_Pos|ÚPSYS_P1_MFP_ALT7_MskƒÚPSYS_P1_MFP_TYPE_PosRÚPSYS_P1_MFP_TYPE_MskYÚPSYS_P1_MFP_P12EXT_PosìÚPSYS_P1_MFP_P12EXT_MskóÚPSYS_P1_MFP_P13EXT_PosëÚPSYS_P1_MFP_P13EXT_MskòÚPSYS_P1_MFP_P14EXT_PosêÚPSYS_P1_MFP_P14EXT_MskñÚPSYS_P2_MFP_ALT0_Pos‚ÚPSYS_P2_MFP_ALT0_Msk‰ÚPSYS_P2_MFP_ALT1_PosÚPSYS_P2_MFP_ALT1_MskˆÚPSYS_P2_MFP_ALT2_Pos€ÚPSYS_P2_MFP_ALT2_Msk‡ÚPSYS_P2_MFP_ALT3_PosÚPSYS_P2_MFP_ALT3_Msk†ÚPSYS_P2_MFP_ALT4_Pos~ÚPSYS_P2_MFP_ALT4_Msk…ÚPSYS_P2_MFP_ALT5_Pos}ÚPSYS_P2_MFP_ALT5_Msk„ÚPSYS_P2_MFP_ALT6_Pos|ÚPSYS_P2_MFP_ALT6_MskƒÚPSYS_P2_MFP_ALT7_Pos{ÚPSYS_P2_MFP_ALT7_Msk‚ÚPSYS_P3_MFP_MFP_Pos±ÚPSYS_P3_MFP_MFP_Msk¸ÚPSYS_P3_MFP_ALT0_PosÚPSYS_P3_MFP_ALT0_MskˆÚPSYS_P3_MFP_ALT1_Pos€ÚPSYS_P3_MFP_ALT1_Msk‡ÚPSYS_P3_MFP_ALT2_PosÚPSYS_P3_MFP_ALT2_Msk†ÚPSYS_P3_MFP_ALT4_Pos}ÚPSYS_P3_MFP_ALT4_Msk„ÚPSYS_P3_MFP_ALT5_Pos|ÚPSYS_P3_MFP_ALT5_MskƒÚPSYS_P3_MFP_ALT6_Pos{ÚPSYS_P3_MFP_ALT6_Msk‚ÚPSYS_P3_MFP_P32EXT_PosèÚPSYS_P3_MFP_P32EXT_MskïÚPSYS_P4_MFP_MFP_Pos°ÚPSYS_P4_MFP_MFP_Msk·ÚPSYS_P4_MFP_ALT6_PoszÚPSYS_P4_MFP_ALT6_MskÚPSYS_P4_MFP_ALT7_PosyÚPSYS_P4_MFP_ALT7_Msk€ÚPSYS_P5_MFP_MFP_Pos¯ÚPSYS_P5_MFP_MFP_Msk¶ÚPSYS_P5_MFP_ALT0_PosÚPSYS_P5_MFP_ALT0_Msk†ÚPSYS_P5_MFP_ALT1_Pos~ÚPSYS_P5_MFP_ALT1_Msk…ÚPSYS_P5_MFP_ALT2_Pos}ÚPSYS_P5_MFP_ALT2_Msk„ÚPSYS_P5_MFP_ALT3_Pos|ÚPSYS_P5_MFP_ALT3_MskƒÚPSYS_P5_MFP_ALT4_Pos{ÚPSYS_P5_MFP_ALT4_Msk‚ÚPSYS_P5_MFP_ALT5_PoszÚPSYS_P5_MFP_ALT5_MskÚPSYS_P5_MFP_ALT6_PosyÚPSYS_P5_MFP_ALT6_Msk€ÚPSYS_P5_MFP_ALT7_PosxÚPSYS_P5_MFP_ALT7_MskÚPSYS_P5_MFP_P50EXT_PosæÚPSYS_P5_MFP_P50EXT_MskíÚPSYS_P5_MFP_P51EXT_PosåÚPSYS_P5_MFP_P51EXT_MskìÚ PSYS_REGLCTL_REGLCTL_Pos5Ú PSYS_REGLCTL_REGLCTL_Msk<Ú8


<unnamed>QÚ 


"†RSTSTS4Ú 


"†IPRST0eÚ 


"†IPRST1dÚ 


"†


BODCTL_3VÚ 


"†BLDBCTL_3V@Ú 


"†CLK_TOP_CTRL_3VmÚ 


"†RCL_CTRL_3VÀÚ 


"†    RCH_CTRL²Ú 


"†XTL_CTRL_3V©Ú 


"†    XTH_CTRL›Ú 


"†


DPLL_CTRLaÚ 


"† AHB_CLK_CTRLƒÚ 


"†APB1_CLK_CTRLHÚ 


"†APB2_CLK_CTRLGÚ 


"†MEAS_CLK_CTRL&ÚCLK_TjÚPCLK_RSTSTS_CHIPRF_PosÉÚPCLK_RSTSTS_CHIPRF_MskÐÚPCLK_RSTSTS_PINRF_PosÚPCLK_RSTSTS_PINRF_MskÚPCLK_RSTSTS_WDTRF_PosÚPCLK_RSTSTS_WDTRF_MskÚPCLK_RSTSTS_LVRRF_PosûÚPCLK_RSTSTS_LVRRF_MskÚPCLK_RSTSTS_BODRF_PosÚPCLK_RSTSTS_BODRF_Msk!ÚPCLK_RSTSTS_SYSRF_PosðÚPCLK_RSTSTS_SYSRF_Msk÷ÚPCLK_RSTSTS_PORRF_PosþÚPCLK_RSTSTS_PORRF_MskÚPCLK_RSTSTS_CPURF_PosÚPCLK_RSTSTS_CPURF_MskÚPCLK_IPRST0_CHIPRST_Pos—ÚPCLK_IPRST0_CHIPRST_MskžÚPCLK_IPRST0_CPURST_PosÕÚPCLK_IPRST0_CPURST_MskÜÚPCLK_IPRST0_DMARST_PosëÚPCLK_IPRST0_DMARST_MskòÚPCLK_IPRST0_RFRST_Pos'ÚPCLK_IPRST0_RFRST_Msk.Ú PCLK_IPRST0_EFUSERST_PosAÚ PCLK_IPRST0_EFUSERST_MskHÚPCLK_IPRST0_USBRST_PosÓÚPCLK_IPRST0_USBRST_MskÚÚ#PCLK_IPRST0_MDMSTDBYRST_PosOÚ#PCLK_IPRST0_MDMSTDBYRST_MskVÚPCLK_IPRST0_MDMRST_PosßÚPCLK_IPRST0_MDMRST_MskæÚ#PCLK_IPRST0_CHIPSCOPEEN_Pos{Ú#PCLK_IPRST0_CHIPSCOPEEN_Msk‚ÚPCLK_IPRST0_FTORRST_Pos€ÚPCLK_IPRST0_FTORRST_Msk‡ÚPCLK_IPRST1_I2C0RST_PosÌÚPCLK_IPRST1_I2C0RST_MskÓÚPCLK_IPRST1_SPI0RST_PosžÚPCLK_IPRST1_SPI0RST_Msk¥ÚPCLK_IPRST1_SPI1RST_PosÚPCLK_IPRST1_SPI1RST_Msk¤Ú PCLK_IPRST1_UART0RST_PosLÚ PCLK_IPRST1_UART0RST_MskSÚ PCLK_IPRST1_UART1RST_PosKÚ PCLK_IPRST1_UART1RST_MskRÚPCLK_IPRST1_PWM0RST_Pos–ÚPCLK_IPRST1_PWM0RST_MskÚPCLK_IPRST1_ADCRST_PosôÚPCLK_IPRST1_ADCRST_MskûÚPCLK_IPRST1_WDTRST_PosÍÚPCLK_IPRST1_WDTRST_MskÔÚPCLK_IPRST1_WWDTRST_PostÚPCLK_IPRST1_WWDTRST_Msk{ÚPCLK_IPRST1_TMR0RST_Pos—ÚPCLK_IPRST1_TMR0RST_MskžÚPCLK_IPRST1_TMR1RST_Pos–ÚPCLK_IPRST1_TMR1RST_MskÚPCLK_IPRST1_TMR2RST_Pos•ÚPCLK_IPRST1_TMR2RST_MskœÚPCLK_IPRST1_GPIORST_Pos‹ÚPCLK_IPRST1_GPIORST_Msk’ÚPCLK_IPRST1_TRIMRST_Pos~ÚPCLK_IPRST1_TRIMRST_Msk…Ú#PCLK_BODCTL_BODRSTEN_Pos_3vMÚ#PCLK_BODCTL_BODRSTEN_Msk_3vTÚPCLK_BODCTL_BODIF_Pos^ÚPCLK_BODCTL_BODIF_MskeÚPCLK_BODCTL_BODOUT_PosóÚPCLK_BODCTL_BODOUT_MskúÚ PCLK_BODCTL_LVREN_Pos_3v-Ú PCLK_BODCTL_LVREN_Msk_3v4Ú PCLK_BODCTL_BODEN_Pos_3vLÚ PCLK_BODCTL_BODEN_Msk_3vSÚ!PCLK_BODCTL_BODSEL_Pos_3vùÚ!PCLK_BODCTL_BODSEL_Msk_3vÚ#PCLK_BODCTL_LVR_TEST_Pos_3vÚ#PCLK_BODCTL_LVR_TEST_Msk_3v"Ú#PCLK_BODCTL_BOD_TEST_Pos_3v:Ú#PCLK_BODCTL_BOD_TEST_Msk_3vAÚ%PCLK_BLDBCTL_LVRDB_SEL_Pos_3v®Ú%PCLK_BLDBCTL_LVRDB_SEL_Msk_3vµÚ%PCLK_BLDBCTL_BODDB_SEL_Pos_3vÍÚ%PCLK_BLDBCTL_BODDB_SEL_Msk_3vÔÚ'PCLK_TOPCTL_RSICV_SYSCNT_EN_PosÔÚ'PCLK_TOPCTL_RSICV_SYSCNT_EN_MskÛÚ#PCLK_TOPCTL_SYS_CLK_SEL_PosÚ#PCLK_TOPCTL_SYS_CLK_SEL_Msk$Ú&PCLK_TOPCTL_32K_CLK_SEL_Pos_3v^Ú&PCLK_TOPCTL_32K_CLK_SEL_Msk_3veÚPCLK_TOPCTL_AHB_DIV_Pos“ÚPCLK_TOPCTL_AHB_DIV_MskšÚ PCLK_TOPCTL_APB1_DIV_PosXÚ PCLK_TOPCTL_APB1_DIV_Msk_Ú PCLK_TOPCTL_APB2_DIV_PosWÚ PCLK_TOPCTL_APB2_DIV_Msk^Ú#PCLK_RCLCTL_RC32K_EN_Pos_3vkÚ#PCLK_RCLCTL_RC32K_EN_Msk_3vrÚ$PCLK_RCLCTL_RC32K_TST_EN_PosÚ$PCLK_RCLCTL_RC32K_TST_EN_MskÚ"PCLK_RCLCTL_CLK_SEL_Pos_3v‡Ú"PCLK_RCLCTL_CLK_SEL_Msk_3vŽÚ'PCLK_RCLCTL_RC32K_COARSE_Pos_3v9Ú'PCLK_RCLCTL_RC32K_COARSE_Msk_3v@Ú%PCLK_RCLCTL_RC32K_FINE_Pos_3vØÚ%PCLK_RCLCTL_RC32K_FINE_Msk_3vßÚ&PCLK_RCLCTL_RC32K_DELAY_Pos_3v‰Ú&PCLK_RCLCTL_RC32K_DELAY_Msk_3vÚPCLK_RCLCTL_STABLE_PosùÚPCLK_RCLCTL_STABLE_MskÚPCLK_RCHCTL_RCH_EN_PoséÚPCLK_RCHCTL_RCH_EN_MskðÚ"PCLK_RCHCTL_RCH_TST_EN_Pos‡Ú"PCLK_RCHCTL_RCH_TST_EN_MskŽÚPCLK_RCHCTL_CLK_SEL_Pos™ÚPCLK_RCHCTL_CLK_SEL_Msk ÚPCLK_RCHCTL_BIAS_PosÚPCLK_RCHCTL_BIAS_Msk¤Ú PCLK_RCHCTL_RCH_FREQ_PosJÚ PCLK_RCHCTL_RCH_FREQ_MskQÚPCLK_RCHCTL_DELAY_PosKÚPCLK_RCHCTL_DELAY_MskRÚPCLK_RCHCTL_STABLE_PosýÚPCLK_RCHCTL_STABLE_MskÚ!PCLK_XTLCTL_XTL_EN_Pos_3v¥Ú!PCLK_XTLCTL_XTL_EN_Msk_3v¬Ú"PCLK_XTLCTL_XTL_TST_EN_PosQÚ"PCLK_XTLCTL_XTL_TST_EN_MskXÚ$PCLK_XTLCTL_CORE_BIAS_Pos_3vâÚ$PCLK_XTLCTL_CORE_BIAS_Msk_3véÚ#PCLK_XTLCTL_XTL_TRIM_Pos_3vøÚ#PCLK_XTLCTL_XTL_TRIM_Msk_3vÿÚ%PCLK_XTLCTL_XTL_CAP_EN_Pos_3vjÚ%PCLK_XTLCTL_XTL_CAP_EN_Msk_3vqÚ PCLK_XTLCTL_DELAY_Pos_3v"Ú PCLK_XTLCTL_DELAY_Msk_3v)ÚPCLK_XTLCTL_STABLE_PosâÚPCLK_XTLCTL_STABLE_MskéÚPCLK_XTHCTL_XTH_EN_Pos»ÚPCLK_XTHCTL_XTH_EN_MskÂÚ"PCLK_XTHCTL_XTH_TST_EN_PosYÚ"PCLK_XTHCTL_XTH_TST_EN_Msk`Ú"PCLK_XTHCTL_START_FAST_Pos~Ú"PCLK_XTHCTL_START_FAST_Msk…Ú#PCLK_XTHCTL_DEGLITCH_EN_PosaÚ#PCLK_XTHCTL_DEGLITCH_EN_MskhÚ"PCLK_XTHCTL_XO_CAP_SEL_Pos|Ú"PCLK_XTHCTL_XO_CAP_SEL_MskƒÚPCLK_XTHCTL_DELAY_Pos4ÚPCLK_XTHCTL_DELAY_Msk;ÚPCLK_XTHCTL_STABLE_PosæÚPCLK_XTHCTL_STABLE_MskíÚ PCLK_DPLLCTL_DPLL_EN_PosGÚ PCLK_DPLLCTL_DPLL_EN_MskNÚ$PCLK_DPLLCTL_DPLL_TST_EN_PosåÚ$PCLK_DPLLCTL_DPLL_TST_EN_MskìÚ!PCLK_DPLLCTL_FREQ_OUT_PosÞÚ!PCLK_DPLLCTL_FREQ_OUT_MskåÚ!PCLK_DPLLCTL_RCLK_SEL_PosôÚ!PCLK_DPLLCTL_RCLK_SEL_MskûÚ!PCLK_DPLLCTL_ICP_BIAS_Pos    Ú!PCLK_DPLLCTL_ICP_BIAS_MskÚ!PCLK_DPLLCTL_ICP_CTRL_PosóÚ!PCLK_DPLLCTL_ICP_CTRL_MskúÚ"PCLK_DPLLCTL_KVCO_CTRL_PosšÚ"PCLK_DPLLCTL_KVCO_CTRL_Msk¡Ú&PCLK_DPLLCTL_VCO_FREQ_TRIM_PosIÚ&PCLK_DPLLCTL_VCO_FREQ_TRIM_MskPÚ PCLK_DPLLCTL_DIV_SEL_Pos?Ú PCLK_DPLLCTL_DIV_SEL_MskFÚPCLK_DPLLCTL_DELAY_PosúÚPCLK_DPLLCTL_DELAY_MskÚPCLK_DPLLCTL_STABLE_Pos¬ÚPCLK_DPLLCTL_STABLE_Msk³ÚPCLK_AHBCLK_DMAEN_PospÚPCLK_AHBCLK_DMAEN_MskwÚPCLK_AHBCLK_GPIOEN_PosÚPCLK_AHBCLK_GPIOEN_MskÚ"PCLK_AHBCLK_SYSTICK_EN_Pos¯Ú"PCLK_AHBCLK_SYSTICK_EN_Msk¶ÚPCLK_AHBCLK_APB1EN_Pos<ÚPCLK_AHBCLK_APB1EN_MskCÚPCLK_AHBCLK_APB2EN_Pos;ÚPCLK_AHBCLK_APB2EN_MskBÚPCLK_AHBCLK_AHBEN_PoswÚPCLK_AHBCLK_AHBEN_Msk~Ú!PCLK_AHBCLK_BLE32M_EN_PosVÚ!PCLK_AHBCLK_BLE32M_EN_Msk]Ú!PCLK_AHBCLK_BLE32K_EN_PosXÚ!PCLK_AHBCLK_BLE32K_EN_Msk_Ú"PCLK_AHBCLK_BLE32M_SEL_PosÚ"PCLK_AHBCLK_BLE32M_SEL_Msk


Ú"PCLK_AHBCLK_ROM_CLK_EN_Pos²Ú"PCLK_AHBCLK_ROM_CLK_EN_Msk¹Ú$PCLK_AHBCLK_EFUSE_CLK_EN_Pos$Ú$PCLK_AHBCLK_EFUSE_CLK_EN_Msk+Ú&PCLK_AHBCLK_USB_AHB_CLK_EN_Pos„Ú&PCLK_AHBCLK_USB_AHB_CLK_EN_Msk‹Ú&PCLK_AHBCLK_USB_48M_CLK_EN_Pos–Ú&PCLK_AHBCLK_USB_48M_CLK_EN_MskÚ%PCLK_AHBCLK_SPI_FLASH_DIV_PosÊÚ%PCLK_AHBCLK_SPI_FLASH_DIV_MskÑÚ)P!CLK_AHBCLK_SPI_FLASH_CLK_SEL_PosˆÚ)P!CLK_AHBCLK_SPI_FLASH_CLK_SEL_MskÚ'PCLK_AHBCLK_DPLL_CLK_TST_EN_PosÚ'PCLK_AHBCLK_DPLL_CLK_TST_EN_MskÚ(P CLK_AHBCLK_SPI_CLK_SEL_FPGA_PosÚÚ(P CLK_AHBCLK_SPI_CLK_SEL_FPGA_MskáÚ#PCLK_APB1CLK_WDTSRC_SEL_PosvÚ#PCLK_APB1CLK_WDTSRC_SEL_Msk}Ú$PCLK_APB1CLK_WWDTSRC_SEL_PosÚ$PCLK_APB1CLK_WWDTSRC_SEL_Msk$Ú$PCLK_APB1CLK_TMR0SRC_SEL_Pos@Ú$PCLK_APB1CLK_TMR0SRC_SEL_MskGÚ&PCLK_APB1CLK_PWM01_CLK_SEL_Pos¹Ú&PCLK_APB1CLK_PWM01_CLK_SEL_MskÀÚ&PCLK_APB1CLK_PWM23_CLK_SEL_PosµÚ&PCLK_APB1CLK_PWM23_CLK_SEL_Msk¼Ú&PCLK_APB1CLK_PWM45_CLK_SEL_Pos±Ú&PCLK_APB1CLK_PWM45_CLK_SEL_Msk¸Ú&PCLK_APB1CLK_PWM67_CLK_SEL_Pos­Ú&PCLK_APB1CLK_PWM67_CLK_SEL_Msk´Ú$PCLK_APB1CLK_ADC_CLK_SEL_PosJÚ$PCLK_APB1CLK_ADC_CLK_SEL_MskQÚ$PCLK_APB2CLK_TMR1SRC_SEL_Pos>Ú$PCLK_APB2CLK_TMR1SRC_SEL_MskEÚ$PCLK_APB2CLK_TMR2SRC_SEL_Pos=Ú$PCLK_APB2CLK_TMR2SRC_SEL_MskDÚ$PCLK_MEASCLK_TRIM_CLK_EN_PosÚ$PCLK_MEASCLK_TRIM_CLK_EN_MskÚ%PCLK_MEASCLK_TRIM_CLK_SEL_Pos²Ú%PCLK_MEASCLK_TRIM_CLK_SEL_Msk¹Ú%PCLK_MEASCLK_TRIM_CLK_DIV_Pos³Ú%PCLK_MEASCLK_TRIM_CLK_DIV_MskºÚ%PCLK_MEASCLK_XTL_QUICK_EN_Pos¤Ú%PCLK_MEASCLK_XTL_QUICK_EN_Msk«Ú PCLK_MEASCLK_XTH_DIV_Pos>Ú PCLK_MEASCLK_XTH_DIV_MskEÚ8


<unnamed>QÚ 


"…CTLIÚ 


"…ALTCTLbÚWDT_TUÚPWDT_CTL_RSTCNT_Pos¨ÚPWDT_CTL_RSTCNT_Msk¯ÚPWDT_CTL_RSTEN_PosüÚPWDT_CTL_RSTEN_MskÚPWDT_CTL_RSTF_PosKÚPWDT_CTL_RSTF_MskRÚPWDT_CTL_IF_PosÿÚPWDT_CTL_IF_MskÚPWDT_CTL_WKEN_PosUÚPWDT_CTL_WKEN_Msk\ÚPWDT_CTL_WKF_Pos¤ÚPWDT_CTL_WKF_Msk«ÚPWDT_CTL_INTEN_Pos


ÚPWDT_CTL_INTEN_MskÚPWDT_CTL_WDTEN_PosÚPWDT_CTL_WDTEN_Msk ÚPWDT_CTL_TOUTSEL_PosTÚPWDT_CTL_TOUTSEL_Msk[Ú#PWDT_CTL_RST_REGION_SEL_PosÚ#PWDT_CTL_RST_REGION_SEL_MskÚPWDT_CTL_TOF_Pos£ÚPWDT_CTL_TOF_MskªÚPWDT_CTL_ICEDEBUG_PosJÚPWDT_CTL_ICEDEBUG_MskQÚPWDT_ALTCTL_RSTDSEL_Pos|ÚPWDT_ALTCTL_RSTDSEL_MskƒÚ8


<unnamed>QÚ 


"£RLDCNTAÚ 


"£CTL+Ú 


"£STATUS$Ú 


"£CNT)ÚWWDT_TüÚPWWDT_RLDCNT_RLDCNT_Pos|ÚPWWDT_RLDCNT_RLDCNT_MskƒÚPWWDT_CTL_WWDTEN_PosTÚPWWDT_CTL_WWDTEN_Msk[ÚPWWDT_CTL_INTEN_Pos±ÚPWWDT_CTL_INTEN_Msk¸ÚPWWDT_CTL_PSCSEL_PoscÚPWWDT_CTL_PSCSEL_MskjÚPWWDT_CTL_CMPDAT_PostÚPWWDT_CTL_CMPDAT_Msk{ÚPWWDT_CTL_ICEDEBUG_PosñÚPWWDT_CTL_ICEDEBUG_MskøÚPWWDT_STATUS_WWDTIF_PosQÚPWWDT_STATUS_WWDTIF_MskXÚPWWDT_STATUS_WWDTRF_PosHÚPWWDT_STATUS_WWDTRF_MskOÚPWWDT_STATUS_WWDTF_PosœÚPWWDT_STATUS_WWDTF_Msk£ÚPWWDT_CNT_CNTDAT_PosmÚPWWDT_CNT_CNTDAT_MsktÚ8


<unnamed>QÚ 


"½CLKPSC.Ú 


"½CLKDIV1Ú 


"½CTLÚ 


"½PERIOD0ùÚ 


"½PERIOD1øÚ 


"½PERIOD2÷Ú 


"½PERIOD3öÚ 


"½PERIOD4õÚ 


"½PERIOD5ôÚ 


"½PERIOD6óÚ 


"½PERIOD7òÚ 


"½CMPDAT0Ú 


"½CMPDAT1Ú 


"½CMPDAT2Ú 


"½CMPDAT3Ú 


"½CMPDAT4ÿÚ 


"½CMPDAT5þÚ 


"½CMPDAT6ýÚ 


"½CMPDAT7üÚ 


"½CTL2ÝÚ 


"½FLAGØÚ 


"½INTENrÚ 


"½INTSTS    Ú 


"½POENÀÚ <"½


RESERVED0&Ú 


"½DTCTLuÚ 


"½    ADCTCTL0»Ú 


"½    ADCTCTL1ºÚ 


"½    ADCTSTS0¤Ú 


"½    ADCTSTS1£Ú <"½


RESERVED1Ú 


"½PCACTL7ÚPWM_TPÚ PPWM_CLKPSC_CLKPSC01_PosyÚ PPWM_CLKPSC_CLKPSC01_Msk€Ú PPWM_CLKPSC_CLKPSC23_PosuÚ PPWM_CLKPSC_CLKPSC23_Msk|Ú PPWM_CLKPSC_CLKPSC45_PosqÚ PPWM_CLKPSC_CLKPSC45_MskxÚ PPWM_CLKPSC_CLKPSC67_PosmÚ PPWM_CLKPSC_CLKPSC67_MsktÚPPWM_CLKDIV_CLKDIV0_Pos²ÚPPWM_CLKDIV_CLKDIV0_Msk¹ÚPPWM_CLKDIV_CLKDIV1_Pos±ÚPPWM_CLKDIV_CLKDIV1_Msk¸ÚPPWM_CLKDIV_CLKDIV2_Pos°ÚPPWM_CLKDIV_CLKDIV2_Msk·ÚPPWM_CLKDIV_CLKDIV3_Pos¯ÚPPWM_CLKDIV_CLKDIV3_Msk¶ÚPPWM_CLKDIV_CLKDIV4_Pos®ÚPPWM_CLKDIV_CLKDIV4_MskµÚPPWM_CLKDIV_CLKDIV5_Pos­ÚPPWM_CLKDIV_CLKDIV5_Msk´ÚPPWM_CLKDIV_CLKDIV6_Pos¬ÚPPWM_CLKDIV_CLKDIV6_Msk³ÚPPWM_CLKDIV_CLKDIV7_Pos«ÚPPWM_CLKDIV_CLKDIV7_Msk²ÚPPWM_CTL_CNTEN0_PosÙÚPPWM_CTL_CNTEN0_MskàÚPPWM_CTL_PINV0_PosÚPPWM_CTL_PINV0_MskÚPPWM_CTL_CNTMODE0_PosCÚPPWM_CTL_CNTMODE0_MskJÚPPWM_CTL_CNTEN1_PosØÚPPWM_CTL_CNTEN1_MskßÚPPWM_CTL_HCUPDT_Pos¹ÚPPWM_CTL_HCUPDT_MskÀÚPPWM_CTL_PINV1_PosÚPPWM_CTL_PINV1_MskÚPPWM_CTL_CNTMODE1_PosBÚPPWM_CTL_CNTMODE1_MskIÚPPWM_CTL_CNTEN2_Pos×ÚPPWM_CTL_CNTEN2_MskÞÚPPWM_CTL_PINV2_PosÚPPWM_CTL_PINV2_MskÚPPWM_CTL_CNTMODE2_PosAÚPPWM_CTL_CNTMODE2_MskHÚPPWM_CTL_CNTEN3_PosÖÚPPWM_CTL_CNTEN3_MskÝÚPPWM_CTL_PINV3_PosÚPPWM_CTL_PINV3_MskÚPPWM_CTL_CNTMODE3_Pos@ÚPPWM_CTL_CNTMODE3_MskGÚPPWM_CTL_CNTEN4_PosÕÚPPWM_CTL_CNTEN4_MskÜÚPPWM_CTL_PINV4_PosÚPPWM_CTL_PINV4_MskÚPPWM_CTL_CNTMODE4_Pos?ÚPPWM_CTL_CNTMODE4_MskFÚPPWM_CTL_CNTEN5_PosÔÚPPWM_CTL_CNTEN5_MskÛÚPPWM_CTL_ASYMEN_Pos´ÚPPWM_CTL_ASYMEN_Msk»ÚPPWM_CTL_PINV5_PosÚPPWM_CTL_PINV5_MskÚPPWM_CTL_CNTMODE5_Pos>ÚPPWM_CTL_CNTMODE5_MskEÚPPWM_CTL_CNTEN6_PosÓÚPPWM_CTL_CNTEN6_MskÚÚPPWM_CTL_PINV6_PosÚPPWM_CTL_PINV6_MskÚPPWM_CTL_CNTMODE6_Pos=ÚPPWM_CTL_CNTMODE6_MskDÚPPWM_CTL_CNTEN7_PosÒÚPPWM_CTL_CNTEN7_MskÙÚPPWM_CTL_PINV7_PosÚPPWM_CTL_PINV7_MskÚPPWM_CTL_CNTMODE7_Pos<ÚPPWM_CTL_CNTMODE7_MskCÚ PPWM_PERIOD0_PERIOD0_PostÚ PPWM_PERIOD0_PERIOD0_Msk{Ú PPWM_PERIOD0_PERIOD1_PossÚ PPWM_PERIOD0_PERIOD1_MskzÚ PPWM_PERIOD0_PERIOD2_PosrÚ PPWM_PERIOD0_PERIOD2_MskyÚ PPWM_PERIOD0_PERIOD3_PosqÚ PPWM_PERIOD0_PERIOD3_MskxÚ PPWM_PERIOD0_PERIOD4_PospÚ PPWM_PERIOD0_PERIOD4_MskwÚ PPWM_PERIOD0_PERIOD5_PosoÚ PPWM_PERIOD0_PERIOD5_MskvÚ PPWM_PERIOD0_PERIOD6_PosnÚ PPWM_PERIOD0_PERIOD6_MskuÚ PPWM_PERIOD0_PERIOD7_PosmÚ PPWM_PERIOD0_PERIOD7_MsktÚ PPWM_PERIOD1_PERIOD0_PossÚ PPWM_PERIOD1_PERIOD0_MskzÚ PPWM_PERIOD1_PERIOD1_PosrÚ PPWM_PERIOD1_PERIOD1_MskyÚ PPWM_PERIOD1_PERIOD2_PosqÚ PPWM_PERIOD1_PERIOD2_MskxÚ PPWM_PERIOD1_PERIOD3_PospÚ PPWM_PERIOD1_PERIOD3_MskwÚ PPWM_PERIOD1_PERIOD4_PosoÚ PPWM_PERIOD1_PERIOD4_MskvÚ PPWM_PERIOD1_PERIOD5_PosnÚ PPWM_PERIOD1_PERIOD5_MskuÚ PPWM_PERIOD1_PERIOD6_PosmÚ PPWM_PERIOD1_PERIOD6_MsktÚ PPWM_PERIOD1_PERIOD7_PoslÚ PPWM_PERIOD1_PERIOD7_MsksÚ PPWM_PERIOD2_PERIOD0_PosrÚ PPWM_PERIOD2_PERIOD0_MskyÚ PPWM_PERIOD2_PERIOD1_PosqÚ PPWM_PERIOD2_PERIOD1_MskxÚ PPWM_PERIOD2_PERIOD2_PospÚ PPWM_PERIOD2_PERIOD2_MskwÚ PPWM_PERIOD2_PERIOD3_PosoÚ PPWM_PERIOD2_PERIOD3_MskvÚ PPWM_PERIOD2_PERIOD4_PosnÚ PPWM_PERIOD2_PERIOD4_MskuÚ PPWM_PERIOD2_PERIOD5_PosmÚ PPWM_PERIOD2_PERIOD5_MsktÚ PPWM_PERIOD2_PERIOD6_PoslÚ PPWM_PERIOD2_PERIOD6_MsksÚ PPWM_PERIOD2_PERIOD7_PoskÚ PPWM_PERIOD2_PERIOD7_MskrÚ PPWM_PERIOD3_PERIOD0_PosqÚ PPWM_PERIOD3_PERIOD0_MskxÚ PPWM_PERIOD3_PERIOD1_PospÚ PPWM_PERIOD3_PERIOD1_MskwÚ PPWM_PERIOD3_PERIOD2_PosoÚ PPWM_PERIOD3_PERIOD2_MskvÚ PPWM_PERIOD3_PERIOD3_PosnÚ PPWM_PERIOD3_PERIOD3_MskuÚ PPWM_PERIOD3_PERIOD4_PosmÚ PPWM_PERIOD3_PERIOD4_MsktÚ PPWM_PERIOD3_PERIOD5_PoslÚ PPWM_PERIOD3_PERIOD5_MsksÚ PPWM_PERIOD3_PERIOD6_PoskÚ PPWM_PERIOD3_PERIOD6_MskrÚ PPWM_PERIOD3_PERIOD7_PosjÚ PPWM_PERIOD3_PERIOD7_MskqÚ PPWM_PERIOD4_PERIOD0_PospÚ PPWM_PERIOD4_PERIOD0_MskwÚ PPWM_PERIOD4_PERIOD1_PosoÚ PPWM_PERIOD4_PERIOD1_MskvÚ PPWM_PERIOD4_PERIOD2_PosnÚ PPWM_PERIOD4_PERIOD2_MskuÚ PPWM_PERIOD4_PERIOD3_PosmÚ PPWM_PERIOD4_PERIOD3_MsktÚ PPWM_PERIOD4_PERIOD4_PoslÚ PPWM_PERIOD4_PERIOD4_MsksÚ PPWM_PERIOD4_PERIOD5_PoskÚ PPWM_PERIOD4_PERIOD5_MskrÚ PPWM_PERIOD4_PERIOD6_PosjÚ PPWM_PERIOD4_PERIOD6_MskqÚ PPWM_PERIOD4_PERIOD7_PosiÚ PPWM_PERIOD4_PERIOD7_MskpÚ PPWM_PERIOD5_PERIOD0_PosoÚ PPWM_PERIOD5_PERIOD0_MskvÚ PPWM_PERIOD5_PERIOD1_PosnÚ PPWM_PERIOD5_PERIOD1_MskuÚ PPWM_PERIOD5_PERIOD2_PosmÚ PPWM_PERIOD5_PERIOD2_MsktÚ PPWM_PERIOD5_PERIOD3_PoslÚ PPWM_PERIOD5_PERIOD3_MsksÚ PPWM_PERIOD5_PERIOD4_PoskÚ PPWM_PERIOD5_PERIOD4_MskrÚ PPWM_PERIOD5_PERIOD5_PosjÚ PPWM_PERIOD5_PERIOD5_MskqÚ PPWM_PERIOD5_PERIOD6_PosiÚ PPWM_PERIOD5_PERIOD6_MskpÚ PPWM_PERIOD5_PERIOD7_PoshÚ PPWM_PERIOD5_PERIOD7_MskoÚ PPWM_PERIOD6_PERIOD0_PosnÚ PPWM_PERIOD6_PERIOD0_MskuÚ PPWM_PERIOD6_PERIOD1_PosmÚ PPWM_PERIOD6_PERIOD1_MsktÚ PPWM_PERIOD6_PERIOD2_PoslÚ PPWM_PERIOD6_PERIOD2_MsksÚ PPWM_PERIOD6_PERIOD3_PoskÚ PPWM_PERIOD6_PERIOD3_MskrÚ PPWM_PERIOD6_PERIOD4_PosjÚ PPWM_PERIOD6_PERIOD4_MskqÚ PPWM_PERIOD6_PERIOD5_PosiÚ PPWM_PERIOD6_PERIOD5_MskpÚ PPWM_PERIOD6_PERIOD6_PoshÚ PPWM_PERIOD6_PERIOD6_MskoÚ PPWM_PERIOD6_PERIOD7_PosgÚ PPWM_PERIOD6_PERIOD7_MsknÚ PPWM_PERIOD7_PERIOD0_PosmÚ PPWM_PERIOD7_PERIOD0_MsktÚ PPWM_PERIOD7_PERIOD1_PoslÚ PPWM_PERIOD7_PERIOD1_MsksÚ PPWM_PERIOD7_PERIOD2_PoskÚ PPWM_PERIOD7_PERIOD2_MskrÚ PPWM_PERIOD7_PERIOD3_PosjÚ PPWM_PERIOD7_PERIOD3_MskqÚ PPWM_PERIOD7_PERIOD4_PosiÚ PPWM_PERIOD7_PERIOD4_MskpÚ PPWM_PERIOD7_PERIOD5_PoshÚ PPWM_PERIOD7_PERIOD5_MskoÚ PPWM_PERIOD7_PERIOD6_PosgÚ PPWM_PERIOD7_PERIOD6_MsknÚ PPWM_PERIOD7_PERIOD7_PosfÚ PPWM_PERIOD7_PERIOD7_MskmÚPPWM_CMPDAT0_CMP0_PosgÚPPWM_CMPDAT0_CMP0_MsknÚPPWM_CMPDAT0_CMP1_PosfÚPPWM_CMPDAT0_CMP1_MskmÚPPWM_CMPDAT0_CMP2_PoseÚPPWM_CMPDAT0_CMP2_MsklÚPPWM_CMPDAT0_CMP3_PosdÚPPWM_CMPDAT0_CMP3_MskkÚPPWM_CMPDAT0_CMP4_PoscÚPPWM_CMPDAT0_CMP4_MskjÚPPWM_CMPDAT0_CMP5_PosbÚPPWM_CMPDAT0_CMP5_MskiÚPPWM_CMPDAT0_CMP6_PosaÚPPWM_CMPDAT0_CMP6_MskhÚPPWM_CMPDAT0_CMP7_Pos`ÚPPWM_CMPDAT0_CMP7_MskgÚPPWM_CMPDAT0_CMPD0_Pos!ÚPPWM_CMPDAT0_CMPD0_Msk(ÚPPWM_CMPDAT0_CMPD1_Pos ÚPPWM_CMPDAT0_CMPD1_Msk'ÚPPWM_CMPDAT0_CMPD2_PosÚPPWM_CMPDAT0_CMPD2_Msk&ÚPPWM_CMPDAT0_CMPD3_PosÚPPWM_CMPDAT0_CMPD3_Msk%ÚPPWM_CMPDAT0_CMPD4_PosÚPPWM_CMPDAT0_CMPD4_Msk$ÚPPWM_CMPDAT0_CMPD5_PosÚPPWM_CMPDAT0_CMPD5_Msk#ÚPPWM_CMPDAT0_CMPD6_PosÚPPWM_CMPDAT0_CMPD6_Msk"ÚPPWM_CMPDAT0_CMPD7_PosÚPPWM_CMPDAT0_CMPD7_Msk!ÚPPWM_CMPDAT1_CMP0_PosfÚPPWM_CMPDAT1_CMP0_MskmÚPPWM_CMPDAT1_CMP1_PoseÚPPWM_CMPDAT1_CMP1_MsklÚPPWM_CMPDAT1_CMP2_PosdÚPPWM_CMPDAT1_CMP2_MskkÚPPWM_CMPDAT1_CMP3_PoscÚPPWM_CMPDAT1_CMP3_MskjÚPPWM_CMPDAT1_CMP4_PosbÚPPWM_CMPDAT1_CMP4_MskiÚPPWM_CMPDAT1_CMP5_PosaÚPPWM_CMPDAT1_CMP5_MskhÚPPWM_CMPDAT1_CMP6_Pos`ÚPPWM_CMPDAT1_CMP6_MskgÚPPWM_CMPDAT1_CMP7_Pos_ÚPPWM_CMPDAT1_CMP7_MskfÚPPWM_CMPDAT1_CMPD0_Pos ÚPPWM_CMPDAT1_CMPD0_Msk'ÚPPWM_CMPDAT1_CMPD1_PosÚPPWM_CMPDAT1_CMPD1_Msk&ÚPPWM_CMPDAT1_CMPD2_PosÚPPWM_CMPDAT1_CMPD2_Msk%ÚPPWM_CMPDAT1_CMPD3_PosÚPPWM_CMPDAT1_CMPD3_Msk$ÚPPWM_CMPDAT1_CMPD4_PosÚPPWM_CMPDAT1_CMPD4_Msk#ÚPPWM_CMPDAT1_CMPD5_PosÚPPWM_CMPDAT1_CMPD5_Msk"ÚPPWM_CMPDAT1_CMPD6_PosÚPPWM_CMPDAT1_CMPD6_Msk!ÚPPWM_CMPDAT1_CMPD7_PosÚPPWM_CMPDAT1_CMPD7_Msk ÚPPWM_CMPDAT2_CMP0_PoseÚPPWM_CMPDAT2_CMP0_MsklÚPPWM_CMPDAT2_CMP1_PosdÚPPWM_CMPDAT2_CMP1_MskkÚPPWM_CMPDAT2_CMP2_PoscÚPPWM_CMPDAT2_CMP2_MskjÚPPWM_CMPDAT2_CMP3_PosbÚPPWM_CMPDAT2_CMP3_MskiÚPPWM_CMPDAT2_CMP4_PosaÚPPWM_CMPDAT2_CMP4_MskhÚPPWM_CMPDAT2_CMP5_Pos`ÚPPWM_CMPDAT2_CMP5_MskgÚPPWM_CMPDAT2_CMP6_Pos_ÚPPWM_CMPDAT2_CMP6_MskfÚPPWM_CMPDAT2_CMP7_Pos^ÚPPWM_CMPDAT2_CMP7_MskeÚPPWM_CMPDAT2_CMPD0_PosÚPPWM_CMPDAT2_CMPD0_Msk&ÚPPWM_CMPDAT2_CMPD1_PosÚPPWM_CMPDAT2_CMPD1_Msk%ÚPPWM_CMPDAT2_CMPD2_PosÚPPWM_CMPDAT2_CMPD2_Msk$ÚPPWM_CMPDAT2_CMPD3_PosÚPPWM_CMPDAT2_CMPD3_Msk#ÚPPWM_CMPDAT2_CMPD4_PosÚPPWM_CMPDAT2_CMPD4_Msk"ÚPPWM_CMPDAT2_CMPD5_PosÚPPWM_CMPDAT2_CMPD5_Msk!ÚPPWM_CMPDAT2_CMPD6_PosÚPPWM_CMPDAT2_CMPD6_Msk ÚPPWM_CMPDAT2_CMPD7_PosÚPPWM_CMPDAT2_CMPD7_MskÚPPWM_CMPDAT3_CMP0_PosdÚPPWM_CMPDAT3_CMP0_MskkÚPPWM_CMPDAT3_CMP1_PoscÚPPWM_CMPDAT3_CMP1_MskjÚPPWM_CMPDAT3_CMP2_PosbÚPPWM_CMPDAT3_CMP2_MskiÚPPWM_CMPDAT3_CMP3_PosaÚPPWM_CMPDAT3_CMP3_MskhÚPPWM_CMPDAT3_CMP4_Pos`ÚPPWM_CMPDAT3_CMP4_MskgÚPPWM_CMPDAT3_CMP5_Pos_ÚPPWM_CMPDAT3_CMP5_MskfÚPPWM_CMPDAT3_CMP6_Pos^ÚPPWM_CMPDAT3_CMP6_MskeÚPPWM_CMPDAT3_CMP7_Pos]ÚPPWM_CMPDAT3_CMP7_MskdÚPPWM_CMPDAT3_CMPD0_PosÚPPWM_CMPDAT3_CMPD0_Msk%ÚPPWM_CMPDAT3_CMPD1_PosÚPPWM_CMPDAT3_CMPD1_Msk$ÚPPWM_CMPDAT3_CMPD2_PosÚPPWM_CMPDAT3_CMPD2_Msk#ÚPPWM_CMPDAT3_CMPD3_PosÚPPWM_CMPDAT3_CMPD3_Msk"ÚPPWM_CMPDAT3_CMPD4_PosÚPPWM_CMPDAT3_CMPD4_Msk!ÚPPWM_CMPDAT3_CMPD5_PosÚPPWM_CMPDAT3_CMPD5_Msk ÚPPWM_CMPDAT3_CMPD6_PosÚPPWM_CMPDAT3_CMPD6_MskÚPPWM_CMPDAT3_CMPD7_PosÚPPWM_CMPDAT3_CMPD7_MskÚPPWM_CMPDAT4_CMP0_PoscÚPPWM_CMPDAT4_CMP0_MskjÚPPWM_CMPDAT4_CMP1_PosbÚPPWM_CMPDAT4_CMP1_MskiÚPPWM_CMPDAT4_CMP2_PosaÚPPWM_CMPDAT4_CMP2_MskhÚPPWM_CMPDAT4_CMP3_Pos`ÚPPWM_CMPDAT4_CMP3_MskgÚPPWM_CMPDAT4_CMP4_Pos_ÚPPWM_CMPDAT4_CMP4_MskfÚPPWM_CMPDAT4_CMP5_Pos^ÚPPWM_CMPDAT4_CMP5_MskeÚPPWM_CMPDAT4_CMP6_Pos]ÚPPWM_CMPDAT4_CMP6_MskdÚPPWM_CMPDAT4_CMP7_Pos\ÚPPWM_CMPDAT4_CMP7_MskcÚPPWM_CMPDAT4_CMPD0_PosÚPPWM_CMPDAT4_CMPD0_Msk$ÚPPWM_CMPDAT4_CMPD1_PosÚPPWM_CMPDAT4_CMPD1_Msk#ÚPPWM_CMPDAT4_CMPD2_PosÚPPWM_CMPDAT4_CMPD2_Msk"ÚPPWM_CMPDAT4_CMPD3_PosÚPPWM_CMPDAT4_CMPD3_Msk!ÚPPWM_CMPDAT4_CMPD4_PosÚPPWM_CMPDAT4_CMPD4_Msk ÚPPWM_CMPDAT4_CMPD5_PosÚPPWM_CMPDAT4_CMPD5_MskÚPPWM_CMPDAT4_CMPD6_PosÚPPWM_CMPDAT4_CMPD6_MskÚPPWM_CMPDAT4_CMPD7_PosÚPPWM_CMPDAT4_CMPD7_MskÚPPWM_CMPDAT5_CMP0_PosbÚPPWM_CMPDAT5_CMP0_MskiÚPPWM_CMPDAT5_CMP1_PosaÚPPWM_CMPDAT5_CMP1_MskhÚPPWM_CMPDAT5_CMP2_Pos`ÚPPWM_CMPDAT5_CMP2_MskgÚPPWM_CMPDAT5_CMP3_Pos_ÚPPWM_CMPDAT5_CMP3_MskfÚPPWM_CMPDAT5_CMP4_Pos^ÚPPWM_CMPDAT5_CMP4_MskeÚPPWM_CMPDAT5_CMP5_Pos]ÚPPWM_CMPDAT5_CMP5_MskdÚPPWM_CMPDAT5_CMP6_Pos\ÚPPWM_CMPDAT5_CMP6_MskcÚPPWM_CMPDAT5_CMP7_Pos[ÚPPWM_CMPDAT5_CMP7_MskbÚPPWM_CMPDAT5_CMPD0_PosÚPPWM_CMPDAT5_CMPD0_Msk#ÚPPWM_CMPDAT5_CMPD1_PosÚPPWM_CMPDAT5_CMPD1_Msk"ÚPPWM_CMPDAT5_CMPD2_PosÚPPWM_CMPDAT5_CMPD2_Msk!ÚPPWM_CMPDAT5_CMPD3_PosÚPPWM_CMPDAT5_CMPD3_Msk ÚPPWM_CMPDAT5_CMPD4_PosÚPPWM_CMPDAT5_CMPD4_MskÚPPWM_CMPDAT5_CMPD5_PosÚPPWM_CMPDAT5_CMPD5_MskÚPPWM_CMPDAT5_CMPD6_PosÚPPWM_CMPDAT5_CMPD6_MskÚPPWM_CMPDAT5_CMPD7_PosÚPPWM_CMPDAT5_CMPD7_MskÚPPWM_CMPDAT6_CMP0_PosaÚPPWM_CMPDAT6_CMP0_MskhÚPPWM_CMPDAT6_CMP1_Pos`ÚPPWM_CMPDAT6_CMP1_MskgÚPPWM_CMPDAT6_CMP2_Pos_ÚPPWM_CMPDAT6_CMP2_MskfÚPPWM_CMPDAT6_CMP3_Pos^ÚPPWM_CMPDAT6_CMP3_MskeÚPPWM_CMPDAT6_CMP4_Pos]ÚPPWM_CMPDAT6_CMP4_MskdÚPPWM_CMPDAT6_CMP5_Pos\ÚPPWM_CMPDAT6_CMP5_MskcÚPPWM_CMPDAT6_CMP6_Pos[ÚPPWM_CMPDAT6_CMP6_MskbÚPPWM_CMPDAT6_CMP7_PosZÚPPWM_CMPDAT6_CMP7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<unnamed>QÚ 


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"X_RESVRÉÚ 


"X_CACHE_INIÀÚ CR_T±Ú8


<unnamed>QÚ 


"”CR0PÚ 


"”CR1OÚ  


"”DRÚ  


"”SRrÚ 


"”CPSRÛÚ 


"”IMSCçÚ 


"”RIS'Ú 


"”MIS,Ú 


"”ICR7Ú 


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<unnamed>QÚ 


"êRBR_THR_DLLAÚ 


"êIER_DLH Ú 


"êIIR_FCR™Ú 


"êLCRÞÚ 


"êMCRÝÚ 


"êLSRÎÚ 


"êMSRÍÚ 


"êSCR×Ú 


"êLPDLLCÚ 


"êLPDLHGÚ <"Tê


RESERVED0¡Ú 


"êUSRÅÚ 


"êTFLÙÚ 


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RESERVED1ØÚ 


"êHTXËÚ 


"êDMASAUÚ <"ê


RESERVED2ßÚ 


"êDLFéÚ 


"êRARÚÚ 


"êTARØÚ 


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RESERVED0êÚ 


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"êRAW_BLOCK_LNÚ 


"êRAW_BLOCK_HRÚ 


"êRAW_SRCTRAN_L˜Ú 


"êRAW_SRCTRAN_HœÚ 


"êRAW_DSTTRAN_L•Ú 


"êRAW_DSTTRAN_H™Ú 


"ê


RAW_ERR_LÔÚ 


"ê


RAW_ERR_HØÚ 


"ê STATUS_TFR_LÑÚ 


"ê STATUS_TFR_HÕÚ 


"êSTATUS_BLOCK_LNÚ 


"êSTATUS_BLOCK_HRÚ 


"êSTATUS_SRCTRAN_L˜Ú 


"êSTATUS_SRCTRAN_HœÚ 


"êSTATUS_DSTTRAN_L•Ú 


"êSTATUS_DSTTRAN_H™Ú 


"ê STATUS_ERR_LÔÚ 


"ê STATUS_ERR_HØÚ 


"ê


MSK_TFR_LÐÚ 


"ê


MSK_TFR_HÔÚ 


"êMSK_BLOCK_LMÚ 


"êMSK_BLOCK_HQÚ 


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"êMSK_SRCTRAN_H›Ú 


"êMSK_DSTTRAN_L”Ú 


"êMSK_DSTTRAN_H˜Ú 


"ê


MSK_ERR_LÓÚ 


"ê


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"êCLEAR_TFR_LPÚ 


"êCLEAR_TFR_HTÚ 


"êCLEAR_BLOCK_LÍÚ 


"êCLEAR_BLOCK_HÑÚ 


"êCLEAR_SRCTRAN_LÚ 


"êCLEAR_SRCTRAN_HÚ 


"êCLEAR_DSTTRAN_LÚ 


"êCLEAR_DSTTRAN_HÚ 


"êCLEAR_ERR_LSÚ 


"êCLEAR_ERR_HWÚ 


"ê STATUS_INT_LÒÚ 


"ê STATUS_INT_HÖÚ <"0ê


RESERVED3ÀÚ 


"êDMA_CFG_REG_LÀÚ 


"êDMA_CFG_REG_HÄÚ 


"êCH_EN_REG_LHÚ 


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"ûCONËÚ 


"ûTARÄÚ 


"ûSARÅÚ 


"û    HS_MADDR?Ú 


"ûDATACMDµÚ 


"ûSS_SCL_HCNT(Ú 


"ûSS_SCL_LCNT$Ú 


"ûFS_SCL_HCNT5Ú 


"ûFS_SCL_LCNT1Ú 


"ûHS_SCL_HCNT3Ú 


"ûHS_SCL_LCNT/Ú 


"û


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"ûRAW_INTR_STATvÚ 


"ûRX_TLþÚ 


"ûTX_TLüÚ 


"û    CLR_INTR$Ú 


"ûCLR_RX_UNDmÚ 


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"ûCLR_TX_OVR[Ú 


"ûCLR_RD_REQ€Ú 


"ûCLR_TX_ABRT'Ú 


"ûCLR_RX_DONE,Ú 


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"û


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"ûDMA_CRßÚ 


"û    DMA_TDLR:Ú 


"û    DMA_RDLR<Ú 


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"ûENABLE_STATUS­Ú 


"û


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I2C_TXFLRÚP


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<unnamed>QÚ 


"¸LP_REG_SYNCgÚ 


"¸LP_FL_CTRL_3VÏÚ 


"¸LP_SPACING_TIME0Ú 


"¸LP_SPACING_TIME1Ú 


"¸LP_SPACING_TIME2Ú 


"¸


LP_SLPTMRÚ 


"¸LP_INT_CTRLbÚ 


"¸LP_DLY_CTRL_3VvÚ 


"¸ LP_PTAT_POLYÚ 


"¸


LP_HP_LDOÚ 


"¸ LP_LP_LDO_3VÚ 


"¸LP_ANA_LDOÕÚ 


"¸LP_FSYN_LDOcÚ 


"¸LP_SWCÚ 


"¸LP_BUCK_3VÖÚ 


"¸ANA_ADC_LDO§Ú 


"¸ ANA_RFFE_LDOJÚ 


"¸ANA_VCO_LDO‡Ú 


"¸ANA_DFT×Ú 


"¸ANA_MISC_3V™Ú 


"¸ANA_RESERVED_3V]Ú 


"¸ ACT_32K_CTRL_Ú 


"¸ACT_32K_BASECORR;Ú 


"¸CPU_ADDR_REMAP_CTRLÚ 


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<unnamed>QÚ 


"Ó!EF_CTLüÚ 


"Ó!EF_ADDRÂÚ 


"Ó!EF_DATÚ 


"Ó!EF_RSV0²Ú 


"Ó!EF_VDDÚ 


"Ó!EF_RSV1±Ú 


"Ó!EF_CMDÚ 


"Ó!EF_TRGòÚ 


"Ó!EF_PROG_TIMING1=Ú 


"Ó!EF_PROG_TIMING2<Ú 


"Ó!EF_PROG_TIMING3;Ú 


"Ó!EF_READ_TIMING4VÚ 


"Ó!EF_READ_TIMING5UÚ <"0Ó!EF_RSV2RÚ 


"Ó!EF_OP_ERRORMÚ 


"Ó!EF_VERIFY_DEBUG1ÿÚ 


"Ó!EF_VERIFY_DEBUG2þÚ 


"Ó!EF_VERIFY_DEBUG3ýÚ 


"Ó!EF_VERIFY_DEBUG4üÚ 


"Ó!EF_FLASH_PERMISSIONïÚEFUSE_TÈÚPEFUSE_CTL_EFUSE_EN_Pos‹ÚPEFUSE_CTL_EFUSE_EN_Msk’ÚPEFUSE_CTL_THR_DVDD_Pos†ÚPEFUSE_CTL_THR_DVDD_MskÚ"PEFUSE_CTL_TAEN_RD_CTL_PosÚ"PEFUSE_CTL_TAEN_RD_CTL_Msk—Ú!PEFUSE_CTL_THR_RD_CTL_PosÌÚ!PEFUSE_CTL_THR_RD_CTL_MskÓÚPEFUSE_CTL_TRD_CTL_PosËÚPEFUSE_CTL_TRD_CTL_MskÒÚ!PEFUSE_CTL_TSR_RD_CTL_PosÁÚ!PEFUSE_CTL_TSR_RD_CTL_MskÈÚ#PEFUSE_CTL_TSR_DVDD_CTL_Pos1Ú#PEFUSE_CTL_TSR_DVDD_CTL_Msk8Ú!PEFUSE_CTL_THP_RD_CTL_PosÎÚ!PEFUSE_CTL_THP_RD_CTL_MskÕÚ&PEFUSE_CTL_THP_PG_AVDD_CTL_PosEÚ&PEFUSE_CTL_THP_PG_AVDD_CTL_MskLÚ#PEFUSE_CTL_TAEN_PGM_CTL_Pos@Ú#PEFUSE_CTL_TAEN_PGM_CTL_MskGÚ"PEFUSE_CTL_THP_PGM_CTL_Pos~Ú"PEFUSE_CTL_THP_PGM_CTL_Msk…ÚPEFUSE_CTL_TPGM_CTL_Pos{ÚPEFUSE_CTL_TPGM_CTL_Msk‚Ú"PEFUSE_CTL_TSP_PGM_CTL_PossÚ"PEFUSE_CTL_TSP_PGM_CTL_MskzÚ&PEFUSE_CTL_TSP_PG_AVDD_CTL_Pos:Ú&PEFUSE_CTL_TSP_PG_AVDD_CTL_MskAÚ!PEFUSE_CTL_TSP_RD_CTL_PosÃÚ%PEFUSE_CTL_TSP_TSP_RD_CTL_MsklÚ%PEFUSE_ADDR_EFUSEADDR_ADR_PosèÚ%PEFUSE_ADDR_EFUSEADDR_ADR_MskïÚ#PEFUSE_DAT_EFUSEDAT_DAT_PosnÚ#PEFUSE_DAT_EFUSEDAT_DAT_MskuÚ+P#EFUSE_DAT_EFUSEDAT_DAT_CONFIRM_PosñÚ+P#EFUSE_DAT_EFUSEDAT_DAT_CONFIRM_MskøÚPEFUSE_VDD_DVDD_REG_Pos›ÚPEFUSE_VDD_DVDD_REG_Msk¢ÚPEFUSE_VDD_AVDD_REG_PosžÚPEFUSE_VDD_AVDD_REG_Msk¥Ú#PEFUSE_CMD_EFUSECMD_CMD_Pos}Ú#PEFUSE_CMD_EFUSECMD_CMD_Msk„Ú"PEFUSE_TRG_EFUSETRG_GO_Pos‹Ú"PEFUSE_TRG_EFUSETRG_GO_Msk’Ú*P"EFUSE_PROG_TIMING1_TSP_RD_SET_PosûÚ*P"EFUSE_PROG_TIMING1_TSP_RD_SET_MskÚ/P'EFUSE_PROG_TIMING1_TSP_PG_AVDD_SET_PosrÚ/P'EFUSE_PROG_TIMING1_TSP_PG_AVDD_SET_MskyÚ+P#EFUSE_PROG_TIMING1_TSP_PGM_SET_Pos«Ú+P#EFUSE_PROG_TIMING1_TSP_PGM_SET_Msk²Ú(P EFUSE_PROG_TIMING2_TPGM_SET_Pos²Ú(P EFUSE_PROG_TIMING2_TPGM_SET_Msk¹Ú+P#EFUSE_PROG_TIMING2_THP_PGM_SET_PosµÚ+P#EFUSE_PROG_TIMING2_THP_PGM_SET_Msk¼Ú,P$EFUSE_PROG_TIMING2_TAEN_PGM_SET_PoswÚ,P$EFUSE_PROG_TIMING2_TAEN_PGM_SET_Msk~Ú/P'EFUSE_PROG_TIMING3_THP_PG_AVDD_SET_Pos{Ú/P'EFUSE_PROG_TIMING3_THP_PG_AVDD_SET_Msk‚Ú*P"EFUSE_PROG_TIMING3_THP_RD_SET_PosÚ*P"EFUSE_PROG_TIMING3_THP_RD_SET_MskÚ,P$EFUSE_READ_TIMING4_TSR_DVDD_SET_Pos‚Ú,P$EFUSE_READ_TIMING4_TSR_DVDD_SET_Msk‰Ú*P"EFUSE_READ_TIMING4_TSR_RD_SET_PosÚ*P"EFUSE_READ_TIMING4_TSR_RD_SET_MskÚ'PEFUSE_READ_TIMING4_TRD_SET_PosÚ'PEFUSE_READ_TIMING4_TRD_SET_Msk#Ú*P"EFUSE_READ_TIMING5_THR_RD_SET_PosÚ*P"EFUSE_READ_TIMING5_THR_RD_SET_Msk#Ú+P#EFUSE_READ_TIMING5_TAEN_RD_SET_PosàÚ+P#EFUSE_READ_TIMING5_TAEN_RD_SET_MskçÚ,P$EFUSE_READ_TIMING5_THR_DVDD_SET_PosŒÚ,P$EFUSE_READ_TIMING5_THR_DVDD_SET_Msk“Ú$PEFUSE_OP_ERROR_OP_ERROR_Pos¾Ú$PEFUSE_OP_ERROR_OP_ERROR_MskÅÚ0P(EFUSE_VERIFY_DEBUG1_VERIFY_DBG_KEY1_PospÚ0P(EFUSE_VERIFY_DEBUG1_VERIFY_DBG_KEY1_MskwÚ0P(EFUSE_VERIFY_DEBUG2_VERIFY_DBG_KEY2_PosnÚ0P(EFUSE_VERIFY_DEBUG2_VERIFY_DBG_KEY2_MskuÚ0P(EFUSE_VERIFY_DEBUG3_VERIFY_DBG_KEY3_PoslÚ0P(EFUSE_VERIFY_DEBUG3_VERIFY_DBG_KEY3_MsksÚ0P(EFUSE_VERIFY_DEBUG4_VERIFY_DBG_KEY4_PosjÚ0P(EFUSE_VERIFY_DEBUG4_VERIFY_DBG_KEY4_MskqÚ(P EFUSE_FLASH_PERMISSION_CTRL_Pos»Ú(P EFUSE_FLASH_PERMISSION_CTRL_MskÂÚ8


<unnamed>QÚ "½"FADDR†Ú "½"POWERZÚ "½"INT_IN1ÑÚ "½"INT_IN2ÐÚ "½"    INT_OUT1nÚ "½"    INT_OUT2mÚ "½"INT_USB¯Ú "½"    INT_IN1EŠÚ "½"    INT_IN2E‰Ú "½"


INT_OUT1E'Ú "½"


INT_OUT2E&Ú "½"    INT_USBEhÚ "½"FRAME1IÚ "½"FRAME2HÚ "½"INDEXoÚ "½"REVþÚ "½"MAX_PKT_IN³Ú "½"CSR0_INCSR1´Ú "½"IN_CSR2ÓÚ "½"MAX_PKT_OUTPÚ "½"    OUT_CSR1qÚ "½"    OUT_CSR2pÚ "½"OUT_COUNT1ÌÚ "½"OUT_COUNT2ËÚ <"½"REV0Ú "½"    FIFO_EP0™Ú <"½"REV1“Ú "½"    FIFO_EP1˜Ú <"½"REV2’Ú "½"    FIFO_EP2—Ú <"½"REV3‘Ú "½"    FIFO_EP3–ÚUSB_TZÚ8


<unnamed>QÚ 


"ß"    DMA_INTRJÚ 


"ß"CNTL1\Ú 


"ß"ADDR1rÚ 


"ß"COUNT1Ú    USBDMA_T‚ÚPUSB_DMA_REQUEST_PosqÚPUSB_DMA_REQUEST_MskxÚPUSB_DMA_DIRECTION_PosõÚPUSB_DMA_DIRECTION_MsküÚPUSB_DMA_MODE_SEL_Pos0ÚPUSB_DMA_MODE_SEL_Msk7ÚPUSB_DMA_EP_NUM_Pos¸ÚPUSB_DMA_EP_NUM_Msk¿Ú8


<unnamed>QÚ 


"í"revs0ÀÚ 


"í"FSM5—Ú 


"í"FSM6–Ú 


"í"FSM13fÚ 


"í"FSM14eÚ 


"í"FSM15dÚ 


"í"FSM16cÚ 


"í"FSM17bÚ 


"í"FSM18aÚ 


"í"FSM19`Ú 


"í"PHY1Ú 


"í"PHY2Ú 


"í"PHY3ŽÚ 


"í"PHY4Ú 


"í"PHY5ŒÚ <"í"revs1‰Ú 


"í"INTR1BÚ 


"í"INTCLRâÚ 


"í"INTMSKØÚ 


"í"INTR4?Ú 


"í"revs2¾Ú 


"í"ACTTMR1°Ú 


"í"ACTTMR2¯Ú 


"í"ACTTMR6«Ú 


"í"ACTTMR7ªÚ 


"í"revs3½Ú 


"í"SECURE1´Ú 


"í"SECURE2³Ú 


"í"SECURE3²Ú 


"í"SECURE4±Ú 


"í"SECURE5°Ú 


"í"SECURE6¯Ú 


"í"SECURE7®Ú 


"í"SECURE8­Ú 


"í"SECURE9¬Ú 


"í"    SECURE10‚Ú 


"í"revs4¼Ú 


"í"TEST_MUX00­Ú 


"í"RNG1šÚ 


"í"RNG2™Ú 


"í"revs5»Ú 


"í"LL_MAC_CTRLHÚ 


"í"TEST_MUX01¬Ú 


"í"TEST_MUX02«Ú 


"í"TEST_MUX03ªÚ <"í"revs6„Ú 


"í"R00_CTL¸Ú 


"í"R01_INT¯Ú 


"í"R02_TMR_CTL\Ú 


"í"R03_RX_ADDR_L½Ú 


"í"R04_RX_CTL¥Ú 


"í"R05_TX_ADDR_L¹Ú 


"í"R06_TX_CTL¡Ú 


"í" R07_SRAM_CTLÚ 


"í"R08_RX_ADDR1_L…Ú 


"í"R09_RX_ADDR2_LƒÚ 


"í"R0A_RX_ADDR3_LzÚ 


"í"R0B_RX_ADDR4_LxÚ 


"í"R0C_RX_ADDR5_LvÚ 


"í"R0D_RX_ADDR6_LtÚ 


"í"R0E_RX_ADDR7_LrÚ 


"í"R0F_RX_ADDR_H®Ú 


"í"R10_RX_ADDR_ENvÚ 


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CLEAR_BITÚP    READ_BITaÚP


CLEAR_REGÚP


WRITE_REGñÚP    READ_REGbÚPMODIFY_REG²ÚPUSE_FULL_ASSERTûÚP assert_param±ÚP    FREQ_RCLMÚP    FREQ_XTL6ÚNVIC_SystemReset½ÚP__ZEPHYR__WÚP__PAN_SYS_LOG_H__ÚPDBG_ONöÚPINFO_ON•ÚPWARN_ON‰ÚPERR_ONÚÚPTEST_ONÚP


ASSERT_ONëÚP


SYS_ABORTãÚPLOGãÚPSYS_DBG’ÚP    SYS_INFO1ÚP    SYS_WARN%ÚP    SYS_TESTÚPSYS_ERRvÚPSYS_ASSERT‡Ú ,file)Ú ,


line/Ú ,expr


ÚSYS_AssertErrorðÚP__PAN_SYS_H__QÚPSYS_MFP_TYPE_Msk?ÚPSYS_MFP_ALT_Msk¢ÚPSYS_MFP_MFP_Msk ÚP SYS_MFP_GPIOäÚPSYS_MFP_P00_GPIOÍÚPSYS_MFP_P00_SWD_CLKÏÚPSYS_MFP_P00_UART1_RX~ÚPSYS_MFP_P00_I2C0_SCLÅÚPSYS_MFP_P00_SPI0_CLKŸÚPSYS_MFP_P00_LL_DBG_14jÚPSYS_MFP_P00_MDM_DBG_11%ÚPSYS_MFP_P00_RESERVED”ÚPSYS_MFP_P00_MskÓÚPSYS_MFP_P01_GPIOÌÚPSYS_MFP_P01_SWD_DATÏÚPSYS_MFP_P01_UART1_TX{ÚPSYS_MFP_P01_I2C0_SDAÎÚPSYS_MFP_P01_SPI0_CSäÚPSYS_MFP_P01_LL_DBG_15hÚPSYS_MFP_P01_MDM_DBG_12#ÚPSYS_MFP_P01_RESERVED“ÚPSYS_MFP_P01_MskÒÚPSYS_MFP_P02_GPIOËÚPSYS_MFP_P02_UART0_CTS;ÚPSYS_MFP_P02_SPI1_MISO<ÚPSYS_MFP_P02_PWM_CH3ãÚPSYS_MFP_P02_UART1_CTS:ÚPSYS_MFP_P02_LL_DBG_8—ÚPSYS_MFP_P02_MDM_DBG_19ÚPSYS_MFP_P02_RESERVED’ÚPSYS_MFP_P02_MskÑÚPSYS_MFP_P03_GPIOÊÚPSYS_MFP_P03_UART0_CTS:ÚPSYS_MFP_P03_SPI0_CSâÚPSYS_MFP_P03_PWM_CH2ãÚ#PSYS_MFP_P03_TIMER0_CNT_OUT™ÚPSYS_MFP_P03_LL_DBG_8–ÚPSYS_MFP_P03_MDM_DBG_5QÚPSYS_MFP_P03_RESERVED‘ÚPSYS_MFP_P03_MskÐÚPSYS_MFP_P04_GPIOÉÚPSYS_MFP_P04_UART0_RTS*ÚPSYS_MFP_P04_SPI0_CLK›ÚPSYS_MFP_P04_PWM_CH3áÚPSYS_MFP_P04_TIMER0_EXTëÚPSYS_MFP_P04_LL_DBG_9”ÚPSYS_MFP_P04_MDM_DBG_6OÚPSYS_MFP_P04_RESERVEDÚPSYS_MFP_P04_MskÏÚPSYS_MFP_P05_GPIOÈÚPSYS_MFP_P05_UART0_TXxÚPSYS_MFP_P05_SPI0_MISO:ÚPSYS_MFP_P05_PWM_CH4ßÚPSYS_MFP_P05_EXT_STADC.ÚPSYS_MFP_P05_LL_DBG_12gÚPSYS_MFP_P05_MDM_DBG_9KÚPSYS_MFP_P05_RESERVEDÚPSYS_MFP_P05_MskÎÚPSYS_MFP_P06_GPIOÇÚPSYS_MFP_P06_UART0_RXyÚPSYS_MFP_P06_SPI0_MISO9ÚPSYS_MFP_P06_PWM_CH5ÝÚPSYS_MFP_P06_TIMER1_EXTèÚPSYS_MFP_P06_LL_DBG_13eÚPSYS_MFP_P06_MDM_DBG_3PÚPSYS_MFP_P06_AHB_CLKìÚPSYS_MFP_P06_MskÍÚPSYS_MFP_P07_GPIOÆÚPSYS_MFP_P07_UART1_RXwÚPSYS_MFP_P07_I2C0_SCL¾ÚPSYS_MFP_P07_SPI0_MOSI8ÚPSYS_MFP_P07_PWM_CH0áÚPSYS_MFP_P07_LL_DBG_10gÚPSYS_MFP_P07_MDM_DBG_7KÚPSYS_MFP_P07_RESERVEDÚPSYS_MFP_P07_MskÌÚPSYS_MFP_P10_GPIOÌÚPSYS_MFP_P10_UART1_TX{ÚPSYS_MFP_P10_I2C0_SDAÎÚPSYS_MFP_P10_SPI0_MISO>ÚPSYS_MFP_P10_PWM_CH5âÚPSYS_MFP_P10_LL_DBG_11lÚPSYS_MFP_P10_MDM_DBG_8PÚPSYS_MFP_P10_RESERVED“ÚPSYS_MFP_P10_MskÒÚPSYS_MFP_P11_GPIOËÚPSYS_MFP_P11_UART1_RTS+ÚPSYS_MFP_P11_SPI0_MOSI=ÚPSYS_MFP_P11_PWM_CH7ßÚPSYS_MFP_P11_CLK_32KÚPSYS_MFP_P11_LL_DBG_9–ÚPSYS_MFP_P11_MDM_DBG_0WÚPSYS_MFP_P11_UART0_TX{ÚPSYS_MFP_P11_MskÑÚPSYS_MFP_P12_GPIOÊÚPSYS_MFP_P12_UART0_RX|ÚPSYS_MFP_P12_PWM_CH4áÚ#PSYS_MFP_P12_TIMER0_CNT_OUT™ÚPSYS_MFP_P12_UART1_TXyÚPSYS_MFP_P12_LL_DBG_4šÚPSYS_MFP_P12_MDM_DBG_17ÚPSYS_MFP_P12_SPI0_MISO<ÚPSYS_MFP_P12_MskÐÚPSYS_MFP_P13_GPIOÉÚPSYS_MFP_P13_UART0_RTS*ÚPSYS_MFP_P13_I2C0_SDAËÚPSYS_MFP_P13_PWM_CH3áÚPSYS_MFP_P13_LL_DBG_3šÚPSYS_MFP_P13_MDM_DBG_16ÚPSYS_MFP_P13_SPI1_CSàÚPSYS_MFP_P13_SPI0_CSáÚPSYS_MFP_P13_MskÏÚPSYS_MFP_P14_GPIOÈÚPSYS_MFP_P14_UART0_CTS8ÚPSYS_MFP_P14_I2C0_SCLÀÚPSYS_MFP_P14_PWM_CH2áÚPSYS_MFP_P14_LL_DEBUG_2üÚPSYS_MFP_P14_MDM_DBG_15ÚPSYS_MFP_P14_SPI0_CLKšÚPSYS_MFP_P14_RESERVEDÚPSYS_MFP_P14_MskÎÚPSYS_MFP_P15_GPIOÇÚPSYS_MFP_P15_SPI0_CSßÚPSYS_MFP_P15_PWM_CH5ÝÚPSYS_MFP_P15_TIMER0_EXTéÚPSYS_MFP_P15_UART0_RXyÚPSYS_MFP_P15_LL_DBG_5–ÚPSYS_MFP_P15_MDM_DBG_18ÚPSYS_MFP_P15_RESERVEDŽÚPSYS_MFP_P15_MskÍÚPSYS_MFP_P16_GPIOÆÚPSYS_MFP_P16_UART0_TXvÚ#PSYS_MFP_P16_TIMER2_CNT_OUT“ÚPSYS_MFP_P16_PWM_CH0áÚPSYS_MFP_P16_LL_DBG_0šÚPSYS_MFP_P16_MDM_DBG_13ÚPSYS_MFP_P16_SPI1_CLK—ÚPSYS_MFP_P16_I2C0_SCL¾ÚPSYS_MFP_P16_MskÌÚPSYS_MFP_P17_GPIOÅÚPSYS_MFP_P17_UART0_RXwÚPSYS_MFP_P17_TIMER2_EXTåÚPSYS_MFP_P17_PWM_CH1ßÚPSYS_MFP_P17_LL_DBG_1˜ÚPSYS_MFP_P17_MDM_DBG_14ÚPSYS_MFP_P17_RCHÚPSYS_MFP_P17_RESERVEDŒÚPSYS_MFP_P17_MskËÚPSYS_MFP_P20_GPIOËÚPSYS_MFP_P20_SPI1_MISO<ÚPSYS_MFP_P20_PWM_CH6àÚPSYS_MFP_P20_TADC_CLKÚPSYS_MFP_P20_LL_DBG_6™ÚPSYS_MFP_P20_MDM_DBG_2UÚPSYS_MFP_P20_XTL_C1_CLKêÚPSYS_MFP_P20_RESERVED’ÚPSYS_MFP_P20_MskÑÚPSYS_MFP_P21_GPIOÊÚPSYS_MFP_P21_SPI1_MOSI;ÚPSYS_MFP_P21_PWM_CH7ÞÚPSYS_MFP_P21_TADC_VLDÚPSYS_MFP_P21_LL_DBG_7—ÚPSYS_MFP_P21_MDM_DBG_1UÚPSYS_MFP_P21_XTL_C2_CLKèÚPSYS_MFP_P21_RESERVED‘ÚPSYS_MFP_P21_MskÐÚPSYS_MFP_P22_GPIOÉÚPSYS_MFP_P22_SPI1_CLKšÚPSYS_MFP_P22_PWM_CH0äÚPSYS_MFP_P22_RESERVEDÚPSYS_MFP_P22_TADC_DATl.ÚPSYS_MFP_P22_MDM_DBG_0UÚPSYS_MFP_P22_SPI0_MOSI;ÚPSYS_MFP_P22_RESERVED1]ÚPSYS_MFP_P22_MskÏÚPSYS_MFP_P23_GPIOÈÚPSYS_MFP_P23_SPI1_CSßÚPSYS_MFP_P23_PWM_CH1âÚPSYS_MFP_P23_DPLL_DIV8GÚPSYS_MFP_P23_TADC_DATHQÚPSYS_MFP_P23_MDM_DBG_10!ÚPSYS_MFP_P23_I2C0_SCLÀÚPSYS_MFP_P23_RESERVEDÚPSYS_MFP_P23_MskÎÚPSYS_MFP_P24_GPIOÇÚPSYS_MFP_P24_SPI1_MISO8ÚPSYS_MFP_P24_UART1_RXxÚPSYS_MFP_P24_PWM_CH2àÚ#PSYS_MFP_P24_TIMER1_CNT_OUT•ÚPSYS_MFP_P24_MDM_DBG_4OÚPSYS_MFP_P24_RESERVEDŽÚPSYS_MFP_P24_RESERVED1[ÚPSYS_MFP_P24_MskÍÚPSYS_MFP_P25_GPIOÆÚPSYS_MFP_P25_SPI1_MOSI7ÚPSYS_MFP_P25_UART1_TXuÚPSYS_MFP_P25_PWM_CH3ÞÚPSYS_MFP_P25_MDM_DBG_5MÚPSYS_MFP_P25_RESERVEDÚPSYS_MFP_P25_I2C0_SDAÈÚPSYS_MFP_P25_RESERVED1ZÚPSYS_MFP_P25_MskÌÚPSYS_MFP_P26_GPIOÅÚPSYS_MFP_P26_UART1_RTS%ÚPSYS_MFP_P26_PWM_CH4ÜÚPSYS_MFP_P26_SPI1_CSÜÚPSYS_MFP_P26_MDM_DBG_4MÚPSYS_MFP_P26_MDM_DBG_10ÚPSYS_MFP_P26_RESERVEDŒÚPSYS_MFP_P26_RESERVED1YÚPSYS_MFP_P26_MskËÚPSYS_MFP_P27_GPIOÄÚPSYS_MFP_P27_UART1_CTS3ÚPSYS_MFP_P27_PWM_CH5ÚÚPSYS_MFP_P27_SPI1_CLK•ÚPSYS_MFP_P27_RESERVED‹ÚPSYS_MFP_P27_MDM_DBG_20ÚPSYS_MFP_P27_XTHÚPSYS_MFP_P27_RESERVED1XÚPSYS_MFP_P27_MskÊÚPSYS_MFP_P30_GPIOÊÚPSYS_MFP_P30_UART1_RX{ÚPSYS_MFP_P30_PWM_CH6ßÚPSYS_MFP_P30_SPI1_MISO;ÚPSYS_MFP_P30_MDM_DBG_10#ÚPSYS_MFP_P30_RESERVED‘ÚPSYS_MFP_P30_RESERVED1^ÚPSYS_MFP_P30_RESERVED2]ÚPSYS_MFP_P30_MskÐÚPSYS_MFP_P31_GPIOÉÚPSYS_MFP_P31_UART1_TXxÚPSYS_MFP_P31_PWM_CH7ÝÚPSYS_MFP_P31_SPI1_MOSI:ÚPSYS_MFP_P31_RESERVEDÚPSYS_MFP_P31_RESERVED1]ÚPSYS_MFP_P31_RESERVED2\ÚPSYS_MFP_P31_RESERVED3[ÚPSYS_MFP_P31_MskÏÚPSYS_SET_MFP)ÚSYS_UnlockRegòÚSYS_LockRegÙÚSYS_IsRegLocked@Ú,


 


u32NopCnt¡ÚSYS_delay_10nopPÚP__PAN_CLK_H__vÚ$PCLK_APB1_WDTSEL_MILLI_PULSEhÚPCLK_APB1_WDTSEL_RCL32K@Ú%PCLK_APB1_WWDTSEL_MILLI_PULSEÚ PCLK_APB1_WWDTSEL_RCL32KçÚ!PCLK_APB1_TMR0SEL_APB1CLK»Ú PCLK_APB1_TMR0SEL_RCL32K


ÚPCLK_APB1_TMR0SEL_TM0ÐÚ!PCLK_APB2_TMR1SEL_APB2CLK¸Ú PCLK_APB2_TMR1SEL_RCL32KÚPCLK_APB2_TMR1SEL_TM1ÍÚ!PCLK_APB2_TMR2SEL_APB2CLK·Ú PCLK_APB2_TMR2SEL_RCL32KÚPCLK_APB2_TMR2SEL_TM2ËÚ"PCLK_APB1_PWM_CH01_SEL_APBIÚ%PCLK_APB1_PWM_CH01_SEL_CLK32KŒÚ"PCLK_APB1_PWM_CH23_SEL_APBEÚ%PCLK_APB1_PWM_CH23_SEL_CLK32KˆÚ"PCLK_APB1_PWM_CH45_SEL_APBAÚ%PCLK_APB1_PWM_CH45_SEL_CLK32K„Ú"PCLK_APB1_PWM_CH67_SEL_APB=Ú%PCLK_APB1_PWM_CH67_SEL_CLK32K€ÚP


FREQ_1MHZÚP


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EFUSE_RSTéÚPUSB_RST{ÚPMDMSTB_RST˜ÚPMDM_RST‡ÚP    I2C0_RSTuÚP    SPI0_RSTGÚP    SPI1_RSTFÚP


UART0_RSTõÚP


UART1_RSTôÚP    PWM0_RST?ÚPADC_RSTÚPWDT_RSTvÚP    WWDT_RSTÚP    TMR0_RST@ÚP    TMR1_RST?ÚP    TMR2_RST>ÚP    GPIO_RST4ÚPCLKTRIM_RSTGÚPCLK_BODCTL_BOD_INT_EN@ÚPCLK_BODCTL_BOD_RST_EN2Ú PCLK_BODCTL_BODSEL_1_75VãÚ PCLK_BODCTL_BODSEL_1_95VáÚ PCLK_BODCTL_BODSEL_2_15VèÚ PCLK_BODCTL_BODSEL_2_35VæÚ PCLK_BODCTL_BODSEL_2_55VäÚ PCLK_BODCTL_BODSEL_2_75VâÚ PCLK_BODCTL_BODSEL_2_95VàÚ#PCLK_BLDBCTL_BODDBSEL_2POW0Ú#PCLK_BLDBCTL_BODDBSEL_2POW1Ú#PCLK_BLDBCTL_BODDBSEL_2POW2Ú#PCLK_BLDBCTL_BODDBSEL_2POW3Ú#PCLK_BLDBCTL_BODDBSEL_2POW4Ú#PCLK_BLDBCTL_BODDBSEL_2POW5 Ú#PCLK_BLDBCTL_LVRDBSEL_2POW0óÚ#PCLK_BLDBCTL_LVRDBSEL_2POW1òÚ#PCLK_BLDBCTL_LVRDBSEL_2POW2ñÚ#PCLK_BLDBCTL_LVRDBSEL_2POW3ðÚ#PCLK_BLDBCTL_LVRDBSEL_2POW4ïÚ#PCLK_BLDBCTL_LVRDBSEL_2POW5îÚCLK_XthStartupConfigÚCLK_HCLKConfig'Ú,


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u32clkseluÚCLK_SetTmrClkSrcîÚ,


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u32clkseluÚCLK_SetPwmClkSrcíÚ,Peripheral±ÚCLK_GetPeripheralFreqËÚCLK_ResetChipÚ!CLK_ResetSystemToRomModeÚ,


u32ModuleIndex‹ÚCLK_ResetModule(Ú,i32Mode€Ú,


u32BODLevel"ÚCLK_ConfigureBODÚCLK_EnableBODyÚCLK_DisableBOD


ÚCLK_GetBODStatusÚCLK_GetBODIntFlagóÚCLK_ClearBODIntFlag(Ú,


 u32BodDBTimeÃÚCLK_SetBODDebounceTimeÎÚCLK_EnableLVRZÚCLK_DisableLVRëÚ,


 u32LvrDBTime¤ÚCLK_SetLVRDebounceTime¯ÚP__PAN_ADC_H__ˆÚPADC_INPUTRANGE_HIGHÚPADC_INPUTRANGE_LOW2ÚPADC_CH8_EXT{ÚPADC_CH8_BGP“ÚPADC_CMP0_LESS_THANPÚPADC_CMP1_LESS_THANOÚ%PADC_CMP0_GREATER_OR_EQUAL_TOÚ%PADC_CMP1_GREATER_OR_EQUAL_TOÚPADC_TRIGGER_BY_EXT_PINÔÚPADC_TRIGGER_BY_PWMÚ!PADC_FALLING_EDGE_TRIGGERÚ PADC_RISING_EDGE_TRIGGERÃÚP ADC_ADIF_INT.ÚP ADC_CMP0_INT2ÚP ADC_CMP1_INT1ÚPADC_FIFO_FULL_INT‚ÚPADC_FIFO_EMPTY_INT$ÚPADC_FIFO_OVER_INTyÚPADC_FIFO_HALF_INTšÚPADC_SAMPLE_CLOCK_0dÚPADC_SAMPLE_CLOCK_1cÚPADC_SAMPLE_CLOCK_2bÚPADC_SAMPLE_CLOCK_4`ÚPADC_SAMPLE_CLOCK_8\ÚPADC_SAMPLE_CLOCK_16+ÚPADC_SAMPLE_CLOCK_32-ÚPADC_SAMPLE_CLOCK_64(ÚPADC_SAMPLE_CLOCK_128õÚPADC_SAMPLE_CLOCK_256óÚPADC_SAMPLE_CLOCK_512øÚPADC_SAMPLE_CLOCK_1024ÇÚ!PADC_SEQMODE_TYPE_23SHUNToÚ PADC_SEQMODE_TYPE_1SHUNT¥Ú$PADC_SEQMODE_MODESELECT_CH01ÑÚ$PADC_SEQMODE_MODESELECT_CH12ÏÚ$PADC_SEQMODE_MODESELECT_CH02ÐÚ#PADC_SEQMODE_MODESELECT_ONEÝÚ PADC_SEQMODE_PWM0_RISINGºÚ PADC_SEQMODE_PWM0_CENTERÅÚ!PADC_SEQMODE_PWM0_FALLING‡Ú PADC_SEQMODE_PWM0_PERIODÃÚ PADC_SEQMODE_PWM2_RISING¸Ú PADC_SEQMODE_PWM2_CENTERÃÚ!PADC_SEQMODE_PWM2_FALLING…Ú PADC_SEQMODE_PWM2_PERIODÁÚ PADC_SEQMODE_PWM4_RISING¶Ú PADC_SEQMODE_PWM4_CENTERÁÚ!PADC_SEQMODE_PWM4_FALLINGƒÚ PADC_SEQMODE_PWM4_PERIOD¿Ú PADC_SEQMODE_PWM6_RISING´Ú PADC_SEQMODE_PWM6_CENTER¿Ú!PADC_SEQMODE_PWM6_FALLINGÚ PADC_SEQMODE_PWM6_PERIOD½ÚPADC_COMPARATOR_0ýÚPADC_COMPARATOR_1üÚ!PADC_FIFO_TRIG_LEVEL_HALFjÚ!PADC_FIFO_TRIG_LEVEL_FULLRÚ8


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chip_info Ú "×+ft_version{Ú "×+


adc_vdd_b8Ú "×+


adc_vdd_k$Ú "×+


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rsvd_0x30“Ú <"×+adc_vbg_kbwÚ "×+adc_vbat_k³Ú "×+adc_vbat_b¾Ú "×+adc_vbat_dtemp_k0Ú "×+adc_vbat_dtemp_b9Ú "×+adc_temp_k¢Ú 


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adc_ctrl2GÚ 


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ADC_OPT_T"Ú@


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global_calc_vbat_mv$Ú,optxÚ ADC_SetCalirationParamsýÚADC_GetConversionDataãÚ,"ï+ADCxMÚADC_StatusFlag³Ú,"ñ+ADCxKÚ,


"ñ+IntMaskÜÚADC_ClearStatusFlagÂÚ,"ô+ADCxHÚ,


"ô+IntMaskÙÚADC_IntMaskÚ,"÷+ADCxEÚ,


"÷+IntMaskÖÚ,""÷+    NewStateKÚADC_IsIntOccuredÚ,"û+ADCxAÚ,


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"þ+IntMaskÏÚADC_IsBusyZÚ,",ADCxºÚADC_IsDataOverrun„Ú,"ƒ,ADCx¸ÚADC_IsDataValid‰Ú,"…,ADCx¶ÚADC_PowerDownÚ,"‡,ADCx´ÚADC_PowerOníÚ,"‰,ADCx²Ú"ADC_SequentialModeDisableGÚ,"‹,ADCx°ÚADC_Trigger2SelectCÚ,",ADCx®Ú,"",    NewState´ÚADC_DisableCompare0üÚ,",ADCx«ÚADC_DisableCompare1ûÚ,"’,ADCx©ÚADC_StartConvert¾Ú,"”,ADCx§ÚADC_StopConvert(Ú,"–,ADCx¥ÚADC_TestModeEnable=Ú,"˜,ADCx£ÚADC_TestModeDisableÎÚ,"š,ADCx¡ÚADC_DmaModeEnableÍÚ,"œ,ADCxŸÚ,""œ,    NewState¥ÚADC_SetClockDividerÈÚ,"Ÿ,ADCxœÚ,


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Ú ,ADCx‰Ú&ADC_MeasureSocTemperatureFasttÚ ,ADCx‰ÚADC_MeasureSocVbatÚ ,ADCx‰ÚADC_Disable÷Ú


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MaskKÚADC_DisableIntÆÚ ,ADCx‰Ú,


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ModeSel(ÚADC_SeqModeEnableªÚ ,ADCx‰Ú,


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 CmpConditionÚ,


CmpData7Ú,


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CmpSelectMÚADC_CompareEnable‘Ú ,ADCx‰Ú ,


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CMD_DREAD&ÚP


CMD_2READ8ÚP


CMD_QREADÚP


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PAGE_SIZEÚPSECTOR_SIZEKÚ8_flash_ids¥Ú "ž-manufacturer_id®Ú8


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<unnamed>QÚ "¢-memory_type_idÿÚ "¢-memory_density_id»Ú <"ž-uidxÚFLASH_IDS_T‹Ú


flash_idsÚ#FMC_EnterDeepPowerDownModeåÚ,"¨-fmcžÚ"FMC_ExitDeepPowerDownModeKÚ,"ª-fmcœÚFMC_IsBusyWorking]Ú,"¬-fmcšÚ,fmc•ÚFMC_GetFlashUniqueIdYÚ,fmc•ÚFMC_GetFlashJedecId÷Ú,fmc•ÚFMC_SetFlashCapacityCÚ,fmc•Ú!FMC_GetFlashCodeAreaSizeæÚ,fmc•Ú,adršÚFMC_EraseSector5Ú,fmc•Ú ,addr4ÚFMC_EraseBlock32kæÚ,fmc•Ú ,addr4ÚFMC_EraseBlock64káÚ,fmc•Ú ,


addr<Ú,


lenšÚFMC_EraseCodeArea­Ú,fmc•Ú ,


mode2ÚInitIcacheÚ,fmc•Ú ,


addr<Ú,


count¬Ú,chksum:ÚFMC_GetCrc32SumÃÚ,fmc•Ú,adršÚ,szæÚBlankCheckÚ,fmc•Ú,adršÚ,szæÚ,bufŽÚVerifygÚ,fmc•Ú,adršÚ,szæÚ,bufŽÚProgramPage}Ú,fmc•Ú,cmd¬ÚFMC_ReadStatusRegsÚ,fmc•ÚFMC_WriteEnableCÚ,fmc•ÚFMC_WriteDisableÔÚ,fmc•Ú,opsŽÚ,


bufœÚFMC_WriteStatusRegâÚ,fmc•Ú ,


Addr\Ú,cmd¬Ú FMC_ReadByte‹Ú,fmc•Ú ,


addr<Ú ,dataDÚFMC_WriteByteúÚ,fmc•Ú ,


addr<Ú ,data;ÚFMC_WriteHalfWordoÚ,fmc•Ú ,


Addr\Ú,cmd¬Ú FMC_ReadWordƒÚ,fmc•Ú ,


Addr\Ú,cmd¬Ú FMC_ReadPage¢Ú,fmc•Ú ,


Addr\Ú,cmd¬Ú,bufŽÚ,


lenšÚFMC_ReadStream¯Ú,fmc•Ú ,


Addr\Ú,bufŽÚ,


lenšÚFMC_WriteStreamÚ,fmc•Ú ,


Addr\Ú,cmd¬Ú,bufŽÚ,


lenšÚFMC_ReadInfoAreaÚ,fmc•Ú ,


Addr\Ú,bufŽÚ,


lenšÚFMC_WriteInfoAreaÚ,fmc•ÚFMC_EraseInfoAreaœÚ,fmc•Ú ,


mode2Ú,enhanceÚFMC_SetFlashModeôÚ,fmc•ÚFMC_ExitEnhanceMode¼Ú,fmc•Ú ,


mode2ÚFMC_EnterEnhanceModeVÚ,fmc•ÚFMC_EnableAutoDpÿÚ,fmc•ÚFMC_DisableAutoDpÚ,fmc•Ú,


cnt”ÚFMC_SetRdpWaitCountÚ,fmc•Ú,


cnt”ÚFMC_SetDpWaitCountÚ,fmc•Ú ,"IRQnhÚ,"    NewStateÚFMC_SetSuspendIrqWÚ,fmc•Ú,


timeoutÊÚFMC_SetSuspendTimeout”ÚP__PAN_DMAC_H__9ÚPDMAC_CHANNEL_NUMBERÚPDMA_INVLID_CHANNELXÚ"PDMAC_TransferType_Mem2MemoÚ"PDMAC_TransferType_Mem2PergÚ"PDMAC_TransferType_Per2MemgÚ"PDMAC_TransferType_Per2Per_ÚPDMAC_FlowControl_DMA…Ú$PDMAC_FlowControl_Peripheral=ÚPDMAC_BurstLen_1zÚPDMAC_BurstLen_4wÚPDMAC_BurstLen_8sÚPDMAC_BurstLen_16BÚPDMAC_BurstLen_32DÚPDMAC_BurstLen_64?ÚPDMAC_BurstLen_128ÚPDMAC_BurstLen_256


Ú"PDMAC_AddrChange_Increment`Ú"PDMAC_AddrChange_DecrementnÚ!PDMAC_AddrChange_NoChangeÚPDMAC_DataWidth_8&ÚPDMAC_DataWidth_16õÚPDMAC_DataWidth_32÷ÚPDMAC_DataWidth_64òÚPDMAC_DataWidth_128¿ÚPDMAC_DataWidth_256½Ú PDMAC_Peripheral_I2C0_Tx¥Ú PDMAC_Peripheral_I2C0_Rx§Ú PDMAC_Peripheral_SPI0_TxwÚ PDMAC_Peripheral_SPI0_RxyÚ!PDMAC_Peripheral_UART0_Tx%Ú!PDMAC_Peripheral_UART0_Rx'Ú PDMAC_Peripheral_SPI1_TxvÚ PDMAC_Peripheral_SPI1_RxxÚ!PDMAC_Peripheral_UART1_Tx$Ú!PDMAC_Peripheral_UART1_Rx&ÚPDMAC_Peripheral_ADCþÚPDMAC_Peripheral_USB_Rx­ÚPDMAC_Peripheral_USB_Tx«Ú#PDMAC_HandshakePolarity_Low·Ú$PDMAC_HandshakePolarity_HighgÚPDMAC_Handshake_Default€Ú PDMAC_Handshake_SoftwareøÚ PDMAC_Handshake_HardwareÚ$PDMAC_LockLevel_Tfr_Complete}Ú&PDMAC_LockLevel_Block_CompleteºÚ,P$DMAC_LockLevel_Transaction_CompleteÚPDMAC_ChannelPriority_0ÚPDMAC_ChannelPriority_1€ÚPDMAC_ChannelPriority_2ÚPDMAC_ChannelPriority_3~ÚPDMAC_ChannelPriority_4}ÚPDMAC_ChannelPriority_5|ÚPDMAC_ChannelPriority_6{ÚPDMAC_ChannelPriority_7zÚPDMAC_CHANNELALL_MASKÒÚPDMAC_FLAG_INDEX_TFRõÚPDMAC_FLAG_INDEX_BLKÚPDMAC_FLAG_INDEX_SRCTFRÚPDMAC_FLAG_INDEX_DSTTFRÚPDMAC_FLAG_INDEX_ERRøÚPDMAC_FLAG_MASK_TFRCÚPDMAC_FLAG_MASK_BLKVÚPDMAC_FLAG_MASK_SRCTFRUÚPDMAC_FLAG_MASK_DSTTFRRÚPDMAC_FLAG_MASK_ERRFÚPDMAC_FLAG_MASK_ALLVÚ$8__DMAC_ChannelConfigTypeDefÚ 


"í.CTL_LÚ 


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"í.CFG_H-Ú$__DMAC_ChannelConfigTypeDefÙÚ"8DMAC_ChannelConfigTypeDef_Ú 


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"ó.BurstLenDst8Ú 


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BlockSizeÚ 


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"ó.ChannelPriorityoÚ 


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FifoEmptyÚ 


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"ó.LockBusçÚ 


"ó.LockChannelPÚ 


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"ó.HandshakePolaritySrc}Ú 


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"ó.__Rev7zÚ 


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"ó.__Rev8yÚ"DMAC_ChannelConfigTypeDef›ÚDMAC_IsChannelValidõÚ,"›/dma­Ú,


"›/ChIdxÚPDMAC_ChannelMaskòÚDMAC_CombinedIntStatus„Ú,"Ÿ/dma©Ú,


"Ÿ/FlgMskŸÚDMAC_StatusFlagdÚ,"¢/dma¦Ú,


"¢/ChIdxÚ,


"¢/FlgIdx¢Ú DMAC_IntFlagÃÚ,"¦/dma¢Ú,


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Ú,


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"®/FlgIdx–Ú,dma™Ú


DMAC_InitÎÚ,dma™ÚDMAC_DeInit!Ú,dma™Ú,


ChIdxÚ,


FlgIdx•ÚDMAC_ClrIntFlagMsk_Ú,dma™Ú,


ChIdxÚ,


FlgIdx•ÚDMAC_SetIntFlagMskTÚ,dma™Ú,


ChIdxÚ,ConfigoÚDMAC_SetChannelConfigÚ,dma™Ú,


ChIdxÚ,ConfigoÚDMAC_GetChannelConfigÚ,dma™Ú,


ChIdxÚ,Src£Ú,Dst Ú,


LenºÚDMAC_StartChannel‹Ú,dma™Ú,


ChIdxÚ,


LenºÚDMAC_ContinueChannelNÚ,dma™Ú,


ChIdxÚDMAC_StopChannelõÚ,dma™Ú,


ChIdxÚ"DMAC_GetXferredBlockCount^Ú,dma™ÚDMAC_AcquireChannelËÚ,dma™Ú,


ChIdxÚDMAC_ReleaseChannelÔÚ,dma™Ú"DMAC_IsAllChannelReleasedÚP__PAN_GPIO_H__ÚP GPIO_PIN_MAXùÚ8"_GPIO_ModeDef$Ú"ß/GPIO_MODE_INPUT Ú"ß/GPIO_MODE_OUTPUTªÚ"ß/GPIO_MODE_OPEN_DRAIN”Ú"ß/GPIO_MODE_QUASIÚ GPIO_ModeDefÇÚ8"_GPIO_IntAttrDefÝÚ"å/GPIO_INT_RISINGÚ"å/GPIO_INT_FALLINGÒÚ"å/GPIO_INT_BOTH_EDGE*Ú"å/GPIO_INT_HIGHµÚ"å/ GPIO_INT_LOWåÚGPIO_IntAttrDef€Ú8"_GPIO_ClkSrcDefcÚ""ì/GPIO_DBCTL_DBCLKSRC_RCL´Ú#"ì/GPIO_DBCTL_DBCLKSRC_HCLKqÚGPIO_ClkSrcDefÚ8"_GPIO_ClkSelDefgÚ "ð/GPIO_DBCTL_DBCLKSEL_1hÚ "ð/GPIO_DBCTL_DBCLKSEL_2gÚ "ð/GPIO_DBCTL_DBCLKSEL_4eÚ "ð/GPIO_DBCTL_DBCLKSEL_8aÚ!"ð/GPIO_DBCTL_DBCLKSEL_160Ú!"ð/GPIO_DBCTL_DBCLKSEL_322Ú!"ð/GPIO_DBCTL_DBCLKSEL_64-Ú""ð/GPIO_DBCTL_DBCLKSEL_128úÚ""ð/GPIO_DBCTL_DBCLKSEL_256øÚ""ð/GPIO_DBCTL_DBCLKSEL_512ýÚ#"ð/GPIO_DBCTL_DBCLKSEL_1024ÌÚ#"ð/GPIO_DBCTL_DBCLKSEL_2048ÅÚ#"ð/GPIO_DBCTL_DBCLKSEL_4096ÀÚ#"ð/GPIO_DBCTL_DBCLKSEL_8192¿Ú$"ð/GPIO_DBCTL_DBCLKSEL_16384‹Ú$"ð/GPIO_DBCTL_DBCLKSEL_32768‡ÚGPIO_ClkSelDef


ÚPGPIO_PIN_ADDRÂÚPP00ÚPP01ÚPP02ÚPP03ÚPP04ÚPP05ÚPP06ÚPP07ÚPP10ÚPP11ÚPP12ÚPP13ÚPP14ÚPP15ÚPP16ÚPP17 ÚPP20ÚPP21ÚPP22ÚPP23ÚPP24ÚPP25ÚPP26 ÚPP27ÚPP30ÚPP31ÚGPIO_ClrIntFlag‚Ú,"0gpio+Ú,


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"¢0u32PinMaskJÚGPIO_EnableDebounceÔÚ,"¥0gpio#Ú,


"¥0u32PinMaskGÚ GPIO_DisableDigitalPath9Ú,"¨0gpio Ú,


"¨0u32PinMaskDÚGPIO_EnableDigitalPath¨Ú,"«0gpioÚ,


"«0u32PinMaskAÚGPIO_DisablePullupPathwÚ,"®0gpioÚ,


"®0u32PinMask>ÚGPIO_EnablePullupPathæÚ,"±0gpioÚ,


"±0u32PinMask;Ú!GPIO_DisablePulldownPath Ú,"´0gpioÚ,


"´0u32PinMask8Ú GPIO_EnablePulldownPathÚ,"·0gpioÚ,


"·0u32PinMask5ÚGPIO_DisableDoutMaskbÚ,"º0gpioÚ,


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"Ô0u32Pin¬ÚPGPIO_EnableEINT0vÚPGPIO_DisableEINT0ÚPGPIO_EnableEINT1uÚPGPIO_DisableEINT1Ú ,gpioÚ,


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"ž6u32ChannelNumÚPWM_EnableDeadZone,Ú,"¡6pwm~Ú,


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"±6u32ChannelNumùÚPWM_EnablePeriodInt¦Ú,"´6pwmkÚ,


"´6u32ChannelNumöÚPWM_DisablePeriodInt7Ú,"·6pwmhÚ,


"·6u32ChannelNumóÚPWM_ClearPeriodIntFlag†Ú,"º6pwmeÚ,


"º6u32ChannelNumðÚPWM_GetPeriodIntFlagQÚ,"½6pwmbÚ,


"½6u32ChannelNumíÚPWM_EnableZeroIntmÚ,"À6pwm_Ú,


"À6u32ChannelNumêÚPWM_DisableZeroIntþÚ,"Ã6pwm\Ú,


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"Æ6u32ChannelNumäÚPWM_GetZeroIntFlagÚ,"É6pwmVÚ,


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"Ì6u32ChannelNumÞÚPWM_DisableCMPUIntiÚ,"Ï6pwmPÚ,


"Ï6u32ChannelNumÛÚPWM_ClearCMPUIntFlag¸Ú,"Ò6pwmMÚ,


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"Ø6u32ChannelNumÒÚ,""Ø6IntPeriodTypePÚPWM_DisableCenterInt9Ú,"Ü6pwmCÚ,


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"ó6u32ChannelNum·Ú,


"ó6 u32PrescalerÚPWM_ResetPrescalerÙÚ,"÷6pwm(Ú,


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ÚPGPIO_P1_PIN_NUM    ÚPGPIO_P2_PIN_NUMÚPGPIO_P3_PIN_NUMÚPGPIO_INTEN_MASK_BASE’ÚPGPIO_INTTYPE_MASK_BASEßÚ P0_0æÚ P0_1åÚ P0_2äÚ P0_3ãÚ P0_4âÚ P0_5áÚ P0_6àÚ P0_7ßÚ P1_0åÚ P1_1äÚ P1_2ãÚ P1_3âÚ P1_4áÚ P1_5àÚ P1_6ßÚ P1_7ÞÚ P2_0äÚ P2_1ãÚ P2_2âÚ P2_3áÚ P2_4àÚ P2_5ßÚ P2_6ÞÚ P2_7ÝÚ P3_0ãÚ P3_1âÚHAL_GPIO_PinIdOÚ$HAL_GPIO_MODE_INPUT_DIGITAL”Ú#HAL_GPIO_MODE_INPUT_ANALOGâÚ&HAL_GPIO_MODE_OUTPUT_PUSHPULL°Ú'HAL_GPIO_MODE_OUTPUT_OPENDRAIN‹Ú*"HAL_GPIO_MODE_QUASI_BIDIRECTIONALÚÚHAL_GPIO_Mode ÚHAL_GPIO_PULL_DISABLEÚHAL_GPIO_PULL_UPÚÚHAL_GPIO_PULL_DOWNCÚHAL_GPIO_PullˆÚHAL_GPIO_LEVEL_LOWNÚHAL_GPIO_LEVEL_HIGHÚHAL_GPIO_Level+ÚHAL_GPIO_INT_RISINGÿÚHAL_GPIO_INT_FALLINGÌÚHAL_GPIO_INT_BOTH_EDGE$ÚHAL_GPIO_INT_HIGH¯ÚHAL_GPIO_INT_LOWßÚHAL_GPIO_INT_DISABLEÕÚHAL_GPIO_IntModeoÚHAL_GPIO_CallbackFunc|Ú<hHAL_GPIO_CallbackArraykÚ8


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