/**
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*******************************************************************************
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* @file soc.c
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* @create 2024-12-11
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* @author Panchip BLE GROUP
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* @note
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* Copyright (c) 2022-2024 Shanghai Panchip Microelectronics Co.,Ltd.
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*
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*******************************************************************************
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*/
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#include "soc_api.h"
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#if CONFIG_APP_USE_IMAGE_HEADER
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#include "img_hdr.h"
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#endif
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#if BLE_EN
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#include "pan_ble.h"
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#endif
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#if CONFIG_RTT_LOG_ENABLE
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#include "SEGGER_RTT.h"
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#endif
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#include "app_log.h"
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#include "utility.h"
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/*******************************************************************************
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* Macro
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******************************************************************************/
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#define CLK_ACT32K_TMR_EN_Pos (0)
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#define CLK_ACT32K_TMR_EN_Msk (0x1ul << CLK_ACT32K_TMR_EN_Pos)
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#define CLK_ACT32K_LL_32KCLK_SEL_Pos (1)
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#define CLK_ACT32K_LL_32KCLK_SEL_Msk (0x1ul << CLK_ACT32K_LL_32KCLK_SEL_Pos)
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/* Do not modify this definition */
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#define LPTMR_CURR_CNT_ENA_REG (0x5002000C)
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/*******************************************************************************
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* Variable Define & Declaration
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******************************************************************************/
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uint32_t lp_int_ctrl_reg;
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uint32_t rst_status_reg;
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uint8_t m_chip_mac[6];
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/*******************************************************************************
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* Constant Data Structure
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******************************************************************************/
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#if (!IS_BOOTLOADER && CONFIG_APP_USE_IMAGE_HEADER)
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IMG_HDR_SECTION const struct img_hdr image_header = {
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.ih_magic = IMAGE_MAGIC,
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.ih_hdr_size = IMAGE_HEADER_SIZE,
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.ih_img_size = 0,
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.ih_ver.iv_major = CONFIG_APP_IMG_VER_MAJOR,
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.ih_ver.iv_minor = CONFIG_APP_IMG_VER_MINOR,
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.ih_ver.iv_revision = CONFIG_APP_IMG_VER_REVISION,
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.ih_ver.iv_build_num = CONFIG_APP_IMG_VER_BUILD,
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};
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#endif /* CONFIG_APP_USE_IMAGE_HEADER */
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/*******************************************************************************
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* Public Function Define
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******************************************************************************/
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CONFIG_RAM_CODE void soc_busy_wait(uint32_t us)
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{
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while (us--) {
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#if (CONFIG_SYSTEM_CLOCK == 32)
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__NOP(); __NOP(); __NOP(); __NOP(); __NOP();
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__NOP(); __NOP(); __NOP(); __NOP(); __NOP();
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__NOP(); __NOP(); __NOP(); __NOP(); __NOP();
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__NOP(); __NOP(); __NOP(); __NOP(); __NOP();
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__NOP(); __NOP(); __NOP(); __NOP(); __NOP();
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__NOP(); __NOP(); __NOP();
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#elif (CONFIG_SYSTEM_CLOCK == 48)
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__NOP(); __NOP(); __NOP(); __NOP(); __NOP();
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__NOP(); __NOP(); __NOP(); __NOP(); __NOP();
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__NOP(); __NOP(); __NOP(); __NOP(); __NOP();
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__NOP(); __NOP(); __NOP(); __NOP(); __NOP();
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__NOP(); __NOP(); __NOP(); __NOP(); __NOP();
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__NOP(); __NOP(); __NOP(); __NOP(); __NOP();
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__NOP(); __NOP(); __NOP(); __NOP(); __NOP();
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__NOP(); __NOP(); __NOP(); __NOP(); __NOP();
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__NOP(); __NOP(); __NOP(); __NOP();
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#else
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#error "Unsupported system clock for soc_busy_wait()!"
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#endif
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}
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}
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uint8_t soc_reset_reason_get(void)
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{
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#if 0
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printf("ANA->LP_INT_CTRL: 0x%08x\n", lp_int_ctrl_reg);
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printf("CLK->RSTSTS: 0x%08x\n", rst_status_reg);
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#endif
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/* Check standby mode int flags to detect standby mode wakeup */
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if (lp_int_ctrl_reg & ANAC_INT_STANDBY_M1_FLAG_Msk) {
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/* Check lptmr wakeup flag */
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if (lp_int_ctrl_reg & ANAC_INT_SLEEP_TMR0_Msk) {
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return SOC_RST_REASON_STBM1_SLPTMR0_WAKEUP;
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} else if (lp_int_ctrl_reg & ANAC_INT_SLEEP_TMR1_Msk) {
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return SOC_RST_REASON_STBM1_SLPTMR1_WAKEUP;
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} else if (lp_int_ctrl_reg & ANAC_INT_SLEEP_TMR2_Msk) {
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return SOC_RST_REASON_STBM1_SLPTMR2_WAKEUP;
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} else {
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return SOC_RST_REASON_STBM1_GPIO_WAKEUP;
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}
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} else if (lp_int_ctrl_reg & ANAC_INT_STANDBY_M0_FLAG_Msk) {
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return SOC_RST_REASON_STBM0_EXTIO_WAKEUP;
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}
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/* Check common reset status flags */
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if (rst_status_reg & BIT0) {
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return SOC_RST_REASON_CHIP_RESET;
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} else if (rst_status_reg & BIT1) {
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return SOC_RST_REASON_PIN_RESET;
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} else if (rst_status_reg & BIT2) {
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return SOC_RST_REASON_WDT_RESET;
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} else if (rst_status_reg & BIT3) {
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return SOC_RST_REASON_LVR_RESET;
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} else if (rst_status_reg & BIT4) {
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return SOC_RST_REASON_BOD_RESET;
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} else if (!(ANA->LP_FL_CTRL_3V & BIT6)) {
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/* (Workaround) Re-set the additional reserved indication flag after use */
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ANA->LP_FL_CTRL_3V |= BIT6;
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return SOC_RST_REASON_SYS_RESET;
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} else if (rst_status_reg & BIT6) {
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return SOC_RST_REASON_POR_RESET;
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}
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return SOC_RST_REASON_UNKNOWN_RESET;
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}
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/*******************************************************************************
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* Private Function Define
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******************************************************************************/
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void sys_clock_Init(void)
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{
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/* Unlock protected registers */
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SYS_UnlockReg();
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ANA->LP_FSYN_LDO |= 0X1;
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CLK_XthStartupConfig();
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CLK->XTH_CTRL |= CLK_XTHCTL_XTH_EN_Msk;
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CLK_WaitClockReady(CLK_SYS_SRCSEL_XTH);
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#if (CONFIG_SYSTEM_CLOCK == 32)
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CLK_HCLKConfig(1);
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CLK_SYSCLKConfig(CLK_DPLL_REF_CLKSEL_XTH, CLK_DPLL_OUT_64M);
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#elif (CONFIG_SYSTEM_CLOCK == 48)
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CLK_HCLKConfig(0);
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CLK_SYSCLKConfig(CLK_DPLL_REF_CLKSEL_XTH, CLK_DPLL_OUT_48M);
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#endif
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CLK_RefClkSrcConfig(CLK_SYS_SRCSEL_DPLL);
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CLK->RCH_CTRL &= ~BIT(0);
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CLK_PCLK1Config(CONFIG_APB1_CLOCK_DIVISOR >> 1);
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CLK_PCLK2Config(CONFIG_APB2_CLOCK_DIVISOR >> 1);
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/*
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* Note that all clocks on APB are disabled by default after SoC power up, and
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* the default AHB clocks enabled after SoC power up are:
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* ACC/eFuse/ROM/RCC_AHB/Systick/GPIO.
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* Here we disable ACC, eFuse and ROM clock as these modules are not commonly
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* used. We should re-enabled them once we use later.
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* Here We also enable APB1 and APB2 clock path to make sure modules on APB can
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* be easily enabled by each peripheral driver by enabling their clock enable
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* bits on APB bus.
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*/
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CLK_AHBPeriphClockCmd(CLK_AHBPeriph_ROM, DISABLE);
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CLK_AHBPeriphClockCmd(CLK_AHBPeriph_APB1 | CLK_AHBPeriph_APB2, ENABLE);
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/*Basic clock for BLE*/
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CLK_AHBPeriphClockCmd(CLK_AHBPeriph_BLE_32M | CLK_AHBPeriph_BLE_32K, ENABLE);
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CLK_AHBPeriphClockCmd(CLK_AHBPeriph_USB_AHB | CLK_AHBPeriph_USB_48M, DISABLE);
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}
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#define APP_POWER_TEST_EN 0
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#if APP_POWER_TEST_EN
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void app_power_test(OTP_STRUCT_T *otp)
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{
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//buck out(DCDC):default:8; FT-2
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uint32_t tmp = ANA->LP_BUCK_3V;
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tmp &= ~(0xFul<<2);
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tmp |= (((otp->m.buck_out_trim >> 1) - 2) << 2);
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//tmp |= (((otp->m.buck_out_trim >> 1) - 3) << 2);
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ANA->LP_BUCK_3V = tmp;
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//HPLDO(DVDD) default - 1/2; default:8
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tmp = ANA->LP_HP_LDO;
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tmp &= ~(0xFul <<3);
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tmp |= ((otp->m.hp_ldo_trim - 2)<<3); //~1.12V
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ANA->LP_HP_LDO = tmp;
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}
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#endif
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static int pan10xx_hw_calib_init(void)
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{
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OTP_STRUCT_T otp;
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printf("Try to load HW calibration data..");
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if (!SystemHwParamLoader(&otp)) {
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printf("\nWARNING: Cannot find valid calib data in current chip!\n");
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} else {
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printf(" DONE.\n");
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printf("- Chip Info : 0x%x\n", otp.m.chip_info);
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printf("- Chip CP Version : %d\n", otp.m.cp_version);
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printf("- Chip FT Version : %d\n", otp.m.ft_version);
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if (otp.m.ft_version >= 2) {
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memcpy(m_chip_mac, otp.m_v2.mac_addr, 6);
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printf("- Chip MAC Address : %02X%02X%02X%02X%02X%02X\n", otp.m_v2.mac_addr[0], otp.m_v2.mac_addr[1],
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otp.m_v2.mac_addr[2], otp.m_v2.mac_addr[3], otp.m_v2.mac_addr[4], otp.m_v2.mac_addr[5]);
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} else {
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memcpy(m_chip_mac, otp.m.mac_addr, 6);
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printf("- Chip MAC Address : %02X%02X%02X%02X%02X%02X\n", otp.m.mac_addr[0], otp.m.mac_addr[1],
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otp.m.mac_addr[2], otp.m.mac_addr[3], otp.m.mac_addr[4], otp.m.mac_addr[5]);
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}
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printf("- Chip UID : %02X%02X%02X%02X%02X%02X%02X%02X%02X\n", otp.m.uid[0], otp.m.uid[1],
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otp.m.uid[2], otp.m.uid[3], otp.m.uid[4], otp.m.uid[5], otp.m.uid[6], otp.m.uid[7], otp.m.uid[8]);
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#if APP_POWER_TEST_EN
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app_power_test(&otp);
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#endif
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}
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printf("- Chip Flash UID : ");
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for (uint32_t i = 0; i < 16; i++) {
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printf("%02X", flash_ids.uid[i]);
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}
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printf("\n- Chip Flash Size : %ld KB\n", BIT(flash_ids.memory_density_id) >> 10);
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return 0;
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}
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__WEAK void sleep_timer0_handler(void)
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{
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/* This function can be overridden in application */
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printf("%s in..\n", __func__);
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}
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__WEAK void sleep_timer1_handler(void)
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{
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/* This function can be overridden in application */
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printf("%s in..\n", __func__);
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}
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__WEAK void sleep_timer2_handler(void)
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{
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/* This function can be overridden in application */
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printf("%s in..\n", __func__);
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}
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__WEAK void sleep_timer_post_irq_handler(void)
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{
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/* This function can be overridden in application */
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}
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CONFIG_RAM_CODE void SLPTMR_IRQHandler(void)
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{
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PAN_IO_TIMING_TRACK_LEVEL(CONFIG_TRACK_PIN_SLPTMR_IRQ, 1);
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/* Handle os clock timeout */
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if (ANA->LP_INT_CTRL & ANAC_INT_SLEEP_TMR0_Msk) {
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/*
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* Clear sleep timer 0 interrupt flags (write 1 to clear) in this register,
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* and retain other settings / flags.
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*/
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ANA->LP_INT_CTRL = (ANA->LP_INT_CTRL | ANAC_INT_SLEEP_TMR0_Msk)
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& ~(ANAC_INT_SLEEP_TMR1_Msk | ANAC_INT_SLEEP_TMR2_Msk
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| ANAC_INT_DP_FLAG_Msk | ANAC_INT_STANDBY_M1_FLAG_Msk
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| ANAC_INT_STANDBY_M0_FLAG_Msk | ANAC_INT_SRAM_RET_FLAG_Msk);
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/* Execute slptmr0 handler */
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sleep_timer0_handler();
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}
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/* Handle custom sleep timer1 event */
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if (ANA->LP_INT_CTRL & ANAC_INT_SLEEP_TMR1_Msk) {
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/*
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* Clear sleep timer 1 interrupt flags (write 1 to clear) in this register,
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* and retain other settings / flags.
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*/
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ANA->LP_INT_CTRL = (ANA->LP_INT_CTRL | ANAC_INT_SLEEP_TMR1_Msk)
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& ~(ANAC_INT_SLEEP_TMR0_Msk | ANAC_INT_SLEEP_TMR2_Msk
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| ANAC_INT_DP_FLAG_Msk | ANAC_INT_STANDBY_M1_FLAG_Msk
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| ANAC_INT_STANDBY_M0_FLAG_Msk | ANAC_INT_SRAM_RET_FLAG_Msk);
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/* Execute slptmr1 handler */
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sleep_timer1_handler();
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}
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/* Handle custom sleep timer2 event */
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if (ANA->LP_INT_CTRL & ANAC_INT_SLEEP_TMR2_Msk) {
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/*
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* Clear sleep timer 2 interrupt flags (write 1 to clear) in this register,
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* and retain other settings / flags.
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*/
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ANA->LP_INT_CTRL = (ANA->LP_INT_CTRL | ANAC_INT_SLEEP_TMR2_Msk)
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& ~(ANAC_INT_SLEEP_TMR0_Msk | ANAC_INT_SLEEP_TMR1_Msk
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| ANAC_INT_DP_FLAG_Msk | ANAC_INT_STANDBY_M1_FLAG_Msk
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| ANAC_INT_STANDBY_M0_FLAG_Msk | ANAC_INT_SRAM_RET_FLAG_Msk);
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/* Execute slptmr2 handler */
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sleep_timer2_handler();
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}
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sleep_timer_post_irq_handler();
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PAN_IO_TIMING_TRACK_LEVEL(CONFIG_TRACK_PIN_SLPTMR_IRQ, 0);
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}
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void pan10xx_platform_init()
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{
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#if CONFIG_VECTOR_REMAP_TO_RAM
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static __ALIGNED(256) uint32_t ram_vector[64] = {0};
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extern uint32_t __Vectors;
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memcpy((void*)ram_vector, &__Vectors, 256);
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ANA->CPU_ADDR_REMAP_CTRL = ((uint32_t)ram_vector >> 8) | BIT(31);
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#endif /* CONFIG_VECTOR_REMAP_TO_RAM */
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pan10xx_hw_calib_init();
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#if CONFIG_FLASH_LDO_EN
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ANA->LP_HP_LDO &= ~ANAC_HPLDO_FLASHLDO_BP_Msk_3v;
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#else
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ANA->LP_HP_LDO |= ANAC_HPLDO_FLASHLDO_BP_Msk_3v;
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#endif /* CONFIG_FLASH_LDO_EN */
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// Ensure SoC LP configure is sleep mode (default state)
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SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
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LP_SetSleepMode(ANA, LP_MODE_SEL_SLEEP_MODE);
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#if (CONFIG_LOW_SPEED_CLOCK_SRC == 0) /*LP Clock from RCL, 32000 HZ default*/
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/* Enable RCL */
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CLK->RCL_CTRL_3V |= CLK_RCLCTL_RC32K_EN_Msk_3v;
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/* Wait for stable */
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while (!(CLK->RCL_CTRL_3V & CLK_STABLE_STATUS_Msk));
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/* Select RCL as SoC 32K clock source */
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CLK->CLK_TOP_CTRL_3V &= ~CLK_TOPCTL_32K_CLK_SEL_Msk_3v;
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/* Disable lp xtl src */
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ANA->LP_FL_CTRL_3V &= ~ANAC_FL_XTAL32K_EN_Msk_3v;
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ANA->LP_FL_CTRL_3V |= ANAC_FL_RC32K_EN_Msk_3v;
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/* Delay more than two 32K clock cycles */
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SYS_delay_10nop(250);
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/* Disable XTL */
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CLK->XTL_CTRL_3V &= ~CLK_XTLCTL_XTL_EN_Msk_3v;
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#if CONFIG_FORCE_CALIB_RCL_CLK
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/* Calibrate RCL to 32K Hz */
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calibrate_rcl_clk(32000);
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#endif /* CONFIG_FORCE_CALIB_RCL_CLK */
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#elif ( CONFIG_LOW_SPEED_CLOCK_SRC == 2) /*LP Clock from ACT32K,32000 HZ default*/
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ANA->ACT_32K_CTRL |= (CLK_ACT32K_TMR_EN_Msk | CLK_ACT32K_LL_32KCLK_SEL_Msk); /*LP Clock from XTL,32768 HZ default*/
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#else /*LP Clock from XTL, 32768 HZ */
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#ifdef XTL_SLOW_SETUP
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/* Enable XTL clock */
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CLK->XTL_CTRL_3V |= CLK_XTLCTL_XTL_EN_Msk_3v;
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while(!(CLK->XTL_CTRL_3V & CLK_XTLCTL_STABLE_Msk));
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#else // Quick Setup
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CLK->MEAS_CLK_CTRL = (CLK->MEAS_CLK_CTRL & ~(CLK_MEASCLK_XTH_DIV_Msk)) | (0x1e8 << CLK_MEASCLK_XTH_DIV_Pos);
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CLK->XTL_CTRL_3V = (CLK->XTL_CTRL_3V & ~(CLK_XTLCTL_DELAY_Msk_3v)) | (3 << CLK_XTLCTL_DELAY_Pos_3v);
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/* Enable quick startup */
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CLK->MEAS_CLK_CTRL |= CLK_MEASCLK_XTL_QUICK_EN_Msk;
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SYS_SET_MFP(P2, 0, XTL_C1_CLK);
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SYS_SET_MFP(P2, 1, XTL_C2_CLK);
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/* Enable XTL clock */
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CLK->XTL_CTRL_3V |= CLK_XTLCTL_XTL_EN_Msk_3v;
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/* Delay a while */
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SYS_delay_10nop(5000);
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/* Disable quick startup */
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CLK->MEAS_CLK_CTRL &= ~CLK_MEASCLK_XTL_QUICK_EN_Msk;
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SYS_SET_MFP(P2, 0, GPIO);
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SYS_SET_MFP(P2, 1, GPIO);
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/* Wait for stable */
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while (!(CLK->XTL_CTRL_3V & CLK_STABLE_STATUS_Msk)) {
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/* Busy wait */
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__NOP();
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}
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#endif /* XTL_SLOW_SETUP */
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/* Select XTL as current 32K clock */
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CLK->CLK_TOP_CTRL_3V |= CLK_TOPCTL_32K_CLK_SEL_Msk_3v;
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/* Delay more than two 32K clock cycles */
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SYS_delay_10nop(250);
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/* Disable lp rcl src */
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ANA->LP_FL_CTRL_3V |= ANAC_FL_XTAL32K_EN_Msk_3v;
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ANA->LP_FL_CTRL_3V &= ~ANAC_FL_RC32K_EN_Msk_3v;
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/* Disable RCL clock */
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CLK->RCL_CTRL_3V &= ~BIT(0);
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#endif /* CONFIG_LOW_SPEED_CLOCK_SRC */
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/* Store value in rst status reg and lp int ctrl reg for later possible soc_reset_reason_get() use */
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rst_status_reg = CLK->RSTSTS;
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lp_int_ctrl_reg = ANA->LP_INT_CTRL;
|
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/* Clear status registers for next time detecting. And would not clear it in bootloader so that these
|
flags can also be obtained in app. */
|
#if !IS_BOOTLOADER
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CLK->RSTSTS = CLK->RSTSTS;
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ANA->LP_INT_CTRL = ANA->LP_INT_CTRL;
|
#endif
|
|
/* Enable sleeptimer counter */
|
ANA->LP_FL_CTRL_3V |= ANAC_FL_SLEEP_CNT_EN_Msk;
|
(*(volatile uint32_t *)LPTMR_CURR_CNT_ENA_REG) |= BIT1;
|
/* Clear configured time of sleep timers */
|
ANA->LP_SPACING_TIME0 = 0;
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ANA->LP_SPACING_TIME1 = 0;
|
ANA->LP_SPACING_TIME2 = 0;
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/* Enable sleeptimer interrupt */
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ANA->LP_INT_CTRL |= ANAC_INT_SLEEP_TMR_INT_EN_Msk;
|
NVIC_EnableIRQ(SLPTMR_IRQn);
|
NVIC_SetPriority(SLPTMR_IRQn, 3); // Lowest prio
|
}
|
|
__WEAK void HAL_DriverInit(void)
|
{
|
// This weak function impl would be replaced by corresponding function in pan_hal.c
|
// when hal driver is added in project build.
|
}
|
|
void $Sub$$main(void)
|
{
|
/* system clock initialization */
|
sys_clock_Init();
|
|
#if CONFIG_STARTUP_LONG_DELAY
|
soc_busy_wait(1000*1000);
|
#endif
|
|
/* Init IO Timing Track Pins */
|
#if CONFIG_IO_TIMING_TRACK
|
track_pin_init();
|
#endif // CONFIG_IO_TIMING_TRACK
|
|
/* Init Logging System */
|
#if APP_LOG_EN
|
#if CONFIG_UART_LOG_ENABLE
|
debug_uart_init();
|
#endif // CONFIG_UART_LOG_ENABLE
|
#if CONFIG_RTT_LOG_ENABLE
|
SEGGER_RTT_Init();
|
#endif // CONFIG_RTT_LOG_ENABLE
|
#if BLE_EN
|
#if (CONFIG_UART_LOG_ENABLE || CONFIG_RTT_LOG_ENABLE)
|
pan_misc_register_print(vprintf);
|
#endif // CONFIG_UART_LOG_ENABLE || CONFIG_RTT_LOG_ENABLE
|
#endif // BLE_EN
|
#endif // APP_LOG_EN
|
|
/* Platform misc configurations (32K Clock, FT load, Flash LDO) */
|
pan10xx_platform_init();
|
|
/* init hal driver when needed */
|
HAL_DriverInit();
|
|
/* PM initialization */
|
#if CONFIG_PM
|
extern void soc_pm_init(void);
|
soc_pm_init();
|
#endif
|
|
/* get clock frequence, no matter rcl or xtl */
|
#if ((CONFIG_LOW_SPEED_CLOCK_SRC == 0) || (CONFIG_LOW_SPEED_CLOCK_SRC == 1))
|
clktrim_measure_32k_clk(1000);
|
#endif
|
|
#if (!IS_BOOTLOADER && CONFIG_APP_USE_IMAGE_HEADER)
|
struct img_hdr *image_header_p = (void *)CONFIG_FLASH_PARTITION_APP_ADDR;
|
if (image_header_p->ih_magic == IMAGE_MAGIC) {
|
printf("APP image header check passed, image version: %d.%d.%d.%d\n",
|
image_header_p->ih_ver.iv_major,
|
image_header_p->ih_ver.iv_minor,
|
image_header_p->ih_ver.iv_revision,
|
image_header_p->ih_ver.iv_build_num
|
);
|
}
|
#endif /* CONFIG_APP_USE_IMAGE_HEADER */
|
|
#if CONFIG_OS_EN
|
extern __NO_RETURN void os_schedule_main(void);
|
os_schedule_main();
|
#else
|
extern int $Super$$main(void);
|
$Super$$main();
|
#endif /* CONFIG_OS_EN */
|
}
|
