/*
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* Licensed to the Apache Software Foundation (ASF) under one
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* or more contributor license agreements. See the NOTICE file
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* distributed with this work for additional information
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* regarding copyright ownership. The ASF licenses this file
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* to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance
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* with the License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing,
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* software distributed under the License is distributed on an
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* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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* KIND, either express or implied. See the License for the
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* specific language governing permissions and limitations
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* under the License.
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <string.h>
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#include "nimble_syscfg.h"
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#include "sysflash/sysflash.h"
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#include "os/os.h"
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#include "mcu/mcu.h"
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#include "mcu/cmsis_nvic.h"
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#include "mcu/da1469x_hal.h"
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#include "mcu/da1469x_lpclk.h"
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#include "mcu/da1469x_clock.h"
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#include "mcu/da1469x_trimv.h"
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#include "mcu/da1469x_pdc.h"
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#include "cmac_driver/cmac_host.h"
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#include "cmac_driver/cmac_shared.h"
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#include "cmac_driver/cmac_diag.h"
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#include "trng/trng.h"
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#if MYNEWT_VAL(CMAC_DEBUG_COREDUMP_ENABLE)
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#include "console/console.h"
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#endif
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/* CMAC data */
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extern char _binary_cmac_rom_bin_start[];
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extern char _binary_cmac_rom_bin_end;
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extern char _binary_cmac_ram_bin_start[];
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extern char _binary_cmac_ram_bin_end;
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struct cmac_image_info {
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uint32_t magic;
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uint32_t size_rom;
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uint32_t size_ram;
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uint32_t offset_data;
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uint32_t offset_shared;
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};
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/* PDC entry for waking up CMAC */
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static int8_t g_cmac_host_pdc_sys2cmac;
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/* PDC entry for waking up M33 */
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static int8_t g_cmac_host_pdc_cmac2sys;
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static void cmac_host_rand_fill(struct os_event *ev);
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static struct os_event g_cmac_host_rand_ev = {
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.ev_cb = cmac_host_rand_fill
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};
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static void cmac_host_rand_chk_fill(void);
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#if MYNEWT_VAL_CHOICE(BLE_TRANSPORT_HS, uart)
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static void cmac_host_error_w4flush(struct os_event *ev);
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static struct os_event g_cmac_host_error_ev = {
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.ev_cb = cmac_host_error_w4flush
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};
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#endif
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static void
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cmac2sys_isr(void)
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{
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#if MYNEWT_VAL(CMAC_DEBUG_COREDUMP_ENABLE)
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volatile struct cmac_coredump *cd = &g_cmac_shared_data->coredump;
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const char *assert_file;
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#endif
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os_trace_isr_enter();
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/* Clear CMAC2SYS interrupt */
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*(volatile uint32_t *)0x40002000 = 2;
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cmac_mbox_read();
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if (*(volatile uint32_t *)0x40002000 & 0x1c00) {
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#if MYNEWT_VAL(CMAC_DEBUG_COREDUMP_ENABLE)
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console_blocking_mode();
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console_printf("CMAC error (0x%08lx)\n", *(volatile uint32_t *)0x40002000);
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console_printf(" lr:0x%08lx pc:0x%08lx\n", cd->lr, cd->pc);
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if (cd->assert) {
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console_printf(" assert:0x%08lx\n", cd->assert);
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if (cd->assert_file) {
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/* Need to translate pointer from M0 code segment to M33 data */
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assert_file = cd->assert_file + MCU_MEM_SYSRAM_START_ADDRESS +
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MEMCTRL->CMI_CODE_BASE_REG;
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console_printf(" %s:%d\n",
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assert_file, (unsigned)cd->assert_line);
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}
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}
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console_printf(" 0x%08lx CM_ERROR_REG\n", cd->CM_ERROR_REG);
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console_printf(" 0x%08lx CM_EXC_STAT_REG\n", cd->CM_EXC_STAT_REG);
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console_printf(" 0x%08lx CM_LL_TIMER1_36_10_REG\n", cd->CM_LL_TIMER1_36_10_REG);
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console_printf(" 0x%08lx CM_LL_TIMER1_9_0_REG\n", cd->CM_LL_TIMER1_9_0_REG);
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/* Spin if debugger is connected to CMAC to avoid resetting it */
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if (cd->CM_STAT_REG & 0x20) {
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for (;;);
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}
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#endif
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#if MYNEWT_VAL_CHOICE(BLE_TRANSPORT_HS, uart)
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NVIC_DisableIRQ(CMAC2SYS_IRQn);
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/* Wait until UART is flushed and then assert */
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cmac_host_error_w4flush(NULL);
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return;
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#endif
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/* XXX CMAC is in error state, need to recover */
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assert(0);
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return;
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}
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cmac_host_rand_chk_fill();
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os_trace_isr_exit();
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}
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static void
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cmac_host_rand_fill(struct os_event *ev)
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{
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size_t num_bytes;
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struct trng_dev *trng;
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uint32_t *rnum;
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uint32_t rnums[CMAC_RAND_BUF_ELEMS];
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/* Check if full */
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if (!cmac_rand_is_active() || cmac_rand_is_full()) {
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return;
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}
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assert(ev->ev_arg != NULL);
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/* Fill buffer with random numbers even though we may not use all of them */
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trng = ev->ev_arg;
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rnum = &rnums[0];
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num_bytes = trng_read(trng, rnum, CMAC_RAND_BUF_ELEMS * sizeof(uint32_t));
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cmac_rand_fill(rnum, num_bytes / 4);
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cmac_host_signal2cmac();
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}
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static void
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cmac_host_rand_chk_fill(void)
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{
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if (cmac_rand_is_active() && !cmac_rand_is_full()) {
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os_eventq_put(os_eventq_dflt_get(), &g_cmac_host_rand_ev);
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}
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}
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#if MYNEWT_VAL_CHOICE(BLE_TRANSPORT_HS, uart)
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#if MYNEWT_VAL(BLE_TRANSPORT_UART_PORT) < 0 || MYNEWT_VAL(BLE_TRANSPORT_UART_PORT) > 2
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#error Invalid BLE_HCI_UART_PORT
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#endif
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static void
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cmac_host_error_w4flush(struct os_event *ev)
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{
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static UART_Type * const regs[] = {
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(void *)UART,
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(void *)UART2,
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(void *)UART3
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};
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if (!ev) {
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/* Move to task context, we do not want to spin in interrupt */
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os_eventq_put(os_eventq_dflt_get(), &g_cmac_host_error_ev);
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return;
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}
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do {
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cmac_mbox_read();
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while ((regs[MYNEWT_VAL(BLE_TRANSPORT_UART_PORT)]->UART_LSR_REG &
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UART_UART_LSR_REG_UART_TEMT_Msk) == 0) {
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/* Wait until both FIFO and shift registers are empty */
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}
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} while (cmac_mbox_has_data());
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/* Reset CMAC */
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CRG_TOP->CLK_RADIO_REG |= CRG_TOP_CLK_RADIO_REG_CMAC_SYNCH_RESET_Msk;
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assert(0);
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}
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#endif
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void
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cmac_host_signal2cmac(void)
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{
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da1469x_pdc_set(g_cmac_host_pdc_sys2cmac);
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}
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static void
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cmac_host_lpclk_cb(uint32_t freq)
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{
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/* No need to wakeup CMAC if LP clock frequency did not change */
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if (g_cmac_shared_data->lp_clock_freq == freq) {
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return;
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}
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cmac_shared_lock();
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g_cmac_shared_data->lp_clock_freq = freq;
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g_cmac_shared_data->pending_ops |= CMAC_PENDING_OP_LP_CLK;
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cmac_shared_unlock();
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cmac_host_signal2cmac();
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}
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#if MYNEWT_VAL(CMAC_DEBUG_HOST_PRINT_ENABLE)
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static void
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cmac_host_print_trim(const char *name, const uint32_t *tv, unsigned len)
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{
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console_printf("[CMAC] Trim values for '%s'\n", name);
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while (len) {
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console_printf(" 0x%08x = 0x%08x\n", (unsigned)tv[0], (unsigned)tv[1]);
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len -= 2;
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tv += 2;
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}
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}
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#endif
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void
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cmac_host_rf_calibrate(void)
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{
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cmac_shared_lock();
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g_cmac_shared_data->pending_ops |= CMAC_PENDING_OP_RF_CAL;
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cmac_shared_unlock();
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cmac_host_signal2cmac();
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}
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void
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cmac_host_init(void)
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{
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struct trng_dev *trng;
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struct cmac_image_info ii;
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uint32_t cmac_rom_size;
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uint32_t cmac_ram_size;
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#if !MYNEWT_VAL(CMAC_IMAGE_SINGLE)
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const struct flash_area *fa;
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int rc;
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#endif
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struct cmac_trim *trim;
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/* Get trng os device */
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trng = (struct trng_dev *) os_dev_open("trng", OS_TIMEOUT_NEVER, NULL);
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assert(trng);
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g_cmac_host_rand_ev.ev_arg = trng;
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#if MYNEWT_VAL(CMAC_DEBUG_DIAG_ENABLE)
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cmac_diag_setup_host();
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#endif
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#if MYNEWT_VAL(CMAC_DEBUG_SWD_ENABLE)
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/* Enable CMAC debugger */
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CRG_TOP->SYS_CTRL_REG |= 0x40; /* CRG_TOP_SYS_CTRL_REG_CMAC_DEBUGGER_ENABLE_Msk */
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#endif
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/*
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* Add PDC entry to wake up CMAC from M33
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*
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* XXX if MCU_DEBUG_GPIO_DEEP_SLEEP is enabled on CMAC, this should also
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* enable PD_COM so CMAC can access GPIOs after wake up
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*/
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g_cmac_host_pdc_sys2cmac = da1469x_pdc_add(MCU_PDC_TRIGGER_MAC_TIMER,
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MCU_PDC_MASTER_CMAC,
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MCU_PDC_EN_XTAL);
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da1469x_pdc_set(g_cmac_host_pdc_sys2cmac);
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da1469x_pdc_ack(g_cmac_host_pdc_sys2cmac);
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/* Add PDC entry to wake up M33 from CMAC, if does not exist yet */
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g_cmac_host_pdc_cmac2sys = da1469x_pdc_find(MCU_PDC_TRIGGER_COMBO,
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MCU_PDC_MASTER_M33, 0);
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if (g_cmac_host_pdc_cmac2sys < 0) {
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g_cmac_host_pdc_cmac2sys = da1469x_pdc_add(MCU_PDC_TRIGGER_COMBO,
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MCU_PDC_MASTER_M33,
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MCU_PDC_EN_XTAL);
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da1469x_pdc_set(g_cmac_host_pdc_cmac2sys);
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da1469x_pdc_ack(g_cmac_host_pdc_cmac2sys);
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}
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/* Setup CMAC2SYS interrupt */
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NVIC_SetVector(CMAC2SYS_IRQn, (uint32_t)cmac2sys_isr);
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NVIC_SetPriority(CMAC2SYS_IRQn, MYNEWT_VAL(CMAC_CMAC2SYS_IRQ_PRIORITY));
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NVIC_DisableIRQ(CMAC2SYS_IRQn);
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/* Enable Radio LDO */
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CRG_TOP->POWER_CTRL_REG |= CRG_TOP_POWER_CTRL_REG_LDO_RADIO_ENABLE_Msk;
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/* Enable CMAC, but keep it in reset */
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CRG_TOP->CLK_RADIO_REG = (1 << CRG_TOP_CLK_RADIO_REG_RFCU_ENABLE_Pos) |
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(1 << CRG_TOP_CLK_RADIO_REG_CMAC_SYNCH_RESET_Pos) |
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(0 << CRG_TOP_CLK_RADIO_REG_CMAC_CLK_SEL_Pos) |
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(1 << CRG_TOP_CLK_RADIO_REG_CMAC_CLK_ENABLE_Pos) |
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(0 << CRG_TOP_CLK_RADIO_REG_CMAC_DIV_Pos);
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/* Calculate size of ROM and RAM area */
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cmac_rom_size = &_binary_cmac_rom_bin_end - &_binary_cmac_rom_bin_start[0];
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cmac_ram_size = &_binary_cmac_ram_bin_end - &_binary_cmac_ram_bin_start[0];
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/* Load image header and check if image can be loaded */
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#if MYNEWT_VAL(CMAC_IMAGE_SINGLE)
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memcpy(&ii, &_binary_cmac_rom_bin_start[128], sizeof(ii));
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#else
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rc = flash_area_open(FLASH_AREA_IMAGE_1, &fa);
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assert(rc == 0);
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rc = flash_area_read(fa, 128, &ii, sizeof(ii));
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assert(rc == 0);
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#endif
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assert(ii.magic == 0xC3ACC3AC);
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assert(ii.size_rom == cmac_rom_size);
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assert(ii.size_ram <= cmac_ram_size);
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/* Copy CMAC image to RAM */
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#if MYNEWT_VAL(CMAC_IMAGE_SINGLE)
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memset(&_binary_cmac_ram_bin_start, 0xaa, cmac_ram_size);
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memcpy(&_binary_cmac_ram_bin_start, &_binary_cmac_rom_bin_start, ii.size_rom);
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#else
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memset(&_binary_cmac_ram_bin_start, 0xaa, cmac_ram_size);
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rc = flash_area_read(fa, 0, &_binary_cmac_ram_bin_start, ii.size_rom);
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assert(rc == 0);
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#endif
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/* Setup CMAC memory addresses */
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MEMCTRL->CMI_CODE_BASE_REG = (uint32_t)&_binary_cmac_ram_bin_start;
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MEMCTRL->CMI_DATA_BASE_REG = MEMCTRL->CMI_CODE_BASE_REG + ii.offset_data;
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MEMCTRL->CMI_SHARED_BASE_REG = MEMCTRL->CMI_CODE_BASE_REG + ii.offset_shared;
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MEMCTRL->CMI_END_REG = MEMCTRL->CMI_CODE_BASE_REG + ii.size_ram - 1;
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/* Initialize shared memory */
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cmac_shared_init();
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trim = (struct cmac_trim *)&g_cmac_shared_data->trim;
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trim->rfcu_len = da1469x_trimv_group_read(6, trim->rfcu, ARRAY_SIZE(trim->rfcu));
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trim->rfcu_mode1_len = da1469x_trimv_group_read(8, trim->rfcu_mode1, ARRAY_SIZE(trim->rfcu_mode1));
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trim->rfcu_mode2_len = da1469x_trimv_group_read(10, trim->rfcu_mode2, ARRAY_SIZE(trim->rfcu_mode2));
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trim->synth_len = da1469x_trimv_group_read(7, trim->synth, ARRAY_SIZE(trim->synth));
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#if MYNEWT_VAL(CMAC_DEBUG_HOST_PRINT_ENABLE)
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cmac_host_print_trim("rfcu", trim->rfcu, trim->rfcu_len);
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cmac_host_print_trim("rfcu_mode1", trim->rfcu_mode1, trim->rfcu_mode1_len);
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cmac_host_print_trim("rfcu_mode2", trim->rfcu_mode2, trim->rfcu_mode2_len);
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cmac_host_print_trim("synth", trim->synth, trim->synth_len);
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#endif
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/* Release CMAC from reset and sync */
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CRG_TOP->CLK_RADIO_REG &= ~CRG_TOP_CLK_RADIO_REG_CMAC_SYNCH_RESET_Msk;
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cmac_shared_sync();
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da1469x_lpclk_register_cmac_cb(cmac_host_lpclk_cb);
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#if MYNEWT_VAL(CMAC_DEBUG_HOST_PRINT_ENABLE) && MYNEWT_VAL(CMAC_DEBUG_DATA_ENABLE)
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/* Trim values are calculated on RF init, so are valid after synced with CMAC */
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console_printf("[CMAC] Calculated trim_val1: 1=0x%08x 2=0x%08x\n",
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(unsigned)g_cmac_shared_data->debug.trim_val1_tx_1,
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(unsigned)g_cmac_shared_data->debug.trim_val1_tx_2);
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console_printf("[CMAC] Calculated trim_val2: tx=0x%08x rx=0x%08x\n",
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(unsigned)g_cmac_shared_data->debug.trim_val2_tx,
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(unsigned)g_cmac_shared_data->debug.trim_val2_rx);
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#endif
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}
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