/**************************************************************************//**
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* @file clk.c
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* @version V1.00
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* $Date: 16/02/22 9:39a $
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* @brief Panchip series CLK driver source file
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*
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* @note
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* Copyright (C) 2016 Panchip Technology Corp. All rights reserved.
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*****************************************************************************/
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#include "PanSeries.h"
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#include "pan_clk.h"
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#include "pan_sys.h"
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/** @addtogroup Panchip_Device_Driver Panchip Device Driver
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@{
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*/
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/** @addtogroup Panchip_CLK_Driver CLK Driver
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@{
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*/
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/** @addtogroup Panchip_CLK_EXPORTED_FUNCTIONS CLK Exported Functions
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@{
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*/
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/**
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* @brief This function get HCLK frequency. The frequency unit is Hz.
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* @return HCLK frequency
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*/
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uint32_t CLK_GetHCLKFreq(void)
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{
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SystemCoreClockUpdate();
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return SystemCoreClock;
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}
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/**
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* @brief This function get CPU frequency. The frequency unit is Hz.
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* @return CPU frequency
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*/
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uint32_t CLK_GetCPUFreq(void)
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{
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SystemCoreClockUpdate();
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return SystemCoreClock;
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}
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/**
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* @brief This function get APB1 frequency. The frequency unit is Hz.
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* @return HCLK frequency
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*/
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uint32_t CLK_GetPCLK1Freq(void)
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{
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uint32_t ahbclock,apb1_clock;
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uint32_t apb1_div;
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// update ahb clock
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SystemCoreClockUpdate();
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ahbclock = SystemCoreClock;
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apb1_div = (CLK->CLK_TOP_CTRL_3V & CLK_TOPCTL_APB1_DIV_Msk) >> CLK_TOPCTL_APB1_DIV_Pos;
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if(apb1_div)
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apb1_clock = ahbclock / (2 * apb1_div);
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else
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apb1_clock = ahbclock;
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return apb1_clock;
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}
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/**
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* @brief This function get APB2 frequency. The frequency unit is Hz.
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* @return HCLK frequency
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*/
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uint32_t CLK_GetPCLK2Freq(void)
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{
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uint32_t ahbclock,apb2_clock;
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uint32_t apb2_div;
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// update ahb clock
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SystemCoreClockUpdate();
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ahbclock = SystemCoreClock;
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apb2_div = (CLK->CLK_TOP_CTRL_3V & CLK_TOPCTL_APB2_DIV_Msk) >> CLK_TOPCTL_APB2_DIV_Pos;
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if(apb2_div)
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apb2_clock = ahbclock / (2 * apb2_div);
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else
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apb2_clock = ahbclock;
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return apb2_clock;
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}
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/**
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* @brief This function set 16M ref clock source
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* @param[in] u32ClkSrc is HCLK clock source. Including :
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* - \ref CLK_SYS_SRCSEL_RCH
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* - \ref CLK_SYS_SRCSEL_XTH
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* - \ref CLK_SYS_SRCSEL_RCL
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* - \ref CLK_SYS_SRCSEL_XTL
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* - \ref CLK_SYS_SRCSEL_DPLL
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* @return None
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*/
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void CLK_RefClkSrcConfig(uint32_t u32ClkSrc)
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{
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uint32_t tmpreg = CLK->CLK_TOP_CTRL_3V;
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tmpreg &= ~CLK_TOPCTL_SYS_CLK_SEL_Msk;
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switch(u32ClkSrc)
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{
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case CLK_SYS_SRCSEL_RCH:
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CLK->RCH_CTRL |= CLK_RCHCTL_RCH_EN_Msk;
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#ifdef SYNC_3V_REG_MANUALLY
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CLK_Wait3vSyncReady();
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#endif
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CLK_WaitClockReady(u32ClkSrc);
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tmpreg |= CLK_SYS_SRCSEL_RCH;
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break;
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case CLK_SYS_SRCSEL_XTH:
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CLK_XthStartupConfig();
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CLK->XTH_CTRL |= CLK_XTHCTL_XTH_EN_Msk;
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#ifdef SYNC_3V_REG_MANUALLY
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CLK_Wait3vSyncReady();
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#endif
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CLK_WaitClockReady(u32ClkSrc);
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tmpreg |= CLK_SYS_SRCSEL_XTH;
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break;
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case CLK_SYS_SRCSEL_DPLL:
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CLK->DPLL_CTRL |= CLK_DPLLCTL_DPLL_EN_Msk;
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#ifdef SYNC_3V_REG_MANUALLY
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CLK_Wait3vSyncReady();
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#endif
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CLK_WaitClockReady(u32ClkSrc);
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tmpreg |= CLK_SYS_SRCSEL_DPLL;
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break;
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default: break;
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}
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CLK->CLK_TOP_CTRL_3V = tmpreg;
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//wait xtal clock stable
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// CLK_WaitClockReady(u32ClkSrc);
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SystemCoreClockUpdate();
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}
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/**
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* @brief This function set HCLK clock source
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* @param[in] u32ClkSrc is HCLK clock source. Including :
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* - \ref CLK_DPLL_REF_CLKSEL_RCH
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* - \ref CLK_DPLL_REF_CLKSEL_XTH
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* @return None
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*/
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void CLK_SYSCLKConfig(uint32_t u32ClkSrc,uint32_t freq_out)
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{
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if(u32ClkSrc == CLK_DPLL_REF_CLKSEL_RCH){
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CLK->DPLL_CTRL &= ~CLK_DPLLCTL_RCLK_SEL_Msk;
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}
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else if(u32ClkSrc == CLK_DPLL_REF_CLKSEL_XTH){
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CLK->DPLL_CTRL |= CLK_DPLLCTL_RCLK_SEL_Msk;
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}
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/* Config MCU DPLL*/
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CLK_SetDpllOutputFreq(freq_out);
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//enable dpll clock
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CLK->DPLL_CTRL |= CLK_DPLLCTL_DPLL_EN_Msk;
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#ifdef SYNC_3V_REG_MANUALLY
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CLK_Wait3vSyncReady();
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#endif
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CLK_WaitClockReady(CLK_SYS_SRCSEL_DPLL);
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/* Update System Core Clock */
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// SystemCoreClockUpdate();
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}
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/**
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* @brief Enables or disables the AHB peripheral clock.
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* @note After reset, the peripheral clock (used for registers read/write access)
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* is disabled and the application software has to enable this clock before
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* using it.
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* @param CLK_AHBPeriph: specifies the AHB2 peripheral to gates its clock.
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* This parameter can be any combination of the following values:
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* @arg CLK_AHBPeriph_DMAC
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* @arg CLK_AHBPeriph_GPIO
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* @arg CLK_AHBPeriph_SYSTICK
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* @arg CLK_AHBPeriph_APB1
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* @arg CLK_AHBPeriph_APB2
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* @arg CLK_AHBPeriph_AHB
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* @arg CLK_AHBPeriph_RF
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* @arg CLK_AHBPeriph_All
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* @param NewState : new state of the specified peripheral clock.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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void CLK_AHBPeriphClockCmd(uint32_t CLK_AHBPeriph, FunctionalState NewState)
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{
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(NewState != DISABLE)?(CLK->AHB_CLK_CTRL |= CLK_AHBPeriph):(CLK->AHB_CLK_CTRL &= ~CLK_AHBPeriph);
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}
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/**
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* @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
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* @note After reset, the peripheral clock (used for registers read/write access)
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* is disabled and the application software has to enable this clock before
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* using it.
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* @param CLK_APB1Periph: specifies the APB1 peripheral to gates its clock.
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* This parameter can be any combination of the following values:
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* @arg CLK_APB1Periph_I2C0
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* @arg CLK_APB1Periph_SPI0
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* @arg CLK_APB1Periph_UART0
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* @arg CLK_APB1Periph_PWM01
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* @arg CLK_APB1Periph_PWM23
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* @arg CLK_APB1Periph_PWM45
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* @arg CLK_APB1Periph_PWM67
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* @arg CLK_APB1Periph_PWMEN
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* @arg CLK_APB1Periph_ADC
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* @arg CLK_APB1Periph_WDT
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* @arg CLK_APB1Periph_WWDT
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* @arg CLK_APB1Periph_TMR0
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* @arg CLK_APB1Periph_All
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* @param NewState : new state of the specified peripheral clock.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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void CLK_APB1PeriphClockCmd(uint32_t CLK_APB1Periph, FunctionalState NewState)
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{
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(NewState != DISABLE)?(CLK->APB1_CLK_CTRL |= CLK_APB1Periph):(CLK->APB1_CLK_CTRL &= ~CLK_APB1Periph);
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}
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/**
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* @brief Enables or disables the High Speed APB (APB2) peripheral clock.
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* @note After reset, the peripheral clock (used for registers read/write access)
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* is disabled and the application software has to enable this clock before
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* using it.
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* @param CLK_APB2Periph: specifies the APB2 peripheral to gates its clock.
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* This parameter can be any combination of the following values:
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* @arg CLK_APB2Periph_SPI1
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* @arg CLK_APB2Periph_UART1
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* @arg CLK_APB2Periph_TMR1
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* @arg CLK_APB2Periph_TMR2
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* @arg CLK_APB2Periph_All
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* @param NewState: new state of the specified peripheral clock.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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void CLK_APB2PeriphClockCmd(uint32_t CLK_APB2Periph, FunctionalState NewState)
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{
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(NewState != DISABLE)?(CLK->APB2_CLK_CTRL |= CLK_APB2Periph):(CLK->APB2_CLK_CTRL &= ~CLK_APB2Periph);
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}
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/**
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* @brief This function check selected clock source status
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* @param[in] u32ClkMask is selected clock source. Including
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* - \ref CLK_RCL_SELECT
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* - \ref CLK_RCH_SELECT
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* - \ref CLK_XTL_SELECT
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* - \ref CLK_XTH_SELECT
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* - \ref CLK_DPLL_SELECT
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* @return 0 clock is not stable
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* 1 clock is stable
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*
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* @details To wait for clock ready by specified CLKSTATUS bit or timeout (~5ms)
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*/
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uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
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{
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int32_t i32TimeOutCnt = 2160000;
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uint32_t u32ClkTmp = 0;
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while(1)
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{
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switch(u32ClkMask){
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case CLK_SYS_SRCSEL_RCH : u32ClkTmp = CLK->RCH_CTRL; break;
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case CLK_SYS_SRCSEL_XTH : u32ClkTmp = CLK->XTH_CTRL; break;
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// case CLK_SYS_SRCSEL_RCL : u32ClkTmp = CLK->RCL_CTRL_3V; break;
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// case CLK_SYS_SRCSEL_XTL : u32ClkTmp = CLK->XTL_CTRL_3V; break;
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case CLK_SYS_SRCSEL_DPLL: u32ClkTmp = CLK->DPLL_CTRL; break;
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default: break;
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}
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if((u32ClkTmp & CLK_STABLE_STATUS_Msk) != CLK_STABLE_STATUS_Msk){
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if(i32TimeOutCnt-- <= 0)
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return 0;
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}else{
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break;
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}
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}
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return 1;
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}
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/**
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* @brief This function wait sync 3v clock locale stable
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* @param[in] none
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* @return 0 clock sync is not stable
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* 1 clock sync is stable
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*
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* @details To wait for clock ready by specified CLKSTATUS bit or timeout (~5ms)
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*/
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uint32_t CLK_Wait3vSyncReady(void)
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{
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// Trigger manual 3v sync
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ANA->LP_REG_SYNC |= ANAC_LP_REG_SYNC_3V_Msk | ANAC_LP_REG_SYNC_3V_TRG_Msk;
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// Force delay 60us+ (should be larger than 31.25us)
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SYS_delay_10nop(200);
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return 1;
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}
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/**
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* @brief This function wait sync 3v clock locale stable by hardware
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* @param[in] none
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* @return none
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*/
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void CLK_Set3vSyncAuto(void)
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{
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ANA->LP_REG_SYNC |= ANAC_LP_REG_SYNC_3V_Msk;
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}
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/**
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* @brief This API is used to select wdt clock source
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* @param[in] u32clksel wdt clock selection. Could be
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* - \ref CLK_APB1_WDTSEL_MILLI_PULSE, \ref CLK_APB1_WDTSEL_RCL32K
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* @return none
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* @note This API is only used to select wdt clock source
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*/
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void CLK_SetWdtClkSrc(uint32_t u32clksel)
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{
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if (u32clksel == CLK_APB1_WDTSEL_MILLI_PULSE) {
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// Enable Mili Pulse Clock if WDT selects it
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u32clksel |= CLK_APB1Periph_MILI_CLK;
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}
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CLK->APB1_CLK_CTRL = (CLK->APB1_CLK_CTRL & ~CLK_APB1CLK_WDTSRC_SEL_Msk) | u32clksel;
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}
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/**
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* @brief This API is used to select wwdt clock source
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* @param[in] wwdt The base address of wwdt module
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* @param[in] u32clksel wwdt clock selection. Could be
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* - \ref CLK_APB1_WDTSEL_MILLI_PULSE, \ref CLK_APB1_WDTSEL_RCL32K
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* @return none
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* @note This API is only used to select wwdt clock source
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*/
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void CLK_SetWwdtClkSrc(uint32_t u32clksel)
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{
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if (u32clksel == CLK_APB1_WWDTSEL_MILLI_PULSE) {
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// Enable Mili Pulse Clock if WWDT selects it
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u32clksel |= CLK_APB1Periph_MILI_CLK;
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}
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CLK->APB1_CLK_CTRL = (CLK->APB1_CLK_CTRL & ~CLK_APB1CLK_WWDTSRC_SEL_Msk) | u32clksel;
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}
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/**
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* @brief This API is used to SELECT timer clock source
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* @param[in] timer The base address of Timer module
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* @param[in] u32clksel timer clock selection. Could be
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* - \ref CLK_APB_TMR0SEL_APB1CLK, \ref CLK_APB_TMR0SEL_LIRC,\ref CLK_APB_TMR0SEL_TM0
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* - \ref CLK_APB_TMR1SEL_APB2CLK, \ref CLK_APB_TMR1SEL_LIRC,\ref CLK_APB_TMR0SEL_TM1
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* - \ref CLK_APB_TMR2SEL_APB2CLK, \ref CLK_APB_TMR2SEL_LIRC,\ref CLK_APB_TMR0SEL_TM2
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* @return none
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* @note This API is only used to select timer clock source
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*/
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void CLK_SetTmrClkSrc(TIMER_T *timer, uint32_t u32clksel)
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{
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if(timer == TIMER0) {
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CLK->APB1_CLK_CTRL = (CLK->APB1_CLK_CTRL & ~CLK_APB1CLK_TMR0SRC_SEL_Msk) | u32clksel;
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}
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else if(timer == TIMER1){
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CLK->APB2_CLK_CTRL = (CLK->APB2_CLK_CTRL & ~CLK_APB2CLK_TMR1SRC_SEL_Msk) | u32clksel;
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}
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else if(timer == TIMER2){
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CLK->APB2_CLK_CTRL = (CLK->APB2_CLK_CTRL & ~CLK_APB2CLK_TMR2SRC_SEL_Msk) | u32clksel;
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}
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}
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/**
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* @brief This API is used to select pwm counting clock source
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* @param[in] u32ChNum pwm channel. Could be 0 ~ 7
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* @param[in] u32clksel pwm counting clock selection. Could be
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* - \ref CLK_APB1_PWM_CH01_SEL_APB, \ref CLK_APB1_PWM_CH01_SEL_CLK32K
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* - \ref CLK_APB1_PWM_CH23_SEL_APB, \ref CLK_APB1_PWM_CH23_SEL_CLK32K
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* - \ref CLK_APB1_PWM_CH45_SEL_APB, \ref CLK_APB1_PWM_CH45_SEL_CLK32K
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* - \ref CLK_APB1_PWM_CH67_SEL_APB, \ref CLK_APB1_PWM_CH67_SEL_CLK32K
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* @return none
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* @note PWM channel 0/1, 2/3, 4/5, 6/7 share same clock source.
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*/
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void CLK_SetPwmClkSrc(uint32_t u32ChNum, uint32_t u32clksel)
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{
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switch (u32ChNum) {
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case 0:
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case 1:
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CLK->APB1_CLK_CTRL = (CLK->APB1_CLK_CTRL & ~CLK_APB1CLK_PWM01_CLK_SEL_Msk) | u32clksel;
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break;
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case 2:
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case 3:
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CLK->APB1_CLK_CTRL = (CLK->APB1_CLK_CTRL & ~CLK_APB1CLK_PWM23_CLK_SEL_Msk) | u32clksel;
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break;
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case 4:
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case 5:
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CLK->APB1_CLK_CTRL = (CLK->APB1_CLK_CTRL & ~CLK_APB1CLK_PWM45_CLK_SEL_Msk) | u32clksel;
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break;
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case 6:
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case 7:
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CLK->APB1_CLK_CTRL = (CLK->APB1_CLK_CTRL & ~CLK_APB1CLK_PWM67_CLK_SEL_Msk) | u32clksel;
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break;
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default:
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break;
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}
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}
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uint32_t CLK_GetPeripheralFreq(void * Peripheral)
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{
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uint8_t u8ApbDiv = 0;
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uint32_t u32AhbClk,u32Pclk;
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/*get system clock frequency*/
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u32AhbClk = CLK_GetHCLKFreq();
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if((I2C0 == (I2C_T *) Peripheral)
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||(UART0 == (UART_T *) Peripheral)
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||(SPI0 == (SPI_T *) Peripheral)
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||(TIMER0 == (TIMER_T *) Peripheral))
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{
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u8ApbDiv = (CLK->CLK_TOP_CTRL_3V & CLK_TOPCTL_APB1_DIV_Msk) >> CLK_TOPCTL_APB1_DIV_Pos;
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}
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else if((SPI1 == (SPI_T *) Peripheral)
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||(UART1 == (UART_T *) Peripheral)
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||(TIMER1 == (TIMER_T *) Peripheral)
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||(TIMER2 == (TIMER_T *) Peripheral))
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u8ApbDiv = (CLK->CLK_TOP_CTRL_3V & CLK_TOPCTL_APB2_DIV_Msk) >> CLK_TOPCTL_APB2_DIV_Pos;
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if(u8ApbDiv)
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u32Pclk = u32AhbClk / (2 * u8ApbDiv);
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else
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u32Pclk = u32AhbClk;
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return u32Pclk;
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}
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/**
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* @brief This function clear the selected system reset source
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* @param[in] u32Src is system reset source. Including:
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* - \ref CLK_RSTSTS_CHIPRF_Msk
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* - \ref CLK_RSTSTS_PINRF_Msk
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* - \ref CLK_RSTSTS_WDTRF_Msk
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* - \ref CLK_RSTSTS_LVRRF_Msk
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* - \ref CLK_RSTSTS_BODRF_Msk
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* - \ref CLK_RSTSTS_SYSRF_Msk
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* - \ref CLK_RSTSTS_PORRF_Msk
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* - \ref CLK_RSTSTS_CPURF_Msk
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* @return None
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*/
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void CLK_ClearResetSrc(uint32_t u32Src)
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{
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CLK->RSTSTS |= u32Src;
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}
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/**
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* @brief This function get the system reset source register value
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* @return Reset source
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*/
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uint32_t CLK_GetResetSrc(void)
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{
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return (CLK->RSTSTS);
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}
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/**
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* @brief This function reset chip.
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* @details Setting this bit will reset the whole chip, including cpu core and all peripherals,
|
* and this bit will automatically return to 0. The CHIPRST is the same as the POR reset,
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* all the chip controllers is reset and the chip settings from flash are also reload.
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* @note This bit is write protected. Do SYS_UnlockReg() before setting this bit.
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* @return None
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*/
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void CLK_ResetChip(void)
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{
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CLK->IPRST0 |= CLK_IPRST0_CHIPRST_Msk;
|
while (1) {
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/* Busy wait until SoC reset */
|
}
|
}
|
|
/**
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* @brief This function reset system from Flash Mode to ROM Mode (with Panchip USB DFU Enabled).
|
* @details The FTOR reset is used to reset system and switch from flash mode to rom mode. If
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* this bit is set, reset range is completely consistent with RCCRESETREQ (sys reset),
|
* and this bit will automatically return to 0.
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* @note This bit is write protected. Do SYS_UnlockReg() before setting this bit.
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* @return None
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*/
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void CLK_ResetSystemToRomMode(void)
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{
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CLK->IPRST0 |= CLK_IPRST0_FTORRST_Msk;
|
while (1) {
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/* Busy wait until SoC reset */
|
}
|
}
|
|
/**
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* @brief This function reset selected modules.
|
* @param[in] u32ModuleIndex is module index. Including :
|
* - \ref DMA_RST
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* - \ref LL_RST
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* - \ref EFUSE_RST
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* - \ref USB_RST
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* - \ref MDMSTB_RST
|
* - \ref MDM_RST
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* - \ref I2C0_RST
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* - \ref SPI0_RST
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* - \ref SPI1_RST
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* - \ref UART0_RST
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* - \ref UART1_RST
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* - \ref PWM0_RST
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* - \ref ADC_RST
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* - \ref WDT_RST
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* - \ref WWDT_RST
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* - \ref TMR0_RST
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* - \ref TMR1_RST
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* - \ref TMR2_RST
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* - \ref GPIO_RST
|
* - \ref CLKTRIM_RST
|
* @return None
|
*/
|
void CLK_ResetModule(uint32_t u32ModuleIndex)
|
{
|
*(volatile uint32_t *)((uint32_t)&(CLK->IPRST0) + (u32ModuleIndex>>24)) |= 1<<(u32ModuleIndex & 0x00ffffff);
|
*(volatile uint32_t *)((uint32_t)&(CLK->IPRST0) + (u32ModuleIndex>>24)) &= ~(1<<(u32ModuleIndex & 0x00ffffff));
|
}
|
|
/**
|
* @brief This function configure BOD function.
|
* Configure BOD reset or interrupt mode and set Brown-out voltage level.
|
* Enable Brown-out function
|
* @param[in] i32Mode is reset or interrupt mode. Including :
|
* - \ref CLK_BODCTL_BOD_INT_EN
|
* - \ref CLK_BODCTL_BOD_RST_EN
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* @param[in] u32BODLevel is Brown-out voltage level. Including :
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* - \ref CLK_BODCTL_BODSEL_1_75V
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* - \ref CLK_BODCTL_BODSEL_1_95V
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* - \ref CLK_BODCTL_BODSEL_2_15V
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* - \ref CLK_BODCTL_BODSEL_2_35V
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* - \ref CLK_BODCTL_BODSEL_2_55V
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* - \ref CLK_BODCTL_BODSEL_2_75V
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* - \ref CLK_BODCTL_BODSEL_2_95V
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* @note This function operates the 3v-always-on register, please ensure the auto-3v-sync mechanism is on, otherwise
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* you need to do the high-voltage-sync manually.
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* @return None
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*/
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void CLK_ConfigureBOD(int32_t i32Mode, uint32_t u32BODLevel)
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{
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uint32_t tmpreg = CLK->BODCTL_3V;
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tmpreg = (tmpreg & ~CLK_BODCTL_BODRSTEN_Msk_3v) | i32Mode;
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tmpreg = (tmpreg & ~CLK_BODCTL_BODSEL_Msk_3v) | u32BODLevel;
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CLK->BODCTL_3V = tmpreg;
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}
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/**
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* @brief This function enable BOD function.
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* @note This function operates the 3v-always-on register, please ensure the auto-3v-sync mechanism is on, otherwise
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* you need to do the high-voltage-sync manually.
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* @return None
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*/
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void CLK_EnableBOD(void)
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{
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CLK->BODCTL_3V |= CLK_BODCTL_BODEN_Msk_3v;
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}
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/**
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* @brief This function disable BOD function.
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* @note This function operates the 3v-always-on register, please ensure the auto-3v-sync mechanism is on, otherwise
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* you need to do the high-voltage-sync manually.
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* @return None
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*/
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void CLK_DisableBOD(void)
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{
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CLK->BODCTL_3V &= ~CLK_BODCTL_BODEN_Msk_3v;
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}
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/**
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* @brief This function get Brown-out detector output status
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* @return 0: System voltage is higher than BOD_SEL setting or BODEN is 0.
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* 1: System voltage is lower than BOD_SEL setting.
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* @note If the BODEN is 0, this function always return 0.
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*/
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uint32_t CLK_GetBODStatus(void)
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{
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return (CLK->BODCTL_3V & CLK_BODCTL_BODOUT_Msk) ? 1 : 0;
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}
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/**
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* @brief Get Brown-out detector interrupt flag
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* @retval 0 Brown-out detect interrupt flag is not set.
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* @retval 1 Brown-out detect interrupt flag is set.
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*/
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uint32_t CLK_GetBODIntFlag(void)
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{
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return (CLK->BODCTL_3V & CLK_BODCTL_BODIF_Msk) ? 1 : 0;
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}
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/**
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* @brief Clear Brown-out detector interrupt flag
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* @param None
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* @return None
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*/
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void CLK_ClearBODIntFlag(void)
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{
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CLK->BODCTL_3V |= CLK_BODCTL_BODIF_Msk;
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}
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/**
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* @brief This function set BOD debounce time.
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* @param[in] u32BodDBTime is BOD debounce time in slow clock cycles. Including:
|
* - \ref CLK_BLDBCTL_BODDBSEL_2POW0
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* - \ref CLK_BLDBCTL_BODDBSEL_2POW1
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* - \ref CLK_BLDBCTL_BODDBSEL_2POW2
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* - \ref CLK_BLDBCTL_BODDBSEL_2POW3
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* - \ref CLK_BLDBCTL_BODDBSEL_2POW4
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* - \ref CLK_BLDBCTL_BODDBSEL_2POW5
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* @note This function operates the 3v-always-on register, please ensure the auto-3v-sync mechanism is on, otherwise
|
* you need to do the high-voltage-sync manually.
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* @return None
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*/
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void CLK_SetBODDebounceTime(uint32_t u32BodDBTime)
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{
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CLK->BLDBCTL_3V = (CLK->BLDBCTL_3V & ~CLK_BLDBCTL_BODDB_SEL_Msk_3v) | u32BodDBTime;
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}
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/**
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* @brief This function enable LVR function.
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* @note This function operates the 3v-always-on register, please ensure the auto-3v-sync mechanism is on, otherwise
|
* you need to do the high-voltage-sync manually.
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* @return None
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*/
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void CLK_EnableLVR(void)
|
{
|
CLK->BODCTL_3V |= CLK_BODCTL_LVREN_Msk_3v;
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}
|
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/**
|
* @brief This function disable LVR function.
|
* @note This function operates the 3v-always-on register, please ensure the auto-3v-sync mechanism is on, otherwise
|
* you need to do the high-voltage-sync manually.
|
* @return None
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*/
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void CLK_DisableLVR(void)
|
{
|
CLK->BODCTL_3V &= ~CLK_BODCTL_LVREN_Msk_3v;
|
}
|
|
/**
|
* @brief This function set LVR debounce time.
|
* @param[in] u32LvrDBTime is LVR debounce time in slow clock cycles. Including:
|
* - \ref CLK_BLDBCTL_LVRDBSEL_2POW0
|
* - \ref CLK_BLDBCTL_LVRDBSEL_2POW1
|
* - \ref CLK_BLDBCTL_LVRDBSEL_2POW2
|
* - \ref CLK_BLDBCTL_LVRDBSEL_2POW3
|
* - \ref CLK_BLDBCTL_LVRDBSEL_2POW4
|
* - \ref CLK_BLDBCTL_LVRDBSEL_2POW5
|
* @note This function operates the 3v-always-on register, please ensure the auto-3v-sync mechanism is on, otherwise
|
* you need to do the high-voltage-sync manually.
|
* @return None
|
*/
|
void CLK_SetLVRDebounceTime(uint32_t u32LvrDBTime)
|
{
|
CLK->BLDBCTL_3V = (CLK->BLDBCTL_3V & ~CLK_BLDBCTL_LVRDB_SEL_Msk_3v) | u32LvrDBTime;
|
}
|
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/*@}*/ /* end of group Panchip_CLK_EXPORTED_FUNCTIONS */
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/*@}*/ /* end of group Panchip_CLK_Driver */
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/*@}*/ /* end of group Panchip_Device_Driver */
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/*** (C) COPYRIGHT 2016 Panchip Technology Corp. ***/
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