/**************************************************************************//**
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* @file retarget.c
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* @version V1.00
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* $Revision: 2 $
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* $Date: 15/02/06 7:41p $
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* @brief PN020 series retarget source file
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*
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* @note
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* Copyright (C) 2016 Panchip Technology Corp. All rights reserved.
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*****************************************************************************/
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#include <stdio.h>
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#include "PanSeries.h"
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#define UART0_ENABLE (1)
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#if defined ( __CC_ARM )
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#if (__ARMCC_VERSION < 400000)
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#else
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/* Insist on keeping widthprec, to avoid X propagation by benign code in C-lib */
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#pragma import _printf_widthprec
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#endif
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#endif
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//#define DEBUG_ENABLE_UART1
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#ifdef DEBUG_ENABLE_UART1
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#define DEBUG_PORT UART1
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#else
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#define DEBUG_PORT UART0
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#endif
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/* Un-comment this line to disable all printf and getchar. getchar() will always return 0x00*/
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//#define DISABLE_UART
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/*---------------------------------------------------------------------------------------------------------*/
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/* Global variables */
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/*---------------------------------------------------------------------------------------------------------*/
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//#if !(defined(__ICCARM__) && (__VER__ >= 6010000))
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//struct __FILE { int handle; /* Add whatever you need here */ };
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//#endif
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//FILE __stdout;
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//FILE __stdin;
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enum { r0, r1, r2, r3, r12, lr, pc, psr};
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void stackDump(uint32_t stack[])
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{
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printf("r0 = 0x%x\r\n", stack[r0]);
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printf("r1 = 0x%x\r\n", stack[r1]);
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printf("r2 = 0x%x\r\n", stack[r2]);
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printf("r3 = 0x%x\r\n", stack[r3]);
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printf("r12 = 0x%x\r\n", stack[r12]);
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printf("lr = 0x%x\r\n", stack[lr]);
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printf("pc = 0x%x\r\n", stack[pc]);
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printf("psr = 0x%x\r\n", stack[psr]);
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}
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void Hard_Fault_Handler(uint32_t stack[])
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{
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printf("In Hard Fault Handler\r\n");
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stackDump(stack);
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//Chip Reset
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//SYS_UnlockReg();
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//SYS->IPRSTC1 |= SYS_IPRSTC1_CHIP_RST_Msk;
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while(1);
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}
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#if defined(DEBUG_ENABLE_SEMIHOST)
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/* The static buffer is used to speed up the semihost */
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static char g_buf[16];
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static char g_buf_len = 0;
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# if defined(__ICCARM__)
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/**
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* @brief This HardFault handler is implemented to support semihost
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*
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* @param None
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*
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* @returns None
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*
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* @details This function is implement to support semihost message print.
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*
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*/
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void HardFault_Handler(void)
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{
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asm("MOV R0, lr \n"
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"LSLS R0, #29 \n" //; Check bit 2
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"BMI SP_is_PSP \n" //; previous stack is PSP
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"MRS R0, MSP \n" //; previous stack is MSP, read MSP
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"B SP_Read_Ready \n"
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"SP_is_PSP: \n"
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"MRS R0, PSP \n" //; Read PSP
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"SP_Read_Ready: \n"
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"LDR R1, [R0, #24] \n" //; Get previous PC
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"LDRH R3, [R1] \n" //; Get instruction
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"LDR R2, [pc, #8] \n" //; The special BKPT instruction
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"CMP R3, R2 \n" //; Test if the instruction at previous PC is BKPT
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"BNE HardFault_Handler_Ret\n" //; Not BKPT
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"ADDS R1, #4 \n" //; Skip BKPT and next line
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"STR R1, [R0, #24] \n" //; Save previous PC
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"BX lr \n" //; Return
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"DCD 0xBEAB \n" //; BKPT instruction code
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"HardFault_Handler_Ret:\n"
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"MOVS r0, #4 \n"
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"MOV r1, LR \n"
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"TST r0, r1 \n"
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"BEQ Stack_Use_MSP \n"
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"MRS R0, PSP \n" //; stack use PSP
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"B Get_LR_and_Branch \n"
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"Stack_Use_MSP: \n"
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"MRS R0, MSP \n" //; stack use MSP
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"Get_LR_and_Branch: \n"
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"MOV R1, LR \n" //; LR current value
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"B Hard_Fault_Handler \n"
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);
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while(1);
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}
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/**
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*
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* @brief The function to process semihosted command
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* @param[in] n32In_R0 : semihost register 0
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* @param[in] n32In_R1 : semihost register 1
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* @param[out] pn32Out_R0: semihost register 0
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* @retval 0: No ICE debug
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* @retval 1: ICE debug
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*
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*/
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int32_t SH_DoCommand(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0)
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{
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asm("BKPT 0xAB \n" //; This instruction will cause ICE trap or system HardFault
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"B SH_ICE \n"
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"SH_HardFault: \n" //; Captured by HardFault
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"MOVS R0, #0 \n" //; Set return value to 0
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"BX lr \n" //; Return
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"SH_ICE: \n" //; Captured by ICE
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"CMP R2, #0 \n"
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"BEQ SH_End \n"
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"STR R0, [R2]\n" //; Save the return value to *pn32Out_R0
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"SH_End: \n");
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return 1; //; Return 1 when it is trap by ICE
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}
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# else
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/**
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* @brief This HardFault handler is implemented to support semihost
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*
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* @param None
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*
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* @returns None
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*
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* @details This function is implement to support semihost message print.
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*
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*/
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__asm int32_t HardFault_Handler(void)
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{
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MOV R0, LR
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LSLS R0, #29 //; Check bit 2
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BMI SP_is_PSP //; previous stack is PSP
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MRS R0, MSP //; previous stack is MSP, read MSP
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B SP_Read_Ready
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SP_is_PSP
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MRS R0, PSP //; Read PSP
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SP_Read_Ready
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LDR R1, [R0, #24] //; Get previous PC
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LDRH R3, [R1] //; Get instruction
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LDR R2, =0xBEAB //; The special BKPT instruction
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CMP R3, R2 //; Test if the instruction at previous PC is BKPT
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BNE HardFault_Handler_Ret //; Not BKPT
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ADDS R1, #4 //; Skip BKPT and next line
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STR R1, [R0, #24] //; Save previous PC
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BX LR //; Return
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HardFault_Handler_Ret
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/* TODO: Implement your own hard fault handler here. */
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MOVS r0, #4
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MOV r1, LR
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TST r0, r1
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BEQ Stack_Use_MSP
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MRS R0, PSP ;stack use PSP
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B Get_LR_and_Branch
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Stack_Use_MSP
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MRS R0, MSP ; stack use MSP
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Get_LR_and_Branch
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MOV R1, LR ; LR current value
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LDR R2,=__cpp(Hard_Fault_Handler)
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BX R2
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B .
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ALIGN
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}
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/**
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*
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* @brief The function to process semihosted command
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* @param[in] n32In_R0 : semihost register 0
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* @param[in] n32In_R1 : semihost register 1
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* @param[out] pn32Out_R0: semihost register 0
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* @retval 0: No ICE debug
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* @retval 1: ICE debug
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*
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*/
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__asm int32_t SH_DoCommand(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0)
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{
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BKPT 0xAB //; Wait ICE or HardFault
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//; ICE will step over BKPT directly
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//; HardFault will step BKPT and the next line
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B SH_ICE
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SH_HardFault //; Captured by HardFault
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MOVS R0, #0 //; Set return value to 0
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BX lr //; Return
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SH_ICE //; Captured by ICE
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//; Save return value
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CMP R2, #0
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BEQ SH_End
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STR R0, [R2] //; Save the return value to *pn32Out_R0
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SH_End
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MOVS R0, #1 //; Set return value to 1
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BX lr //; Return
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}
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#endif
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#else
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# if defined(__ICCARM__)
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/**
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* @brief This HardFault handler is implemented to show r0, r1, r2, r3, r12, lr, pc, psr
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*
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* @param None
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*
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* @returns None
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*
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* @details This function is implement to print r0, r1, r2, r3, r12, lr, pc, psr.
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*
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*/
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void HardFault_Handler(void)
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{
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asm("MOVS r0, #4 \n"
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"MOV r1, LR \n"
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"TST r0, r1 \n"
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"BEQ Stack_Use_MSP \n"
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"MRS R0, PSP \n" //; stack use PSP
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"B Get_LR_and_Branch \n"
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"Stack_Use_MSP: \n"
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"MRS R0, MSP \n" //; stack use MSP
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"Get_LR_and_Branch: \n"
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"MOV R1, LR \n" //; LR current value
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"B Hard_Fault_Handler \n"
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);
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while(1);
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}
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# else
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/**
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* @brief This HardFault handler is implemented to show r0, r1, r2, r3, r12, lr, pc, psr
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*
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* @param None
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*
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* @returns None
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*
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* @details This function is implement to print r0, r1, r2, r3, r12, lr, pc, psr
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*
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*/
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// #if !(defined(__ICCARM__) && (__VER__ >= 6100100))
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#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
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void HardFault_Handler(void)
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{
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__asm("MOVS r0, #4 \n"
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"MOV r1, LR \n"
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"TST r0, r1 \n"
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"BEQ Stack_Use_MSP \n"
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"MRS R0, PSP \n" //; stack use PSP
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"B Get_LR_and_Branch \n"
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"Stack_Use_MSP: \n"
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"MRS R0, MSP \n" //; stack use MSP
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"Get_LR_and_Branch: \n"
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"MOV R1, LR \n" //; LR current value
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"B Hard_Fault_Handler \n"
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);
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}
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#else
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__asm int32_t HardFault_Handler(void)
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{
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MOVS r0, #4
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MOV r1, LR
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TST r0, r1
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BEQ Stack_Use_MSP
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MRS R0, PSP ;stack use PSP
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B Get_LR_and_Branch
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Stack_Use_MSP
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MRS R0, MSP ; stack use MSP
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Get_LR_and_Branch
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MOV R1, LR ; LR current value
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LDR R2,=__cpp(Hard_Fault_Handler)
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BX R2
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}
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#endif
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#endif
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#endif
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/**
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* @brief Write a char to UART.
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* @param ch The character sent to UART.
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* @return None
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*/
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void SendChar_ToUART(int ch)
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{
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#ifndef DISABLE_UART
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#if (UART0_ENABLE)
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while(UART_IsTxFifoFull(DEBUG_PORT));
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DEBUG_PORT->RBR_THR_DLL = ch;
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#endif //UART0_ENABLE
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#endif //DISABLE_UART
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}
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/**
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* @brief Write a char to debug console.
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* @param ch The character sent to debug console
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* @return None
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*/
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__WEAK void SendChar(int ch)
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{
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#if defined(DEBUG_ENABLE_SEMIHOST)
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g_buf[g_buf_len++] = ch;
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g_buf[g_buf_len] = '\0';
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if(g_buf_len + 1 >= sizeof(g_buf) || ch == '\n' || ch == '\0')
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{
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/* Send the char */
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if(SH_DoCommand(0x04, (int)g_buf, NULL) != 0)
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{
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g_buf_len = 0;
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return;
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}
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else
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{
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int i;
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for(i=0;i<g_buf_len;i++)
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SendChar_ToUART(g_buf[i]);
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g_buf_len = 0;
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}
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}
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#else
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SendChar_ToUART(ch);
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#endif
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}
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/**
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* @brief Read a char from debug console.
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* @param None
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* @return Received character from debug console
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* @note This API waits until UART debug port or semihost input a character
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*/
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__WEAK char GetChar(void)
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{
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#if defined(DEBUG_ENABLE_SEMIHOST)
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#if defined ( __CC_ARM )
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int nRet;
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while(SH_DoCommand(0x101, 0, &nRet) != 0)
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{
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if(nRet != 0)
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{
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SH_DoCommand(0x07, 0, &nRet);
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return (char)nRet;
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}
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}
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#else
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int nRet;
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while(SH_DoCommand(0x7, 0, &nRet) != 0)
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{
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if(nRet != 0)
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return (char)nRet;
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}
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#endif
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#endif
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#ifndef DISABLE_UART
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while (1)
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{
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if((DEBUG_PORT->USR & UART_USR_RFNE_Msk))
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{
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return (DEBUG_PORT->RBR_THR_DLL);
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}
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}
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#else
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return(0);
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#endif
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}
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/**
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* @brief Check whether UART receive FIFO is empty or not.
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* @param None
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* @return UART Rx FIFO empty status
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* @retval 1 Indicates at least one character is available in UART Rx FIFO
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* @retval 0 UART Rx FIFO is empty
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*/
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int kbhit(void)
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{
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#ifndef DISABLE_UART
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return (DEBUG_PORT->USR & UART_USR_RFNE_Msk);
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#else
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return(0);
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#endif
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}
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/**
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* @brief Check whether UART transmit FIFO is empty or not.
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* @param None
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* @return UART Tx FIFO empty status
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* @retval 1 UART Tx FIFO is empty
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* @retval 0 UART Tx FIFO is not empty
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*/
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int IsDebugFifoEmpty(void)
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{
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#ifndef DISABLE_UART
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return (DEBUG_PORT->USR & UART_USR_TFE_Msk) ? 1 : 0;
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#else
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return(1);
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#endif
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}
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/*---------------------------------------------------------------------------------------------------------*/
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/* C library retargetting */
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/*---------------------------------------------------------------------------------------------------------*/
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void _ttywrch(int ch)
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{
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SendChar(ch);
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return;
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}
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int fputc(int ch, FILE *f)
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{
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SendChar(ch);
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return ch;
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}
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int fgetc(FILE *f) {
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return (GetChar());
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}
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int ferror(FILE *f) {
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return EOF;
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}
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#ifdef DEBUG_ENABLE_SEMIHOST
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# ifdef __ICCARM__
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void __exit(int return_code) {
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/* Check if link with ICE */
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if(SH_DoCommand(0x18, 0x20026, NULL) == 0)
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{
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/* Make sure all message is print out */
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while(IsDebugFifoEmpty() == 0);
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}
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label: goto label; /* endless loop */
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}
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# else
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void _sys_exit(int return_code) {
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/* Check if link with ICE */
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if(SH_DoCommand(0x18, 0x20026, NULL) == 0)
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{
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/* Make sure all message is print out */
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while(IsDebugFifoEmpty() == 0);
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}
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label: goto label; /* endless loop */
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}
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# endif
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#endif
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/*** (C) COPYRIGHT 2016 Panchip Technology Corp. ***/
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