/**************************************************************************//**
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* @file system_PanSeries.c
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* @version V1.00
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* @brief Panchip series SoC system clock init code and assert handler
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* @note
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* Copyright (C) 2020 Panchip Technology Corp. All rights reserved.
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*****************************************************************************/
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#include "PanSeries.h"
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#include "pan_clk.h"
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#include "pan_fmc.h"
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#include "pan_sys.h"
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#include "pan_efuse.h"
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/*
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* Global variables defined here should be used after RAM RW/ZI data init.
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*/
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uint32_t SystemCoreClock;
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bool isFtDataValid = true;
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float SocTemperature = 22; /* Treat default SoC temperature as 22 C */
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/*
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* Global variables here to be used in SystemInit() function should reside
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* in flash, since RAM RW/ZI data are not initialized at that time.
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*/
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const uint32_t PanFlashLineMode = CONFIG_FLASH_LINE_MODE;
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const bool PanFlashEnhanceEnable = false;
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uint32_t vec_remap_adr = 0x20007000;
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/**
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* @brief Setup the microcontroller system
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* Initialize the Embedded Flash Interface and other modules which should
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* be init in early boot stage.
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* @param None
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* @retval None
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*/
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void SystemInit(void)
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{
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ANA->CPU_ADDR_REMAP_CTRL =0;
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// Speed up flash clock from default 16MHz to 32MHz
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CLK_SetFlashClkDiv(CLK_FLASH_CLKDIV_1);
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// Switch flash to 4-Line mode
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FMC_SetFlashMode(FLCTL, PanFlashLineMode, PanFlashEnhanceEnable);
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// Init I-Cache
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InitIcache(FLCTL, PanFlashLineMode);
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#ifndef SYNC_3V_REG_MANUALLY
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// Auto sync value to 3v registers
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// Note that this auto-sync mechanism works for all registers needed
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// doing 3v sync except Px_DINOFF regs for P46/P47/P56 in GPIO module.
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CLK_Set3vSyncAuto();
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#endif
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#if CONFIG_SOC_DCDC_PAN1070
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uint32_t tmpreg = ANA->LP_BUCK_3V;
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// Increase buck default output voltage
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tmpreg &= (~ANAC_BUCK_VOUT_Msk_3v);
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tmpreg |= 0x6 << ANAC_BUCK_VOUT_Pos_3v;
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// Enable DCDC-LDO auto switching when SoC vbat voltage drop off to about 1.8v and then uprise again
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tmpreg |= ANAC_BUCK_VOL_LIMIT_EN_Msk_3v;
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// Enable buck output
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tmpreg &= ~0x1;
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ANA->LP_BUCK_3V = tmpreg;
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#endif
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// Disable eFuse VDD for power saving purpose
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EFUSE->EF_VDD = 0;
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// Clear the internal XOCAP trim of XTH and we prefer to use the external capacitor instead
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CLK->XTH_CTRL &= ~CLK_XTHCTL_XO_CAP_SEL_Msk;
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// Disable SW pull-down res to avoid high power leakage in low temperature
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ANA->LP_SW &= ~ANAC_HP_DVDD_PD_Msk;
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// Forcely reset GPIO debounce clk source to AHB before configure db cycle
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GPIO_DB->DBCTL &= ~GP_DBCTL_DBCLKSRC_Msk;
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// Other optimization configs (From task 4372)
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ANA->LP_PTAT_POLY |= ANAC_PTAT_TMP_TRIM_Msk;
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CLK->XTL_CTRL_3V = (CLK->XTL_CTRL_3V & ~CLK_XTLCTL_CORE_BIAS_Msk_3v) | (0x7u << CLK_XTLCTL_CORE_BIAS_Pos_3v);
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}
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/**
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* @brief Update SystemCoreClock variable according to Clock Register Values.
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* The SystemCoreClock variable contains the core clock (HCLK), it can
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* be used by the user application to setup the SysTick timer or configure
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* other parameters.
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*
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* @note Each time the core clock (HCLK) changes, this function must be called
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* to update SystemCoreClock variable value. Otherwise, any configuration
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* based on this variable will be incorrect.
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*
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* @param None
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* @retval None
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*/
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void SystemCoreClockUpdate(void)
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{
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#ifdef FPGA_MODE
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//Fixed 32M System Clock on FPGA
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SystemCoreClock = FREQ_32MHZ;
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#else
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uint32_t div = 0;
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uint32_t freq_out = 0;
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div = (CLK->CLK_TOP_CTRL_3V & CLK_TOPCTL_AHB_DIV_Msk) >> CLK_TOPCTL_AHB_DIV_Pos;
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if(div == 0)
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div = 1;
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else
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div += 1;
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if(CLK->CLK_TOP_CTRL_3V & CLK_SYS_SRCSEL_DPLL){
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freq_out = (CLK->DPLL_CTRL & CLK_DPLLCTL_FREQ_OUT_Msk);
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if(freq_out == CLK_DPLL_OUT_64M){
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SystemCoreClock = FREQ_64MHZ / div;
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}
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else{
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SystemCoreClock = FREQ_48MHZ / div;
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}
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}
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else{
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SystemCoreClock = FREQ_32MHZ / div;
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}
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#endif
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}
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static bool HwParamDataVerify(OTP_STRUCT_T *p_opt)
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{
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uint8_t calc_checksum = 0;
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for (size_t i = 0x1E; i < 0x7B; i++)
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{
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calc_checksum += p_opt->d8[i];
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}
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if (calc_checksum != p_opt->m.ft_checksum)
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{
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return false; // Calib data checksum failed
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}
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if (p_opt->m.ft_version >= 2)
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{
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calc_checksum = 0;
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for (size_t i = 0x80; i < 0xFF; i++)
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{
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calc_checksum += p_opt->d8[i];
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}
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if (calc_checksum != p_opt->m_v2.ft_checksum2)
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{
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return false; // Calib data checksum2 failed
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}
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}
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return true;
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}
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__WEAK void ADC_SetCalirationParams(OTP_STRUCT_T *otp)
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{
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return;
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}
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__WEAK void PW_ParamsSet(OTP_STRUCT_T *otp)
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{
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return;
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}
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bool SystemHwParamLoader(OTP_STRUCT_T *otp)
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{
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/*
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* NOTE: We should make sure flash enhance mode is disabled before read
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* data from flash.
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*/
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FMC_GetFlashUniqueId(FLCTL);
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FMC_GetFlashJedecId(FLCTL);
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FMC_SetFlashCapacity(FLCTL);
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FMC_ReadInfoArea(FLCTL, 0x0, CMD_DREAD, (uint8_t *)otp, sizeof(OTP_STRUCT_T));
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if (!HwParamDataVerify(otp))
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{
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/* Mark chip as NoFT */
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isFtDataValid = false;
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/* Exit if Hw Parameter Data Checking Failed */
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memset(&otp->d8[0x00], 0x00, sizeof(OTP_STRUCT_T)); // clear the global otp structure
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return false;
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}
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// Note:
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// 1. Clock XTH and XTL may need Board-Level calibration on customers MP stage
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// 2. ADC calibration data is loaded when calling ADC APIs (e.g. ADC_Init(), ADC_OutputVoltage(), ..)
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ANA->LP_PTAT_POLY = (ANA->LP_PTAT_POLY & ~(0x7u << 3) & ~(0x7u << 16)) | (otp->m.pmu_vbg_trim << 3) | (otp->m.ipoly_trim << 16);
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ANA->LP_HP_LDO = (ANA->LP_HP_LDO & ~(0xFu << 3) & ~(0x7u << 20)) | (otp->m.hp_ldo_trim << 3) | (otp->m.flash_ldo_trim << 20);
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ANA->LP_LP_LDO_3V = (ANA->LP_LP_LDO_3V & ~(0xFu << 1) & ~(0xFu << 17)) | (otp->m.lpl_ldo_trim << 1) | (otp->m.lph_ldo_trim << 17);
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ANA->LP_ANA_LDO = (ANA->LP_ANA_LDO & ~(0xFu << 3)) | (otp->m.ana_ldo_trim << 3);
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ANA->ANA_RFFE_LDO = (ANA->ANA_RFFE_LDO & ~(0xFu << 3)) | (otp->m.rffe_ldo_trim << 3);
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ANA->LP_FSYN_LDO = (ANA->LP_FSYN_LDO & ~(0xFu << 3)) | (otp->m.fsyn_ldo_trim << 3);
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ANA->ANA_ADC_LDO = (ANA->ANA_ADC_LDO & ~(0xFu << 3)) | (otp->m.adc_ldo_trim << 3);
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ANA->ANA_VCO_LDO = (ANA->ANA_VCO_LDO & ~(0xFu << 3)) | (otp->m.vco_ldo_trim << 3);
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ANA->ANA_MISC_3V = (ANA->ANA_MISC_3V & ~(0x7u << 0)) | (otp->m.bod_vref_trim << 0);
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CLK->RCH_CTRL = (CLK->RCH_CTRL & ~(0xFFu << 8)) | (otp->m.rch_trim << 8);
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CLK->RCL_CTRL_3V = (CLK->RCL_CTRL_3V & ~(0xFFFu << 4)) | (otp->m.rcl_coarse_trim << 4) | (otp->m.rcl_fine_trim << 8);
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otp->m.buck_imax_cal_trim = (otp->m.buck_imax_cal_trim + 4 > 0x1F) ? 0x1F : (otp->m.buck_imax_cal_trim + 4);
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ANA->ANA_RESERVED_3V = (ANA->ANA_RESERVED_3V & ~(0x1u << 21)) | ((otp->m.buck_out_trim & 0x1u) << 21); // lsb of buck vout trim code
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ANA->LP_BUCK_3V = (ANA->LP_BUCK_3V & ~(0xFu << 2) & ~(0x1Fu << 9) & ~(0x1Fu << 14))
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| ((otp->m.buck_out_trim >> 1) << 2) | (otp->m.buck_imax_cal_trim << 9) | (otp->m.buck_zero_cal_trim << 14);
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ANA->ANA_DFT = (ANA->ANA_DFT & ~(0xFFu << 24)) | (otp->m.battery_trim << 24);
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if (otp->m.ft_version >= 2)
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{
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if (otp->m.ft_version < 4)
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{
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otp->m_v2.lph_ldo_vref_trim++;
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if (otp->m_v2.lph_ldo_vref_trim > 7)
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{
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otp->m_v2.lph_ldo_vref_trim = 7;
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}
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}
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ANA->LP_LP_LDO_3V = (ANA->LP_LP_LDO_3V & ~(0x7u << 21)) | (otp->m_v2.lph_ldo_vref_trim << 21);
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ANA->ANA_RESERVED_3V |= (0x1u << 24); // LPLDOH enhance mode (default enabled, coordinate with lph vref trim)
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if (otp->m.ft_version >= 7)
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{
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// Start from this ft version, we change LPLDOH calibrate flow to MODE2 (indtead of MODE1 with enhance mode),
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// hence we should switch LPLDOH to MODE2 before we use it.
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// Note that lph_ldo_trim would take no effect anymore when we switch LPLDOH to MODE2
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ANA->LP_LP_LDO_3V |= ANAC_LPLDO_H_MODE_SEL_Msk_3v;
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}
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}
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if (otp->m.ft_version >= 6)
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{
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ANA->LP_PTAT_POLY = (ANA->LP_PTAT_POLY & ~(0x3u << 1)) | (otp->m_v2.ptat_temp_trim << 1);
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CLK->XTL_CTRL_3V = (CLK->XTL_CTRL_3V & ~(0x7u << 4)) | (otp->m_v2.xtl_core << 4);
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CLK->XTH_CTRL = (CLK->XTH_CTRL & ~(0x1u << 10)) | (otp->m_v2.xth_icore << 10);
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CLK->RCH_CTRL = (CLK->RCH_CTRL & ~(0x3u << 4)) | (otp->m_v2.rch_bias << 4);
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CLK->DPLL_CTRL = (CLK->DPLL_CTRL & ~(0x3u << 4) & ~(0x3u << 6) & ~(0x7u << 8) & ~(0x3u << 11))
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| (otp->m_v2.dpll_icp_bias << 4) | (otp->m_v2.dpll_icp_ctrl << 6) | (otp->m_v2.dpll_kvco_ctrl << 8) | (otp->m_v2.dpll_vco_freq_trim << 11);
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}
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/*
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* Storing adc params related calibration. if adc symbol is not linked,
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* this function would be handled as weak function.
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*/
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ADC_SetCalirationParams(otp);
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/*
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* Storing power params related calibration.
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*/
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PW_ParamsSet(otp);
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#ifdef SYNC_3V_REG_MANUALLY
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CLK_Wait3vSyncReady();
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#endif
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return true;
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}
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#if USE_ASSERT
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/**
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* @brief Assert Error Message
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*
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* @param[in] file the source file name
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* @param[in] line line number
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*
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* @return None
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*
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* @details The function prints the source file name and line number where
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* the ASSERT_PARAM() error occurs, and then stops in an infinite loop.
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*/
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void AssertError(uint8_t * file, uint32_t line)
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{
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SYS_DBG(" wrong parameters.\r\n", file, line);
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/* Infinite loop */
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while(1) ;
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}
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#endif
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