/**************************************************************************
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* @file pan_spi.h
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* @version V1.10
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* $Revision: 2 $
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* $Date: 2023/11/08 $
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* @brief PAN series SPI driver header file
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*
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* @note
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* Copyright (C) 2023 Panchip Technology Corp. All rights reserved.
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*****************************************************************************/
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#ifndef __PAN_SPI_H__
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#define __PAN_SPI_H__
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/**
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* @brief Spi Interface
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* @defgroup spi_interface Spi Interface
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* @{
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*/
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/**@defgroup SPI_IRQ_FLAG Spi interrupt event type
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* @brief Spi interrupt event type constants definitions
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* @{ */
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typedef enum SPI_Irq
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{
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SPI_IRQ_TX_HALF_EMPTY = 0x08, //Transmit FIFO Half Empty Interrupt
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SPI_IRQ_RX_HALF_FULL = 0x04, //Receive FIFO Half Full Interrupt
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SPI_IRQ_RX_TIMEOUT = 0x02, //Receive FIFO Not Empty and No Read prior to Timeout Interrupt
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SPI_IRQ_RX_OVERRUN = 0x01, //Receive FIFO Overflow Interrupt
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SPI_IRQ_ALL = 0x0f //All interrupts
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} SPI_IrqDef;
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/**@} */
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/**@defgroup SPI_WORK_MODE_FLAG Spi operating mode
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* @brief Spi operating mode constants definitions
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* @{ */
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typedef enum SPI_Role
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{
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SPI_RoleMaster = 0x0,
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SPI_RoleSlave = 0x1
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} SPI_RoleDef;
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/**@} */
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#if 0
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/*Transfer Mode. Selects the mode of transfer for serial communication. This field
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does not affect the transfer duplicity. Only indicates whether the receive or transmit
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data are valid.*/
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typedef enum SPI_TransferMode
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{
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Spi_dir_full_duplex = 0x0,
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Spi_dir_tx_only = 0x1,
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Spi_dir_rx_only = 0x2,
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Spi_dir_read_eeprom = 0x3
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} SPI_TransferModeDef;
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#endif
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/**@defgroup SPI_DATA_SIZE_FLAG Spi data frame size
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* @brief Spi data frame size constants definitions
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* @{ */
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typedef enum SPI_DataFrameSize
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{
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SPI_DataFrame_4b = 0x03,
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SPI_DataFrame_5b = 0x04,
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SPI_DataFrame_6b = 0x05,
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SPI_DataFrame_7b = 0x06,
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SPI_DataFrame_8b = 0x07,
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SPI_DataFrame_9b = 0x08,
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SPI_DataFrame_10b = 0x09,
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SPI_DataFrame_11b = 0x0a,
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SPI_DataFrame_12b = 0x0b,
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SPI_DataFrame_13b = 0x0c,
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SPI_DataFrame_14b = 0x0d,
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SPI_DataFrame_15b = 0x0e,
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SPI_DataFrame_16b = 0x0f
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} SPI_DataFrameSizeDef;
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/**@} */
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/**@defgroup SPI_BAUD_DIV_FLAG Spi baudrate divider
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* @brief Spi baudrate divider constants definitions
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* @{ */
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typedef enum SPI_BaudRateDiv
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{
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SPI_BaudRateDiv_2 = 0x02,
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SPI_BaudRateDiv_4 = 0x04,
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SPI_BaudRateDiv_6 = 0x06,
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SPI_BaudRateDiv_8 = 0x08,
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SPI_BaudRateDiv_16 = 0x10,
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SPI_BaudRateDiv_32 = 0x20,
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SPI_BaudRateDiv_48 = 0x30,
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SPI_BaudRateDiv_64 = 0x40,
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SPI_BaudRateDiv_96 = 0x60,
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SPI_BaudRateDiv_128 = 0x80,
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SPI_BaudRateDiv_160 = 0xA0,
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SPI_BaudRateDiv_192 = 0xC0,
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SPI_BaudRateDiv_224 = 0xE0,
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SPI_BaudRateDiv_240 = 0xF0,
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SPI_BaudRateDiv_250 = 0xFA,
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} SPI_BaudRateDivDef;
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/**@} */
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#define SPI_BAUD_RATE_DIV(x) ((x)?(x):(256))
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/**@defgroup SPI_POLARITY_FLAG Spi clock polarity
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* @brief Spi clock polarity constants definitions,Serial Clock Polarity, Used to
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* select the polarity of the inactive serial clock, which is held inactive when
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* the DW_apb_ssi master is not actively transferring data on the serial bus
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* @{ */
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typedef enum SPI_ClockPol
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{
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SPI_ClockPolarityLow = 0x0,
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SPI_ClockPolarityHigh = 0x1
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} SPI_ClockPolDef;
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/**@} */
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/**@defgroup SPI_PHASE_FLAG Spi clock phase
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* @brief Spi clock phase constants definitions
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* @{ */
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typedef enum SPI_ClockPhase
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{
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SPI_ClockPhaseFirstEdge = 0x0,
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SPI_ClockPhaseSecondEdge = 0x1
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} SPI_ClockPhaseDef;
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/**@} */
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/**@defgroup SPI_FORMAT_FLAG Spi frame format
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* @brief Spi frame format constants definitions
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* @{ */
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typedef enum SPI_FrameFormat
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{
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SPI_FormatMotorola = 0x00,
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SPI_FormatTi = 0x01,
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SPI_FormatMicrowire = 0x02,
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} SPI_FrameFormatDef;
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/**@} */
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/**
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* @brief Enumeration of SPI Wire Number.
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*/
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typedef enum SPI_WireNum
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{
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SPI_WireNumThree = 0x01, /*!< 3-wire SPI communication */
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SPI_WireNumFour = 0x00 /*!< 4-wire SPI communication */
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} SPI_WireNumDef;
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/**
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* @brief Enumeration of SPI Command/Data Selection.
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*/
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typedef enum SPI_CmdDat
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{
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SPI_CommandSelect = 0x00, /*!< SPI command selection */
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SPI_DataSelect = 0x01 /*!< SPI data selection */
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} SPI_CmdDatDef;
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/**
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* @brief Enumeration of SPI Write/Read Selection.
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*/
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typedef enum SPI_WriteReadSel
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{
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SPI_3WireRead = 0x00, /*!< 3-wire SPI read selection */
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SPI_3WireWrite = 0x01 /*!< 3-wire SPI write selection */
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} SPI_WriteReadSelDef;
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/**
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* @brief Structure with spi init feature.
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*
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* @param SPI_role Specifies the SPI operating mode.\ref SPI_WORK_MODE_FLAG
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* @param SPI_dataFrameSize Specifies the SPI data size \ref SPI_DATA_SIZE_FLAG
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* @param SPI_CPOL Specifies the SPI data size \ref SPI_POLARITY_FLAG
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* @param SPI_CPHA Specifies the clock active edge for the bit capture \ref SPI_PHASE_FLAG
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* @param SPI_baudRateDiv Specifies the Baud Rate Divisor used to configure the transmit and receive
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* SCK clock \ref SPI_BAUD_DIV_FLAG
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* @param SPI_format Specifies the SPI format \ref SPI_FORMAT_FLAG
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*/
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typedef struct
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{
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SPI_RoleDef SPI_role; /*!< Specifies the SPI operating mode */
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SPI_DataFrameSizeDef SPI_dataFrameSize; /*!< Specifies the SPI data size */
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SPI_ClockPolDef SPI_CPOL; /*!< Specifies the serial clock steady state */
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SPI_ClockPhaseDef SPI_CPHA; /*!< Specifies the clock active edge for the bit capture */
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// SPI_BaudRateDivDef SPI_baudRateDiv; /*!< Specifies the Baud Rate Divisor used to configure the transmit and receive SCK clock. */
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uint16_t SPI_baudRateDiv; /*!< Specifies the Baud Rate Divisor used to configure the transmit and receive SCK clock. */
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SPI_FrameFormatDef SPI_format; /*!< Specifies the SPI format */
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} SPI_InitTypeDef;
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/**
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* @brief Synchronous serial port enable
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* @param SPIx: where x can be 1, 2 to select the
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* SPI peripheral.
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* @retval None
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*/
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__STATIC_INLINE void SPI_EnableSpi(SPI_T* SPIx)
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{
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uint32_t tmpreg = 0;
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tmpreg = SPIx->CR1;
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tmpreg |= SPI_CR1_SSE_Msk;
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SPIx->CR1 = tmpreg;
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}
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/**
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* @brief Synchronous serial port disable
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* @param SPIx: where x can be 1, 2 to select the
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* SPI peripheral.
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* @retval None
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*/
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__STATIC_INLINE void SPI_DisableSpi(SPI_T* SPIx)
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{
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uint32_t tmpreg = 0;
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tmpreg = SPIx->CR1;
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tmpreg &= ~SPI_CR1_SSE_Msk;
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SPIx->CR1 = tmpreg;
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}
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/**
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* @brief get synchronous serial port status
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* @param SPIx: where x can be 1, 2 to select the
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* SPI peripheral.
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* @retval true/false
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*/
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__STATIC_INLINE bool SPI_IsSpiEnabled(SPI_T* SPIx)
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{
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uint32_t tmpreg = 0;
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tmpreg = SPIx->CR1;
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if(tmpreg & SPI_CR1_SSE_Msk)
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return true;
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else
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return false;
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}
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/**
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* @brief DMA for the transmit FIFO is enabled
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* @param SPIx: where x can be 1, 2 to select the
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* SPI peripheral.
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* @retval None
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*/
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__STATIC_INLINE void SPI_EnableDmaTx(SPI_T* SPIx)
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{
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uint32_t tmpreg = 0x00;
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tmpreg = SPIx->DMACR;
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tmpreg |= SPI_DMACR_TDMAE_Msk;
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SPIx->DMACR = tmpreg;
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}
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/**
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* @brief DMA for the transmit FIFO is disabled
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* @param SPIx: where x can be 1, 2 to select the
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* SPI peripheral.
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* @retval None
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*/
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__STATIC_INLINE void SPI_DisableDmaTx(SPI_T* SPIx)
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{
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uint32_t tmpreg = 0x00;
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tmpreg = SPIx->DMACR;
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tmpreg &= ~SPI_DMACR_TDMAE_Msk;
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SPIx->DMACR = tmpreg;
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}
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/**
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* @brief get DMA for the transmit FIFO status
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* @param SPIx: where x can be 1, 2 to select the
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* SPI peripheral.
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* @retval true/false
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*/
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__STATIC_INLINE bool SPI_IsDmaTxEnabled(SPI_T* SPIx)
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{
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uint32_t tmpreg = 0x00;
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tmpreg = SPIx->DMACR;
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if(tmpreg & SPI_DMACR_TDMAE_Msk)
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return true;
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else
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return false;
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}
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/**
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* @brief DMA for the receive FIFO is enabled
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* @param SPIx: where x can be 1, 2 to select the
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* SPI peripheral.
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* @retval None
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*/
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__STATIC_INLINE void SPI_EnableDmaRx(SPI_T* SPIx)
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{
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uint32_t tmpreg = 0x00;
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tmpreg = SPIx->DMACR;
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tmpreg |= SPI_DMACR_RDMAE_Msk;
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SPIx->DMACR = tmpreg;
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}
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/**
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* @brief DMA for the receive FIFO is disabled
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* @param SPIx: where x can be 1, 2 to select the
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* SPI peripheral.
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* @retval None
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*/
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__STATIC_INLINE void SPI_DisableDmaRx(SPI_T* SPIx)
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{
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uint32_t tmpreg = 0x00;
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tmpreg = SPIx->DMACR;
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tmpreg &= ~SPI_DMACR_RDMAE_Msk;
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SPIx->DMACR = tmpreg;
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}
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/**
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* @brief get DMA for the receive FIFO status
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* @param SPIx: where x can be 1, 2 to select the
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* SPI peripheral.
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* @retval true/false
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*/
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__STATIC_INLINE bool SPI_IsDmaRxEnabled(SPI_T* SPIx)
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{
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uint32_t tmpreg = 0x00;
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tmpreg = SPIx->DMACR;
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if(tmpreg & SPI_DMACR_RDMAE_Msk)
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return true;
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else
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return false;
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}
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/**
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* @brief Send data,DR is the data register and is 16-bits wide
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* @param SPIx: where x can be 1, 2 to select the
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* SPI peripheral.
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* @retval None
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*/
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__STATIC_INLINE void SPI_SendData(SPI_T* SPIx, uint32_t Data)
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{
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SPIx->DR = Data;
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}
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/**
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* @brief Receive data,DR is the data register and is 16-bits wide
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* @param SPIx: where x can be 1, 2 to select the
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* SPI peripheral.
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* @retval None
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*/
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__STATIC_INLINE uint32_t SPI_ReceiveData(SPI_T* SPIx)
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{
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return SPIx->DR;
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}
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/**
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* @brief Interruput mask Enable
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* @param SPIx: where x can be 1, 2 to select the
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* SPI peripheral.
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* @param irq: where x can be
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* SPI_IRQ_TX_HALF_EMPTY
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* SPI_IRQ_RX_HALF_FULL
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* SPI_IRQ_RX_TIMEOUT
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* SPI_IRQ_RX_OVERRUN
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* SPI_IRQ_ALL
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* @retval None
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*/
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__STATIC_INLINE void SPI_EnableIrq(SPI_T* SPIx, SPI_IrqDef irq)
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{
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uint32_t tmpreg = 0x00;
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tmpreg = SPIx->IMSC;
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tmpreg |= irq;
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SPIx->IMSC = tmpreg;
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}
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/**
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* @brief Interruput mask Disable
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* @param SPIx: where x can be 1, 2 to select the
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* SPI peripheral.
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* @param irq: where x can be
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* \ref SPI_IRQ_TX_HALF_EMPTY
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* \ref SPI_IRQ_RX_HALF_FULL
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* \ref SPI_IRQ_RX_TIMEOUT
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* \ref SPI_IRQ_RX_OVERRUN
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* \ref SPI_IRQ_ALL
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* @return None
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*/
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__STATIC_INLINE void SPI_DisableIrq(SPI_T* SPIx, SPI_IrqDef irq)
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{
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uint32_t tmpreg = 0x00;
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tmpreg = SPIx->IMSC;
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tmpreg &= ~irq;
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SPIx->IMSC = tmpreg;
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}
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/**
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* @brief Get Interruput mask status
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* @param SPIx: where x can be 1, 2 to select the
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* SPI peripheral.
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* @param irq: where x can be
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* \ref SPI_IRQ_TX_HALF_EMPTY
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* \ref SPI_IRQ_RX_HALF_FULL
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* \ref SPI_IRQ_RX_TIMEOUT
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* \ref SPI_IRQ_RX_OVERRUN
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* \ref SPI_IRQ_ALL
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* @return None
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*/
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__STATIC_INLINE bool SPI_IsIrqEnabled(SPI_T* SPIx, SPI_IrqDef irq)
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{
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uint32_t tmpreg;
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tmpreg = SPIx->IMSC;
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if(tmpreg & irq )
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return true;
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else
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return false;
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}
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/**
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* @brief Get Masked Interruput status
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* @param SPIx: where x can be 1, 2 to select the
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* SPI peripheral.
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* @retval SPI_IrqDef: where return value can be
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* SPI_IRQ_TX_HALF_EMPTY
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* SPI_IRQ_RX_HALF_FULL
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* SPI_IRQ_RX_TIMEOUT
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* SPI_IRQ_RX_OVERRUN
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* SPI_IRQ_ALL
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*/
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__STATIC_INLINE SPI_IrqDef SPI_GetMskedActiveIrq(SPI_T* SPIx)
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{
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uint32_t tmpreg = 0x00;
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tmpreg = SPIx->MIS;
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tmpreg &= SPI_IRQ_ALL;
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return (SPI_IrqDef)tmpreg;
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}
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/**
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* @brief Get Masked Interruput status
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* @param SPIx: where x can be 1, 2 to select the
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* SPI peripheral.
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* @param irq: where x can be
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* \ref SPI_IRQ_TX_HALF_EMPTY
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* \ref SPI_IRQ_RX_HALF_FULL
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* \ref SPI_IRQ_RX_TIMEOUT
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* \ref SPI_IRQ_RX_OVERRUN
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* \ref SPI_IRQ_ALL
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* @return true/false
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*/
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__STATIC_INLINE bool SPI_IsIrqActive(SPI_T * SPIx, SPI_IrqDef irq)
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{
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uint32_t tmpreg = 0x00;
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tmpreg = SPIx->MIS;
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if(tmpreg & irq )
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return true;
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else
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return false;
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}
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/**
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* @brief Get raw Interruput status
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* @param SPIx: where x can be 1, 2 to select the
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* SPI peripheral.
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* @param irq: where x can be
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* \ref SPI_IRQ_TX_HALF_EMPTY
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* \ref SPI_IRQ_RX_HALF_FULL
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* \ref SPI_IRQ_RX_TIMEOUT
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* \ref SPI_IRQ_RX_OVERRUN
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* \ref SPI_IRQ_ALL
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* @return true/false
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*/
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__STATIC_INLINE bool SPI_IsRawIrqActive(SPI_T * SPIx, SPI_IrqDef irq)
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{
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uint32_t tmpreg = 0x00;
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tmpreg = SPIx->RIS;
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if(tmpreg & irq )
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return true;
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else
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return false;
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}
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/**
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* @brief clear Interruput status
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* @param SPIx: where x can be 1, 2 to select the
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* SPI peripheral.
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* @param irq: can be
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* \ref SPI_IRQ_RX_TIMEOUT
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* \ref SPI_IRQ_RX_OVERRUN
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* @return None
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*/
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__STATIC_INLINE void SPI_ClearIrq(SPI_T * SPIx, SPI_IrqDef irq)
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{
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uint32_t tmpreg = 0x00;
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tmpreg = SPIx->ICR;
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tmpreg |= irq ;
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SPIx->ICR = tmpreg;
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}
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/**
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* @brief Get Raw Interruput status
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* @param SPIx: where x can be 1, 2 to select the
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* SPI peripheral.
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* @return SPI_IrqDef: where return value can be
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* \ref SPI_IRQ_TX_HALF_EMPTY
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* \ref SPI_IRQ_RX_HALF_FULL
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* \ref SPI_IRQ_RX_TIMEOUT
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* \ref SPI_IRQ_RX_OVERRUN
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* \ref SPI_IRQ_ALL
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*/
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__STATIC_INLINE SPI_IrqDef SPI_GetRawActiveIrq(SPI_T* SPIx)
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{
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uint32_t tmpreg = 0x00;
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tmpreg = SPIx->RIS;
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tmpreg &= SPI_IRQ_ALL;
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return (SPI_IrqDef)tmpreg;
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}
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/**
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* @brief Get Tx FIFO empty status
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* @param SPIx: where x can be 1, 2 to select the
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* SPI peripheral.
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* @retval true/false
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*/
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__STATIC_INLINE bool SPI_IsTxFifoEmpty(SPI_T* SPIx)
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{
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uint32_t tmpreg = 0x00;
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tmpreg = SPIx->SR;
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if(tmpreg & SPI_SR_TFE_Msk)
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return true;
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else
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return false;
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}
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/**
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* @brief Get Tx FIFO full status
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* @param SPIx: where x can be 1, 2 to select the
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* SPI peripheral.
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* @retval true/false
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*/
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__STATIC_INLINE bool SPI_IsTxFifoFull(SPI_T* SPIx)
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{
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uint32_t tmpreg = 0x00;
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tmpreg = SPIx->SR;
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if(tmpreg & SPI_SR_TFNF_Msk)
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return false;
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else
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return true;
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}
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/**
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* @brief Get Tx FIFO empty status
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* @param SPIx: where x can be 1, 2 to select the
|
* SPI peripheral.
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* @retval true/false
|
*/
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__STATIC_INLINE bool SPI_IsRxFifoEmpty(SPI_T* SPIx)
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{
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uint32_t tmpreg = 0x00;
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tmpreg = SPIx->SR;
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if(tmpreg & SPI_SR_RFNE_Msk)
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return false;
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else
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return true;
|
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}
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/**
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* @brief Get Tx FIFO full status
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* @param SPIx: where x can be 1, 2 to select the
|
* SPI peripheral.
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* @retval true/false
|
*/
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__STATIC_INLINE bool SPI_IsRxFifoFull(SPI_T* SPIx)
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{
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uint32_t tmpreg = 0x00;
|
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tmpreg = SPIx->SR;
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if(tmpreg & SPI_SR_RFF_Msk)
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return true;
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else
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return false;
|
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}
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/**
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* @brief Get Synchronous serial port busy status
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* @param SPIx: where x can be 1, 2 to select the
|
* SPI peripheral.
|
* @retval true/false
|
*/
|
__STATIC_INLINE bool SPI_IsBusy(SPI_T* SPIx)
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{
|
uint32_t tmpreg = 0x00;
|
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tmpreg = SPIx->SR;
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if(tmpreg & SPI_SR_BUSY_Msk)
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return true;
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else
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return false;
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}
|
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/**
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* @brief Tx Lsb Send function control
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* @param SPIx: where x can be 1, 2 to select the
|
* SPI peripheral.
|
* @retval none
|
*/
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__STATIC_INLINE void SPI_TxLsbEnable(SPI_T* SPIx,bool enable)
|
{
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(enable) ? (SPIx->CR1 |= SPI_CR1_TX_LSB_EN_Msk) : (SPIx->CR1 &= ~SPI_CR1_TX_LSB_EN_Msk);
|
}
|
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/**
|
* @brief Rx Lsb Send function control
|
* @param SPIx: where x can be 1, 2 to select the
|
* SPI peripheral.
|
* @retval none
|
*/
|
__STATIC_INLINE void SPI_RxLsbEnable(SPI_T* SPIx,bool enable)
|
{
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(enable) ? (SPIx->CR1 |= SPI_CR1_RX_LSB_EN_Msk) : (SPIx->CR1 &= ~SPI_CR1_RX_LSB_EN_Msk);
|
}
|
|
/**
|
* @brief set spi wire number,which controlled the spi work mode
|
* @param SPIx: where x can be 1, 2 to select the
|
* SPI peripheral.
|
* @param num: where num can be
|
* SPI_WireNumThree
|
* SPI_WireNumFour
|
* @retval none
|
*/
|
__STATIC_INLINE void SPI_SetWireNum(SPI_T* SPIx,SPI_WireNumDef num)
|
{
|
(num == SPI_WireNumThree) ? (SPIx->CR1 |= SPI_CR1_SPI_MODE_SEL_Msk) : (SPIx->CR1 &= ~SPI_CR1_SPI_MODE_SEL_Msk);
|
}
|
|
/**
|
* @brief Distinguish whether there is a DC output line in 3-wire SPI mode,
|
* @param SPIx: where x can be 1, 2 to select the
|
* SPI peripheral.
|
* @param NewState: new state of spi dc output line state
|
* enable-> dc output line
|
* disable-> no dc output line
|
* @retval none
|
*/
|
__STATIC_INLINE void SPI_DataCmdLineEnable(SPI_T* SPIx, FunctionalState NewState)
|
{
|
(NewState == ENABLE) ? (SPIx->CR1 |= SPI_CR1_CMD_DAT_EN_Msk) : (SPIx->CR1 &= ~SPI_CR1_CMD_DAT_EN_Msk);
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}
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/**
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* @brief Write read control in 3-wire SPI mode,
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* @param SPIx: where x can be 1, 2 to select the
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* SPI peripheral.
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* @param cmdDat: where cmdDat can be
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* SPI_DataSelect
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* SPI_CommandSelect
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* @retval none
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*/
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__STATIC_INLINE void SPI_DataCmdSelCmdDat(SPI_T* SPIx, SPI_CmdDatDef cmdDat)
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{
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(cmdDat == SPI_DataSelect) ? (SPIx->CR1 |= SPI_CR1_CMD_DAT_CTRL_Msk) : (SPIx->CR1 &= ~SPI_CR1_CMD_DAT_CTRL_Msk);
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}
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/**
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* @brief Write read control in 3-wire SPI mode
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* @param SPIx: where x can be 1, 2 to select the
|
* SPI peripheral.
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* @param wr: where wr can be
|
* SPI_3WireRead
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* SPI_3WireWrite
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* @retval none
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*/
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__STATIC_INLINE void SPI_WriteReadCtrl(SPI_T* SPIx, SPI_WriteReadSelDef wr)
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{
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(wr == SPI_3WireWrite) ? (SPIx->CR1 |= SPI_CR1_WR_CTRL_Msk) : (SPIx->CR1 &= ~SPI_CR1_WR_CTRL_Msk);
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}
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|
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/**
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* @brief Initializes the SPIx peripheral according to the specified
|
* parameters in the SPI_InitStruct .
|
* @param SPIx: where x can be 1, 2 to select the
|
* SPI peripheral.
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* @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that contains
|
* the configuration information for the specified SPI peripheral.
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* @return None
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*/
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void SPI_Init(SPI_T* SPIx, SPI_InitTypeDef* SPI_InitStruct);
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/**@} */
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#ifdef __cplusplus
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}
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#endif
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#endif //__PAN_SPI_H__
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/*** (C) COPYRIGHT 2023 Panchip Technology Corp. ***/
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