/*
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* Copyright (C) 2021 Panchip Technology Corp. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Panchip series pri_rf driver header file
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* @version V1.00
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* $Revision: 3 $
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* $Date: 21/11/19 18:33 $
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*/
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#ifndef __PAN_PRI_RF_H__
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#define __PAN_PRI_RF_H__
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/**
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* @brief Private rf Interface
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* @defgroup private_rf_interface Private rf Interface
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* @{
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*/
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#include "PanSeries.h"
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/**@defgroup PRI_RF_MODE_FLAG Private rf mode type
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* @brief Private rf mode type definitions
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* @{ */
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#define PRI_RF_MODE_SEL_TX (0) /*!< Tx mode */
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#define PRI_RF_MODE_SEL_RX (1) /*!< Rx mode */
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#define PRI_RF_MODE_SEL_TRX (2) /*!< Tx mode and Rx mode */
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/**@} */
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/**@defgroup PRI_RF_ADR_LEN_FLAG Private rf address lenth type
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* @brief Private rf address lenth type definitions
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* @{ */
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#define PRI_RF_ADDR_BYTE_LEN_2 (0) /*!< 2-bytes is invalid */
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#define PRI_RF_ADDR_BYTE_LEN_3 (1) /*!< 3-bytes address */
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#define PRI_RF_ADDR_BYTE_LEN_4 (2) /*!< 4-bytes address */
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#define PRI_RF_ADDR_BYTE_LEN_5 (3) /*!< 5-bytes address */
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/**@} */
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/**@defgroup PRI_RF_CHIP_MODE_FLAG Private rf chip mode type
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* @brief Private rf chip mode type definitions
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* @{ */
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#define PRI_RF_CHIP_MODE_INVALID (0) /*!< Chip mode is invalid */
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#define PRI_RF_CHIP_MODE_BLE (1) /*!< Ble mode */
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#define PRI_RF_CHIP_MODE_297 (2) /*!< 297 mode */
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#define PRI_RF_CHIP_MODE_NORDIC (3) /*!< Nordic mode */
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/**@} */
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/**@defgroup PRI_RF_BUf_MEM_FLAG Private rf buf memory address offset
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* @brief Private rf buf memory address offset definitions
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* @{ */
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#define REG_FILE_OFST 0x0000 /*!< Register address offset */
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#define SEQ_RAM_OFST 0x1000 /*!< Sequence ram address offset */
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#define LIST_RAM_OFST 0x8000 /*!< List ram address offset */
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#define TX_RX_RAM_OFST 0x8200 /*!< Tx and rx ram address offset */
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#define CTE_IQ_RAM_OFST 0xB7FC /*!< Cte ram address offset */
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/**@} */
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/**
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* @brief Read 32 bit register value
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*
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* @param[in] base_addr Module base address
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* @param[in] reg_ofst register address offset
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*/
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#define LLHWC_READ32_REG(base_addr, reg_ofst) \
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(*(volatile uint32_t *)((0x50020000) + (base_addr) + (reg_ofst)))
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/**
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* @brief Write value to 32 bit register
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*
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* @param[in] base_addr Module base address
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* @param[in] reg_ofst register address offset
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* @param[in] data register expect value
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*/
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#define LLHWC_WRITE32_REG(base_addr, reg_ofst, data) \
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(*(volatile uint32_t *)(((0x50020000) + (base_addr) + (reg_ofst))) = (data))
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/**
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* @brief Read 4 byte with byte read mode
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*
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* @param[in] pckt Base address
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* @param[in] pos address offset
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*/
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#define READ_4_BYTES(pckt, pos) (((uint32_t) (pckt)[pos]) | \
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(((uint32_t) (pckt)[pos + 1]) << 8) | \
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(((uint32_t) (pckt)[pos + 2]) << 16) | \
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(((uint32_t) (pckt)[pos + 3]) << 24))
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/**
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* @brief Write value to register
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*
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* @param[in] base Module base address
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* @param[in] Reg register address
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* @param[in] Func register function
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* @param[in] Value register expect value
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*/
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#define PRI_RF_WRITE_REG_VALUE(base,Reg,Func,Value) \
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(base->Reg = (base->Reg & ~(Reg##_##Func##_Msk)) | ((Value << Reg##_##Func##_Pos) & Reg##_##Func##_Msk))
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/**
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* @brief Read value to register
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*
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* @param[in] base Module base address
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* @param[in] Reg register address
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* @param[in] Func register function
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*/
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#define PRI_RF_READ_REG_VALUE(base,Reg,Func) \
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((base->Reg & (Reg##_##Func##_Msk)) >> Reg##_##Func##_Pos)
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/**
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* @brief Set function according to state
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*
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* @param[in] base Module base address
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* @param[in] Reg register address
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* @param[in] Func register function
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* @param[in] State enable state
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*/
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#define PRI_RF_SET_FUNC_ENABLE(base,Reg,Func,State) \
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((State == ENABLE) ? (base->Reg |= Reg##_##Func##_Msk) : (base->Reg &= ~Reg##_##Func##_Msk))
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/**
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* @brief This function used to enable or disable auto analysis payload function
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* @param rf: where rf is a private rf peripheral base address
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* @param NewState: new state of enabling state
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* @return none
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*/
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__STATIC_INLINE void PRI_RF_AutoAnlsPayloadEn(PRI_RF_T *rf,FunctionalState NewState)
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{
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PRI_RF_SET_FUNC_ENABLE(rf,R00_CTL,DPY_EN,NewState);
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}
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/**
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* @brief This function used to enable or disable crc check function
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* @param rf: where rf is a private rf peripheral base address
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* @param NewState: new state of enabling state
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* @return none
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*/
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__STATIC_INLINE void PRI_RF_CrcCheckEn(PRI_RF_T *rf,FunctionalState NewState)
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{
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PRI_RF_SET_FUNC_ENABLE(rf,R00_CTL,CRC_EN,NewState);
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}
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/**
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* @brief This function select crc check mode
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* @param rf: where rf is a private rf peripheral base address
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* @param NewState: new state of crc16 select,if enable,crc16 selected,or crc8 selected
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* @return none
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*/
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__STATIC_INLINE void PRI_RF_Crc16Select(PRI_RF_T *rf,FunctionalState NewState)
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{
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PRI_RF_SET_FUNC_ENABLE(rf,R00_CTL,CRC_SEL16,NewState);
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}
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/**
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* @brief This function used to enable or disable scamble function
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* @param rf: where rf is a private rf peripheral base address
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* @param NewState: new state of enabling state
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* @return none
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*/
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__STATIC_INLINE void PRI_RF_ScambleEn(PRI_RF_T *rf,FunctionalState NewState)
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{
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PRI_RF_SET_FUNC_ENABLE(rf,R00_CTL,SCR_EN,NewState);
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}
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/**
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* @brief This function used to enable or disable enhance mode2(compatible with nordic)
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* @param rf: where rf is a private rf peripheral base address
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* @param NewState: new state of enabling state
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* @return none
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*/
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__STATIC_INLINE void PRI_RF_NordicEnhanceEn(PRI_RF_T *rf,FunctionalState NewState)
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{
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PRI_RF_SET_FUNC_ENABLE(rf,R00_CTL,NRF_ENHANCE,NewState);
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}
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/**
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* @brief This function used to adjuest enhance mode2 enable or not
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* @param rf: where rf is a private rf peripheral base address
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* @return enable state
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*/
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__STATIC_INLINE uint8_t PRI_RF_IsNordicEnhance(PRI_RF_T *rf)
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{
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return PRI_RF_READ_REG_VALUE(rf,R00_CTL,NRF_ENHANCE);
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}
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/**
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* @brief This function used to enable or disable enhance mode
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* @param rf: where rf is a private rf peripheral base address
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* @param NewState: new state of enabling state
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* @return none
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*/
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__STATIC_INLINE void PRI_RF_EnhanceEn(PRI_RF_T *rf,FunctionalState NewState)
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{
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PRI_RF_SET_FUNC_ENABLE(rf,R00_CTL,ENHANCE,NewState);
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}
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/**
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* @brief This function used to adjuest enhance mode is enable or not
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* @param rf: where rf is a private rf peripheral base address
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* @return enable state
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*/
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__STATIC_INLINE uint8_t PRI_RF_IsEnhance(PRI_RF_T *rf)
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{
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return PRI_RF_READ_REG_VALUE(rf,R00_CTL,ENHANCE);
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}
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/**
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* @brief This function used to set band width, 1Mbps or 2Mbps can selected
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* @param rf: where rf is a private rf peripheral base address
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* @param NewState: state of 2Mbps selected,if 1,2Mbps selected, or 1Mbps selected
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* @return none
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*/
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__STATIC_INLINE void PRI_RF_BandWidth2mSel(PRI_RF_T *rf,FunctionalState NewState)
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{
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PRI_RF_SET_FUNC_ENABLE(rf,R00_CTL,BW_MODE,NewState);
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}
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/**
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* @brief This function used to select chip mode
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* @param rf: where rf is a private rf peripheral base address
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* @param modeSel: chip mode select,including:
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* \ref PRI_RF_CHIP_MODE_INVALID
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* \ref PRI_RF_CHIP_MODE_BLE
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* \ref PRI_RF_CHIP_MODE_297
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* \ref PRI_RF_CHIP_MODE_NORDIC
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* @return none
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*/
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__STATIC_INLINE void PRI_RF_ChipModeSel(PRI_RF_T *rf,uint8_t modeSel)
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{
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PRI_RF_WRITE_REG_VALUE(rf,R00_CTL,CHIP_MODE,modeSel);
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}
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/**
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* @brief This function used to get chip mode
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* @param rf: where rf is a private rf peripheral base address
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* @return chip mode
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*/
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__STATIC_INLINE uint8_t PRI_RF_GetChipMode(PRI_RF_T *rf)
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{
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return PRI_RF_READ_REG_VALUE(rf,R00_CTL,CHIP_MODE);
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}
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/**
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* @brief This function used to enable or disable rx ack if rx with payload
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* @param rf: where rf is a private rf peripheral base address
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* @param NewState: new state of enabling state
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* @return none
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*/
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__STATIC_INLINE void PRI_RF_RxAckEn(PRI_RF_T *rf,FunctionalState NewState)
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{
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PRI_RF_SET_FUNC_ENABLE(rf,R00_CTL,RX_ACK_PAYLOAD_EN,NewState);
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}
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/**
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* @brief This function used to adjust rx ack is enable or not
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* @param rf: where rf is a private rf peripheral base address
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* @return enable state
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*/
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__STATIC_INLINE uint8_t PRI_RF_IsRxAckEn(PRI_RF_T *rf)
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{
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return (rf->R00_CTL & R00_CTL_RX_ACK_PAYLOAD_EN_Msk) >> R00_CTL_RX_ACK_PAYLOAD_EN_Pos;
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}
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/**
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* @brief This function used to enable or disable tx no ack if function enabled and
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* tx works in enhance mode,then rx ack is no needed
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* @param rf: where rf is a private rf peripheral base address
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* @param NewState: new state of enabling state
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* @return none
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*/
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__STATIC_INLINE void PRI_RF_TxNoAckEn(PRI_RF_T *rf,FunctionalState NewState)
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{
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PRI_RF_SET_FUNC_ENABLE(rf,R00_CTL,TX_NOACK_EN,NewState);
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}
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/**
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* @brief This function used to adjuest tx no ack is enable or not
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* @param rf: where rf is a private rf peripheral base address
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* @return tx enable state
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*/
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__STATIC_INLINE uint8_t PRI_RF_IsTxNoAckEn(PRI_RF_T *rf)
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{
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return (rf->R00_CTL & R00_CTL_TX_NOACK_EN_Msk) >> R00_CTL_TX_NOACK_EN_Pos;
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}
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/**
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* @brief This function used to enable tx or rx function
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* @param rf: where rf is a private rf peripheral base address
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* @param NewState: new state of function control state,if enabled,rx function enabled,
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* or tx function enabled
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* @return none
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*/
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__STATIC_INLINE void PRI_RF_TrxFuncSel(PRI_RF_T *rf,FunctionalState NewState)
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{
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PRI_RF_SET_FUNC_ENABLE(rf,R00_CTL,PRI_RX,NewState);
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}
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/**
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* @brief This function used to adjust rx function is enable or not
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* @param rf: where rf is a private rf peripheral base address
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* @return none
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*/
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__STATIC_INLINE uint8_t PRI_RF_IsRxSel(PRI_RF_T *rf)
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{
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return PRI_RF_READ_REG_VALUE(rf,R00_CTL,PRI_RX);
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}
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/**
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* @brief This function used to enable or disable all interrupt clear function
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* @param rf: where rf is a private rf peripheral base address
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* @param NewState: new state of enabling state
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* @return none
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*/
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__STATIC_INLINE void PRI_RF_ClearAllIrqEn(PRI_RF_T *rf,FunctionalState NewState)
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{
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PRI_RF_SET_FUNC_ENABLE(rf,R01_INT,IRQ_CLR_EN,NewState);
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}
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/**
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* @brief This function used to set interrupt mask
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* @param rf: where rf is a private rf peripheral base address
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* @param msk: interrupt mask bit,including:
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* R01_INT_CTL_RX_CRC_ERR_MASK_Msk
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* R01_INT_CTL_TX_TIMEOUT_IRQ_MASK_Msk
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* R01_INT_CTL_TX_IRQ_MASK_Msk
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* R01_INT_CTL_RX_IRQ_MASK_Msk
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* @param NewState: new state of interrupt mask
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* @return none
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*/
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__STATIC_INLINE void PRI_RF_IntMask(PRI_RF_T *rf,uint32_t msk,FunctionalState NewState)
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{
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(NewState)?(rf->R01_INT |= msk):(rf->R01_INT &= ~msk);
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}
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/**
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* @brief This function used to read interrupt flag
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* @param rf: where rf is a private rf peripheral base address
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* @param msk: interrupt flag bit,including:
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* R01_INT_CTL_RX_CRC_ERR_Msk
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* R01_INT_CTL_TX_TIMEOUT_IRQ_Msk
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* R01_INT_CTL_TX_IRQ_Msk
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* R01_INT_CTL_RX_IRQ_Msk
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* @return true,interrupt happened
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* @return false,interrupt does not happened
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*/
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__STATIC_INLINE bool PRI_RF_IntFlag(PRI_RF_T *rf,uint32_t msk)
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{
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return (rf->R01_INT & msk)?(true):(false);
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}
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/**
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* @brief This function used to force exit rx mode
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* @param rf: where rf is a private rf peripheral base address
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* @param NewState: new state of force exit function
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* @return none
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*/
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__STATIC_INLINE void PRI_RF_ForceExitRx(PRI_RF_T *rf,FunctionalState NewState)
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{
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PRI_RF_SET_FUNC_ENABLE(rf,R01_INT,EXIT_RX,NewState);
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}
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/**
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* @brief This function used to set tx& rx transmit wait time
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* @param rf: where rf is a private rf peripheral base address
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* @param NewState: new state of enabling state
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* @return none
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*/
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__STATIC_INLINE void PRI_RF_SetTrxTransWaitTime(PRI_RF_T *rf,uint16_t time)
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{
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PRI_RF_WRITE_REG_VALUE(rf,R02_TMR_CTL,TRX_TRANS_WAIT_TIME,time);
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}
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/**
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* @brief This function used to set tx& rx transmit wait time
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* @param rf: where rf is a private rf peripheral base address
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* @param pipe: where pipe is a rx pipe number, valid 0~7
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* @param NewState: new state of enabling state
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* @return none
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*/
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__STATIC_INLINE void PRI_RF_EnableRxPipeAdr(PRI_RF_T *rf,uint16_t pipe, FunctionalState NewState)
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{
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if (NewState)
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rf->R10_RX_ADDR_EN |= (0x1ul << (R10_RX_ADDR0_EN_Pos + pipe));
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else
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rf->R10_RX_ADDR_EN &= ~(0x1ul << (R10_RX_ADDR0_EN_Pos + pipe));
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}
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__STATIC_INLINE void PRI_RF_SetRxGoon(PRI_RF_T *rf, uint8_t en_flag)
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{
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PRI_RF_WRITE_REG_VALUE(rf, R01_INT, PRI_RX_GOON, en_flag);
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}
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__STATIC_INLINE void PRI_RF_SetAddrMatchBit(PRI_RF_T *rf, uint8_t value)
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{
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PRI_RF_WRITE_REG_VALUE(rf, R11_CFG, ADDR_ERR_THR, value);
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}
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__STATIC_INLINE void PRI_RF_SetPayloadEndian(PRI_RF_T *rf, uint8_t endian)
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{
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PRI_RF_WRITE_REG_VALUE(rf, R01_INT, PRI_ENDIAN, endian);
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}
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__STATIC_INLINE void PRI_RF_MultiPreamble(PRI_RF_T *rf, uint8_t pre_length)
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{
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PRI_RF_WRITE_REG_VALUE(rf, R11_CFG, PREAM_2BYTE_EN, 1);
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PRI_RF_WRITE_REG_VALUE(rf, R11_CFG, B250K_PREAM, pre_length); // preamble length ctrl
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}
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__STATIC_INLINE void PRI_RF_StopRx(PRI_RF_T *rf, uint8_t en_flag)
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{
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PRI_RF_WRITE_REG_VALUE(rf, R01_INT, EXIT_RX, en_flag); // stop rx
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}
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__STATIC_INLINE void PRI_RF_RandomNumGenInit(PRI_RF_T *rf)
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{
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rf->RNG1 |= RNG1_RNG_EN_Msk;
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}
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__STATIC_INLINE void PRI_RF_RandomNumGenReinit(PRI_RF_T *rf)
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{
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rf->RNG1 &= ~(RNG1_RNG_EN_Msk | RNG1_RNG_RING_SCRMB_SEL_Msk);
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}
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__STATIC_INLINE uint32_t PRI_RF_GetRandomNum(PRI_RF_T *rf)
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{
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return rf->RNG2;
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}
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/**
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* @brief This function used to enable private radio ldo
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* @return none
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*/
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void ana_prf_ldo_en(void);
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/**
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* @brief This function used to disable private radio ldo
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* @return none
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*/
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void ana_prf_ldo_dis(void);
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/**
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* @brief This function used to set private rf payload lenth
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* @param rf: where rf is a private rf peripheral base address
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* @param mode: tx or rx mode select,including:
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* \ref PRI_RF_MODE_SEL_TX
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* \ref PRI_RF_MODE_SEL_RX
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* @param len: payload lenth
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* @retval none
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*/
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void PRI_RF_SetTrxPayloadLen(PRI_RF_T *rf,uint8_t mode,uint8_t len);
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/**
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* @brief This function used to set private rf address byte lenth
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* @param rf: where rf is a private rf peripheral base address
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* @param len: address byte lenth ,including:
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* \ref PRI_RF_ADDR_BYTE_LEN_2
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* \ref PRI_RF_ADDR_BYTE_LEN_3
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* \ref PRI_RF_ADDR_BYTE_LEN_4
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* \ref PRI_RF_ADDR_BYTE_LEN_5
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* @retval none
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*/
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void PRI_RF_SetAddrByteLen(PRI_RF_T *rf,uint8_t len);
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/**
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* @brief This function used to set pid manual
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* @param rf: where rf is a private rf peripheral base address
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* @param mode: tx or rx mode select,including:
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* PRI_RF_MODE_SEL_TX
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* PRI_RF_MODE_SEL_RX
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* @param pid: pid value
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* @retval none
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*/
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void PRI_RF_SetPidManual(PRI_RF_T *rf,uint8_t mode,uint8_t pid);
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/**
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* @brief This function used to set rx wait time
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* @param rf: where rf is a private rf peripheral base address
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* @param NewState: new state of enabling state
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* @retval none
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*/
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void PRI_RF_SetRxWaitTime(PRI_RF_T *rf,uint16_t time);
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/**
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* @brief This function used to set private rf tx or rx address
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* @param rf: where rf is a private rf peripheral base address
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* @param mode: tx or rx mode select,including:
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* PRI_RF_MODE_SEL_TX
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* PRI_RF_MODE_SEL_RX
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* PRI_RF_MODE_SEL_TRX
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* @param pipe: where pipe is a rx pipe selection, 1 bit represents a channel
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* example: pipe set 7, pipe0\pipe1\pipe2 address need set a value
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* @param addr: addr base address
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* @retval none
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*/
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void PRI_RF_SetTrxAddr(PRI_RF_T *rf,uint8_t mode,uint8_t pipe,uint32_t *addr);
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/**
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* @brief This function used to set private rf tx or rx ram start address
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* @param rf: where rf is a private rf peripheral base address
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* @param mode: tx or rx mode select,including:
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* \ref PRI_RF_MODE_SEL_TX
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* \ref PRI_RF_MODE_SEL_RX
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* \ref PRI_RF_MODE_SEL_TRX
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* @param addr: addr base address
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* @retval none
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*/
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void PRI_RF_SetTrxRamStartAddr(PRI_RF_T *rf,uint8_t mode,uint32_t addr);
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/**
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* @brief This function used to adjust private rf tx or rx ram state is ready or not
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* @param rf: where rf is a private rf peripheral base address
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* @param mode: tx or rx mode select,including:
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* \ref PRI_RF_MODE_SEL_TX
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* \ref PRI_RF_MODE_SEL_RX
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* \ref PRI_RF_MODE_SEL_TRX
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* @retval true ram is ready
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* @retval false ram is not ready
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*/
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bool PRI_RF_IsTrxRamReady(PRI_RF_T *rf,uint8_t mode);
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/**
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* @brief This function used to set private rf ram ready state
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* @param rf: where rf is a private rf peripheral base address
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* @param mode: tx or rx mode select,including:
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* \ref PRI_RF_MODE_SEL_TX
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* \ref PRI_RF_MODE_SEL_RX
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* \ref PRI_RF_MODE_SEL_TRX
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* @param ready: ready state
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* @retval none
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*/
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void PRI_RF_SetTrxRamReady(PRI_RF_T *rf,uint8_t mode,uint8_t ready);
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/**@} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __PRI_RF_H__ */
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