#include <stddef.h>
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#include "FreeRTOS.h"
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#include "task.h"
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#include "nimble/nimble_port.h"
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#include "nimble_syscfg.h"
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#include "nimble/ble.h"
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#include "nimble/pan107x/nimble_glue_spark.h"
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#include "nimble/hci_common.h"
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#include "pan_ble_stack.h"
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#include "pan_svc_call.h"
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#include "comm_prf.h"
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#if CONFIG_PM && (CONFIG_LOW_SPEED_CLOCK_SRC == 2)
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#error "[Allert]LP 32K Clock in ACT32K mode cannot be enabled in low power mode.!!!"
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#endif
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#if (configUSE_TICKLESS_IDLE == 1)
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extern void UpdateTickAndSch(void);
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#endif
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static TaskHandle_t host_task_h;
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static uint8_t ll_enable = false;
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#define CONFIG_BT_CTLR_MAX_MST_CONN CONFIG_BT_MAX_NUM_OF_CENTRAL
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#define CONFIG_BT_CTLR_MAX_SLV_CONN CONFIG_BT_MAX_NUM_OF_PERIPHERAL
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#if NIMBLE_BLE_SM
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#define CONFIG_BT_CTLR_LL_ENC_TIME 200
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#else
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#define CONFIG_BT_CTLR_LL_ENC_TIME 100
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#endif
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#define CONFIG_BT_CTLR_MST_CONN_MARGN 6
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#if CONFIG_LOW_SPEED_CLOCK_SRC == 0
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#define BLE_SCA 1000
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#else
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#define BLE_SCA 50
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#endif
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#ifdef IP_107x
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#if CONFIG_SMP_OTA
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#define PAN_BLE_CTLR_BUFFER_ALLOC (4748)
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#elif CONFIG_BLE_MULTI_ROLE
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#define PAN_BLE_CTLR_BUFFER_ALLOC (6300)
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#elif ((CONFIG_BT_CTLR_MAX_MST_CONN > 1) || (CONFIG_BT_CTLR_MAX_SLV_CONN > 1))
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#define PAN_BLE_CTLR_BUFFER_ALLOC (5500)
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#elif CONFIG_THROUGHPUT_TEST
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#define PAN_BLE_CTLR_BUFFER_ALLOC (5624)
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#else
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#define PAN_BLE_CTLR_BUFFER_ALLOC (4332)
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#endif
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#elif defined(IP_101x)
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#define PAN_BLE_CTLR_BUFFER_ALLOC (2500)
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#endif
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#define PAN_BLE_CTLR_BUFFER_SIZE (((PAN_BLE_CTLR_BUFFER_ALLOC) +3) & (~((uint32_t)0x03))) /*4 bytes aligned*/
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static uint32_t mem_buffer[PAN_BLE_CTLR_BUFFER_SIZE / 4];
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static uint32_t mem_pos = 0;
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#if CONFIG_CNTRL_MEM_POOL_PRINT
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static uint32_t mem_pool_usage = 0;
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#endif
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static void *mem_alloc(uint32_t size)
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{
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void *mem_ret = NULL;
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char *p_mem = (char *)mem_buffer;
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if (PAN_BLE_CTLR_BUFFER_SIZE - mem_pos >= size) {
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mem_ret = &p_mem[mem_pos];
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mem_pos += size;
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} else {
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configASSERT(0);
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}
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#if CONFIG_CNTRL_MEM_POOL_PRINT
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mem_pool_usage += size;
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printf("BT controller memory pool used: %d bytes, remain bytes: %d, total:%d \n", mem_pool_usage, PAN_BLE_CTLR_BUFFER_SIZE - mem_pool_usage, PAN_BLE_CTLR_BUFFER_SIZE);
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#endif
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return mem_ret;
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}
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pan_ble_cfg ble_cfg = {
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.sleep_clock_source = CONFIG_LOW_SPEED_CLOCK_SRC, /* CONFIG_BT_CTLR_SLEEP_CLOCK_SOURCE,*/
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.sleep_clock_accuracy = BLE_SCA,
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.max_num_of_states = 0, /*unused param*/
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.tx_power = CONFIG_BT_CTLR_TX_POWER_DFT,
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.pf_mem_init = mem_alloc,
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#if (CONFIG_BT_CTLR_LINK_LAYER_DEBUG)
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.link_layer_debug = true,
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#else
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.link_layer_debug = false,
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#endif
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.agc_cfg_mode = 0,
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#if CONFIG_PM
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.pmEnable = true,
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#endif
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.mstMargin = CONFIG_BT_CTLR_MST_CONN_MARGN,
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.wlNum = 1,
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.rlNum = 1,
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.maxMst = CONFIG_BT_CTLR_MAX_MST_CONN,
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.maxSlv = CONFIG_BT_CTLR_MAX_SLV_CONN,
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// .maxAclLen = (MYNEWT_VAL_BLE_TRANSPORT_ACL_SIZE - 4), /*should adjust PAN_BLE_CTLR_BUFFER_ALLOC size*/
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#ifdef IP_107x
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#if CONFIG_SMP_OTA
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.maxAclLen = CONFIG_BLE_ACL_RX_SIZE,
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.numRxBufs = 8,
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.numTxBufs = 8,
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.numMoreData = 5,
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#elif CONFIG_THROUGHPUT_TEST
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.maxAclLen = CONFIG_BLE_ACL_RX_SIZE,
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.numRxBufs = 8,
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.numTxBufs = 8,
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.numMoreData = 6,
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#elif CONFIG_BLE_MULTI_ROLE
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.maxAclLen = CONFIG_BLE_ACL_RX_SIZE,
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.numRxBufs = 16,
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.numTxBufs = 8,
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.numMoreData = 4,
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#else
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.maxAclLen = 27,
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.numRxBufs = 16,
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.numTxBufs = 16,
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.numMoreData = 4,
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#endif
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#elif defined(IP_101x)
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.maxAclLen = 80,
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.numRxBufs = 8,
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.numTxBufs = 16,
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.numMoreData = 6,
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#endif
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.llEncTime = CONFIG_BT_CTLR_LL_ENC_TIME,
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};
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CONFIG_RAM_CODE int ll_semphr_cback(void)
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{
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NVIC_EnableIRQ(BLE_EVENT_PROC_IRQn);
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NVIC_SetPendingIRQ(BLE_EVENT_PROC_IRQn);
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return 0;
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}
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void ble_hs_thread_entry(void *parameter)
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{
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nimble_port_run();
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}
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void hs_thread_init(void)
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{
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xTaskCreate(ble_hs_thread_entry, "host", MYNEWT_VAL(BLE_HOST_THREAD_STACK_SIZE),
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NULL, configMAX_PRIORITIES - os_priority_low, &host_task_h);
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}
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void vApplicationUserHook(void)
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{
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if(ll_enable){
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pan_update_stimer();
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}
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}
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int host_copydata(void *from, void *dst, uint16_t len)
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{
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struct os_mbuf *om = from;
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return os_mbuf_copydata(om, 0, OS_MBUF_PKTLEN(om), dst);
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}
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void ble_hci_evt_ll_to_host_cbk(uint8_t *p_evt, uint16_t evt_len)
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{
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void *buf;
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if (p_evt[2] == BLE_HCI_LE_SUBEV_ADV_RPT) {
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buf = ble_transport_alloc_evt(1);
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} else {
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buf = ble_transport_alloc_evt(0);
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}
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if (buf) {
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memcpy(buf, p_evt, evt_len);
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ble_transport_to_hs_evt(buf);
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}
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}
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void ble_hci_acl_ll_to_host_cbk(uint8_t *p_acl, uint16_t acl_len)
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{
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int ret;
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struct os_mbuf *om;
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om = ble_transport_alloc_acl_from_ll();
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if (om) {
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ret = os_mbuf_append(om, p_acl, acl_len);
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if (ret) {
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os_mbuf_free_chain(om);
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} else {
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ble_transport_to_hs_acl(om);
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}
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}
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else{
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APP_TRACK_ERR("Host transport alloc ACL buffer failed\n");
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}
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}
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void ll_init(void)
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{
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printf("LL Spark Controller Version:%07x\n", pan_ble_get_version()->commit_id);
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pan_ll_register_hostcopy_cb(host_copydata);
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pan_ll_register_semphr_cback(ll_semphr_cback);
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pan_ble_hci_init(ble_hci_evt_ll_to_host_cbk, ble_hci_acl_ll_to_host_cbk);
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pan_ble_init(&ble_cfg);
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ll_enable = true;
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}
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int ble_transport_to_ll_acl_impl(struct os_mbuf *om)
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{
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int rc = 0;
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rc = pan_ble_hci_acl_nimble_handle((void *)om, OS_MBUF_PKTLEN(om));
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os_mbuf_free_chain(om);
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return (rc != 0) ? BLE_ERR_MEM_CAPACITY : 0;
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}
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int ble_transport_to_ll_cmd_impl(void *buf)
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{
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int rc;
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struct ble_hci_cmd *cmd = buf;
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pan_ble_hci_cmd_handle(buf, sizeof(struct ble_hci_cmd) + cmd->length, 0, 0);
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ble_transport_free(cmd);
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return (rc < 0) ? BLE_ERR_MEM_CAPACITY : 0;
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}
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void TRIM_IRQHandler(void)
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{
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printf("trim\n");
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}
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CONFIG_RAM_CODE void BLE_EVENT_PROC_IRQ(void)
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{
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pan_ble_handle();
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#if (configUSE_TICKLESS_IDLE == 1)
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UpdateTickAndSch();
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#endif
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}
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CONFIG_RAM_CODE void LL_IRQHandler(void)
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{
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#ifdef PRF_BLE_DUAL_MODE
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if (panchip_prf_ble_handler()) {
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return;
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}
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#endif
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pan_ble_irq();
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}
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uint32_t db_set_bd_address(uint8_t *bd_addr)
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{
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LL_SetBdAddr(bd_addr, 6);
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return 0;
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}
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