国产蓝牙芯片的仓库
blame | 历史 | 原始文档
WXK
2024-12-16 78e84fcf264afd731cd66c807d9fcb690fe12126 
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Ø    I˜LïÙ/#.\configuration\app_config_spark.hºÝµ5Ù7+..\..\..\..\os\freertos\include\FreeRTOS.hºÝµ+Ù9-C:\Keil_v5\ARM\ARMCC\Bin\..\include\stddef.hÜ Íò@Ù9-C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.hÜ Íò$Ù-!.\configuration\FreeRTOSConfig.hºÝµ¯Ù^R..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\PanSeries.hºÝµHÙ8,C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.hÜ Íò™Ù9-C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdlib.hÜ Íò8Ù9-C:\Keil_v5\ARM\ARMCC\Bin\..\include\string.hÜ Íò#Ù\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\core_cm0.hºÝµÿÙaU..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\cmsis_version.hºÝµyÙbV..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\cmsis_compiler.hºÝµ"Ù_S..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\cmsis_armcc.hºÝµ}ÙeY..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\system_PanSeries.hºÝµ6Ù:.C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdbool.hÜ ÍòÁÙ`T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_sys_log.hºÝµ0Ù\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_sys.hºÝµÙÙ\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_clk.hºÝµþÙ\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_adc.hºÝµÞÙ\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_fmc.hºÝµÐÙ]Q..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_dmac.hºÝµoÙ]Q..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_gpio.hºÝµUÙ\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_spi.hºÝµºÙ]Q..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_uart.hºÝµHÙ\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_i2c.hºÝµÙ^R..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_timer.hºÝµáÙ\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_pwm.hºÝµ²Ù\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_wdt.hºÝµ·Ù]Q..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_wwdt.hºÝµ>Ù[O..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_lp.hºÝµ^Ù^R..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_efuse.hºÝµÙfZ..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\radio\prf_lib\include\pan_pri_rf.hºÝµ©Ù^R..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\PanSeries.hºÝµHÙ`T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_clktrim.hºÝµ:Ù^R..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_power.hºÝµÙ\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal.hºÝµÑÙaU..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_gpio.hºÝµ¹Ù`T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_def.hºÝµ;ÙaU..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_uart.hºÝµ¬ÙaU..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_dmac.hºÝµÓÙ`T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_spi.hì˜Æ¶,Ù`T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_i2c.hºÝµlÙ`T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_wdt.hºÝµÙaU..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_wwdt.hºÝµ¢Ù`T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_pwm.hºÝµÙbV..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_timer.hºÝµEÙ`T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_adc.hºÝµBÙ.".\configuration\pan_host_config.hºÝµœÙ7+..\..\..\..\os\freertos\include\projdefs.hºÝµ˜Ù7+..\..\..\..\os\freertos\include\portable.hºÝµœÙE9..\..\..\..\os\freertos\include\deprecated_definitions.hºÝµÍÙF:..\..\..\..\os\freertos\portable\RVDS\ARM_CM0\portmacro.hºÝµ•Ù;/..\..\..\..\os\freertos\include\mpu_wrappers.hºÝµÈÙ3'..\..\..\..\os\freertos\include\task.hºÝµJÙ3'..\..\..\..\os\freertos\include\list.hºÝµAÙMA..\..\..\..\os\freertos\portable\RVDS\ARM_CM0\pan107x\os_setup.cºÝµGÙPD..\..\..\..\host\nimble\porting\nimble\include\nimble/nimble_port.hºÝµgÙG;..\..\..\..\host\nimble\nimble\include\nimble/nimble_npl.hºÝµSÙXL..\..\..\..\host\nimble\porting\npl\freertos\include\nimble/nimble_npl_os.hºÝµøÙ9-C:\Keil_v5\ARM\ARMCC\Bin\..\include\assert.hÚ Íò*Ù4(..\..\..\..\os\freertos\include\queue.hºÝµÖÙ5)..\..\..\..\os\freertos\include\semphr.hºÝµjÙ5)..\..\..\..\os\freertos\include\timers.hºÝµeÙWK..\..\..\..\host\nimble\porting\npl\freertos\include\nimble/npl_freertos.hºÝµHÙH<..\..\..\..\controller\pan107x_spark\include\pan_svc_call.hºÝµ'ÙL@..\..\..\..\controller\pan107x_spark\include\utils\defs_types.hºÝµAÙG;..\..\..\..\controller\pan107x_spark\include\utils/track.hºÝµ™Ù9-C:\Ke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"ÉV¤Ú 


"ÉC·Ú 


"ÉZ Ú 


"ÉN¬Ú "Èb‡Ú 


"Èw„Ú


xPSR_TypeÚPxPSR_N_PosÚPxPSR_N_MskÚPxPSR_Z_PosÚPxPSR_Z_MskÚPxPSR_C_PosÚPxPSR_C_MskÚPxPSR_V_PosÚPxPSR_V_MskÚPxPSR_T_PosÚPxPSR_T_Msk ÚP xPSR_ISR_PoshÚP xPSR_ISR_MskoÚ8


<unnamed>SÚ8


<unnamed>QÚ 


"â_reserved0àÚ 


"âSPSELRÚ 


"â_reserved1ßÚ "ábnÚ 


"áwkÚ CONTROL_TypeÇÚPCONTROL_SPSEL_PosÚPCONTROL_SPSEL_MskÚ8


<unnamed>QÚ <"ëISERmÚ <"|ë


RESERVED0ŽÚ <"ëICER}Ú <"|ë


RESERVED1Ú <"ëISPRbÚ <"|ë


RESERVED2ŒÚ <"ëICPRrÚ <"|ë


RESERVED3‹Ú <"€ë


RESERVED4ƒÚ  <" ëIPïÚ


NVIC_Type¾Ú8


<unnamed>QÚ 


"÷CPUIDOÚ 


"÷ICSR•Ú 


"÷


RESERVED0,Ú 


"÷AIRCRSÚ 


"÷SCRàÚ 


"÷CCRðÚ 


"÷


RESERVED1+Ú <"÷SHP§Ú 


"÷SHCSRAÚ    SCB_TypeÚ"PSCB_CPUID_IMPLEMENTER_Pos»Ú"PSCB_CPUID_IMPLEMENTER_MskÂÚPSCB_CPUID_VARIANT_PosðÚPSCB_CPUID_VARIANT_Msk÷Ú#PSCB_CPUID_ARCHITECTURE_PosxÚ#PSCB_CPUID_ARCHITECTURE_MskÚPSCB_CPUID_PARTNO_Pos3ÚPSCB_CPUID_PARTNO_Msk:ÚPSCB_CPUID_REVISION_Pos”ÚPSCB_CPUID_REVISION_Msk›Ú PSCB_ICSR_NMIPENDSET_PosNÚ PSCB_ICSR_NMIPENDSET_MskUÚPSCB_ICSR_PENDSVSET_Pos‹ÚPSCB_ICSR_PENDSVSET_Msk’ÚPSCB_ICSR_PENDSVCLR_Pos–ÚPSCB_ICSR_PENDSVCLR_MskÚPSCB_ICSR_PENDSTSET_PosÚPSCB_ICSR_PENDSTSET_Msk”ÚPSCB_ICSR_PENDSTCLR_Pos˜ÚPSCB_ICSR_PENDSTCLR_MskŸÚ PSCB_ICSR_ISRPREEMPT_Pos:Ú PSCB_ICSR_ISRPREEMPT_MskAÚ PSCB_ICSR_ISRPENDING_PosRÚ PSCB_ICSR_ISRPENDING_MskYÚ!PSCB_ICSR_VECTPENDING_PosÚ!PSCB_ICSR_VECTPENDING_MskÚ PSCB_ICSR_VECTACTIVE_PosWÚ PSCB_ICSR_VECTACTIVE_Msk^ÚPSCB_AIRCR_VECTKEY_PosîÚPSCB_AIRCR_VECTKEY_MskõÚ"PSCB_AIRCR_VECTKEYSTAT_PosªÚ"PSCB_AIRCR_VECTKEYSTAT_Msk±Ú PSCB_AIRCR_ENDIANESS_PoskÚ PSCB_AIRCR_ENDIANESS_MskrÚ"PSCB_AIRCR_SYSRESETREQ_Pos—Ú"PSCB_AIRCR_SYSRESETREQ_MskžÚ$PSCB_AIRCR_VECTCLRACTIVE_Pos.Ú$PSCB_AIRCR_VECTCLRACTIVE_Msk5ÚPSCB_SCR_SEVONPEND_PosàÚPSCB_SCR_SEVONPEND_MskçÚPSCB_SCR_SLEEPDEEP_PosûÚPSCB_SCR_SLEEPDEEP_MskÚ PSCB_SCR_SLEEPONEXIT_Pos>Ú PSCB_SCR_SLEEPONEXIT_MskEÚPSCB_CCR_STKALIGN_PosGÚPSCB_CCR_STKALIGN_MskNÚ PSCB_CCR_UNALIGN_TRP_Pos;Ú PSCB_CCR_UNALIGN_TRP_MskBÚ#PSCB_SHCSR_SVCALLPENDED_PosxÚ#PSCB_SHCSR_SVCALLPENDED_MskÚ8


<unnamed>QÚ 


"´CTRLÓÚ 


"´LOADèÚ 


"´VAL'Ú 


"´CALIB«Ú SysTick_TypeÚ#PSysTick_CTRL_COUNTFLAG_Pos¦Ú#PSysTick_CTRL_COUNTFLAG_Msk­Ú#PSysTick_CTRL_CLKSOURCE_PosžÚ#PSysTick_CTRL_CLKSOURCE_Msk¥Ú!PSysTick_CTRL_TICKINT_Pos7Ú!PSysTick_CTRL_TICKINT_Msk>Ú PSysTick_CTRL_ENABLE_Pos¨Ú PSysTick_CTRL_ENABLE_Msk¯Ú PSysTick_LOAD_RELOAD_Pos­Ú PSysTick_LOAD_RELOAD_Msk´Ú PSysTick_VAL_CURRENT_Pos~Ú PSysTick_VAL_CURRENT_Msk…Ú PSysTick_CALIB_NOREF_Pos¯Ú PSysTick_CALIB_NOREF_Msk¶ÚPSysTick_CALIB_SKEW_PosñÚPSysTick_CALIB_SKEW_MskøÚ PSysTick_CALIB_TENMS_Pos¢Ú PSysTick_CALIB_TENMS_Msk©ÚP    _VAL2FLDqÚP    _FLD2VALqÚP    SCS_BASEXÚP SysTick_BASEoÚP


NVIC_BASEÚP    SCB_BASEiÚPSCBíÚPSysTickóÚ PNVIC“ÚPCMSIS_NVIC_VIRTUALÚ!PNVIC_SetPriorityGrouping3Ú!PNVIC_GetPriorityGrouping?ÚPNVIC_EnableIRQíÚPNVIC_GetEnableIRQÇÚPNVIC_DisableIRQ~ÚPNVIC_GetPendingIRQGÚPNVIC_SetPendingIRQ;ÚPNVIC_ClearPendingIRQ|ÚPNVIC_SetPriorityŽÚPNVIC_GetPriorityšÚPNVIC_SystemReset”ÚPCMSIS_VECTAB_VIRTUALˆÚPNVIC_SetVectorÚPNVIC_GetVectorÚPNVIC_USER_IRQ_OFFSETdÚPEXC_RETURN_HANDLER+ÚPEXC_RETURN_THREAD_MSPÚPEXC_RETURN_THREAD_PSPÚP_BIT_SHIFTœÚP    _SHP_IDX-ÚP_IP_IDXÚ#P__NVIC_SetPriorityGroupingqÚ#P__NVIC_GetPriorityGrouping}Ú__NVIC_EnableIRQTÚ,""íIRQnTÚ__memory_changedHÚ__NVIC_GetEnableIRQ.Ú,""ðIRQnQÚ__NVIC_DisableIRQåÚ,""òIRQnOÚ__schedule_barriersÚ__dsbçÚ__isbâÚ__NVIC_GetPendingIRQ®Ú,""÷IRQnJÚ__NVIC_SetPendingIRQ¢Ú,""ùIRQnHÚ__NVIC_ClearPendingIRQãÚ,""ûIRQnFÚ__NVIC_SetPriorityõÚ,""ýIRQnDÚ,


"ý    priority)Ú__NVIC_GetPriorityÚ,""€IRQnÀÚNVIC_EncodePriorityÚ,


"‚PriorityGroup¬Ú,


"‚PreemptPriorityØÚ,


"‚SubPriority“Ú


"‚PriorityGroupTmp™Ú


"‚PreemptPriorityBitsbÚ


"‚SubPriorityBitsÚNVIC_DecodePriority™Ú,


"‰    Priority¼Ú,


"‰PriorityGroup¥Ú,"‰pPreemptPriorityQÚ,"‰ pSubPriorityÚ


"‰PriorityGroupTmp’Ú


"‰PreemptPriorityBits[Ú


"‰SubPriorityBitsÚ__NVIC_SetVectorèÚ,""‘IRQn¯Ú,


"‘vector‡Ú


"‘vectors6Ú__NVIC_GetVectorôÚ,""•IRQn«Ú


"•vectors2Ú__NVIC_SystemResetûÚ__nopÓÚSCB_GetFPUTypeôÚSysTick_ConfigYÚ,


"›ticksôÚP__SYSTEM_PANSERIES_H__ŽÚ&P__bool_true_false_are_definedÙÚ PboolÚ PtrueÚPfalse¶Ú8_adc_vbg_kb^Ú "¢


adc_vbg_k}Ú "¢


adc_vbg_bˆÚ ADC_VBG_KB_TDÚ8_otp_structûÚ <"€¦d8ÌÚ8


<unnamed>QÚ <"¨rsvd0ÖÚ "¨ pmu_vbg_trimÿÚ "¨rsvd1(Ú "¨pmu_vbg_volt_l'Ú "¨pmu_vbg_volt_h+Ú "¨hp_ldo_trim{Ú "¨hp_ldo_volt_l£Ú "¨hp_ldo_volt_h§Ú "¨ lph_ldo_trim Ú "¨lph_ldo_volt_l5Ú "¨lph_ldo_volt_h9Ú "¨ lpl_ldo_trim    Ú "¨lpl_ldo_volt_l1Ú "¨lpl_ldo_volt_h5Ú "¨flash_ldo_trim?Ú "¨rsvd2'Ú "¨flash_ldo_volt_lgÚ "¨flash_ldo_volt_hkÚ "¨ ana_ldo_trim!Ú "¨rffe_ldo_trim¬Ú "¨fsyn_ldo_trimÚ "¨ adc_ldo_trim)Ú "¨ vco_ldo_trim    Ú "¨ipoly_trimÆÚ "¨rsvd3&Ú "¨bod_vref_trim¦Ú "¨rsvd4%Ú "¨bod_vref_volt_lÎÚ "¨bod_vref_volt_hÒÚ "¨adc_vbg_1v17_trim±Ú "¨rsvd5$Ú "¨adc_vbg_1v17_voltŸÚ "¨adc_vbg_1v20_trim·Ú "¨rsvd6#Ú "¨adc_vbg_1v20_volt¥Ú "¨    rch_trimºÚ 


"¨    rch_freqÁÚ "¨rcl_coarse_trimÌÚ "¨rsvd7"Ú "¨rcl_fine_trim«Ú "¨    rcl_freq»Ú "¨xth_xocap_amÚ "¨xth_xocap_maÚ "¨xth_xocap_n`Ú "¨xtl_xocap_aiÚ "¨xtl_xocap_m]Ú "¨xtl_xocap_n\Ú "¨buck_imax_cal_trim¡Ú "¨rsvd8!Ú "¨buck_zero_cal_trimÚ "¨rsvd9 Ú "¨buck_out_trim‘Ú "¨rsvd10öÚ "¨buck_vout_voltÚ "¨


adc_vdd_kxÚ "¨


adc_vdd_bŒÚ "¨


adc_vbg_kwÚ "¨


adc_vbg_b‚Ú "¨adc_temp_voltžÚ "¨current_temp_valuecÚ "¨ battery_trimôÚ# "¨pa_power_calib_trim_6dbmXÚ# "¨pa_power_calib_trim_0dbm^Ú <"¨    mac_addr¬Ú <"    ¨uidœÚ "¨


chip_infoaÚ "¨cp_versionÖÚ "¨ft_versionÏÚ "¨ cp_pass_flag(Ú "¨ ft_pass_flag!Ú "¨cp_checksum‡Ú "¨ft_checksum€Ú <"¨ user_rw_dataÑÚ  "€¦mÚ8


<unnamed>QÚ <"órsvd0‹Ú "ó pmu_vbg_trim´Ú "órsvd1ÝÚ "ópmu_vbg_volt_lÜÚ "ópmu_vbg_volt_hàÚ "óhp_ldo_trim0Ú "óhp_ldo_volt_lXÚ "óhp_ldo_volt_h\Ú "ó lph_ldo_trimÂÚ "ólph_ldo_volt_lêÚ "ólph_ldo_volt_hîÚ "ó lpl_ldo_trim¾Ú "ólpl_ldo_volt_læÚ "ólpl_ldo_volt_hêÚ "óflash_ldo_trimôÚ "órsvd2ÜÚ "óflash_ldo_volt_lÚ "óflash_ldo_volt_h Ú "ó ana_ldo_trimÖÚ "órffe_ldo_trimaÚ "ófsyn_ldo_trimDÚ "ó adc_ldo_trimÞÚ "ó vco_ldo_trim¾Ú "óipoly_trim{Ú "órsvd3ÛÚ "óbod_vref_trim[Ú "órsvd4ÚÚ "óbod_vref_volt_lƒÚ "óbod_vref_volt_h‡Ú "órsvd5ÙÚ "ó    xtl_coregÚ "ó


xth_icoreÚ "ó    rch_biasŒÚ "ódpll_vco_freq_trim8Ú "ódpll_kvco_ctrléÚ "ódpll_icp_ctrlbÚ "ódpll_icp_biasxÚ "órsvd6ØÚ "óadc_vbg_1v20_trimlÚ "óptat_temp_trimÒÚ "óadc_vbg_1v20_voltZÚ "ó    rch_trimoÚ 


"ó    rch_freqvÚ "órcl_coarse_trimÚ "ólph_ldo_vref_trim¦Ú "órsvd7×Ú "órcl_fine_trim`Ú "ó    rcl_freqpÚ "óanalog_temp_voltÚ <"


ó


rsvd_0x3e(Ú "óanalog_0p6v_voltmÚ <"


órsvd8—Ú "óbuck_imax_cal_trimVÚ "órsvd9ÕÚ "óbuck_zero_cal_trimEÚ "órsvd10«Ú "óbuck_out_trimFÚ "órsvd11ªÚ "óbuck_vout_volt¼Ú "ó


adc_vdd_k-Ú "ó


adc_vdd_bAÚ "ó


adc_vbg_k,Ú "ó


adc_vbg_b7Ú "óadc_temp_voltSÚ "ócurrent_temp_valueÚ "ó battery_trim©Ú <"órsvd12mÚ <"    óuidQÚ "ó


chip_infoÚ "ócp_version‹Ú "óft_version„Ú "ó cp_pass_flagÝÚ "ó ft_pass_flagÖÚ "ócp_checksum<Ú "óft_checksum5Ú <"ó user_rw_data†Ú <"ó    mac_addraÚ "óxth_xocap_a"Ú "óxth_xocap_mÚ "óxth_xocap_nÚ "óxth_xocap_trimÒÚ "óxtl_xocap_aÚ "óxtl_xocap_mÚ "óxtl_xocap_nÚ "óxtl_xocap_trimÎÚ <"óadc_vbg_kb€Ú "óadc_vbat_k¼Ú "óadc_vbat_bÇÚ "óadc_vbat_dtemp_k9Ú "óadc_vbat_dtemp_bBÚ "óadc_temp_k«Ú 


"ó


adc_ctrl2PÚ 


"óadc_extsmptÚ "óxth_fix_code1˜Ú "óxth_fix_code2—Ú "óxtl_fix_code1”Ú "óxtl_fix_code2“Ú <"+órsvd13HÚ "ó ft_checksum2Ú "€¦m_v2Ú OTP_STRUCT_TÿÚisFtDataValidèÚ


vec_remap_adr™ÚSystemCoreClockUpdateaÚSystemInit»Ú,otpxÚSystemHwParamLoader6ÚRESETpÚSETÚFlagStatusïÚ    ITStatusÐÚDISABLEûÚENABLEJÚFunctionalStateÏÚPIS_FUNCTIONAL_STATE×Ú8


<unnamed>QÚ 


"çCTLòÚ 


"çCMPõÚ 


"çINTSTSêÚ 


"çCNTðÚ 


"çCAPÚ 


"çEXTCTLûÚ 


"çEINTSTS£Ú 


"çCMP1ÂÚ 


"çCMP2ÁÚTIMER_T¿ÚPTIMER_CTL_PSC_PosÚPTIMER_CTL_PSC_MskÚPTIMER_CTL_CAPSRC_Pos4ÚPTIMER_CTL_CAPSRC_Msk;ÚPTIMER_CTL_WKEN_Pos¿ÚPTIMER_CTL_WKEN_MskÆÚPTIMER_CTL_EXTCNTEN_PosƒÚPTIMER_CTL_EXTCNTEN_MskŠÚPTIMER_CTL_ACTSTS_PosÚPTIMER_CTL_ACTSTS_Msk%ÚPTIMER_CTL_RSTCNT_PosÚPTIMER_CTL_RSTCNT_MskÚPTIMER_CTL_OPMODE_Pos,ÚPTIMER_CTL_OPMODE_Msk3ÚPTIMER_CTL_INTEN_PostÚPTIMER_CTL_INTEN_Msk{ÚPTIMER_CTL_CNTEN_PoszÚPTIMER_CTL_CNTEN_MskÚPTIMER_CTL_ICEDEBUG_Pos´ÚPTIMER_CTL_ICEDEBUG_Msk»ÚPTIMER_CMP_CMPDAT_Pos:ÚPTIMER_CMP_CMPDAT_MskAÚPTIMER_INTSTS_TIF_PosÚPTIMER_INTSTS_TIF_MskÚPTIMER_INTSTS_TWKF0_Pos~ÚPTIMER_INTSTS_TWKF0_Msk…ÚPTIMER_INTSTS_TWKF1_Pos}ÚPTIMER_INTSTS_TWKF1_Msk„ÚPTIMER_INTSTS_TWKF2_Pos|ÚPTIMER_INTSTS_TWKF2_MskƒÚPTIMER_INTSTS_TF0_Pos$ÚPTIMER_INTSTS_TF0_Msk+ÚPTIMER_INTSTS_TF1_Pos#ÚPTIMER_INTSTS_TF1_Msk*ÚPTIMER_INTSTS_TF2_Pos"ÚPTIMER_INTSTS_TF2_Msk)ÚPTIMER_CNT_CNT_PosÚPTIMER_CNT_CNT_MskÚPTIMER_CAP_CAPDAT_PosRÚPTIMER_CAP_CAPDAT_MskYÚ"PTIMER_EXTCTL_CNTPHASE_PosŸÚ"PTIMER_EXTCTL_CNTPHASE_Msk¦Ú!PTIMER_EXTCTL_CAPEDGE_PosÚ!PTIMER_EXTCTL_CAPEDGE_MskÚPTIMER_EXTCTL_CAPEN_Pos”ÚPTIMER_EXTCTL_CAPEN_Msk›Ú"PTIMER_EXTCTL_CAPFUNCS_Pos¢Ú"PTIMER_EXTCTL_CAPFUNCS_Msk©Ú PTIMER_EXTCTL_CAPIEN_PosIÚ PTIMER_EXTCTL_CAPIEN_MskPÚ!PTIMER_EXTCTL_CAPDBEN_Pos


Ú!PTIMER_EXTCTL_CAPDBEN_MskÚ!PTIMER_EXTCTL_CNTDBEN_PosùÚ!PTIMER_EXTCTL_CNTDBEN_MskÚ PTIMER_EXTCTL_CAPSEL_PosAÚ PTIMER_EXTCTL_CAPSEL_MskHÚ"PTIMER_EXTCTL_ACMPSSEL_PosÚ"PTIMER_EXTCTL_ACMPSSEL_Msk¤Ú PTIMER_EINTSTS_CAPIF_Pos@Ú PTIMER_EINTSTS_CAPIF_MskGÚPTIMER_EINTSTS_CAPF_Pos‹ÚPTIMER_EINTSTS_CAPF_Msk’Ú8


<unnamed>QÚ 


"°TRIM_ENÕÚ 


"°


TRIM_CODEIÚ 


"°


TRIM_CTRL/Ú 


"°    TRIM_INT{Ú 


"° TRIM_CAL_CNTJÚ 


"°TRIM_IDEAL_CNT·Ú 


"°TRIM_REAL_CNTôÚTRIM_TÚ#PTRIM_MEASURE_TUNING_EN_Pos3Ú#PTRIM_MEASURE_TUNING_EN_Msk:Ú"PTRIM_COARSE_TUNING_EN_PosŠÚ"PTRIM_COARSE_TUNING_EN_Msk‘Ú PTRIM_FINE_TUNING_EN_Pos)Ú PTRIM_FINE_TUNING_EN_Msk0ÚPTRIM_COARSE_CODE_Pos@ÚPTRIM_COARSE_CODE_MskGÚPTRIM_FINE_CODE_PosßÚPTRIM_FINE_CODE_MskæÚPTRIM_BIT_WIDTH_Pos½ÚPTRIM_BIT_WIDTH_MskÄÚPTRIM_CLRL_RELATION_Pos‰ÚPTRIM_CLRL_RELATION_MskÚ$PTRIM_CLRL_EARLY_TERM_EN_Pos×Ú$PTRIM_CLRL_EARLY_TERM_EN_MskÞÚ%PTRIM_CLRL_FAIL_CLAC_FLAG_PosÔÚ%PTRIM_CLRL_FAIL_CLAC_FLAG_MskÛÚ PTRIM_CLRL_CODE_STEP_Pos/Ú PTRIM_CLRL_CODE_STEP_Msk6Ú PTRIM_CLRL_ERR_RANGE_Pos0Ú PTRIM_CLRL_ERR_RANGE_Msk7ÚPTRIM_INT_EN_Pos¤ÚPTRIM_INT_EN_Msk«Ú"PTRIM_INT_MEASURE_STOP_PoslÚ"PTRIM_INT_MEASURE_STOP_MsksÚ#PTRIM_FLAG_MEASURE_STOP_Pos;Ú#PTRIM_FLAG_MEASURE_STOP_MskBÚ PTRIM_INT_CTUNE_STOP_PosÚ PTRIM_INT_CTUNE_STOP_Msk


Ú!PTRIM_FLAG_CTUNE_STOP_PosÒÚ!PTRIM_FLAG_CTUNE_STOP_MskÙÚ PTRIM_INT_FTUNE_STOP_PosÚ PTRIM_INT_FTUNE_STOP_MskÚ!PTRIM_FLAG_FTUNE_STOP_PosÏÚ!PTRIM_FLAG_FTUNE_STOP_MskÖÚPTRIM_INT_OVERFLOW_Pos·ÚPTRIM_INT_OVERFLOW_Msk¾ÚPTRIM_FLAG_OVERFLOW_Pos†ÚPTRIM_FLAG_OVERFLOW_MskÚPTRIM_CALC_CNT_Pos&ÚPTRIM_CALC_CNT_Msk-ÚPTRIM_CALC_WATI_CNT_PosˆÚPTRIM_CALC_WATI_CNT_MskÚ8


<unnamed>QÚ 


"åMODE¯Ú 


"åDINOFFÚ 


"åDOUT˜Ú 


"åDATMSKÚ 


"åPINïÚ 


"åDBEN»Ú 


"åINTTYPE¡Ú 


"åINTENTÚ 


"åINTSRCýÚGPIO_TÚ8


<unnamed>QÚ 


"ðDBCTL^Ú


GPIO_DB_T(ÚPGP_MODE_MODE0_PosIÚPGP_MODE_MODE0_MskPÚPGP_MODE_MODE1_PosHÚPGP_MODE_MODE1_MskOÚPGP_MODE_MODE2_PosGÚPGP_MODE_MODE2_MskNÚPGP_MODE_MODE3_PosFÚPGP_MODE_MODE3_MskMÚPGP_MODE_MODE4_PosEÚPGP_MODE_MODE4_MskLÚPGP_MODE_MODE5_PosDÚPGP_MODE_MODE5_MskKÚPGP_DINOFF_DINOFF0_PosÚPGP_DINOFF_DINOFF0_Msk&ÚPGP_DINOFF_DINOFF1_PosÚPGP_DINOFF_DINOFF1_Msk%ÚPGP_DINOFF_DINOFF2_PosÚPGP_DINOFF_DINOFF2_Msk$ÚPGP_DINOFF_DINOFF3_PosÚPGP_DINOFF_DINOFF3_Msk#ÚPGP_DINOFF_DINOFF4_PosÚPGP_DINOFF_DINOFF4_Msk"ÚPGP_DINOFF_DINOFF5_PosÚPGP_DINOFF_DINOFF5_Msk!ÚPGP_DINOFF_DINOFF6_PosÚPGP_DINOFF_DINOFF6_Msk ÚPGP_DINOFF_DINOFF7_PosÚPGP_DINOFF_DINOFF7_MskÚPGP_DOUT_DOUT0_PosÚPGP_DOUT_DOUT0_Msk"ÚPGP_DOUT_DOUT1_PosÚPGP_DOUT_DOUT1_Msk!ÚPGP_DOUT_DOUT2_PosÚPGP_DOUT_DOUT2_Msk ÚPGP_DOUT_DOUT3_PosÚPGP_DOUT_DOUT3_MskÚPGP_DOUT_DOUT4_PosÚPGP_DOUT_DOUT4_MskÚPGP_DOUT_DOUT5_PosÚPGP_DOUT_DOUT5_MskÚPGP_DOUT_DOUT6_PosÚPGP_DOUT_DOUT6_MskÚPGP_DOUT_DOUT7_PosÚPGP_DOUT_DOUT7_MskÚPGP_DATMSK_DATMSK0_PosÚPGP_DATMSK_DATMSK0_Msk


ÚPGP_DATMSK_DATMSK1_PosÚPGP_DATMSK_DATMSK1_Msk    ÚPGP_DATMSK_DATMSK2_PosÚPGP_DATMSK_DATMSK2_MskÚPGP_DATMSK_DATMSK3_PosÚPGP_DATMSK_DATMSK3_MskÚPGP_DATMSK_DATMSK4_PosÿÚPGP_DATMSK_DATMSK4_MskÚPGP_DATMSK_DATMSK5_PosþÚPGP_DATMSK_DATMSK5_MskÚPGP_DATMSK_DATMSK6_PosýÚPGP_DATMSK_DATMSK6_MskÚPGP_DATMSK_DATMSK7_PosüÚPGP_DATMSK_DATMSK7_MskÚPGP_PIN_PIN0_PosÉÚPGP_PIN_PIN0_MskÐÚPGP_PIN_PIN1_PosÈÚPGP_PIN_PIN1_MskÏÚPGP_PIN_PIN2_PosÇÚPGP_PIN_PIN2_MskÎÚPGP_PIN_PIN3_PosÆÚPGP_PIN_PIN3_MskÍÚPGP_PIN_PIN4_PosÅÚPGP_PIN_PIN4_MskÌÚPGP_PIN_PIN5_PosÄÚPGP_PIN_PIN5_MskËÚPGP_PIN_PIN6_PosÃÚPGP_PIN_PIN6_MskÊÚPGP_PIN_PIN7_PosÂÚPGP_PIN_PIN7_MskÉÚPGP_DBEN_DBEN0_PosaÚPGP_DBEN_DBEN0_MskhÚPGP_DBEN_DBEN1_Pos`ÚPGP_DBEN_DBEN1_MskgÚPGP_DBEN_DBEN2_Pos_ÚPGP_DBEN_DBEN2_MskfÚPGP_DBEN_DBEN3_Pos^ÚPGP_DBEN_DBEN3_MskeÚPGP_DBEN_DBEN4_Pos]ÚPGP_DBEN_DBEN4_MskdÚPGP_DBEN_DBEN5_Pos\ÚPGP_DBEN_DBEN5_MskcÚPGP_DBEN_DBEN6_Pos[ÚPGP_DBEN_DBEN6_MskbÚPGP_DBEN_DBEN7_PosZÚPGP_DBEN_DBEN7_MskaÚPGP_INTTYPE_TYPE0_PosÚPGP_INTTYPE_TYPE0_Msk%ÚPGP_INTTYPE_TYPE1_PosÚPGP_INTTYPE_TYPE1_Msk$ÚPGP_INTTYPE_TYPE2_PosÚPGP_INTTYPE_TYPE2_Msk#ÚPGP_INTTYPE_TYPE3_PosÚPGP_INTTYPE_TYPE3_Msk"ÚPGP_INTTYPE_TYPE4_PosÚPGP_INTTYPE_TYPE4_Msk!ÚPGP_INTTYPE_TYPE5_PosÚPGP_INTTYPE_TYPE5_Msk ÚPGP_INTTYPE_TYPE6_PosÚPGP_INTTYPE_TYPE6_MskÚPGP_INTTYPE_TYPE7_PosÚPGP_INTTYPE_TYPE7_MskÚPGP_INTEN_FLIEN0_Pos£ÚPGP_INTEN_FLIEN0_MskªÚPGP_INTEN_FLIEN1_Pos¢ÚPGP_INTEN_FLIEN1_Msk©ÚPGP_INTEN_FLIEN2_Pos¡ÚPGP_INTEN_FLIEN2_Msk¨ÚPGP_INTEN_FLIEN3_Pos ÚPGP_INTEN_FLIEN3_Msk§ÚPGP_INTEN_FLIEN4_PosŸÚPGP_INTEN_FLIEN4_Msk¦ÚPGP_INTEN_FLIEN5_PosžÚPGP_INTEN_FLIEN5_Msk¥ÚPGP_INTEN_FLIEN6_PosÚPGP_INTEN_FLIEN6_Msk¤ÚPGP_INTEN_FLIEN7_PosœÚPGP_INTEN_FLIEN7_Msk£ÚPGP_INTEN_RHIEN0_Pos›ÚPGP_INTEN_RHIEN0_Msk¢ÚPGP_INTEN_RHIEN1_PosšÚPGP_INTEN_RHIEN1_Msk¡ÚPGP_INTEN_RHIEN2_Pos™ÚPGP_INTEN_RHIEN2_Msk ÚPGP_INTEN_RHIEN3_Pos˜ÚPGP_INTEN_RHIEN3_MskŸÚPGP_INTEN_RHIEN4_Pos—ÚPGP_INTEN_RHIEN4_MskžÚPGP_INTEN_RHIEN5_Pos–ÚPGP_INTEN_RHIEN5_MskÚPGP_INTEN_RHIEN6_Pos•ÚPGP_INTEN_RHIEN6_MskœÚPGP_INTEN_RHIEN7_Pos”ÚPGP_INTEN_RHIEN7_Msk›ÚPGP_INTSRC_INTSRC0_PosåÚPGP_INTSRC_INTSRC0_MskìÚPGP_INTSRC_INTSRC1_PosäÚPGP_INTSRC_INTSRC1_MskëÚPGP_INTSRC_INTSRC2_PosãÚPGP_INTSRC_INTSRC2_MskêÚPGP_INTSRC_INTSRC3_PosâÚPGP_INTSRC_INTSRC3_MskéÚPGP_INTSRC_INTSRC4_PosáÚPGP_INTSRC_INTSRC4_MskèÚPGP_INTSRC_INTSRC5_PosàÚPGP_INTSRC_INTSRC5_MskçÚPGP_INTSRC_INTSRC6_PosßÚPGP_INTSRC_INTSRC6_MskæÚPGP_INTSRC_INTSRC7_PosÞÚPGP_INTSRC_INTSRC7_MskåÚPGP_INTSRC_INTSRC8_PosÝÚPGP_INTSRC_INTSRC8_MskäÚPGP_INTSRC_INTSRC9_PosÜÚPGP_INTSRC_INTSRC9_MskãÚPGP_INTSRC_INTSRC10_Pos²ÚPGP_INTSRC_INTSRC10_Msk¹ÚPGP_INTSRC_INTSRC11_Pos±ÚPGP_INTSRC_INTSRC11_Msk¸ÚPGP_INTSRC_INTSRC12_Pos°ÚPGP_INTSRC_INTSRC12_Msk·ÚPGP_INTSRC_INTSRC13_Pos¯ÚPGP_INTSRC_INTSRC13_Msk¶ÚPGP_INTSRC_INTSRC14_Pos®ÚPGP_INTSRC_INTSRC14_MskµÚPGP_INTSRC_INTSRC15_Pos­ÚPGP_INTSRC_INTSRC15_Msk´ÚPGP_DBCTL_DBCLKSEL_PosÚPGP_DBCTL_DBCLKSEL_MskÚPGP_DBCTL_DBCLKSRC_Pos


ÚPGP_DBCTL_DBCLKSRC_MskÚPGP_DBCTL_ICLKON_Pos–ÚPGP_DBCTL_ICLKON_MskÚ8


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DAT;Ú <"¥


 


RESERVED0.Ú 


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CTL1Ú 


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CHENôÚ 


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CMP1Ú 


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STATUS*Ú <"¥


 


RESERVED19Ú 


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TRGDLY8Ú 


"¥


EXTSMPT×Ú 


"¥


SEQCTLBÚ 


"¥


SEQDAT1Ú 


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SEQDAT2Ú 


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CTL2ýÚ <"¥


 


RESERVED28Ú 


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BV_CTL4ÚADC_T|ÚPADC_DAT_RESULT_PosØÚPADC_DAT_RESULT_MskßÚPADC_DAT_OV_PosÚPADC_DAT_OV_Msk!ÚPADC_DAT_VALID_PosIÚPADC_DAT_VALID_MskPÚPADC_CTL_ADCEN_PosTÚPADC_CTL_ADCEN_Msk[ÚPADC_CTL_ADCIEN_Pos    ÚPADC_CTL_ADCIEN_MskÚPADC_CTL_HWTRGSEL_Pos9ÚPADC_CTL_HWTRGSEL_Msk@ÚPADC_CTL_HWTRGCOND_Pos÷ÚPADC_CTL_HWTRGCOND_MskþÚPADC_CTL_HWTRGEN_PosŒÚPADC_CTL_HWTRGEN_Msk“ÚPADC_CTL_FIFO_EN_Pos•ÚPADC_CTL_FIFO_EN_MskœÚ$PADC_CTL_FIFO_THRE_STATE_PosÚ$PADC_CTL_FIFO_THRE_STATE_MskÚPADC_CTL_SWTRG_PosÚPADC_CTL_SWTRG_MskÚ"PADC_CTL_LEFT_SHIFT_EN_Pos¥Ú"PADC_CTL_LEFT_SHIFT_EN_Msk¬Ú PADC_CTL_SUB_BIAS_EN_PosIÚ PADC_CTL_SUB_BIAS_EN_MskPÚPADC_CTL_BIAS_VALUE_PosªÚPADC_CTL_BIAS_VALUE_Msk±ÚPADC_CHEN_CHEN0_Pos$ÚPADC_CHEN_CHEN0_Msk+ÚPADC_CHEN_CHEN1_Pos#ÚPADC_CHEN_CHEN1_Msk*ÚPADC_CHEN_CHEN2_Pos"ÚPADC_CHEN_CHEN2_Msk)ÚPADC_CHEN_CHEN3_Pos!ÚPADC_CHEN_CHEN3_Msk(ÚPADC_CHEN_CHEN4_Pos ÚPADC_CHEN_CHEN4_Msk'ÚPADC_CHEN_CHEN5_PosÚPADC_CHEN_CHEN5_Msk&ÚPADC_CHEN_CHEN6_PosÚPADC_CHEN_CHEN6_Msk%ÚPADC_CHEN_CHEN7_PosÚPADC_CHEN_CHEN7_Msk$ÚPADC_CHEN_CHEN8_VBG_PosÖÚPADC_CHEN_CHEN8_VBG_MskÝÚPADC_CHEN_CH9_TMP_PosZÚPADC_CHEN_CH9_TMP_MskaÚ PADC_CHEN_CH10_VDD_4_Pos¬Ú PADC_CHEN_CH10_VDD_4_Msk³Ú PADC_CHEN_CH11_VBG_2_Pos¬Ú PADC_CHEN_CH11_VBG_2_Msk³ÚPADC_CHEN_ALL_Msk¤ÚPADC_CMP0_ADCMPEN_Pos„ÚPADC_CMP0_ADCMPEN_Msk‹ÚPADC_CMP0_ADCMPIE_Pos‰ÚPADC_CMP0_ADCMPIE_MskÚPADC_CMP0_CMPCOND_PosxÚPADC_CMP0_CMPCOND_MskÚPADC_CMP0_CMPCH_PosÚPADC_CMP0_CMPCH_MskÚPADC_CMP0_CMPMCNT_PosjÚPADC_CMP0_CMPMCNT_MskqÚPADC_CMP0_CMPDAT_PosÅÚPADC_CMP0_CMPDAT_MskÌÚPADC_CMP1_ADCMPEN_PosƒÚPADC_CMP1_ADCMPEN_MskŠÚPADC_CMP1_ADCMPIE_PosˆÚPADC_CMP1_ADCMPIE_MskÚPADC_CMP1_CMPCOND_PoswÚPADC_CMP1_CMPCOND_Msk~ÚPADC_CMP1_CMPCH_PosÚPADC_CMP1_CMPCH_MskÚPADC_CMP1_CMPMCNT_PosiÚPADC_CMP1_CMPMCNT_MskpÚPADC_CMP1_CMPDAT_PosÄÚPADC_CMP1_CMPDAT_MskËÚPADC_STATUS_ADIF_Pos–ÚPADC_STATUS_ADIF_MskÚ PADC_STATUS_ADCMPIF0_Pos~Ú PADC_STATUS_ADCMPIF0_Msk…Ú PADC_STATUS_ADCMPIF1_Pos}Ú PADC_STATUS_ADCMPIF1_Msk„ÚPADC_STATUS_BUSY_PosgÚPADC_STATUS_BUSY_MsknÚPADC_STATUS_CHANNEL_Pos«ÚPADC_STATUS_CHANNEL_Msk²ÚPADC_STATUS_VALID_Pos8ÚPADC_STATUS_VALID_Msk?Ú#PADC_STATUS_INTMSK_FULL_Pos4Ú#PADC_STATUS_INTMSK_FULL_Msk;Ú$PADC_STATUS_INTMSK_EMPTY_PosÖÚ$PADC_STATUS_INTMSK_EMPTY_MskÝÚ#PADC_STATUS_INTMSK_OVER_Pos+Ú#PADC_STATUS_INTMSK_OVER_Msk2Ú#PADC_STATUS_INTMSK_HALF_PosLÚ#PADC_STATUS_INTMSK_HALF_MskSÚ!PADC_STATUS_INTMSK_AD_PosæÚ!PADC_STATUS_INTMSK_AD_MskíÚ#PADC_STATUS_INTMSK_CMP0_PosWÚ#PADC_STATUS_INTMSK_CMP0_Msk^Ú#PADC_STATUS_INTMSK_CMP1_PosVÚ#PADC_STATUS_INTMSK_CMP1_Msk]ÚPADC_STATUS_OV_Pos    ÚPADC_STATUS_OV_MskÚ&PADC_STATUS_ONE_CH_CLR_SEL_PosGÚ&PADC_STATUS_ONE_CH_CLR_SEL_MskNÚ#PADC_STATUS_ONE_CH_FLAG_PosWÚ#PADC_STATUS_ONE_CH_FLAG_Msk^Ú#PADC_STATUS_INTFLG_FULL_PosFÚ#PADC_STATUS_INTFLG_FULL_MskMÚ$PADC_STATUS_INTFLG_EMPTY_PosèÚ$PADC_STATUS_INTFLG_EMPTY_MskïÚ#PADC_STATUS_INTFLG_OVER_Pos=Ú#PADC_STATUS_INTFLG_OVER_MskDÚ#PADC_STATUS_INTFLG_HALF_Pos^Ú#PADC_STATUS_INTFLG_HALF_MskeÚPADC_STATUS_ADCF_PosœÚPADC_STATUS_ADCF_Msk£ÚPADC_STATUS_ADCMPF0_PosÉÚPADC_STATUS_ADCMPF0_MskÐÚPADC_STATUS_ADCMPF1_PosÈÚPADC_STATUS_ADCMPF1_MskÏÚ!PADC_STATUS_FLAG_FULL_PosôÚ!PADC_STATUS_FLAG_FULL_MskûÚ"PADC_STATUS_FLAG_EMPTY_Pos–Ú"PADC_STATUS_FLAG_EMPTY_MskÚ!PADC_STATUS_FLAG_OVER_PosëÚ!PADC_STATUS_FLAG_OVER_MskòÚ!PADC_STATUS_FLAG_HALF_PosÚ!PADC_STATUS_FLAG_HALF_MskÚPADC_TRGDLY_DELAY_PosGÚPADC_TRGDLY_DELAY_MskNÚ PADC_EXTSMPT_EXTSMPT_PosÚ PADC_EXTSMPT_EXTSMPT_Msk#ÚPADC_SEQCTL_SEQEN_PosDÚPADC_SEQCTL_SEQEN_MskKÚPADC_SEQCTL_SEQTYPE_Pos‘ÚPADC_SEQCTL_SEQTYPE_Msk˜ÚPADC_SEQCTL_MODESEL_Pos³ÚPADC_SEQCTL_MODESEL_MskºÚ PADC_SEQCTL_DELAY_EN_PosYÚ PADC_SEQCTL_DELAY_EN_Msk`ÚPADC_SEQCTL_TRG_SEL_PosŒÚPADC_SEQCTL_TRG_SEL_Msk“Ú!PADC_SEQCTL_ONE_CH_EN_PosúÚ!PADC_SEQCTL_ONE_CH_EN_MskÚPADC_SEQCTL_TRG1CTL_Pos»ÚPADC_SEQCTL_TRG1CTL_MskÂÚPADC_SEQCTL_TRG2CTL_PosºÚPADC_SEQCTL_TRG2CTL_MskÁÚPADC_SEQDAT1_RESULT_Pos¶ÚPADC_SEQDAT1_RESULT_Msk½ÚPADC_SEQDAT1_OV_PosøÚPADC_SEQDAT1_OV_MskÿÚPADC_SEQDAT1_VALID_Pos'ÚPADC_SEQDAT1_VALID_Msk.ÚPADC_SEQDAT2_RESULT_PosµÚPADC_SEQDAT2_RESULT_Msk¼ÚPADC_SEQDAT2_OV_Pos÷ÚPADC_SEQDAT2_OV_MskþÚPADC_SEQDAT2_VALID_Pos&ÚPADC_SEQDAT2_VALID_Msk-ÚPADC_CTL2_TESTMODE_PosÚPADC_CTL2_TESTMODE_MskÚPADC_CTL2_SHSEL_PosüÚPADC_CTL2_SHSEL_MskÚPADC_CTL2_DMA_EN_PosµÚPADC_CTL2_DMA_EN_Msk¼ÚPADC_CTL2_CLKDIV_Pos¼ÚPADC_CTL2_CLKDIV_MskÃÚPADC_SEL_VREF_Pos}ÚPADC_SEL_VREF_Msk„ÚPADC_CTL2_CMPCTL_Pos¶ÚPADC_CTL2_CMPCTL_Msk½ÚPADC_CTL2_DRVCTL_PosªÚPADC_CTL2_DRVCTL_Msk±Ú8


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"èP0_MFPÚ 


"èP1_MFPÚ 


"èP2_MFPÚ 


"èP3_MFPÚ <"0èRESV0Ú 


"èREGLCTL»Ú 


"èSTATUSæÚ 


"èCTRL0gÚ 


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"ÝRSTSTSáÚ 


"ÝIPRST0Ú 


"ÝIPRST1Ú 


"Ý


BODCTL_3V.Ú 


"ÝBLDBCTL_3VíÚ 


"ÝCLK_TOP_CTRL_3VÚ 


"ÝRCL_CTRL_3VmÚ 


"Ý    RCH_CTRL_Ú 


"ÝXTL_CTRL_3VVÚ 


"Ý    XTH_CTRLHÚ 


"Ý


DPLL_CTRLÚ 


"Ý AHB_CLK_CTRL0Ú 


"ÝAPB1_CLK_CTRLõÚ 


"ÝAPB2_CLK_CTRLôÚ 


"ÝMEAS_CLK_CTRLÓÚCLK_TjÚPCLK_RSTSTS_CHIPRF_PosÉÚPCLK_RSTSTS_CHIPRF_MskÐÚPCLK_RSTSTS_PINRF_PosÚPCLK_RSTSTS_PINRF_MskÚPCLK_RSTSTS_WDTRF_PosÚPCLK_RSTSTS_WDTRF_MskÚPCLK_RSTSTS_LVRRF_PosûÚPCLK_RSTSTS_LVRRF_MskÚPCLK_RSTSTS_BODRF_PosÚPCLK_RSTSTS_BODRF_Msk!ÚPCLK_RSTSTS_SYSRF_PosðÚPCLK_RSTSTS_SYSRF_Msk÷ÚPCLK_RSTSTS_PORRF_PosþÚPCLK_RSTSTS_PORRF_MskÚPCLK_RSTSTS_CPURF_PosÚPCLK_RSTSTS_CPURF_MskÚPCLK_IPRST0_CHIPRST_Pos—ÚPCLK_IPRST0_CHIPRST_MskžÚPCLK_IPRST0_CPURST_PosÕÚPCLK_IPRST0_CPURST_MskÜÚPCLK_IPRST0_DMARST_PosëÚPCLK_IPRST0_DMARST_MskòÚPCLK_IPRST0_RFRST_Pos'ÚPCLK_IPRST0_RFRST_Msk.Ú PCLK_IPRST0_EFUSERST_PosAÚ PCLK_IPRST0_EFUSERST_MskHÚPCLK_IPRST0_USBRST_PosÓÚPCLK_IPRST0_USBRST_MskÚÚ#PCLK_IPRST0_MDMSTDBYRST_PosOÚ#PCLK_IPRST0_MDMSTDBYRST_MskVÚPCLK_IPRST0_MDMRST_PosßÚPCLK_IPRST0_MDMRST_MskæÚ#PCLK_IPRST0_CHIPSCOPEEN_Pos{Ú#PCLK_IPRST0_CHIPSCOPEEN_Msk‚ÚPCLK_IPRST0_FTORRST_Pos€ÚPCLK_IPRST0_FTORRST_Msk‡ÚPCLK_IPRST1_I2C0RST_PosÌÚPCLK_IPRST1_I2C0RST_MskÓÚPCLK_IPRST1_SPI0RST_PosžÚPCLK_IPRST1_SPI0RST_Msk¥ÚPCLK_IPRST1_SPI1RST_PosÚPCLK_IPRST1_SPI1RST_Msk¤Ú PCLK_IPRST1_UART0RST_PosLÚ PCLK_IPRST1_UART0RST_MskSÚ PCLK_IPRST1_UART1RST_PosKÚ PCLK_IPRST1_UART1RST_MskRÚPCLK_IPRST1_PWM0RST_Pos–ÚPCLK_IPRST1_PWM0RST_MskÚPCLK_IPRST1_ADCRST_PosôÚPCLK_IPRST1_ADCRST_MskûÚPCLK_IPRST1_WDTRST_PosÍÚPCLK_IPRST1_WDTRST_MskÔÚPCLK_IPRST1_WWDTRST_PostÚPCLK_IPRST1_WWDTRST_Msk{ÚPCLK_IPRST1_TMR0RST_Pos—ÚPCLK_IPRST1_TMR0RST_MskžÚPCLK_IPRST1_TMR1RST_Pos–ÚPCLK_IPRST1_TMR1RST_MskÚPCLK_IPRST1_TMR2RST_Pos•ÚPCLK_IPRST1_TMR2RST_MskœÚPCLK_IPRST1_GPIORST_Pos‹ÚPCLK_IPRST1_GPIORST_Msk’ÚPCLK_IPRST1_TRIMRST_Pos~ÚPCLK_IPRST1_TRIMRST_Msk…Ú#PCLK_BODCTL_BODRSTEN_Pos_3vMÚ#PCLK_BODCTL_BODRSTEN_Msk_3vTÚPCLK_BODCTL_BODIF_Pos^ÚPCLK_BODCTL_BODIF_MskeÚPCLK_BODCTL_BODOUT_PosóÚPCLK_BODCTL_BODOUT_MskúÚ PCLK_BODCTL_LVREN_Pos_3v-Ú PCLK_BODCTL_LVREN_Msk_3v4Ú PCLK_BODCTL_BODEN_Pos_3vLÚ PCLK_BODCTL_BODEN_Msk_3vSÚ!PCLK_BODCTL_BODSEL_Pos_3vùÚ!PCLK_BODCTL_BODSEL_Msk_3vÚ#PCLK_BODCTL_LVR_TEST_Pos_3vÚ#PCLK_BODCTL_LVR_TEST_Msk_3v"Ú#PCLK_BODCTL_BOD_TEST_Pos_3v:Ú#PCLK_BODCTL_BOD_TEST_Msk_3vAÚ%PCLK_BLDBCTL_LVRDB_SEL_Pos_3v®Ú%PCLK_BLDBCTL_LVRDB_SEL_Msk_3vµÚ%PCLK_BLDBCTL_BODDB_SEL_Pos_3vÍÚ%PCLK_BLDBCTL_BODDB_SEL_Msk_3vÔÚ'PCLK_TOPCTL_RSICV_SYSCNT_EN_PosÔÚ'PCLK_TOPCTL_RSICV_SYSCNT_EN_MskÛÚ#PCLK_TOPCTL_SYS_CLK_SEL_PosÚ#PCLK_TOPCTL_SYS_CLK_SEL_Msk$Ú&PCLK_TOPCTL_32K_CLK_SEL_Pos_3v^Ú&PCLK_TOPCTL_32K_CLK_SEL_Msk_3veÚPCLK_TOPCTL_AHB_DIV_Pos“ÚPCLK_TOPCTL_AHB_DIV_MskšÚ PCLK_TOPCTL_APB1_DIV_PosXÚ PCLK_TOPCTL_APB1_DIV_Msk_Ú PCLK_TOPCTL_APB2_DIV_PosWÚ PCLK_TOPCTL_APB2_DIV_Msk^Ú#PCLK_RCLCTL_RC32K_EN_Pos_3vkÚ#PCLK_RCLCTL_RC32K_EN_Msk_3vrÚ$PCLK_RCLCTL_RC32K_TST_EN_PosÚ$PCLK_RCLCTL_RC32K_TST_EN_MskÚ"PCLK_RCLCTL_CLK_SEL_Pos_3v‡Ú"PCLK_RCLCTL_CLK_SEL_Msk_3vŽÚ'PCLK_RCLCTL_RC32K_COARSE_Pos_3v9Ú'PCLK_RCLCTL_RC32K_COARSE_Msk_3v@Ú%PCLK_RCLCTL_RC32K_FINE_Pos_3vØÚ%PCLK_RCLCTL_RC32K_FINE_Msk_3vßÚ&PCLK_RCLCTL_RC32K_DELAY_Pos_3v‰Ú&PCLK_RCLCTL_RC32K_DELAY_Msk_3vÚPCLK_RCLCTL_STABLE_PosùÚPCLK_RCLCTL_STABLE_MskÚPCLK_RCHCTL_RCH_EN_PoséÚPCLK_RCHCTL_RCH_EN_MskðÚ"PCLK_RCHCTL_RCH_TST_EN_Pos‡Ú"PCLK_RCHCTL_RCH_TST_EN_MskŽÚPCLK_RCHCTL_CLK_SEL_Pos™ÚPCLK_RCHCTL_CLK_SEL_Msk ÚPCLK_RCHCTL_BIAS_PosÚPCLK_RCHCTL_BIAS_Msk¤Ú PCLK_RCHCTL_RCH_FREQ_PosJÚ PCLK_RCHCTL_RCH_FREQ_MskQÚPCLK_RCHCTL_DELAY_PosKÚPCLK_RCHCTL_DELAY_MskRÚPCLK_RCHCTL_STABLE_PosýÚPCLK_RCHCTL_STABLE_MskÚ!PCLK_XTLCTL_XTL_EN_Pos_3v¥Ú!PCLK_XTLCTL_XTL_EN_Msk_3v¬Ú"PCLK_XTLCTL_XTL_TST_EN_PosQÚ"PCLK_XTLCTL_XTL_TST_EN_MskXÚ$PCLK_XTLCTL_CORE_BIAS_Pos_3vâÚ$PCLK_XTLCTL_CORE_BIAS_Msk_3véÚ#PCLK_XTLCTL_XTL_TRIM_Pos_3vøÚ#PCLK_XTLCTL_XTL_TRIM_Msk_3vÿÚ%PCLK_XTLCTL_XTL_CAP_EN_Pos_3vjÚ%PCLK_XTLCTL_XTL_CAP_EN_Msk_3vqÚ PCLK_XTLCTL_DELAY_Pos_3v"Ú PCLK_XTLCTL_DELAY_Msk_3v)ÚPCLK_XTLCTL_STABLE_PosâÚPCLK_XTLCTL_STABLE_MskéÚPCLK_XTHCTL_XTH_EN_Pos»ÚPCLK_XTHCTL_XTH_EN_MskÂÚ"PCLK_XTHCTL_XTH_TST_EN_PosYÚ"PCLK_XTHCTL_XTH_TST_EN_Msk`Ú"PCLK_XTHCTL_START_FAST_Pos~Ú"PCLK_XTHCTL_START_FAST_Msk…Ú#PCLK_XTHCTL_DEGLITCH_EN_PosaÚ#PCLK_XTHCTL_DEGLITCH_EN_MskhÚ"PCLK_XTHCTL_XO_CAP_SEL_Pos|Ú"PCLK_XTHCTL_XO_CAP_SEL_MskƒÚPCLK_XTHCTL_DELAY_Pos4ÚPCLK_XTHCTL_DELAY_Msk;ÚPCLK_XTHCTL_STABLE_PosæÚPCLK_XTHCTL_STABLE_MskíÚ PCLK_DPLLCTL_DPLL_EN_PosGÚ PCLK_DPLLCTL_DPLL_EN_MskNÚ$PCLK_DPLLCTL_DPLL_TST_EN_PosåÚ$PCLK_DPLLCTL_DPLL_TST_EN_MskìÚ!PCLK_DPLLCTL_FREQ_OUT_PosÞÚ!PCLK_DPLLCTL_FREQ_OUT_MskåÚ!PCLK_DPLLCTL_RCLK_SEL_PosôÚ!PCLK_DPLLCTL_RCLK_SEL_MskûÚ!PCLK_DPLLCTL_ICP_BIAS_Pos    Ú!PCLK_DPLLCTL_ICP_BIAS_MskÚ!PCLK_DPLLCTL_ICP_CTRL_PosóÚ!PCLK_DPLLCTL_ICP_CTRL_MskúÚ"PCLK_DPLLCTL_KVCO_CTRL_PosšÚ"PCLK_DPLLCTL_KVCO_CTRL_Msk¡Ú&PCLK_DPLLCTL_VCO_FREQ_TRIM_PosIÚ&PCLK_DPLLCTL_VCO_FREQ_TRIM_MskPÚ PCLK_DPLLCTL_DIV_SEL_Pos?Ú PCLK_DPLLCTL_DIV_SEL_MskFÚPCLK_DPLLCTL_DELAY_PosúÚPCLK_DPLLCTL_DELAY_MskÚPCLK_DPLLCTL_STABLE_Pos¬ÚPCLK_DPLLCTL_STABLE_Msk³ÚPCLK_AHBCLK_DMAEN_PospÚPCLK_AHBCLK_DMAEN_MskwÚPCLK_AHBCLK_GPIOEN_PosÚPCLK_AHBCLK_GPIOEN_MskÚ"PCLK_AHBCLK_SYSTICK_EN_Pos¯Ú"PCLK_AHBCLK_SYSTICK_EN_Msk¶ÚPCLK_AHBCLK_APB1EN_Pos<ÚPCLK_AHBCLK_APB1EN_MskCÚPCLK_AHBCLK_APB2EN_Pos;ÚPCLK_AHBCLK_APB2EN_MskBÚPCLK_AHBCLK_AHBEN_PoswÚPCLK_AHBCLK_AHBEN_Msk~Ú!PCLK_AHBCLK_BLE32M_EN_PosVÚ!PCLK_AHBCLK_BLE32M_EN_Msk]Ú!PCLK_AHBCLK_BLE32K_EN_PosXÚ!PCLK_AHBCLK_BLE32K_EN_Msk_Ú"PCLK_AHBCLK_BLE32M_SEL_PosÚ"PCLK_AHBCLK_BLE32M_SEL_Msk


Ú"PCLK_AHBCLK_ROM_CLK_EN_Pos²Ú"PCLK_AHBCLK_ROM_CLK_EN_Msk¹Ú$PCLK_AHBCLK_EFUSE_CLK_EN_Pos$Ú$PCLK_AHBCLK_EFUSE_CLK_EN_Msk+Ú&PCLK_AHBCLK_USB_AHB_CLK_EN_Pos„Ú&PCLK_AHBCLK_USB_AHB_CLK_EN_Msk‹Ú&PCLK_AHBCLK_USB_48M_CLK_EN_Pos–Ú&PCLK_AHBCLK_USB_48M_CLK_EN_MskÚ%PCLK_AHBCLK_SPI_FLASH_DIV_PosÊÚ%PCLK_AHBCLK_SPI_FLASH_DIV_MskÑÚ)P!CLK_AHBCLK_SPI_FLASH_CLK_SEL_PosˆÚ)P!CLK_AHBCLK_SPI_FLASH_CLK_SEL_MskÚ'PCLK_AHBCLK_DPLL_CLK_TST_EN_PosÚ'PCLK_AHBCLK_DPLL_CLK_TST_EN_MskÚ(P CLK_AHBCLK_SPI_CLK_SEL_FPGA_PosÚÚ(P CLK_AHBCLK_SPI_CLK_SEL_FPGA_MskáÚ#PCLK_APB1CLK_WDTSRC_SEL_PosvÚ#PCLK_APB1CLK_WDTSRC_SEL_Msk}Ú$PCLK_APB1CLK_WWDTSRC_SEL_PosÚ$PCLK_APB1CLK_WWDTSRC_SEL_Msk$Ú$PCLK_APB1CLK_TMR0SRC_SEL_Pos@Ú$PCLK_APB1CLK_TMR0SRC_SEL_MskGÚ&PCLK_APB1CLK_PWM01_CLK_SEL_Pos¹Ú&PCLK_APB1CLK_PWM01_CLK_SEL_MskÀÚ&PCLK_APB1CLK_PWM23_CLK_SEL_PosµÚ&PCLK_APB1CLK_PWM23_CLK_SEL_Msk¼Ú&PCLK_APB1CLK_PWM45_CLK_SEL_Pos±Ú&PCLK_APB1CLK_PWM45_CLK_SEL_Msk¸Ú&PCLK_APB1CLK_PWM67_CLK_SEL_Pos­Ú&PCLK_APB1CLK_PWM67_CLK_SEL_Msk´Ú$PCLK_APB1CLK_ADC_CLK_SEL_PosJÚ$PCLK_APB1CLK_ADC_CLK_SEL_MskQÚ$PCLK_APB2CLK_TMR1SRC_SEL_Pos>Ú$PCLK_APB2CLK_TMR1SRC_SEL_MskEÚ$PCLK_APB2CLK_TMR2SRC_SEL_Pos=Ú$PCLK_APB2CLK_TMR2SRC_SEL_MskDÚ$PCLK_MEASCLK_TRIM_CLK_EN_PosÚ$PCLK_MEASCLK_TRIM_CLK_EN_MskÚ%PCLK_MEASCLK_TRIM_CLK_SEL_Pos²Ú%PCLK_MEASCLK_TRIM_CLK_SEL_Msk¹Ú%PCLK_MEASCLK_TRIM_CLK_DIV_Pos³Ú%PCLK_MEASCLK_TRIM_CLK_DIV_MskºÚ%PCLK_MEASCLK_XTL_QUICK_EN_Pos¤Ú%PCLK_MEASCLK_XTL_QUICK_EN_Msk«Ú PCLK_MEASCLK_XTH_DIV_Pos>Ú PCLK_MEASCLK_XTH_DIV_MskEÚ8


<unnamed>QÚ 


"ÜCTLöÚ 


"ÜALTCTLÚWDT_TUÚPWDT_CTL_RSTCNT_Pos¨ÚPWDT_CTL_RSTCNT_Msk¯ÚPWDT_CTL_RSTEN_PosüÚPWDT_CTL_RSTEN_MskÚPWDT_CTL_RSTF_PosKÚPWDT_CTL_RSTF_MskRÚPWDT_CTL_IF_PosÿÚPWDT_CTL_IF_MskÚPWDT_CTL_WKEN_PosUÚPWDT_CTL_WKEN_Msk\ÚPWDT_CTL_WKF_Pos¤ÚPWDT_CTL_WKF_Msk«ÚPWDT_CTL_INTEN_Pos


ÚPWDT_CTL_INTEN_MskÚPWDT_CTL_WDTEN_PosÚPWDT_CTL_WDTEN_Msk ÚPWDT_CTL_TOUTSEL_PosTÚPWDT_CTL_TOUTSEL_Msk[Ú#PWDT_CTL_RST_REGION_SEL_PosÚ#PWDT_CTL_RST_REGION_SEL_MskÚPWDT_CTL_TOF_Pos£ÚPWDT_CTL_TOF_MskªÚPWDT_CTL_ICEDEBUG_PosJÚPWDT_CTL_ICEDEBUG_MskQÚPWDT_ALTCTL_RSTDSEL_Pos|ÚPWDT_ALTCTL_RSTDSEL_MskƒÚ8


<unnamed>QÚ 


"úRLDCNTîÚ 


"úCTLØÚ 


"úSTATUSÑÚ 


"úCNTÖÚWWDT_TüÚPWWDT_RLDCNT_RLDCNT_Pos|ÚPWWDT_RLDCNT_RLDCNT_MskƒÚPWWDT_CTL_WWDTEN_PosTÚPWWDT_CTL_WWDTEN_Msk[ÚPWWDT_CTL_INTEN_Pos±ÚPWWDT_CTL_INTEN_Msk¸ÚPWWDT_CTL_PSCSEL_PoscÚPWWDT_CTL_PSCSEL_MskjÚPWWDT_CTL_CMPDAT_PostÚPWWDT_CTL_CMPDAT_Msk{ÚPWWDT_CTL_ICEDEBUG_PosñÚPWWDT_CTL_ICEDEBUG_MskøÚPWWDT_STATUS_WWDTIF_PosQÚPWWDT_STATUS_WWDTIF_MskXÚPWWDT_STATUS_WWDTRF_PosHÚPWWDT_STATUS_WWDTRF_MskOÚPWWDT_STATUS_WWDTF_PosœÚPWWDT_STATUS_WWDTF_Msk£ÚPWWDT_CNT_CNTDAT_PosmÚPWWDT_CNT_CNTDAT_MsktÚ8


<unnamed>QÚ 


"”CLKPSCZÚ 


"”CLKDIV]Ú 


"”CTL=Ú 


"”PERIOD0%Ú 


"”PERIOD1$Ú 


"”PERIOD2#Ú 


"”PERIOD3"Ú 


"”PERIOD4!Ú 


"”PERIOD5 Ú 


"”PERIOD6Ú 


"”PERIOD7Ú 


"”CMPDAT0/Ú 


"”CMPDAT1.Ú 


"”CMPDAT2-Ú 


"”CMPDAT3,Ú 


"”CMPDAT4+Ú 


"”CMPDAT5*Ú 


"”CMPDAT6)Ú 


"”CMPDAT7(Ú 


"”CTL2    Ú 


"”FLAGÚ 


"”INTENžÚ 


"”INTSTS5Ú 


"”POENìÚ <"”


RESERVED0RÚ 


"”DTCTL¡Ú 


"”    ADCTCTL0çÚ 


"”    ADCTCTL1æÚ 


"”    ADCTSTS0ÐÚ 


"”    ADCTSTS1ÏÚ <"”


RESERVED1EÚ 


"”PCACTLcÚPWM_TPÚ PPWM_CLKPSC_CLKPSC01_PosyÚ PPWM_CLKPSC_CLKPSC01_Msk€Ú PPWM_CLKPSC_CLKPSC23_PosuÚ PPWM_CLKPSC_CLKPSC23_Msk|Ú PPWM_CLKPSC_CLKPSC45_PosqÚ PPWM_CLKPSC_CLKPSC45_MskxÚ PPWM_CLKPSC_CLKPSC67_PosmÚ PPWM_CLKPSC_CLKPSC67_MsktÚPPWM_CLKDIV_CLKDIV0_Pos²ÚPPWM_CLKDIV_CLKDIV0_Msk¹ÚPPWM_CLKDIV_CLKDIV1_Pos±ÚPPWM_CLKDIV_CLKDIV1_Msk¸ÚPPWM_CLKDIV_CLKDIV2_Pos°ÚPPWM_CLKDIV_CLKDIV2_Msk·ÚPPWM_CLKDIV_CLKDIV3_Pos¯ÚPPWM_CLKDIV_CLKDIV3_Msk¶ÚPPWM_CLKDIV_CLKDIV4_Pos®ÚPPWM_CLKDIV_CLKDIV4_MskµÚPPWM_CLKDIV_CLKDIV5_Pos­ÚPPWM_CLKDIV_CLKDIV5_Msk´ÚPPWM_CLKDIV_CLKDIV6_Pos¬ÚPPWM_CLKDIV_CLKDIV6_Msk³ÚPPWM_CLKDIV_CLKDIV7_Pos«ÚPPWM_CLKDIV_CLKDIV7_Msk²ÚPPWM_CTL_CNTEN0_PosÙÚPPWM_CTL_CNTEN0_MskàÚPPWM_CTL_PINV0_PosÚPPWM_CTL_PINV0_MskÚPPWM_CTL_CNTMODE0_PosCÚPPWM_CTL_CNTMODE0_MskJÚPPWM_CTL_CNTEN1_PosØÚPPWM_CTL_CNTEN1_MskßÚPPWM_CTL_HCUPDT_Pos¹ÚPPWM_CTL_HCUPDT_MskÀÚPPWM_CTL_PINV1_PosÚPPWM_CTL_PINV1_MskÚPPWM_CTL_CNTMODE1_PosBÚPPWM_CTL_CNTMODE1_MskIÚPPWM_CTL_CNTEN2_Pos×ÚPPWM_CTL_CNTEN2_MskÞÚPPWM_CTL_PINV2_PosÚPPWM_CTL_PINV2_MskÚPPWM_CTL_CNTMODE2_PosAÚPPWM_CTL_CNTMODE2_MskHÚPPWM_CTL_CNTEN3_PosÖÚPPWM_CTL_CNTEN3_MskÝÚPPWM_CTL_PINV3_PosÚPPWM_CTL_PINV3_MskÚPPWM_CTL_CNTMODE3_Pos@ÚPPWM_CTL_CNTMODE3_MskGÚPPWM_CTL_CNTEN4_PosÕÚPPWM_CTL_CNTEN4_MskÜÚPPWM_CTL_PINV4_PosÚPPWM_CTL_PINV4_MskÚPPWM_CTL_CNTMODE4_Pos?ÚPPWM_CTL_CNTMODE4_MskFÚPPWM_CTL_CNTEN5_PosÔÚPPWM_CTL_CNTEN5_MskÛÚPPWM_CTL_ASYMEN_Pos´ÚPPWM_CTL_ASYMEN_Msk»ÚPPWM_CTL_PINV5_PosÚPPWM_CTL_PINV5_MskÚPPWM_CTL_CNTMODE5_Pos>ÚPPWM_CTL_CNTMODE5_MskEÚPPWM_CTL_CNTEN6_PosÓÚPPWM_CTL_CNTEN6_MskÚÚPPWM_CTL_PINV6_PosÚPPWM_CTL_PINV6_MskÚPPWM_CTL_CNTMODE6_Pos=ÚPPWM_CTL_CNTMODE6_MskDÚPPWM_CTL_CNTEN7_PosÒÚPPWM_CTL_CNTEN7_MskÙÚPPWM_CTL_PINV7_PosÚPPWM_CTL_PINV7_MskÚPPWM_CTL_CNTMODE7_Pos<ÚPPWM_CTL_CNTMODE7_MskCÚ PPWM_PERIOD0_PERIOD0_PostÚ PPWM_PERIOD0_PERIOD0_Msk{Ú PPWM_PERIOD0_PERIOD1_PossÚ PPWM_PERIOD0_PERIOD1_MskzÚ PPWM_PERIOD0_PERIOD2_PosrÚ PPWM_PERIOD0_PERIOD2_MskyÚ PPWM_PERIOD0_PERIOD3_PosqÚ PPWM_PERIOD0_PERIOD3_MskxÚ PPWM_PERIOD0_PERIOD4_PospÚ PPWM_PERIOD0_PERIOD4_MskwÚ PPWM_PERIOD0_PERIOD5_PosoÚ PPWM_PERIOD0_PERIOD5_MskvÚ PPWM_PERIOD0_PERIOD6_PosnÚ PPWM_PERIOD0_PERIOD6_MskuÚ PPWM_PERIOD0_PERIOD7_PosmÚ PPWM_PERIOD0_PERIOD7_MsktÚ PPWM_PERIOD1_PERIOD0_PossÚ PPWM_PERIOD1_PERIOD0_MskzÚ PPWM_PERIOD1_PERIOD1_PosrÚ PPWM_PERIOD1_PERIOD1_MskyÚ PPWM_PERIOD1_PERIOD2_PosqÚ PPWM_PERIOD1_PERIOD2_MskxÚ PPWM_PERIOD1_PERIOD3_PospÚ PPWM_PERIOD1_PERIOD3_MskwÚ PPWM_PERIOD1_PERIOD4_PosoÚ PPWM_PERIOD1_PERIOD4_MskvÚ PPWM_PERIOD1_PERIOD5_PosnÚ PPWM_PERIOD1_PERIOD5_MskuÚ PPWM_PERIOD1_PERIOD6_PosmÚ PPWM_PERIOD1_PERIOD6_MsktÚ PPWM_PERIOD1_PERIOD7_PoslÚ PPWM_PERIOD1_PERIOD7_MsksÚ PPWM_PERIOD2_PERIOD0_PosrÚ PPWM_PERIOD2_PERIOD0_MskyÚ PPWM_PERIOD2_PERIOD1_PosqÚ PPWM_PERIOD2_PERIOD1_MskxÚ PPWM_PERIOD2_PERIOD2_PospÚ PPWM_PERIOD2_PERIOD2_MskwÚ PPWM_PERIOD2_PERIOD3_PosoÚ PPWM_PERIOD2_PERIOD3_MskvÚ PPWM_PERIOD2_PERIOD4_PosnÚ PPWM_PERIOD2_PERIOD4_MskuÚ PPWM_PERIOD2_PERIOD5_PosmÚ PPWM_PERIOD2_PERIOD5_MsktÚ PPWM_PERIOD2_PERIOD6_PoslÚ PPWM_PERIOD2_PERIOD6_MsksÚ PPWM_PERIOD2_PERIOD7_PoskÚ PPWM_PERIOD2_PERIOD7_MskrÚ PPWM_PERIOD3_PERIOD0_PosqÚ PPWM_PERIOD3_PERIOD0_MskxÚ PPWM_PERIOD3_PERIOD1_PospÚ PPWM_PERIOD3_PERIOD1_MskwÚ PPWM_PERIOD3_PERIOD2_PosoÚ PPWM_PERIOD3_PERIOD2_MskvÚ PPWM_PERIOD3_PERIOD3_PosnÚ PPWM_PERIOD3_PERIOD3_MskuÚ PPWM_PERIOD3_PERIOD4_PosmÚ PPWM_PERIOD3_PERIOD4_MsktÚ PPWM_PERIOD3_PERIOD5_PoslÚ PPWM_PERIOD3_PERIOD5_MsksÚ PPWM_PERIOD3_PERIOD6_PoskÚ PPWM_PERIOD3_PERIOD6_MskrÚ PPWM_PERIOD3_PERIOD7_PosjÚ PPWM_PERIOD3_PERIOD7_MskqÚ PPWM_PERIOD4_PERIOD0_PospÚ PPWM_PERIOD4_PERIOD0_MskwÚ PPWM_PERIOD4_PERIOD1_PosoÚ PPWM_PERIOD4_PERIOD1_MskvÚ PPWM_PERIOD4_PERIOD2_PosnÚ PPWM_PERIOD4_PERIOD2_MskuÚ PPWM_PERIOD4_PERIOD3_PosmÚ PPWM_PERIOD4_PERIOD3_MsktÚ PPWM_PERIOD4_PERIOD4_PoslÚ PPWM_PERIOD4_PERIOD4_MsksÚ PPWM_PERIOD4_PERIOD5_PoskÚ PPWM_PERIOD4_PERIOD5_MskrÚ PPWM_PERIOD4_PERIOD6_PosjÚ PPWM_PERIOD4_PERIOD6_MskqÚ PPWM_PERIOD4_PERIOD7_PosiÚ PPWM_PERIOD4_PERIOD7_MskpÚ PPWM_PERIOD5_PERIOD0_PosoÚ PPWM_PERIOD5_PERIOD0_MskvÚ PPWM_PERIOD5_PERIOD1_PosnÚ PPWM_PERIOD5_PERIOD1_MskuÚ PPWM_PERIOD5_PERIOD2_PosmÚ PPWM_PERIOD5_PERIOD2_MsktÚ PPWM_PERIOD5_PERIOD3_PoslÚ PPWM_PERIOD5_PERIOD3_MsksÚ PPWM_PERIOD5_PERIOD4_PoskÚ PPWM_PERIOD5_PERIOD4_MskrÚ PPWM_PERIOD5_PERIOD5_PosjÚ PPWM_PERIOD5_PERIOD5_MskqÚ PPWM_PERIOD5_PERIOD6_PosiÚ PPWM_PERIOD5_PERIOD6_MskpÚ PPWM_PERIOD5_PERIOD7_PoshÚ PPWM_PERIOD5_PERIOD7_MskoÚ PPWM_PERIOD6_PERIOD0_PosnÚ PPWM_PERIOD6_PERIOD0_MskuÚ PPWM_PERIOD6_PERIOD1_PosmÚ PPWM_PERIOD6_PERIOD1_MsktÚ PPWM_PERIOD6_PERIOD2_PoslÚ PPWM_PERIOD6_PERIOD2_MsksÚ PPWM_PERIOD6_PERIOD3_PoskÚ PPWM_PERIOD6_PERIOD3_MskrÚ PPWM_PERIOD6_PERIOD4_PosjÚ PPWM_PERIOD6_PERIOD4_MskqÚ PPWM_PERIOD6_PERIOD5_PosiÚ PPWM_PERIOD6_PERIOD5_MskpÚ PPWM_PERIOD6_PERIOD6_PoshÚ PPWM_PERIOD6_PERIOD6_MskoÚ PPWM_PERIOD6_PERIOD7_PosgÚ PPWM_PERIOD6_PERIOD7_MsknÚ PPWM_PERIOD7_PERIOD0_PosmÚ PPWM_PERIOD7_PERIOD0_MsktÚ PPWM_PERIOD7_PERIOD1_PoslÚ PPWM_PERIOD7_PERIOD1_MsksÚ PPWM_PERIOD7_PERIOD2_PoskÚ PPWM_PERIOD7_PERIOD2_MskrÚ PPWM_PERIOD7_PERIOD3_PosjÚ PPWM_PERIOD7_PERIOD3_MskqÚ PPWM_PERIOD7_PERIOD4_PosiÚ PPWM_PERIOD7_PERIOD4_MskpÚ PPWM_PERIOD7_PERIOD5_PoshÚ PPWM_PERIOD7_PERIOD5_MskoÚ PPWM_PERIOD7_PERIOD6_PosgÚ PPWM_PERIOD7_PERIOD6_MsknÚ PPWM_PERIOD7_PERIOD7_PosfÚ PPWM_PERIOD7_PERIOD7_MskmÚPPWM_CMPDAT0_CMP0_PosgÚPPWM_CMPDAT0_CMP0_MsknÚPPWM_CMPDAT0_CMP1_PosfÚPPWM_CMPDAT0_CMP1_MskmÚPPWM_CMPDAT0_CMP2_PoseÚPPWM_CMPDAT0_CMP2_MsklÚPPWM_CMPDAT0_CMP3_PosdÚPPWM_CMPDAT0_CMP3_MskkÚPPWM_CMPDAT0_CMP4_PoscÚPPWM_CMPDAT0_CMP4_MskjÚPPWM_CMPDAT0_CMP5_PosbÚPPWM_CMPDAT0_CMP5_MskiÚPPWM_CMPDAT0_CMP6_PosaÚPPWM_CMPDAT0_CMP6_MskhÚPPWM_CMPDAT0_CMP7_Pos`ÚPPWM_CMPDAT0_CMP7_MskgÚPPWM_CMPDAT0_CMPD0_Pos!ÚPPWM_CMPDAT0_CMPD0_Msk(ÚPPWM_CMPDAT0_CMPD1_Pos ÚPPWM_CMPDAT0_CMPD1_Msk'ÚPPWM_CMPDAT0_CMPD2_PosÚPPWM_CMPDAT0_CMPD2_Msk&ÚPPWM_CMPDAT0_CMPD3_PosÚPPWM_CMPDAT0_CMPD3_Msk%ÚPPWM_CMPDAT0_CMPD4_PosÚPPWM_CMPDAT0_CMPD4_Msk$ÚPPWM_CMPDAT0_CMPD5_PosÚPPWM_CMPDAT0_CMPD5_Msk#ÚPPWM_CMPDAT0_CMPD6_PosÚPPWM_CMPDAT0_CMPD6_Msk"ÚPPWM_CMPDAT0_CMPD7_PosÚPPWM_CMPDAT0_CMPD7_Msk!ÚPPWM_CMPDAT1_CMP0_PosfÚPPWM_CMPDAT1_CMP0_MskmÚPPWM_CMPDAT1_CMP1_PoseÚPPWM_CMPDAT1_CMP1_MsklÚPPWM_CMPDAT1_CMP2_PosdÚPPWM_CMPDAT1_CMP2_MskkÚPPWM_CMPDAT1_CMP3_PoscÚPPWM_CMPDAT1_CMP3_MskjÚPPWM_CMPDAT1_CMP4_PosbÚPPWM_CMPDAT1_CMP4_MskiÚPPWM_CMPDAT1_CMP5_PosaÚPPWM_CMPDAT1_CMP5_MskhÚPPWM_CMPDAT1_CMP6_Pos`ÚPPWM_CMPDAT1_CMP6_MskgÚPPWM_CMPDAT1_CMP7_Pos_ÚPPWM_CMPDAT1_CMP7_MskfÚPPWM_CMPDAT1_CMPD0_Pos ÚPPWM_CMPDAT1_CMPD0_Msk'ÚPPWM_CMPDAT1_CMPD1_PosÚPPWM_CMPDAT1_CMPD1_Msk&ÚPPWM_CMPDAT1_CMPD2_PosÚPPWM_CMPDAT1_CMPD2_Msk%ÚPPWM_CMPDAT1_CMPD3_PosÚPPWM_CMPDAT1_CMPD3_Msk$ÚPPWM_CMPDAT1_CMPD4_PosÚPPWM_CMPDAT1_CMPD4_Msk#ÚPPWM_CMPDAT1_CMPD5_PosÚPPWM_CMPDAT1_CMPD5_Msk"ÚPPWM_CMPDAT1_CMPD6_PosÚPPWM_CMPDAT1_CMPD6_Msk!ÚPPWM_CMPDAT1_CMPD7_PosÚPPWM_CMPDAT1_CMPD7_Msk ÚPPWM_CMPDAT2_CMP0_PoseÚPPWM_CMPDAT2_CMP0_MsklÚPPWM_CMPDAT2_CMP1_PosdÚPPWM_CMPDAT2_CMP1_MskkÚPPWM_CMPDAT2_CMP2_PoscÚPPWM_CMPDAT2_CMP2_MskjÚPPWM_CMPDAT2_CMP3_PosbÚPPWM_CMPDAT2_CMP3_MskiÚPPWM_CMPDAT2_CMP4_PosaÚPPWM_CMPDAT2_CMP4_MskhÚPPWM_CMPDAT2_CMP5_Pos`ÚPPWM_CMPDAT2_CMP5_MskgÚPPWM_CMPDAT2_CMP6_Pos_ÚPPWM_CMPDAT2_CMP6_MskfÚPPWM_CMPDAT2_CMP7_Pos^ÚPPWM_CMPDAT2_CMP7_MskeÚPPWM_CMPDAT2_CMPD0_PosÚPPWM_CMPDAT2_CMPD0_Msk&ÚPPWM_CMPDAT2_CMPD1_PosÚPPWM_CMPDAT2_CMPD1_Msk%ÚPPWM_CMPDAT2_CMPD2_PosÚPPWM_CMPDAT2_CMPD2_Msk$ÚPPWM_CMPDAT2_CMPD3_PosÚPPWM_CMPDAT2_CMPD3_Msk#ÚPPWM_CMPDAT2_CMPD4_PosÚPPWM_CMPDAT2_CMPD4_Msk"ÚPPWM_CMPDAT2_CMPD5_PosÚPPWM_CMPDAT2_CMPD5_Msk!ÚPPWM_CMPDAT2_CMPD6_PosÚPPWM_CMPDAT2_CMPD6_Msk ÚPPWM_CMPDAT2_CMPD7_PosÚPPWM_CMPDAT2_CMPD7_MskÚPPWM_CMPDAT3_CMP0_PosdÚPPWM_CMPDAT3_CMP0_MskkÚPPWM_CMPDAT3_CMP1_PoscÚPPWM_CMPDAT3_CMP1_MskjÚPPWM_CMPDAT3_CMP2_PosbÚPPWM_CMPDAT3_CMP2_MskiÚPPWM_CMPDAT3_CMP3_PosaÚPPWM_CMPDAT3_CMP3_MskhÚPPWM_CMPDAT3_CMP4_Pos`ÚPPWM_CMPDAT3_CMP4_MskgÚPPWM_CMPDAT3_CMP5_Pos_ÚPPWM_CMPDAT3_CMP5_MskfÚPPWM_CMPDAT3_CMP6_Pos^ÚPPWM_CMPDAT3_CMP6_MskeÚPPWM_CMPDAT3_CMP7_Pos]ÚPPWM_CMPDAT3_CMP7_MskdÚPPWM_CMPDAT3_CMPD0_PosÚPPWM_CMPDAT3_CMPD0_Msk%ÚPPWM_CMPDAT3_CMPD1_PosÚPPWM_CMPDAT3_CMPD1_Msk$ÚPPWM_CMPDAT3_CMPD2_PosÚPPWM_CMPDAT3_CMPD2_Msk#ÚPPWM_CMPDAT3_CMPD3_PosÚPPWM_CMPDAT3_CMPD3_Msk"ÚPPWM_CMPDAT3_CMPD4_PosÚPPWM_CMPDAT3_CMPD4_Msk!ÚPPWM_CMPDAT3_CMPD5_PosÚPPWM_CMPDAT3_CMPD5_Msk ÚPPWM_CMPDAT3_CMPD6_PosÚPPWM_CMPDAT3_CMPD6_MskÚPPWM_CMPDAT3_CMPD7_PosÚPPWM_CMPDAT3_CMPD7_MskÚPPWM_CMPDAT4_CMP0_PoscÚPPWM_CMPDAT4_CMP0_MskjÚPPWM_CMPDAT4_CMP1_PosbÚPPWM_CMPDAT4_CMP1_MskiÚPPWM_CMPDAT4_CMP2_PosaÚPPWM_CMPDAT4_CMP2_MskhÚPPWM_CMPDAT4_CMP3_Pos`ÚPPWM_CMPDAT4_CMP3_MskgÚPPWM_CMPDAT4_CMP4_Pos_ÚPPWM_CMPDAT4_CMP4_MskfÚPPWM_CMPDAT4_CMP5_Pos^ÚPPWM_CMPDAT4_CMP5_MskeÚPPWM_CMPDAT4_CMP6_Pos]ÚPPWM_CMPDAT4_CMP6_MskdÚPPWM_CMPDAT4_CMP7_Pos\ÚPPWM_CMPDAT4_CMP7_MskcÚPPWM_CMPDAT4_CMPD0_PosÚPPWM_CMPDAT4_CMPD0_Msk$ÚPPWM_CMPDAT4_CMPD1_PosÚPPWM_CMPDAT4_CMPD1_Msk#ÚPPWM_CMPDAT4_CMPD2_PosÚPPWM_CMPDAT4_CMPD2_Msk"ÚPPWM_CMPDAT4_CMPD3_PosÚPPWM_CMPDAT4_CMPD3_Msk!ÚPPWM_CMPDAT4_CMPD4_PosÚPPWM_CMPDAT4_CMPD4_Msk ÚPPWM_CMPDAT4_CMPD5_PosÚPPWM_CMPDAT4_CMPD5_MskÚPPWM_CMPDAT4_CMPD6_PosÚPPWM_CMPDAT4_CMPD6_MskÚPPWM_CMPDAT4_CMPD7_PosÚPPWM_CMPDAT4_CMPD7_MskÚPPWM_CMPDAT5_CMP0_PosbÚPPWM_CMPDAT5_CMP0_MskiÚPPWM_CMPDAT5_CMP1_PosaÚPPWM_CMPDAT5_CMP1_MskhÚPPWM_CMPDAT5_CMP2_Pos`ÚPPWM_CMPDAT5_CMP2_MskgÚPPWM_CMPDAT5_CMP3_Pos_ÚPPWM_CMPDAT5_CMP3_MskfÚPPWM_CMPDAT5_CMP4_Pos^ÚPPWM_CMPDAT5_CMP4_MskeÚPPWM_CMPDAT5_CMP5_Pos]ÚPPWM_CMPDAT5_CMP5_MskdÚPPWM_CMPDAT5_CMP6_Pos\ÚPPWM_CMPDAT5_CMP6_MskcÚPPWM_CMPDAT5_CMP7_Pos[ÚPPWM_CMPDAT5_CMP7_MskbÚPPWM_CMPDAT5_CMPD0_PosÚPPWM_CMPDAT5_CMPD0_Msk#ÚPPWM_CMPDAT5_CMPD1_PosÚPPWM_CMPDAT5_CMPD1_Msk"ÚPPWM_CMPDAT5_CMPD2_PosÚPPWM_CMPDAT5_CMPD2_Msk!ÚPPWM_CMPDAT5_CMPD3_PosÚPPWM_CMPDAT5_CMPD3_Msk ÚPPWM_CMPDAT5_CMPD4_PosÚPPWM_CMPDAT5_CMPD4_MskÚPPWM_CMPDAT5_CMPD5_PosÚPPWM_CMPDAT5_CMPD5_MskÚPPWM_CMPDAT5_CMPD6_PosÚPPWM_CMPDAT5_CMPD6_MskÚPPWM_CMPDAT5_CMPD7_PosÚPPWM_CMPDAT5_CMPD7_MskÚPPWM_CMPDAT6_CMP0_PosaÚPPWM_CMPDAT6_CMP0_MskhÚPPWM_CMPDAT6_CMP1_Pos`ÚPPWM_CMPDAT6_CMP1_MskgÚPPWM_CMPDAT6_CMP2_Pos_ÚPPWM_CMPDAT6_CMP2_MskfÚPPWM_CMPDAT6_CMP3_Pos^ÚPPWM_CMPDAT6_CMP3_MskeÚPPWM_CMPDAT6_CMP4_Pos]ÚPPWM_CMPDAT6_CMP4_MskdÚPPWM_CMPDAT6_CMP5_Pos\ÚPPWM_CMPDAT6_CMP5_MskcÚPPWM_CMPDAT6_CMP6_Pos[ÚPPWM_CMPDAT6_CMP6_MskbÚPPWM_CMPDAT6_CMP7_PosZÚPPWM_CMPDAT6_CMP7_MskaÚPPWM_CMPDAT6_CMPD0_PosÚPPWM_CMPDAT6_CMPD0_Msk"ÚPPWM_CMPDAT6_CMPD1_PosÚPPWM_CMPDAT6_CMPD1_Msk!ÚPPWM_CMPDAT6_CMPD2_PosÚPPWM_CMPDAT6_CMPD2_Msk ÚPPWM_CMPDAT6_CMPD3_PosÚPPWM_CMPDAT6_CMPD3_MskÚPPWM_CMPDAT6_CMPD4_PosÚPPWM_CMPDAT6_CMPD4_MskÚPPWM_CMPDAT6_CMPD5_PosÚPPWM_CMPDAT6_CMPD5_MskÚPPWM_CMPDAT6_CMPD6_PosÚPPWM_CMPDAT6_CMPD6_MskÚPPWM_CMPDAT6_CMPD7_PosÚPPWM_CMPDAT6_CMPD7_MskÚPPWM_CMPDAT7_CMP0_Pos`ÚPPWM_CMPDAT7_CMP0_MskgÚPPWM_CMPDAT7_CMP1_Pos_ÚPPWM_CMPDAT7_CMP1_MskfÚPPWM_CMPDAT7_CMP2_Pos^ÚPPWM_CMPDAT7_CMP2_MskeÚPPWM_CMPDAT7_CMP3_Pos]ÚPPWM_CMPDAT7_CMP3_MskdÚPPWM_CMPDAT7_CMP4_Pos\ÚPPWM_CMPDAT7_CMP4_MskcÚPPWM_CMPDAT7_CMP5_Pos[ÚPPWM_CMPDAT7_CMP5_MskbÚPPWM_CMPDAT7_CMP6_PosZÚPPWM_CMPDAT7_CMP6_MskaÚPPWM_CMPDAT7_CMP7_PosYÚPPWM_CMPDAT7_CMP7_Msk`ÚPPWM_CMPDAT7_CMPD0_PosÚPPWM_CMPDAT7_CMPD0_Msk!ÚPPWM_CMPDAT7_CMPD1_PosÚPPWM_CMPDAT7_CMPD1_Msk ÚPPWM_CMPDAT7_CMPD2_PosÚPPWM_CMPDAT7_CMPD2_MskÚPPWM_CMPDAT7_CMPD3_PosÚPPWM_CMPDAT7_CMPD3_MskÚPPWM_CMPDAT7_CMPD4_PosÚPPWM_CMPDAT7_CMPD4_MskÚPPWM_CMPDAT7_CMPD5_PosÚPPWM_CMPDAT7_CMPD5_MskÚPPWM_CMPDAT7_CMPD6_PosÚPPWM_CMPDAT7_CMPD6_MskÚPPWM_CMPDAT7_CMPD7_PosÚPPWM_CMPDAT7_CMPD7_MskÚPPWM_CTL2_BRKIEN_Pos’ÚPPWM_CTL2_BRKIEN_Msk™ÚPPWM_CTL2_PINTTYPE_PosÌÚPPWM_CTL2_PINTTYPE_MskÓÚPPWM_CTL2_DTCNT01_PosmÚPPWM_CTL2_DTCNT01_MsktÚPPWM_CTL2_DTCNT23_PosiÚPPWM_CTL2_DTCNT23_MskpÚPPWM_CTL2_DTCNT45_PoseÚPPWM_CTL2_DTCNT45_MsklÚPPWM_CTL2_DTCNT67_PosaÚPPWM_CTL2_DTCNT67_MskhÚPPWM_CTL2_CNTCLR_Pos‡ÚPPWM_CTL2_CNTCLR_MskŽÚPPWM_CTL2_MODE_Pos,ÚPPWM_CTL2_MODE_Msk3ÚPPWM_CTL2_GROUPEN_Pos+ÚPPWM_CTL2_GROUPEN_Msk2ÚPPWM_CTL2_CNTTYPE_Pos$ÚPPWM_CTL2_CNTTYPE_Msk+ÚPPWM_FLAG_ZF0_Pos~ÚPPWM_FLAG_ZF0_Msk…ÚPPWM_FLAG_ZF1_Pos}ÚPPWM_FLAG_ZF1_Msk„ÚPPWM_FLAG_ZF2_Pos|ÚPPWM_FLAG_ZF2_MskƒÚPPWM_FLAG_ZF3_Pos{ÚPPWM_FLAG_ZF3_Msk‚ÚPPWM_FLAG_ZF4_PoszÚPPWM_FLAG_ZF4_MskÚPPWM_FLAG_ZF5_PosyÚPPWM_FLAG_ZF5_Msk€ÚPPWM_FLAG_ZF6_PosxÚPPWM_FLAG_ZF6_MskÚPPWM_FLAG_ZF7_PoswÚPPWM_FLAG_ZF7_Msk~ÚPPWM_FLAG_CMPDF0_Pos®ÚPPWM_FLAG_CMPDF0_MskµÚPPWM_FLAG_CMPDF1_Pos­ÚPPWM_FLAG_CMPDF1_Msk´ÚPPWM_FLAG_CMPDF2_Pos¬ÚPPWM_FLAG_CMPDF2_Msk³ÚPPWM_FLAG_CMPDF3_Pos«ÚPPWM_FLAG_CMPDF3_Msk²ÚPPWM_FLAG_CMPDF4_PosªÚPPWM_FLAG_CMPDF4_Msk±ÚPPWM_FLAG_CMPDF5_Pos©ÚPPWM_FLAG_CMPDF5_Msk°ÚPPWM_FLAG_CMPDF6_Pos¨ÚPPWM_FLAG_CMPDF6_Msk¯ÚPPWM_FLAG_CMPDF7_Pos§ÚPPWM_FLAG_CMPDF7_Msk®ÚPPWM_FLAG_PF0_PosˆÚPPWM_FLAG_PF0_MskÚPPWM_FLAG_PF1_Pos‡ÚPPWM_FLAG_PF1_MskŽÚPPWM_FLAG_PF2_Pos†ÚPPWM_FLAG_PF2_MskÚPPWM_FLAG_PF3_Pos…ÚPPWM_FLAG_PF3_MskŒÚPPWM_FLAG_PF4_Pos„ÚPPWM_FLAG_PF4_Msk‹ÚPPWM_FLAG_PF5_PosƒÚPPWM_FLAG_PF5_MskŠÚPPWM_FLAG_PF6_Pos‚ÚPPWM_FLAG_PF6_Msk‰ÚPPWM_FLAG_PF7_PosÚPPWM_FLAG_PF7_MskˆÚPPWM_FLAG_CMPUF0_PosÚPPWM_FLAG_CMPUF0_Msk¤ÚPPWM_FLAG_CMPUF1_PosœÚPPWM_FLAG_CMPUF1_Msk£ÚPPWM_FLAG_CMPUF2_Pos›ÚPPWM_FLAG_CMPUF2_Msk¢ÚPPWM_FLAG_CMPUF3_PosšÚPPWM_FLAG_CMPUF3_Msk¡ÚPPWM_FLAG_CMPUF4_Pos™ÚPPWM_FLAG_CMPUF4_Msk ÚPPWM_FLAG_CMPUF5_Pos˜ÚPPWM_FLAG_CMPUF5_MskŸÚPPWM_FLAG_CMPUF6_Pos—ÚPPWM_FLAG_CMPUF6_MskžÚPPWM_FLAG_CMPUF7_Pos–ÚPPWM_FLAG_CMPUF7_MskÚPPWM_INTEN_ZIEN0_Pos~ÚPPWM_INTEN_ZIEN0_Msk…ÚPPWM_INTEN_ZIEN1_Pos}ÚPPWM_INTEN_ZIEN1_Msk„ÚPPWM_INTEN_ZIEN2_Pos|ÚPPWM_INTEN_ZIEN2_MskƒÚPPWM_INTEN_ZIEN3_Pos{ÚPPWM_INTEN_ZIEN3_Msk‚ÚPPWM_INTEN_ZIEN4_PoszÚPPWM_INTEN_ZIEN4_MskÚPPWM_INTEN_ZIEN5_PosyÚPPWM_INTEN_ZIEN5_Msk€ÚPPWM_INTEN_ZIEN6_PosxÚPPWM_INTEN_ZIEN6_MskÚPPWM_INTEN_ZIEN7_PoswÚPPWM_INTEN_ZIEN7_Msk~ÚPPWM_INTEN_CMPDIEN0_Pos®ÚPPWM_INTEN_CMPDIEN0_MskµÚPPWM_INTEN_CMPDIEN1_Pos­ÚPPWM_INTEN_CMPDIEN1_Msk´ÚPPWM_INTEN_CMPDIEN2_Pos¬ÚPPWM_INTEN_CMPDIEN2_Msk³ÚPPWM_INTEN_CMPDIEN3_Pos«ÚPPWM_INTEN_CMPDIEN3_Msk²ÚPPWM_INTEN_CMPDIEN4_PosªÚPPWM_INTEN_CMPDIEN4_Msk±ÚPPWM_INTEN_CMPDIEN5_Pos©ÚPPWM_INTEN_CMPDIEN5_Msk°ÚPPWM_INTEN_CMPDIEN6_Pos¨ÚPPWM_INTEN_CMPDIEN6_Msk¯ÚPPWM_INTEN_CMPDIEN7_Pos§ÚPPWM_INTEN_CMPDIEN7_Msk®ÚPPWM_INTEN_PIEN0_PosˆÚPPWM_INTEN_PIEN0_MskÚPPWM_INTEN_PIEN1_Pos‡ÚPPWM_INTEN_PIEN1_MskŽÚPPWM_INTEN_PIEN2_Pos†ÚPPWM_INTEN_PIEN2_MskÚPPWM_INTEN_PIEN3_Pos…ÚPPWM_INTEN_PIEN3_MskŒÚPPWM_INTEN_PIEN4_Pos„ÚPPWM_INTEN_PIEN4_Msk‹ÚPPWM_INTEN_PIEN5_PosƒÚPPWM_INTEN_PIEN5_MskŠÚPPWM_INTEN_PIEN6_Pos‚ÚPPWM_INTEN_PIEN6_Msk‰ÚPPWM_INTEN_PIEN7_PosÚPPWM_INTEN_PIEN7_MskˆÚPPWM_INTEN_CMPUIEN0_PosÚPPWM_INTEN_CMPUIEN0_Msk¤ÚPPWM_INTEN_CMPUIEN1_PosœÚPPWM_INTEN_CMPUIEN1_Msk£ÚPPWM_INTEN_CMPUIEN2_Pos›ÚPPWM_INTEN_CMPUIEN2_Msk¢ÚPPWM_INTEN_CMPUIEN3_PosšÚPPWM_INTEN_CMPUIEN3_Msk¡ÚPPWM_INTEN_CMPUIEN4_Pos™ÚPPWM_INTEN_CMPUIEN4_Msk ÚPPWM_INTEN_CMPUIEN5_Pos˜ÚPPWM_INTEN_CMPUIEN5_MskŸÚPPWM_INTEN_CMPUIEN6_Pos—ÚPPWM_INTEN_CMPUIEN6_MskžÚPPWM_INTEN_CMPUIEN7_Pos–ÚPPWM_INTEN_CMPUIEN7_MskÚPPWM_INTSTS_ZIF0_PosdÚPPWM_INTSTS_ZIF0_MskkÚPPWM_INTSTS_ZIF1_PoscÚPPWM_INTSTS_ZIF1_MskjÚPPWM_INTSTS_ZIF2_PosbÚPPWM_INTSTS_ZIF2_MskiÚPPWM_INTSTS_ZIF3_PosaÚPPWM_INTSTS_ZIF3_MskhÚPPWM_INTSTS_ZIF4_Pos`ÚPPWM_INTSTS_ZIF4_MskgÚPPWM_INTSTS_ZIF5_Pos_ÚPPWM_INTSTS_ZIF5_MskfÚPPWM_INTSTS_ZIF6_Pos^ÚPPWM_INTSTS_ZIF6_MskeÚPPWM_INTSTS_ZIF7_Pos]ÚPPWM_INTSTS_ZIF7_MskdÚPPWM_INTSTS_CMPDIF0_Pos”ÚPPWM_INTSTS_CMPDIF0_Msk›ÚPPWM_INTSTS_CMPDIF1_Pos“ÚPPWM_INTSTS_CMPDIF1_MskšÚPPWM_INTSTS_CMPDIF2_Pos’ÚPPWM_INTSTS_CMPDIF2_Msk™ÚPPWM_INTSTS_CMPDIF3_Pos‘ÚPPWM_INTSTS_CMPDIF3_Msk˜ÚPPWM_INTSTS_CMPDIF4_PosÚPPWM_INTSTS_CMPDIF4_Msk—ÚPPWM_INTSTS_CMPDIF5_PosÚPPWM_INTSTS_CMPDIF5_Msk–ÚPPWM_INTSTS_CMPDIF6_PosŽÚPPWM_INTSTS_CMPDIF6_Msk•ÚPPWM_INTSTS_CMPDIF7_PosÚPPWM_INTSTS_CMPDIF7_Msk”ÚPPWM_INTSTS_PIF0_PosnÚPPWM_INTSTS_PIF0_MskuÚPPWM_INTSTS_PIF1_PosmÚPPWM_INTSTS_PIF1_MsktÚPPWM_INTSTS_PIF2_PoslÚPPWM_INTSTS_PIF2_MsksÚPPWM_INTSTS_PIF3_PoskÚPPWM_INTSTS_PIF3_MskrÚPPWM_INTSTS_PIF4_PosjÚPPWM_INTSTS_PIF4_MskqÚPPWM_INTSTS_PIF5_PosiÚPPWM_INTSTS_PIF5_MskpÚPPWM_INTSTS_PIF6_PoshÚPPWM_INTSTS_PIF6_MskoÚPPWM_INTSTS_PIF7_PosgÚPPWM_INTSTS_PIF7_MsknÚPPWM_INTSTS_CMPUIF0_PosƒÚPPWM_INTSTS_CMPUIF0_MskŠÚPPWM_INTSTS_CMPUIF1_Pos‚ÚPPWM_INTSTS_CMPUIF1_Msk‰ÚPPWM_INTSTS_CMPUIF2_PosÚPPWM_INTSTS_CMPUIF2_MskˆÚPPWM_INTSTS_CMPUIF3_Pos€ÚPPWM_INTSTS_CMPUIF3_Msk‡ÚPPWM_INTSTS_CMPUIF4_PosÚPPWM_INTSTS_CMPUIF4_Msk†ÚPPWM_INTSTS_CMPUIF5_Pos~ÚPPWM_INTSTS_CMPUIF5_Msk…ÚPPWM_INTSTS_CMPUIF6_Pos}ÚPPWM_INTSTS_CMPUIF6_Msk„ÚPPWM_INTSTS_CMPUIF7_Pos|ÚPPWM_INTSTS_CMPUIF7_MskƒÚPPWM_POEN_POEN0_PosÐÚPPWM_POEN_POEN0_Msk×ÚPPWM_POEN_POEN1_PosÏÚPPWM_POEN_POEN1_MskÖÚPPWM_POEN_POEN2_PosÎÚPPWM_POEN_POEN2_MskÕÚPPWM_POEN_POEN3_PosÍÚPPWM_POEN_POEN3_MskÔÚPPWM_POEN_POEN4_PosÌÚPPWM_POEN_POEN4_MskÓÚPPWM_POEN_POEN5_PosËÚPPWM_POEN_POEN5_MskÒÚPPWM_POEN_POEN6_PosÊÚPPWM_POEN_POEN6_MskÑÚPPWM_POEN_POEN7_PosÉÚPPWM_POEN_POEN7_MskÐÚPPWM_BRKCTL_BRK0EN_PosúÚPPWM_BRKCTL_BRK0EN_MskÚPPWM_BRKCTL_BRK1EN_PosùÚPPWM_BRKCTL_BRK1EN_MskÚPPWM_BRKCTL_BRK0SEL_Pos§ÚPPWM_BRKCTL_BRK0SEL_Msk®ÚPPWM_BRKCTL_BRK1SEL_Pos¦ÚPPWM_BRKCTL_BRK1SEL_Msk­ÚPPWM_BRKCTL_BRKSTS_PosÃÚPPWM_BRKCTL_BRKSTS_MskÊÚPPWM_BRKCTL_BRKACT_PosåÚPPWM_BRKCTL_BRKACT_MskìÚPPWM_BRKCTL_SWBRK_PosÚPPWM_BRKCTL_SWBRK_MskÚPPWM_BRKCTL_BRKIF0_PosþÚPPWM_BRKCTL_BRKIF0_MskÚPPWM_BRKCTL_BRKIF1_PosýÚPPWM_BRKCTL_BRKIF1_MskÚPPWM_BRKCTL_BRKF0_PosIÚPPWM_BRKCTL_BRKF0_MskPÚPPWM_BRKCTL_BRKF1_PosHÚPPWM_BRKCTL_BRKF1_MskOÚPPWM_BRKCTL_BKOD0_PosNÚPPWM_BRKCTL_BKOD0_MskUÚPPWM_BRKCTL_BKOD1_PosMÚPPWM_BRKCTL_BKOD1_MskTÚPPWM_BRKCTL_BKOD2_PosLÚPPWM_BRKCTL_BKOD2_MskSÚPPWM_BRKCTL_BKOD3_PosKÚPPWM_BRKCTL_BKOD3_MskRÚPPWM_BRKCTL_BKOD4_PosJÚPPWM_BRKCTL_BKOD4_MskQÚPPWM_BRKCTL_BKOD5_PosIÚPPWM_BRKCTL_BKOD5_MskPÚPPWM_BRKCTL_D6BKOD_PosÚPPWM_BRKCTL_D6BKOD_Msk    ÚPPWM_BRKCTL_D7BKOD_PosÚPPWM_BRKCTL_D7BKOD_MskÚPPWM_DTCTL_DTI01_Pos¥ÚPPWM_DTCTL_DTI01_Msk¬ÚPPWM_DTCTL_DTI23_Pos¡ÚPPWM_DTCTL_DTI23_Msk¨ÚPPWM_DTCTL_DTI45_PosÚPPWM_DTCTL_DTI45_Msk¤ÚPPWM_DTCTL_DTI67_Pos™ÚPPWM_DTCTL_DTI67_Msk Ú"PPWM_ADCTCTL0_CUTRGEN0_PosßÚ"PPWM_ADCTCTL0_CUTRGEN0_MskæÚ"PPWM_ADCTCTL0_CPTRGEN0_PosäÚ"PPWM_ADCTCTL0_CPTRGEN0_MskëÚ"PPWM_ADCTCTL0_CDTRGEN0_PosðÚ"PPWM_ADCTCTL0_CDTRGEN0_Msk÷Ú"PPWM_ADCTCTL0_ZPTRGEN0_PosÍÚ"PPWM_ADCTCTL0_ZPTRGEN0_MskÔÚ"PPWM_ADCTCTL0_CUTRGEN1_PosÞÚ"PPWM_ADCTCTL0_CUTRGEN1_MskåÚ"PPWM_ADCTCTL0_CPTRGEN1_PosãÚ"PPWM_ADCTCTL0_CPTRGEN1_MskêÚ"PPWM_ADCTCTL0_CDTRGEN1_PosïÚ"PPWM_ADCTCTL0_CDTRGEN1_MsköÚ"PPWM_ADCTCTL0_ZPTRGEN1_PosÌÚ"PPWM_ADCTCTL0_ZPTRGEN1_MskÓÚ"PPWM_ADCTCTL0_CUTRGEN2_PosÝÚ"PPWM_ADCTCTL0_CUTRGEN2_MskäÚ"PPWM_ADCTCTL0_CPTRGEN2_PosâÚ"PPWM_ADCTCTL0_CPTRGEN2_MskéÚ"PPWM_ADCTCTL0_CDTRGEN2_PosîÚ"PPWM_ADCTCTL0_CDTRGEN2_MskõÚ"PPWM_ADCTCTL0_ZPTRGEN2_PosËÚ"PPWM_ADCTCTL0_ZPTRGEN2_MskÒÚ"PPWM_ADCTCTL0_CUTRGEN3_PosÜÚ"PPWM_ADCTCTL0_CUTRGEN3_MskãÚ"PPWM_ADCTCTL0_CPTRGEN3_PosáÚ"PPWM_ADCTCTL0_CPTRGEN3_MskèÚ"PPWM_ADCTCTL0_CDTRGEN3_PosíÚ"PPWM_ADCTCTL0_CDTRGEN3_MskôÚ"PPWM_ADCTCTL0_ZPTRGEN3_PosÊÚ"PPWM_ADCTCTL0_ZPTRGEN3_MskÑÚ"PPWM_ADCTCTL1_CUTRGEN4_PosÚÚ"PPWM_ADCTCTL1_CUTRGEN4_MskáÚ"PPWM_ADCTCTL1_CPTRGEN4_PosßÚ"PPWM_ADCTCTL1_CPTRGEN4_MskæÚ"PPWM_ADCTCTL1_CDTRGEN4_PosëÚ"PPWM_ADCTCTL1_CDTRGEN4_MskòÚ"PPWM_ADCTCTL1_ZPTRGEN4_PosÈÚ"PPWM_ADCTCTL1_ZPTRGEN4_MskÏÚ"PPWM_ADCTCTL1_CUTRGEN5_PosÙÚ"PPWM_ADCTCTL1_CUTRGEN5_MskàÚ"PPWM_ADCTCTL1_CPTRGEN5_PosÞÚ"PPWM_ADCTCTL1_CPTRGEN5_MskåÚ"PPWM_ADCTCTL1_CDTRGEN5_PosêÚ"PPWM_ADCTCTL1_CDTRGEN5_MskñÚ"PPWM_ADCTCTL1_ZPTRGEN5_PosÇÚ"PPWM_ADCTCTL1_ZPTRGEN5_MskÎÚ"PPWM_ADCTCTL1_CUTRGEN6_PosØÚ"PPWM_ADCTCTL1_CUTRGEN6_MskßÚ"PPWM_ADCTCTL1_CPTRGEN6_PosÝÚ"PPWM_ADCTCTL1_CPTRGEN6_MskäÚ"PPWM_ADCTCTL1_CDTRGEN6_PoséÚ"PPWM_ADCTCTL1_CDTRGEN6_MskðÚ"PPWM_ADCTCTL1_ZPTRGEN6_PosÆÚ"PPWM_ADCTCTL1_ZPTRGEN6_MskÍÚ"PPWM_ADCTCTL1_CUTRGEN7_Pos×Ú"PPWM_ADCTCTL1_CUTRGEN7_MskÞÚ"PPWM_ADCTCTL1_CPTRGEN7_PosÜÚ"PPWM_ADCTCTL1_CPTRGEN7_MskãÚ"PPWM_ADCTCTL1_CDTRGEN7_PosèÚ"PPWM_ADCTCTL1_CDTRGEN7_MskïÚ"PPWM_ADCTCTL1_ZPTRGEN7_PosÅÚ"PPWM_ADCTCTL1_ZPTRGEN7_MskÌÚ!PPWM_ADCTSTS0_CUTRGF0_PosÚ!PPWM_ADCTSTS0_CUTRGF0_MskÚ!PPWM_ADCTSTS0_CPTRGF0_PosÚ!PPWM_ADCTSTS0_CPTRGF0_Msk#Ú!PPWM_ADCTSTS0_CDTRGF0_Pos(Ú!PPWM_ADCTSTS0_CDTRGF0_Msk/Ú!PPWM_ADCTSTS0_ZPTRGF0_PosÚ!PPWM_ADCTSTS0_ZPTRGF0_MskÚ!PPWM_ADCTSTS0_CUTRGF1_PosÚ!PPWM_ADCTSTS0_CUTRGF1_MskÚ!PPWM_ADCTSTS0_CPTRGF1_PosÚ!PPWM_ADCTSTS0_CPTRGF1_Msk"Ú!PPWM_ADCTSTS0_CDTRGF1_Pos'Ú!PPWM_ADCTSTS0_CDTRGF1_Msk.Ú!PPWM_ADCTSTS0_ZPTRGF1_PosÚ!PPWM_ADCTSTS0_ZPTRGF1_MskÚ!PPWM_ADCTSTS0_CUTRGF2_PosÚ!PPWM_ADCTSTS0_CUTRGF2_MskÚ!PPWM_ADCTSTS0_CPTRGF2_PosÚ!PPWM_ADCTSTS0_CPTRGF2_Msk!Ú!PPWM_ADCTSTS0_CDTRGF2_Pos&Ú!PPWM_ADCTSTS0_CDTRGF2_Msk-Ú!PPWM_ADCTSTS0_ZPTRGF2_PosÚ!PPWM_ADCTSTS0_ZPTRGF2_Msk


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<unnamed>QÚ 


"–    X_FL_CTL‚Ú "–


X_FL_TRIG4Ú "–X_FL_CONFIG°Ú <"–X_FL_WD˜Ú 


"–X_FL_X_MODEƒÚ "–X_FL_X2_CMD©Ú "–X_FL_X4_CMD§Ú "–X_FL_DP_CMDŸÚ "– X_FL_RDP_CMDKÚ 


"–X_FL_REMAP_ADDRhÚ 


"–X_FL_DP_CTL‰Ú 


"– X_FL_IRQ_CTL/Ú 


"–X_FL_SUS_RESU_CMD‡ÚFLCTL_TËÚ8


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<unnamed>QÚ 


"æX_CACHE_EN¼Ú 


"æX_RESVRvÚ 


"æX_CACHE_INImÚ CR_T±Ú8


<unnamed>QÚ 


"ëCR0ýÚ 


"ëCR1üÚ  


"ëDR.Ú  


"ëSRÚ 


"ëCPSRˆÚ 


"ëIMSC”Ú 


"ëRISÔÚ 


"ëMISÙÚ 


"ëICRäÚ 


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<unnamed>QÚ 


"ÁRBR_THR_DLLmÚ 


"ÁIER_DLHÌÚ 


"ÁIIR_FCRÅÚ 


"ÁLCR


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"ÁMCR    Ú 


"ÁLSRúÚ 


"ÁMSRùÚ 


"ÁSCRÚ 


"ÁLPDLLoÚ 


"ÁLPDLHsÚ <"TÁ


RESERVED0ÍÚ 


"ÁUSRñÚ 


"ÁTFLÚ 


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RESERVED1Ú 


"ÁHTX÷Ú 


"ÁDMASAÚ <"Á


RESERVED2Ú 


"ÁDLFÚ 


"ÁRARÚ 


"ÁTARÚ 


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"ÁRAW_BLOCK_H~Ú 


"ÁRAW_SRCTRAN_LÄÚ 


"ÁRAW_SRCTRAN_HÈÚ 


"ÁRAW_DSTTRAN_LÁÚ 


"ÁRAW_DSTTRAN_HÅÚ 


"Á


RAW_ERR_LÚ 


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RAW_ERR_HÚ 


"Á STATUS_TFR_LýÚ 


"Á STATUS_TFR_HÚ 


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"ÁSTATUS_SRCTRAN_HÈÚ 


"ÁSTATUS_DSTTRAN_LÁÚ 


"ÁSTATUS_DSTTRAN_HÅÚ 


"Á STATUS_ERR_LÚ 


"Á STATUS_ERR_HÚ 


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MSK_TFR_LüÚ 


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"ÁMSK_BLOCK_LyÚ 


"ÁMSK_BLOCK_H}Ú 


"ÁMSK_SRCTRAN_LÃÚ 


"ÁMSK_SRCTRAN_HÇÚ 


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"ÁMSK_DSTTRAN_HÄÚ 


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MSK_ERR_LÿÚ 


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MSK_ERR_HÚ 


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"ÁCLEAR_TFR_H€Ú 


"ÁCLEAR_BLOCK_LùÚ 


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"ÁCLEAR_DSTTRAN_HDÚ 


"ÁCLEAR_ERR_LÚ 


"ÁCLEAR_ERR_HƒÚ 


"Á STATUS_INT_LþÚ 


"Á STATUS_INT_HÚ <"0Á


RESERVED3ìÚ 


"ÁDMA_CFG_REG_LìÚ 


"ÁDMA_CFG_REG_HðÚ 


"ÁCH_EN_REG_LtÚ 


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<unnamed>QÚ 


"ÒCON÷Ú 


"ÒTARðÚ 


"ÒSARñÚ 


"Ò    HS_MADDRkÚ 


"ÒDATACMDáÚ 


"ÒSS_SCL_HCNTTÚ 


"ÒSS_SCL_LCNTPÚ 


"ÒFS_SCL_HCNTaÚ 


"ÒFS_SCL_LCNT]Ú 


"ÒHS_SCL_HCNT_Ú 


"ÒHS_SCL_LCNT[Ú 


"Ò


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"ÒRX_TL*Ú 


"ÒTX_TL(Ú 


"Ò    CLR_INTRPÚ 


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"ÒCLR_RX_OVR‰Ú 


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"ÒCLR_RD_REQ¬Ú 


"ÒCLR_TX_ABRTSÚ 


"ÒCLR_RX_DONEXÚ 


"Ò CLR_ACTIVITYÚ 


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"Ò


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"ÒSTATUSíÚ 


"ÒTXFLRCÚ 


"ÒRXFLREÚ 


"Ò    SDA_HOLDoÚ 


"ÒTX_ABRT_SRCLÚ 


"ÒSLV_DATA_NACKÙÚ 


"ÒDMA_CRÚ 


"Ò    DMA_TDLRfÚ 


"Ò    DMA_RDLRhÚ 


"Ò


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"ÒACK_GENERAL_CALLÚ 


"ÒENABLE_STATUSÙÚ 


"Ò


FS_SPKLENÚ 


"Ò


HS_SPKLENÚ 


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I2C_RX_TLóÚP


I2C_TX_TLñÚP I2C_CLR_INTRÚPI2C_CLR_RX_UNDERÇÚPI2C_CLR_TX_OVER    ÚPI2C_CLR_RD_REQuÚPI2C_CLR_TX_ABORTËÚPI2C_CLR_RX_DONE!ÚPI2C_CLR_ACTIVITYáÚPI2C_CLR_STOP_DETÌÚPI2C_CLR_START_DET‚ÚPI2C_CLR_GEN_CALLùÚPI2C_CLR_RESTART_DETçÚPI2C_CLR_MST_ON_HOLDÒÚPI2C_ENABLE_ENABLEßÚPI2C_ENABLE_ABORTÚPI2C_STATUS_ACTIVITYØÚPI2C_STATUS_TFNFÚPI2C_STATUS_TFEpÚPI2C_STATUS_RFNE"ÚPI2C_STATUS_RFErÚ PI2C_STATUS_MST_ACTIVITY}Ú PI2C_STATUS_SLV_ACTIVITY|ÚP


I2C_TXFLRÚP


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<unnamed>QÚ 


"LP_REG_SYNC“Ú 


"LP_FL_CTRL_3VûÚ 


"LP_SPACING_TIME0@Ú 


"LP_SPACING_TIME1?Ú 


"LP_SPACING_TIME2>Ú 


"


LP_SLPTMR/Ú 


"LP_INT_CTRLŽÚ 


"LP_DLY_CTRL_3V¢Ú 


" LP_PTAT_POLY/Ú 


"


LP_HP_LDO;Ú 


" LP_LP_LDO_3VIÚ 


"LP_ANA_LDOÚ 


"LP_FSYN_LDOÚ 


"LP_SWoÚ 


"LP_BUCK_3VÚ 


"ANA_ADC_LDOÓÚ 


" ANA_RFFE_LDOvÚ 


"ANA_VCO_LDO³Ú 


"ANA_DFTÚ 


"ANA_MISC_3VÅÚ 


"ANA_RESERVED_3V‰Ú 


" ACT_32K_CTRL‹Ú 


"ACT_32K_BASECORRgÚ 


"CPU_ADDR_REMAP_CTRL.Ú 


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"ªEF_CTL(Ú 


"ªEF_ADDRîÚ 


"ªEF_DAT2Ú 


"ªEF_RSV0ÞÚ 


"ªEF_VDD-Ú 


"ªEF_RSV1ÝÚ 


"ªEF_CMD7Ú 


"ªEF_TRGÚ 


"ªEF_PROG_TIMING1iÚ 


"ªEF_PROG_TIMING2hÚ 


"ªEF_PROG_TIMING3gÚ 


"ªEF_READ_TIMING4‚Ú 


"ªEF_READ_TIMING5Ú <"0ªEF_RSV2~Ú 


"ªEF_OP_ERRORyÚ 


"ªEF_VERIFY_DEBUG1+Ú 


"ªEF_VERIFY_DEBUG2*Ú 


"ªEF_VERIFY_DEBUG3)Ú 


"ªEF_VERIFY_DEBUG4(Ú 


"ªEF_FLASH_PERMISSIONÚEFUSE_TÈÚPEFUSE_CTL_EFUSE_EN_Pos‹ÚPEFUSE_CTL_EFUSE_EN_Msk’ÚPEFUSE_CTL_THR_DVDD_Pos†ÚPEFUSE_CTL_THR_DVDD_MskÚ"PEFUSE_CTL_TAEN_RD_CTL_PosÚ"PEFUSE_CTL_TAEN_RD_CTL_Msk—Ú!PEFUSE_CTL_THR_RD_CTL_PosÌÚ!PEFUSE_CTL_THR_RD_CTL_MskÓÚPEFUSE_CTL_TRD_CTL_PosËÚPEFUSE_CTL_TRD_CTL_MskÒÚ!PEFUSE_CTL_TSR_RD_CTL_PosÁÚ!PEFUSE_CTL_TSR_RD_CTL_MskÈÚ#PEFUSE_CTL_TSR_DVDD_CTL_Pos1Ú#PEFUSE_CTL_TSR_DVDD_CTL_Msk8Ú!PEFUSE_CTL_THP_RD_CTL_PosÎÚ!PEFUSE_CTL_THP_RD_CTL_MskÕÚ&PEFUSE_CTL_THP_PG_AVDD_CTL_PosEÚ&PEFUSE_CTL_THP_PG_AVDD_CTL_MskLÚ#PEFUSE_CTL_TAEN_PGM_CTL_Pos@Ú#PEFUSE_CTL_TAEN_PGM_CTL_MskGÚ"PEFUSE_CTL_THP_PGM_CTL_Pos~Ú"PEFUSE_CTL_THP_PGM_CTL_Msk…ÚPEFUSE_CTL_TPGM_CTL_Pos{ÚPEFUSE_CTL_TPGM_CTL_Msk‚Ú"PEFUSE_CTL_TSP_PGM_CTL_PossÚ"PEFUSE_CTL_TSP_PGM_CTL_MskzÚ&PEFUSE_CTL_TSP_PG_AVDD_CTL_Pos:Ú&PEFUSE_CTL_TSP_PG_AVDD_CTL_MskAÚ!PEFUSE_CTL_TSP_RD_CTL_PosÃÚ%PEFUSE_CTL_TSP_TSP_RD_CTL_MsklÚ%PEFUSE_ADDR_EFUSEADDR_ADR_PosèÚ%PEFUSE_ADDR_EFUSEADDR_ADR_MskïÚ#PEFUSE_DAT_EFUSEDAT_DAT_PosnÚ#PEFUSE_DAT_EFUSEDAT_DAT_MskuÚ+P#EFUSE_DAT_EFUSEDAT_DAT_CONFIRM_PosñÚ+P#EFUSE_DAT_EFUSEDAT_DAT_CONFIRM_MskøÚPEFUSE_VDD_DVDD_REG_Pos›ÚPEFUSE_VDD_DVDD_REG_Msk¢ÚPEFUSE_VDD_AVDD_REG_PosžÚPEFUSE_VDD_AVDD_REG_Msk¥Ú#PEFUSE_CMD_EFUSECMD_CMD_Pos}Ú#PEFUSE_CMD_EFUSECMD_CMD_Msk„Ú"PEFUSE_TRG_EFUSETRG_GO_Pos‹Ú"PEFUSE_TRG_EFUSETRG_GO_Msk’Ú*P"EFUSE_PROG_TIMING1_TSP_RD_SET_PosûÚ*P"EFUSE_PROG_TIMING1_TSP_RD_SET_MskÚ/P'EFUSE_PROG_TIMING1_TSP_PG_AVDD_SET_PosrÚ/P'EFUSE_PROG_TIMING1_TSP_PG_AVDD_SET_MskyÚ+P#EFUSE_PROG_TIMING1_TSP_PGM_SET_Pos«Ú+P#EFUSE_PROG_TIMING1_TSP_PGM_SET_Msk²Ú(P EFUSE_PROG_TIMING2_TPGM_SET_Pos²Ú(P EFUSE_PROG_TIMING2_TPGM_SET_Msk¹Ú+P#EFUSE_PROG_TIMING2_THP_PGM_SET_PosµÚ+P#EFUSE_PROG_TIMING2_THP_PGM_SET_Msk¼Ú,P$EFUSE_PROG_TIMING2_TAEN_PGM_SET_PoswÚ,P$EFUSE_PROG_TIMING2_TAEN_PGM_SET_Msk~Ú/P'EFUSE_PROG_TIMING3_THP_PG_AVDD_SET_Pos{Ú/P'EFUSE_PROG_TIMING3_THP_PG_AVDD_SET_Msk‚Ú*P"EFUSE_PROG_TIMING3_THP_RD_SET_PosÚ*P"EFUSE_PROG_TIMING3_THP_RD_SET_MskÚ,P$EFUSE_READ_TIMING4_TSR_DVDD_SET_Pos‚Ú,P$EFUSE_READ_TIMING4_TSR_DVDD_SET_Msk‰Ú*P"EFUSE_READ_TIMING4_TSR_RD_SET_PosÚ*P"EFUSE_READ_TIMING4_TSR_RD_SET_MskÚ'PEFUSE_READ_TIMING4_TRD_SET_PosÚ'PEFUSE_READ_TIMING4_TRD_SET_Msk#Ú*P"EFUSE_READ_TIMING5_THR_RD_SET_PosÚ*P"EFUSE_READ_TIMING5_THR_RD_SET_Msk#Ú+P#EFUSE_READ_TIMING5_TAEN_RD_SET_PosàÚ+P#EFUSE_READ_TIMING5_TAEN_RD_SET_MskçÚ,P$EFUSE_READ_TIMING5_THR_DVDD_SET_PosŒÚ,P$EFUSE_READ_TIMING5_THR_DVDD_SET_Msk“Ú$PEFUSE_OP_ERROR_OP_ERROR_Pos¾Ú$PEFUSE_OP_ERROR_OP_ERROR_MskÅÚ0P(EFUSE_VERIFY_DEBUG1_VERIFY_DBG_KEY1_PospÚ0P(EFUSE_VERIFY_DEBUG1_VERIFY_DBG_KEY1_MskwÚ0P(EFUSE_VERIFY_DEBUG2_VERIFY_DBG_KEY2_PosnÚ0P(EFUSE_VERIFY_DEBUG2_VERIFY_DBG_KEY2_MskuÚ0P(EFUSE_VERIFY_DEBUG3_VERIFY_DBG_KEY3_PoslÚ0P(EFUSE_VERIFY_DEBUG3_VERIFY_DBG_KEY3_MsksÚ0P(EFUSE_VERIFY_DEBUG4_VERIFY_DBG_KEY4_PosjÚ0P(EFUSE_VERIFY_DEBUG4_VERIFY_DBG_KEY4_MskqÚ(P EFUSE_FLASH_PERMISSION_CTRL_Pos»Ú(P EFUSE_FLASH_PERMISSION_CTRL_MskÂÚ8


<unnamed>QÚ "”FADDR²Ú "”POWER†Ú "”INT_IN1ýÚ "”INT_IN2üÚ "”    INT_OUT1šÚ "”    INT_OUT2™Ú "”INT_USBÛÚ "”    INT_IN1E¶Ú "”    INT_IN2EµÚ "”


INT_OUT1ESÚ "”


INT_OUT2ERÚ "”    INT_USBE”Ú "”FRAME1uÚ "”FRAME2tÚ "”INDEX›Ú "”REV*Ú "”MAX_PKT_INßÚ "”CSR0_INCSR1àÚ "”IN_CSR2ÿÚ "”MAX_PKT_OUT|Ú "”    OUT_CSR1Ú "”    OUT_CSR2œÚ "”OUT_COUNT1øÚ "”OUT_COUNT2÷Ú <"”REV0»Ú "”    FIFO_EP0ÅÚ <"”REV1¿Ú "”    FIFO_EP1ÄÚ <"”REV2¾Ú "”    FIFO_EP2ÃÚ <"”REV3½Ú "”    FIFO_EP3ÂÚUSB_TZÚ8


<unnamed>QÚ 


"¶    DMA_INTRvÚ 


"¶CNTL1ˆÚ 


"¶ADDR1žÚ 


"¶COUNT1.Ú    USBDMA_T‚ÚPUSB_DMA_REQUEST_PosqÚPUSB_DMA_REQUEST_MskxÚPUSB_DMA_DIRECTION_PosõÚPUSB_DMA_DIRECTION_MsküÚPUSB_DMA_MODE_SEL_Pos0ÚPUSB_DMA_MODE_SEL_Msk7ÚPUSB_DMA_EP_NUM_Pos¸ÚPUSB_DMA_EP_NUM_Msk¿Ú8


<unnamed>QÚ 


"Ärevs0ìÚ 


"ÄFSM5ÃÚ 


"ÄFSM6ÂÚ 


"ÄFSM13’Ú 


"ÄFSM14‘Ú 


"ÄFSM15Ú 


"ÄFSM16Ú 


"ÄFSM17ŽÚ 


"ÄFSM18Ú 


"ÄFSM19ŒÚ 


"ÄPHY1¼Ú 


"ÄPHY2»Ú 


"ÄPHY3ºÚ 


"ÄPHY4¹Ú 


"ÄPHY5¸Ú <"Ärevs1µÚ 


"ÄINTR1nÚ 


"ÄINTCLRÚ 


"ÄINTMSKÚ 


"ÄINTR4kÚ 


"Ärevs2êÚ 


"ÄACTTMR1ÜÚ 


"ÄACTTMR2ÛÚ 


"ÄACTTMR6×Ú 


"ÄACTTMR7ÖÚ 


"Ärevs3éÚ 


"ÄSECURE1àÚ 


"ÄSECURE2ßÚ 


"ÄSECURE3ÞÚ 


"ÄSECURE4ÝÚ 


"ÄSECURE5ÜÚ 


"ÄSECURE6ÛÚ 


"ÄSECURE7ÚÚ 


"ÄSECURE8ÙÚ 


"ÄSECURE9ØÚ 


"Ä    SECURE10®Ú 


"Ärevs4èÚ 


"ÄTEST_MUX00ÙÚ 


"ÄRNG1ÆÚ 


"ÄRNG2ÅÚ 


"Ärevs5çÚ 


"ÄLL_MAC_CTRLtÚ 


"ÄTEST_MUX01ØÚ 


"ÄTEST_MUX02×Ú 


"ÄTEST_MUX03ÖÚ <"Ärevs6°Ú 


"ÄR00_CTLäÚ 


"ÄR01_INTÛÚ 


"ÄR02_TMR_CTLˆÚ 


"ÄR03_RX_ADDR_LéÚ 


"ÄR04_RX_CTLÑÚ 


"ÄR05_TX_ADDR_LåÚ 


"ÄR06_TX_CTLÍÚ 


"Ä R07_SRAM_CTLAÚ 


"ÄR08_RX_ADDR1_L±Ú 


"ÄR09_RX_ADDR2_L¯Ú 


"ÄR0A_RX_ADDR3_L¦Ú 


"ÄR0B_RX_ADDR4_L¤Ú 


"ÄR0C_RX_ADDR5_L¢Ú 


"ÄR0D_RX_ADDR6_L Ú 


"ÄR0E_RX_ADDR7_LžÚ 


"ÄR0F_RX_ADDR_HÚÚ 


"ÄR10_RX_ADDR_EN¢Ú 


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ECURE7_SEC_MD_LEN_Pos¨ÚPSECURE7_SEC_MD_LEN_Msk¯Ú%PSECURE7_SEC_KEY7_RX_ADDR_PosÈÚ%PSECURE7_SEC_KEY7_RX_ADDR_MskÏÚ'PSECURE7_SEC_PKT_CNT_TX_MSB_PosèÚ'PSECURE7_SEC_PKT_CNT_TX_MSB_MskïÚ'PSECURE8_SEC_PKT_CNT_TX_LSB_PosèÚ'PSECURE8_SEC_PKT_CNT_TX_LSB_MskïÚ'PSECURE9_SEC_PKT_CNT_RX_MSB_PosèÚ'PSECURE9_SEC_PKT_CNT_RX_MSB_MskïÚ(P SECURE10_SEC_PKT_CNT_RX_LSB_Pos¿Ú(P SECURE10_SEC_PKT_CNT_RX_LSB_MskÆÚ)P!TEST_MUX00_TST_MUX_SELECT_03_PosmÚ)P!TEST_MUX00_TST_MUX_SELECT_03_MsktÚ)P!TEST_MUX00_TST_MUX_SELECT_02_PosnÚ)P!TEST_MUX00_TST_MUX_SELECT_02_MskuÚ)P!TEST_MUX00_TST_MUX_SELECT_01_PosoÚ)P!TEST_MUX00_TST_MUX_SELECT_01_MskvÚ)P!TEST_MUX00_TST_MUX_SELECT_00_PospÚ)P!TEST_MUX00_TST_MUX_SELECT_00_MskwÚ$PRNG1_RNG_RING_SCRMB_SEL_PosþÚ$PRNG1_RNG_RING_SCRMB_SEL_MskÚPRNG1_RNG_EN_PosÌÚPRNG1_RNG_EN_MskÓÚPRNG2_RNG_DATA_Pos@ÚPRNG2_RNG_DATA_MskGÚ#PLL_MAC_CTRL_CTRL_LL_EN_Pos-Ú#PLL_MAC_CTRL_CTRL_LL_EN_Msk4Ú)P!TEST_MUX01_TST_MUX_SELECT_07_PoshÚ)P!TEST_MUX01_TST_MUX_SELECT_07_MskoÚ)P!TEST_MUX01_TST_MUX_SELECT_06_PosiÚ)P!TEST_MUX01_TST_MUX_SELECT_06_MskpÚ)P!TEST_MUX01_TST_MUX_SELECT_05_PosjÚ)P!TEST_MUX01_TST_MUX_SELECT_05_MskqÚ)P!TEST_MUX01_TST_MUX_SELECT_04_PoskÚ)P!TEST_MUX01_TST_MUX_SELECT_04_MskrÚ)P!TEST_MUX02_TST_MUX_SELECT_11_PoslÚ)P!TEST_MUX02_TST_MUX_SELECT_11_MsksÚ)P!TEST_MUX02_TST_MUX_SELECT_10_PosmÚ)P!TEST_MUX02_TST_MUX_SELECT_10_MsktÚ)P!TEST_MUX02_TST_MUX_SELECT_09_PoseÚ)P!TEST_MUX02_TST_MUX_SELECT_09_MsklÚ)P!TEST_MUX02_TST_MUX_SELECT_08_PosfÚ)P!TEST_MUX02_TST_MUX_SELECT_08_MskmÚ)P!TEST_MUX03_TST_MUX_SELECT_15_PosgÚ)P!TEST_MUX03_TST_MUX_SELECT_15_MsknÚ)P!TEST_MUX03_TST_MUX_SELECT_14_PoshÚ)P!TEST_MUX03_TST_MUX_SELECT_14_MskoÚ)P!TEST_MUX03_TST_MUX_SELECT_13_PosiÚ)P!TEST_MUX03_TST_MUX_SELECT_13_MskpÚ)P!TEST_MUX03_TST_MUX_SELECT_12_PosjÚ)P!TEST_MUX03_TST_MUX_SELECT_12_MskqÚ#PR00_CTL_TX_PAYLOAD_LEN_Pos`Ú#PR00_CTL_TX_PAYLOAD_LEN_MskgÚ#PR00_CTL_RX_PAYLOAD_LEN_PosbÚ#PR00_CTL_RX_PAYLOAD_LEN_MskiÚ#PR00_CTL_CRC_ACCESS_ADR_Pos”Ú#PR00_CTL_CRC_ACCESS_ADR_Msk›ÚPR00_CTL_CRC24_EN_PosÚPR00_CTL_CRC24_EN_Msk–Ú"PR00_CTL_ADDR_BYTE_LEN_PosÉÚ"PR00_CTL_ADDR_BYTE_LEN_MskÐÚPR00_CTL_DPY_EN_PosäÚPR00_CTL_DPY_EN_MskëÚPR00_CTL_CRC_EN_PosùÚPR00_CTL_CRC_EN_MskÚPR00_CTL_CRC_SEL16_Pos;ÚPR00_CTL_CRC_SEL16_MskBÚPR00_CTL_SCR_EN_PoséÚPR00_CTL_SCR_EN_MskðÚ PR00_CTL_NRF_ENHANCE_Pos‚Ú PR00_CTL_NRF_ENHANCE_Msk‰ÚPR00_CTL_ENHANCE_PosÏÚPR00_CTL_ENHANCE_MskÖÚPR00_CTL_BW_MODE_Pos¤ÚPR00_CTL_BW_MODE_Msk«ÚPR00_CTL_CHIP_MODE_PosÚPR00_CTL_CHIP_MODE_MskÚ&PR00_CTL_RX_ACK_PAYLOAD_EN_PoszÚ&PR00_CTL_RX_ACK_PAYLOAD_EN_MskÚ PR00_CTL_TX_NOACK_EN_PosPÚ PR00_CTL_TX_NOACK_EN_MskWÚPR00_CTL_PRI_RX_PosÏÚPR00_CTL_PRI_RX_MskÖÚPR01_INT_PRI_RX_PID_Pos‚ÚPR01_INT_PRI_RX_PID_Msk‰ÚPR01_INT_PRI_TX_PID_Pos€ÚPR01_INT_PRI_TX_PID_Msk‡Ú"PR01_INT_RX_LENGTH_ERR_Pos™Ú"PR01_INT_RX_LENGTH_ERR_Msk Ú#PR01_INT_RX_ACCADDR_ERR_PoswÚ#PR01_INT_RX_ACCADDR_ERR_Msk~Ú(P R01_INT_RX_ACCADDR_ERR_MASK_PosâÚ(P R01_INT_RX_ACCADDR_ERR_MASK_MskéÚ'PR01_INT_RX_LENGTH_ERR_MASK_PosÚ'PR01_INT_RX_LENGTH_ERR_MASK_MskÚPR01_INT_PRI_ENDIAN_Pos¹ÚPR01_INT_PRI_ENDIAN_MskÀÚ'PR01_INT_PRI_TX_DONE_IRQ_EN_PosêÚ'PR01_INT_PRI_TX_DONE_IRQ_EN_MskñÚ'PR01_INT_PRI_RX_DONE_IRQ_EN_PosìÚ'PR01_INT_PRI_RX_DONE_IRQ_EN_MskóÚ PR01_INT_PRI_RX_GOON_Pos*Ú PR01_INT_PRI_RX_GOON_Msk1ÚPR01_INT_PRI_RST_PosuÚPR01_INT_PRI_RST_Msk|ÚPR01_INT_EXIT_RX_PosuÚPR01_INT_EXIT_RX_Msk|Ú%PR01_INT_TX_DONE_IRQ_FLAG_Pos±Ú%PR01_INT_TX_DONE_IRQ_FLAG_Msk¸Ú%PR01_INT_RX_DONE_IRQ_FLAG_Pos³Ú%PR01_INT_RX_DONE_IRQ_FLAG_MskºÚ(P R01_INT_RX_PID_ERR_IRQ_FLAG_Pos®Ú(P R01_INT_RX_PID_ERR_IRQ_FLAG_MskµÚPR01_INT_RX_CRC_ERR_Pos‰ÚPR01_INT_RX_CRC_ERR_MskÚ#PR01_INT_TX_TIMEOUT_IRQ_Pos-Ú#PR01_INT_TX_TIMEOUT_IRQ_Msk4ÚPR01_INT_TX_IRQ_PosÃÚPR01_INT_TX_IRQ_MskÊÚPR01_INT_RX_IRQ_PosÅÚPR01_INT_RX_IRQ_MskÌÚPR01_INT_IRQ_CLR_EN_Pos”ÚPR01_INT_IRQ_CLR_EN_Msk›Ú$PR01_INT_RX_CRC_ERR_MASK_PosôÚ$PR01_INT_RX_CRC_ERR_MASK_MskûÚ!PR01_INT_PID_ERR_MASK_PosþÚ!PR01_INT_PID_ERR_MASK_MskÚ(P R01_INT_TX_TIMEOUT_IRQ_MASK_Pos˜Ú(P R01_INT_TX_TIMEOUT_IRQ_MASK_MskŸÚ PR01_INT_TX_IRQ_MASK_Pos.Ú PR01_INT_TX_IRQ_MASK_Msk5Ú PR01_INT_RX_IRQ_MASK_Pos0Ú PR01_INT_RX_IRQ_MASK_Msk7Ú%PR01_INT_MULTI_RX_ACC_ADR_Pos¶Ú%PR01_INT_MULTI_RX_ACC_ADR_Msk½Ú%PR02_TMR_CTL_RX_WAIT_TIME_PosÚ%PR02_TMR_CTL_RX_WAIT_TIME_Msk–Ú(P R02_TMR_CTL_RX_WAIT_TIME_EN_Pos—Ú(P R02_TMR_CTL_RX_WAIT_TIME_EN_MskžÚ,P$R02_TMR_CTL_TRX_TRANS_WAIT_TIME_PosFÚ,P$R02_TMR_CTL_TRX_TRANS_WAIT_TIME_MskMÚPR03_RX_ADDR_L_L32B_PosÙÚPR03_RX_ADDR_L_L32B_MskàÚ"PR04_RX_CTL_RX_HEADER1_PosÅÚ"PR04_RX_CTL_RX_HEADER1_MskÌÚ!PR04_RX_CTL_RX_HEADER_PosøÚ!PR04_RX_CTL_RX_HEADER_MskÿÚPR04_RX_CTL_RX_FEC_PosÙÚPR04_RX_CTL_RX_FEC_MskàÚPR04_RX_CTL_TX_FEC_Pos×ÚPR04_RX_CTL_TX_FEC_MskÞÚPR04_RX_CTL_CI_MODE_PosžÚPR04_RX_CTL_CI_MODE_Msk¥Ú!PR04_RX_CTL_NORMAL_M1_PosÚ!PR04_RX_CTL_NORMAL_M1_MskÚ$PR04_RX_CTL_HDR_LEN_NUMB_Pos÷Ú$PR04_RX_CTL_HDR_LEN_NUMB_MskþÚ%PR04_RX_CTL_HDR_LEN_EXIST_PosšÚ%PR04_RX_CTL_HDR_LEN_EXIST_Msk¡ÚPR04_RX_CTL_M8B_PosïÚPR04_RX_CTL_M8B_MsköÚPR05_TX_ADDR_L_L32B_PosÕÚPR05_TX_ADDR_L_L32B_MskÜÚ"PR06_TX_CTL_RX_HEADER1_PosÁÚ"PR06_TX_CTL_RX_HEADER1_MskÈÚ!PR06_TX_CTL_RX_HEADER_PosôÚ!PR06_TX_CTL_RX_HEADER_MskûÚ%PR06_TX_CTL_MAX_LENGTH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CLEAR_BITÚP    READ_BITaÚP


CLEAR_REGÚP


WRITE_REGñÚP    READ_REGbÚPMODIFY_REG²ÚPUSE_FULL_ASSERTûÚP assert_param±ÚP    FREQ_RCLMÚP    FREQ_XTL6ÚNVIC_SystemReset½ÚP__PAN_SYS_LOG_H__ÚPDBG_ONöÚPINFO_ON•ÚPWARN_ON‰ÚPERR_ONÚÚPTEST_ONÚP


ASSERT_ONëÚP


SYS_ABORTãÚPLOGãÚPSYS_DBG’ÚP    SYS_INFO1ÚP    SYS_WARN%ÚP    SYS_TESTÚPSYS_ERRvÚPSYS_ASSERT‡Ú ,file)Ú ,


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SYS_MFP_GPIOäÚPSYS_MFP_P00_GPIOÍÚPSYS_MFP_P00_SWD_CLKÏÚPSYS_MFP_P00_UART1_RX~ÚPSYS_MFP_P00_I2C0_SCLÅÚPSYS_MFP_P00_SPI0_CLKŸÚPSYS_MFP_P00_LL_DBG_14jÚPSYS_MFP_P00_MDM_DBG_11%ÚPSYS_MFP_P00_RESERVED”ÚPSYS_MFP_P00_MskÓÚPSYS_MFP_P01_GPIOÌÚPSYS_MFP_P01_SWD_DATÏÚPSYS_MFP_P01_UART1_TX{ÚPSYS_MFP_P01_I2C0_SDAÎÚPSYS_MFP_P01_SPI0_CSäÚPSYS_MFP_P01_LL_DBG_15hÚPSYS_MFP_P01_MDM_DBG_12#ÚPSYS_MFP_P01_RESERVED“ÚPSYS_MFP_P01_MskÒÚPSYS_MFP_P02_GPIOËÚPSYS_MFP_P02_UART0_CTS;ÚPSYS_MFP_P02_SPI1_MISO<ÚPSYS_MFP_P02_PWM_CH3ãÚPSYS_MFP_P02_UART1_CTS:ÚPSYS_MFP_P02_LL_DBG_8—ÚPSYS_MFP_P02_MDM_DBG_19ÚPSYS_MFP_P02_RESERVED’ÚPSYS_MFP_P02_MskÑÚPSYS_MFP_P03_GPIOÊÚPSYS_MFP_P03_UART0_CTS:ÚPSYS_MFP_P03_SPI0_CSâÚPSYS_MFP_P03_PWM_CH2ãÚ#PSYS_MFP_P03_TIMER0_CNT_OUT™ÚPSYS_MFP_P03_LL_DBG_8–ÚPSYS_MFP_P03_MDM_DBG_5QÚPSYS_MFP_P03_RESERVED‘ÚPSYS_MFP_P03_MskÐÚPSYS_MFP_P04_GPIOÉÚPSYS_MFP_P04_UART0_RTS*ÚPSYS_MFP_P04_SPI0_CLK›ÚPSYS_MFP_P04_PWM_CH3áÚPSYS_MFP_P04_TIMER0_EXTëÚPSYS_MFP_P04_LL_DBG_9”ÚPSYS_MFP_P04_MDM_DBG_6OÚPSYS_MFP_P04_RESERVEDÚPSYS_MFP_P04_MskÏÚPSYS_MFP_P05_GPIOÈÚPSYS_MFP_P05_UART0_TXxÚPSYS_MFP_P05_SPI0_MISO:ÚPSYS_MFP_P05_PWM_CH4ßÚPSYS_MFP_P05_EXT_STADC.ÚPSYS_MFP_P05_LL_DBG_12gÚPSYS_MFP_P05_MDM_DBG_9KÚPSYS_MFP_P05_RESERVEDÚPSYS_MFP_P05_MskÎÚPSYS_MFP_P06_GPIOÇÚPSYS_MFP_P06_UART0_RXyÚPSYS_MFP_P06_SPI0_MISO9ÚPSYS_MFP_P06_PWM_CH5ÝÚPSYS_MFP_P06_TIMER1_EXTèÚPSYS_MFP_P06_LL_DBG_13eÚPSYS_MFP_P06_MDM_DBG_3PÚPSYS_MFP_P06_AHB_CLKìÚPSYS_MFP_P06_MskÍÚPSYS_MFP_P07_GPIOÆÚPSYS_MFP_P07_UART1_RXwÚPSYS_MFP_P07_I2C0_SCL¾ÚPSYS_MFP_P07_SPI0_MOSI8ÚPSYS_MFP_P07_PWM_CH0áÚPSYS_MFP_P07_LL_DBG_10gÚPSYS_MFP_P07_MDM_DBG_7KÚPSYS_MFP_P07_RESERVEDÚPSYS_MFP_P07_MskÌÚPSYS_MFP_P10_GPIOÌÚPSYS_MFP_P10_UART1_TX{ÚPSYS_MFP_P10_I2C0_SDAÎÚPSYS_MFP_P10_SPI0_MISO>ÚPSYS_MFP_P10_PWM_CH5âÚPSYS_MFP_P10_LL_DBG_11lÚPSYS_MFP_P10_MDM_DBG_8PÚPSYS_MFP_P10_RESERVED“ÚPSYS_MFP_P10_MskÒÚPSYS_MFP_P11_GPIOËÚPSYS_MFP_P11_UART1_RTS+ÚPSYS_MFP_P11_SPI0_MOSI=ÚPSYS_MFP_P11_PWM_CH7ßÚPSYS_MFP_P11_CLK_32KÚPSYS_MFP_P11_LL_DBG_9–ÚPSYS_MFP_P11_MDM_DBG_0WÚPSYS_MFP_P11_UART0_TX{ÚPSYS_MFP_P11_MskÑÚPSYS_MFP_P12_GPIOÊÚPSYS_MFP_P12_UART0_RX|ÚPSYS_MFP_P12_PWM_CH4áÚ#PSYS_MFP_P12_TIMER0_CNT_OUT™ÚPSYS_MFP_P12_UART1_TXyÚPSYS_MFP_P12_LL_DBG_4šÚPSYS_MFP_P12_MDM_DBG_17ÚPSYS_MFP_P12_SPI0_MISO<ÚPSYS_MFP_P12_MskÐÚPSYS_MFP_P13_GPIOÉÚPSYS_MFP_P13_UART0_RTS*ÚPSYS_MFP_P13_I2C0_SDAËÚPSYS_MFP_P13_PWM_CH3áÚPSYS_MFP_P13_LL_DBG_3šÚPSYS_MFP_P13_MDM_DBG_16ÚPSYS_MFP_P13_SPI1_CSàÚPSYS_MFP_P13_SPI0_CSáÚPSYS_MFP_P13_MskÏÚPSYS_MFP_P14_GPIOÈÚPSYS_MFP_P14_UART0_CTS8ÚPSYS_MFP_P14_I2C0_SCLÀÚPSYS_MFP_P14_PWM_CH2áÚPSYS_MFP_P14_LL_DEBUG_2üÚPSYS_MFP_P14_MDM_DBG_15ÚPSYS_MFP_P14_SPI0_CLKšÚPSYS_MFP_P14_RESERVEDÚPSYS_MFP_P14_MskÎÚPSYS_MFP_P15_GPIOÇÚPSYS_MFP_P15_SPI0_CSßÚPSYS_MFP_P15_PWM_CH5ÝÚPSYS_MFP_P15_TIMER0_EXTéÚPSYS_MFP_P15_UART0_RXyÚPSYS_MFP_P15_LL_DBG_5–ÚPSYS_MFP_P15_MDM_DBG_18ÚPSYS_MFP_P15_RESERVEDŽÚPSYS_MFP_P15_MskÍÚPSYS_MFP_P16_GPIOÆÚPSYS_MFP_P16_UART0_TXvÚ#PSYS_MFP_P16_TIMER2_CNT_OUT“ÚPSYS_MFP_P16_PWM_CH0áÚPSYS_MFP_P16_LL_DBG_0šÚPSYS_MFP_P16_MDM_DBG_13ÚPSYS_MFP_P16_SPI1_CLK—ÚPSYS_MFP_P16_I2C0_SCL¾ÚPSYS_MFP_P16_MskÌÚPSYS_MFP_P17_GPIOÅÚPSYS_MFP_P17_UART0_RXwÚPSYS_MFP_P17_TIMER2_EXTåÚPSYS_MFP_P17_PWM_CH1ßÚPSYS_MFP_P17_LL_DBG_1˜ÚPSYS_MFP_P17_MDM_DBG_14ÚPSYS_MFP_P17_RCHÚPSYS_MFP_P17_RESERVEDŒÚPSYS_MFP_P17_MskËÚPSYS_MFP_P20_GPIOËÚPSYS_MFP_P20_SPI1_MISO<ÚPSYS_MFP_P20_PWM_CH6àÚPSYS_MFP_P20_TADC_CLKÚPSYS_MFP_P20_LL_DBG_6™ÚPSYS_MFP_P20_MDM_DBG_2UÚPSYS_MFP_P20_XTL_C1_CLKêÚPSYS_MFP_P20_RESERVED’ÚPSYS_MFP_P20_MskÑÚPSYS_MFP_P21_GPIOÊÚPSYS_MFP_P21_SPI1_MOSI;ÚPSYS_MFP_P21_PWM_CH7ÞÚPSYS_MFP_P21_TADC_VLDÚPSYS_MFP_P21_LL_DBG_7—ÚPSYS_MFP_P21_MDM_DBG_1UÚPSYS_MFP_P21_XTL_C2_CLKèÚPSYS_MFP_P21_RESERVED‘ÚPSYS_MFP_P21_MskÐÚPSYS_MFP_P22_GPIOÉÚPSYS_MFP_P22_SPI1_CLKšÚPSYS_MFP_P22_PWM_CH0äÚPSYS_MFP_P22_RESERVEDÚPSYS_MFP_P22_TADC_DATl.ÚPSYS_MFP_P22_MDM_DBG_0UÚPSYS_MFP_P22_SPI0_MOSI;ÚPSYS_MFP_P22_RESERVED1]ÚPSYS_MFP_P22_MskÏÚPSYS_MFP_P23_GPIOÈÚPSYS_MFP_P23_SPI1_CSßÚPSYS_MFP_P23_PWM_CH1âÚPSYS_MFP_P23_DPLL_DIV8GÚPSYS_MFP_P23_TADC_DATHQÚPSYS_MFP_P23_MDM_DBG_10!ÚPSYS_MFP_P23_I2C0_SCLÀÚPSYS_MFP_P23_RESERVEDÚPSYS_MFP_P23_MskÎÚPSYS_MFP_P24_GPIOÇÚPSYS_MFP_P24_SPI1_MISO8ÚPSYS_MFP_P24_UART1_RXxÚPSYS_MFP_P24_PWM_CH2àÚ#PSYS_MFP_P24_TIMER1_CNT_OUT•ÚPSYS_MFP_P24_MDM_DBG_4OÚPSYS_MFP_P24_RESERVEDŽÚPSYS_MFP_P24_RESERVED1[ÚPSYS_MFP_P24_MskÍÚPSYS_MFP_P25_GPIOÆÚPSYS_MFP_P25_SPI1_MOSI7ÚPSYS_MFP_P25_UART1_TXuÚPSYS_MFP_P25_PWM_CH3ÞÚPSYS_MFP_P25_MDM_DBG_5MÚPSYS_MFP_P25_RESERVEDÚPSYS_MFP_P25_I2C0_SDAÈÚPSYS_MFP_P25_RESERVED1ZÚPSYS_MFP_P25_MskÌÚPSYS_MFP_P26_GPIOÅÚPSYS_MFP_P26_UART1_RTS%ÚPSYS_MFP_P26_PWM_CH4ÜÚPSYS_MFP_P26_SPI1_CSÜÚPSYS_MFP_P26_MDM_DBG_4MÚPSYS_MFP_P26_MDM_DBG_10ÚPSYS_MFP_P26_RESERVEDŒÚPSYS_MFP_P26_RESERVED1YÚPSYS_MFP_P26_MskËÚPSYS_MFP_P27_GPIOÄÚPSYS_MFP_P27_UART1_CTS3ÚPSYS_MFP_P27_PWM_CH5ÚÚPSYS_MFP_P27_SPI1_CLK•ÚPSYS_MFP_P27_RESERVED‹ÚPSYS_MFP_P27_MDM_DBG_20ÚPSYS_MFP_P27_XTHÚPSYS_MFP_P27_RESERVED1XÚPSYS_MFP_P27_MskÊÚPSYS_MFP_P30_GPIOÊÚPSYS_MFP_P30_UART1_RX{ÚPSYS_MFP_P30_PWM_CH6ßÚPSYS_MFP_P30_SPI1_MISO;ÚPSYS_MFP_P30_MDM_DBG_10#ÚPSYS_MFP_P30_RESERVED‘ÚPSYS_MFP_P30_RESERVED1^ÚPSYS_MFP_P30_RESERVED2]ÚPSYS_MFP_P30_MskÐÚPSYS_MFP_P31_GPIOÉÚPSYS_MFP_P31_UART1_TXxÚPSYS_MFP_P31_PWM_CH7ÝÚPSYS_MFP_P31_SPI1_MOSI:ÚPSYS_MFP_P31_RESERVEDÚPSYS_MFP_P31_RESERVED1]ÚPSYS_MFP_P31_RESERVED2\ÚPSYS_MFP_P31_RESERVED3[ÚPSYS_MFP_P31_MskÏÚPSYS_SET_MFP)ÚSYS_UnlockRegòÚSYS_LockRegÙÚSYS_IsRegLocked@Ú,


 


u32NopCnt¡ÚSYS_delay_10nopPÚP__PAN_CLK_H__vÚ$PCLK_APB1_WDTSEL_MILLI_PULSEhÚPCLK_APB1_WDTSEL_RCL32K@Ú%PCLK_APB1_WWDTSEL_MILLI_PULSEÚ PCLK_APB1_WWDTSEL_RCL32KçÚ!PCLK_APB1_TMR0SEL_APB1CLK»Ú PCLK_APB1_TMR0SEL_RCL32K


ÚPCLK_APB1_TMR0SEL_TM0ÐÚ!PCLK_APB2_TMR1SEL_APB2CLK¸Ú PCLK_APB2_TMR1SEL_RCL32KÚPCLK_APB2_TMR1SEL_TM1ÍÚ!PCLK_APB2_TMR2SEL_APB2CLK·Ú PCLK_APB2_TMR2SEL_RCL32KÚPCLK_APB2_TMR2SEL_TM2ËÚ"PCLK_APB1_PWM_CH01_SEL_APBIÚ%PCLK_APB1_PWM_CH01_SEL_CLK32KŒÚ"PCLK_APB1_PWM_CH23_SEL_APBEÚ%PCLK_APB1_PWM_CH23_SEL_CLK32KˆÚ"PCLK_APB1_PWM_CH45_SEL_APBAÚ%PCLK_APB1_PWM_CH45_SEL_CLK32K„Ú"PCLK_APB1_PWM_CH67_SEL_APB=Ú%PCLK_APB1_PWM_CH67_SEL_CLK32K€ÚP


FREQ_1MHZÚP


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ÚCLK_GetBODStatusÚCLK_GetBODIntFlagóÚCLK_ClearBODIntFlag(Ú,


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")    BiasDataüÚADC_SetFifoTrigLevelgÚ,"’)ADCx¬Ú,"’)LevelÚADC_SeqModeOneChEn{Ú,"•)ADCx©Ú,""•)    NewState¯Ú ,ADCx‰Ú,buf_enkÚ    ADC_InitÚ ,ADCx‰Ú ADC_PrepareVbgCalibDataPÚ ,ADCx‰Ú,


    adc_code­ÚADC_OutputVoltage<Ú ,ADCx‰Ú,sample_bufŸÚ,


sample_cnt¥Ú,


    trim_cntoÚ!ADC_SamplingCodeTrimMean¾Ú ,ADCx‰Ú"ADC_MeasureSocTemperature


Ú ,ADCx‰Ú&ADC_MeasureSocTemperatureFasttÚ ,ADCx‰ÚADC_MeasureSocVbatÚ ,ADCx‰ÚADC_Disable÷Ú


ADC_Close¹Ú ,ADCx‰Ú,


SourcebÚ,


ParamäÚADC_EnableHWTriggeráÚ ,ADCx‰ÚADC_DisableHWTriggerrÚ ,ADCx‰Ú ,


MaskKÚADC_EnableInt5Ú ,ADCx‰Ú ,


MaskKÚADC_DisableIntÆÚ ,ADCx‰Ú,


SeqTYPEfÚ,


ModeSel(ÚADC_SeqModeEnableªÚ ,ADCx‰Ú,


SeqModeTriSrcÀÚADC_SeqModeTriggerSrcíÚ ,ADCx‰Ú,


ChNumúÚ,


 CmpConditionÚ,


CmpData7Ú,


    MatchCnt½Ú,


 


CmpSelectMÚADC_CompareEnable‘Ú ,ADCx‰Ú ,


TrigAÚ,LeveläÚ,DmaEnÚ,HwClrENeÚADC_SeqOneChModeConfigÄÚP__PAN_FMC_H__zÚPM32ÚPCMD_ERASE_PAGEÚPCMD_ERASE_SECTORÙÚPCMD_ERASE_32KÿÚPCMD_ERASE_64KúÚPCMD_ERASE_CHIP‰ÚPCMD_READ_STATUS_LlÚPCMD_READ_STATUS_HpÚPCMD_WRITE_STATUSªÚPOPS_WR_STU_REG_NORÇÚPOPS_WR_STU_REG_ALLÝÚPCMD_FAST_READÕÚPCMD_NORM_READÇÚP


CMD_DREAD&ÚP


CMD_2READ8ÚP


CMD_QREADÚP


CMD_4READ6ÚPCMD_BURST_READqÚPBURST_READ_MODE_8ƒÚPBURST_READ_MODE_16RÚPBURST_READ_MODE_32TÚPBURST_READ_MODE_64OÚP    CMD_TRIGRÚPCMD_WRITE_ENABLEçÚPCMD_WRITE_DISABLE˜ÚPFLASH_X1_MODE×ÚPFLASH_X2_MODEÖÚPFLASH_X4_MODEÔÚPQUAD_ENABLE_PosëÚPQUAD_ENABLE_MskòÚPWrite_Enable_Latch_PosÚPWrite_Enable_Latch_MskÚPWrite_In_Process_Pos³ÚPWrite_In_Process_MskºÚPLong_Time_Op_Pos~ÚP


PAGE_SIZEÚPSECTOR_SIZEKÚ8_flash_ids¥Ú "ô)manufacturer_id\Ú8


<unnamed>SÚ <"ö)dÚ8


<unnamed>QÚ "ø)memory_type_id­Ú "ø)memory_density_idiÚ <"ô)uid&ÚFLASH_IDS_T‹Ú


flash_idsÚ#FMC_EnterDeepPowerDownModeåÚ,"þ)fmcLÚ"FMC_ExitDeepPowerDownModeKÚ,"€*fmcÉÚ,fmc•ÚFMC_GetFlashUniqueIdYÚ,fmc•ÚFMC_GetFlashJedecId÷Ú,fmc•ÚFMC_SetFlashCapacityCÚ,fmc•Ú!FMC_GetFlashCodeAreaSizeæÚ,fmc•Ú,adršÚFMC_EraseSector5Ú,fmc•Ú ,addr4ÚFMC_EraseBlock32kæÚ,fmc•Ú ,addr4ÚFMC_EraseBlock64káÚ,fmc•ÚFMC_EraseChip%Ú,fmc•Ú ,


addr<Ú,


lenšÚFMC_EraseCodeArea­Ú,fmc•Ú ,


mode2ÚInitIcacheÚ,fmc•Ú ,


addr<Ú,


count¬Ú,chksum:ÚFMC_GetCrc32SumÃÚ,fmc•Ú,adršÚ,szæÚBlankCheckÚ,fmc•Ú,adršÚ,szæÚ,bufŽÚVerifygÚ,fmc•Ú,adršÚ,szæÚ,bufŽÚProgramPage}Ú,fmc•Ú,cmd¬ÚFMC_ReadStatusRegsÚ,fmc•ÚFMC_WriteEnableCÚ,fmc•ÚFMC_WriteDisableÔÚ,fmc•Ú,opsŽÚ,


bufœÚFMC_WriteStatusRegâÚ,fmc•Ú ,


Addr\Ú,cmd¬Ú FMC_ReadByte‹Ú,fmc•Ú ,


addr<Ú ,dataDÚFMC_WriteByteúÚ,fmc•Ú ,


addr<Ú ,data;ÚFMC_WriteHalfWordoÚ,fmc•Ú ,


Addr\Ú,cmd¬Ú FMC_ReadWordƒÚ,fmc•Ú ,


Addr\Ú,cmd¬Ú FMC_ReadPage¢Ú,fmc•Ú ,


Addr\Ú,cmd¬Ú,bufŽÚ,


lenšÚFMC_ReadStream¯Ú,fmc•Ú ,


Addr\Ú,bufŽÚ,


lenšÚFMC_WriteStreamÚ,fmc•Ú ,


Addr\Ú,cmd¬Ú,bufŽÚ,


lenšÚFMC_ReadInfoAreaÚ,fmc•Ú ,


Addr\Ú,bufŽÚ,


lenšÚFMC_WriteInfoAreaÚ,fmc•ÚFMC_EraseInfoAreaœÚ,fmc•Ú ,


mode2Ú,enhanceÚFMC_SetFlashModeôÚ,fmc•ÚFMC_ExitEnhanceMode¼Ú,fmc•Ú ,


mode2ÚFMC_EnterEnhanceModeVÚ,fmc•ÚFMC_EnableAutoDpÿÚ,fmc•ÚFMC_DisableAutoDpÚ,fmc•Ú,


cnt”ÚFMC_SetRdpWaitCountÚ,fmc•Ú,


cnt”ÚFMC_SetDpWaitCountÚ,fmc•Ú ,"IRQnhÚ,"    NewStateÚFMC_SetSuspendIrqWÚ,fmc•Ú,


timeoutÊÚFMC_SetSuspendTimeout”ÚP__PAN_DMAC_H__9ÚPDMAC_CHANNEL_NUMBERÚPDMA_INVLID_CHANNELXÚ"PDMAC_TransferType_Mem2MemoÚ"PDMAC_TransferType_Mem2PergÚ"PDMAC_TransferType_Per2MemgÚ"PDMAC_TransferType_Per2Per_ÚPDMAC_FlowControl_DMA…Ú$PDMAC_FlowControl_Peripheral=ÚPDMAC_BurstLen_1zÚPDMAC_BurstLen_4wÚPDMAC_BurstLen_8sÚPDMAC_BurstLen_16BÚPDMAC_BurstLen_32DÚPDMAC_BurstLen_64?ÚPDMAC_BurstLen_128ÚPDMAC_BurstLen_256


Ú"PDMAC_AddrChange_Increment`Ú"PDMAC_AddrChange_DecrementnÚ!PDMAC_AddrChange_NoChangeÚPDMAC_DataWidth_8&ÚPDMAC_DataWidth_16õÚPDMAC_DataWidth_32÷ÚPDMAC_DataWidth_64òÚPDMAC_DataWidth_128¿ÚPDMAC_DataWidth_256½Ú PDMAC_Peripheral_I2C0_Tx¥Ú PDMAC_Peripheral_I2C0_Rx§Ú PDMAC_Peripheral_SPI0_TxwÚ PDMAC_Peripheral_SPI0_RxyÚ!PDMAC_Peripheral_UART0_Tx%Ú!PDMAC_Peripheral_UART0_Rx'Ú PDMAC_Peripheral_SPI1_TxvÚ PDMAC_Peripheral_SPI1_RxxÚ!PDMAC_Peripheral_UART1_Tx$Ú!PDMAC_Peripheral_UART1_Rx&ÚPDMAC_Peripheral_ADCþÚPDMAC_Peripheral_USB_Rx­ÚPDMAC_Peripheral_USB_Tx«Ú#PDMAC_HandshakePolarity_Low·Ú$PDMAC_HandshakePolarity_HighgÚPDMAC_Handshake_Default€Ú PDMAC_Handshake_SoftwareøÚ PDMAC_Handshake_HardwareÚ$PDMAC_LockLevel_Tfr_Complete}Ú&PDMAC_LockLevel_Block_CompleteºÚ,P$DMAC_LockLevel_Transaction_CompleteÚPDMAC_ChannelPriority_0ÚPDMAC_ChannelPriority_1€ÚPDMAC_ChannelPriority_2ÚPDMAC_ChannelPriority_3~ÚPDMAC_ChannelPriority_4}ÚPDMAC_ChannelPriority_5|ÚPDMAC_ChannelPriority_6{ÚPDMAC_ChannelPriority_7zÚPDMAC_CHANNELALL_MASKÒÚPDMAC_FLAG_INDEX_TFRõÚPDMAC_FLAG_INDEX_BLKÚPDMAC_FLAG_INDEX_SRCTFRÚPDMAC_FLAG_INDEX_DSTTFRÚPDMAC_FLAG_INDEX_ERRøÚPDMAC_FLAG_MASK_TFRCÚPDMAC_FLAG_MASK_BLKVÚPDMAC_FLAG_MASK_SRCTFRUÚPDMAC_FLAG_MASK_DSTTFRRÚPDMAC_FLAG_MASK_ERRFÚPDMAC_FLAG_MASK_ALLVÚ$8__DMAC_ChannelConfigTypeDefÚ 


"Ã+CTL_LCÚ 


"Ã+CTL_HGÚ 


"Ã+CFG_LVÚ 


"Ã+CFG_HZÚ$__DMAC_ChannelConfigTypeDefÙÚ"8DMAC_ChannelConfigTypeDef_Ú 


"É+


IntEnableQÚ 


"É+ DataWidthDstÚ 


"É+ DataWidthSrcÚ 


"É+AddrChangeDstÏÚ 


"É+AddrChangeSrcÒÚ 


"É+BurstLenDsteÚ 


"É+BurstLenSrchÚ 


"É+GatherEnSrc‰Ú 


"É+ ScatterEnDst    Ú 


"É+__Rev0®Ú 


"É+ TransferTypeÖÚ 


"É+FlowControlFÚ 


"É+__Rev1­Ú 


"É+


BlockSize=Ú 


"É+DoneGÚ 


"É+__Rev3«Ú 


"É+__Rev4ªÚ 


"É+ChannelPriorityœÚ 


"É+ChannelSuspendÚ 


"É+


FifoEmpty0Ú 


"É+ HandshakeDstÚ 


"É+ HandshakeSrcÚ 


"É+LockBusÚ 


"É+LockChannel}Ú 


"É+ LockBusLevelÚ 


"É+LockChannelLevel{Ú 


"É+HandshakePolarityDst§Ú 


"É+HandshakePolaritySrcªÚ 


"É+__Rev6¨Ú 


"É+AutoReloadSrc£Ú 


"É+AutoReloadDst Ú 


"É+FlowControlMode¹Ú 


"É+    FifoMode¼Ú 


"É+ProtectControl÷Ú 


"É+__Rev7§Ú 


"É+PeripheralSrc‡Ú 


"É+PeripheralDst„Ú 


"É+__Rev8¦Ú"DMAC_ChannelConfigTypeDef›ÚDMAC_IsChannelValidõÚ,"ñ+dma[Ú,


"ñ+ChIdxÇÚPDMAC_ChannelMaskòÚDMAC_CombinedIntStatus„Ú,"õ+dmaWÚ,


"õ+FlgMskMÚDMAC_StatusFlagdÚ,"ø+dmaTÚ,


"ø+ChIdxÀÚ,


"ø+FlgIdxPÚ DMAC_IntFlagÃÚ,"ü+dmaPÚ,


"ü+ChIdx¼Ú,


"ü+FlgIdxLÚDMAC_IntFlagMsk’Ú,"€,dmaËÚ,


"€,ChIdx7Ú,


"€,FlgIdxÇÚDMAC_ClrIntFlagœÚ,"„,dmaÇÚ,


"„,ChIdx3Ú,


"„,FlgIdxÃÚ,dma™Ú


DMAC_InitÎÚ,dma™ÚDMAC_DeInit!Ú,dma™Ú,


ChIdxÚ,


FlgIdx•ÚDMAC_ClrIntFlagMsk_Ú,dma™Ú,


ChIdxÚ,


FlgIdx•ÚDMAC_SetIntFlagMskTÚ,dma™Ú,


ChIdxÚ,ConfigoÚDMAC_SetChannelConfigÚ,dma™Ú,


ChIdxÚ,ConfigoÚDMAC_GetChannelConfigÚ,dma™Ú,


ChIdxÚ,Src£Ú,Dst Ú,


LenºÚDMAC_StartChannel‹Ú,dma™Ú,


ChIdxÚDMAC_StopChannelõÚ,dma™ÚDMAC_AcquireChannelËÚ,dma™Ú,


ChIdxÚDMAC_ReleaseChannelÔÚ,dma™Ú"DMAC_IsAllChannelReleasedÚP__PAN_GPIO_H__ÚP GPIO_PIN_MAXùÚ8"_GPIO_ModeDef$Ú"®,GPIO_MODE_INPUTAÚ"®,GPIO_MODE_OUTPUTÞÚ"®,GPIO_MODE_OPEN_DRAINÈÚ"®,GPIO_MODE_QUASINÚ GPIO_ModeDefÇÚ8"_GPIO_IntAttrDefÝÚ"´,GPIO_INT_RISING9Ú"´,GPIO_INT_FALLINGÚ"´,GPIO_INT_BOTH_EDGE^Ú"´,GPIO_INT_HIGHéÚ"´, GPIO_INT_LOWÚGPIO_IntAttrDef€Ú8"_GPIO_ClkSrcDefcÚ""»,GPIO_DBCTL_DBCLKSRC_RCLèÚ#"»,GPIO_DBCTL_DBCLKSRC_HCLK¥ÚGPIO_ClkSrcDefÚ8"_GPIO_ClkSelDefgÚ "¿,GPIO_DBCTL_DBCLKSEL_1œÚ "¿,GPIO_DBCTL_DBCLKSEL_2›Ú "¿,GPIO_DBCTL_DBCLKSEL_4™Ú "¿,GPIO_DBCTL_DBCLKSEL_8•Ú!"¿,GPIO_DBCTL_DBCLKSEL_16dÚ!"¿,GPIO_DBCTL_DBCLKSEL_32fÚ!"¿,GPIO_DBCTL_DBCLKSEL_64aÚ""¿,GPIO_DBCTL_DBCLKSEL_128.Ú""¿,GPIO_DBCTL_DBCLKSEL_256,Ú""¿,GPIO_DBCTL_DBCLKSEL_5121Ú#"¿,GPIO_DBCTL_DBCLKSEL_1024Ú#"¿,GPIO_DBCTL_DBCLKSEL_2048ùÚ#"¿,GPIO_DBCTL_DBCLKSEL_4096ôÚ#"¿,GPIO_DBCTL_DBCLKSEL_8192óÚ$"¿,GPIO_DBCTL_DBCLKSEL_16384¿Ú$"¿,GPIO_DBCTL_DBCLKSEL_32768»ÚGPIO_ClkSelDef


ÚPGPIO_PIN_ADDRÂÚPP00ÚPP01ÚPP02ÚPP03ÚPP04ÚPP05ÚPP06ÚPP07ÚPP10ÚPP11ÚPP12ÚPP13ÚPP14ÚPP15ÚPP16ÚPP17 ÚPP20ÚPP21ÚPP22ÚPP23ÚPP24ÚPP25ÚPP26 ÚPP27ÚPP30ÚPP31ÚGPIO_ClrIntFlag‚Ú,"ì,gpioàÚ,


"ì,u32PinMaskÚGPIO_ClrAllIntFlagcÚ,"ï,gpioÝÚGPIO_DisableDebounceeÚ,"ñ,gpioÛÚ,


"ñ,u32PinMaskÿÚGPIO_EnableDebounceÔÚ,"ô,gpioØÚ,


"ô,u32PinMasküÚ GPIO_DisableDigitalPath9Ú,"÷,gpioÕÚ,


"÷,u32PinMaskùÚGPIO_EnableDigitalPath¨Ú,"ú,gpioÒÚ,


"ú,u32PinMasköÚGPIO_DisablePullupPathwÚ,"ý,gpioÏÚ,


"ý,u32PinMaskóÚGPIO_EnablePullupPathæÚ,"€-gpioKÚ,


"€-u32PinMaskoÚ!GPIO_DisablePulldownPath Ú,"ƒ-gpioHÚ,


"ƒ-u32PinMasklÚ GPIO_EnablePulldownPathÚ,"†-gpioEÚ,


"†-u32PinMaskiÚGPIO_DisableDoutMaskbÚ,"‰-gpioBÚ,


"‰-u32PinMaskfÚGPIO_EnableDoutMaskÑÚ,"Œ-gpio?Ú,


"Œ-u32PinMaskcÚGPIO_GetIntFlagƒÚ,"-gpio<Ú,


"-u32PinMask`ÚGPIO_SetDebounceTime^Ú,""’-clksrc[Ú,""’-clksel_ÚGPIO_GetInDataùÚ,"•-gpio6ÚGPIO_SetOutDatajÚ,"—-gpio4Ú,


"—-dataWÚGPIO_GetOutDatavÚ,"š-gpio1ÚGPIO_ToggleîÚ,"œ-gpio/Ú,


"œ-u32PinMaskSÚGPIO_EnableIntØÚ,"Ÿ-gpio,Ú,


"Ÿ-u32PinäÚ,""Ÿ-IntAttribsÁÚGPIO_DisableIntiÚ,"£-gpio(Ú,


"£-u32PinàÚPGPIO_EnableEINT0vÚPGPIO_DisableEINT0ÚPGPIO_EnableEINT1uÚPGPIO_DisableEINT1Ú ,gpioÚ,


PinMaskÚ ,"Mode=Ú GPIO_SetMode‘ÚP__PAN_SPI_H__dÚ8"SPI_Irq:Ú "¯-SPI_IRQ_TX_HALF_EMPTY+Ú"¯-SPI_IRQ_RX_HALF_FULL‹Ú"¯-SPI_IRQ_RX_TIMEOUTÚ"¯-SPI_IRQ_RX_OVERRUNÚ"¯-SPI_IRQ_ALLzÚSPI_IrqDefgÚ8"    SPI_RoleÒÚ"¶-SPI_RoleMaster“Ú"¶-SPI_RoleSlaveÚSPI_RoleDefÿÚ8"SPI_DataFrameSizeRÚ"º-SPI_DataFrame_4b/Ú"º-SPI_DataFrame_5b.Ú"º-SPI_DataFrame_6b-Ú"º-SPI_DataFrame_7b,Ú"º-SPI_DataFrame_8b+Ú"º-SPI_DataFrame_9b*Ú"º-SPI_DataFrame_10bÚ"º-SPI_DataFrame_11bÿÚ"º-SPI_DataFrame_12bþÚ"º-SPI_DataFrame_13býÚ"º-SPI_DataFrame_14büÚ"º-SPI_DataFrame_15bûÚ"º-SPI_DataFrame_16búÚSPI_DataFrameSizeDefÚ8"SPI_BaudRateDiv+Ú"É-SPI_BaudRateDiv_2¼Ú"É-SPI_BaudRateDiv_4ºÚ"É-SPI_BaudRateDiv_6¸Ú"É-SPI_BaudRateDiv_8¶Ú"É-SPI_BaudRateDiv_16…Ú"É-SPI_BaudRateDiv_32‡Ú"É-SPI_BaudRateDiv_48€Ú"É-SPI_BaudRateDiv_64‚Ú"É-SPI_BaudRateDiv_96}Ú"É-SPI_BaudRateDiv_128OÚ"É-SPI_BaudRateDiv_160SÚ"É-SPI_BaudRateDiv_192NÚ"É-SPI_BaudRateDiv_224RÚ"É-SPI_BaudRateDiv_240TÚ"É-SPI_BaudRateDiv_250SÚSPI_BaudRateDivDefXÚPSPI_BAUD_RATE_DIVuÚ8" SPI_ClockPolEÚ"Û-SPI_ClockPolarityLowîÚ "Û-SPI_ClockPolarityHighžÚSPI_ClockPolDefrÚ8"SPI_ClockPhase{Ú""ß-SPI_ClockPhaseFirstEdgeüÚ#"ß-SPI_ClockPhaseSecondEdge¦ÚSPI_ClockPhaseDef¨Ú8"SPI_FrameFormatÚ"ã-SPI_FormatMotorola¦Ú"ã- SPI_FormatTiBÚ"ã-SPI_FormatMicrowire@ÚSPI_FrameFormatDef/Ú8"SPI_WireNum—Ú"è-SPI_WireNumThreeœÚ"è-SPI_WireNumFourúÚSPI_WireNumDefÄÚ8"SPI_CmdDat3Ú"ì-SPI_CommandSelect6Ú"ì-SPI_DataSelectÚSPI_CmdDatDef`Ú8"SPI_WriteReadSel©Ú"ð-SPI_3WireReadÚ"ð-SPI_3WireWrite‚ÚSPI_WriteReadSelDefÖÚ8


<unnamed>QÚ ""ô-    SPI_role†Ú ""ô-SPI_dataFrameSizeÚ ""ô-    SPI_CPOL


Ú ""ô-    SPI_CPHAÚ "ô-SPI_baudRateDivòÚ ""ô-SPI_format«ÚSPI_InitTypeDefSÚSPI_EnableSpiÚ,"ü-SPIxÚ


"ü-tmpregÚSPI_DisableSpi­Ú,"ÿ-SPIxÚ


"ÿ-tmpregÚSPI_IsSpiEnabledöÚ,"‚.SPIx“Ú


"‚.tmpreg–ÚSPI_EnableDmaTxfÚ,"….SPIxÚ


"….tmpreg“ÚSPI_DisableDmaTx÷Ú,"ˆ.SPIxÚ


"ˆ.tmpregÚSPI_IsDmaTxEnabled@Ú,"‹.SPIxŠÚ


"‹.tmpregÚSPI_EnableDmaRxhÚ,"Ž.SPIx‡Ú


"Ž.tmpregŠÚSPI_DisableDmaRxùÚ,"‘.SPIx„Ú


"‘.tmpreg‡ÚSPI_IsDmaRxEnabledBÚ,"”.SPIxÚ


"”.tmpreg„Ú SPI_SendDataÚ,"—.SPIx~Ú,


"—.DatavÚSPI_ReceiveDataNÚ,"š.SPIx{ÚSPI_EnableIrqÚ,"œ.SPIxyÚ,""œ.irqŒÚ


"œ.tmpreg|ÚSPI_DisableIrq­Ú," .SPIxuÚ,"" .irqˆÚ


" .tmpregxÚSPI_IsIrqEnabledöÚ,"¤.SPIxqÚ,""¤.irq„Ú


"¤.tmpregtÚSPI_GetMskedActiveIrqãÚ,"¨.SPIxmÚ


"¨.tmpregpÚSPI_IsIrqActiveGÚ,"«.SPIxjÚ,""«.irq}Ú


"«.tmpregmÚSPI_IsRawIrqActiveÚ,"¯.SPIxfÚ,""¯.irqyÚ


"¯.tmpregiÚ SPI_ClearIrq~Ú,"³.SPIxbÚ,""³.irquÚ


"³.tmpregeÚSPI_GetRawActiveIrq±Ú,"·.SPIx^Ú


"·.tmpregaÚSPI_IsTxFifoEmptylÚ,"º.SPIx[Ú


"º.tmpreg^ÚSPI_IsTxFifoFullêÚ,"½.SPIxXÚ


"½.tmpreg[ÚSPI_IsRxFifoEmptynÚ,"À.SPIxUÚ


"À.tmpregXÚSPI_IsRxFifoFullìÚ,"Ã.SPIxRÚ


"Ã.tmpregUÚSPI_IsBusy6Ú,"Æ.SPIxOÚ


"Æ.tmpregRÚSPI_TxLsbEnableWÚ,"É.SPIxLÚ,"É.enableZÚSPI_RxLsbEnableYÚ,"Ì.SPIxIÚ,"Ì.enableWÚSPI_SetWireNumšÚ,"Ï.SPIxFÚ,""Ï.numUÚSPI_DataCmdLineEnable"Ú,"Ò.SPIxCÚ,""Ò.    NewStatemÚSPI_DataCmdSelCmdDat¢Ú,"Õ.SPIx@Ú,""Õ.cmdDatLÚSPI_WriteReadCtrlkÚ,"Ø.SPIx=Ú ,""Ø.wrµÚ ,SPIxeÚ,SPI_InitStructQÚ    SPI_InitùÚP__PAN_UART_H__Ú8"UART_TxTriggerhÚ"ß.UART_TX_FIFO_EMPTYòÚ!"ß.UART_TX_FIFO_TWO_CHARS¯Ú$"ß.UART_TX_FIFO_QUARTER_FULL½Ú!"ß.UART_TX_FIFO_HALF_FULLÌÚUART_TxTriggerDef•Ú8"UART_RxTriggerjÚ "å.UART_RX_FIFO_ONE_CHARÚ$"å.UART_RX_FIFO_QUARTER_FULL¹Ú!"å.UART_RX_FIFO_HALF_FULLÈÚ*"å. UART_RX_FIFO_TWO_LESS_THAN_FULL·ÚUART_RxTriggerDef—Ú8"UART_LineCtrlíÚ"ë.Uart_Line_5n1òÚ"ë.Uart_Line_5n1_5ZÚ"ë.Uart_Line_5e1ûÚ"ë.Uart_Line_5e1_5cÚ"ë.Uart_Line_5o1ñÚ"ë.Uart_Line_5o1_5YÚ"ë.Uart_Line_5s1íÚ"ë.Uart_Line_5s1_5UÚ"ë.Uart_Line_5m1óÚ"ë.Uart_Line_5m1_5[Ú"ë.Uart_Line_6n1ñÚ"ë.Uart_Line_6n2ðÚ"ë.Uart_Line_6e1úÚ"ë.Uart_Line_6e2ùÚ"ë.Uart_Line_6o1ðÚ"ë.Uart_Line_6o2ïÚ"ë.Uart_Line_6s1ìÚ"ë.Uart_Line_6s2ëÚ"ë.Uart_Line_6m1òÚ"ë.Uart_Line_6m2ñÚ"ë.Uart_Line_7n1ðÚ"ë.Uart_Line_7n2ïÚ"ë.Uart_Line_7e1ùÚ"ë.Uart_Line_7e2øÚ"ë.Uart_Line_7o1ïÚ"ë.Uart_Line_7o2îÚ"ë.Uart_Line_7s1ëÚ"ë.Uart_Line_7s2êÚ"ë.Uart_Line_7m1ñÚ"ë.Uart_Line_7m2ðÚ"ë.Uart_Line_8n1ïÚ"ë.Uart_Line_8n2îÚ"ë.Uart_Line_8e1øÚ"ë.Uart_Line_8e2÷Ú"ë.Uart_Line_8o1îÚ"ë.Uart_Line_8o2íÚ"ë.Uart_Line_8s1êÚ"ë.Uart_Line_8s2éÚ"ë.Uart_Line_8m1ðÚ"ë.Uart_Line_8m2ïÚUART_LineCtrlDefÚ8"    UART_IrqèÚ!"•/UART_IRQ_RECV_DATA_AVLÚ"•/UART_IRQ_THR_EMPTY1Ú"•/UART_IRQ_LINE_STATUSžÚ "•/UART_IRQ_MODEM_STATUSRÚ"•/ UART_IRQ_ALL@ÚUART_IrqDefÚ8"UART_EventÚ"œ/UART_EVENT_MODEMÚ"œ/UART_EVENT_NONEFÚ"œ/UART_EVENT_THR_EMPTYÚ"œ/UART_EVENT_DATA\Ú"œ/UART_EVENT_LINENÚ"œ/UART_EVENT_TIMEOUTIÚUART_EventDef;Ú8"UART_LineStatusúÚ"¤/UART_LINE_DATA_RDYZÚ "¤/UART_LINE_OVERRUN_ERRCÚ"¤/UART_LINE_PARITY_ERRÚ"¤/UART_LINE_FRAME_ERR Ú"¤/UART_LINE_BREAK_INTÚ"¤/UART_LINE_THRE—Ú"¤/UART_LINE_TXSR_EMPTYÚ$"¤/UART_LINE_RECV_FIFO_EMPTYÚ"¤/UART_LINE_ADDR_RCVDÚUART_LineStatusDef'Ú8"UART_ModemStatusŽÚ"¯/UART_MODEM_DCTSEÚ"¯/UART_MODEM_DDSRFÚ"¯/UART_MODEM_TERI?Ú"¯/UART_MODEM_DDCDdÚ"¯/UART_MODEM_CTS‹Ú"¯/UART_MODEM_DSRŒÚ"¯/UART_MODEM_RIÜÚ"¯/UART_MODEM_DCDªÚUART_ModemStatusDef»Ú8


<unnamed>QÚ 


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