Ø R¶X ¼Ù/ #.\configuration\app_config_spark.h ºÝµ 5Ù9 -C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h Ü Íò $Ù, .\configuration\nimble_syscfg.h ºÝµ lÙ. ".\configuration\pan_host_config.h ºÝµ ÙM A..\..\..\..\host\nimble\porting\nimble\include\sysinit/sysinit.h ºÝµ YÙ9 -C:\Keil_v5\ARM\ARMCC\Bin\..\include\assert.h Ú Íò *ÙH <..\..\..\..\host\nimble\porting\nimble\include\os/os_mbuf.h ºÝµ ¼ÙC 7..\..\..\..\host\nimble\porting\nimble\include\os/os.h ºÝµ ÏÙ9 -C:\Keil_v5\ARM\ARMCC\Bin\..\include\assert.h Ú Íò *ÙG ;..\..\..\..\host\nimble\nimble\include\nimble/nimble_npl.h ºÝµ SÙ: .C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdbool.h Ü Íò ÁÙ9 -C:\Keil_v5\ARM\ARMCC\Bin\..\include\stddef.h Ü Íò @ÙX L..\..\..\..\host\nimble\porting\npl\freertos\include\nimble/nimble_npl_os.h ºÝµ øÙ9 -C:\Keil_v5\ARM\ARMCC\Bin\..\include\assert.h Ú Íò *Ù9 -C:\Keil_v5\ARM\ARMCC\Bin\..\include\string.h Ü Íò #Ù7 +..\..\..\..\os\freertos\include\FreeRTOS.h ºÝµ +Ù- !.\configuration\FreeRTOSConfig.h ºÝµ ¯Ù^ R..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\PanSeries.h ºÝµ HÙ8 ,C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h Ü Íò Ù9 -C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdlib.h Ü Íò 8Ù\ P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\core_cm0.h ºÝµ ÿÙa U..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\cmsis_version.h ºÝµ yÙb V..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\cmsis_compiler.h ºÝµ "Ù_ S..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\cmsis_armcc.h ºÝµ }Ùe Y..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\system_PanSeries.h ºÝµ 6Ù` T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_sys_log.h ºÝµ 0Ù\ P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_sys.h ºÝµ ÙÙ\ P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_clk.h ºÝµ þÙ\ P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_adc.h ºÝµ ÞÙ\ P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_fmc.h ºÝµ ÐÙ] Q..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_dmac.h ºÝµ oÙ] Q..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_gpio.h ºÝµ UÙ\ P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_spi.h ºÝµ ºÙ] Q..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_uart.h ºÝµ HÙ\ P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_i2c.h ºÝµ Ù^ R..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_timer.h ºÝµ áÙ\ P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_pwm.h ºÝµ ²Ù\ P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_wdt.h ºÝµ ·Ù] Q..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_wwdt.h ºÝµ >Ù[ O..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_lp.h ºÝµ ^Ù^ R..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_efuse.h ºÝµ Ùf Z..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\radio\prf_lib\include\pan_pri_rf.h ºÝµ ©Ù^ R..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\PanSeries.h ºÝµ HÙ` T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_clktrim.h ºÝµ :Ù^ R..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_power.h ºÝµ Ù\ P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal.h ºÝµ ÑÙa U..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_gpio.h ºÝµ ¹Ù` T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_def.h ºÝµ ;Ùa U..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_uart.h ºÝµ ¬Ùa U..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_dmac.h ºÝµ ÓÙ` T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_spi.h ìƶ ,Ù` T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_i2c.h ºÝµ lÙ` T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_wdt.h ºÝµ Ùa U..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_wwdt.h ºÝµ ¢Ù` T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_pwm.h ºÝµ Ùb V..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_timer.h ºÝµ EÙ` T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_adc.h ºÝµ BÙ7 +..\..\..\..\os\freertos\include\projdefs.h ºÝµ Ù7 +..\..\..\..\os\freertos\include\portable.h ºÝµ ÙE 9..\..\..\..\os\freertos\include\deprecated_definitions.h ºÝµ ÍÙF :..\..\..\..\os\freertos\portable\RVDS\ARM_CM0\portmacro.h ºÝµ Ù; /..\..\..\..\os\freertos\include\mpu_wrappers.h ºÝµ ÈÙ4 (..\..\..\..\os\freertos\include\queue.h ºÝµ ÖÙ3 '..\..\..\..\os\freertos\include\task.h ºÝµ JÙ3 '..\..\..\..\os\freertos\include\list.h ºÝµ AÙ5 )..\..\..\..\os\freertos\include\semphr.h ºÝµ jÙ5 )..\..\..\..\os\freertos\include\timers.h ºÝµ eÙW K..\..\..\..\host\nimble\porting\npl\freertos\include\nimble/npl_freertos.h ºÝµ HÙG ;..\..\..\..\host\nimble\porting\nimble\include\os/endian.h ºÝµ :Ù; /C:\Keil_v5\ARM\ARMCC\Bin\..\include\inttypes.h Ü Íò 6ÙF :..\..\..\..\host\nimble\porting\nimble\include\os/queue.h ºÝµ ÙI =..\..\..\..\host\nimble\porting\nimble\include\os/os_error.h ºÝµ :ÙC 7..\..\..\..\host\nimble\porting\nimble\include\os/os.h ºÝµ ÏÙH <..\..\..\..\host\nimble\porting\nimble\include\os/os_mbuf.h ºÝµ ¼ÙK ?..\..\..\..\host\nimble\porting\nimble\include\os/os_mempool.h ºÝµ gÙP D..\..\..\..\host\nimble\porting\nimble\include\os/panchip_mempool.h ºÝµ \Ù@ 4..\..\..\..\host\nimble\nimble\include\nimble/ble.h ºÝµ NÙG ;..\..\..\..\host\nimble\nimble\include\nimble/hci_common.h ºÝµ WÙP D..\..\..\..\host\nimble\nimble\transport\include\nimble/transport.h ºÝµ +ÙU I..\..\..\..\host\nimble\nimble\transport\include\nimble/transport_impl.h ºÝµ ÙX L..\..\..\..\host\nimble\nimble\transport\include\nimble/transport/monitor.h ºÝµ äÙE 9..\..\..\..\host\nimble\nimble\transport\src\transport.c ºÝµ Ú P SAMPLE_CONFIG_H /Ú P CONFIG_SYSTEM_CLOCK àÚ P CONFIG_PERIPH_DIVIDE ²Ú P CONFIG_SOC_DCDC_PAN1070 0Ú# P CONFIG_FREERTOS_HEAP_PRINT ¯Ú# P CONFIG_VECTOR_REMAP_TO_RAM Ú' P CONFIG_SYSTEM_WATCH_DOG_ENABLE Ú P CONFIG_RAM_FUNCTION ëÚ P CONFIG_RAM_CODE >Ú P CONFIG_LOG_ENABLE ¬Ú P CONFIG_FLASH_LDO_EN òÚ P CONFIG_FLASH_LDO_VOL Ú" P CONFIG_USER_CHIP_MAC_ADDR Ú# P CONFIG_LOW_SPEED_CLOCK_SRC ®Ú% P CONFIG_BT_MAX_NUM_OF_CENTRAL øÚ( P CONFIG_BT_MAX_NUM_OF_PERIPHERAL Ú$ P CONFIG_BT_CTLR_TX_POWER_DFT "Ú# P CONFIG_FORCE_CALIB_RCL_CLK àÚ$ P CONFIG_CNTRL_MEM_POOL_PRINT :Ú P CONFIG_BT_CTLR_AGC_MODE °Ú( P CONFIG_BT_CTLR_LINK_LAYER_DEBUG Ú P CONFIG_RF_CALIB FÚ P
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CONFIG_PM Ú+ P #CONFIG_KEEP_FLASH_POWER_IN_LP_MODE Ú P CONFIG_DEEPSLEEP_MODE_2 ÜÚ. P &CONFIG_SOC_INCREASE_LPLDOH_CALIB_CODE Ú2 P *CONFIG_PM_STANDBY_M1_WAKEUP_WITHOUT_RESET ÕÚ) P !CONFIG_AUTO_OPTIMIZE_POWER_PARAM ±Ú& P CONFIG_TEMP_SAMPLE_INTERVAL_S ¯Ú$ P CONFIG_DVDD_VOL_OPTIMIZE_EN LÚ P CONFIG_HCLK_OPTIMIZE_EN ¤Ú# P CONFIG_SETTINGS_START_ADDR ªÚ# P CONFIG_SETTINGS_SECTOR_NUM Ú P __stdint_h Ú P __ARMCLIB_VERSION lÚ P __INT64_TYPE__ ;Ú P __INT64 ªÚ P __INT64_C_SUFFIX__ Ú P __PASTE2 NÚ P __PASTE Ú P
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__INT64_C Ú P __UINT64_C Ú P __ARMCC_VERSION Ú P __LONGLONG Ú P __STDINT_DECLS QÚ P __CLIBNS BÚ P __cplusplus
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Ú int8_t Ú int16_t nÚ int32_t pÚ int64_t kÚ uint8_t (Ú uint16_t ÷Ú uint32_t ùÚ uint64_t ôÚ int_least8_t Ú int_least16_t êÚ int_least32_t ìÚ int_least64_t çÚ uint_least8_t ¤Ú uint_least16_t sÚ uint_least32_t uÚ uint_least64_t pÚ int_fast8_t Ú int_fast16_t WÚ int_fast32_t YÚ int_fast64_t TÚ uint_fast8_t Ú uint_fast16_t àÚ uint_fast32_t âÚ uint_fast64_t ÝÚ P __sizeof_ptr ®Ú intptr_t }Ú
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uintptr_t Ú intmax_t Ú
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uintmax_t Ú P INT8_MIN UÚ P
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INT16_MIN $Ú P
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INT32_MIN &Ú P
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INT64_MIN !Ú P INT8_MAX SÚ P
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INT16_MAX "Ú P
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INT32_MAX $Ú P
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INT64_MAX Ú P
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UINT8_MAX üÚ P UINT16_MAX ËÚ P UINT32_MAX ÍÚ P UINT64_MAX ÈÚ P INT_LEAST8_MIN qÚ P INT_LEAST16_MIN @Ú P INT_LEAST32_MIN BÚ P INT_LEAST64_MIN =Ú P INT_LEAST8_MAX oÚ P INT_LEAST16_MAX >Ú P INT_LEAST32_MAX @Ú P INT_LEAST64_MAX ;Ú P UINT_LEAST8_MAX Ú P UINT_LEAST16_MAX çÚ P UINT_LEAST32_MAX éÚ P UINT_LEAST64_MAX äÚ P INT_FAST8_MIN ¾Ú P INT_FAST16_MIN Ú P INT_FAST32_MIN Ú P INT_FAST64_MIN Ú P INT_FAST8_MAX ¼Ú P INT_FAST16_MAX Ú P INT_FAST32_MAX Ú P INT_FAST64_MAX Ú P UINT_FAST8_MAX eÚ P UINT_FAST16_MAX 4Ú P UINT_FAST32_MAX 6Ú P UINT_FAST64_MAX 1Ú P INTPTR_MIN Ú P INTPTR_MAX Ú P UINTPTR_MAX :Ú P INTMAX_MIN £Ú P INTMAX_MAX ¡Ú P UINTMAX_MAX JÚ P PTRDIFF_MIN cÚ P PTRDIFF_MAX aÚ P SIG_ATOMIC_MIN mÚ P SIG_ATOMIC_MAX kÚ P SIZE_MAX ;Ú P
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WCHAR_MIN Ú P
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WCHAR_MAX ÿÚ P WINT_MIN 6Ú P WINT_MAX 4Ú P INT8_C úÚ P INT16_C ÉÚ P INT32_C ËÚ P INT64_C ÆÚ P UINT8_C £Ú P UINT16_C rÚ P UINT32_C tÚ P UINT64_C oÚ P INTMAX_C HÚ P
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UINTMAX_C ñÚ P H_MYNEWT_SYSCFG_ Ú P PAN_HOST_CONFIG__H_ ¯Ú P CONIFG_TOTAL_HEAP_SIZE ïÚ& P CONFIG_THRAD_TIMER_STACK_SIZE ºÚ( P CONFIG_THRAD_TIMER_QUEUE_LENGTH Ú* P "CONFIG_THREAD_BLE_HOST_STACK_SIZE ~Ú% P CONFIG_L2CAP_ATT_BLOCK_COUNT 2Ú$ P CONFIG_L2CAP_ATT_BLOCK_SIZE Ú! P CONFIG_ATT_PREFERRED_MTU JÚ% P CONFIG_ATT_SERVER_MAX_NUMBER òÚ+ P #CONFIG_PREFERRED_MAX_CONN_INTERVAL =Ú+ P #CONFIG_PREFERRED_MIN_CONN_INTERVAL ?Ú- P %CONFIG_PREFERRED_SLAVE_CONN_ILATENCY °Ú' P CONFIG_PREFERRED_CONN_SUP_TIME iÚ P CONFIG_BLE_ACL_RX_COUNT Ú P CONFIG_BLE_ACL_RX_SIZE åÚ P CONFIG_BLE_EVT_COUNT
Ú) P !CONFIG_BLE_EVT_DISCARDABLE_COUNT Ú P MYNEWT_VAL Ú P MYNEWT_VAL_CHOICE yÚ+ P #MYNEWT_VAL_TINYCRYPT_SYSINIT_STAGE ÇÚ4 P ,MYNEWT_VAL_TINYCRYPT_UECC_RNG_TRNG_DEV_NAME ýÚ/ P 'MYNEWT_VAL_TINYCRYPT_UECC_RNG_USE_TRNG yÚ! P MYNEWT_VAL_BSP_SIMULATED *Ú3 P +MYNEWT_VAL_HAL_ENABLE_SOFTWARE_BREAKPOINTS ¬Ú. P &MYNEWT_VAL_HAL_FLASH_MAX_DEVICE_COUNT Ú+ P #MYNEWT_VAL_HAL_FLASH_VERIFY_BUF_SZ äÚ+ P #MYNEWT_VAL_HAL_FLASH_VERIFY_ERASES
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Ú+ P #MYNEWT_VAL_HAL_FLASH_VERIFY_WRITES ïÚ P MYNEWT_VAL_HAL_SBRK ºÚ' P MYNEWT_VAL_HAL_SYSTEM_RESET_CB +Ú P MYNEWT_VAL_I2C_0 ÙÚ, P $MYNEWT_VAL_MCU_FLASH_MIN_WRITE_SIZE Ú* P "MYNEWT_VAL_MCU_FLASH_STYLE_NORDIC DÚ& P MYNEWT_VAL_MCU_FLASH_STYLE_ST dÚ P MYNEWT_VAL_MCU_NATIVE Ú* P "MYNEWT_VAL_MCU_NATIVE_USE_SIGNALS =Ú) P !MYNEWT_VAL_MCU_TIMER_POLLER_PRIO {Ú( P MYNEWT_VAL_MCU_UART_POLLER_PRIO ÂÚ P MYNEWT_VAL_FLOAT_USER Ú& P MYNEWT_VAL_MSYS_1_BLOCK_COUNT ~Ú% P MYNEWT_VAL_MSYS_1_BLOCK_SIZE ÎÚ+ P #MYNEWT_VAL_MSYS_1_SANITY_MIN_COUNT ÄÚ& P MYNEWT_VAL_MSYS_2_BLOCK_COUNT }Ú% P MYNEWT_VAL_MSYS_2_BLOCK_SIZE ÍÚ+ P #MYNEWT_VAL_MSYS_2_SANITY_MIN_COUNT ÃÚ' P MYNEWT_VAL_MSYS_SANITY_TIMEOUT Ú P MYNEWT_VAL_OS_ASSERT_CB aÚ P MYNEWT_VAL_OS_CLI KÚ P MYNEWT_VAL_OS_COREDUMP ºÚ" P MYNEWT_VAL_OS_COREDUMP_CB ÐÚ# P MYNEWT_VAL_OS_CPUTIME_FREQ mÚ( P MYNEWT_VAL_OS_CPUTIME_TIMER_NUM ÁÚ& P MYNEWT_VAL_OS_CRASH_FILE_LINE Ú P MYNEWT_VAL_OS_CRASH_LOG eÚ) P !MYNEWT_VAL_OS_CRASH_RESTORE_REGS Ú' P MYNEWT_VAL_OS_CRASH_STACKTRACE TÚ) P !MYNEWT_VAL_OS_CTX_SW_STACK_CHECK {Ú) P !MYNEWT_VAL_OS_CTX_SW_STACK_GUARD fÚ! P MYNEWT_VAL_OS_DEBUG_MODE *Ú# P MYNEWT_VAL_OS_EVENTQ_DEBUG xÚ% P MYNEWT_VAL_OS_EVENTQ_MONITOR ³Ú+ P #MYNEWT_VAL_OS_IDLE_TICKLESS_MS_MAX ÞÚ+ P #MYNEWT_VAL_OS_IDLE_TICKLESS_MS_MIN àÚ& P MYNEWT_VAL_OS_MAIN_STACK_SIZE wÚ% P MYNEWT_VAL_OS_MAIN_TASK_PRIO ½Ú/ P 'MYNEWT_VAL_OS_MAIN_TASK_SANITY_ITVL_MS nÚ$ P MYNEWT_VAL_OS_MEMPOOL_CHECK 9Ú$ P MYNEWT_VAL_OS_MEMPOOL_GUARD $Ú% P MYNEWT_VAL_OS_MEMPOOL_POISON ½Ú! P MYNEWT_VAL_OS_SCHEDULING /Ú$ P MYNEWT_VAL_OS_SYSINIT_STAGE Ú P MYNEWT_VAL_OS_SYSVIEW áÚ, P $MYNEWT_VAL_OS_SYSVIEW_TRACE_CALLOUT Ú+ P #MYNEWT_VAL_OS_SYSVIEW_TRACE_EVENTQ ÇÚ) P !MYNEWT_VAL_OS_SYSVIEW_TRACE_MBUF tÚ, P $MYNEWT_VAL_OS_SYSVIEW_TRACE_MEMPOOL Ú* P "MYNEWT_VAL_OS_SYSVIEW_TRACE_MUTEX Ú( P MYNEWT_VAL_OS_SYSVIEW_TRACE_SEM »Ú, P $MYNEWT_VAL_OS_TASK_RUN_TIME_CPUTIME tÚ$ P MYNEWT_VAL_OS_TICKS_PER_SEC Ú! P MYNEWT_VAL_OS_TIME_DEBUG Ú' P MYNEWT_VAL_OS_WATCHDOG_MONITOR 1Ú# P MYNEWT_VAL_SANITY_INTERVAL vÚ% P MYNEWT_VAL_WATCHDOG_INTERVAL ùÚ& P MYNEWT_VAL_NATIVE_SOCKETS_MAX
Ú* P "MYNEWT_VAL_NATIVE_SOCKETS_MAX_UDP 5Ú3 P +MYNEWT_VAL_NATIVE_SOCKETS_POLL_INTERVAL_MS WÚ, P $MYNEWT_VAL_NATIVE_SOCKETS_POLL_ITVL Ú' P MYNEWT_VAL_NATIVE_SOCKETS_PRIO /Ú+ P #MYNEWT_VAL_NATIVE_SOCKETS_STACK_SZ ßÚ0 P (MYNEWT_VAL_NATIVE_SOCKETS_SYSINIT_STAGE QÚ% P MYNEWT_VAL_CONSOLE_UART_BAUD åÚ$ P MYNEWT_VAL_CONSOLE_UART_DEV $Ú- P %MYNEWT_VAL_CONSOLE_UART_FLOW_CONTROL 9Ú' P MYNEWT_VAL_FLASH_MAP_MAX_AREAS OÚ) P !MYNEWT_VAL_FLASH_MAP_SUPPORT_MFG Ú+ P #MYNEWT_VAL_FLASH_MAP_SYSINIT_STAGE òÚ P MYNEWT_VAL_DFLT_LOG_LVL `Ú P MYNEWT_VAL_DFLT_LOG_MOD nÚ" P MYNEWT_VAL_LOG_GLOBAL_IDX ÞÚ' P MYNEWT_VAL_MODLOG_CONSOLE_DFLT MÚ% P MYNEWT_VAL_MODLOG_LOG_MACROS çÚ' P MYNEWT_VAL_MODLOG_MAX_MAPPINGS EÚ) P !MYNEWT_VAL_MODLOG_MAX_PRINTF_LEN Ú( P MYNEWT_VAL_MODLOG_SYSINIT_STAGE áÚ P MYNEWT_VAL_LOG_CONSOLE ÆÚ P MYNEWT_VAL_LOG_FCB Ú! P MYNEWT_VAL_LOG_FCB_SLOT1 8Ú P MYNEWT_VAL_LOG_LEVEL eÚ' P MYNEWT_VAL_DEBUG_PANIC_ENABLED Ú* P "MYNEWT_VAL_SYSDOWN_CONSTRAIN_DOWN &Ú+ P #MYNEWT_VAL_SYSDOWN_PANIC_FILE_LINE ûÚ) P !MYNEWT_VAL_SYSDOWN_PANIC_MESSAGE ¡Ú& P MYNEWT_VAL_SYSDOWN_TIMEOUT_MS PÚ* P "MYNEWT_VAL_SYSINIT_CONSTRAIN_INIT .Ú+ P #MYNEWT_VAL_SYSINIT_PANIC_FILE_LINE ÿÚ) P !MYNEWT_VAL_SYSINIT_PANIC_MESSAGE ¥Ú P MYNEWT_VAL_RWLOCK_DEBUG Ú P MYNEWT_VAL_BLE_EXT_ADV ½Ú( P MYNEWT_VAL_BLE_EXT_ADV_MAX_SIZE ÌÚ P MYNEWT_VAL_BLE_HCI_VS Ú) P !MYNEWT_VAL_BLE_HCI_VS_OCF_OFFSET Ú P MYNEWT_VAL_BLE_ISO Ú P MYNEWT_VAL_BLE_ISO_TEST \Ú' P MYNEWT_VAL_BLE_MAX_CONNECTIONS PÚ* P "MYNEWT_VAL_BLE_MAX_PERIODIC_SYNCS OÚ+ P #MYNEWT_VAL_BLE_MULTI_ADV_INSTANCES Ú$ P MYNEWT_VAL_BLE_PERIODIC_ADV UÚ2 P *MYNEWT_VAL_BLE_PERIODIC_ADV_SYNC_TRANSFER ÙÚ( P MYNEWT_VAL_BLE_ROLE_BROADCASTER Ú$ P MYNEWT_VAL_BLE_ROLE_CENTRAL DÚ% P MYNEWT_VAL_BLE_ROLE_OBSERVER ãÚ' P MYNEWT_VAL_BLE_ROLE_PERIPHERAL [Ú P MYNEWT_VAL_BLE_VERSION ÂÚ! P MYNEWT_VAL_BLE_WHITELIST 'Ú% P MYNEWT_VAL_BLE_POWER_CONTROL ÏÚ) P !MYNEWT_VAL_BLE_ATT_PREFERRED_MTU Ú) P !MYNEWT_VAL_BLE_ATT_SVR_FIND_INFO Ú) P !MYNEWT_VAL_BLE_ATT_SVR_FIND_TYPE pÚ( P MYNEWT_VAL_BLE_ATT_SVR_INDICATE óÚ0 P (MYNEWT_VAL_BLE_ATT_SVR_MAX_PREP_ENTRIES /Ú& P MYNEWT_VAL_BLE_ATT_SVR_NOTIFY _Ú, P $MYNEWT_VAL_BLE_ATT_SVR_QUEUED_WRITE yÚ0 P (MYNEWT_VAL_BLE_ATT_SVR_QUEUED_WRITE_TMO "Ú$ P MYNEWT_VAL_BLE_ATT_SVR_READ Ú) P !MYNEWT_VAL_BLE_ATT_SVR_READ_BLOB Ú/ P 'MYNEWT_VAL_BLE_ATT_SVR_READ_GROUP_TYPE }Ú) P !MYNEWT_VAL_BLE_ATT_SVR_READ_MULT uÚ) P !MYNEWT_VAL_BLE_ATT_SVR_READ_TYPE uÚ, P $MYNEWT_VAL_BLE_ATT_SVR_SIGNED_WRITE Ú% P MYNEWT_VAL_BLE_ATT_SVR_WRITE ¯Ú, P $MYNEWT_VAL_BLE_ATT_SVR_WRITE_NO_RSP QÚ9 P 1MYNEWT_VAL_BLE_GAP_MAX_PENDING_CONN_PARAM_UPDATE ´Ú* P "MYNEWT_VAL_BLE_GATT_DISC_ALL_CHRS YÚ* P "MYNEWT_VAL_BLE_GATT_DISC_ALL_DSCS \Ú* P "MYNEWT_VAL_BLE_GATT_DISC_ALL_SVCS JÚ* P "MYNEWT_VAL_BLE_GATT_DISC_CHR_UUID NÚ* P "MYNEWT_VAL_BLE_GATT_DISC_SVC_UUID ?Ú* P "MYNEWT_VAL_BLE_GATT_FIND_INC_SVCS KÚ% P MYNEWT_VAL_BLE_GATT_INDICATE Ú& P MYNEWT_VAL_BLE_GATT_MAX_PROCS Ú# P MYNEWT_VAL_BLE_GATT_NOTIFY xÚ! P MYNEWT_VAL_BLE_GATT_READ 9Ú& P MYNEWT_VAL_BLE_GATT_READ_LONG Ú+ P #MYNEWT_VAL_BLE_GATT_READ_MAX_ATTRS óÚ& P MYNEWT_VAL_BLE_GATT_READ_MULT Ú& P MYNEWT_VAL_BLE_GATT_READ_UUID Ú( P MYNEWT_VAL_BLE_GATT_RESUME_RATE ëÚ) P !MYNEWT_VAL_BLE_GATT_SIGNED_WRITE ¡Ú" P MYNEWT_VAL_BLE_GATT_WRITE ÈÚ' P MYNEWT_VAL_BLE_GATT_WRITE_LONG /Ú, P $MYNEWT_VAL_BLE_GATT_WRITE_MAX_ATTRS Ú) P !MYNEWT_VAL_BLE_GATT_WRITE_NO_RSP jÚ+ P #MYNEWT_VAL_BLE_GATT_WRITE_RELIABLE Ú P MYNEWT_VAL_BLE_HOST °Ú* P "PKG_NIMBLE_HOST_THREAD_STACK_SIZE lÚ. P &MYNEWT_VAL_BLE_HOST_THREAD_STACK_SIZE Ú( P PKG_NIMBLE_HOST_THREAD_PRIORITY þÚ, P $MYNEWT_VAL_BLE_HOST_THREAD_PRIORITY Ú% P MYNEWT_VAL_BLE_HS_AUTO_START ¼Ú P MYNEWT_VAL_BLE_HS_DEBUG
Ú$ P MYNEWT_VAL_BLE_HS_FLOW_CTRL Ú) P !MYNEWT_VAL_BLE_HS_FLOW_CTRL_ITVL pÚ+ P #MYNEWT_VAL_BLE_HS_FLOW_CTRL_THRESH ÝÚ5 P -MYNEWT_VAL_BLE_HS_FLOW_CTRL_TX_ON_DISCONNECT ¦Ú" P MYNEWT_VAL_BLE_HS_LOG_LVL ¹Ú" P MYNEWT_VAL_BLE_HS_LOG_MOD ÇÚ) P !MYNEWT_VAL_BLE_HS_PHONY_HCI_ACKS Ú% P MYNEWT_VAL_BLE_HS_REQUIRE_OS ÄÚ+ P #MYNEWT_VAL_BLE_HS_STOP_ON_SHUTDOWN ¹Ú3 P +MYNEWT_VAL_BLE_HS_STOP_ON_SHUTDOWN_TIMEOUT #Ú( P MYNEWT_VAL_BLE_HS_SYSINIT_STAGE ÖÚ) P !MYNEWT_VAL_BLE_L2CAP_COC_MAX_NUM ºÚ% P MYNEWT_VAL_BLE_L2CAP_COC_MPS Ú* P "MYNEWT_VAL_BLE_L2CAP_ENHANCED_COC ·Ú+ P #MYNEWT_VAL_BLE_L2CAP_JOIN_RX_FRAGS Ú' P MYNEWT_VAL_BLE_L2CAP_MAX_CHANS uÚ- P %MYNEWT_VAL_BLE_L2CAP_RX_FRAG_TIMEOUT lÚ+ P #MYNEWT_VAL_BLE_L2CAP_SIG_MAX_PROCS Ú P MYNEWT_VAL_BLE_MESH ÁÚ3 P +MYNEWT_VAL_BLE_MONITOR_CONSOLE_BUFFER_SIZE sÚ# P MYNEWT_VAL_BLE_MONITOR_RTT _Ú, P $MYNEWT_VAL_BLE_MONITOR_RTT_BUFFERED «Ú/ P 'MYNEWT_VAL_BLE_MONITOR_RTT_BUFFER_NAME ®Ú/ P 'MYNEWT_VAL_BLE_MONITOR_RTT_BUFFER_SIZE Ú$ P MYNEWT_VAL_BLE_MONITOR_UART Ú- P %MYNEWT_VAL_BLE_MONITOR_UART_BAUDRATE bÚ0 P (MYNEWT_VAL_BLE_MONITOR_UART_BUFFER_SIZE PÚ( P MYNEWT_VAL_BLE_MONITOR_UART_DEV ÕÚ# P MYNEWT_VAL_BLE_RPA_TIMEOUT wÚ" P MYNEWT_VAL_BLE_SM_BONDING âÚ! P MYNEWT_VAL_BLE_SM_IO_CAP Ú# P MYNEWT_VAL_BLE_SM_KEYPRESS kÚ! P MYNEWT_VAL_BLE_SM_LEGACY 0Ú$ P MYNEWT_VAL_BLE_SM_MAX_PROCS Ú P MYNEWT_VAL_BLE_SM_MITM ²Ú( P MYNEWT_VAL_BLE_SM_OOB_DATA_FLAG Ú' P MYNEWT_VAL_BLE_SM_OUR_KEY_DIST Ú P MYNEWT_VAL_BLE_SM_SC WÚ( P MYNEWT_VAL_BLE_SM_SC_DEBUG_KEYS àÚ! P MYNEWT_VAL_BLE_SM_SC_LVL Ú" P MYNEWT_VAL_BLE_SM_SC_ONLY ¬Ú) P !MYNEWT_VAL_BLE_SM_THEIR_KEY_DIST ~Ú, P $MYNEWT_VAL_BLE_STORE_CONFIG_PERSIST £Ú' P MYNEWT_VAL_BLE_STORE_MAX_BONDS 1Ú' P MYNEWT_VAL_BLE_STORE_MAX_CCCDS GÚ- P %MYNEWT_VAL_BLE_SVC_ANS_NEW_ALERT_CAT HÚ- P %MYNEWT_VAL_BLE_SVC_ANS_SYSINIT_STAGE :Ú- P %MYNEWT_VAL_BLE_SVC_ANS_UNR_ALERT_CAT =Ú; P 3MYNEWT_VAL_BLE_SVC_BAS_BATTERY_LEVEL_NOTIFY_ENABLE Ú7 P /MYNEWT_VAL_BLE_SVC_BAS_BATTERY_LEVEL_READ_PERM 8Ú- P %MYNEWT_VAL_BLE_SVC_BAS_SYSINIT_STAGE FÚ1 P )MYNEWT_VAL_BLE_SVC_DIS_DEFAULT_READ_PERM 'Ú9 P 1MYNEWT_VAL_BLE_SVC_DIS_FIRMWARE_REVISION_DEFAULT Ú; P 3MYNEWT_VAL_BLE_SVC_DIS_FIRMWARE_REVISION_READ_PERM íÚ9 P 1MYNEWT_VAL_BLE_SVC_DIS_HARDWARE_REVISION_DEFAULT ªÚ; P 3MYNEWT_VAL_BLE_SVC_DIS_HARDWARE_REVISION_READ_PERM üÚ9 P 1MYNEWT_VAL_BLE_SVC_DIS_MANUFACTURER_NAME_DEFAULT ¹Ú; P 3MYNEWT_VAL_BLE_SVC_DIS_MANUFACTURER_NAME_READ_PERM Ú4 P ,MYNEWT_VAL_BLE_SVC_DIS_MODEL_NUMBER_DEFAULT 7Ú6 P .MYNEWT_VAL_BLE_SVC_DIS_MODEL_NUMBER_READ_PERM Ú5 P -MYNEWT_VAL_BLE_SVC_DIS_SERIAL_NUMBER_DEFAULT æÚ7 P /MYNEWT_VAL_BLE_SVC_DIS_SERIAL_NUMBER_READ_PERM 8Ú9 P 1MYNEWT_VAL_BLE_SVC_DIS_SOFTWARE_REVISION_DEFAULT Ú; P 3MYNEWT_VAL_BLE_SVC_DIS_SOFTWARE_REVISION_READ_PERM ßÚ- P %MYNEWT_VAL_BLE_SVC_DIS_SYSINIT_STAGE <Ú1 P )MYNEWT_VAL_BLE_SVC_DIS_SYSTEM_ID_DEFAULT Ú3 P +MYNEWT_VAL_BLE_SVC_DIS_SYSTEM_ID_READ_PERM WÚ* P "MYNEWT_VAL_BLE_SVC_GAP_APPEARANCE Ú5 P -MYNEWT_VAL_BLE_SVC_GAP_APPEARANCE_WRITE_PERM íÚ: P 2MYNEWT_VAL_BLE_SVC_GAP_CENTRAL_ADDRESS_RESOLUTION OÚ+ P #MYNEWT_VAL_BLE_SVC_GAP_DEVICE_NAME Ú6 P .MYNEWT_VAL_BLE_SVC_GAP_DEVICE_NAME_MAX_LENGTH ¢Ú6 P .MYNEWT_VAL_BLE_SVC_GAP_DEVICE_NAME_WRITE_PERM Ú6 P .MYNEWT_VAL_BLE_SVC_GAP_PPCP_MAX_CONN_INTERVAL oÚ6 P .MYNEWT_VAL_BLE_SVC_GAP_PPCP_MIN_CONN_INTERVAL qÚ2 P *MYNEWT_VAL_BLE_SVC_GAP_PPCP_SLAVE_LATENCY ÄÚ4 P ,MYNEWT_VAL_BLE_SVC_GAP_PPCP_SUPERVISION_TMO ôÚ- P %MYNEWT_VAL_BLE_SVC_GAP_SYSINIT_STAGE DÚ. P &MYNEWT_VAL_BLE_SVC_GATT_SYSINIT_STAGE êÚ- P %MYNEWT_VAL_BLE_SVC_IAS_SYSINIT_STAGE ?Ú. P &MYNEWT_VAL_BLE_SVC_IPSS_SYSINIT_STAGE ÛÚ- P %MYNEWT_VAL_BLE_SVC_LLS_SYSINIT_STAGE 1Ú- P %MYNEWT_VAL_BLE_SVC_TPS_SYSINIT_STAGE %Ú% P MYNEWT_VAL_BLE_ACL_BUF_COUNT æÚ$ P MYNEWT_VAL_BLE_ACL_BUF_SIZE 6Ú" P MYNEWT_VAL_BLE_HCI_BRIDGE Ú( P MYNEWT_VAL_BLE_HCI_EVT_BUF_SIZE ÜÚ, P $MYNEWT_VAL_BLE_HCI_EVT_HI_BUF_COUNT Ú, P $MYNEWT_VAL_BLE_HCI_EVT_LO_BUF_COUNT Ú% P MYNEWT_VAL_BLE_HCI_TRANSPORT ÚÚ! P MYNEWT_VAL_BLE_TRANSPORT Ú+ P #MYNEWT_VAL_BLE_TRANSPORT_ACL_COUNT ìÚ3 P +MYNEWT_VAL_BLE_TRANSPORT_ACL_FROM_HS_COUNT OÚ3 P +MYNEWT_VAL_BLE_TRANSPORT_ACL_FROM_LL_COUNT RÚ* P "MYNEWT_VAL_BLE_TRANSPORT_ACL_SIZE <Ú+ P #MYNEWT_VAL_BLE_TRANSPORT_EVT_COUNT ÍÚ7 P /MYNEWT_VAL_BLE_TRANSPORT_EVT_DISCARDABLE_COUNT HÚ* P "MYNEWT_VAL_BLE_TRANSPORT_EVT_SIZE Ú, P $MYNEWT_VAL_BLE_TRANSPORT_HS__custom ®Ú1 P )MYNEWT_VAL_BLE_TRANSPORT_HS__dialog_cmac ÜÚ, P $MYNEWT_VAL_BLE_TRANSPORT_HS__native ÂÚ- P %MYNEWT_VAL_BLE_TRANSPORT_HS__nrf5340 5Ú* P "MYNEWT_VAL_BLE_TRANSPORT_HS__uart Ú) P !MYNEWT_VAL_BLE_TRANSPORT_HS__usb Ú$ P MYNEWT_VAL_BLE_TRANSPORT_HS Ú, P $MYNEWT_VAL_BLE_TRANSPORT_LL__custom ±Ú1 P )MYNEWT_VAL_BLE_TRANSPORT_LL__dialog_cmac ßÚ, P $MYNEWT_VAL_BLE_TRANSPORT_LL__native ÅÚ- P %MYNEWT_VAL_BLE_TRANSPORT_LL__nrf5340 8Ú, P $MYNEWT_VAL_BLE_TRANSPORT_LL__socket ÃÚ$ P MYNEWT_VAL_BLE_TRANSPORT_LL Ú. P &MYNEWT_VAL_BLE_SOCK_CLI_SYSINIT_STAGE þÚ& P MYNEWT_VAL_BLE_SOCK_LINUX_DEV }Ú' P MYNEWT_VAL_BLE_SOCK_STACK_SIZE 9Ú& P MYNEWT_VAL_BLE_SOCK_TASK_PRIO Ú% P MYNEWT_VAL_BLE_SOCK_TCP_PORT ÂÚ+ P #MYNEWT_VAL_BLE_SOCK_USE_LINUX_BLUE ÞÚ& P MYNEWT_VAL_BLE_SOCK_USE_NUTTX \Ú$ P MYNEWT_VAL_BLE_SOCK_USE_TCP Ú P MYNEWT_VAL_APP_NAME ¿Ú! P MYNEWT_VAL_APP_dummy_app
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Ú P MYNEWT_VAL_ARCH_NAME Ú P MYNEWT_VAL_ARCH_sim ZÚ P MYNEWT_VAL_BSP_NAME »Ú P MYNEWT_VAL_BSP_native QÚ' P MYNEWT_VAL_NEWT_FEATURE_LOGCFG PÚ( P MYNEWT_VAL_NEWT_FEATURE_SYSDOWN ÉÚ P MYNEWT_VAL_TARGET_NAME ÓÚ* P "MYNEWT_VAL_TARGET_porting_default Ú' P MYNEWT_VAL_HOST_PRIVACY_ENABLE IÚ P __SYSINIT_H__ [Ú P __assert_h Ú P _ARMABI_NORETURN ÄÚ P __ARM_PROMISE Ú abort ÆÚ __aeabi_assert +Ú P NDEBUG Ú P __OPT_SMALL_ASSERT ëÚ P
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TMR1_IRQn èÚ " ÿ
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TMR2_IRQn çÚ " ÿ GPIO0_IRQn «Ú " ÿ GPIO1_IRQn ªÚ " ÿ GPIO2_IRQn ©Ú " ÿ GPIO3_IRQn ¨Ú " ÿ USBDMA_IRQn LÚ " ÿ USB_IRQn $Ú " ÿ
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TRIM_IRQn ÐÚ " ÿ DMA_IRQn <Ú " ÿ BOD_IRQn 9Ú " ÿ SLPTMR_IRQn &Ú " ÿLP_IRQn tÚ
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IRQn_Type Ú P
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__CM0_REV ïÚ P __MPU_PRESENT Ú P __NVIC_PRIO_BITS Ú P __Vendor_SysTickConfig ôÚ P __FPU_PRESENT Ú P __CORE_CM0_H_GENERIC Ú P __CMSIS_VERSION_H @Ú P __CM_CMSIS_VERSION_MAIN hÚ P __CM_CMSIS_VERSION_SUB ¥Ú P __CM_CMSIS_VERSION öÚ! P __CM0_CMSIS_VERSION_MAIN 6Ú P __CM0_CMSIS_VERSION_SUB sÚ P __CM0_CMSIS_VERSION ÄÚ P __CORTEX_M xÚ P __FPU_USED ~Ú P __CC_ARM 6Ú P __CMSIS_COMPILER_H Ú P __CMSIS_ARMCC_H Ú P __TARGET_ARCH_6S_M Ú P __ARM_ARCH_6M__ òÚ P __ASM "Ú P __INLINE >Ú P __STATIC_INLINE Ú P __STATIC_FORCEINLINE Ú P __NO_RETURN Ú P __USED ÐÚ P __WEAK ÙÚ P __PACKED UÚ P __PACKED_STRUCT Ú P __PACKED_UNION aÚ P __UNALIGNED_UINT32 NÚ! P __UNALIGNED_UINT16_WRITE VÚ P __UNALIGNED_UINT16_READ ÇÚ! P __UNALIGNED_UINT32_WRITE XÚ P __UNALIGNED_UINT32_READ ÉÚ P
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__ALIGNED Ú P __RESTRICT Ú P __COMPILER_BARRIER (Ú P __PROGRAM_START êÚ P __INITIAL_SP éÚ P __STACK_LIMIT Ú P __VECTOR_TABLE WÚ! P __VECTOR_TABLE_ATTRIBUTE 0Ú __get_CONTROL \Ú
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" É __regControl Ú __set_CONTROL PÚ ,
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" Ëcontrol ÝÚ
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" Ë __regControl Ú __get_IPSR EÚ
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" Î
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__regIPSR ½Ú __get_APSR MÚ
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" Ð
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__regAPSR ÃÚ __get_xPSR Ú
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" Ò
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__regXPSR ªÚ
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__get_PSP Ú#
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" Ô__regProcessStackPointer !Ú
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__set_PSP Ú ,
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" ÖtopOfProcStack 3Ú#
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" Ö__regProcessStackPointer Ú
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__get_MSP Ú
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" Ù__regMainStackPointer |Ú
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__set_MSP Ú ,
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" ÛtopOfMainStack =Ú
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" Û__regMainStackPointer zÚ __get_PRIMASK fÚ
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" Þ __regPriMask .Ú __set_PRIMASK ZÚ ,
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" àpriMask òÚ
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" à __regPriMask ,Ú __get_FPSCR Ú __set_FPSCR ÷Ú ,
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" äfpscr «Ú P __NOP Ú P __WFI Ú P __WFE !Ú P __SEV Ú P __ISB %Ú P __DSB *Ú P __DMB 0Ú P __REV Ú P __NO_EMBEDDED_ASM Ú __REV16 ÔÚ ,
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" ïvalue ¡Ú __REVSH Ú , " ñvalue Ú P __ROR Ú P __BKPT ÐÚ __RBIT ùÚ ,
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" õvalue Ú
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" õresult ;Ú
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" õs qÚ P __CLZ Ú __SSAT ïÚ ," úval vÚ ,
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" úsat oÚ " úmax Ú " úmin Ú __USAT íÚ ," ÿval qÚ ,
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" ÿsat jÚ
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" ÿmax Ú P __CMSIS_GENERIC Ú P __CORE_CM0_H_DEPENDANT Ú P __I ¾Ú P __O ¸Ú P __IO mÚ P __IM oÚ P __OM iÚ P __IOM Ú 8
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<unnamed> SÚ 8
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<unnamed> QÚ
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" _reserved0 3Ú
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" V ÞÚ
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" C ñÚ
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" Z ÚÚ
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" N æÚ " b ÁÚ
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" w ¾Ú
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APSR_Type ¸Ú P APSR_N_Pos CÚ P APSR_N_Msk JÚ P APSR_Z_Pos 7Ú P APSR_Z_Msk >Ú P APSR_C_Pos NÚ P APSR_C_Msk UÚ P APSR_V_Pos ;Ú P APSR_V_Msk BÚ 8
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<unnamed> SÚ 8
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<unnamed> QÚ
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" ISR 0Ú
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" _reserved0 !Ú " b ¯Ú
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" w ¬Ú
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IPSR_Type °Ú P IPSR_ISR_Pos Ú P IPSR_ISR_Msk Ú 8
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<unnamed> SÚ 8
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<unnamed> QÚ
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" §ISR 'Ú
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" § _reserved0 Ú
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" §T ÅÚ
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" § _reserved1 Ú
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" §V ÃÚ
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" §C ÖÚ
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" §Z ¿Ú
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" §N ËÚ " ¦b ¦Ú
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" ¦w £Ú
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xPSR_Type Ú P xPSR_N_Pos Ú P xPSR_N_Msk Ú P xPSR_Z_Pos Ú P xPSR_Z_Msk Ú P xPSR_C_Pos Ú P xPSR_C_Msk Ú P xPSR_V_Pos Ú P xPSR_V_Msk Ú P xPSR_T_Pos Ú P xPSR_T_Msk Ú P xPSR_ISR_Pos hÚ P xPSR_ISR_Msk oÚ 8
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<unnamed> SÚ 8
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<unnamed> QÚ
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" À _reserved0 ÿÚ
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" ÀSPSEL qÚ
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" À _reserved1 þÚ " ¿b Ú
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" ¿w Ú CONTROL_Type ÇÚ P CONTROL_SPSEL_Pos Ú P CONTROL_SPSEL_Msk Ú 8
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<unnamed> QÚ <" ÉISER Ú <" |É
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RESERVED0 Ú <" ÉICER Ú <" |É
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RESERVED1 ¬Ú <" ÉISPR Ú <" |É
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RESERVED2 «Ú <" ÉICPR Ú <" |É
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RESERVED3 ªÚ <" É
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RESERVED4 ¢Ú <" ÉIP Ú
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NVIC_Type ¾Ú 8
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<unnamed> QÚ
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" ÕCPUID nÚ
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" ÕICSR ´Ú
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" Õ
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RESERVED0 KÚ
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" ÕAIRCR rÚ
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" ÕSCR ÿÚ
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" ÕCCR Ú
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" Õ
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RESERVED1 JÚ <" ÕSHP ÆÚ
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" ÕSHCSR `Ú SCB_Type Ú" P SCB_CPUID_IMPLEMENTER_Pos »Ú" P SCB_CPUID_IMPLEMENTER_Msk ÂÚ P SCB_CPUID_VARIANT_Pos ðÚ P SCB_CPUID_VARIANT_Msk ÷Ú# P SCB_CPUID_ARCHITECTURE_Pos xÚ# P SCB_CPUID_ARCHITECTURE_Msk Ú P SCB_CPUID_PARTNO_Pos 3Ú P SCB_CPUID_PARTNO_Msk :Ú P SCB_CPUID_REVISION_Pos Ú P SCB_CPUID_REVISION_Msk Ú P SCB_ICSR_NMIPENDSET_Pos NÚ P SCB_ICSR_NMIPENDSET_Msk UÚ P SCB_ICSR_PENDSVSET_Pos Ú P SCB_ICSR_PENDSVSET_Msk Ú P SCB_ICSR_PENDSVCLR_Pos Ú P SCB_ICSR_PENDSVCLR_Msk Ú P SCB_ICSR_PENDSTSET_Pos Ú P SCB_ICSR_PENDSTSET_Msk Ú P SCB_ICSR_PENDSTCLR_Pos Ú P SCB_ICSR_PENDSTCLR_Msk Ú P SCB_ICSR_ISRPREEMPT_Pos :Ú P SCB_ICSR_ISRPREEMPT_Msk AÚ P SCB_ICSR_ISRPENDING_Pos RÚ P SCB_ICSR_ISRPENDING_Msk YÚ! P SCB_ICSR_VECTPENDING_Pos Ú! P SCB_ICSR_VECTPENDING_Msk Ú P SCB_ICSR_VECTACTIVE_Pos WÚ P SCB_ICSR_VECTACTIVE_Msk ^Ú P SCB_AIRCR_VECTKEY_Pos îÚ P SCB_AIRCR_VECTKEY_Msk õÚ" P SCB_AIRCR_VECTKEYSTAT_Pos ªÚ" P SCB_AIRCR_VECTKEYSTAT_Msk ±Ú P SCB_AIRCR_ENDIANESS_Pos kÚ P SCB_AIRCR_ENDIANESS_Msk rÚ" P SCB_AIRCR_SYSRESETREQ_Pos Ú" P SCB_AIRCR_SYSRESETREQ_Msk Ú$ P SCB_AIRCR_VECTCLRACTIVE_Pos .Ú$ P SCB_AIRCR_VECTCLRACTIVE_Msk 5Ú P SCB_SCR_SEVONPEND_Pos àÚ P SCB_SCR_SEVONPEND_Msk çÚ P SCB_SCR_SLEEPDEEP_Pos ûÚ P SCB_SCR_SLEEPDEEP_Msk Ú P SCB_SCR_SLEEPONEXIT_Pos >Ú P SCB_SCR_SLEEPONEXIT_Msk EÚ P SCB_CCR_STKALIGN_Pos GÚ P SCB_CCR_STKALIGN_Msk NÚ P SCB_CCR_UNALIGN_TRP_Pos ;Ú P SCB_CCR_UNALIGN_TRP_Msk BÚ# P SCB_SHCSR_SVCALLPENDED_Pos xÚ# P SCB_SHCSR_SVCALLPENDED_Msk Ú 8
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<unnamed> QÚ
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" CTRL òÚ
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" LOAD Ú
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" VAL FÚ
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" CALIB ÊÚ SysTick_Type Ú# P SysTick_CTRL_COUNTFLAG_Pos ¦Ú# P SysTick_CTRL_COUNTFLAG_Msk Ú# P SysTick_CTRL_CLKSOURCE_Pos Ú# P SysTick_CTRL_CLKSOURCE_Msk ¥Ú! P SysTick_CTRL_TICKINT_Pos 7Ú! P SysTick_CTRL_TICKINT_Msk >Ú P SysTick_CTRL_ENABLE_Pos ¨Ú P SysTick_CTRL_ENABLE_Msk ¯Ú P SysTick_LOAD_RELOAD_Pos Ú P SysTick_LOAD_RELOAD_Msk ´Ú P SysTick_VAL_CURRENT_Pos ~Ú P SysTick_VAL_CURRENT_Msk
Ú P SysTick_CALIB_NOREF_Pos ¯Ú P SysTick_CALIB_NOREF_Msk ¶Ú P SysTick_CALIB_SKEW_Pos ñÚ P SysTick_CALIB_SKEW_Msk øÚ P SysTick_CALIB_TENMS_Pos ¢Ú P SysTick_CALIB_TENMS_Msk ©Ú P _VAL2FLD qÚ P _FLD2VAL qÚ P SCS_BASE XÚ P SysTick_BASE oÚ P
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NVIC_BASE Ú P SCB_BASE iÚ P SCB íÚ P SysTick óÚ P NVIC Ú P CMSIS_NVIC_VIRTUAL Ú! P NVIC_SetPriorityGrouping 3Ú! P NVIC_GetPriorityGrouping ?Ú P NVIC_EnableIRQ íÚ P NVIC_GetEnableIRQ ÇÚ P NVIC_DisableIRQ ~Ú P NVIC_GetPendingIRQ GÚ P NVIC_SetPendingIRQ ;Ú P NVIC_ClearPendingIRQ |Ú P NVIC_SetPriority Ú P NVIC_GetPriority Ú P NVIC_SystemReset Ú P CMSIS_VECTAB_VIRTUAL Ú P NVIC_SetVector Ú P NVIC_GetVector Ú P NVIC_USER_IRQ_OFFSET dÚ P EXC_RETURN_HANDLER +Ú P EXC_RETURN_THREAD_MSP Ú P EXC_RETURN_THREAD_PSP Ú P _BIT_SHIFT Ú P _SHP_IDX -Ú P _IP_IDX Ú# P __NVIC_SetPriorityGrouping qÚ# P __NVIC_GetPriorityGrouping }Ú __NVIC_EnableIRQ TÚ ,"" ËIRQn sÚ __memory_changed HÚ __NVIC_GetEnableIRQ .Ú ,"" ÎIRQn pÚ __NVIC_DisableIRQ åÚ ,"" ÐIRQn nÚ __schedule_barrier sÚ __dsb çÚ __isb âÚ __NVIC_GetPendingIRQ ®Ú ,"" ÕIRQn iÚ __NVIC_SetPendingIRQ ¢Ú ,"" ×IRQn gÚ __NVIC_ClearPendingIRQ ãÚ ,"" ÙIRQn eÚ __NVIC_SetPriority õÚ ,"" ÛIRQn cÚ ,
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" Û priority HÚ __NVIC_GetPriority Ú ,"" ÞIRQn `Ú NVIC_EncodePriority Ú ,
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" àPriorityGroup LÚ ,
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" àPreemptPriority xÚ ,
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" à SubPriority 3Ú
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" àPriorityGroupTmp 9Ú
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" àPreemptPriorityBits Ú
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" àSubPriorityBits ½Ú NVIC_DecodePriority Ú ,
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" ç Priority \Ú ,
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" çPriorityGroup EÚ ," çpPreemptPriority ñÚ ," ç pSubPriority ¬Ú
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" çPriorityGroupTmp 2Ú
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" çPreemptPriorityBits ûÚ
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" çSubPriorityBits ¶Ú __NVIC_SetVector èÚ ,"" ïIRQn OÚ ,
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" ïvector 'Ú
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" ïvectors ÖÚ __NVIC_GetVector ôÚ ,"" óIRQn KÚ
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" óvectors ÒÚ __NVIC_SystemReset ûÚ __nop ÓÚ SCB_GetFPUType ôÚ SysTick_Config YÚ ,
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" ùticks Ú P __SYSTEM_PANSERIES_H__ Ú 8 _adc_vbg_kb ^Ú " ü
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adc_vbg_k !Ú " ü
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adc_vbg_b ,Ú ADC_VBG_KB_T DÚ 8 _otp_struct ûÚ <" d8 ïÚ 8
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<unnamed> QÚ <" rsvd0 ùÚ " pmu_vbg_trim "Ú " rsvd1 KÚ " pmu_vbg_volt_l JÚ " pmu_vbg_volt_h NÚ " hp_ldo_trim Ú " hp_ldo_volt_l ÆÚ " hp_ldo_volt_h ÊÚ " lph_ldo_trim 0Ú " lph_ldo_volt_l XÚ " lph_ldo_volt_h \Ú " lpl_ldo_trim ,Ú " lpl_ldo_volt_l TÚ " lpl_ldo_volt_h XÚ " flash_ldo_trim bÚ " rsvd2 JÚ " flash_ldo_volt_l Ú " flash_ldo_volt_h Ú " ana_ldo_trim DÚ " rffe_ldo_trim ÏÚ " fsyn_ldo_trim ²Ú " adc_ldo_trim LÚ " vco_ldo_trim ,Ú " ipoly_trim éÚ " rsvd3 IÚ " bod_vref_trim ÉÚ " rsvd4 HÚ " bod_vref_volt_l ñÚ " bod_vref_volt_h õÚ " adc_vbg_1v17_trim ÔÚ " rsvd5 GÚ " adc_vbg_1v17_volt ÂÚ " adc_vbg_1v20_trim ÚÚ " rsvd6 FÚ " adc_vbg_1v20_volt ÈÚ " rch_trim ÝÚ
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" rch_freq äÚ " rcl_coarse_trim ïÚ " rsvd7 EÚ " rcl_fine_trim ÎÚ " rcl_freq ÞÚ " xth_xocap_a Ú " xth_xocap_m Ú " xth_xocap_n Ú " xtl_xocap_a Ú " xtl_xocap_m Ú " xtl_xocap_n Ú " buck_imax_cal_trim ÄÚ " rsvd8 DÚ " buck_zero_cal_trim ³Ú " rsvd9 CÚ " buck_out_trim ´Ú " rsvd10 Ú " buck_vout_volt *Ú "
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adc_vdd_k Ú "
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adc_vdd_b ¯Ú "
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adc_vbg_k Ú "
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adc_vbg_b ¥Ú " adc_temp_volt ÁÚ " current_temp_value Ú " battery_trim Ú# " pa_power_calib_trim_6dbm {Ú# " pa_power_calib_trim_0dbm Ú <" mac_addr ÏÚ <" uid ¿Ú "
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chip_info Ú " cp_version ùÚ " ft_version òÚ " cp_pass_flag KÚ " ft_pass_flag DÚ " cp_checksum ªÚ " ft_checksum £Ú <" user_rw_data ôÚ " m AÚ 8
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<unnamed> QÚ <" Í rsvd0 ®Ú " Í pmu_vbg_trim ×Ú " Í rsvd1 Ú " Í pmu_vbg_volt_l ÿÚ " Í pmu_vbg_volt_h Ú " Í hp_ldo_trim SÚ " Í hp_ldo_volt_l {Ú " Í hp_ldo_volt_h Ú " Í lph_ldo_trim åÚ " Í lph_ldo_volt_l Ú " Í lph_ldo_volt_h Ú " Í lpl_ldo_trim áÚ " Í lpl_ldo_volt_l Ú " Í lpl_ldo_volt_h Ú " Í flash_ldo_trim Ú " Í rsvd2 ÿÚ " Í flash_ldo_volt_l ?Ú " Í flash_ldo_volt_h CÚ " Í ana_ldo_trim ùÚ " Í rffe_ldo_trim Ú " Í fsyn_ldo_trim gÚ " Í adc_ldo_trim Ú " Í vco_ldo_trim áÚ " Í ipoly_trim Ú " Í rsvd3 þÚ " Í bod_vref_trim ~Ú " Í rsvd4 ýÚ " Í bod_vref_volt_l ¦Ú " Í bod_vref_volt_h ªÚ " Í rsvd5 üÚ " Í xtl_core Ú " Í
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xth_icore #Ú " Í rch_bias ¯Ú " Í dpll_vco_freq_trim [Ú " Í dpll_kvco_ctrl Ú " Í dpll_icp_ctrl
Ú " Í dpll_icp_bias Ú " Í rsvd6 ûÚ " Í adc_vbg_1v20_trim Ú " Í ptat_temp_trim õÚ " Í adc_vbg_1v20_volt }Ú " Í rch_trim Ú
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" Í rch_freq Ú " Í rcl_coarse_trim ¤Ú " Í lph_ldo_vref_trim ÉÚ " Í rsvd7 úÚ " Í rcl_fine_trim Ú " Í rcl_freq Ú " Í analog_temp_volt &Ú <"
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Í
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rsvd_0x3e KÚ " Í analog_0p6v_volt Ú <"
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Í rsvd8 ºÚ " Í buck_imax_cal_trim yÚ " Í rsvd9 øÚ " Í buck_zero_cal_trim hÚ " Í rsvd10 ÎÚ " Í buck_out_trim iÚ " Í rsvd11 ÍÚ " Í buck_vout_volt ßÚ " Í
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adc_vdd_k PÚ " Í
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adc_vdd_b dÚ " Í
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adc_vbg_k OÚ " Í
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adc_vbg_b ZÚ " Í adc_temp_volt vÚ " Í current_temp_value ;Ú " Í battery_trim ÌÚ <" Í rsvd12 Ú <" Í uid tÚ " Í
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chip_info 9Ú " Í cp_version ®Ú " Í ft_version §Ú " Í cp_pass_flag Ú " Í ft_pass_flag ùÚ " Í cp_checksum _Ú " Í ft_checksum XÚ <" Í user_rw_data ©Ú <" Í mac_addr Ú " Í xth_xocap_a EÚ " Í xth_xocap_m 9Ú " Í xth_xocap_n 8Ú " Í xth_xocap_trim õÚ " Í xtl_xocap_a AÚ " Í xtl_xocap_m 5Ú " Í xtl_xocap_n 4Ú " Í xtl_xocap_trim ñÚ <" Í adc_vbg_kb £Ú " Í adc_vbat_k ßÚ " Í adc_vbat_b êÚ " Í adc_vbat_dtemp_k \Ú " Í adc_vbat_dtemp_b eÚ " Í adc_temp_k ÎÚ
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" Í
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adc_ctrl2 sÚ
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" Í adc_extsmpt AÚ " Í xth_fix_code1 »Ú " Í xth_fix_code2 ºÚ " Í xtl_fix_code1 ·Ú " Í xtl_fix_code2 ¶Ú <" +Í rsvd13 kÚ " Í ft_checksum2 $Ú " m_v2 3Ú OTP_STRUCT_T ÿÚ isFtDataValid èÚ
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vec_remap_adr Ú SystemCoreClockUpdate aÚ SystemInit »Ú , otp xÚ SystemHwParamLoader 6Ú RESET pÚ SET Ú FlagStatus ïÚ ITStatus ÐÚ DISABLE ûÚ ENABLE JÚ FunctionalState ÏÚ P IS_FUNCTIONAL_STATE ×Ú 8
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<unnamed> QÚ
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" Á
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CTL Ú
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" Á
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CMP Ú
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" Á
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INTSTS Ú
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" Á
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CNT Ú
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" Á
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CAP $Ú
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" Á
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EXTCTL Ú
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" Á
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EINTSTS ÆÚ
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" Á
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CMP1 åÚ
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" Á
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CMP2 äÚ TIMER_T ¿Ú P TIMER_CTL_PSC_Pos Ú P TIMER_CTL_PSC_Msk Ú P TIMER_CTL_CAPSRC_Pos 4Ú P TIMER_CTL_CAPSRC_Msk ;Ú P TIMER_CTL_WKEN_Pos ¿Ú P TIMER_CTL_WKEN_Msk ÆÚ P TIMER_CTL_EXTCNTEN_Pos Ú P TIMER_CTL_EXTCNTEN_Msk Ú P TIMER_CTL_ACTSTS_Pos Ú P TIMER_CTL_ACTSTS_Msk %Ú P TIMER_CTL_RSTCNT_Pos Ú P TIMER_CTL_RSTCNT_Msk Ú P TIMER_CTL_OPMODE_Pos ,Ú P TIMER_CTL_OPMODE_Msk 3Ú P TIMER_CTL_INTEN_Pos tÚ P TIMER_CTL_INTEN_Msk {Ú P TIMER_CTL_CNTEN_Pos zÚ P TIMER_CTL_CNTEN_Msk Ú P TIMER_CTL_ICEDEBUG_Pos ´Ú P TIMER_CTL_ICEDEBUG_Msk »Ú P TIMER_CMP_CMPDAT_Pos :Ú P TIMER_CMP_CMPDAT_Msk AÚ P TIMER_INTSTS_TIF_Pos Ú P TIMER_INTSTS_TIF_Msk Ú P TIMER_INTSTS_TWKF0_Pos ~Ú P TIMER_INTSTS_TWKF0_Msk
Ú P TIMER_INTSTS_TWKF1_Pos }Ú P TIMER_INTSTS_TWKF1_Msk Ú P TIMER_INTSTS_TWKF2_Pos |Ú P TIMER_INTSTS_TWKF2_Msk Ú P TIMER_INTSTS_TF0_Pos $Ú P TIMER_INTSTS_TF0_Msk +Ú P TIMER_INTSTS_TF1_Pos #Ú P TIMER_INTSTS_TF1_Msk *Ú P TIMER_INTSTS_TF2_Pos "Ú P TIMER_INTSTS_TF2_Msk )Ú P TIMER_CNT_CNT_Pos Ú P TIMER_CNT_CNT_Msk Ú P TIMER_CAP_CAPDAT_Pos RÚ P TIMER_CAP_CAPDAT_Msk YÚ" P TIMER_EXTCTL_CNTPHASE_Pos Ú" P TIMER_EXTCTL_CNTPHASE_Msk ¦Ú! P TIMER_EXTCTL_CAPEDGE_Pos Ú! P TIMER_EXTCTL_CAPEDGE_Msk Ú P TIMER_EXTCTL_CAPEN_Pos Ú P TIMER_EXTCTL_CAPEN_Msk Ú" P TIMER_EXTCTL_CAPFUNCS_Pos ¢Ú" P TIMER_EXTCTL_CAPFUNCS_Msk ©Ú P TIMER_EXTCTL_CAPIEN_Pos IÚ P TIMER_EXTCTL_CAPIEN_Msk PÚ! P TIMER_EXTCTL_CAPDBEN_Pos
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Ú! P TIMER_EXTCTL_CAPDBEN_Msk Ú! P TIMER_EXTCTL_CNTDBEN_Pos ùÚ! P TIMER_EXTCTL_CNTDBEN_Msk Ú P TIMER_EXTCTL_CAPSEL_Pos AÚ P TIMER_EXTCTL_CAPSEL_Msk HÚ" P TIMER_EXTCTL_ACMPSSEL_Pos Ú" P TIMER_EXTCTL_ACMPSSEL_Msk ¤Ú P TIMER_EINTSTS_CAPIF_Pos @Ú P TIMER_EINTSTS_CAPIF_Msk GÚ P TIMER_EINTSTS_CAPF_Pos Ú P TIMER_EINTSTS_CAPF_Msk Ú 8
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<unnamed> QÚ
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" TRIM_EN øÚ
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"
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TRIM_CODE lÚ
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"
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TRIM_CTRL RÚ
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" TRIM_INT Ú
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" TRIM_CAL_CNT mÚ
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" TRIM_IDEAL_CNT ÚÚ
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" TRIM_REAL_CNT Ú TRIM_T Ú# P TRIM_MEASURE_TUNING_EN_Pos 3Ú# P TRIM_MEASURE_TUNING_EN_Msk :Ú" P TRIM_COARSE_TUNING_EN_Pos Ú" P TRIM_COARSE_TUNING_EN_Msk Ú P TRIM_FINE_TUNING_EN_Pos )Ú P TRIM_FINE_TUNING_EN_Msk 0Ú P TRIM_COARSE_CODE_Pos @Ú P TRIM_COARSE_CODE_Msk GÚ P TRIM_FINE_CODE_Pos ßÚ P TRIM_FINE_CODE_Msk æÚ P TRIM_BIT_WIDTH_Pos ½Ú P TRIM_BIT_WIDTH_Msk ÄÚ P TRIM_CLRL_RELATION_Pos Ú P TRIM_CLRL_RELATION_Msk Ú$ P TRIM_CLRL_EARLY_TERM_EN_Pos ×Ú$ P TRIM_CLRL_EARLY_TERM_EN_Msk ÞÚ% P TRIM_CLRL_FAIL_CLAC_FLAG_Pos ÔÚ% P TRIM_CLRL_FAIL_CLAC_FLAG_Msk ÛÚ P TRIM_CLRL_CODE_STEP_Pos /Ú P TRIM_CLRL_CODE_STEP_Msk 6Ú P TRIM_CLRL_ERR_RANGE_Pos 0Ú P TRIM_CLRL_ERR_RANGE_Msk 7Ú P TRIM_INT_EN_Pos ¤Ú P TRIM_INT_EN_Msk «Ú" P TRIM_INT_MEASURE_STOP_Pos lÚ" P TRIM_INT_MEASURE_STOP_Msk sÚ# P TRIM_FLAG_MEASURE_STOP_Pos ;Ú# P TRIM_FLAG_MEASURE_STOP_Msk BÚ P TRIM_INT_CTUNE_STOP_Pos Ú P TRIM_INT_CTUNE_STOP_Msk
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Ú! P TRIM_FLAG_CTUNE_STOP_Pos ÒÚ! P TRIM_FLAG_CTUNE_STOP_Msk ÙÚ P TRIM_INT_FTUNE_STOP_Pos Ú P TRIM_INT_FTUNE_STOP_Msk Ú! P TRIM_FLAG_FTUNE_STOP_Pos ÏÚ! P TRIM_FLAG_FTUNE_STOP_Msk ÖÚ P TRIM_INT_OVERFLOW_Pos ·Ú P TRIM_INT_OVERFLOW_Msk ¾Ú P TRIM_FLAG_OVERFLOW_Pos Ú P TRIM_FLAG_OVERFLOW_Msk Ú P TRIM_CALC_CNT_Pos &Ú P TRIM_CALC_CNT_Msk -Ú P TRIM_CALC_WATI_CNT_Pos Ú P TRIM_CALC_WATI_CNT_Msk Ú 8
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<unnamed> QÚ
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" ¿ MODE ÒÚ
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" ¿ DINOFF =Ú
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" ¿ DOUT »Ú
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" ¿ DATMSK /Ú
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" ¿ PIN Ú
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" ¿ DBEN ÞÚ
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" ¿ INTTYPE ÄÚ
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" ¿ INTEN wÚ
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" ¿ INTSRC Ú GPIO_T Ú 8
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<unnamed> QÚ
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" Ê DBCTL Ú
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GPIO_DB_T (Ú P GP_MODE_MODE0_Pos IÚ P GP_MODE_MODE0_Msk PÚ P GP_MODE_MODE1_Pos HÚ P GP_MODE_MODE1_Msk OÚ P GP_MODE_MODE2_Pos GÚ P GP_MODE_MODE2_Msk NÚ P GP_MODE_MODE3_Pos FÚ P GP_MODE_MODE3_Msk MÚ P GP_MODE_MODE4_Pos EÚ P GP_MODE_MODE4_Msk LÚ P GP_MODE_MODE5_Pos DÚ P GP_MODE_MODE5_Msk KÚ P GP_DINOFF_DINOFF0_Pos Ú P GP_DINOFF_DINOFF0_Msk &Ú P GP_DINOFF_DINOFF1_Pos Ú P GP_DINOFF_DINOFF1_Msk %Ú P GP_DINOFF_DINOFF2_Pos Ú P GP_DINOFF_DINOFF2_Msk $Ú P GP_DINOFF_DINOFF3_Pos Ú P GP_DINOFF_DINOFF3_Msk #Ú P GP_DINOFF_DINOFF4_Pos Ú P GP_DINOFF_DINOFF4_Msk "Ú P GP_DINOFF_DINOFF5_Pos Ú P GP_DINOFF_DINOFF5_Msk !Ú P GP_DINOFF_DINOFF6_Pos Ú P GP_DINOFF_DINOFF6_Msk Ú P GP_DINOFF_DINOFF7_Pos Ú P GP_DINOFF_DINOFF7_Msk Ú P GP_DOUT_DOUT0_Pos Ú P GP_DOUT_DOUT0_Msk "Ú P GP_DOUT_DOUT1_Pos Ú P GP_DOUT_DOUT1_Msk !Ú P GP_DOUT_DOUT2_Pos Ú P GP_DOUT_DOUT2_Msk Ú P GP_DOUT_DOUT3_Pos Ú P GP_DOUT_DOUT3_Msk Ú P GP_DOUT_DOUT4_Pos Ú P GP_DOUT_DOUT4_Msk Ú P GP_DOUT_DOUT5_Pos Ú P GP_DOUT_DOUT5_Msk Ú P GP_DOUT_DOUT6_Pos Ú P GP_DOUT_DOUT6_Msk Ú P GP_DOUT_DOUT7_Pos Ú P GP_DOUT_DOUT7_Msk Ú P GP_DATMSK_DATMSK0_Pos Ú P GP_DATMSK_DATMSK0_Msk
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Ú P GP_DATMSK_DATMSK1_Pos Ú P GP_DATMSK_DATMSK1_Msk Ú P GP_DATMSK_DATMSK2_Pos Ú P GP_DATMSK_DATMSK2_Msk Ú P GP_DATMSK_DATMSK3_Pos Ú P GP_DATMSK_DATMSK3_Msk Ú P GP_DATMSK_DATMSK4_Pos ÿÚ P GP_DATMSK_DATMSK4_Msk Ú P GP_DATMSK_DATMSK5_Pos þÚ P GP_DATMSK_DATMSK5_Msk Ú P GP_DATMSK_DATMSK6_Pos ýÚ P GP_DATMSK_DATMSK6_Msk Ú P GP_DATMSK_DATMSK7_Pos üÚ P GP_DATMSK_DATMSK7_Msk Ú P GP_PIN_PIN0_Pos ÉÚ P GP_PIN_PIN0_Msk ÐÚ P GP_PIN_PIN1_Pos ÈÚ P GP_PIN_PIN1_Msk ÏÚ P GP_PIN_PIN2_Pos ÇÚ P GP_PIN_PIN2_Msk ÎÚ P GP_PIN_PIN3_Pos ÆÚ P GP_PIN_PIN3_Msk ÍÚ P GP_PIN_PIN4_Pos ÅÚ P GP_PIN_PIN4_Msk ÌÚ P GP_PIN_PIN5_Pos ÄÚ P GP_PIN_PIN5_Msk ËÚ P GP_PIN_PIN6_Pos ÃÚ P GP_PIN_PIN6_Msk ÊÚ P GP_PIN_PIN7_Pos ÂÚ P GP_PIN_PIN7_Msk ÉÚ P GP_DBEN_DBEN0_Pos aÚ P GP_DBEN_DBEN0_Msk hÚ P GP_DBEN_DBEN1_Pos `Ú P GP_DBEN_DBEN1_Msk gÚ P GP_DBEN_DBEN2_Pos _Ú P GP_DBEN_DBEN2_Msk fÚ P GP_DBEN_DBEN3_Pos ^Ú P GP_DBEN_DBEN3_Msk eÚ P GP_DBEN_DBEN4_Pos ]Ú P GP_DBEN_DBEN4_Msk dÚ P GP_DBEN_DBEN5_Pos \Ú P GP_DBEN_DBEN5_Msk cÚ P GP_DBEN_DBEN6_Pos [Ú P GP_DBEN_DBEN6_Msk bÚ P GP_DBEN_DBEN7_Pos ZÚ P GP_DBEN_DBEN7_Msk aÚ P GP_INTTYPE_TYPE0_Pos Ú P GP_INTTYPE_TYPE0_Msk %Ú P GP_INTTYPE_TYPE1_Pos Ú P GP_INTTYPE_TYPE1_Msk $Ú P GP_INTTYPE_TYPE2_Pos Ú P GP_INTTYPE_TYPE2_Msk #Ú P GP_INTTYPE_TYPE3_Pos Ú P GP_INTTYPE_TYPE3_Msk "Ú P GP_INTTYPE_TYPE4_Pos Ú P GP_INTTYPE_TYPE4_Msk !Ú P GP_INTTYPE_TYPE5_Pos Ú P GP_INTTYPE_TYPE5_Msk Ú P GP_INTTYPE_TYPE6_Pos Ú P GP_INTTYPE_TYPE6_Msk Ú P GP_INTTYPE_TYPE7_Pos Ú P GP_INTTYPE_TYPE7_Msk Ú P GP_INTEN_FLIEN0_Pos £Ú P GP_INTEN_FLIEN0_Msk ªÚ P GP_INTEN_FLIEN1_Pos ¢Ú P GP_INTEN_FLIEN1_Msk ©Ú P GP_INTEN_FLIEN2_Pos ¡Ú P GP_INTEN_FLIEN2_Msk ¨Ú P GP_INTEN_FLIEN3_Pos Ú P GP_INTEN_FLIEN3_Msk §Ú P GP_INTEN_FLIEN4_Pos Ú P GP_INTEN_FLIEN4_Msk ¦Ú P GP_INTEN_FLIEN5_Pos Ú P GP_INTEN_FLIEN5_Msk ¥Ú P GP_INTEN_FLIEN6_Pos Ú P GP_INTEN_FLIEN6_Msk ¤Ú P GP_INTEN_FLIEN7_Pos Ú P GP_INTEN_FLIEN7_Msk £Ú P GP_INTEN_RHIEN0_Pos Ú P GP_INTEN_RHIEN0_Msk ¢Ú P GP_INTEN_RHIEN1_Pos Ú P GP_INTEN_RHIEN1_Msk ¡Ú P GP_INTEN_RHIEN2_Pos Ú P GP_INTEN_RHIEN2_Msk Ú P GP_INTEN_RHIEN3_Pos Ú P GP_INTEN_RHIEN3_Msk Ú P GP_INTEN_RHIEN4_Pos Ú P GP_INTEN_RHIEN4_Msk Ú P GP_INTEN_RHIEN5_Pos Ú P GP_INTEN_RHIEN5_Msk Ú P GP_INTEN_RHIEN6_Pos Ú P GP_INTEN_RHIEN6_Msk Ú P GP_INTEN_RHIEN7_Pos Ú P GP_INTEN_RHIEN7_Msk Ú P GP_INTSRC_INTSRC0_Pos åÚ P GP_INTSRC_INTSRC0_Msk ìÚ P GP_INTSRC_INTSRC1_Pos äÚ P GP_INTSRC_INTSRC1_Msk ëÚ P GP_INTSRC_INTSRC2_Pos ãÚ P GP_INTSRC_INTSRC2_Msk êÚ P GP_INTSRC_INTSRC3_Pos âÚ P GP_INTSRC_INTSRC3_Msk éÚ P GP_INTSRC_INTSRC4_Pos áÚ P GP_INTSRC_INTSRC4_Msk èÚ P GP_INTSRC_INTSRC5_Pos àÚ P GP_INTSRC_INTSRC5_Msk çÚ P GP_INTSRC_INTSRC6_Pos ßÚ P GP_INTSRC_INTSRC6_Msk æÚ P GP_INTSRC_INTSRC7_Pos ÞÚ P GP_INTSRC_INTSRC7_Msk åÚ P GP_INTSRC_INTSRC8_Pos ÝÚ P GP_INTSRC_INTSRC8_Msk äÚ P GP_INTSRC_INTSRC9_Pos ÜÚ P GP_INTSRC_INTSRC9_Msk ãÚ P GP_INTSRC_INTSRC10_Pos ²Ú P GP_INTSRC_INTSRC10_Msk ¹Ú P GP_INTSRC_INTSRC11_Pos ±Ú P GP_INTSRC_INTSRC11_Msk ¸Ú P GP_INTSRC_INTSRC12_Pos °Ú P GP_INTSRC_INTSRC12_Msk ·Ú P GP_INTSRC_INTSRC13_Pos ¯Ú P GP_INTSRC_INTSRC13_Msk ¶Ú P GP_INTSRC_INTSRC14_Pos ®Ú P GP_INTSRC_INTSRC14_Msk µÚ P GP_INTSRC_INTSRC15_Pos Ú P GP_INTSRC_INTSRC15_Msk ´Ú P GP_DBCTL_DBCLKSEL_Pos Ú P GP_DBCTL_DBCLKSEL_Msk Ú P GP_DBCTL_DBCLKSRC_Pos
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Ú P GP_DBCTL_DBCLKSRC_Msk Ú P GP_DBCTL_ICLKON_Pos Ú P GP_DBCTL_ICLKON_Msk Ú 8
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<unnamed> QÚ
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" ÿ DAT ßÚ <" ÿ
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RESERVED0 ÒÚ
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" ÿ CTL ÕÚ
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" ÿ CHEN Ú
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" ÿ CMP0 ¦Ú
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" ÿ CMP1 ¥Ú
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" ÿ STATUS ÎÚ <" ÿ
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RESERVED1 ÝÚ
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" ÿ TRGDLY ÜÚ
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" ÿ EXTSMPT {Ú
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" ÿ SEQCTL æÚ
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" ÿ SEQDAT1 ½Ú
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" ÿ SEQDAT2 ¼Ú
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" ÿ CTL2 ¡Ú <" ÿ
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RESERVED2 ÜÚ
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" ÿ BV_CTL ØÚ ADC_T |Ú P ADC_DAT_RESULT_Pos ØÚ P ADC_DAT_RESULT_Msk ßÚ P ADC_DAT_OV_Pos Ú P ADC_DAT_OV_Msk !Ú P ADC_DAT_VALID_Pos IÚ P ADC_DAT_VALID_Msk PÚ P ADC_CTL_ADCEN_Pos TÚ P ADC_CTL_ADCEN_Msk [Ú P ADC_CTL_ADCIEN_Pos Ú P ADC_CTL_ADCIEN_Msk Ú P ADC_CTL_HWTRGSEL_Pos 9Ú P ADC_CTL_HWTRGSEL_Msk @Ú P ADC_CTL_HWTRGCOND_Pos ÷Ú P ADC_CTL_HWTRGCOND_Msk þÚ P ADC_CTL_HWTRGEN_Pos Ú P ADC_CTL_HWTRGEN_Msk Ú P ADC_CTL_FIFO_EN_Pos Ú P ADC_CTL_FIFO_EN_Msk Ú$ P ADC_CTL_FIFO_THRE_STATE_Pos Ú$ P ADC_CTL_FIFO_THRE_STATE_Msk Ú P ADC_CTL_SWTRG_Pos Ú P ADC_CTL_SWTRG_Msk Ú" P ADC_CTL_LEFT_SHIFT_EN_Pos ¥Ú" P ADC_CTL_LEFT_SHIFT_EN_Msk ¬Ú P ADC_CTL_SUB_BIAS_EN_Pos IÚ P ADC_CTL_SUB_BIAS_EN_Msk PÚ P ADC_CTL_BIAS_VALUE_Pos ªÚ P ADC_CTL_BIAS_VALUE_Msk ±Ú P ADC_CHEN_CHEN0_Pos $Ú P ADC_CHEN_CHEN0_Msk +Ú P ADC_CHEN_CHEN1_Pos #Ú P ADC_CHEN_CHEN1_Msk *Ú P ADC_CHEN_CHEN2_Pos "Ú P ADC_CHEN_CHEN2_Msk )Ú P ADC_CHEN_CHEN3_Pos !Ú P ADC_CHEN_CHEN3_Msk (Ú P ADC_CHEN_CHEN4_Pos Ú P ADC_CHEN_CHEN4_Msk 'Ú P ADC_CHEN_CHEN5_Pos Ú P ADC_CHEN_CHEN5_Msk &Ú P ADC_CHEN_CHEN6_Pos Ú P ADC_CHEN_CHEN6_Msk %Ú P ADC_CHEN_CHEN7_Pos Ú P ADC_CHEN_CHEN7_Msk $Ú P ADC_CHEN_CHEN8_VBG_Pos ÖÚ P ADC_CHEN_CHEN8_VBG_Msk ÝÚ P ADC_CHEN_CH9_TMP_Pos ZÚ P ADC_CHEN_CH9_TMP_Msk aÚ P ADC_CHEN_CH10_VDD_4_Pos ¬Ú P ADC_CHEN_CH10_VDD_4_Msk ³Ú P ADC_CHEN_CH11_VBG_2_Pos ¬Ú P ADC_CHEN_CH11_VBG_2_Msk ³Ú P ADC_CHEN_ALL_Msk ¤Ú P ADC_CMP0_ADCMPEN_Pos Ú P ADC_CMP0_ADCMPEN_Msk Ú P ADC_CMP0_ADCMPIE_Pos Ú P ADC_CMP0_ADCMPIE_Msk Ú P ADC_CMP0_CMPCOND_Pos xÚ P ADC_CMP0_CMPCOND_Msk Ú P ADC_CMP0_CMPCH_Pos Ú P ADC_CMP0_CMPCH_Msk Ú P ADC_CMP0_CMPMCNT_Pos jÚ P ADC_CMP0_CMPMCNT_Msk qÚ P ADC_CMP0_CMPDAT_Pos ÅÚ P ADC_CMP0_CMPDAT_Msk ÌÚ P ADC_CMP1_ADCMPEN_Pos Ú P ADC_CMP1_ADCMPEN_Msk Ú P ADC_CMP1_ADCMPIE_Pos Ú P ADC_CMP1_ADCMPIE_Msk Ú P ADC_CMP1_CMPCOND_Pos wÚ P ADC_CMP1_CMPCOND_Msk ~Ú P ADC_CMP1_CMPCH_Pos Ú P ADC_CMP1_CMPCH_Msk Ú P ADC_CMP1_CMPMCNT_Pos iÚ P ADC_CMP1_CMPMCNT_Msk pÚ P ADC_CMP1_CMPDAT_Pos ÄÚ P ADC_CMP1_CMPDAT_Msk ËÚ P ADC_STATUS_ADIF_Pos Ú P ADC_STATUS_ADIF_Msk Ú P ADC_STATUS_ADCMPIF0_Pos ~Ú P ADC_STATUS_ADCMPIF0_Msk
Ú P ADC_STATUS_ADCMPIF1_Pos }Ú P ADC_STATUS_ADCMPIF1_Msk Ú P ADC_STATUS_BUSY_Pos gÚ P ADC_STATUS_BUSY_Msk nÚ P ADC_STATUS_CHANNEL_Pos «Ú P ADC_STATUS_CHANNEL_Msk ²Ú P ADC_STATUS_VALID_Pos 8Ú P ADC_STATUS_VALID_Msk ?Ú# P ADC_STATUS_INTMSK_FULL_Pos 4Ú# P ADC_STATUS_INTMSK_FULL_Msk ;Ú$ P ADC_STATUS_INTMSK_EMPTY_Pos ÖÚ$ P ADC_STATUS_INTMSK_EMPTY_Msk ÝÚ# P ADC_STATUS_INTMSK_OVER_Pos +Ú# P ADC_STATUS_INTMSK_OVER_Msk 2Ú# P ADC_STATUS_INTMSK_HALF_Pos LÚ# P ADC_STATUS_INTMSK_HALF_Msk SÚ! P ADC_STATUS_INTMSK_AD_Pos æÚ! P ADC_STATUS_INTMSK_AD_Msk íÚ# P ADC_STATUS_INTMSK_CMP0_Pos WÚ# P ADC_STATUS_INTMSK_CMP0_Msk ^Ú# P ADC_STATUS_INTMSK_CMP1_Pos VÚ# P ADC_STATUS_INTMSK_CMP1_Msk ]Ú P ADC_STATUS_OV_Pos Ú P ADC_STATUS_OV_Msk Ú& P ADC_STATUS_ONE_CH_CLR_SEL_Pos GÚ& P ADC_STATUS_ONE_CH_CLR_SEL_Msk NÚ# P ADC_STATUS_ONE_CH_FLAG_Pos WÚ# P ADC_STATUS_ONE_CH_FLAG_Msk ^Ú# P ADC_STATUS_INTFLG_FULL_Pos FÚ# P ADC_STATUS_INTFLG_FULL_Msk MÚ$ P ADC_STATUS_INTFLG_EMPTY_Pos èÚ$ P ADC_STATUS_INTFLG_EMPTY_Msk ïÚ# P ADC_STATUS_INTFLG_OVER_Pos =Ú# P ADC_STATUS_INTFLG_OVER_Msk DÚ# P ADC_STATUS_INTFLG_HALF_Pos ^Ú# P ADC_STATUS_INTFLG_HALF_Msk eÚ P ADC_STATUS_ADCF_Pos Ú P ADC_STATUS_ADCF_Msk £Ú P ADC_STATUS_ADCMPF0_Pos ÉÚ P ADC_STATUS_ADCMPF0_Msk ÐÚ P ADC_STATUS_ADCMPF1_Pos ÈÚ P ADC_STATUS_ADCMPF1_Msk ÏÚ! P ADC_STATUS_FLAG_FULL_Pos ôÚ! P ADC_STATUS_FLAG_FULL_Msk ûÚ" P ADC_STATUS_FLAG_EMPTY_Pos Ú" P ADC_STATUS_FLAG_EMPTY_Msk Ú! P ADC_STATUS_FLAG_OVER_Pos ëÚ! P ADC_STATUS_FLAG_OVER_Msk òÚ! P ADC_STATUS_FLAG_HALF_Pos Ú! P ADC_STATUS_FLAG_HALF_Msk Ú P ADC_TRGDLY_DELAY_Pos GÚ P ADC_TRGDLY_DELAY_Msk NÚ P ADC_EXTSMPT_EXTSMPT_Pos Ú P ADC_EXTSMPT_EXTSMPT_Msk #Ú P ADC_SEQCTL_SEQEN_Pos DÚ P ADC_SEQCTL_SEQEN_Msk KÚ P ADC_SEQCTL_SEQTYPE_Pos Ú P ADC_SEQCTL_SEQTYPE_Msk Ú P ADC_SEQCTL_MODESEL_Pos ³Ú P ADC_SEQCTL_MODESEL_Msk ºÚ P ADC_SEQCTL_DELAY_EN_Pos YÚ P ADC_SEQCTL_DELAY_EN_Msk `Ú P ADC_SEQCTL_TRG_SEL_Pos Ú P ADC_SEQCTL_TRG_SEL_Msk Ú! P ADC_SEQCTL_ONE_CH_EN_Pos úÚ! P ADC_SEQCTL_ONE_CH_EN_Msk Ú P ADC_SEQCTL_TRG1CTL_Pos »Ú P ADC_SEQCTL_TRG1CTL_Msk ÂÚ P ADC_SEQCTL_TRG2CTL_Pos ºÚ P ADC_SEQCTL_TRG2CTL_Msk ÁÚ P ADC_SEQDAT1_RESULT_Pos ¶Ú P ADC_SEQDAT1_RESULT_Msk ½Ú P ADC_SEQDAT1_OV_Pos øÚ P ADC_SEQDAT1_OV_Msk ÿÚ P ADC_SEQDAT1_VALID_Pos 'Ú P ADC_SEQDAT1_VALID_Msk .Ú P ADC_SEQDAT2_RESULT_Pos µÚ P ADC_SEQDAT2_RESULT_Msk ¼Ú P ADC_SEQDAT2_OV_Pos ÷Ú P ADC_SEQDAT2_OV_Msk þÚ P ADC_SEQDAT2_VALID_Pos &Ú P ADC_SEQDAT2_VALID_Msk -Ú P ADC_CTL2_TESTMODE_Pos Ú P ADC_CTL2_TESTMODE_Msk Ú P ADC_CTL2_SHSEL_Pos üÚ P ADC_CTL2_SHSEL_Msk Ú P ADC_CTL2_DMA_EN_Pos µÚ P ADC_CTL2_DMA_EN_Msk ¼Ú P ADC_CTL2_CLKDIV_Pos ¼Ú P ADC_CTL2_CLKDIV_Msk ÃÚ P ADC_SEL_VREF_Pos }Ú P ADC_SEL_VREF_Msk Ú P ADC_CTL2_CMPCTL_Pos ¶Ú P ADC_CTL2_CMPCTL_Msk ½Ú P ADC_CTL2_DRVCTL_Pos ªÚ P ADC_CTL2_DRVCTL_Msk ±Ú 8
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<unnamed> QÚ
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" ÂP0_MFP +Ú
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" ÂP1_MFP *Ú
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" ÂP2_MFP )Ú
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" ÂP3_MFP (Ú <" 0ÂRESV SÚ
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" ÂREGLCTL ÞÚ
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" ÂSTATUS Ú
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" ÂCTRL0 Ú
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" ÂCTRL1 Ú SYS_T EÚ P SYS_P0_MFP_MFP_Pos ´Ú P SYS_P0_MFP_MFP_Msk »Ú P SYS_P0_MFP_ALT0_Pos Ú P SYS_P0_MFP_ALT0_Msk Ú P SYS_P0_MFP_ALT1_Pos Ú P SYS_P0_MFP_ALT1_Msk Ú P SYS_P0_MFP_ALT2_Pos Ú P SYS_P0_MFP_ALT2_Msk Ú P SYS_P0_MFP_ALT3_Pos Ú P SYS_P0_MFP_ALT3_Msk Ú P SYS_P0_MFP_ALT4_Pos Ú P SYS_P0_MFP_ALT4_Msk Ú P SYS_P0_MFP_ALT5_Pos Ú P SYS_P0_MFP_ALT5_Msk Ú P SYS_P0_MFP_ALT6_Pos ~Ú P SYS_P0_MFP_ALT6_Msk
Ú P SYS_P0_MFP_ALT7_Pos }Ú P SYS_P0_MFP_ALT7_Msk Ú P SYS_P1_MFP_MFP_Pos ³Ú P SYS_P1_MFP_MFP_Msk ºÚ P SYS_P1_MFP_ALT0_Pos Ú P SYS_P1_MFP_ALT0_Msk Ú P SYS_P1_MFP_ALT1_Pos Ú P SYS_P1_MFP_ALT1_Msk Ú P SYS_P1_MFP_ALT2_Pos Ú P SYS_P1_MFP_ALT2_Msk Ú P SYS_P1_MFP_ALT3_Pos Ú P SYS_P1_MFP_ALT3_Msk Ú P SYS_P1_MFP_ALT4_Pos Ú P SYS_P1_MFP_ALT4_Msk Ú P SYS_P1_MFP_ALT5_Pos ~Ú P SYS_P1_MFP_ALT5_Msk
Ú P SYS_P1_MFP_ALT6_Pos }Ú P SYS_P1_MFP_ALT6_Msk Ú P SYS_P1_MFP_ALT7_Pos |Ú P SYS_P1_MFP_ALT7_Msk Ú P SYS_P1_MFP_TYPE_Pos RÚ P SYS_P1_MFP_TYPE_Msk YÚ P SYS_P1_MFP_P12EXT_Pos ìÚ P SYS_P1_MFP_P12EXT_Msk óÚ P SYS_P1_MFP_P13EXT_Pos ëÚ P SYS_P1_MFP_P13EXT_Msk òÚ P SYS_P1_MFP_P14EXT_Pos êÚ P SYS_P1_MFP_P14EXT_Msk ñÚ P SYS_P2_MFP_ALT0_Pos Ú P SYS_P2_MFP_ALT0_Msk Ú P SYS_P2_MFP_ALT1_Pos Ú P SYS_P2_MFP_ALT1_Msk Ú P SYS_P2_MFP_ALT2_Pos Ú P SYS_P2_MFP_ALT2_Msk Ú P SYS_P2_MFP_ALT3_Pos Ú P SYS_P2_MFP_ALT3_Msk Ú P SYS_P2_MFP_ALT4_Pos ~Ú P SYS_P2_MFP_ALT4_Msk
Ú P SYS_P2_MFP_ALT5_Pos }Ú P SYS_P2_MFP_ALT5_Msk Ú P SYS_P2_MFP_ALT6_Pos |Ú P SYS_P2_MFP_ALT6_Msk Ú P SYS_P2_MFP_ALT7_Pos {Ú P SYS_P2_MFP_ALT7_Msk Ú P SYS_P3_MFP_MFP_Pos ±Ú P SYS_P3_MFP_MFP_Msk ¸Ú P SYS_P3_MFP_ALT0_Pos Ú P SYS_P3_MFP_ALT0_Msk Ú P SYS_P3_MFP_ALT1_Pos Ú P SYS_P3_MFP_ALT1_Msk Ú P SYS_P3_MFP_ALT2_Pos Ú P SYS_P3_MFP_ALT2_Msk Ú P SYS_P3_MFP_ALT4_Pos }Ú P SYS_P3_MFP_ALT4_Msk Ú P SYS_P3_MFP_ALT5_Pos |Ú P SYS_P3_MFP_ALT5_Msk Ú P SYS_P3_MFP_ALT6_Pos {Ú P SYS_P3_MFP_ALT6_Msk Ú P SYS_P3_MFP_P32EXT_Pos èÚ P SYS_P3_MFP_P32EXT_Msk ïÚ P SYS_P4_MFP_MFP_Pos °Ú P SYS_P4_MFP_MFP_Msk ·Ú P SYS_P4_MFP_ALT6_Pos zÚ P SYS_P4_MFP_ALT6_Msk Ú P SYS_P4_MFP_ALT7_Pos yÚ P SYS_P4_MFP_ALT7_Msk Ú P SYS_P5_MFP_MFP_Pos ¯Ú P SYS_P5_MFP_MFP_Msk ¶Ú P SYS_P5_MFP_ALT0_Pos Ú P SYS_P5_MFP_ALT0_Msk Ú P SYS_P5_MFP_ALT1_Pos ~Ú P SYS_P5_MFP_ALT1_Msk
Ú P SYS_P5_MFP_ALT2_Pos }Ú P SYS_P5_MFP_ALT2_Msk Ú P SYS_P5_MFP_ALT3_Pos |Ú P SYS_P5_MFP_ALT3_Msk Ú P SYS_P5_MFP_ALT4_Pos {Ú P SYS_P5_MFP_ALT4_Msk Ú P SYS_P5_MFP_ALT5_Pos zÚ P SYS_P5_MFP_ALT5_Msk Ú P SYS_P5_MFP_ALT6_Pos yÚ P SYS_P5_MFP_ALT6_Msk Ú P SYS_P5_MFP_ALT7_Pos xÚ P SYS_P5_MFP_ALT7_Msk Ú P SYS_P5_MFP_P50EXT_Pos æÚ P SYS_P5_MFP_P50EXT_Msk íÚ P SYS_P5_MFP_P51EXT_Pos åÚ P SYS_P5_MFP_P51EXT_Msk ìÚ P SYS_REGLCTL_REGLCTL_Pos 5Ú P SYS_REGLCTL_REGLCTL_Msk <Ú 8
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<unnamed> QÚ
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" ·RSTSTS Ú
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" ·IPRST0 5Ú
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" ·IPRST1 4Ú
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" ·
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BODCTL_3V QÚ
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" · BLDBCTL_3V Ú
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" ·CLK_TOP_CTRL_3V =Ú
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" · RCL_CTRL_3V Ú
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" · RCH_CTRL Ú
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" · XTL_CTRL_3V yÚ
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" · XTH_CTRL kÚ
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" ·
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DPLL_CTRL 1Ú
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" · AHB_CLK_CTRL SÚ
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" ·APB1_CLK_CTRL Ú
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" ·APB2_CLK_CTRL Ú
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" ·MEAS_CLK_CTRL öÚ CLK_T jÚ P CLK_RSTSTS_CHIPRF_Pos ÉÚ P CLK_RSTSTS_CHIPRF_Msk ÐÚ P CLK_RSTSTS_PINRF_Pos Ú P CLK_RSTSTS_PINRF_Msk Ú P CLK_RSTSTS_WDTRF_Pos Ú P CLK_RSTSTS_WDTRF_Msk Ú P CLK_RSTSTS_LVRRF_Pos ûÚ P CLK_RSTSTS_LVRRF_Msk Ú P CLK_RSTSTS_BODRF_Pos Ú P CLK_RSTSTS_BODRF_Msk !Ú P CLK_RSTSTS_SYSRF_Pos ðÚ P CLK_RSTSTS_SYSRF_Msk ÷Ú P CLK_RSTSTS_PORRF_Pos þÚ P CLK_RSTSTS_PORRF_Msk Ú P CLK_RSTSTS_CPURF_Pos Ú P CLK_RSTSTS_CPURF_Msk Ú P CLK_IPRST0_CHIPRST_Pos Ú P CLK_IPRST0_CHIPRST_Msk Ú P CLK_IPRST0_CPURST_Pos ÕÚ P CLK_IPRST0_CPURST_Msk ÜÚ P CLK_IPRST0_DMARST_Pos ëÚ P CLK_IPRST0_DMARST_Msk òÚ P CLK_IPRST0_RFRST_Pos 'Ú P CLK_IPRST0_RFRST_Msk .Ú P CLK_IPRST0_EFUSERST_Pos AÚ P CLK_IPRST0_EFUSERST_Msk HÚ P CLK_IPRST0_USBRST_Pos ÓÚ P CLK_IPRST0_USBRST_Msk ÚÚ# P CLK_IPRST0_MDMSTDBYRST_Pos OÚ# P CLK_IPRST0_MDMSTDBYRST_Msk VÚ P CLK_IPRST0_MDMRST_Pos ßÚ P CLK_IPRST0_MDMRST_Msk æÚ# P CLK_IPRST0_CHIPSCOPEEN_Pos {Ú# P CLK_IPRST0_CHIPSCOPEEN_Msk Ú P CLK_IPRST0_FTORRST_Pos Ú P CLK_IPRST0_FTORRST_Msk Ú P CLK_IPRST1_I2C0RST_Pos ÌÚ P CLK_IPRST1_I2C0RST_Msk ÓÚ P CLK_IPRST1_SPI0RST_Pos Ú P CLK_IPRST1_SPI0RST_Msk ¥Ú P CLK_IPRST1_SPI1RST_Pos Ú P CLK_IPRST1_SPI1RST_Msk ¤Ú P CLK_IPRST1_UART0RST_Pos LÚ P CLK_IPRST1_UART0RST_Msk SÚ P CLK_IPRST1_UART1RST_Pos KÚ P CLK_IPRST1_UART1RST_Msk RÚ P CLK_IPRST1_PWM0RST_Pos Ú P CLK_IPRST1_PWM0RST_Msk Ú P CLK_IPRST1_ADCRST_Pos ôÚ P CLK_IPRST1_ADCRST_Msk ûÚ P CLK_IPRST1_WDTRST_Pos ÍÚ P CLK_IPRST1_WDTRST_Msk ÔÚ P CLK_IPRST1_WWDTRST_Pos tÚ P CLK_IPRST1_WWDTRST_Msk {Ú P CLK_IPRST1_TMR0RST_Pos Ú P CLK_IPRST1_TMR0RST_Msk Ú P CLK_IPRST1_TMR1RST_Pos Ú P CLK_IPRST1_TMR1RST_Msk Ú P CLK_IPRST1_TMR2RST_Pos Ú P CLK_IPRST1_TMR2RST_Msk Ú P CLK_IPRST1_GPIORST_Pos Ú P CLK_IPRST1_GPIORST_Msk Ú P CLK_IPRST1_TRIMRST_Pos ~Ú P CLK_IPRST1_TRIMRST_Msk
Ú# P CLK_BODCTL_BODRSTEN_Pos_3v MÚ# P CLK_BODCTL_BODRSTEN_Msk_3v TÚ P CLK_BODCTL_BODIF_Pos ^Ú P CLK_BODCTL_BODIF_Msk eÚ P CLK_BODCTL_BODOUT_Pos óÚ P CLK_BODCTL_BODOUT_Msk úÚ P CLK_BODCTL_LVREN_Pos_3v -Ú P CLK_BODCTL_LVREN_Msk_3v 4Ú P CLK_BODCTL_BODEN_Pos_3v LÚ P CLK_BODCTL_BODEN_Msk_3v SÚ! P CLK_BODCTL_BODSEL_Pos_3v ùÚ! P CLK_BODCTL_BODSEL_Msk_3v Ú# P CLK_BODCTL_LVR_TEST_Pos_3v Ú# P CLK_BODCTL_LVR_TEST_Msk_3v "Ú# P CLK_BODCTL_BOD_TEST_Pos_3v :Ú# P CLK_BODCTL_BOD_TEST_Msk_3v AÚ% P CLK_BLDBCTL_LVRDB_SEL_Pos_3v ®Ú% P CLK_BLDBCTL_LVRDB_SEL_Msk_3v µÚ% P CLK_BLDBCTL_BODDB_SEL_Pos_3v ÍÚ% P CLK_BLDBCTL_BODDB_SEL_Msk_3v ÔÚ' P CLK_TOPCTL_RSICV_SYSCNT_EN_Pos ÔÚ' P CLK_TOPCTL_RSICV_SYSCNT_EN_Msk ÛÚ# P CLK_TOPCTL_SYS_CLK_SEL_Pos Ú# P CLK_TOPCTL_SYS_CLK_SEL_Msk $Ú& P CLK_TOPCTL_32K_CLK_SEL_Pos_3v ^Ú& P CLK_TOPCTL_32K_CLK_SEL_Msk_3v eÚ P CLK_TOPCTL_AHB_DIV_Pos Ú P CLK_TOPCTL_AHB_DIV_Msk Ú P CLK_TOPCTL_APB1_DIV_Pos XÚ P CLK_TOPCTL_APB1_DIV_Msk _Ú P CLK_TOPCTL_APB2_DIV_Pos WÚ P CLK_TOPCTL_APB2_DIV_Msk ^Ú# P CLK_RCLCTL_RC32K_EN_Pos_3v kÚ# P CLK_RCLCTL_RC32K_EN_Msk_3v rÚ$ P CLK_RCLCTL_RC32K_TST_EN_Pos Ú$ P CLK_RCLCTL_RC32K_TST_EN_Msk Ú" P CLK_RCLCTL_CLK_SEL_Pos_3v Ú" P CLK_RCLCTL_CLK_SEL_Msk_3v Ú' P CLK_RCLCTL_RC32K_COARSE_Pos_3v 9Ú' P CLK_RCLCTL_RC32K_COARSE_Msk_3v @Ú% P CLK_RCLCTL_RC32K_FINE_Pos_3v ØÚ% P CLK_RCLCTL_RC32K_FINE_Msk_3v ßÚ& P CLK_RCLCTL_RC32K_DELAY_Pos_3v Ú& P CLK_RCLCTL_RC32K_DELAY_Msk_3v Ú P CLK_RCLCTL_STABLE_Pos ùÚ P CLK_RCLCTL_STABLE_Msk Ú P CLK_RCHCTL_RCH_EN_Pos éÚ P CLK_RCHCTL_RCH_EN_Msk ðÚ" P CLK_RCHCTL_RCH_TST_EN_Pos Ú" P CLK_RCHCTL_RCH_TST_EN_Msk Ú P CLK_RCHCTL_CLK_SEL_Pos Ú P CLK_RCHCTL_CLK_SEL_Msk Ú P CLK_RCHCTL_BIAS_Pos Ú P CLK_RCHCTL_BIAS_Msk ¤Ú P CLK_RCHCTL_RCH_FREQ_Pos JÚ P CLK_RCHCTL_RCH_FREQ_Msk QÚ P CLK_RCHCTL_DELAY_Pos KÚ P CLK_RCHCTL_DELAY_Msk RÚ P CLK_RCHCTL_STABLE_Pos ýÚ P CLK_RCHCTL_STABLE_Msk Ú! P CLK_XTLCTL_XTL_EN_Pos_3v ¥Ú! P CLK_XTLCTL_XTL_EN_Msk_3v ¬Ú" P CLK_XTLCTL_XTL_TST_EN_Pos QÚ" P CLK_XTLCTL_XTL_TST_EN_Msk XÚ$ P CLK_XTLCTL_CORE_BIAS_Pos_3v âÚ$ P CLK_XTLCTL_CORE_BIAS_Msk_3v éÚ# P CLK_XTLCTL_XTL_TRIM_Pos_3v øÚ# P CLK_XTLCTL_XTL_TRIM_Msk_3v ÿÚ% P CLK_XTLCTL_XTL_CAP_EN_Pos_3v jÚ% P CLK_XTLCTL_XTL_CAP_EN_Msk_3v qÚ P CLK_XTLCTL_DELAY_Pos_3v "Ú P CLK_XTLCTL_DELAY_Msk_3v )Ú P CLK_XTLCTL_STABLE_Pos âÚ P CLK_XTLCTL_STABLE_Msk éÚ P CLK_XTHCTL_XTH_EN_Pos »Ú P CLK_XTHCTL_XTH_EN_Msk ÂÚ" P CLK_XTHCTL_XTH_TST_EN_Pos YÚ" P CLK_XTHCTL_XTH_TST_EN_Msk `Ú" P CLK_XTHCTL_START_FAST_Pos ~Ú" P CLK_XTHCTL_START_FAST_Msk
Ú# P CLK_XTHCTL_DEGLITCH_EN_Pos aÚ# P CLK_XTHCTL_DEGLITCH_EN_Msk hÚ" P CLK_XTHCTL_XO_CAP_SEL_Pos |Ú" P CLK_XTHCTL_XO_CAP_SEL_Msk Ú P CLK_XTHCTL_DELAY_Pos 4Ú P CLK_XTHCTL_DELAY_Msk ;Ú P CLK_XTHCTL_STABLE_Pos æÚ P CLK_XTHCTL_STABLE_Msk íÚ P CLK_DPLLCTL_DPLL_EN_Pos GÚ P CLK_DPLLCTL_DPLL_EN_Msk NÚ$ P CLK_DPLLCTL_DPLL_TST_EN_Pos åÚ$ P CLK_DPLLCTL_DPLL_TST_EN_Msk ìÚ! P CLK_DPLLCTL_FREQ_OUT_Pos ÞÚ! P CLK_DPLLCTL_FREQ_OUT_Msk åÚ! P CLK_DPLLCTL_RCLK_SEL_Pos ôÚ! P CLK_DPLLCTL_RCLK_SEL_Msk ûÚ! P CLK_DPLLCTL_ICP_BIAS_Pos Ú! P CLK_DPLLCTL_ICP_BIAS_Msk Ú! P CLK_DPLLCTL_ICP_CTRL_Pos óÚ! P CLK_DPLLCTL_ICP_CTRL_Msk úÚ" P CLK_DPLLCTL_KVCO_CTRL_Pos Ú" P CLK_DPLLCTL_KVCO_CTRL_Msk ¡Ú& P CLK_DPLLCTL_VCO_FREQ_TRIM_Pos IÚ& P CLK_DPLLCTL_VCO_FREQ_TRIM_Msk PÚ P CLK_DPLLCTL_DIV_SEL_Pos ?Ú P CLK_DPLLCTL_DIV_SEL_Msk FÚ P CLK_DPLLCTL_DELAY_Pos úÚ P CLK_DPLLCTL_DELAY_Msk Ú P CLK_DPLLCTL_STABLE_Pos ¬Ú P CLK_DPLLCTL_STABLE_Msk ³Ú P CLK_AHBCLK_DMAEN_Pos pÚ P CLK_AHBCLK_DMAEN_Msk wÚ P CLK_AHBCLK_GPIOEN_Pos Ú P CLK_AHBCLK_GPIOEN_Msk Ú" P CLK_AHBCLK_SYSTICK_EN_Pos ¯Ú" P CLK_AHBCLK_SYSTICK_EN_Msk ¶Ú P CLK_AHBCLK_APB1EN_Pos <Ú P CLK_AHBCLK_APB1EN_Msk CÚ P CLK_AHBCLK_APB2EN_Pos ;Ú P CLK_AHBCLK_APB2EN_Msk BÚ P CLK_AHBCLK_AHBEN_Pos wÚ P CLK_AHBCLK_AHBEN_Msk ~Ú! P CLK_AHBCLK_BLE32M_EN_Pos VÚ! P CLK_AHBCLK_BLE32M_EN_Msk ]Ú! P CLK_AHBCLK_BLE32K_EN_Pos XÚ! P CLK_AHBCLK_BLE32K_EN_Msk _Ú" P CLK_AHBCLK_BLE32M_SEL_Pos Ú" P CLK_AHBCLK_BLE32M_SEL_Msk
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Ú" P CLK_AHBCLK_ROM_CLK_EN_Pos ²Ú" P CLK_AHBCLK_ROM_CLK_EN_Msk ¹Ú$ P CLK_AHBCLK_EFUSE_CLK_EN_Pos $Ú$ P CLK_AHBCLK_EFUSE_CLK_EN_Msk +Ú& P CLK_AHBCLK_USB_AHB_CLK_EN_Pos Ú& P CLK_AHBCLK_USB_AHB_CLK_EN_Msk Ú& P CLK_AHBCLK_USB_48M_CLK_EN_Pos Ú& P CLK_AHBCLK_USB_48M_CLK_EN_Msk Ú% P CLK_AHBCLK_SPI_FLASH_DIV_Pos ÊÚ% P CLK_AHBCLK_SPI_FLASH_DIV_Msk ÑÚ) P !CLK_AHBCLK_SPI_FLASH_CLK_SEL_Pos Ú) P !CLK_AHBCLK_SPI_FLASH_CLK_SEL_Msk Ú' P CLK_AHBCLK_DPLL_CLK_TST_EN_Pos Ú' P CLK_AHBCLK_DPLL_CLK_TST_EN_Msk Ú( P CLK_AHBCLK_SPI_CLK_SEL_FPGA_Pos ÚÚ( P CLK_AHBCLK_SPI_CLK_SEL_FPGA_Msk áÚ# P CLK_APB1CLK_WDTSRC_SEL_Pos vÚ# P CLK_APB1CLK_WDTSRC_SEL_Msk }Ú$ P CLK_APB1CLK_WWDTSRC_SEL_Pos Ú$ P CLK_APB1CLK_WWDTSRC_SEL_Msk $Ú$ P CLK_APB1CLK_TMR0SRC_SEL_Pos @Ú$ P CLK_APB1CLK_TMR0SRC_SEL_Msk GÚ& P CLK_APB1CLK_PWM01_CLK_SEL_Pos ¹Ú& P CLK_APB1CLK_PWM01_CLK_SEL_Msk ÀÚ& P CLK_APB1CLK_PWM23_CLK_SEL_Pos µÚ& P CLK_APB1CLK_PWM23_CLK_SEL_Msk ¼Ú& P CLK_APB1CLK_PWM45_CLK_SEL_Pos ±Ú& P CLK_APB1CLK_PWM45_CLK_SEL_Msk ¸Ú& P CLK_APB1CLK_PWM67_CLK_SEL_Pos Ú& P CLK_APB1CLK_PWM67_CLK_SEL_Msk ´Ú$ P CLK_APB1CLK_ADC_CLK_SEL_Pos JÚ$ P CLK_APB1CLK_ADC_CLK_SEL_Msk QÚ$ P CLK_APB2CLK_TMR1SRC_SEL_Pos >Ú$ P CLK_APB2CLK_TMR1SRC_SEL_Msk EÚ$ P CLK_APB2CLK_TMR2SRC_SEL_Pos =Ú$ P CLK_APB2CLK_TMR2SRC_SEL_Msk DÚ$ P CLK_MEASCLK_TRIM_CLK_EN_Pos Ú$ P CLK_MEASCLK_TRIM_CLK_EN_Msk Ú% P CLK_MEASCLK_TRIM_CLK_SEL_Pos ²Ú% P CLK_MEASCLK_TRIM_CLK_SEL_Msk ¹Ú% P CLK_MEASCLK_TRIM_CLK_DIV_Pos ³Ú% P CLK_MEASCLK_TRIM_CLK_DIV_Msk ºÚ% P CLK_MEASCLK_XTL_QUICK_EN_Pos ¤Ú% P CLK_MEASCLK_XTL_QUICK_EN_Msk «Ú P CLK_MEASCLK_XTH_DIV_Pos >Ú P CLK_MEASCLK_XTH_DIV_Msk EÚ 8
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<unnamed> QÚ
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" ¶CTL Ú
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" ¶ALTCTL 2Ú WDT_T UÚ P WDT_CTL_RSTCNT_Pos ¨Ú P WDT_CTL_RSTCNT_Msk ¯Ú P WDT_CTL_RSTEN_Pos üÚ P WDT_CTL_RSTEN_Msk Ú P WDT_CTL_RSTF_Pos KÚ P WDT_CTL_RSTF_Msk RÚ P WDT_CTL_IF_Pos ÿÚ P WDT_CTL_IF_Msk Ú P WDT_CTL_WKEN_Pos UÚ P WDT_CTL_WKEN_Msk \Ú P WDT_CTL_WKF_Pos ¤Ú P WDT_CTL_WKF_Msk «Ú P WDT_CTL_INTEN_Pos
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Ú P WDT_CTL_INTEN_Msk Ú P WDT_CTL_WDTEN_Pos Ú P WDT_CTL_WDTEN_Msk Ú P WDT_CTL_TOUTSEL_Pos TÚ P WDT_CTL_TOUTSEL_Msk [Ú# P WDT_CTL_RST_REGION_SEL_Pos Ú# P WDT_CTL_RST_REGION_SEL_Msk Ú P WDT_CTL_TOF_Pos £Ú P WDT_CTL_TOF_Msk ªÚ P WDT_CTL_ICEDEBUG_Pos JÚ P WDT_CTL_ICEDEBUG_Msk QÚ P WDT_ALTCTL_RSTDSEL_Pos |Ú P WDT_ALTCTL_RSTDSEL_Msk Ú 8
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<unnamed> QÚ
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" ÔRLDCNT Ú
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" ÔCTL ûÚ
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" ÔSTATUS ôÚ
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" ÔCNT ùÚ WWDT_T üÚ P WWDT_RLDCNT_RLDCNT_Pos |Ú P WWDT_RLDCNT_RLDCNT_Msk Ú P WWDT_CTL_WWDTEN_Pos TÚ P WWDT_CTL_WWDTEN_Msk [Ú P WWDT_CTL_INTEN_Pos ±Ú P WWDT_CTL_INTEN_Msk ¸Ú P WWDT_CTL_PSCSEL_Pos cÚ P WWDT_CTL_PSCSEL_Msk jÚ P WWDT_CTL_CMPDAT_Pos tÚ P WWDT_CTL_CMPDAT_Msk {Ú P WWDT_CTL_ICEDEBUG_Pos ñÚ P WWDT_CTL_ICEDEBUG_Msk øÚ P WWDT_STATUS_WWDTIF_Pos QÚ P WWDT_STATUS_WWDTIF_Msk XÚ P WWDT_STATUS_WWDTRF_Pos HÚ P WWDT_STATUS_WWDTRF_Msk OÚ P WWDT_STATUS_WWDTF_Pos Ú P WWDT_STATUS_WWDTF_Msk £Ú P WWDT_CNT_CNTDAT_Pos mÚ P WWDT_CNT_CNTDAT_Msk tÚ 8
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<unnamed> QÚ
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" îCLKPSC þÚ
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" îCLKDIV Ú
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" îCTL áÚ
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" îPERIOD0 ÉÚ
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" îPERIOD1 ÈÚ
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" îPERIOD2 ÇÚ
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" îPERIOD3 ÆÚ
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" îPERIOD4 ÅÚ
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" îPERIOD5 ÄÚ
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" îPERIOD6 ÃÚ
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" îPERIOD7 ÂÚ
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" îCMPDAT0 ÓÚ
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" îCMPDAT1 ÒÚ
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" îCMPDAT2 ÑÚ
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" îCMPDAT3 ÐÚ
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" îCMPDAT4 ÏÚ
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" îCMPDAT5 ÎÚ
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" îCMPDAT6 ÍÚ
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" îCMPDAT7 ÌÚ
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" îCTL2 Ú
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" îFLAG ¨Ú
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" îINTEN BÚ
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" îINTSTS ÙÚ
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" îPOEN Ú <" î
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RESERVED0 öÚ
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" îDTCTL EÚ
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" î ADCTCTL0 Ú
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" î ADCTCTL1 Ú
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" î ADCTSTS0 tÚ
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" î ADCTSTS1 sÚ <" î
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RESERVED1 éÚ
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" îPCACTL Ú PWM_T PÚ P PWM_CLKPSC_CLKPSC01_Pos yÚ P PWM_CLKPSC_CLKPSC01_Msk Ú P PWM_CLKPSC_CLKPSC23_Pos uÚ P PWM_CLKPSC_CLKPSC23_Msk |Ú P PWM_CLKPSC_CLKPSC45_Pos qÚ P PWM_CLKPSC_CLKPSC45_Msk xÚ P PWM_CLKPSC_CLKPSC67_Pos mÚ P PWM_CLKPSC_CLKPSC67_Msk tÚ P PWM_CLKDIV_CLKDIV0_Pos ²Ú P PWM_CLKDIV_CLKDIV0_Msk ¹Ú P PWM_CLKDIV_CLKDIV1_Pos ±Ú P PWM_CLKDIV_CLKDIV1_Msk ¸Ú P PWM_CLKDIV_CLKDIV2_Pos °Ú P PWM_CLKDIV_CLKDIV2_Msk ·Ú P PWM_CLKDIV_CLKDIV3_Pos ¯Ú P PWM_CLKDIV_CLKDIV3_Msk ¶Ú P PWM_CLKDIV_CLKDIV4_Pos ®Ú P PWM_CLKDIV_CLKDIV4_Msk µÚ P PWM_CLKDIV_CLKDIV5_Pos Ú P PWM_CLKDIV_CLKDIV5_Msk ´Ú P PWM_CLKDIV_CLKDIV6_Pos ¬Ú P PWM_CLKDIV_CLKDIV6_Msk ³Ú P PWM_CLKDIV_CLKDIV7_Pos «Ú P PWM_CLKDIV_CLKDIV7_Msk ²Ú P PWM_CTL_CNTEN0_Pos ÙÚ P PWM_CTL_CNTEN0_Msk àÚ P PWM_CTL_PINV0_Pos Ú P PWM_CTL_PINV0_Msk Ú P PWM_CTL_CNTMODE0_Pos CÚ P PWM_CTL_CNTMODE0_Msk JÚ P PWM_CTL_CNTEN1_Pos ØÚ P PWM_CTL_CNTEN1_Msk ßÚ P PWM_CTL_HCUPDT_Pos ¹Ú P PWM_CTL_HCUPDT_Msk ÀÚ P PWM_CTL_PINV1_Pos Ú P PWM_CTL_PINV1_Msk Ú P PWM_CTL_CNTMODE1_Pos BÚ P PWM_CTL_CNTMODE1_Msk IÚ P PWM_CTL_CNTEN2_Pos ×Ú P PWM_CTL_CNTEN2_Msk ÞÚ P PWM_CTL_PINV2_Pos Ú P PWM_CTL_PINV2_Msk Ú P PWM_CTL_CNTMODE2_Pos AÚ P PWM_CTL_CNTMODE2_Msk HÚ P PWM_CTL_CNTEN3_Pos ÖÚ P PWM_CTL_CNTEN3_Msk ÝÚ P PWM_CTL_PINV3_Pos Ú P PWM_CTL_PINV3_Msk Ú P PWM_CTL_CNTMODE3_Pos @Ú P PWM_CTL_CNTMODE3_Msk GÚ P PWM_CTL_CNTEN4_Pos ÕÚ P PWM_CTL_CNTEN4_Msk ÜÚ P PWM_CTL_PINV4_Pos Ú P PWM_CTL_PINV4_Msk Ú P PWM_CTL_CNTMODE4_Pos ?Ú P PWM_CTL_CNTMODE4_Msk FÚ P PWM_CTL_CNTEN5_Pos ÔÚ P PWM_CTL_CNTEN5_Msk ÛÚ P PWM_CTL_ASYMEN_Pos ´Ú P PWM_CTL_ASYMEN_Msk »Ú P PWM_CTL_PINV5_Pos Ú P PWM_CTL_PINV5_Msk Ú P PWM_CTL_CNTMODE5_Pos >Ú P PWM_CTL_CNTMODE5_Msk EÚ P PWM_CTL_CNTEN6_Pos ÓÚ P PWM_CTL_CNTEN6_Msk ÚÚ P PWM_CTL_PINV6_Pos Ú P PWM_CTL_PINV6_Msk Ú P PWM_CTL_CNTMODE6_Pos =Ú P PWM_CTL_CNTMODE6_Msk DÚ P PWM_CTL_CNTEN7_Pos ÒÚ P PWM_CTL_CNTEN7_Msk ÙÚ P PWM_CTL_PINV7_Pos Ú P PWM_CTL_PINV7_Msk Ú P PWM_CTL_CNTMODE7_Pos <Ú P PWM_CTL_CNTMODE7_Msk CÚ P PWM_PERIOD0_PERIOD0_Pos tÚ P PWM_PERIOD0_PERIOD0_Msk {Ú P PWM_PERIOD0_PERIOD1_Pos sÚ P PWM_PERIOD0_PERIOD1_Msk zÚ P PWM_PERIOD0_PERIOD2_Pos rÚ P PWM_PERIOD0_PERIOD2_Msk yÚ P PWM_PERIOD0_PERIOD3_Pos qÚ P PWM_PERIOD0_PERIOD3_Msk xÚ P PWM_PERIOD0_PERIOD4_Pos pÚ P PWM_PERIOD0_PERIOD4_Msk wÚ P PWM_PERIOD0_PERIOD5_Pos oÚ P PWM_PERIOD0_PERIOD5_Msk vÚ P PWM_PERIOD0_PERIOD6_Pos nÚ P PWM_PERIOD0_PERIOD6_Msk uÚ P PWM_PERIOD0_PERIOD7_Pos mÚ P PWM_PERIOD0_PERIOD7_Msk tÚ P PWM_PERIOD1_PERIOD0_Pos sÚ P PWM_PERIOD1_PERIOD0_Msk zÚ P PWM_PERIOD1_PERIOD1_Pos rÚ P PWM_PERIOD1_PERIOD1_Msk yÚ P PWM_PERIOD1_PERIOD2_Pos qÚ P PWM_PERIOD1_PERIOD2_Msk xÚ P PWM_PERIOD1_PERIOD3_Pos pÚ P PWM_PERIOD1_PERIOD3_Msk wÚ P PWM_PERIOD1_PERIOD4_Pos oÚ P PWM_PERIOD1_PERIOD4_Msk vÚ P PWM_PERIOD1_PERIOD5_Pos nÚ P PWM_PERIOD1_PERIOD5_Msk uÚ P PWM_PERIOD1_PERIOD6_Pos mÚ P PWM_PERIOD1_PERIOD6_Msk tÚ P PWM_PERIOD1_PERIOD7_Pos lÚ P PWM_PERIOD1_PERIOD7_Msk sÚ P PWM_PERIOD2_PERIOD0_Pos rÚ P PWM_PERIOD2_PERIOD0_Msk yÚ P PWM_PERIOD2_PERIOD1_Pos qÚ P PWM_PERIOD2_PERIOD1_Msk xÚ P PWM_PERIOD2_PERIOD2_Pos pÚ P PWM_PERIOD2_PERIOD2_Msk wÚ P PWM_PERIOD2_PERIOD3_Pos oÚ P PWM_PERIOD2_PERIOD3_Msk vÚ P PWM_PERIOD2_PERIOD4_Pos nÚ P PWM_PERIOD2_PERIOD4_Msk uÚ P PWM_PERIOD2_PERIOD5_Pos mÚ P PWM_PERIOD2_PERIOD5_Msk tÚ P PWM_PERIOD2_PERIOD6_Pos lÚ P PWM_PERIOD2_PERIOD6_Msk sÚ P PWM_PERIOD2_PERIOD7_Pos kÚ P PWM_PERIOD2_PERIOD7_Msk rÚ P PWM_PERIOD3_PERIOD0_Pos qÚ P PWM_PERIOD3_PERIOD0_Msk xÚ P PWM_PERIOD3_PERIOD1_Pos pÚ P PWM_PERIOD3_PERIOD1_Msk wÚ P PWM_PERIOD3_PERIOD2_Pos oÚ P PWM_PERIOD3_PERIOD2_Msk vÚ P PWM_PERIOD3_PERIOD3_Pos nÚ P PWM_PERIOD3_PERIOD3_Msk uÚ P PWM_PERIOD3_PERIOD4_Pos mÚ P PWM_PERIOD3_PERIOD4_Msk tÚ P PWM_PERIOD3_PERIOD5_Pos lÚ P PWM_PERIOD3_PERIOD5_Msk sÚ P PWM_PERIOD3_PERIOD6_Pos kÚ P PWM_PERIOD3_PERIOD6_Msk rÚ P PWM_PERIOD3_PERIOD7_Pos jÚ P PWM_PERIOD3_PERIOD7_Msk qÚ P PWM_PERIOD4_PERIOD0_Pos pÚ P PWM_PERIOD4_PERIOD0_Msk wÚ P PWM_PERIOD4_PERIOD1_Pos oÚ P PWM_PERIOD4_PERIOD1_Msk vÚ P PWM_PERIOD4_PERIOD2_Pos nÚ P PWM_PERIOD4_PERIOD2_Msk uÚ P PWM_PERIOD4_PERIOD3_Pos mÚ P PWM_PERIOD4_PERIOD3_Msk tÚ P PWM_PERIOD4_PERIOD4_Pos lÚ P PWM_PERIOD4_PERIOD4_Msk sÚ P PWM_PERIOD4_PERIOD5_Pos kÚ P PWM_PERIOD4_PERIOD5_Msk rÚ P PWM_PERIOD4_PERIOD6_Pos jÚ P PWM_PERIOD4_PERIOD6_Msk qÚ P PWM_PERIOD4_PERIOD7_Pos iÚ P PWM_PERIOD4_PERIOD7_Msk pÚ P PWM_PERIOD5_PERIOD0_Pos oÚ P PWM_PERIOD5_PERIOD0_Msk vÚ P PWM_PERIOD5_PERIOD1_Pos nÚ P PWM_PERIOD5_PERIOD1_Msk uÚ P PWM_PERIOD5_PERIOD2_Pos mÚ P PWM_PERIOD5_PERIOD2_Msk tÚ P PWM_PERIOD5_PERIOD3_Pos lÚ P PWM_PERIOD5_PERIOD3_Msk sÚ P PWM_PERIOD5_PERIOD4_Pos kÚ P PWM_PERIOD5_PERIOD4_Msk rÚ P PWM_PERIOD5_PERIOD5_Pos jÚ P PWM_PERIOD5_PERIOD5_Msk qÚ P PWM_PERIOD5_PERIOD6_Pos iÚ P PWM_PERIOD5_PERIOD6_Msk pÚ P PWM_PERIOD5_PERIOD7_Pos hÚ P PWM_PERIOD5_PERIOD7_Msk oÚ P PWM_PERIOD6_PERIOD0_Pos nÚ P PWM_PERIOD6_PERIOD0_Msk uÚ P PWM_PERIOD6_PERIOD1_Pos mÚ P PWM_PERIOD6_PERIOD1_Msk tÚ P PWM_PERIOD6_PERIOD2_Pos lÚ P PWM_PERIOD6_PERIOD2_Msk sÚ P PWM_PERIOD6_PERIOD3_Pos kÚ P PWM_PERIOD6_PERIOD3_Msk rÚ P PWM_PERIOD6_PERIOD4_Pos jÚ P PWM_PERIOD6_PERIOD4_Msk qÚ P PWM_PERIOD6_PERIOD5_Pos iÚ P PWM_PERIOD6_PERIOD5_Msk pÚ P PWM_PERIOD6_PERIOD6_Pos hÚ P PWM_PERIOD6_PERIOD6_Msk oÚ P PWM_PERIOD6_PERIOD7_Pos gÚ P PWM_PERIOD6_PERIOD7_Msk nÚ P PWM_PERIOD7_PERIOD0_Pos mÚ P PWM_PERIOD7_PERIOD0_Msk tÚ P PWM_PERIOD7_PERIOD1_Pos lÚ P PWM_PERIOD7_PERIOD1_Msk sÚ P PWM_PERIOD7_PERIOD2_Pos kÚ P PWM_PERIOD7_PERIOD2_Msk rÚ P PWM_PERIOD7_PERIOD3_Pos jÚ P PWM_PERIOD7_PERIOD3_Msk qÚ P PWM_PERIOD7_PERIOD4_Pos iÚ P PWM_PERIOD7_PERIOD4_Msk pÚ P PWM_PERIOD7_PERIOD5_Pos hÚ P PWM_PERIOD7_PERIOD5_Msk oÚ P PWM_PERIOD7_PERIOD6_Pos gÚ P PWM_PERIOD7_PERIOD6_Msk nÚ P PWM_PERIOD7_PERIOD7_Pos fÚ P PWM_PERIOD7_PERIOD7_Msk mÚ P PWM_CMPDAT0_CMP0_Pos gÚ P PWM_CMPDAT0_CMP0_Msk nÚ P PWM_CMPDAT0_CMP1_Pos fÚ P PWM_CMPDAT0_CMP1_Msk mÚ P PWM_CMPDAT0_CMP2_Pos eÚ P PWM_CMPDAT0_CMP2_Msk lÚ P PWM_CMPDAT0_CMP3_Pos dÚ P PWM_CMPDAT0_CMP3_Msk kÚ P PWM_CMPDAT0_CMP4_Pos cÚ P PWM_CMPDAT0_CMP4_Msk jÚ P PWM_CMPDAT0_CMP5_Pos bÚ P PWM_CMPDAT0_CMP5_Msk iÚ P PWM_CMPDAT0_CMP6_Pos aÚ P PWM_CMPDAT0_CMP6_Msk hÚ P PWM_CMPDAT0_CMP7_Pos `Ú P PWM_CMPDAT0_CMP7_Msk gÚ P PWM_CMPDAT0_CMPD0_Pos !Ú P PWM_CMPDAT0_CMPD0_Msk (Ú P PWM_CMPDAT0_CMPD1_Pos Ú P PWM_CMPDAT0_CMPD1_Msk 'Ú P PWM_CMPDAT0_CMPD2_Pos Ú P PWM_CMPDAT0_CMPD2_Msk &Ú P PWM_CMPDAT0_CMPD3_Pos Ú P PWM_CMPDAT0_CMPD3_Msk %Ú P PWM_CMPDAT0_CMPD4_Pos Ú P PWM_CMPDAT0_CMPD4_Msk $Ú P PWM_CMPDAT0_CMPD5_Pos Ú P PWM_CMPDAT0_CMPD5_Msk #Ú P PWM_CMPDAT0_CMPD6_Pos Ú P PWM_CMPDAT0_CMPD6_Msk "Ú P PWM_CMPDAT0_CMPD7_Pos Ú P PWM_CMPDAT0_CMPD7_Msk !Ú P PWM_CMPDAT1_CMP0_Pos fÚ P PWM_CMPDAT1_CMP0_Msk mÚ P PWM_CMPDAT1_CMP1_Pos eÚ P PWM_CMPDAT1_CMP1_Msk lÚ P PWM_CMPDAT1_CMP2_Pos dÚ P PWM_CMPDAT1_CMP2_Msk kÚ P PWM_CMPDAT1_CMP3_Pos cÚ P PWM_CMPDAT1_CMP3_Msk jÚ P PWM_CMPDAT1_CMP4_Pos bÚ P PWM_CMPDAT1_CMP4_Msk iÚ P PWM_CMPDAT1_CMP5_Pos aÚ P PWM_CMPDAT1_CMP5_Msk hÚ P PWM_CMPDAT1_CMP6_Pos `Ú P PWM_CMPDAT1_CMP6_Msk gÚ P PWM_CMPDAT1_CMP7_Pos _Ú P PWM_CMPDAT1_CMP7_Msk fÚ P PWM_CMPDAT1_CMPD0_Pos Ú P PWM_CMPDAT1_CMPD0_Msk 'Ú P PWM_CMPDAT1_CMPD1_Pos Ú P PWM_CMPDAT1_CMPD1_Msk &Ú P PWM_CMPDAT1_CMPD2_Pos Ú P PWM_CMPDAT1_CMPD2_Msk %Ú P PWM_CMPDAT1_CMPD3_Pos Ú P PWM_CMPDAT1_CMPD3_Msk $Ú P PWM_CMPDAT1_CMPD4_Pos Ú P PWM_CMPDAT1_CMPD4_Msk #Ú P PWM_CMPDAT1_CMPD5_Pos Ú P PWM_CMPDAT1_CMPD5_Msk "Ú P PWM_CMPDAT1_CMPD6_Pos Ú P PWM_CMPDAT1_CMPD6_Msk !Ú P PWM_CMPDAT1_CMPD7_Pos Ú P PWM_CMPDAT1_CMPD7_Msk Ú P PWM_CMPDAT2_CMP0_Pos eÚ P PWM_CMPDAT2_CMP0_Msk lÚ P PWM_CMPDAT2_CMP1_Pos dÚ P PWM_CMPDAT2_CMP1_Msk kÚ P PWM_CMPDAT2_CMP2_Pos cÚ P PWM_CMPDAT2_CMP2_Msk jÚ P PWM_CMPDAT2_CMP3_Pos bÚ P PWM_CMPDAT2_CMP3_Msk iÚ P PWM_CMPDAT2_CMP4_Pos aÚ P PWM_CMPDAT2_CMP4_Msk hÚ P PWM_CMPDAT2_CMP5_Pos `Ú P PWM_CMPDAT2_CMP5_Msk gÚ P PWM_CMPDAT2_CMP6_Pos _Ú P PWM_CMPDAT2_CMP6_Msk fÚ P PWM_CMPDAT2_CMP7_Pos ^Ú P PWM_CMPDAT2_CMP7_Msk eÚ P PWM_CMPDAT2_CMPD0_Pos Ú P PWM_CMPDAT2_CMPD0_Msk &Ú P PWM_CMPDAT2_CMPD1_Pos Ú P PWM_CMPDAT2_CMPD1_Msk %Ú P PWM_CMPDAT2_CMPD2_Pos Ú P PWM_CMPDAT2_CMPD2_Msk $Ú P PWM_CMPDAT2_CMPD3_Pos Ú P PWM_CMPDAT2_CMPD3_Msk #Ú P PWM_CMPDAT2_CMPD4_Pos Ú P PWM_CMPDAT2_CMPD4_Msk "Ú P PWM_CMPDAT2_CMPD5_Pos Ú P PWM_CMPDAT2_CMPD5_Msk !Ú P PWM_CMPDAT2_CMPD6_Pos Ú P PWM_CMPDAT2_CMPD6_Msk Ú P PWM_CMPDAT2_CMPD7_Pos Ú P PWM_CMPDAT2_CMPD7_Msk Ú P PWM_CMPDAT3_CMP0_Pos dÚ P PWM_CMPDAT3_CMP0_Msk kÚ P PWM_CMPDAT3_CMP1_Pos cÚ P PWM_CMPDAT3_CMP1_Msk jÚ P PWM_CMPDAT3_CMP2_Pos bÚ P PWM_CMPDAT3_CMP2_Msk iÚ P PWM_CMPDAT3_CMP3_Pos aÚ P PWM_CMPDAT3_CMP3_Msk hÚ P PWM_CMPDAT3_CMP4_Pos `Ú P PWM_CMPDAT3_CMP4_Msk gÚ P PWM_CMPDAT3_CMP5_Pos _Ú P PWM_CMPDAT3_CMP5_Msk fÚ P PWM_CMPDAT3_CMP6_Pos ^Ú P PWM_CMPDAT3_CMP6_Msk eÚ P PWM_CMPDAT3_CMP7_Pos ]Ú P PWM_CMPDAT3_CMP7_Msk dÚ P PWM_CMPDAT3_CMPD0_Pos Ú P PWM_CMPDAT3_CMPD0_Msk %Ú P PWM_CMPDAT3_CMPD1_Pos Ú P PWM_CMPDAT3_CMPD1_Msk $Ú P PWM_CMPDAT3_CMPD2_Pos Ú P PWM_CMPDAT3_CMPD2_Msk #Ú P PWM_CMPDAT3_CMPD3_Pos Ú P PWM_CMPDAT3_CMPD3_Msk "Ú P PWM_CMPDAT3_CMPD4_Pos Ú P PWM_CMPDAT3_CMPD4_Msk !Ú P PWM_CMPDAT3_CMPD5_Pos Ú P PWM_CMPDAT3_CMPD5_Msk Ú P PWM_CMPDAT3_CMPD6_Pos Ú P PWM_CMPDAT3_CMPD6_Msk Ú P PWM_CMPDAT3_CMPD7_Pos Ú P PWM_CMPDAT3_CMPD7_Msk Ú P PWM_CMPDAT4_CMP0_Pos cÚ P PWM_CMPDAT4_CMP0_Msk jÚ P PWM_CMPDAT4_CMP1_Pos bÚ P PWM_CMPDAT4_CMP1_Msk iÚ P PWM_CMPDAT4_CMP2_Pos aÚ P PWM_CMPDAT4_CMP2_Msk hÚ P PWM_CMPDAT4_CMP3_Pos `Ú P PWM_CMPDAT4_CMP3_Msk gÚ P PWM_CMPDAT4_CMP4_Pos _Ú P PWM_CMPDAT4_CMP4_Msk fÚ P PWM_CMPDAT4_CMP5_Pos ^Ú P PWM_CMPDAT4_CMP5_Msk eÚ P PWM_CMPDAT4_CMP6_Pos ]Ú P PWM_CMPDAT4_CMP6_Msk dÚ P PWM_CMPDAT4_CMP7_Pos \Ú P PWM_CMPDAT4_CMP7_Msk cÚ P PWM_CMPDAT4_CMPD0_Pos Ú P PWM_CMPDAT4_CMPD0_Msk $Ú P PWM_CMPDAT4_CMPD1_Pos Ú P PWM_CMPDAT4_CMPD1_Msk #Ú P PWM_CMPDAT4_CMPD2_Pos Ú P PWM_CMPDAT4_CMPD2_Msk "Ú P PWM_CMPDAT4_CMPD3_Pos Ú P PWM_CMPDAT4_CMPD3_Msk !Ú P PWM_CMPDAT4_CMPD4_Pos Ú P PWM_CMPDAT4_CMPD4_Msk Ú P PWM_CMPDAT4_CMPD5_Pos Ú P PWM_CMPDAT4_CMPD5_Msk Ú P PWM_CMPDAT4_CMPD6_Pos Ú P PWM_CMPDAT4_CMPD6_Msk Ú P PWM_CMPDAT4_CMPD7_Pos Ú P PWM_CMPDAT4_CMPD7_Msk Ú P PWM_CMPDAT5_CMP0_Pos bÚ P PWM_CMPDAT5_CMP0_Msk iÚ P PWM_CMPDAT5_CMP1_Pos aÚ P PWM_CMPDAT5_CMP1_Msk hÚ P PWM_CMPDAT5_CMP2_Pos `Ú P PWM_CMPDAT5_CMP2_Msk gÚ P PWM_CMPDAT5_CMP3_Pos _Ú P PWM_CMPDAT5_CMP3_Msk fÚ P PWM_CMPDAT5_CMP4_Pos ^Ú P PWM_CMPDAT5_CMP4_Msk eÚ P PWM_CMPDAT5_CMP5_Pos ]Ú P PWM_CMPDAT5_CMP5_Msk dÚ P PWM_CMPDAT5_CMP6_Pos \Ú P PWM_CMPDAT5_CMP6_Msk cÚ P PWM_CMPDAT5_CMP7_Pos [Ú P PWM_CMPDAT5_CMP7_Msk bÚ P PWM_CMPDAT5_CMPD0_Pos Ú P PWM_CMPDAT5_CMPD0_Msk #Ú P PWM_CMPDAT5_CMPD1_Pos Ú P PWM_CMPDAT5_CMPD1_Msk "Ú P PWM_CMPDAT5_CMPD2_Pos Ú P PWM_CMPDAT5_CMPD2_Msk !Ú P PWM_CMPDAT5_CMPD3_Pos Ú P PWM_CMPDAT5_CMPD3_Msk Ú P PWM_CMPDAT5_CMPD4_Pos Ú P PWM_CMPDAT5_CMPD4_Msk Ú P PWM_CMPDAT5_CMPD5_Pos Ú P PWM_CMPDAT5_CMPD5_Msk Ú P PWM_CMPDAT5_CMPD6_Pos Ú P PWM_CMPDAT5_CMPD6_Msk Ú P PWM_CMPDAT5_CMPD7_Pos Ú P PWM_CMPDAT5_CMPD7_Msk Ú P PWM_CMPDAT6_CMP0_Pos aÚ P PWM_CMPDAT6_CMP0_Msk hÚ P PWM_CMPDAT6_CMP1_Pos `Ú P PWM_CMPDAT6_CMP1_Msk gÚ P PWM_CMPDAT6_CMP2_Pos _Ú P PWM_CMPDAT6_CMP2_Msk fÚ P PWM_CMPDAT6_CMP3_Pos ^Ú P PWM_CMPDAT6_CMP3_Msk eÚ P PWM_CMPDAT6_CMP4_Pos ]Ú P PWM_CMPDAT6_CMP4_Msk dÚ P PWM_CMPDAT6_CMP5_Pos \Ú P PWM_CMPDAT6_CMP5_Msk cÚ P PWM_CMPDAT6_CMP6_Pos [Ú P PWM_CMPDAT6_CMP6_Msk bÚ P PWM_CMPDAT6_CMP7_Pos ZÚ P PWM_CMPDAT6_CMP7_Msk aÚ P PWM_CMPDAT6_CMPD0_Pos Ú P PWM_CMPDAT6_CMPD0_Msk "Ú P PWM_CMPDAT6_CMPD1_Pos Ú P PWM_CMPDAT6_CMPD1_Msk !Ú P PWM_CMPDAT6_CMPD2_Pos Ú P PWM_CMPDAT6_CMPD2_Msk Ú P PWM_CMPDAT6_CMPD3_Pos Ú P PWM_CMPDAT6_CMPD3_Msk Ú P PWM_CMPDAT6_CMPD4_Pos Ú P PWM_CMPDAT6_CMPD4_Msk Ú P PWM_CMPDAT6_CMPD5_Pos Ú P PWM_CMPDAT6_CMPD5_Msk Ú P PWM_CMPDAT6_CMPD6_Pos Ú P PWM_CMPDAT6_CMPD6_Msk Ú P PWM_CMPDAT6_CMPD7_Pos Ú P PWM_CMPDAT6_CMPD7_Msk Ú P PWM_CMPDAT7_CMP0_Pos `Ú P PWM_CMPDAT7_CMP0_Msk gÚ P PWM_CMPDAT7_CMP1_Pos _Ú P PWM_CMPDAT7_CMP1_Msk fÚ P PWM_CMPDAT7_CMP2_Pos ^Ú P PWM_CMPDAT7_CMP2_Msk eÚ P PWM_CMPDAT7_CMP3_Pos ]Ú P PWM_CMPDAT7_CMP3_Msk dÚ P PWM_CMPDAT7_CMP4_Pos \Ú P PWM_CMPDAT7_CMP4_Msk cÚ P PWM_CMPDAT7_CMP5_Pos [Ú P PWM_CMPDAT7_CMP5_Msk bÚ P PWM_CMPDAT7_CMP6_Pos ZÚ P PWM_CMPDAT7_CMP6_Msk aÚ P PWM_CMPDAT7_CMP7_Pos YÚ P PWM_CMPDAT7_CMP7_Msk `Ú P PWM_CMPDAT7_CMPD0_Pos Ú P PWM_CMPDAT7_CMPD0_Msk !Ú P PWM_CMPDAT7_CMPD1_Pos Ú P PWM_CMPDAT7_CMPD1_Msk Ú P PWM_CMPDAT7_CMPD2_Pos Ú P PWM_CMPDAT7_CMPD2_Msk Ú P PWM_CMPDAT7_CMPD3_Pos Ú P PWM_CMPDAT7_CMPD3_Msk Ú P PWM_CMPDAT7_CMPD4_Pos Ú P PWM_CMPDAT7_CMPD4_Msk Ú P PWM_CMPDAT7_CMPD5_Pos Ú P PWM_CMPDAT7_CMPD5_Msk Ú P PWM_CMPDAT7_CMPD6_Pos Ú P PWM_CMPDAT7_CMPD6_Msk Ú P PWM_CMPDAT7_CMPD7_Pos Ú P PWM_CMPDAT7_CMPD7_Msk Ú P PWM_CTL2_BRKIEN_Pos Ú P PWM_CTL2_BRKIEN_Msk Ú P PWM_CTL2_PINTTYPE_Pos ÌÚ P PWM_CTL2_PINTTYPE_Msk ÓÚ P PWM_CTL2_DTCNT01_Pos mÚ P PWM_CTL2_DTCNT01_Msk tÚ P PWM_CTL2_DTCNT23_Pos iÚ P PWM_CTL2_DTCNT23_Msk pÚ P PWM_CTL2_DTCNT45_Pos eÚ P PWM_CTL2_DTCNT45_Msk lÚ P PWM_CTL2_DTCNT67_Pos aÚ P PWM_CTL2_DTCNT67_Msk hÚ P PWM_CTL2_CNTCLR_Pos Ú P PWM_CTL2_CNTCLR_Msk Ú P PWM_CTL2_MODE_Pos ,Ú P PWM_CTL2_MODE_Msk 3Ú P PWM_CTL2_GROUPEN_Pos +Ú P PWM_CTL2_GROUPEN_Msk 2Ú P PWM_CTL2_CNTTYPE_Pos $Ú P PWM_CTL2_CNTTYPE_Msk +Ú P PWM_FLAG_ZF0_Pos ~Ú P PWM_FLAG_ZF0_Msk
Ú P PWM_FLAG_ZF1_Pos }Ú P PWM_FLAG_ZF1_Msk Ú P PWM_FLAG_ZF2_Pos |Ú P PWM_FLAG_ZF2_Msk Ú P PWM_FLAG_ZF3_Pos {Ú P PWM_FLAG_ZF3_Msk Ú P PWM_FLAG_ZF4_Pos zÚ P PWM_FLAG_ZF4_Msk Ú P PWM_FLAG_ZF5_Pos yÚ P PWM_FLAG_ZF5_Msk Ú P PWM_FLAG_ZF6_Pos xÚ P PWM_FLAG_ZF6_Msk Ú P PWM_FLAG_ZF7_Pos wÚ P PWM_FLAG_ZF7_Msk ~Ú P PWM_FLAG_CMPDF0_Pos ®Ú P PWM_FLAG_CMPDF0_Msk µÚ P PWM_FLAG_CMPDF1_Pos Ú P PWM_FLAG_CMPDF1_Msk ´Ú P PWM_FLAG_CMPDF2_Pos ¬Ú P PWM_FLAG_CMPDF2_Msk ³Ú P PWM_FLAG_CMPDF3_Pos «Ú P PWM_FLAG_CMPDF3_Msk ²Ú P PWM_FLAG_CMPDF4_Pos ªÚ P PWM_FLAG_CMPDF4_Msk ±Ú P PWM_FLAG_CMPDF5_Pos ©Ú P PWM_FLAG_CMPDF5_Msk °Ú P PWM_FLAG_CMPDF6_Pos ¨Ú P PWM_FLAG_CMPDF6_Msk ¯Ú P PWM_FLAG_CMPDF7_Pos §Ú P PWM_FLAG_CMPDF7_Msk ®Ú P PWM_FLAG_PF0_Pos Ú P PWM_FLAG_PF0_Msk Ú P PWM_FLAG_PF1_Pos Ú P PWM_FLAG_PF1_Msk Ú P PWM_FLAG_PF2_Pos Ú P PWM_FLAG_PF2_Msk Ú P PWM_FLAG_PF3_Pos
Ú P PWM_FLAG_PF3_Msk Ú P PWM_FLAG_PF4_Pos Ú P PWM_FLAG_PF4_Msk Ú P PWM_FLAG_PF5_Pos Ú P PWM_FLAG_PF5_Msk Ú P PWM_FLAG_PF6_Pos Ú P PWM_FLAG_PF6_Msk Ú P PWM_FLAG_PF7_Pos Ú P PWM_FLAG_PF7_Msk Ú P PWM_FLAG_CMPUF0_Pos Ú P PWM_FLAG_CMPUF0_Msk ¤Ú P PWM_FLAG_CMPUF1_Pos Ú P PWM_FLAG_CMPUF1_Msk £Ú P PWM_FLAG_CMPUF2_Pos Ú P PWM_FLAG_CMPUF2_Msk ¢Ú P PWM_FLAG_CMPUF3_Pos Ú P PWM_FLAG_CMPUF3_Msk ¡Ú P PWM_FLAG_CMPUF4_Pos Ú P PWM_FLAG_CMPUF4_Msk Ú P PWM_FLAG_CMPUF5_Pos Ú P PWM_FLAG_CMPUF5_Msk Ú P PWM_FLAG_CMPUF6_Pos Ú P PWM_FLAG_CMPUF6_Msk Ú P PWM_FLAG_CMPUF7_Pos Ú P PWM_FLAG_CMPUF7_Msk Ú P PWM_INTEN_ZIEN0_Pos ~Ú P PWM_INTEN_ZIEN0_Msk
Ú P PWM_INTEN_ZIEN1_Pos }Ú P PWM_INTEN_ZIEN1_Msk Ú P PWM_INTEN_ZIEN2_Pos |Ú P PWM_INTEN_ZIEN2_Msk Ú P PWM_INTEN_ZIEN3_Pos {Ú P PWM_INTEN_ZIEN3_Msk Ú P PWM_INTEN_ZIEN4_Pos zÚ P PWM_INTEN_ZIEN4_Msk Ú P PWM_INTEN_ZIEN5_Pos yÚ P PWM_INTEN_ZIEN5_Msk Ú P PWM_INTEN_ZIEN6_Pos xÚ P PWM_INTEN_ZIEN6_Msk Ú P PWM_INTEN_ZIEN7_Pos wÚ P PWM_INTEN_ZIEN7_Msk ~Ú P PWM_INTEN_CMPDIEN0_Pos ®Ú P PWM_INTEN_CMPDIEN0_Msk µÚ P PWM_INTEN_CMPDIEN1_Pos Ú P PWM_INTEN_CMPDIEN1_Msk ´Ú P PWM_INTEN_CMPDIEN2_Pos ¬Ú P PWM_INTEN_CMPDIEN2_Msk ³Ú P PWM_INTEN_CMPDIEN3_Pos «Ú P PWM_INTEN_CMPDIEN3_Msk ²Ú P PWM_INTEN_CMPDIEN4_Pos ªÚ P PWM_INTEN_CMPDIEN4_Msk ±Ú P PWM_INTEN_CMPDIEN5_Pos ©Ú P PWM_INTEN_CMPDIEN5_Msk °Ú P PWM_INTEN_CMPDIEN6_Pos ¨Ú P PWM_INTEN_CMPDIEN6_Msk ¯Ú P PWM_INTEN_CMPDIEN7_Pos §Ú P PWM_INTEN_CMPDIEN7_Msk ®Ú P PWM_INTEN_PIEN0_Pos Ú P PWM_INTEN_PIEN0_Msk Ú P PWM_INTEN_PIEN1_Pos Ú P PWM_INTEN_PIEN1_Msk Ú P PWM_INTEN_PIEN2_Pos Ú P PWM_INTEN_PIEN2_Msk Ú P PWM_INTEN_PIEN3_Pos
Ú P PWM_INTEN_PIEN3_Msk Ú P PWM_INTEN_PIEN4_Pos Ú P PWM_INTEN_PIEN4_Msk Ú P PWM_INTEN_PIEN5_Pos Ú P PWM_INTEN_PIEN5_Msk Ú P PWM_INTEN_PIEN6_Pos Ú P PWM_INTEN_PIEN6_Msk Ú P PWM_INTEN_PIEN7_Pos Ú P PWM_INTEN_PIEN7_Msk Ú P PWM_INTEN_CMPUIEN0_Pos Ú P PWM_INTEN_CMPUIEN0_Msk ¤Ú P PWM_INTEN_CMPUIEN1_Pos Ú P PWM_INTEN_CMPUIEN1_Msk £Ú P PWM_INTEN_CMPUIEN2_Pos Ú P PWM_INTEN_CMPUIEN2_Msk ¢Ú P PWM_INTEN_CMPUIEN3_Pos Ú P PWM_INTEN_CMPUIEN3_Msk ¡Ú P PWM_INTEN_CMPUIEN4_Pos Ú P PWM_INTEN_CMPUIEN4_Msk Ú P PWM_INTEN_CMPUIEN5_Pos Ú P PWM_INTEN_CMPUIEN5_Msk Ú P PWM_INTEN_CMPUIEN6_Pos Ú P PWM_INTEN_CMPUIEN6_Msk Ú P PWM_INTEN_CMPUIEN7_Pos Ú P PWM_INTEN_CMPUIEN7_Msk Ú P PWM_INTSTS_ZIF0_Pos dÚ P PWM_INTSTS_ZIF0_Msk kÚ P PWM_INTSTS_ZIF1_Pos cÚ P PWM_INTSTS_ZIF1_Msk jÚ P PWM_INTSTS_ZIF2_Pos bÚ P PWM_INTSTS_ZIF2_Msk iÚ P PWM_INTSTS_ZIF3_Pos aÚ P PWM_INTSTS_ZIF3_Msk hÚ P PWM_INTSTS_ZIF4_Pos `Ú P PWM_INTSTS_ZIF4_Msk gÚ P PWM_INTSTS_ZIF5_Pos _Ú P PWM_INTSTS_ZIF5_Msk fÚ P PWM_INTSTS_ZIF6_Pos ^Ú P PWM_INTSTS_ZIF6_Msk eÚ P PWM_INTSTS_ZIF7_Pos ]Ú P PWM_INTSTS_ZIF7_Msk dÚ P PWM_INTSTS_CMPDIF0_Pos Ú P PWM_INTSTS_CMPDIF0_Msk Ú P PWM_INTSTS_CMPDIF1_Pos Ú P PWM_INTSTS_CMPDIF1_Msk Ú P PWM_INTSTS_CMPDIF2_Pos Ú P PWM_INTSTS_CMPDIF2_Msk Ú P PWM_INTSTS_CMPDIF3_Pos Ú P PWM_INTSTS_CMPDIF3_Msk Ú P PWM_INTSTS_CMPDIF4_Pos Ú P PWM_INTSTS_CMPDIF4_Msk Ú P PWM_INTSTS_CMPDIF5_Pos Ú P PWM_INTSTS_CMPDIF5_Msk Ú P PWM_INTSTS_CMPDIF6_Pos Ú P PWM_INTSTS_CMPDIF6_Msk Ú P PWM_INTSTS_CMPDIF7_Pos Ú P PWM_INTSTS_CMPDIF7_Msk Ú P PWM_INTSTS_PIF0_Pos nÚ P PWM_INTSTS_PIF0_Msk uÚ P PWM_INTSTS_PIF1_Pos mÚ P PWM_INTSTS_PIF1_Msk tÚ P PWM_INTSTS_PIF2_Pos lÚ P PWM_INTSTS_PIF2_Msk sÚ P PWM_INTSTS_PIF3_Pos kÚ P PWM_INTSTS_PIF3_Msk rÚ P PWM_INTSTS_PIF4_Pos jÚ P PWM_INTSTS_PIF4_Msk qÚ P PWM_INTSTS_PIF5_Pos iÚ P PWM_INTSTS_PIF5_Msk pÚ P PWM_INTSTS_PIF6_Pos hÚ P PWM_INTSTS_PIF6_Msk oÚ P PWM_INTSTS_PIF7_Pos gÚ P PWM_INTSTS_PIF7_Msk nÚ P PWM_INTSTS_CMPUIF0_Pos Ú P PWM_INTSTS_CMPUIF0_Msk Ú P PWM_INTSTS_CMPUIF1_Pos Ú P PWM_INTSTS_CMPUIF1_Msk Ú P PWM_INTSTS_CMPUIF2_Pos Ú P PWM_INTSTS_CMPUIF2_Msk Ú P PWM_INTSTS_CMPUIF3_Pos Ú P PWM_INTSTS_CMPUIF3_Msk Ú P PWM_INTSTS_CMPUIF4_Pos Ú P PWM_INTSTS_CMPUIF4_Msk Ú P PWM_INTSTS_CMPUIF5_Pos ~Ú P PWM_INTSTS_CMPUIF5_Msk
Ú P PWM_INTSTS_CMPUIF6_Pos }Ú P PWM_INTSTS_CMPUIF6_Msk Ú P PWM_INTSTS_CMPUIF7_Pos |Ú P PWM_INTSTS_CMPUIF7_Msk Ú P PWM_POEN_POEN0_Pos ÐÚ P PWM_POEN_POEN0_Msk ×Ú P PWM_POEN_POEN1_Pos ÏÚ P PWM_POEN_POEN1_Msk ÖÚ P PWM_POEN_POEN2_Pos ÎÚ P PWM_POEN_POEN2_Msk ÕÚ P PWM_POEN_POEN3_Pos ÍÚ P PWM_POEN_POEN3_Msk ÔÚ P PWM_POEN_POEN4_Pos ÌÚ P PWM_POEN_POEN4_Msk ÓÚ P PWM_POEN_POEN5_Pos ËÚ P PWM_POEN_POEN5_Msk ÒÚ P PWM_POEN_POEN6_Pos ÊÚ P PWM_POEN_POEN6_Msk ÑÚ P PWM_POEN_POEN7_Pos ÉÚ P PWM_POEN_POEN7_Msk ÐÚ P PWM_BRKCTL_BRK0EN_Pos úÚ P PWM_BRKCTL_BRK0EN_Msk Ú P PWM_BRKCTL_BRK1EN_Pos ùÚ P PWM_BRKCTL_BRK1EN_Msk Ú P PWM_BRKCTL_BRK0SEL_Pos §Ú P PWM_BRKCTL_BRK0SEL_Msk ®Ú P PWM_BRKCTL_BRK1SEL_Pos ¦Ú P PWM_BRKCTL_BRK1SEL_Msk Ú P PWM_BRKCTL_BRKSTS_Pos ÃÚ P PWM_BRKCTL_BRKSTS_Msk ÊÚ P PWM_BRKCTL_BRKACT_Pos åÚ P PWM_BRKCTL_BRKACT_Msk ìÚ P PWM_BRKCTL_SWBRK_Pos Ú P PWM_BRKCTL_SWBRK_Msk Ú P PWM_BRKCTL_BRKIF0_Pos þÚ P PWM_BRKCTL_BRKIF0_Msk Ú P PWM_BRKCTL_BRKIF1_Pos ýÚ P PWM_BRKCTL_BRKIF1_Msk Ú P PWM_BRKCTL_BRKF0_Pos IÚ P PWM_BRKCTL_BRKF0_Msk PÚ P PWM_BRKCTL_BRKF1_Pos HÚ P PWM_BRKCTL_BRKF1_Msk OÚ P PWM_BRKCTL_BKOD0_Pos NÚ P PWM_BRKCTL_BKOD0_Msk UÚ P PWM_BRKCTL_BKOD1_Pos MÚ P PWM_BRKCTL_BKOD1_Msk TÚ P PWM_BRKCTL_BKOD2_Pos LÚ P PWM_BRKCTL_BKOD2_Msk SÚ P PWM_BRKCTL_BKOD3_Pos KÚ P PWM_BRKCTL_BKOD3_Msk RÚ P PWM_BRKCTL_BKOD4_Pos JÚ P PWM_BRKCTL_BKOD4_Msk QÚ P PWM_BRKCTL_BKOD5_Pos IÚ P PWM_BRKCTL_BKOD5_Msk PÚ P PWM_BRKCTL_D6BKOD_Pos Ú P PWM_BRKCTL_D6BKOD_Msk Ú P PWM_BRKCTL_D7BKOD_Pos Ú P PWM_BRKCTL_D7BKOD_Msk Ú P PWM_DTCTL_DTI01_Pos ¥Ú P PWM_DTCTL_DTI01_Msk ¬Ú P PWM_DTCTL_DTI23_Pos ¡Ú P PWM_DTCTL_DTI23_Msk ¨Ú P PWM_DTCTL_DTI45_Pos Ú P PWM_DTCTL_DTI45_Msk ¤Ú P PWM_DTCTL_DTI67_Pos Ú P PWM_DTCTL_DTI67_Msk Ú" P PWM_ADCTCTL0_CUTRGEN0_Pos ßÚ" P PWM_ADCTCTL0_CUTRGEN0_Msk æÚ" P PWM_ADCTCTL0_CPTRGEN0_Pos äÚ" P PWM_ADCTCTL0_CPTRGEN0_Msk ëÚ" P PWM_ADCTCTL0_CDTRGEN0_Pos ðÚ" P PWM_ADCTCTL0_CDTRGEN0_Msk ÷Ú" P PWM_ADCTCTL0_ZPTRGEN0_Pos ÍÚ" P PWM_ADCTCTL0_ZPTRGEN0_Msk ÔÚ" P PWM_ADCTCTL0_CUTRGEN1_Pos ÞÚ" P PWM_ADCTCTL0_CUTRGEN1_Msk åÚ" P PWM_ADCTCTL0_CPTRGEN1_Pos ãÚ" P PWM_ADCTCTL0_CPTRGEN1_Msk êÚ" P PWM_ADCTCTL0_CDTRGEN1_Pos ïÚ" P PWM_ADCTCTL0_CDTRGEN1_Msk öÚ" P PWM_ADCTCTL0_ZPTRGEN1_Pos ÌÚ" P PWM_ADCTCTL0_ZPTRGEN1_Msk ÓÚ" P PWM_ADCTCTL0_CUTRGEN2_Pos ÝÚ" P PWM_ADCTCTL0_CUTRGEN2_Msk äÚ" P PWM_ADCTCTL0_CPTRGEN2_Pos âÚ" P PWM_ADCTCTL0_CPTRGEN2_Msk éÚ" P PWM_ADCTCTL0_CDTRGEN2_Pos îÚ" P PWM_ADCTCTL0_CDTRGEN2_Msk õÚ" P PWM_ADCTCTL0_ZPTRGEN2_Pos ËÚ" P PWM_ADCTCTL0_ZPTRGEN2_Msk ÒÚ" P PWM_ADCTCTL0_CUTRGEN3_Pos ÜÚ" P PWM_ADCTCTL0_CUTRGEN3_Msk ãÚ" P PWM_ADCTCTL0_CPTRGEN3_Pos áÚ" P PWM_ADCTCTL0_CPTRGEN3_Msk èÚ" P PWM_ADCTCTL0_CDTRGEN3_Pos íÚ" P PWM_ADCTCTL0_CDTRGEN3_Msk ôÚ" P PWM_ADCTCTL0_ZPTRGEN3_Pos ÊÚ" P PWM_ADCTCTL0_ZPTRGEN3_Msk ÑÚ" P PWM_ADCTCTL1_CUTRGEN4_Pos ÚÚ" P PWM_ADCTCTL1_CUTRGEN4_Msk áÚ" P PWM_ADCTCTL1_CPTRGEN4_Pos ßÚ" P PWM_ADCTCTL1_CPTRGEN4_Msk æÚ" P PWM_ADCTCTL1_CDTRGEN4_Pos ëÚ" P PWM_ADCTCTL1_CDTRGEN4_Msk òÚ" P PWM_ADCTCTL1_ZPTRGEN4_Pos ÈÚ" P PWM_ADCTCTL1_ZPTRGEN4_Msk ÏÚ" P PWM_ADCTCTL1_CUTRGEN5_Pos ÙÚ" P PWM_ADCTCTL1_CUTRGEN5_Msk àÚ" P PWM_ADCTCTL1_CPTRGEN5_Pos ÞÚ" P PWM_ADCTCTL1_CPTRGEN5_Msk åÚ" P PWM_ADCTCTL1_CDTRGEN5_Pos êÚ" P PWM_ADCTCTL1_CDTRGEN5_Msk ñÚ" P PWM_ADCTCTL1_ZPTRGEN5_Pos ÇÚ" P PWM_ADCTCTL1_ZPTRGEN5_Msk ÎÚ" P PWM_ADCTCTL1_CUTRGEN6_Pos ØÚ" P PWM_ADCTCTL1_CUTRGEN6_Msk ßÚ" P PWM_ADCTCTL1_CPTRGEN6_Pos ÝÚ" P PWM_ADCTCTL1_CPTRGEN6_Msk äÚ" P PWM_ADCTCTL1_CDTRGEN6_Pos éÚ" P PWM_ADCTCTL1_CDTRGEN6_Msk ðÚ" P PWM_ADCTCTL1_ZPTRGEN6_Pos ÆÚ" P PWM_ADCTCTL1_ZPTRGEN6_Msk ÍÚ" P PWM_ADCTCTL1_CUTRGEN7_Pos ×Ú" P PWM_ADCTCTL1_CUTRGEN7_Msk ÞÚ" P PWM_ADCTCTL1_CPTRGEN7_Pos ÜÚ" P PWM_ADCTCTL1_CPTRGEN7_Msk ãÚ" P PWM_ADCTCTL1_CDTRGEN7_Pos èÚ" P PWM_ADCTCTL1_CDTRGEN7_Msk ïÚ" P PWM_ADCTCTL1_ZPTRGEN7_Pos ÅÚ" P PWM_ADCTCTL1_ZPTRGEN7_Msk ÌÚ! P PWM_ADCTSTS0_CUTRGF0_Pos Ú! P PWM_ADCTSTS0_CUTRGF0_Msk Ú! P PWM_ADCTSTS0_CPTRGF0_Pos Ú! P PWM_ADCTSTS0_CPTRGF0_Msk #Ú! P PWM_ADCTSTS0_CDTRGF0_Pos (Ú! P PWM_ADCTSTS0_CDTRGF0_Msk /Ú! P PWM_ADCTSTS0_ZPTRGF0_Pos Ú! P PWM_ADCTSTS0_ZPTRGF0_Msk Ú! P PWM_ADCTSTS0_CUTRGF1_Pos Ú! P PWM_ADCTSTS0_CUTRGF1_Msk Ú! P PWM_ADCTSTS0_CPTRGF1_Pos Ú! P PWM_ADCTSTS0_CPTRGF1_Msk "Ú! P PWM_ADCTSTS0_CDTRGF1_Pos 'Ú! P PWM_ADCTSTS0_CDTRGF1_Msk .Ú! P PWM_ADCTSTS0_ZPTRGF1_Pos Ú! P PWM_ADCTSTS0_ZPTRGF1_Msk Ú! P PWM_ADCTSTS0_CUTRGF2_Pos Ú! P PWM_ADCTSTS0_CUTRGF2_Msk Ú! P PWM_ADCTSTS0_CPTRGF2_Pos Ú! P PWM_ADCTSTS0_CPTRGF2_Msk !Ú! P PWM_ADCTSTS0_CDTRGF2_Pos &Ú! P PWM_ADCTSTS0_CDTRGF2_Msk -Ú! P PWM_ADCTSTS0_ZPTRGF2_Pos Ú! P PWM_ADCTSTS0_ZPTRGF2_Msk
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Ú! P PWM_ADCTSTS0_CUTRGF3_Pos Ú! P PWM_ADCTSTS0_CUTRGF3_Msk Ú! P PWM_ADCTSTS0_CPTRGF3_Pos Ú! P PWM_ADCTSTS0_CPTRGF3_Msk Ú! P PWM_ADCTSTS0_CDTRGF3_Pos %Ú! P PWM_ADCTSTS0_CDTRGF3_Msk ,Ú! P PWM_ADCTSTS0_ZPTRGF3_Pos Ú! P PWM_ADCTSTS0_ZPTRGF3_Msk Ú! P PWM_ADCTSTS1_CUTRGF4_Pos Ú! P PWM_ADCTSTS1_CUTRGF4_Msk Ú! P PWM_ADCTSTS1_CPTRGF4_Pos Ú! P PWM_ADCTSTS1_CPTRGF4_Msk Ú! P PWM_ADCTSTS1_CDTRGF4_Pos #Ú! P PWM_ADCTSTS1_CDTRGF4_Msk *Ú! P PWM_ADCTSTS1_ZPTRGF4_Pos Ú! P PWM_ADCTSTS1_ZPTRGF4_Msk Ú! P PWM_ADCTSTS1_CUTRGF5_Pos Ú! P PWM_ADCTSTS1_CUTRGF5_Msk Ú! P PWM_ADCTSTS1_CPTRGF5_Pos Ú! P PWM_ADCTSTS1_CPTRGF5_Msk Ú! P PWM_ADCTSTS1_CDTRGF5_Pos "Ú! P PWM_ADCTSTS1_CDTRGF5_Msk )Ú! P PWM_ADCTSTS1_ZPTRGF5_Pos ÿÚ! P PWM_ADCTSTS1_ZPTRGF5_Msk Ú! P PWM_ADCTSTS1_CUTRGF6_Pos Ú! P PWM_ADCTSTS1_CUTRGF6_Msk Ú! P PWM_ADCTSTS1_CPTRGF6_Pos Ú! P PWM_ADCTSTS1_CPTRGF6_Msk Ú! P PWM_ADCTSTS1_CDTRGF6_Pos !Ú! P PWM_ADCTSTS1_CDTRGF6_Msk (Ú! P PWM_ADCTSTS1_ZPTRGF6_Pos þÚ! P PWM_ADCTSTS1_ZPTRGF6_Msk Ú! P PWM_ADCTSTS1_CUTRGF7_Pos Ú! P PWM_ADCTSTS1_CUTRGF7_Msk Ú! P PWM_ADCTSTS1_CPTRGF7_Pos Ú! P PWM_ADCTSTS1_CPTRGF7_Msk Ú! P PWM_ADCTSTS1_CDTRGF7_Pos Ú! P PWM_ADCTSTS1_CDTRGF7_Msk 'Ú! P PWM_ADCTSTS1_ZPTRGF7_Pos ýÚ! P PWM_ADCTSTS1_ZPTRGF7_Msk Ú P PWM_PCACTL_PCAEN_Pos BÚ P PWM_PCACTL_PCAEN_Msk IÚ 8
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<unnamed> QÚ
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" ð X_FL_CTL &Ú " ð
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X_FL_TRIG ØÚ " ð X_FL_CONFIG TÚ <" ðX_FL_WD <Ú
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" ð X_FL_X_MODE 'Ú " ð X_FL_X2_CMD MÚ " ð X_FL_X4_CMD KÚ " ð X_FL_DP_CMD CÚ " ð X_FL_RDP_CMD ïÚ
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" ðX_FL_REMAP_ADDR Ú
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" ð X_FL_DP_CTL -Ú
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" ð X_FL_IRQ_CTL ÓÚ
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" ðX_FL_SUS_RESU_CMD +Ú FLCTL_T ËÚ 8
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<unnamed> QÚ <" ÿ X_FL_BUFFER Ú FLCTL_W_BUFF_T
Ú" P FLCTL_CTL_BYTES_NUM_R_Pos kÚ" P FLCTL_CTL_BYTES_NUM_R_Msk rÚ" P FLCTL_CTL_BYTES_NUM_W_Pos fÚ" P FLCTL_CTL_BYTES_NUM_W_Msk mÚ P FLCTL_TRIG_TRG_Pos ÀÚ P FLCTL_TRIG_TRG_Msk ÇÚ# P FLCTL_CONFIG_FLASH_CAP_Pos |Ú# P FLCTL_CONFIG_FLASH_CAP_Msk Ú' P FLCTL_CONFIG_TX_ADDR_TRANS_Pos Ú' P FLCTL_CONFIG_TX_ADDR_TRANS_Msk Ú! P FLCTL_CONFIG_INFO_EN_Pos Ú! P FLCTL_CONFIG_INFO_EN_Msk
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Ú# P FLCTL_CONFIG_PP_ACTIVE_Pos bÚ# P FLCTL_CONFIG_PP_ACTIVE_Msk iÚ P FLCTL_W_DATA_Pos vÚ P FLCTL_W_DATA_Msk }Ú% P FLCTL_X_MODE_TIMEOUT_CNT_Pos Ú% P FLCTL_X_MODE_TIMEOUT_CNT_Msk Ú# P FLCTL_X_MODE_RESUME_EN_Pos 4Ú# P FLCTL_X_MODE_RESUME_EN_Msk ;Ú% P FLCTL_X_MODE_SUS_SUCCESS_Pos Ú% P FLCTL_X_MODE_SUS_SUCCESS_Msk Ú! P FLCTL_X_MODE_CLK_DLY_Pos ÙÚ! P FLCTL_X_MODE_CLK_DLY_Msk àÚ P FLCTL_X_MODE_RX_NEG_Pos Ú P FLCTL_X_MODE_RX_NEG_Msk !Ú" P FLCTL_X_MODE_CRC32_EN_Pos ÊÚ" P FLCTL_X_MODE_CRC32_EN_Msk ÑÚ& P FLCTL_X_MODE_ENHANCE_MODE_Pos {Ú& P FLCTL_X_MODE_ENHANCE_MODE_Msk Ú& P FLCTL_X_MODE_LONG_TIME_OP_Pos 5Ú& P FLCTL_X_MODE_LONG_TIME_OP_Msk <Ú' P FLCTL_X_MODE_EN_BURST_WRAP_Pos ÔÚ' P FLCTL_X_MODE_EN_BURST_WRAP_Msk ÛÚ' P FLCTL_X_MODE_CS_IDLE_CYCLE_Pos Ú' P FLCTL_X_MODE_CS_IDLE_CYCLE_Msk Ú P FLCTL_X_MODE_X_MODE_Pos !Ú P FLCTL_X_MODE_X_MODE_Msk (Ú P FLCTL_X2_CMD_Pos Ú P FLCTL_X2_CMD_Msk Ú P FLCTL_X4_CMD_Pos Ú P FLCTL_X4_CMD_Msk Ú P FLCTL_DP_CMD_Pos Ú P FLCTL_DP_CMD_Msk Ú P FLCTL_RDP_CMD_Pos +Ú P FLCTL_RDP_CMD_Msk 2Ú P FLCTL_REMAP_ADDR_Pos OÚ P FLCTL_REMAP_ADDR_Msk VÚ$ P FLCTL_DP_CTL_RDP_WT_CNT_Pos ÇÚ$ P FLCTL_DP_CTL_RDP_WT_CNT_Msk ÎÚ# P FLCTL_DP_CTL_DP_WT_CNT_Pos Ú# P FLCTL_DP_CTL_DP_WT_CNT_Msk "Ú P FLCTL_DP_CTL_DP_EN_Pos Ú P FLCTL_DP_CTL_DP_EN_Msk Ú" P FLCTL_PROGRAM_SUS_CMD_Pos Ú" P FLCTL_PROGRAM_SUS_CMD_Msk Ú% P FLCTL_PROGRAM_RESUME_CMD_Pos ³Ú% P FLCTL_PROGRAM_RESUME_CMD_Msk ºÚ P FLCTL_ERASE_SUS_CMD_Pos ;Ú P FLCTL_ERASE_SUS_CMD_Msk BÚ# P FLCTL_ERASE_RESUME_CMD_Pos _Ú# P FLCTL_ERASE_RESUME_CMD_Msk fÚ 8
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<unnamed> QÚ
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" À X_CACHE_EN ßÚ
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" ÀX_RESVR Ú
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" À X_CACHE_INI Ú CR_T ±Ú 8
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<unnamed> QÚ
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" ÅCR0 Ú
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" ÅCR1 Ú
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" ÅDR QÚ
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" ÅSR BÚ
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" ÅCPSR «Ú
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" ÅIMSC ·Ú
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" ÅRIS ÷Ú
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" ÅMIS üÚ
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" ÅICR Ú
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" ÅDMACR zÚ SPI_T XÚ P SPI_CR0_SCR_Pos ÅÚ P SPI_CR0_SCR_Msk ÌÚ P SPI_CR0_SPH_Pos ÂÚ P SPI_CR0_SPH_Msk ÉÚ P SPI_CR0_SPO_Pos »Ú P SPI_CR0_SPO_Msk ÂÚ P SPI_CR0_FRF_Pos ÏÚ P SPI_CR0_FRF_Msk ÖÚ P SPI_CR0_DSS_Pos ÃÚ P SPI_CR0_DSS_Msk ÊÚ! P SPI_CR1_SPI_MODE_SEL_Pos çÚ! P SPI_CR1_SPI_MODE_SEL_Msk îÚ P SPI_CR1_CMD_DAT_EN_Pos Ú P SPI_CR1_CMD_DAT_EN_Msk §Ú! P SPI_CR1_CMD_DAT_CTRL_Pos úÚ! P SPI_CR1_CMD_DAT_CTRL_Msk Ú P SPI_CR1_WR_CTRL_Pos gÚ P SPI_CR1_WR_CTRL_Msk nÚ P SPI_CR1_RX_LSB_EN_Pos ÄÚ P SPI_CR1_RX_LSB_EN_Msk ËÚ P SPI_CR1_TX_LSB_EN_Pos ÂÚ P SPI_CR1_TX_LSB_EN_Msk ÉÚ P SPI_CR1_SOD_Pos ÆÚ P SPI_CR1_SOD_Msk ÍÚ P SPI_CR1_MS_Pos Ú P SPI_CR1_MS_Msk Ú P SPI_CR1_SSE_Pos ÁÚ P SPI_CR1_SSE_Msk ÈÚ P SPI_CR1_LBM_Pos ÑÚ P SPI_CR1_LBM_Msk ØÚ P SPI_DR_Pos EÚ P SPI_DR_Msk LÚ P SPI_SR_BUSY_Pos Ú P SPI_SR_BUSY_Msk Ú P SPI_SR_RFF_Pos ñÚ P SPI_SR_RFF_Msk øÚ P SPI_SR_RFNE_Pos ¢Ú P SPI_SR_RFNE_Msk ©Ú P SPI_SR_TFNF_Pos Ú P SPI_SR_TFNF_Msk ¦Ú P SPI_SR_TFE_Pos ðÚ P SPI_SR_TFE_Msk ÷Ú P SPI_CPSR_DIV_Pos UÚ P SPI_CPSR_DIV_Msk \Ú P SPI_IMSC_TXIM_Pos Ú P SPI_IMSC_TXIM_Msk Ú P SPI_IMSC_RXIM_Pos Ú P SPI_IMSC_RXIM_Msk Ú P SPI_IMSC_RTIM_Pos Ú P SPI_IMSC_RTIM_Msk Ú P SPI_RIS_TXIS_Pos :Ú P SPI_RIS_TXIS_Msk AÚ P SPI_RIS_RXIS_Pos <Ú P SPI_RIS_RXIS_Msk CÚ P SPI_RIS_RTIS_Pos @Ú P SPI_RIS_RTIS_Msk GÚ P SPI_RIS_RORIS_Pos ñÚ P SPI_RIS_RORIS_Msk øÚ P SPI_MIS_TXMIS_Pos ðÚ P SPI_MIS_TXMIS_Msk ÷Ú P SPI_MIS_RXMIS_Pos òÚ P SPI_MIS_RXMIS_Msk ùÚ P SPI_MIS_RTMIS_Pos öÚ P SPI_MIS_RTMIS_Msk ýÚ P SPI_MIS_RORMIS_Pos §Ú P SPI_MIS_RORMIS_Msk ®Ú P SPI_ICR_RTICR_Pos Ú P SPI_ICR_RTICR_Msk Ú P SPI_ICR_RORICR_Pos ½Ú P SPI_ICR_RORICR_Msk ÄÚ P SPI_DMACR_TDMAE_Pos Ú P SPI_DMACR_TDMAE_Msk Ú P SPI_DMACR_RDMAE_Pos Ú P SPI_DMACR_RDMAE_Msk ¡Ú 8
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<unnamed> QÚ
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" RBR_THR_DLL Ú
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" IER_DLH ïÚ
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" IIR_FCR èÚ
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" LCR -Ú
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" MCR ,Ú
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" LSR Ú
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" MSR Ú
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" SCR &Ú
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" LPDLL Ú
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" LPDLH Ú <" T
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RESERVED0 ðÚ
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" USR Ú
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" TFL (Ú
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" RFL *Ú <"
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RESERVED1 'Ú
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" HTX Ú
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" DMASA ¤Ú <"
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RESERVED2 .Ú
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" DLF 8Ú
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" RAR )Ú
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" TAR 'Ú
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" LCR_EXT ÕÚ UART_T Ú P UART_RBR_MSB9_Pos Ú P UART_RBR_MSB9_Msk $Ú P UART_RBR_DAT_Pos aÚ P UART_RBR_DAT_Msk hÚ P UART_THR_MSB9_Pos Ú P UART_THR_MSB9_Msk Ú P UART_THR_DAT_Pos YÚ P UART_THR_DAT_Msk `Ú P UART_DLH_Pos ¯Ú P UART_DLH_Msk ¶Ú P UART_DLL_Pos «Ú P UART_DLL_Msk ²Ú P UART_IER_EPTI_Pos Ú P UART_IER_EPTI_Msk Ú P UART_IER_EMSI_Pos Ú P UART_IER_EMSI_Msk Ú P UART_IER_ERLSI_Pos ½Ú P UART_IER_ERLSI_Msk ÄÚ P UART_IER_ETHREI_Pos yÚ P UART_IER_ETHREI_Msk Ú P UART_IER_ERDAI_Pos ×Ú P UART_IER_ERDAI_Msk ÞÚ P UART_IER_ALL_IRQ_Pos Ú P UART_IER_ALL_IRQ_Msk Ú P UART_IIR_FIFOSE_Pos zÚ P UART_IIR_FIFOSE_Msk Ú P UART_IIR_IID_Pos fÚ P UART_IIR_IID_Msk mÚ P UART_FCR_RT_Pos ¡Ú P UART_FCR_RT_Msk ¨Ú P UART_FCR_TET_Pos XÚ P UART_FCR_TET_Msk _Ú P UART_FCR_DMAM_Pos $Ú P UART_FCR_DMAM_Msk +Ú P UART_FCR_XFIFOR_Pos qÚ P UART_FCR_XFIFOR_Msk xÚ P UART_FCR_RFIFOR_Pos wÚ P UART_FCR_RFIFOR_Msk ~Ú P UART_FCR_FIFOE_Pos ØÚ P UART_FCR_FIFOE_Msk ßÚ P UART_LCR_DLAB_Pos *Ú P UART_LCR_DLAB_Msk 1Ú P UART_LCR_BC_Pos ¼Ú P UART_LCR_BC_Msk ÃÚ P UART_LCR_SP_Pos Ú P UART_LCR_SP_Msk ¥Ú P UART_LCR_EPS_Pos WÚ P UART_LCR_EPS_Msk ^Ú P UART_LCR_PEN_Pos \Ú P UART_LCR_PEN_Msk cÚ P UART_LCR_STOP_Pos ÷Ú P UART_LCR_STOP_Msk þÚ P UART_LCR_DLS_Pos \Ú P UART_LCR_DLS_Msk cÚ P UART_MCR_SIRE_Pos Ú P UART_MCR_SIRE_Msk Ú P UART_MCR_AFCE_Pos -Ú P UART_MCR_AFCE_Msk 4Ú P UART_MCR_LB_Pos ²Ú P UART_MCR_LB_Msk ¹Ú P UART_MCR_OUT2_Pos Ú P UART_MCR_OUT2_Msk Ú P UART_MCR_OUT1_Pos Ú P UART_MCR_OUT1_Msk Ú P UART_MCR_RTS_Pos EÚ P UART_MCR_RTS_Msk LÚ P UART_MCR_DTR_Pos TÚ P UART_MCR_DTR_Msk [Ú P UART_LSR_ADDR_RCVD_Pos zÚ P UART_LSR_ADDR_RCVD_Msk Ú P UART_LSR_RFE_Pos RÚ P UART_LSR_RFE_Msk YÚ P UART_LSR_TEMT_Pos óÚ P UART_LSR_TEMT_Msk úÚ P UART_LSR_THRE_Pos úÚ P UART_LSR_THRE_Msk Ú P UART_LSR_BI_Pos ¦Ú P UART_LSR_BI_Msk Ú P UART_LSR_FE_Pos ¦Ú P UART_LSR_FE_Msk Ú P UART_LSR_PE_Pos Ú P UART_LSR_PE_Msk £Ú P UART_LSR_OE_Pos Ú P UART_LSR_OE_Msk ¤Ú P UART_LSR_DR_Pos Ú P UART_LSR_DR_Msk ¢Ú! P UART_LSR_LINE_STATUS_Pos ´Ú! P UART_LSR_LINE_STATUS_Msk »Ú P UART_MSR_DCD_Pos cÚ P UART_MSR_DCD_Msk jÚ P UART_MSR_RI_Pos Ú P UART_MSR_RI_Msk Ú P UART_MSR_DSR_Pos EÚ P UART_MSR_DSR_Msk LÚ P UART_MSR_CTS_Pos DÚ P UART_MSR_CTS_Msk KÚ P UART_MSR_DDCD_Pos Ú P UART_MSR_DDCD_Msk $Ú P UART_MSR_TERI_Pos øÚ P UART_MSR_TERI_Msk ÿÚ P UART_MSR_DDSR_Pos ÿÚ P UART_MSR_DDSR_Msk Ú P UART_MSR_DCTS_Pos þÚ P UART_MSR_DCTS_Msk Ú" P UART_MSR_MODEM_STATUS_Pos gÚ" P UART_MSR_MODEM_STATUS_Msk nÚ P UART_SCR_Pos Ú P UART_SCR_Msk ¦Ú P UART_LPDLL_Pos Ú P UART_LPDLL_Msk Ú P UART_LPDLH_Pos Ú P UART_LPDLH_Msk Ú P UART_USR_RFF_Pos HÚ P UART_USR_RFF_Msk OÚ P UART_USR_RFNE_Pos ùÚ P UART_USR_RFNE_Msk Ú P UART_USR_TFE_Pos GÚ P UART_USR_TFE_Msk NÚ P UART_USR_TFNF_Pos öÚ P UART_USR_TFNF_Msk ýÚ P UART_TFL_Pos ¡Ú P UART_TFL_Msk ¨Ú P UART_RFL_Pos £Ú P UART_RFL_Msk ªÚ P UART_DMASA_Pos Ú P UART_DMASA_Msk $Ú P UART_DLF_Pos ±Ú P UART_DLF_Msk ¸Ú P UART_RAR_Pos ¢Ú P UART_RAR_Msk ©Ú P UART_TAR_Pos Ú P UART_TAR_Msk §Ú' P UART_LCR_EXT_TRANSMIT_MODE_Pos ÝÚ' P UART_LCR_EXT_TRANSMIT_MODE_Msk äÚ# P UART_LCR_EXT_SEND_ADDR_Pos 7Ú# P UART_LCR_EXT_SEND_ADDR_Msk >Ú$ P UART_LCR_EXT_ADDR_MATCH_Pos òÚ$ P UART_LCR_EXT_ADDR_MATCH_Msk ùÚ P UART_LCR_EXT_DLS_E_Pos \Ú P UART_LCR_EXT_DLS_E_Msk cÚ P UART_DR_OE Ú P UART_DR_BE Ú P UART_DR_PE Ú P UART_DR_FE Ú P UART_DR_DATA Ú P UART_RSCR_OE ëÚ P UART_RSCR_BE øÚ P UART_RSCR_PE êÚ P UART_RSCR_FE ôÚ P UART_RSCR_CLR_ERR LÚ P UART_STATUS_RI 6Ú P UART_STATUS_TXFE Ú P UART_STATUS_RXFF Ú P UART_STATUS_TXFF Ú P UART_STATUS_RXFE Ú P UART_STATUS_BUSY Ú P UART_STATUS_DCD Ú P UART_STATUS_DSR æÚ P UART_STATUS_CTS åÚ P UART_IRDA_LP_DIV ³Ú P UART_BRD_IBRD ¾Ú P UART_BRD_FBRD ÁÚ P UART_LC_CLEAR_MSK oÚ P UART_LC_SPS 6Ú P UART_LC_WLEN ôÚ P UART_LC_FEN SÚ P UART_LC_STP2 Ú P UART_LC_EPS DÚ P UART_LC_PEN IÚ P UART_LC_BRK MÚ P UART_CR_CLEAR_MSK iÚ P UART_CR_CTSEN ¥Ú P UART_CR_RTSEN Ú P UART_CR_OUT2 úÚ P UART_CR_OUT1 ûÚ P UART_CR_RTS -Ú P UART_CR_DTR <Ú P UART_CR_RXE 7Ú P UART_CR_TXE 5Ú P UART_CR_LBE SÚ P UART_CR_SIRLP Ú P UART_CR_SIREN ¡Ú P UART_CR_UARTEN QÚ P UART_INT_FIFO_RXIFLSEL ÎÚ P UART_INT_FIFO_TXIFLSEL ÌÚ P UART_INT_MSK_OEIM PÚ P UART_INT_MSK_BEIM ]Ú P UART_INT_MSK_PEIM OÚ P UART_INT_MSK_FEIM YÚ P UART_INT_MSK_RTIM >Ú P UART_INT_MSK_TXIM 8Ú P UART_INT_MSK_RXIM :Ú P UART_INT_MSK_DSRMIM ªÚ P UART_INT_MSK_DCDMIM ÈÚ P UART_INT_MSK_CTSMIM ©Ú P UART_INT_MSK_RIMIM úÚ P UART_RAW_INT_MSK_OEIM ÿÚ P UART_RAW_INT_MSK_BEIM Ú P UART_RAW_INT_MSK_PEIM þÚ P UART_RAW_INT_MSK_FEIM Ú P UART_RAW_INT_MSK_RTIM íÚ P UART_RAW_INT_MSK_TXIM çÚ P UART_RAW_INT_MSK_RXIM éÚ P UART_RAW_INT_MSK_DSRMIM YÚ P UART_RAW_INT_MSK_DCDMIM wÚ P UART_RAW_INT_MSK_CTSMIM XÚ P UART_RAW_INT_MSK_RIMIM ©Ú" P UART_MASKED_INT_STAT_OEIM ÛÚ" P UART_MASKED_INT_STAT_BEIM èÚ" P UART_MASKED_INT_STAT_PEIM ÚÚ" P UART_MASKED_INT_STAT_FEIM äÚ" P UART_MASKED_INT_STAT_RTIM ÉÚ" P UART_MASKED_INT_STAT_TXIM ÃÚ" P UART_MASKED_INT_STAT_RXIM ÅÚ$ P UART_MASKED_INT_STAT_DSRMIM 5Ú$ P UART_MASKED_INT_STAT_DCDMIM SÚ$ P UART_MASKED_INT_STAT_CTSMIM 4Ú# P UART_MASKED_INT_STAT_RIMIM
Ú P UART_CLR_INT_OEIM ZÚ P UART_CLR_INT_BEIM gÚ P UART_CLR_INT_PEIM YÚ P UART_CLR_INT_FEIM cÚ P UART_CLR_INT_RTIM HÚ P UART_CLR_INT_TXIM BÚ P UART_CLR_INT_RXIM DÚ P UART_CLR_INT_DSRMIM ´Ú P UART_CLR_INT_DCDMIM ÒÚ P UART_CLR_INT_CTSMIM ³Ú P UART_CLR_INT_RIMIM Ú P UART_DMA_CR_DMAONERR Ú P UART_DMA_CR_TXDMAE $Ú P UART_DMA_CR_RXDMAE &Ú 8
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<unnamed> QÚ 8
|
<unnamed> QÚ
|
" SAR_L vÚ
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" SAR_H zÚ
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" DAR_L
Ú
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" DAR_H Ú <"
|
RESERVED0 9Ú
|
" CTL_L yÚ
|
" CTL_H }Ú <"
|
RESERVED1 Ú
|
" CFG_L Ú
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" CFG_H Ú
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" SGR_L pÚ
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" SGR_H tÚ
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" DSR_L sÚ
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" DSR_H wÚ <" À CH Ú
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"
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RAW_TFR_L Ú
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"
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RAW_TFR_H $Ú
|
" RAW_BLOCK_L Ú
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" RAW_BLOCK_H ¡Ú
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" RAW_SRCTRAN_L çÚ
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" RAW_SRCTRAN_H ëÚ
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" RAW_DSTTRAN_L äÚ
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" RAW_DSTTRAN_H èÚ
|
"
|
RAW_ERR_L #Ú
|
"
|
RAW_ERR_H 'Ú
|
" STATUS_TFR_L Ú
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" STATUS_TFR_H $Ú
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" STATUS_BLOCK_L Ú
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" STATUS_BLOCK_H ¡Ú
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" STATUS_SRCTRAN_L çÚ
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" STATUS_SRCTRAN_H ëÚ
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" STATUS_DSTTRAN_L äÚ
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" STATUS_DSTTRAN_H èÚ
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" STATUS_ERR_L #Ú
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" STATUS_ERR_H 'Ú
|
"
|
MSK_TFR_L Ú
|
"
|
MSK_TFR_H #Ú
|
" MSK_BLOCK_L Ú
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" MSK_BLOCK_H Ú
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" MSK_SRCTRAN_L æÚ
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" MSK_SRCTRAN_H êÚ
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" MSK_DSTTRAN_L ãÚ
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" MSK_DSTTRAN_H çÚ
|
"
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MSK_ERR_L "Ú
|
"
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MSK_ERR_H &Ú
|
" CLEAR_TFR_L Ú
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" CLEAR_TFR_H £Ú
|
" CLEAR_BLOCK_L Ú
|
" CLEAR_BLOCK_H Ú
|
" CLEAR_SRCTRAN_L fÚ
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" CLEAR_SRCTRAN_H jÚ
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" CLEAR_DSTTRAN_L cÚ
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" CLEAR_DSTTRAN_H gÚ
|
" CLEAR_ERR_L ¢Ú
|
" CLEAR_ERR_H ¦Ú
|
" STATUS_INT_L !Ú
|
" STATUS_INT_H %Ú <" 0
|
RESERVED3 Ú
|
" DMA_CFG_REG_L Ú
|
" DMA_CFG_REG_H Ú
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" CH_EN_REG_L Ú
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" CH_EN_REG_H Ú DMA_T rÚ$ P DMAC_DMACFGREG_L_DMA_EN_Pos BÚ$ P DMAC_DMACFGREG_L_DMA_EN_Msk IÚ! P DMAC_CHENREG_L_CH_EN_Pos Ú! P DMAC_CHENREG_L_CH_EN_Msk Ú% P DMAC_CHENREG_L_CH_EN_ALL_Pos ÓÚ% P DMAC_CHENREG_L_CH_EN_ALL_Msk ÚÚ$ P DMAC_CHENREG_L_CH_EN_WE_Pos Ú$ P DMAC_CHENREG_L_CH_EN_WE_Msk Ú( P DMAC_CHENREG_L_CH_EN_WE_ALL_Pos ÒÚ( P DMAC_CHENREG_L_CH_EN_WE_ALL_Msk ÙÚ P DMAC_SAR_L_SAR_Pos ÌÚ P DMAC_SAR_L_SAR_Msk ÓÚ P DMAC_DAR_L_DAR_Pos êÚ P DMAC_DAR_L_DAR_Msk ñÚ P DMAC_CTL_L_INT_EN_Pos ÒÚ P DMAC_CTL_L_INT_EN_Msk ÙÚ$ P DMAC_CTL_L_DST_TR_WIDTH_Pos ÔÚ$ P DMAC_CTL_L_DST_TR_WIDTH_Msk ÛÚ$ P DMAC_CTL_L_SRC_TR_WIDTH_Pos ×Ú$ P DMAC_CTL_L_SRC_TR_WIDTH_Msk ÞÚ P DMAC_CTL_L_DINC_Pos Ú P DMAC_CTL_L_DINC_Msk Ú P DMAC_CTL_L_SINC_Pos Ú P DMAC_CTL_L_SINC_Msk Ú" P DMAC_CTL_L_DEST_MSIZE_Pos Ú" P DMAC_CTL_L_DEST_MSIZE_Msk Ú! P DMAC_CTL_L_SRC_MSIZE_Pos ÚÚ! P DMAC_CTL_L_SRC_MSIZE_Msk áÚ P DMAC_CTL_L_TT_FC_Pos !Ú P DMAC_CTL_L_TT_FC_Msk (Ú P DMAC_CTL_H_BLOCK_TS_Pos >Ú P DMAC_CTL_H_BLOCK_TS_Msk EÚ P DMAC_CTL_H_DONE_Pos Ú P DMAC_CTL_H_DONE_Msk Ú P DMAC_CFG_L_CH_PRIOR_Pos HÚ P DMAC_CFG_L_CH_PRIOR_Msk OÚ P DMAC_CFG_L_CH_SUSP_Pos Ú P DMAC_CFG_L_CH_SUSP_Msk Ú" P DMAC_CFG_L_FIFO_EMPTY_Pos ¨Ú" P DMAC_CFG_L_FIFO_EMPTY_Msk ¯Ú" P DMAC_CFG_L_HS_SEL_DST_Pos Ú" P DMAC_CFG_L_HS_SEL_DST_Msk Ú" P DMAC_CFG_L_HS_SEL_SRC_Pos Ú" P DMAC_CFG_L_HS_SEL_SRC_Msk Ú" P DMAC_CFG_L_DST_HS_POL_Pos Ú" P DMAC_CFG_L_DST_HS_POL_Msk Ú" P DMAC_CFG_L_SRC_HS_POL_Pos Ú" P DMAC_CFG_L_SRC_HS_POL_Msk Ú P DMAC_CFG_H_FCMODE_Pos Ú P DMAC_CFG_H_FCMODE_Msk Ú! P DMAC_CFG_H_FIFO_MODE_Pos Ú! P DMAC_CFG_H_FIFO_MODE_Msk Ú P DMAC_CFG_H_PROTCTL_Pos Ú P DMAC_CFG_H_PROTCTL_Msk £Ú P DMAC_CFG_H_SRC_PER_Pos Ú P DMAC_CFG_H_SRC_PER_Msk Ú P DMAC_CFG_H_DEST_PER_Pos LÚ P DMAC_CFG_H_DEST_PER_Msk SÚ" P DMAC_INT_RAW_STAT_CLR_Pos
Ú" P DMAC_INT_RAW_STAT_CLR_Msk Ú& P DMAC_INT_RAW_STAT_CLR_ALL_Pos EÚ& P DMAC_INT_RAW_STAT_CLR_ALL_Msk LÚ P DMAC_INT_MASK_L_Pos Ú P DMAC_INT_MASK_L_Msk Ú P DMAC_INT_MASK_L_ALL_Pos ?Ú P DMAC_INT_MASK_L_ALL_Msk FÚ P DMAC_INT_MASK_L_WE_Pos ~Ú P DMAC_INT_MASK_L_WE_Msk
Ú# P DMAC_INT_MASK_L_WE_ALL_Pos >Ú# P DMAC_INT_MASK_L_WE_ALL_Msk EÚ! P DMAC_STATUSINT_L_TFR_Pos ÑÚ! P DMAC_STATUSINT_L_TFR_Msk ØÚ# P DMAC_STATUSINT_L_BLOCK_Pos NÚ# P DMAC_STATUSINT_L_BLOCK_Msk UÚ% P DMAC_STATUSINT_L_SRCTRAN_Pos Ú% P DMAC_STATUSINT_L_SRCTRAN_Msk Ú% P DMAC_STATUSINT_L_DSTTRAN_Pos Ú% P DMAC_STATUSINT_L_DSTTRAN_Msk Ú! P DMAC_STATUSINT_L_ERR_Pos ÔÚ! P DMAC_STATUSINT_L_ERR_Msk ÛÚ 8
|
<unnamed> QÚ
|
" ¬ CON Ú
|
" ¬ TAR Ú
|
" ¬ SAR Ú
|
" ¬ HS_MADDR Ú
|
" ¬ DATACMD Ú
|
" ¬ SS_SCL_HCNT wÚ
|
" ¬ SS_SCL_LCNT sÚ
|
" ¬ FS_SCL_HCNT Ú
|
" ¬ FS_SCL_LCNT Ú
|
" ¬ HS_SCL_HCNT Ú
|
" ¬ HS_SCL_LCNT ~Ú
|
" ¬
|
INTR_STAT Ú
|
" ¬
|
INTR_MASK &Ú
|
" ¬ RAW_INTR_STAT ÅÚ
|
" ¬ RX_TL MÚ
|
" ¬ TX_TL KÚ
|
" ¬ CLR_INTR sÚ
|
" ¬ CLR_RX_UND ¼Ú
|
" ¬ CLR_RX_OVR ¬Ú
|
" ¬ CLR_TX_OVR ªÚ
|
" ¬ CLR_RD_REQ ÏÚ
|
" ¬ CLR_TX_ABRT vÚ
|
" ¬ CLR_RX_DONE {Ú
|
" ¬ CLR_ACTIVITY ;Ú
|
" ¬ CLR_STOP_DET &Ú
|
" ¬ CLR_START_DET ÜÚ
|
" ¬ CLR_GEN_CALL SÚ
|
" ¬
|
IC_ENABLE \Ú
|
" ¬ STATUS Ú
|
" ¬ TXFLR fÚ
|
" ¬ RXFLR hÚ
|
" ¬ SDA_HOLD Ú
|
" ¬ TX_ABRT_SRC oÚ
|
" ¬ SLV_DATA_NACK üÚ
|
" ¬ DMA_CR .Ú
|
" ¬ DMA_TDLR Ú
|
" ¬ DMA_RDLR Ú
|
" ¬
|
SDA_SETUP &Ú
|
" ¬ ACK_GENERAL_CALL 9Ú
|
" ¬ ENABLE_STATUS üÚ
|
" ¬
|
FS_SPKLEN )Ú
|
" ¬
|
HS_SPKLEN 'Ú
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" ¬ CLR_RESTART_DET AÚ I2C_T Ú P I2C_CON_MASTER_MODE ùÚ P I2C_CON_SPEED äÚ P I2C_CON_SPEED_0 QÚ P I2C_CON_SPEED_1 PÚ# P I2C_CON_IC_10BITADDR_SLAVE Ú$ P I2C_CON_IC_10BITADDR_MASTER ÈÚ P I2C_CON_IC_RESTART_EN CÚ! P I2C_CON_IC_SLAVE_DISABLE Ú% P I2C_CON_STOP_DET_IFADDRESSED 8Ú P I2C_CON_TX_EMPTY_CTRL Ú P I2C_TAR_TAR kÚ P I2C_TAR_IC_TAR_0 çÚ P I2C_TAR_IC_TAR_1 æÚ P I2C_TAR_IC_TAR_2 åÚ P I2C_TAR_IC_TAR_3 äÚ P I2C_TAR_IC_TAR_4 ãÚ P I2C_TAR_IC_TAR_5 âÚ P I2C_TAR_IC_TAR_6 áÚ P I2C_TAR_IC_TAR_7 àÚ P I2C_TAR_IC_TAR_8 ßÚ P I2C_TAR_IC_TAR_9 ÞÚ P I2C_TAR_GC_OR_START ËÚ P I2C_TAR_SPECIAL IÚ$ P I2C_TAR_IC_10BITADDR_MASTER ÁÚ P I2C_SAR_IC_SAR |Ú P I2C_HS_MADDR_IC_HS_MAR üÚ P I2C_DATA_CMD_DAT Ú P I2C_DATA_CMD_CMD_R YÚ P I2C_DATA_CMD_STOP Ú P I2C_DATA_CMD_RESTART µÚ P I2C_SS_SCL_HCNT Ú P I2C_SS_SCL_LCNT Ú P I2C_FS_SCL_HCNT *Ú P I2C_FS_SCL_LCNT &Ú P I2C_HS_SCL_HCNT (Ú P I2C_HS_SCL_LCNT $Ú! P I2C_INTR_STAT_R_RX_UNDER Ú P I2C_INTR_STAT_R_RX_OVER SÚ P I2C_INTR_STAT_R_RX_FULL \Ú P I2C_INTR_STAT_R_TX_OVER QÚ! P I2C_INTR_STAT_R_TX_EMPTY üÚ P I2C_INTR_STAT_R_RD_REQ ½Ú P I2C_INTR_STAT_R_TX_ABRT dÚ P I2C_INTR_STAT_R_RX_DONE iÚ! P I2C_INTR_STAT_R_ACTIVITY )Ú! P I2C_INTR_STAT_R_STOP_DET Ú" P I2C_INTR_STAT_R_START_DET ÊÚ! P I2C_INTR_STAT_R_GEN_CALL AÚ$ P I2C_INTR_STAT_R_RESTART_DET /Ú$ P I2C_INTR_STAT_R_MST_ON_HOLD Ú! P I2C_INTR_MASK_M_RX_UNDER $Ú P I2C_INTR_MASK_M_RX_OVER hÚ P I2C_INTR_MASK_M_RX_FULL qÚ P I2C_INTR_MASK_M_TX_OVER fÚ! P I2C_INTR_MASK_M_TX_EMPTY Ú P I2C_INTR_MASK_M_RD_REQ ÒÚ P I2C_INTR_MASK_M_TX_ABRT yÚ P I2C_INTR_MASK_M_RX_DONE ~Ú! P I2C_INTR_MASK_M_ACTIVITY >Ú! P I2C_INTR_MASK_M_STOP_DET )Ú" P I2C_INTR_MASK_M_START_DET ßÚ! P I2C_INTR_MASK_M_GEN_CALL VÚ$ P I2C_INTR_MASK_M_RESTART_DET DÚ$ P I2C_INTR_MASK_M_MST_ON_HOLD /Ú# P I2C_RAW_INTR_STAT_RX_UNDER sÚ" P I2C_RAW_INTR_STAT_RX_OVER ·Ú" P I2C_RAW_INTR_STAT_RX_FULL ÀÚ" P I2C_RAW_INTR_STAT_TX_OVER µÚ# P I2C_RAW_INTR_STAT_TX_EMPTY `Ú! P I2C_RAW_INTR_STAT_RD_REQ !Ú" P I2C_RAW_INTR_STAT_TX_ABRT ÈÚ" P I2C_RAW_INTR_STAT_RX_DONE ÍÚ# P I2C_RAW_INTR_STAT_ACTIVITY Ú# P I2C_RAW_INTR_STAT_STOP_DET xÚ$ P I2C_RAW_INTR_STAT_START_DET .Ú# P I2C_RAW_INTR_STAT_GEN_CALL ¥Ú& P I2C_RAW_INTR_STAT_RESTART_DET Ú& P I2C_RAW_INTR_STAT_MST_ON_HOLD ~Ú P
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I2C_RX_TL óÚ P
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I2C_TX_TL ñÚ P I2C_CLR_INTR Ú P I2C_CLR_RX_UNDER ÇÚ P I2C_CLR_TX_OVER Ú P I2C_CLR_RD_REQ uÚ P I2C_CLR_TX_ABORT ËÚ P I2C_CLR_RX_DONE !Ú P I2C_CLR_ACTIVITY áÚ P I2C_CLR_STOP_DET ÌÚ P I2C_CLR_START_DET Ú P I2C_CLR_GEN_CALL ùÚ P I2C_CLR_RESTART_DET çÚ P I2C_CLR_MST_ON_HOLD ÒÚ P I2C_ENABLE_ENABLE ßÚ P I2C_ENABLE_ABORT Ú P I2C_STATUS_ACTIVITY ØÚ P I2C_STATUS_TFNF Ú P I2C_STATUS_TFE pÚ P I2C_STATUS_RFNE "Ú P I2C_STATUS_RFE rÚ P I2C_STATUS_MST_ACTIVITY }Ú P I2C_STATUS_SLV_ACTIVITY |Ú P
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I2C_TXFLR Ú P
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I2C_RXFLR Ú P I2C_SDA_HOLD 8Ú) P !I2C_TX_ABRT_SOURCE_7B_ADDR_NOACK íÚ) P !I2C_TX_ABRT_SOURCE_10ADDR1_NOACK 3Ú) P !I2C_TX_ABRT_SOURCE_10ADDR2_NOACK 2Ú( P I2C_TX_ABRT_SOURCE_TXDATA_NOACK Ú' P I2C_TX_ABRT_SOURCE_GCALL_NOACK Ú& P I2C_TX_ABRT_SOURCE_GCALL_READ ÓÚ% P I2C_TX_ABRT_SOURCE_HS_ACKDET Ú( P I2C_TX_ABRT_SOURCE_SBYTE_ACKDET Ú& P I2C_TX_ABRT_SOURCE_HS_NORSTRT {Ú) P !I2C_TX_ABRT_SOURCE_SBYTE_NORSTRT Ú* P "I2C_TX_ABRT_SOURCE_10B_RD_NORSTRT vÚ& P I2C_TX_ABRT_SOURCE_MASTER_DIS ¦Ú$ P I2C_TX_ABRT_SOURCE_ARB_LOST ?Ú+ P #I2C_TX_ABRT_SOURCE_SLVFLUSH_TXFIFO Ú' P I2C_TX_ABRT_SOURCE_SLV_ARBLOST DÚ& P I2C_TX_ABRT_SOURCE_SLVRD_INTX Ú% P I2C_TX_ABRT_SOURCE_USER_ABRT ìÚ( P I2C_TX_ABRT_SOURCE_TX_FLUSH_CNT ÜÚ P I2C_SLV_DATA_NACK_ONLY ÷Ú P I2C_DMA_CR_RDMAE Ú P I2C_DMA_CR_TDMAE þÚ P I2C_DMA_TDLR /Ú P I2C_DMA_RDLR 1Ú P I2C_SDA_SETUP ÌÚ P I2C_ACK_GENERAL_CALL ßÚ P I2C_ENABLE_STATUS_IC_EN ¹Ú) P !I2C_ENABLE_STATUS_SLV_RX_ABORTED ÇÚ6 P .I2C_ENABLE_STATUS_SLV_FIFO_FILLED_AND_FLUSHED èÚ P I2C_FS_SPKLEN ÏÚ P I2C_HS_SPKLEN ÍÚ' P I2C_COMP_PARAM1_APB_DATA_WIDTH ¸Ú' P I2C_COMP_PARAM1_MAX_SPEED_MODE ©Ú( P I2C_COMP_PARAM1_HC_COUNT_VALUES ?Ú P I2C_COMP_PARAM1_INTR_IO ½Ú P I2C_COMP_PARAM1_HAS_DMA äÚ+ P #I2C_COMP_PARAM1_ADD_ENCODED_PARAMS Ú( P I2C_COMP_PARAM1_RX_BUFFER_DEPTH JÚ( P I2C_COMP_PARAM1_TX_BUFFER_DEPTH HÚ P I2C_COMP_VERSION ÚÚ P I2C_COMP_TYPE ÄÚ 8
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<unnamed> QÚ
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" é LP_REG_SYNC 7Ú
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" é LP_FL_CTRL_3V Ú
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" é LP_SPACING_TIME0 äÚ
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" é LP_SPACING_TIME1 ãÚ
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" é LP_SPACING_TIME2 âÚ
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" é
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LP_SLPTMR ÓÚ
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" é LP_INT_CTRL 2Ú
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" é LP_DLY_CTRL_3V FÚ
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" é LP_PTAT_POLY ÓÚ
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" é
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LP_HP_LDO ßÚ
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" é LP_LP_LDO_3V íÚ
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" é LP_ANA_LDO ¥Ú
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" é LP_FSYN_LDO 3Ú
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" é LP_SW Ú
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" é LP_BUCK_3V ¦Ú
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" é ANA_ADC_LDO wÚ
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" é ANA_RFFE_LDO Ú
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" é ANA_VCO_LDO WÚ
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" é ANA_DFT §Ú
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" é ANA_MISC_3V iÚ
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" é ANA_RESERVED_3V -Ú
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" é ACT_32K_CTRL /Ú
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" é ACT_32K_BASECORR Ú
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" é CPU_ADDR_REMAP_CTRL ÒÚ
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" é RCL_HW_CAL_CTRL Ú ANA_T tÚ P ANAC_LP_REG_SYNC_3V_Pos =Ú P ANAC_LP_REG_SYNC_3V_Msk DÚ$ P ANAC_LP_REG_SYNC_3V_TRG_Pos éÚ$ P ANAC_LP_REG_SYNC_3V_TRG_Msk ðÚ# P ANAC_FL_SLEEP_MODE_SEL_Pos cÚ# P ANAC_FL_SLEEP_MODE_SEL_Msk jÚ& P ANAC_FL_EXT_WAKEUP_SEL_Pos_3v 5Ú& P ANAC_FL_EXT_WAKEUP_SEL_Msk_3v <Ú! P ANAC_FL_SLEEP_CNT_EN_Pos øÚ! P ANAC_FL_SLEEP_CNT_EN_Msk ÿÚ% P ANAC_FL_CPU_RETENTION_EN_Pos ®Ú% P ANAC_FL_CPU_RETENTION_EN_Msk µÚ# P ANAC_FL_LDO_ISOLATE_EN_Pos bÚ# P ANAC_FL_LDO_ISOLATE_EN_Msk iÚ P ANAC_FL_RCL_GATE_EN_Pos VÚ P ANAC_FL_RCL_GATE_EN_Msk ]Ú P ANAC_FL_PWR_CTL_EN_Pos ~Ú P ANAC_FL_PWR_CTL_EN_Msk
Ú P ANAC_FL_FLASH_BP_EN_Pos XÚ P ANAC_FL_FLASH_BP_EN_Msk _Ú P ANAC_FL_FLASH_LP_EN_Pos NÚ P ANAC_FL_FLASH_LP_EN_Msk UÚ P ANAC_FL_BUCK_BP_EN_Pos £Ú P ANAC_FL_BUCK_BP_EN_Msk ªÚ P ANAC_FL_BUCK_EN_Pos Ú P ANAC_FL_BUCK_EN_Msk ¡Ú P ANAC_FL_DPLL_EN_Pos Ú P ANAC_FL_DPLL_EN_Msk Ú P ANAC_FL_RCH_EN_Pos äÚ P ANAC_FL_RCH_EN_Msk ëÚ P ANAC_FL_XTH_EN_Pos ÍÚ P ANAC_FL_XTH_EN_Msk ÔÚ" P ANAC_FL_XTAL32K_EN_Pos_3v ÂÚ" P ANAC_FL_XTAL32K_EN_Msk_3v ÉÚ P ANAC_FL_RC32K_EN_Pos_3v jÚ P ANAC_FL_RC32K_EN_Msk_3v qÚ P ANAC_FL_LDO_HP_EN_Pos åÚ P ANAC_FL_LDO_HP_EN_Msk ìÚ P ANAC_FL_PMU_EN_Pos ÏÚ P ANAC_FL_PMU_EN_Msk ÖÚ! P ANAC_SRAM0_POWER_CTL_Pos Ú! P ANAC_SRAM0_POWER_CTL_Msk Ú! P ANAC_SRAM1_POWER_CTL_Pos Ú! P ANAC_SRAM1_POWER_CTL_Msk Ú P ANAC_CPU_POWER_CTL_Pos Ú P ANAC_CPU_POWER_CTL_Msk Ú P ANAC_PHY_POWER_CTL_Pos }Ú P ANAC_PHY_POWER_CTL_Msk Ú# P ANAC_LL_SRAM_POWER_CTL_Pos <Ú# P ANAC_LL_SRAM_POWER_CTL_Msk CÚ! P ANAC_FLASH_POWER_CTL_Pos üÚ! P ANAC_FLASH_POWER_CTL_Msk Ú P ANAC_LDO_POWER_CTL_Pos Ú P ANAC_LDO_POWER_CTL_Msk Ú P ANAC_LDOL_POWER_CTL_Pos AÚ P ANAC_LDOL_POWER_CTL_Msk HÚ P ANAC_INT_LP_INT_EN_Pos zÚ P ANAC_INT_LP_INT_EN_Msk Ú P ANAC_INT_DP_FLAG_Pos IÚ P ANAC_INT_DP_FLAG_Msk PÚ% P ANAC_INT_STANDBY_M1_FLAG_Pos ÛÚ% P ANAC_INT_STANDBY_M1_FLAG_Msk âÚ% P ANAC_INT_STANDBY_M0_FLAG_Pos ÜÚ% P ANAC_INT_STANDBY_M0_FLAG_Msk ãÚ# P ANAC_INT_SRAM_RET_FLAG_Pos TÚ# P ANAC_INT_SRAM_RET_FLAG_Msk [Ú& P ANAC_INT_SLEEP_TMR_INT_EN_Pos =Ú& P ANAC_INT_SLEEP_TMR_INT_EN_Msk DÚ P ANAC_INT_SLEEP_TMR0_Pos UÚ P ANAC_INT_SLEEP_TMR0_Msk \Ú P ANAC_INT_SLEEP_TMR1_Pos TÚ P ANAC_INT_SLEEP_TMR1_Msk [Ú P ANAC_INT_SLEEP_TMR2_Pos SÚ P ANAC_INT_SLEEP_TMR2_Msk ZÚ% P ANAC_INT_SLEEP_TMR_WK_EN_Pos Ú% P ANAC_INT_SLEEP_TMR_WK_EN_Msk Ú! P ANAC_32KCLK_DLY_TIME_Pos 8Ú! P ANAC_32KCLK_DLY_TIME_Msk ?Ú P ANAC_32KCLK_DLY_EN_Pos ØÚ P ANAC_32KCLK_DLY_EN_Msk ßÚ" P ANAC_HPLDO_RDY_BYPASS_Pos Ú" P ANAC_HPLDO_RDY_BYPASS_Msk §Ú$ P ANAC_LPLDOH_DLY_TIME_Pos_3v ñÚ$ P ANAC_LPLDOH_DLY_TIME_Msk_3v øÚ P ANAC_PTAT_CORE_EN_Pos ëÚ P ANAC_PTAT_CORE_EN_Msk òÚ P ANAC_PTAT_TMP_TRIM_Pos xÚ P ANAC_PTAT_TMP_TRIM_Msk Ú P ANAC_PTAT_TRIM_Pos ÐÚ P ANAC_PTAT_TRIM_Msk ×Ú# P ANAC_PTAT_FLT_SHIFT_EN_Pos GÚ# P ANAC_PTAT_FLT_SHIFT_EN_Msk NÚ! P ANAC_PTAT_FLT_ACT_EN_Pos ñÚ! P ANAC_PTAT_FLT_ACT_EN_Msk øÚ P ANAC_POLY_EN_Pos rÚ P ANAC_POLY_EN_Msk yÚ P ANAC_IPOLY_TRIM_Pos zÚ P ANAC_IPOLY_TRIM_Msk Ú P ANAC_HPLDO_EN_Pos =Ú P ANAC_HPLDO_EN_Msk DÚ P ANAC_HPLDO_BYPASS_Pos öÚ P ANAC_HPLDO_BYPASS_Msk ýÚ P ANAC_HPLDO_TRIM_Pos Ú P ANAC_HPLDO_TRIM_Msk Ú P ANAC_HPLDO_SEL_Pos êÚ P ANAC_HPLDO_SEL_Msk ñÚ& P ANAC_HPLDO_FLASHLDO_BP_Pos_3v rÚ& P ANAC_HPLDO_FLASHLDO_BP_Msk_3v yÚ& P ANAC_HPLDO_FLASHLDO_EN_Pos_3v qÚ& P ANAC_HPLDO_FLASHLDO_EN_Msk_3v xÚ& P ANAC_HPLDO_FLASHLDO_LP_EN_Pos ~Ú& P ANAC_HPLDO_FLASHLDO_LP_EN_Msk
Ú( P ANAC_HPLDO_FLASHLDO_CAP_SEL_Pos ñÚ( P ANAC_HPLDO_FLASHLDO_CAP_SEL_Msk øÚ% P ANAC_HPLDO_FLASHLDO_TRIM_Pos ÒÚ% P ANAC_HPLDO_FLASHLDO_TRIM_Msk ÙÚ P ANAC_LPLDO_L_EN_Pos Ú P ANAC_LPLDO_L_EN_Msk Ú" P ANAC_LPLDO_L_DVDD_SEL_Pos ¬Ú" P ANAC_LPLDO_L_DVDD_SEL_Msk ³Ú P ANAC_LPLDO_H_EN_Pos_3v Ú P ANAC_LPLDO_H_EN_Msk_3v Ú% P ANAC_LPLDO_H_DVDD_SEL_Pos_3v ¢Ú% P ANAC_LPLDO_H_DVDD_SEL_Msk_3v ©Ú% P ANAC_LPLDO_H_REF_TRIM_Pos_3v Ú% P ANAC_LPLDO_H_REF_TRIM_Msk_3v Ú% P ANAC_LPLDO_H_MODE_SEL_Pos_3v Ú% P ANAC_LPLDO_H_MODE_SEL_Msk_3v ¦Ú P ANAC_ANA_LDO_EN_Pos ¢Ú P ANAC_ANA_LDO_EN_Msk ©Ú P ANAC_ANA_LDO_TRIM_Pos õÚ P ANAC_ANA_LDO_TRIM_Msk üÚ P ANAC_FSYN_LDO_EN_Pos 0Ú P ANAC_FSYN_LDO_EN_Msk 7Ú P ANAC_FSYN_LDO_TRIM_Pos Ú P ANAC_FSYN_LDO_TRIM_Msk Ú P ANAC_HP_DVDD_PD_Pos Ú P ANAC_HP_DVDD_PD_Msk Ú P ANAC_HP_DVDD_EN_Pos Ú P ANAC_HP_DVDD_EN_Msk Ú P ANAC_DVDD_SRAM0_EN_Pos ÆÚ P ANAC_DVDD_SRAM0_EN_Msk ÍÚ P ANAC_DVDD_SRAM1_EN_Pos ÅÚ P ANAC_DVDD_SRAM1_EN_Msk ÌÚ P ANAC_DVDD_LPLDO_EN_Pos ®Ú P ANAC_DVDD_LPLDO_EN_Msk µÚ P ANAC_VDD_FLASH_EN_Pos Ú P ANAC_VDD_FLASH_EN_Msk Ú P ANAC_DVDD_DLL_EN_Pos QÚ P ANAC_DVDD_DLL_EN_Msk XÚ P ANAC_DVDD_PHY_EN_Pos <Ú P ANAC_DVDD_PHY_EN_Msk CÚ P ANAC_DVDD_CPU_EN_Pos EÚ P ANAC_DVDD_CPU_EN_Msk LÚ# P ANAC_BUCK_BYPASS_EN_Pos_3v DÚ# P ANAC_BUCK_BYPASS_EN_Msk_3v KÚ P ANAC_BUCK_EN_Pos_3v Ú P ANAC_BUCK_EN_Msk_3v Ú P ANAC_BUCK_VOUT_Pos_3v ÄÚ P ANAC_BUCK_VOUT_Msk_3v ËÚ P ANAC_BUCK_IMAX_Pos_3v ãÚ P ANAC_BUCK_IMAX_Msk_3v êÚ" P ANAC_BUCK_IMAX_CAL_Pos_3v ¬Ú" P ANAC_BUCK_IMAX_CAL_Msk_3v ³Ú" P ANAC_BUCK_ZERO_CAL_Pos_3v Ú" P ANAC_BUCK_ZERO_CAL_Msk_3v ¢Ú% P ANAC_BUCK_DLY_MODE_EN_Pos_3v ¥Ú% P ANAC_BUCK_DLY_MODE_EN_Msk_3v ¬Ú P ANAC_BUCK_TEST_EN_Pos èÚ P ANAC_BUCK_TEST_EN_Msk ïÚ% P ANAC_BUCK_DEBOUNCE_EN_Pos_3v ÍÚ% P ANAC_BUCK_DEBOUNCE_EN_Msk_3v ÔÚ P ANAC_BUCK_CAL_EN_Pos_3v LÚ P ANAC_BUCK_CAL_EN_Msk_3v SÚ P ANAC_BUCK_CAL_OUT_Pos óÚ P ANAC_BUCK_CAL_OUT_Msk úÚ& P ANAC_BUCK_VOL_LIMIT_EN_Pos_3v AÚ& P ANAC_BUCK_VOL_LIMIT_EN_Msk_3v HÚ P ANAC_ADC_LDO_EN_Pos ªÚ P ANAC_ADC_LDO_EN_Msk ±Ú P ANAC_ADC_LDO_TRIM_Pos ýÚ P ANAC_ADC_LDO_TRIM_Msk Ú P ANAC_RFFE_LDO_EN_Pos MÚ P ANAC_RFFE_LDO_EN_Msk TÚ P ANAC_RFFE_LDO_TRIM_Pos Ú P ANAC_RFFE_LDO_TRIM_Msk §Ú P ANAC_VCO_LDO_EN_Pos Ú P ANAC_VCO_LDO_EN_Msk Ú P ANAC_VCO_LDO_TRIM_Pos ÝÚ P ANAC_VCO_LDO_TRIM_Msk äÚ P ANAC_DFT_BUF_BYPASS_Pos OÚ P ANAC_DFT_BUF_BYPASS_Msk VÚ P ANAC_DFT_FLAG_SEL_Pos Ú P ANAC_DFT_FLAG_SEL_Msk Ú P ANAC_DFT_CLK_SEL_Pos FÚ P ANAC_DFT_CLK_SEL_Msk MÚ P ANAC_DFT_I_SEL_Pos ÛÚ P ANAC_DFT_I_SEL_Msk âÚ P ANAC_DFT_V_SEL_Pos ÎÚ P ANAC_DFT_V_SEL_Msk ÕÚ$ P ANAC_DFT_FLAG_OUTPUT_EN_Pos ùÚ$ P ANAC_DFT_FLAG_OUTPUT_EN_Msk Ú# P ANAC_DFT_CLK_OUTPUT_EN_Pos ;Ú# P ANAC_DFT_CLK_OUTPUT_EN_Msk BÚ! P ANAC_DFT_I_OUTPUT_EN_Pos ÐÚ! P ANAC_DFT_I_OUTPUT_EN_Msk ×Ú! P ANAC_DFT_V_OUTPUT_EN_Pos ÃÚ! P ANAC_DFT_V_OUTPUT_EN_Msk ÊÚ" P ANAC_DFT_PAD_TEST_SEL_Pos ¢Ú" P ANAC_DFT_PAD_TEST_SEL_Msk ©Ú% P ANAC_DFT_BATTERY_TEST_EN_Pos §Ú% P ANAC_DFT_BATTERY_TEST_EN_Msk ®Ú& P ANAC_DFT_BATTERY_TEST_SEL_Pos TÚ& P ANAC_DFT_BATTERY_TEST_SEL_Msk [Ú' P ANAC_DFT_BATTERY_TEST_TRIM_Pos úÚ' P ANAC_DFT_BATTERY_TEST_TRIM_Msk Ú' P ANAC_MISC_RST_VREF_TRIM_Pos_3v ÓÚ' P ANAC_MISC_RST_VREF_TRIM_Msk_3v ÚÚ" P ANAC_MISC_PMU_LDO_TST_Pos Ú" P ANAC_MISC_PMU_LDO_TST_Msk Ú% P ANAC_MISC_PMU_VBG_BUF_EN_Pos §Ú% P ANAC_MISC_PMU_VBG_BUF_EN_Msk ®Ú. P &ANAC_MISC_LPLDO_LEVEL_SHIFT_EN_Pos_3v ÊÚ. P &ANAC_MISC_LPLDO_LEVEL_SHIFT_EN_Msk_3v ÑÚ+ P #ANAC_MISC_HPLDO_LEVEL_SHIFT_EN_Pos ÜÚ+ P #ANAC_MISC_HPLDO_LEVEL_SHIFT_EN_Msk ãÚ% P ANAC_MISC_FLASH_PAD_PUEN_Pos ÌÚ% P ANAC_MISC_FLASH_PAD_PUEN_Msk ÓÚ% P ANAC_MISC_FLASH_PAD_PDEN_Pos ÝÚ% P ANAC_MISC_FLASH_PAD_PDEN_Msk äÚ P ANAC_MISC_USB_EN_Pos 9Ú P ANAC_MISC_USB_EN_Msk @Ú P ANAC_MISC_USB_DP_PU_Pos .Ú P ANAC_MISC_USB_DP_PU_Msk 5Ú P ANAC_MISC_USB_DM_PU_Pos 1Ú P ANAC_MISC_USB_DM_PU_Msk 8Ú P ANAC_ACT_32K_EN_Pos ÉÚ P ANAC_ACT_32K_EN_Msk ÐÚ P ANAC_ACT_32K_SEL_Pos vÚ P ANAC_ACT_32K_SEL_Msk }Ú! P ANAC_ACT_32K_UP_DONE_Pos (Ú! P ANAC_ACT_32K_UP_DONE_Msk /Ú% P ANAC_ACT_32K_FINE_OFFSET_Pos Ú% P ANAC_ACT_32K_FINE_OFFSET_Msk Ú& P ANAC_ACT_32K_FINE_CORRECT_Pos µÚ& P ANAC_ACT_32K_FINE_CORRECT_Msk ¼Ú P ANAC_CPU_REMAP_ADR_Pos ªÚ P ANAC_CPU_REMAP_ADR_Msk ±Ú" P ANAC_CPU_ADR_REMAP_EN_Pos ²Ú" P ANAC_CPU_ADR_REMAP_EN_Msk ¹Ú! P ANAC_RCL_HW_CAL_TIME_Pos üÚ! P ANAC_RCL_HW_CAL_TIME_Msk Ú P ANAC_RCL_HW_CAL_EN_Pos Ú P ANAC_RCL_HW_CAL_EN_Msk £Ú! P ANAC_RCL_HW_CAL_BUSY_Pos èÚ! P ANAC_RCL_HW_CAL_BUSY_Msk ïÚ 8
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<unnamed> QÚ
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" !EF_CTL KÚ
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" !EF_ADDR Ú
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" !EF_DAT UÚ
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" !EF_RSV0 Ú
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" !EF_VDD PÚ
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" !EF_RSV1 Ú
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" !EF_CMD ZÚ
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" !EF_TRG AÚ
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" !EF_PROG_TIMING1 Ú
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" !EF_PROG_TIMING2 Ú
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" !EF_PROG_TIMING3 Ú
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" !EF_READ_TIMING4 ¥Ú
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" !EF_READ_TIMING5 ¤Ú <" 0!EF_RSV2 ¡Ú
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" ! EF_OP_ERROR Ú
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" !EF_VERIFY_DEBUG1 NÚ
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" !EF_VERIFY_DEBUG2 MÚ
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" !EF_VERIFY_DEBUG3 LÚ
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" !EF_VERIFY_DEBUG4 KÚ
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" !EF_FLASH_PERMISSION >Ú EFUSE_T ÈÚ P EFUSE_CTL_EFUSE_EN_Pos Ú P EFUSE_CTL_EFUSE_EN_Msk Ú P EFUSE_CTL_THR_DVDD_Pos Ú P EFUSE_CTL_THR_DVDD_Msk Ú" P EFUSE_CTL_TAEN_RD_CTL_Pos Ú" P EFUSE_CTL_TAEN_RD_CTL_Msk Ú! P EFUSE_CTL_THR_RD_CTL_Pos ÌÚ! P EFUSE_CTL_THR_RD_CTL_Msk ÓÚ P EFUSE_CTL_TRD_CTL_Pos ËÚ P EFUSE_CTL_TRD_CTL_Msk ÒÚ! P EFUSE_CTL_TSR_RD_CTL_Pos ÁÚ! P EFUSE_CTL_TSR_RD_CTL_Msk ÈÚ# P EFUSE_CTL_TSR_DVDD_CTL_Pos 1Ú# P EFUSE_CTL_TSR_DVDD_CTL_Msk 8Ú! P EFUSE_CTL_THP_RD_CTL_Pos ÎÚ! P EFUSE_CTL_THP_RD_CTL_Msk ÕÚ& P EFUSE_CTL_THP_PG_AVDD_CTL_Pos EÚ& P EFUSE_CTL_THP_PG_AVDD_CTL_Msk LÚ# P EFUSE_CTL_TAEN_PGM_CTL_Pos @Ú# P EFUSE_CTL_TAEN_PGM_CTL_Msk GÚ" P EFUSE_CTL_THP_PGM_CTL_Pos ~Ú" P EFUSE_CTL_THP_PGM_CTL_Msk
Ú P EFUSE_CTL_TPGM_CTL_Pos {Ú P EFUSE_CTL_TPGM_CTL_Msk Ú" P EFUSE_CTL_TSP_PGM_CTL_Pos sÚ" P EFUSE_CTL_TSP_PGM_CTL_Msk zÚ& P EFUSE_CTL_TSP_PG_AVDD_CTL_Pos :Ú& P EFUSE_CTL_TSP_PG_AVDD_CTL_Msk AÚ! P EFUSE_CTL_TSP_RD_CTL_Pos ÃÚ% P EFUSE_CTL_TSP_TSP_RD_CTL_Msk lÚ% P EFUSE_ADDR_EFUSEADDR_ADR_Pos èÚ% P EFUSE_ADDR_EFUSEADDR_ADR_Msk ïÚ# P EFUSE_DAT_EFUSEDAT_DAT_Pos nÚ# P EFUSE_DAT_EFUSEDAT_DAT_Msk uÚ+ P #EFUSE_DAT_EFUSEDAT_DAT_CONFIRM_Pos ñÚ+ P #EFUSE_DAT_EFUSEDAT_DAT_CONFIRM_Msk øÚ P EFUSE_VDD_DVDD_REG_Pos Ú P EFUSE_VDD_DVDD_REG_Msk ¢Ú P EFUSE_VDD_AVDD_REG_Pos Ú P EFUSE_VDD_AVDD_REG_Msk ¥Ú# P EFUSE_CMD_EFUSECMD_CMD_Pos }Ú# P EFUSE_CMD_EFUSECMD_CMD_Msk Ú" P EFUSE_TRG_EFUSETRG_GO_Pos Ú" P EFUSE_TRG_EFUSETRG_GO_Msk Ú* P "EFUSE_PROG_TIMING1_TSP_RD_SET_Pos ûÚ* P "EFUSE_PROG_TIMING1_TSP_RD_SET_Msk Ú/ P 'EFUSE_PROG_TIMING1_TSP_PG_AVDD_SET_Pos rÚ/ P 'EFUSE_PROG_TIMING1_TSP_PG_AVDD_SET_Msk yÚ+ P #EFUSE_PROG_TIMING1_TSP_PGM_SET_Pos «Ú+ P #EFUSE_PROG_TIMING1_TSP_PGM_SET_Msk ²Ú( P EFUSE_PROG_TIMING2_TPGM_SET_Pos ²Ú( P EFUSE_PROG_TIMING2_TPGM_SET_Msk ¹Ú+ P #EFUSE_PROG_TIMING2_THP_PGM_SET_Pos µÚ+ P #EFUSE_PROG_TIMING2_THP_PGM_SET_Msk ¼Ú, P $EFUSE_PROG_TIMING2_TAEN_PGM_SET_Pos wÚ, P $EFUSE_PROG_TIMING2_TAEN_PGM_SET_Msk ~Ú/ P 'EFUSE_PROG_TIMING3_THP_PG_AVDD_SET_Pos {Ú/ P 'EFUSE_PROG_TIMING3_THP_PG_AVDD_SET_Msk Ú* P "EFUSE_PROG_TIMING3_THP_RD_SET_Pos Ú* P "EFUSE_PROG_TIMING3_THP_RD_SET_Msk Ú, P $EFUSE_READ_TIMING4_TSR_DVDD_SET_Pos Ú, P $EFUSE_READ_TIMING4_TSR_DVDD_SET_Msk Ú* P "EFUSE_READ_TIMING4_TSR_RD_SET_Pos Ú* P "EFUSE_READ_TIMING4_TSR_RD_SET_Msk Ú' P EFUSE_READ_TIMING4_TRD_SET_Pos Ú' P EFUSE_READ_TIMING4_TRD_SET_Msk #Ú* P "EFUSE_READ_TIMING5_THR_RD_SET_Pos Ú* P "EFUSE_READ_TIMING5_THR_RD_SET_Msk #Ú+ P #EFUSE_READ_TIMING5_TAEN_RD_SET_Pos àÚ+ P #EFUSE_READ_TIMING5_TAEN_RD_SET_Msk çÚ, P $EFUSE_READ_TIMING5_THR_DVDD_SET_Pos Ú, P $EFUSE_READ_TIMING5_THR_DVDD_SET_Msk Ú$ P EFUSE_OP_ERROR_OP_ERROR_Pos ¾Ú$ P EFUSE_OP_ERROR_OP_ERROR_Msk ÅÚ0 P (EFUSE_VERIFY_DEBUG1_VERIFY_DBG_KEY1_Pos pÚ0 P (EFUSE_VERIFY_DEBUG1_VERIFY_DBG_KEY1_Msk wÚ0 P (EFUSE_VERIFY_DEBUG2_VERIFY_DBG_KEY2_Pos nÚ0 P (EFUSE_VERIFY_DEBUG2_VERIFY_DBG_KEY2_Msk uÚ0 P (EFUSE_VERIFY_DEBUG3_VERIFY_DBG_KEY3_Pos lÚ0 P (EFUSE_VERIFY_DEBUG3_VERIFY_DBG_KEY3_Msk sÚ0 P (EFUSE_VERIFY_DEBUG4_VERIFY_DBG_KEY4_Pos jÚ0 P (EFUSE_VERIFY_DEBUG4_VERIFY_DBG_KEY4_Msk qÚ( P EFUSE_FLASH_PERMISSION_CTRL_Pos »Ú( P EFUSE_FLASH_PERMISSION_CTRL_Msk ÂÚ 8
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<unnamed> QÚ " î!FADDR VÚ " î!POWER *Ú " î!INT_IN1 ¡Ú " î!INT_IN2 Ú " î! INT_OUT1 >Ú " î! INT_OUT2 =Ú " î!INT_USB Ú " î! INT_IN1E ZÚ " î! INT_IN2E YÚ " î!
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INT_OUT1E ÷Ú " î!
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INT_OUT2E öÚ " î! INT_USBE 8Ú " î!FRAME1 Ú " î!FRAME2 Ú " î!INDEX ?Ú " î!REV ÎÚ " î! MAX_PKT_IN Ú " î! CSR0_INCSR1 Ú " î!IN_CSR2 £Ú " î! MAX_PKT_OUT Ú " î! OUT_CSR1 AÚ " î! OUT_CSR2 @Ú " î! OUT_COUNT1 Ú " î! OUT_COUNT2 Ú <" î!REV0 _Ú " î! FIFO_EP0 iÚ <" î!REV1 cÚ " î! FIFO_EP1 hÚ <" î!REV2 bÚ " î! FIFO_EP2 gÚ <" î!REV3 aÚ " î! FIFO_EP3 fÚ USB_T ZÚ 8
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<unnamed> QÚ
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" " DMA_INTR Ú
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" "CNTL1 «Ú
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" "ADDR1 ÁÚ
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" "COUNT1 QÚ USBDMA_T Ú P USB_DMA_REQUEST_Pos qÚ P USB_DMA_REQUEST_Msk xÚ P USB_DMA_DIRECTION_Pos õÚ P USB_DMA_DIRECTION_Msk üÚ P USB_DMA_MODE_SEL_Pos 0Ú P USB_DMA_MODE_SEL_Msk 7Ú P USB_DMA_EP_NUM_Pos ¸Ú P USB_DMA_EP_NUM_Msk ¿Ú 8
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<unnamed> QÚ
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" "revs0 Ú
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" "FSM5 æÚ
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" "FSM6 åÚ
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" "FSM13 µÚ
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" "FSM14 ´Ú
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" "FSM15 ³Ú
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" "FSM16 ²Ú
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" "FSM17 ±Ú
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" "FSM18 °Ú
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" "FSM19 ¯Ú
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" "PHY1 ßÚ
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" "PHY2 ÞÚ
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" "PHY3 ÝÚ
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" "PHY4 ÜÚ
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" "PHY5 ÛÚ <" "revs1 ØÚ
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" "INTR1 Ú
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" "INTCLR 1Ú
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" "INTMSK 'Ú
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" "INTR4 Ú
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" "revs2 Ú
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" "ACTTMR1 ÿÚ
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" "ACTTMR2 þÚ
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" "ACTTMR6 úÚ
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" "ACTTMR7 ùÚ
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" "revs3 Ú
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" "SECURE1 Ú
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" "SECURE2 Ú
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" "SECURE3 Ú
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" "SECURE4 Ú
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" "SECURE5 ÿÚ
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" "SECURE6 þÚ
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" "SECURE7 ýÚ
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" "SECURE8 üÚ
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" "SECURE9 ûÚ
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" " SECURE10 ÑÚ
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" "revs4 Ú
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" " TEST_MUX00 üÚ
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" "RNG1 éÚ
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" "RNG2 èÚ
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" "revs5
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Ú
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" " LL_MAC_CTRL Ú
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" " TEST_MUX01 ûÚ
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" " TEST_MUX02 úÚ
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" " TEST_MUX03 ùÚ <" "revs6 ÓÚ
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" "R00_CTL Ú
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" "R01_INT þÚ
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" " R02_TMR_CTL «Ú
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" "R03_RX_ADDR_L Ú
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" " R04_RX_CTL ôÚ
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" "R05_TX_ADDR_L Ú
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" " R06_TX_CTL ðÚ
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" " R07_SRAM_CTL dÚ
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" "R08_RX_ADDR1_L ÔÚ
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" "R09_RX_ADDR2_L ÒÚ
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" "R0A_RX_ADDR3_L ÉÚ
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" "R0B_RX_ADDR4_L ÇÚ
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" "R0C_RX_ADDR5_L ÅÚ
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" "R0D_RX_ADDR6_L ÃÚ
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" "R0E_RX_ADDR7_L ÁÚ
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" "R0F_RX_ADDR_H ýÚ
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" "R10_RX_ADDR_EN ÅÚ
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" "R11_CFG Ú PRI_RF_T \Ú P FSM5_SM_STP_Pos ¬Ú P FSM5_SM_STP_Msk ³Ú P FSM5_SM_TX_LATENCY_Pos zÚ P FSM5_SM_TX_LATENCY_Msk Ú P FSM6_SM_RX_LATENCY_Pos {Ú P FSM6_SM_RX_LATENCY_Msk Ú& P FSM13_SM_RX_PACKET_ADDR_1_Pos Ú& P FSM13_SM_RX_PACKET_ADDR_1_Msk Ú& P FSM13_SM_TX_PACKET_ADDR_1_Pos Ú& P FSM13_SM_TX_PACKET_ADDR_1_Msk Ú& P FSM14_SM_RX_PACKET_ADDR_2_Pos Ú& P FSM14_SM_RX_PACKET_ADDR_2_Msk Ú& P FSM14_SM_TX_PACKET_ADDR_2_Pos Ú& P FSM14_SM_TX_PACKET_ADDR_2_Msk Ú& P FSM15_SM_RX_PACKET_ADDR_3_Pos Ú& P FSM15_SM_RX_PACKET_ADDR_3_Msk Ú& P FSM15_SM_TX_PACKET_ADDR_3_Pos Ú& P FSM15_SM_TX_PACKET_ADDR_3_Msk Ú& P FSM16_SM_RX_PACKET_ADDR_4_Pos Ú& P FSM16_SM_RX_PACKET_ADDR_4_Msk Ú& P FSM16_SM_TX_PACKET_ADDR_4_Pos
Ú& P FSM16_SM_TX_PACKET_ADDR_4_Msk Ú& P FSM17_SM_RX_PACKET_ADDR_5_Pos
Ú& P FSM17_SM_RX_PACKET_ADDR_5_Msk Ú& P FSM17_SM_TX_PACKET_ADDR_5_Pos Ú& P FSM17_SM_TX_PACKET_ADDR_5_Msk Ú& P FSM18_SM_RX_PACKET_ADDR_6_Pos Ú& P FSM18_SM_RX_PACKET_ADDR_6_Msk Ú& P FSM18_SM_TX_PACKET_ADDR_6_Pos Ú& P FSM18_SM_TX_PACKET_ADDR_6_Msk Ú& P FSM19_SM_RX_PACKET_ADDR_7_Pos Ú& P FSM19_SM_RX_PACKET_ADDR_7_Msk Ú& P FSM19_SM_TX_PACKET_ADDR_7_Pos Ú& P FSM19_SM_TX_PACKET_ADDR_7_Msk Ú& P PHY1_PHY_DRV_RSP_BUF_FULL_Pos !Ú& P PHY1_PHY_DRV_RSP_BUF_FULL_Msk (Ú' P PHY1_PHY_DRV_RSP_BUF_EMPTY_Pos ÃÚ' P PHY1_PHY_DRV_RSP_BUF_EMPTY_Msk ÊÚ' P PHY1_PHY_DRV_CFG_BUF_ERROR_Pos íÚ' P PHY1_PHY_DRV_CFG_BUF_ERROR_Msk ôÚ& P PHY1_PHY_DRV_CFG_BUF_FULL_Pos FÚ& P PHY1_PHY_DRV_CFG_BUF_FULL_Msk MÚ' P PHY1_PHY_DRV_CFG_BUF_EMPTY_Pos èÚ' P PHY1_PHY_DRV_CFG_BUF_EMPTY_Msk ïÚ! P PHY1_IF_CLK_PRESCALE_Pos Ú! P PHY1_IF_CLK_PRESCALE_Msk Ú' P PHY1_PHY_DRV_RSSI_REG_ADDR_Pos êÚ' P PHY1_PHY_DRV_RSSI_REG_ADDR_Msk ñÚ! P PHY1_PHY_DRV_CFG_TRG_Pos ÒÚ! P PHY1_PHY_DRV_CFG_TRG_Msk ÙÚ! P PHY1_PHY_DRV_CFG_REG_Pos áÚ! P PHY1_PHY_DRV_CFG_REG_Msk èÚ' P PHY1_PHY_DRV_RSP_BUF_FLUSH_Pos ÐÚ' P PHY1_PHY_DRV_RSP_BUF_FLUSH_Msk ×Ú' P PHY1_PHY_DRV_CFG_BUF_FLUSH_Pos õÚ' P PHY1_PHY_DRV_CFG_BUF_FLUSH_Msk üÚ' P PHY2_PHY_DRV_RSP_BUF_ERROR_Pos ÇÚ' P PHY2_PHY_DRV_RSP_BUF_ERROR_Msk ÎÚ) P !PHY2_PHY_DRV_SEQ_RX_END_ADDR_Pos ;Ú) P !PHY2_PHY_DRV_SEQ_RX_END_ADDR_Msk BÚ) P !PHY2_PHY_DRV_SEQ_TX_END_ADDR_Pos 9Ú) P !PHY2_PHY_DRV_SEQ_TX_END_ADDR_Msk @Ú* P "PHY2_PHY_DRV_SEQ_RX_STRT_ADDR_Pos ÃÚ* P "PHY2_PHY_DRV_SEQ_RX_STRT_ADDR_Msk ÊÚ* P "PHY2_PHY_DRV_SEQ_TX_STRT_ADDR_Pos ÁÚ* P "PHY2_PHY_DRV_SEQ_TX_STRT_ADDR_Msk ÈÚ% P PHY3_PHY_DRV_CFG_BUF_DIN_Pos Ú% P PHY3_PHY_DRV_CFG_BUF_DIN_Msk ¥Ú& P PHY4_PHY_DRV_RSP_BUF_DOUT_Pos Ú& P PHY4_PHY_DRV_RSP_BUF_DOUT_Msk Ú+ P #PHY5_PHY_DRV_SET_CHAN_REG_ADDR_Pos ºÚ+ P #PHY5_PHY_DRV_SET_CHAN_REG_ADDR_Msk ÁÚ P INTR1_IC_RNG_DONE_Pos ìÚ P INTR1_IC_RNG_DONE_Msk óÚ P INTR1_IC_SEC_DONE_Pos øÚ P INTR1_IC_SEC_DONE_Msk ÿÚ0 P (INTR1_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_Pos Ú0 P (INTR1_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_Msk Ú& P INTR1_IC_PHY_DRV_CFG_DONE_Pos XÚ& P INTR1_IC_PHY_DRV_CFG_DONE_Msk _Ú# P INTCLR_IC_RNG_DONE_CLR_Pos DÚ# P INTCLR_IC_RNG_DONE_CLR_Msk KÚ# P INTCLR_IC_SEC_DONE_CLR_Pos PÚ# P INTCLR_IC_SEC_DONE_CLR_Msk WÚ5 P -INTCLR_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_CLR_Pos XÚ5 P -INTCLR_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_CLR_Msk _Ú+ P #INTCLR_IC_PHY_DRV_CFG_DONE_CLR_Pos °Ú+ P #INTCLR_IC_PHY_DRV_CFG_DONE_CLR_Msk ·Ú$ P INTMSK_IC_RNG_DONE_MASK_Pos íÚ$ P INTMSK_IC_RNG_DONE_MASK_Msk ôÚ$ P INTMSK_IC_SEC_DONE_MASK_Pos ùÚ$ P INTMSK_IC_SEC_DONE_MASK_Msk Ú6 P .INTMSK_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_MASK_Pos Ú6 P .INTMSK_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_MASK_Msk Ú, P $INTMSK_IC_PHY_DRV_CFG_DONE_MASK_Pos YÚ, P $INTMSK_IC_PHY_DRV_CFG_DONE_MASK_Msk `Ú P INTR4_IC_CLR_IRQ_Pos +Ú P INTR4_IC_CLR_IRQ_Msk 2Ú( P INTR4_IC_ONE_PULSE_FLAG_IRQ_Pos ³Ú( P INTR4_IC_ONE_PULSE_FLAG_IRQ_Msk ºÚ P INTR4_IC_MODE_IRQ_Pos åÚ P INTR4_IC_MODE_IRQ_Msk ìÚ P INTR4_IC_PULSE_CNT_Pos Ú P INTR4_IC_PULSE_CNT_Msk Ú. P &ACTTMR1_ACTTMR_CMPR_MAX_EVENT_DIN_Pos ÙÚ. P &ACTTMR1_ACTTMR_CMPR_MAX_EVENT_DIN_Msk àÚ' P ACTTMR2_ACTTMR_DISABLE_FLG_Pos LÚ' P ACTTMR2_ACTTMR_DISABLE_FLG_Msk SÚ& P ACTTMR2_ACT_CLK_ACCUR_FLG_Pos Ú& P ACTTMR2_ACT_CLK_ACCUR_FLG_Msk Ú- P %ACTTMR2_ACTTMR_CMPR_MAX_EVENT_EN_Pos "Ú- P %ACTTMR2_ACTTMR_CMPR_MAX_EVENT_EN_Msk )Ú/ P 'ACTTMR6_ACTTMR_CMPR_STRT_EVENT_DIN_Pos kÚ/ P 'ACTTMR6_ACTTMR_CMPR_STRT_EVENT_DIN_Msk rÚ* P "ACTTMR7_ACTTMR_CPTUR_BUS_DOUT_Pos ûÚ* P "ACTTMR7_ACTTMR_CPTUR_BUS_DOUT_Msk Ú# P SECURE1_SEC_DECRYPT_EN_Pos hÚ# P SECURE1_SEC_DECRYPT_EN_Msk oÚ P SECURE1_SEC_AD_LEN_Pos ºÚ P SECURE1_SEC_AD_LEN_Msk ÁÚ P SECURE1_SEC_MIC_LEN_Pos dÚ P SECURE1_SEC_MIC_LEN_Msk kÚ P SECURE1_SEC_VLD_MAC_Pos eÚ P SECURE1_SEC_VLD_MAC_Msk lÚ$ P SECURE1_SEC_PKT_ENABLES_Pos +Ú$ P SECURE1_SEC_PKT_ENABLES_Msk 2Ú P SECURE1_SEC_MODE_Pos \Ú P SECURE1_SEC_MODE_Msk cÚ P SECURE1_SEC_ENABLE_Pos ÖÚ P SECURE1_SEC_ENABLE_Msk ÝÚ P SECURE2_SEC_IV3_Pos °Ú P SECURE2_SEC_IV3_Msk ·Ú P SECURE2_SEC_IV2_Pos ±Ú P SECURE2_SEC_IV2_Msk ¸Ú P SECURE2_SEC_IV1_Pos ²Ú P SECURE2_SEC_IV1_Msk ¹Ú P SECURE2_SEC_IV0_Pos ³Ú P SECURE2_SEC_IV0_Msk ºÚ P SECURE3_SEC_IV7_Pos «Ú P SECURE3_SEC_IV7_Msk ²Ú P SECURE3_SEC_IV6_Pos ¬Ú P SECURE3_SEC_IV6_Msk ³Ú P SECURE3_SEC_IV5_Pos Ú P SECURE3_SEC_IV5_Msk ´Ú P SECURE3_SEC_IV4_Pos ®Ú P SECURE3_SEC_IV4_Msk µÚ% P SECURE4_SEC_KEY2_RX_ADDR_Pos ÐÚ% P SECURE4_SEC_KEY2_RX_ADDR_Msk ×Ú% P SECURE4_SEC_KEY1_RX_ADDR_Pos ÑÚ% P SECURE4_SEC_KEY1_RX_ADDR_Msk ØÚ% P SECURE5_SEC_KEY4_RX_ADDR_Pos ÍÚ% P SECURE5_SEC_KEY4_RX_ADDR_Msk ÔÚ% P SECURE5_SEC_KEY3_RX_ADDR_Pos ÎÚ% P SECURE5_SEC_KEY3_RX_ADDR_Msk ÕÚ% P SECURE6_SEC_KEY6_RX_ADDR_Pos ÊÚ% P SECURE6_SEC_KEY6_RX_ADDR_Msk ÑÚ% P SECURE6_SEC_KEY5_RX_ADDR_Pos ËÚ% P SECURE6_SEC_KEY5_RX_ADDR_Msk ÒÚ P SECURE7_SEC_MD_LEN_Pos ¨Ú P SECURE7_SEC_MD_LEN_Msk ¯Ú% P SECURE7_SEC_KEY7_RX_ADDR_Pos ÈÚ% P SECURE7_SEC_KEY7_RX_ADDR_Msk ÏÚ' P SECURE7_SEC_PKT_CNT_TX_MSB_Pos èÚ' P SECURE7_SEC_PKT_CNT_TX_MSB_Msk ïÚ' P SECURE8_SEC_PKT_CNT_TX_LSB_Pos èÚ' P SECURE8_SEC_PKT_CNT_TX_LSB_Msk ïÚ' P SECURE9_SEC_PKT_CNT_RX_MSB_Pos èÚ' P SECURE9_SEC_PKT_CNT_RX_MSB_Msk ïÚ( P SECURE10_SEC_PKT_CNT_RX_LSB_Pos ¿Ú( P SECURE10_SEC_PKT_CNT_RX_LSB_Msk ÆÚ) P !TEST_MUX00_TST_MUX_SELECT_03_Pos mÚ) P !TEST_MUX00_TST_MUX_SELECT_03_Msk tÚ) P !TEST_MUX00_TST_MUX_SELECT_02_Pos nÚ) P !TEST_MUX00_TST_MUX_SELECT_02_Msk uÚ) P !TEST_MUX00_TST_MUX_SELECT_01_Pos oÚ) P !TEST_MUX00_TST_MUX_SELECT_01_Msk vÚ) P !TEST_MUX00_TST_MUX_SELECT_00_Pos pÚ) P !TEST_MUX00_TST_MUX_SELECT_00_Msk wÚ$ P RNG1_RNG_RING_SCRMB_SEL_Pos þÚ$ P RNG1_RNG_RING_SCRMB_SEL_Msk Ú P RNG1_RNG_EN_Pos ÌÚ P RNG1_RNG_EN_Msk ÓÚ P RNG2_RNG_DATA_Pos @Ú P RNG2_RNG_DATA_Msk GÚ# P LL_MAC_CTRL_CTRL_LL_EN_Pos -Ú# P LL_MAC_CTRL_CTRL_LL_EN_Msk 4Ú) P !TEST_MUX01_TST_MUX_SELECT_07_Pos hÚ) P !TEST_MUX01_TST_MUX_SELECT_07_Msk oÚ) P !TEST_MUX01_TST_MUX_SELECT_06_Pos iÚ) P !TEST_MUX01_TST_MUX_SELECT_06_Msk pÚ) P !TEST_MUX01_TST_MUX_SELECT_05_Pos jÚ) P !TEST_MUX01_TST_MUX_SELECT_05_Msk qÚ) P !TEST_MUX01_TST_MUX_SELECT_04_Pos kÚ) P !TEST_MUX01_TST_MUX_SELECT_04_Msk rÚ) P !TEST_MUX02_TST_MUX_SELECT_11_Pos lÚ) P !TEST_MUX02_TST_MUX_SELECT_11_Msk sÚ) P !TEST_MUX02_TST_MUX_SELECT_10_Pos mÚ) P !TEST_MUX02_TST_MUX_SELECT_10_Msk tÚ) P !TEST_MUX02_TST_MUX_SELECT_09_Pos eÚ) P !TEST_MUX02_TST_MUX_SELECT_09_Msk lÚ) P !TEST_MUX02_TST_MUX_SELECT_08_Pos fÚ) P !TEST_MUX02_TST_MUX_SELECT_08_Msk mÚ) P !TEST_MUX03_TST_MUX_SELECT_15_Pos gÚ) P !TEST_MUX03_TST_MUX_SELECT_15_Msk nÚ) P !TEST_MUX03_TST_MUX_SELECT_14_Pos hÚ) P !TEST_MUX03_TST_MUX_SELECT_14_Msk oÚ) P !TEST_MUX03_TST_MUX_SELECT_13_Pos iÚ) P !TEST_MUX03_TST_MUX_SELECT_13_Msk pÚ) P !TEST_MUX03_TST_MUX_SELECT_12_Pos jÚ) P !TEST_MUX03_TST_MUX_SELECT_12_Msk qÚ# P R00_CTL_TX_PAYLOAD_LEN_Pos `Ú# P R00_CTL_TX_PAYLOAD_LEN_Msk gÚ# P R00_CTL_RX_PAYLOAD_LEN_Pos bÚ# P R00_CTL_RX_PAYLOAD_LEN_Msk iÚ# P R00_CTL_CRC_ACCESS_ADR_Pos Ú# P R00_CTL_CRC_ACCESS_ADR_Msk Ú P R00_CTL_CRC24_EN_Pos Ú P R00_CTL_CRC24_EN_Msk Ú" P R00_CTL_ADDR_BYTE_LEN_Pos ÉÚ" P R00_CTL_ADDR_BYTE_LEN_Msk ÐÚ P R00_CTL_DPY_EN_Pos äÚ P R00_CTL_DPY_EN_Msk ëÚ P R00_CTL_CRC_EN_Pos ùÚ P R00_CTL_CRC_EN_Msk Ú P R00_CTL_CRC_SEL16_Pos ;Ú P R00_CTL_CRC_SEL16_Msk BÚ P R00_CTL_SCR_EN_Pos éÚ P R00_CTL_SCR_EN_Msk ðÚ P R00_CTL_NRF_ENHANCE_Pos Ú P R00_CTL_NRF_ENHANCE_Msk Ú P R00_CTL_ENHANCE_Pos ÏÚ P R00_CTL_ENHANCE_Msk ÖÚ P R00_CTL_BW_MODE_Pos ¤Ú P R00_CTL_BW_MODE_Msk «Ú P R00_CTL_CHIP_MODE_Pos Ú P R00_CTL_CHIP_MODE_Msk Ú& P R00_CTL_RX_ACK_PAYLOAD_EN_Pos zÚ& P R00_CTL_RX_ACK_PAYLOAD_EN_Msk Ú P R00_CTL_TX_NOACK_EN_Pos PÚ P R00_CTL_TX_NOACK_EN_Msk WÚ P R00_CTL_PRI_RX_Pos ÏÚ P R00_CTL_PRI_RX_Msk ÖÚ P R01_INT_PRI_RX_PID_Pos Ú P R01_INT_PRI_RX_PID_Msk Ú P R01_INT_PRI_TX_PID_Pos Ú P R01_INT_PRI_TX_PID_Msk Ú" P R01_INT_RX_LENGTH_ERR_Pos Ú" P R01_INT_RX_LENGTH_ERR_Msk Ú# P R01_INT_RX_ACCADDR_ERR_Pos wÚ# P R01_INT_RX_ACCADDR_ERR_Msk ~Ú( P R01_INT_RX_ACCADDR_ERR_MASK_Pos âÚ( P R01_INT_RX_ACCADDR_ERR_MASK_Msk éÚ' P R01_INT_RX_LENGTH_ERR_MASK_Pos Ú' P R01_INT_RX_LENGTH_ERR_MASK_Msk Ú P R01_INT_PRI_ENDIAN_Pos ¹Ú P R01_INT_PRI_ENDIAN_Msk ÀÚ' P R01_INT_PRI_TX_DONE_IRQ_EN_Pos êÚ' P R01_INT_PRI_TX_DONE_IRQ_EN_Msk ñÚ' P R01_INT_PRI_RX_DONE_IRQ_EN_Pos ìÚ' P R01_INT_PRI_RX_DONE_IRQ_EN_Msk óÚ P R01_INT_PRI_RX_GOON_Pos *Ú P R01_INT_PRI_RX_GOON_Msk 1Ú P R01_INT_PRI_RST_Pos uÚ P R01_INT_PRI_RST_Msk |Ú P R01_INT_EXIT_RX_Pos uÚ P R01_INT_EXIT_RX_Msk |Ú% P R01_INT_TX_DONE_IRQ_FLAG_Pos ±Ú% P R01_INT_TX_DONE_IRQ_FLAG_Msk ¸Ú% P R01_INT_RX_DONE_IRQ_FLAG_Pos ³Ú% P R01_INT_RX_DONE_IRQ_FLAG_Msk ºÚ( P R01_INT_RX_PID_ERR_IRQ_FLAG_Pos ®Ú( P R01_INT_RX_PID_ERR_IRQ_FLAG_Msk µÚ P R01_INT_RX_CRC_ERR_Pos Ú P R01_INT_RX_CRC_ERR_Msk Ú# P R01_INT_TX_TIMEOUT_IRQ_Pos -Ú# P R01_INT_TX_TIMEOUT_IRQ_Msk 4Ú P R01_INT_TX_IRQ_Pos ÃÚ P R01_INT_TX_IRQ_Msk ÊÚ P R01_INT_RX_IRQ_Pos ÅÚ P R01_INT_RX_IRQ_Msk ÌÚ P R01_INT_IRQ_CLR_EN_Pos Ú P R01_INT_IRQ_CLR_EN_Msk Ú$ P R01_INT_RX_CRC_ERR_MASK_Pos ôÚ$ P R01_INT_RX_CRC_ERR_MASK_Msk ûÚ! P R01_INT_PID_ERR_MASK_Pos þÚ! P R01_INT_PID_ERR_MASK_Msk Ú( P R01_INT_TX_TIMEOUT_IRQ_MASK_Pos Ú( P R01_INT_TX_TIMEOUT_IRQ_MASK_Msk Ú P R01_INT_TX_IRQ_MASK_Pos .Ú P R01_INT_TX_IRQ_MASK_Msk 5Ú P R01_INT_RX_IRQ_MASK_Pos 0Ú P R01_INT_RX_IRQ_MASK_Msk 7Ú% P R01_INT_MULTI_RX_ACC_ADR_Pos ¶Ú% P R01_INT_MULTI_RX_ACC_ADR_Msk ½Ú% P R02_TMR_CTL_RX_WAIT_TIME_Pos Ú% P R02_TMR_CTL_RX_WAIT_TIME_Msk Ú( P R02_TMR_CTL_RX_WAIT_TIME_EN_Pos Ú( P R02_TMR_CTL_RX_WAIT_TIME_EN_Msk Ú, P $R02_TMR_CTL_TRX_TRANS_WAIT_TIME_Pos FÚ, P $R02_TMR_CTL_TRX_TRANS_WAIT_TIME_Msk MÚ P R03_RX_ADDR_L_L32B_Pos ÙÚ P R03_RX_ADDR_L_L32B_Msk àÚ" P R04_RX_CTL_RX_HEADER1_Pos ÅÚ" P R04_RX_CTL_RX_HEADER1_Msk ÌÚ! P R04_RX_CTL_RX_HEADER_Pos øÚ! P R04_RX_CTL_RX_HEADER_Msk ÿÚ P R04_RX_CTL_RX_FEC_Pos ÙÚ P R04_RX_CTL_RX_FEC_Msk àÚ P R04_RX_CTL_TX_FEC_Pos ×Ú P R04_RX_CTL_TX_FEC_Msk ÞÚ P R04_RX_CTL_CI_MODE_Pos Ú P R04_RX_CTL_CI_MODE_Msk ¥Ú! P R04_RX_CTL_NORMAL_M1_Pos Ú! P R04_RX_CTL_NORMAL_M1_Msk Ú$ P R04_RX_CTL_HDR_LEN_NUMB_Pos ÷Ú$ P R04_RX_CTL_HDR_LEN_NUMB_Msk þÚ% P R04_RX_CTL_HDR_LEN_EXIST_Pos Ú% P R04_RX_CTL_HDR_LEN_EXIST_Msk ¡Ú P R04_RX_CTL_M8B_Pos ïÚ P R04_RX_CTL_M8B_Msk öÚ P R05_TX_ADDR_L_L32B_Pos ÕÚ P R05_TX_ADDR_L_L32B_Msk ÜÚ" P R06_TX_CTL_RX_HEADER1_Pos ÁÚ" P R06_TX_CTL_RX_HEADER1_Msk ÈÚ! P R06_TX_CTL_RX_HEADER_Pos ôÚ! P R06_TX_CTL_RX_HEADER_Msk ûÚ% P R06_TX_CTL_MAX_LENGTH_EN_Pos ¥Ú% P R06_TX_CTL_MAX_LENGTH_EN_Msk ¬Ú& P R06_TX_CTL_WHITENING_INIT_Pos \Ú& P R06_TX_CTL_WHITENING_INIT_Msk cÚ P R06_TX_CTL_M8B_Pos ëÚ P R06_TX_CTL_M8B_Msk òÚ' P R07_SRAM_CTL_RX_START_ADDR_Pos Ú' P R07_SRAM_CTL_RX_START_ADDR_Msk Ú" P R07_SRAM_CTL_RX_READY_Pos Ú" P R07_SRAM_CTL_RX_READY_Msk ¥Ú' P R07_SRAM_CTL_TX_START_ADDR_Pos ÿÚ' P R07_SRAM_CTL_TX_START_ADDR_Msk Ú" P R07_SRAM_CTL_TX_READY_Pos Ú" P R07_SRAM_CTL_TX_READY_Msk £Ú P R0F_RX_ADDR4_M8B_Pos mÚ P R0F_RX_ADDR4_M8B_Msk tÚ P R0F_RX_ADDR3_M8B_Pos nÚ P R0F_RX_ADDR3_M8B_Msk uÚ P R0F_RX_ADDR2_M8B_Pos oÚ P R0F_RX_ADDR2_M8B_Msk vÚ P R0F_RX_ADDR1_M8B_Pos pÚ P R0F_RX_ADDR1_M8B_Msk wÚ P R10_RX_ADDR7_EN_Pos µÚ P R10_RX_ADDR7_EN_Msk ¼Ú P R10_RX_ADDR6_EN_Pos ¶Ú P R10_RX_ADDR6_EN_Msk ½Ú P R10_RX_ADDR5_EN_Pos ·Ú P R10_RX_ADDR5_EN_Msk ¾Ú P R10_RX_ADDR4_EN_Pos ¸Ú P R10_RX_ADDR4_EN_Msk ¿Ú P R10_RX_ADDR3_EN_Pos ¹Ú P R10_RX_ADDR3_EN_Msk ÀÚ P R10_RX_ADDR2_EN_Pos ºÚ P R10_RX_ADDR2_EN_Msk ÁÚ P R10_RX_ADDR1_EN_Pos »Ú P R10_RX_ADDR1_EN_Msk ÂÚ P R10_RX_ADDR0_EN_Pos ¼Ú P R10_RX_ADDR0_EN_Msk ÃÚ P R10_RX_ADDR7_M8B_Pos Ú P R10_RX_ADDR7_M8B_Msk Ú P R10_RX_ADDR6_M8B_Pos Ú P R10_RX_ADDR6_M8B_Msk Ú P R10_RX_ADDR5_M8B_Pos Ú P R10_RX_ADDR5_M8B_Msk Ú P R11_CFG_NRF_PRE_SEL_Pos [Ú P R11_CFG_NRF_PRE_SEL_Msk bÚ# P R11_CFG_RX_DATA_REV_EN_Pos cÚ# P R11_CFG_RX_DATA_REV_EN_Msk jÚ$ P R11_CFG_PRE_SYNC_12B_EN_Pos IÚ$ P R11_CFG_PRE_SYNC_12B_EN_Msk PÚ# P R11_CFG_PRE_SYNC_8B_EN_Pos vÚ# P R11_CFG_PRE_SYNC_8B_EN_Msk }Ú# P R11_CFG_PRE_SYNC_4B_EN_Pos zÚ# P R11_CFG_PRE_SYNC_4B_EN_Msk Ú P R11_CFG_PRE_SYNC_EN_Pos UÚ P R11_CFG_PRE_SYNC_EN_Msk \Ú! P R11_CFG_250K_MODE_EN_Pos pÚ! P R11_CFG_250K_MODE_EN_Msk wÚ" P R11_CFG_B250K_PRE_SEL_Pos Ú" P R11_CFG_B250K_PRE_SEL_Msk Ú P R11_CFG_LQI_EN_Pos üÚ P R11_CFG_LQI_EN_Msk Ú" P R11_CFG_RX_PID_MANUAL_Pos ÃÚ" P R11_CFG_RX_PID_MANUAL_Msk ÊÚ" P R11_CFG_TX_PID_MANUAL_Pos ÁÚ" P R11_CFG_TX_PID_MANUAL_Msk ÈÚ# P R11_CFG_PREAM_2BYTE_EN_Pos Ú# P R11_CFG_PREAM_2BYTE_EN_Msk Ú$ P R11_CFG_B250K_INVERT_EN_Pos uÚ$ P R11_CFG_B250K_INVERT_EN_Msk |Ú) P !R11_CFG_B250K_SCR_INIT_VALUE_Pos ÞÚ) P !R11_CFG_B250K_SCR_INIT_VALUE_Msk åÚ P R11_CFG_B250K_PREAM_Pos ÒÚ P R11_CFG_B250K_PREAM_Msk ÙÚ P R11_CFG_B250K_MODE_Pos $Ú P R11_CFG_B250K_MODE_Msk +Ú! P R11_CFG_ADDR_ERR_THR_Pos Ú! P R11_CFG_ADDR_ERR_THR_Msk Ú" P R11_CFG_PID_MANUAL_EN_Pos ÚÚ" P R11_CFG_PID_MANUAL_EN_Msk áÚ! P R11_CFG_ADDR_SCR_DIS_Pos 'Ú! P R11_CFG_ADDR_SCR_DIS_Msk .Ú P CR_BASE ®Ú P
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SRAM_BASE Ú P AHB1_PERIPH_BASE Ú P APB1_PERIPH_BASE Ú P APB2_PERIPH_BASE Ú P BLE_PERIPH_BASE 9Ú P
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I2C0_BASE QÚ P
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SPI0_BASE #Ú P UART0_BASE ÑÚ P PWM_BASE MÚ P ADC_BASE yÚ P WDT_BASE RÚ P
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WWDT_BASE ùÚ P TIMER0_BASE Ú P
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SPI1_BASE "Ú P UART1_BASE ÐÚ P TIMER1_BASE Ú P TIMER2_BASE Ú P
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TRIM_BASE Ú P
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GPIO_BASE Ú P P0_BASE ÃÚ P P1_BASE ÂÚ P P2_BASE ÁÚ P P3_BASE ÀÚ P GPIO_DBNCECON_BASE cÚ P GPIOBIT0_BASE ùÚ P GPIOBIT1_BASE øÚ P GPIOBIT2_BASE ÷Ú P GPIOBIT3_BASE öÚ P SYS_BASE BÚ P CLK_BASE gÚ P FLCTL_BASE ÈÚ P FLCTL_BASE1 Ú P DMA_BASE oÚ P ANA_BASE qÚ P EFUSE_BASE ÅÚ P USB_BASE WÚ P USBDMA_BASE Ú P PRI_RF_BASE YÚ P CR 2Ú P I2C0 ÕÚ P SPI0 §Ú P UART0 UÚ P PWM ÑÚ P ADC ýÚ P WDT ÖÚ P WWDT }Ú P TIMER0 Ú P SPI1 ¦Ú P UART1 TÚ P TIMER1 Ú P TIMER2 Ú P TRIM Ú P GPIO Ú P P0 GÚ P P1 FÚ P P2 EÚ P P3 DÚ P GPIO_DB ©Ú P SYS ÆÚ P CLK ëÚ P FLCTL LÚ P FLCTL_BUFF ÀÚ P DMA óÚ P ANA õÚ P EFUSE IÚ P USB ÛÚ P USBDMA Ú P PRI_RF ÝÚ P __ZEPHYR__ WÚ P TRUE Ú P FALSE VÚ P BIT0 ´Ú P BIT1 ³Ú P BIT2 ²Ú P BIT3 ±Ú P BIT4 °Ú P BIT5 ¯Ú P BIT6 ®Ú P BIT7 Ú P BIT8 ¬Ú P BIT9 «Ú P BIT10 Ú P BIT11 Ú P BIT12 Ú P BIT13 ~Ú P BIT14 }Ú P BIT15 |Ú P BIT16 {Ú P BIT17 zÚ P BIT18 yÚ P BIT19 xÚ P BIT20 Ú P BIT21 Ú P BIT22 ~Ú P BIT23 }Ú P BIT24 |Ú P BIT25 {Ú P BIT26 zÚ P BIT27 yÚ P BIT28 xÚ P BIT29 wÚ P BIT30 Ú P BIT31 ~Ú P BIT æÚ P
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BYTE0_Msk ËÚ P
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BYTE1_Msk ÊÚ P
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BYTE2_Msk ÉÚ P
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BYTE3_Msk ÈÚ P
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GET_BYTE0 Ú P
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GET_BYTE1 Ú P
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GET_BYTE2 Ú P
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GET_BYTE3 Ú P SET_BIT Ú P
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CLEAR_BIT Ú P READ_BIT aÚ P
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CLEAR_REG Ú P
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WRITE_REG ñÚ P READ_REG bÚ P MODIFY_REG ²Ú P USE_FULL_ASSERT ûÚ P assert_param ±Ú P FREQ_RCL MÚ P FREQ_XTL 6Ú NVIC_SystemReset ½Ú P __PAN_SYS_LOG_H__ Ú P DBG_ON öÚ P INFO_ON Ú P WARN_ON Ú P ERR_ON ÚÚ P TEST_ON Ú P
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ASSERT_ON ëÚ P
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SYS_ABORT ãÚ P LOG ãÚ P SYS_DBG Ú P SYS_INFO 1Ú P SYS_WARN %Ú P SYS_TEST Ú P SYS_ERR vÚ P SYS_ASSERT Ú , file )Ú ,
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line /Ú SYS_AssertError ðÚ P __PAN_SYS_H__ QÚ P SYS_MFP_TYPE_Msk ?Ú P SYS_MFP_ALT_Msk ¢Ú P SYS_MFP_MFP_Msk Ú P SYS_MFP_GPIO äÚ P SYS_MFP_P00_GPIO ÍÚ P SYS_MFP_P00_SWD_CLK ÏÚ P SYS_MFP_P00_UART1_RX ~Ú P SYS_MFP_P00_I2C0_SCL ÅÚ P SYS_MFP_P00_SPI0_CLK Ú P SYS_MFP_P00_LL_DBG_14 jÚ P SYS_MFP_P00_MDM_DBG_11 %Ú P SYS_MFP_P00_RESERVED Ú P SYS_MFP_P00_Msk ÓÚ P SYS_MFP_P01_GPIO ÌÚ P SYS_MFP_P01_SWD_DAT ÏÚ P SYS_MFP_P01_UART1_TX {Ú P SYS_MFP_P01_I2C0_SDA ÎÚ P SYS_MFP_P01_SPI0_CS äÚ P SYS_MFP_P01_LL_DBG_15 hÚ P SYS_MFP_P01_MDM_DBG_12 #Ú P SYS_MFP_P01_RESERVED Ú P SYS_MFP_P01_Msk ÒÚ P SYS_MFP_P02_GPIO ËÚ P SYS_MFP_P02_UART0_CTS ;Ú P SYS_MFP_P02_SPI1_MISO <Ú P SYS_MFP_P02_PWM_CH3 ãÚ P SYS_MFP_P02_UART1_CTS :Ú P SYS_MFP_P02_LL_DBG_8 Ú P SYS_MFP_P02_MDM_DBG_19 Ú P SYS_MFP_P02_RESERVED Ú P SYS_MFP_P02_Msk ÑÚ P SYS_MFP_P03_GPIO ÊÚ P SYS_MFP_P03_UART0_CTS :Ú P SYS_MFP_P03_SPI0_CS âÚ P SYS_MFP_P03_PWM_CH2 ãÚ# P SYS_MFP_P03_TIMER0_CNT_OUT Ú P SYS_MFP_P03_LL_DBG_8 Ú P SYS_MFP_P03_MDM_DBG_5 QÚ P SYS_MFP_P03_RESERVED Ú P SYS_MFP_P03_Msk ÐÚ P SYS_MFP_P04_GPIO ÉÚ P SYS_MFP_P04_UART0_RTS *Ú P SYS_MFP_P04_SPI0_CLK Ú P SYS_MFP_P04_PWM_CH3 áÚ P SYS_MFP_P04_TIMER0_EXT ëÚ P SYS_MFP_P04_LL_DBG_9 Ú P SYS_MFP_P04_MDM_DBG_6 OÚ P SYS_MFP_P04_RESERVED Ú P SYS_MFP_P04_Msk ÏÚ P SYS_MFP_P05_GPIO ÈÚ P SYS_MFP_P05_UART0_TX xÚ P SYS_MFP_P05_SPI0_MISO :Ú P SYS_MFP_P05_PWM_CH4 ßÚ P SYS_MFP_P05_EXT_STADC .Ú P SYS_MFP_P05_LL_DBG_12 gÚ P SYS_MFP_P05_MDM_DBG_9 KÚ P SYS_MFP_P05_RESERVED Ú P SYS_MFP_P05_Msk ÎÚ P SYS_MFP_P06_GPIO ÇÚ P SYS_MFP_P06_UART0_RX yÚ P SYS_MFP_P06_SPI0_MISO 9Ú P SYS_MFP_P06_PWM_CH5 ÝÚ P SYS_MFP_P06_TIMER1_EXT èÚ P SYS_MFP_P06_LL_DBG_13 eÚ P SYS_MFP_P06_MDM_DBG_3 PÚ P SYS_MFP_P06_AHB_CLK ìÚ P SYS_MFP_P06_Msk ÍÚ P SYS_MFP_P07_GPIO ÆÚ P SYS_MFP_P07_UART1_RX wÚ P SYS_MFP_P07_I2C0_SCL ¾Ú P SYS_MFP_P07_SPI0_MOSI 8Ú P SYS_MFP_P07_PWM_CH0 áÚ P SYS_MFP_P07_LL_DBG_10 gÚ P SYS_MFP_P07_MDM_DBG_7 KÚ P SYS_MFP_P07_RESERVED Ú P SYS_MFP_P07_Msk ÌÚ P SYS_MFP_P10_GPIO ÌÚ P SYS_MFP_P10_UART1_TX {Ú P SYS_MFP_P10_I2C0_SDA ÎÚ P SYS_MFP_P10_SPI0_MISO >Ú P SYS_MFP_P10_PWM_CH5 âÚ P SYS_MFP_P10_LL_DBG_11 lÚ P SYS_MFP_P10_MDM_DBG_8 PÚ P SYS_MFP_P10_RESERVED Ú P SYS_MFP_P10_Msk ÒÚ P SYS_MFP_P11_GPIO ËÚ P SYS_MFP_P11_UART1_RTS +Ú P SYS_MFP_P11_SPI0_MOSI =Ú P SYS_MFP_P11_PWM_CH7 ßÚ P SYS_MFP_P11_CLK_32K Ú P SYS_MFP_P11_LL_DBG_9 Ú P SYS_MFP_P11_MDM_DBG_0 WÚ P SYS_MFP_P11_UART0_TX {Ú P SYS_MFP_P11_Msk ÑÚ P SYS_MFP_P12_GPIO ÊÚ P SYS_MFP_P12_UART0_RX |Ú P SYS_MFP_P12_PWM_CH4 áÚ# P SYS_MFP_P12_TIMER0_CNT_OUT Ú P SYS_MFP_P12_UART1_TX yÚ P SYS_MFP_P12_LL_DBG_4 Ú P SYS_MFP_P12_MDM_DBG_17 Ú P SYS_MFP_P12_SPI0_MISO <Ú P SYS_MFP_P12_Msk ÐÚ P SYS_MFP_P13_GPIO ÉÚ P SYS_MFP_P13_UART0_RTS *Ú P SYS_MFP_P13_I2C0_SDA ËÚ P SYS_MFP_P13_PWM_CH3 áÚ P SYS_MFP_P13_LL_DBG_3 Ú P SYS_MFP_P13_MDM_DBG_16 Ú P SYS_MFP_P13_SPI1_CS àÚ P SYS_MFP_P13_SPI0_CS áÚ P SYS_MFP_P13_Msk ÏÚ P SYS_MFP_P14_GPIO ÈÚ P SYS_MFP_P14_UART0_CTS 8Ú P SYS_MFP_P14_I2C0_SCL ÀÚ P SYS_MFP_P14_PWM_CH2 áÚ P SYS_MFP_P14_LL_DEBUG_2 üÚ P SYS_MFP_P14_MDM_DBG_15 Ú P SYS_MFP_P14_SPI0_CLK Ú P SYS_MFP_P14_RESERVED Ú P SYS_MFP_P14_Msk ÎÚ P SYS_MFP_P15_GPIO ÇÚ P SYS_MFP_P15_SPI0_CS ßÚ P SYS_MFP_P15_PWM_CH5 ÝÚ P SYS_MFP_P15_TIMER0_EXT éÚ P SYS_MFP_P15_UART0_RX yÚ P SYS_MFP_P15_LL_DBG_5 Ú P SYS_MFP_P15_MDM_DBG_18 Ú P SYS_MFP_P15_RESERVED Ú P SYS_MFP_P15_Msk ÍÚ P SYS_MFP_P16_GPIO ÆÚ P SYS_MFP_P16_UART0_TX vÚ# P SYS_MFP_P16_TIMER2_CNT_OUT Ú P SYS_MFP_P16_PWM_CH0 áÚ P SYS_MFP_P16_LL_DBG_0 Ú P SYS_MFP_P16_MDM_DBG_13 Ú P SYS_MFP_P16_SPI1_CLK Ú P SYS_MFP_P16_I2C0_SCL ¾Ú P SYS_MFP_P16_Msk ÌÚ P SYS_MFP_P17_GPIO ÅÚ P SYS_MFP_P17_UART0_RX wÚ P SYS_MFP_P17_TIMER2_EXT åÚ P SYS_MFP_P17_PWM_CH1 ßÚ P SYS_MFP_P17_LL_DBG_1 Ú P SYS_MFP_P17_MDM_DBG_14 Ú P SYS_MFP_P17_RCH Ú P SYS_MFP_P17_RESERVED Ú P SYS_MFP_P17_Msk ËÚ P SYS_MFP_P20_GPIO ËÚ P SYS_MFP_P20_SPI1_MISO <Ú P SYS_MFP_P20_PWM_CH6 àÚ P SYS_MFP_P20_TADC_CLK Ú P SYS_MFP_P20_LL_DBG_6 Ú P SYS_MFP_P20_MDM_DBG_2 UÚ P SYS_MFP_P20_XTL_C1_CLK êÚ P SYS_MFP_P20_RESERVED Ú P SYS_MFP_P20_Msk ÑÚ P SYS_MFP_P21_GPIO ÊÚ P SYS_MFP_P21_SPI1_MOSI ;Ú P SYS_MFP_P21_PWM_CH7 ÞÚ P SYS_MFP_P21_TADC_VLD Ú P SYS_MFP_P21_LL_DBG_7 Ú P SYS_MFP_P21_MDM_DBG_1 UÚ P SYS_MFP_P21_XTL_C2_CLK èÚ P SYS_MFP_P21_RESERVED Ú P SYS_MFP_P21_Msk ÐÚ P SYS_MFP_P22_GPIO ÉÚ P SYS_MFP_P22_SPI1_CLK Ú P SYS_MFP_P22_PWM_CH0 äÚ P SYS_MFP_P22_RESERVED Ú P SYS_MFP_P22_TADC_DATl .Ú P SYS_MFP_P22_MDM_DBG_0 UÚ P SYS_MFP_P22_SPI0_MOSI ;Ú P SYS_MFP_P22_RESERVED1 ]Ú P SYS_MFP_P22_Msk ÏÚ P SYS_MFP_P23_GPIO ÈÚ P SYS_MFP_P23_SPI1_CS ßÚ P SYS_MFP_P23_PWM_CH1 âÚ P SYS_MFP_P23_DPLL_DIV8 GÚ P SYS_MFP_P23_TADC_DATH QÚ P SYS_MFP_P23_MDM_DBG_10 !Ú P SYS_MFP_P23_I2C0_SCL ÀÚ P SYS_MFP_P23_RESERVED Ú P SYS_MFP_P23_Msk ÎÚ P SYS_MFP_P24_GPIO ÇÚ P SYS_MFP_P24_SPI1_MISO 8Ú P SYS_MFP_P24_UART1_RX xÚ P SYS_MFP_P24_PWM_CH2 àÚ# P SYS_MFP_P24_TIMER1_CNT_OUT Ú P SYS_MFP_P24_MDM_DBG_4 OÚ P SYS_MFP_P24_RESERVED Ú P SYS_MFP_P24_RESERVED1 [Ú P SYS_MFP_P24_Msk ÍÚ P SYS_MFP_P25_GPIO ÆÚ P SYS_MFP_P25_SPI1_MOSI 7Ú P SYS_MFP_P25_UART1_TX uÚ P SYS_MFP_P25_PWM_CH3 ÞÚ P SYS_MFP_P25_MDM_DBG_5 MÚ P SYS_MFP_P25_RESERVED Ú P SYS_MFP_P25_I2C0_SDA ÈÚ P SYS_MFP_P25_RESERVED1 ZÚ P SYS_MFP_P25_Msk ÌÚ P SYS_MFP_P26_GPIO ÅÚ P SYS_MFP_P26_UART1_RTS %Ú P SYS_MFP_P26_PWM_CH4 ÜÚ P SYS_MFP_P26_SPI1_CS ÜÚ P SYS_MFP_P26_MDM_DBG_4 MÚ P SYS_MFP_P26_MDM_DBG_10 Ú P SYS_MFP_P26_RESERVED Ú P SYS_MFP_P26_RESERVED1 YÚ P SYS_MFP_P26_Msk ËÚ P SYS_MFP_P27_GPIO ÄÚ P SYS_MFP_P27_UART1_CTS 3Ú P SYS_MFP_P27_PWM_CH5 ÚÚ P SYS_MFP_P27_SPI1_CLK Ú P SYS_MFP_P27_RESERVED Ú P SYS_MFP_P27_MDM_DBG_20 Ú P SYS_MFP_P27_XTH Ú P SYS_MFP_P27_RESERVED1 XÚ P SYS_MFP_P27_Msk ÊÚ P SYS_MFP_P30_GPIO ÊÚ P SYS_MFP_P30_UART1_RX {Ú P SYS_MFP_P30_PWM_CH6 ßÚ P SYS_MFP_P30_SPI1_MISO ;Ú P SYS_MFP_P30_MDM_DBG_10 #Ú P SYS_MFP_P30_RESERVED Ú P SYS_MFP_P30_RESERVED1 ^Ú P SYS_MFP_P30_RESERVED2 ]Ú P SYS_MFP_P30_Msk ÐÚ P SYS_MFP_P31_GPIO ÉÚ P SYS_MFP_P31_UART1_TX xÚ P SYS_MFP_P31_PWM_CH7 ÝÚ P SYS_MFP_P31_SPI1_MOSI :Ú P SYS_MFP_P31_RESERVED Ú P SYS_MFP_P31_RESERVED1 ]Ú P SYS_MFP_P31_RESERVED2 \Ú P SYS_MFP_P31_RESERVED3 [Ú P SYS_MFP_P31_Msk ÏÚ P SYS_SET_MFP )Ú SYS_UnlockReg òÚ SYS_LockReg ÙÚ SYS_IsRegLocked @Ú ,
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u32NopCnt ¡Ú SYS_delay_10nop PÚ P __PAN_CLK_H__ vÚ$ P CLK_APB1_WDTSEL_MILLI_PULSE hÚ P CLK_APB1_WDTSEL_RCL32K @Ú% P CLK_APB1_WWDTSEL_MILLI_PULSE Ú P CLK_APB1_WWDTSEL_RCL32K çÚ! P CLK_APB1_TMR0SEL_APB1CLK »Ú P CLK_APB1_TMR0SEL_RCL32K
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Ú P CLK_APB1_TMR0SEL_TM0 ÐÚ! P CLK_APB2_TMR1SEL_APB2CLK ¸Ú P CLK_APB2_TMR1SEL_RCL32K Ú P CLK_APB2_TMR1SEL_TM1 ÍÚ! P CLK_APB2_TMR2SEL_APB2CLK ·Ú P CLK_APB2_TMR2SEL_RCL32K Ú P CLK_APB2_TMR2SEL_TM2 ËÚ" P CLK_APB1_PWM_CH01_SEL_APB IÚ% P CLK_APB1_PWM_CH01_SEL_CLK32K Ú" P CLK_APB1_PWM_CH23_SEL_APB EÚ% P CLK_APB1_PWM_CH23_SEL_CLK32K Ú" P CLK_APB1_PWM_CH45_SEL_APB AÚ% P CLK_APB1_PWM_CH45_SEL_CLK32K Ú" P CLK_APB1_PWM_CH67_SEL_APB =Ú% P CLK_APB1_PWM_CH67_SEL_CLK32K Ú P
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FREQ_1MHZ Ú P
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FREQ_8MHZ Ú P FREQ_16MHZ ÔÚ P FREQ_25MHZ ÔÚ P FREQ_32MHZ ÖÚ P FREQ_48MHZ ÏÚ P FREQ_64MHZ ÑÚ P FREQ_96MHZ ÌÚ P FREQ_50MHZ ÖÚ P FREQ_72MHZ ÒÚ P FREQ_100MHZ ¨Ú P CLK_SYS_SRCSEL_RCH Ú P CLK_SYS_SRCSEL_XTH ñÚ P CLK_SYS_SRCSEL_DPLL ·Ú P CLK_DPLL_REF_CLKSEL_RCH £Ú P CLK_DPLL_REF_CLKSEL_XTH Ú P CLK_DPLL_OUT_48M ×Ú P CLK_DPLL_OUT_64M ÙÚ P CLK_APB1Periph_I2C0 ³Ú P CLK_APB1Periph_SPI0
Ú P CLK_APB1Periph_UART0 3Ú! P CLK_APB1Periph_PWM0_CH01 (Ú! P CLK_APB1Periph_PWM0_CH23 $Ú! P CLK_APB1Periph_PWM0_CH45 Ú! P CLK_APB1Periph_PWM0_CH67 Ú P CLK_APB1Periph_PWM0_EN
Ú P CLK_APB1Periph_ADC ÛÚ P CLK_APB1Periph_WDT ´Ú P CLK_APB1Periph_WWDT [Ú P CLK_APB1Periph_TMR0 ~Ú P CLK_APB1Periph_MILI_CLK 5Ú P CLK_APB1Periph_All Ú P CLK_APB2Periph_SPI1 Ú P CLK_APB2Periph_UART1 1Ú P CLK_APB2Periph_TMR1 |Ú P CLK_APB2Periph_TMR2 {Ú P CLK_APB2Periph_All Ú P CLK_AHBPeriph_DMAC ÇÚ P CLK_AHBPeriph_GPIO Ú P CLK_AHBPeriph_SYSTICK ¬Ú P CLK_AHBPeriph_APB1 ØÚ P CLK_AHBPeriph_APB2 ×Ú P CLK_AHBPeriph_AHB Ú P CLK_AHBPeriph_BLE_32M òÚ P CLK_AHBPeriph_BLE_32K ôÚ P CLK_AHBPeriph_ROM ðÚ P CLK_AHBPeriph_EFUSE bÚ P CLK_AHBPeriph_USB_AHB ÂÚ P CLK_AHBPeriph_USB_48M ÔÚ P CLK_AHBPeriph_All ÅÚ P CLK_DivideSource_Ahb :Ú P CLK_DivideSource_Apb1 ÿÚ P CLK_DivideSource_Apb2 þÚ P CLK_RCL_SELECT vÚ P CLK_RCH_SELECT zÚ P CLK_XTL_SELECT _Ú P CLK_XTH_SELECT cÚ P CLK_DPLL_SELECT )Ú P CLK_STABLE_STATUS_Pos ÙÚ P CLK_STABLE_STATUS_Msk àÚ! P CLKTRIM_CALC_CLK_SEL_32K Ú! P CLKTRIM_CALC_CLK_SEL_32M Ú! P CLKTRIM_QDEC_CLK_SEL_APB [Ú! P CLKTRIM_QDEC_CLK_SEL_32K ~Ú" P CLKTRIM_KSCAN_CLK_SEL_APB Ú" P CLKTRIM_KSCAN_CLK_SEL_32K )Ú P DMA_RST Ú P LL_RST ÏÚ P
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EFUSE_RST éÚ P USB_RST {Ú P MDMSTB_RST Ú P MDM_RST Ú P I2C0_RST uÚ P SPI0_RST GÚ P SPI1_RST FÚ P
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UART0_RST õÚ P
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UART1_RST ôÚ P PWM0_RST ?Ú P ADC_RST Ú P WDT_RST vÚ P WWDT_RST Ú P TMR0_RST @Ú P TMR1_RST ?Ú P TMR2_RST >Ú P GPIO_RST 4Ú P CLKTRIM_RST GÚ P CLK_BODCTL_BOD_INT_EN @Ú P CLK_BODCTL_BOD_RST_EN 2Ú P CLK_BODCTL_BODSEL_1_75V ãÚ P CLK_BODCTL_BODSEL_1_95V áÚ P CLK_BODCTL_BODSEL_2_15V èÚ P CLK_BODCTL_BODSEL_2_35V æÚ P CLK_BODCTL_BODSEL_2_55V äÚ P CLK_BODCTL_BODSEL_2_75V âÚ P CLK_BODCTL_BODSEL_2_95V àÚ# P CLK_BLDBCTL_BODDBSEL_2POW0 Ú# P CLK_BLDBCTL_BODDBSEL_2POW1 Ú# P CLK_BLDBCTL_BODDBSEL_2POW2 Ú# P CLK_BLDBCTL_BODDBSEL_2POW3 Ú# P CLK_BLDBCTL_BODDBSEL_2POW4 Ú# P CLK_BLDBCTL_BODDBSEL_2POW5 Ú# P CLK_BLDBCTL_LVRDBSEL_2POW0 óÚ# P CLK_BLDBCTL_LVRDBSEL_2POW1 òÚ# P CLK_BLDBCTL_LVRDBSEL_2POW2 ñÚ# P CLK_BLDBCTL_LVRDBSEL_2POW3 ðÚ# P CLK_BLDBCTL_LVRDBSEL_2POW4 ïÚ# P CLK_BLDBCTL_LVRDBSEL_2POW5 îÚ CLK_XthStartupConfig Ú CLK_HCLKConfig 'Ú ,
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" þ)
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u32ClkDiv mÚ CLK_PCLK1Config ìÚ ,
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" *
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u32ClkDiv êÚ CLK_PCLK2Config ëÚ ,
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" *
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u32ClkDiv èÚ CLK_SetDpllOutputFreq ºÚ ,
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" *freq YÚ CLK_EnableClkTrim Ú ,"" * NewState ½Ú CLK_SelectClkTrimSrc UÚ ,
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" *src ½Ú CLK_SetClkTrimCalClkDiv ^Ú ," *div ¾Ú
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" *reg éÚ CLK_FLASH_CLKDIV_1 Ú CLK_FLASH_CLKDIV_2
Ú CLK_FLASH_CLKDIV_4 Ú CLK_FLASH_CLKDIV_8 Ú CLK_FLASH_CLKDIV_16 NÚ CLK_FLASH_CLKDIV_32 PÚ CLK_SetFlashClkDiv @Ú ," *div ¾Ú
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" *reg àÚ CLK_GetHCLKFreq ÁÚ CLK_GetCPUFreq ýÚ CLK_GetPCLK1Freq Ú CLK_GetPCLK2Freq
Ú ,
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u32ClkSrc ±Ú CLK_RefClkSrcConfig ÔÚ ,
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u32ClkSrc ±Ú ,
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freq_out jÚ CLK_SYSCLKConfig `Ú ,
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u32ClkDiv ¶Ú ,
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u32ClkDiv ¶Ú ,
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u32ClkDiv ¶Ú ,
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CLK_AHBPeriph YÚ ," NewState Ú CLK_AHBPeriphClockCmd RÚ ,
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CLK_APB1Periph Ú ," NewState Ú CLK_APB1PeriphClockCmd Ú ,
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CLK_APB2Periph Ú ," NewState Ú CLK_APB2PeriphClockCmd Ú ,
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u32ClkMask KÚ CLK_WaitClockReady Ú CLK_Wait3vSyncReady ¹Ú CLK_Set3vSyncAuto Ú ,
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u32clksel uÚ CLK_SetWdtClkSrc òÚ ,
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u32clksel uÚ CLK_SetWwdtClkSrc yÚ , timer ¦Ú ,
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u32clksel uÚ CLK_SetTmrClkSrc îÚ ,
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u32ChNum Ú ,
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u32clksel uÚ CLK_SetPwmClkSrc íÚ , Peripheral ±Ú CLK_GetPeripheralFreq ËÚ CLK_ResetChip Ú! CLK_ResetSystemToRomMode Ú ,
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u32ModuleIndex Ú CLK_ResetModule (Ú , i32Mode Ú ,
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u32BODLevel "Ú CLK_ConfigureBOD Ú CLK_EnableBOD yÚ CLK_DisableBOD
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Ú CLK_GetBODStatus Ú CLK_GetBODIntFlag óÚ CLK_ClearBODIntFlag (Ú ,
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u32BodDBTime ÃÚ CLK_SetBODDebounceTime ÎÚ CLK_EnableLVR ZÚ CLK_DisableLVR ëÚ ,
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u32LvrDBTime ¤Ú CLK_SetLVRDebounceTime ¯Ú P __PAN_ADC_H__ Ú P ADC_INPUTRANGE_HIGH Ú P ADC_INPUTRANGE_LOW 2Ú P ADC_CH8_EXT {Ú P ADC_CH8_BGP Ú P ADC_CMP0_LESS_THAN PÚ P ADC_CMP1_LESS_THAN OÚ% P ADC_CMP0_GREATER_OR_EQUAL_TO Ú% P ADC_CMP1_GREATER_OR_EQUAL_TO Ú P ADC_TRIGGER_BY_EXT_PIN ÔÚ P ADC_TRIGGER_BY_PWM Ú! P ADC_FALLING_EDGE_TRIGGER Ú P ADC_RISING_EDGE_TRIGGER ÃÚ P ADC_ADIF_INT .Ú P ADC_CMP0_INT 2Ú P ADC_CMP1_INT 1Ú P ADC_FIFO_FULL_INT Ú P ADC_FIFO_EMPTY_INT $Ú P ADC_FIFO_OVER_INT yÚ P ADC_FIFO_HALF_INT Ú P ADC_SAMPLE_CLOCK_0 dÚ P ADC_SAMPLE_CLOCK_1 cÚ P ADC_SAMPLE_CLOCK_2 bÚ P ADC_SAMPLE_CLOCK_4 `Ú P ADC_SAMPLE_CLOCK_8 \Ú P ADC_SAMPLE_CLOCK_16 +Ú P ADC_SAMPLE_CLOCK_32 -Ú P ADC_SAMPLE_CLOCK_64 (Ú P ADC_SAMPLE_CLOCK_128 õÚ P ADC_SAMPLE_CLOCK_256 óÚ P ADC_SAMPLE_CLOCK_512 øÚ P ADC_SAMPLE_CLOCK_1024 ÇÚ! P ADC_SEQMODE_TYPE_23SHUNT oÚ P ADC_SEQMODE_TYPE_1SHUNT ¥Ú$ P ADC_SEQMODE_MODESELECT_CH01 ÑÚ$ P ADC_SEQMODE_MODESELECT_CH12 ÏÚ$ P ADC_SEQMODE_MODESELECT_CH02 ÐÚ# P ADC_SEQMODE_MODESELECT_ONE ÝÚ P ADC_SEQMODE_PWM0_RISING ºÚ P ADC_SEQMODE_PWM0_CENTER ÅÚ! P ADC_SEQMODE_PWM0_FALLING Ú P ADC_SEQMODE_PWM0_PERIOD ÃÚ P ADC_SEQMODE_PWM2_RISING ¸Ú P ADC_SEQMODE_PWM2_CENTER ÃÚ! P ADC_SEQMODE_PWM2_FALLING
Ú P ADC_SEQMODE_PWM2_PERIOD ÁÚ P ADC_SEQMODE_PWM4_RISING ¶Ú P ADC_SEQMODE_PWM4_CENTER ÁÚ! P ADC_SEQMODE_PWM4_FALLING Ú P ADC_SEQMODE_PWM4_PERIOD ¿Ú P ADC_SEQMODE_PWM6_RISING ´Ú P ADC_SEQMODE_PWM6_CENTER ¿Ú! P ADC_SEQMODE_PWM6_FALLING Ú P ADC_SEQMODE_PWM6_PERIOD ½Ú P ADC_COMPARATOR_0 ýÚ P ADC_COMPARATOR_1 üÚ! P ADC_FIFO_TRIG_LEVEL_HALF jÚ! P ADC_FIFO_TRIG_LEVEL_FULL RÚ 8
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<unnamed> QÚ " +
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chip_info ]Ú " + ft_version ËÚ " +
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adc_vdd_b Ú " +
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adc_vdd_k tÚ " +
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adc_vbg_k sÚ " +
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adc_vbg_b ~Ú " +adc_temp_volt Ú " +current_temp_value _Ú " +adc_vbg_1v20_trim ³Ú " +
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rsvd_0x30 ãÚ <" + adc_vbg_kb ÇÚ " + adc_vbat_k Ú " + adc_vbat_b Ú " +adc_vbat_dtemp_k Ú " +adc_vbat_dtemp_b Ú " + adc_temp_k òÚ
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" +
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adc_ctrl2 Ú
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" + adc_extsmpt eÚ
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ADC_OPT_T "Ú @
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m_adc_opt õÚ
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global_calc_vbat_mv $Ú , opt xÚ ADC_SetCalirationParams ýÚ ADC_GetConversionData ãÚ ," +ADCx Ú ADC_StatusFlag ³Ú ," ¡+ADCx Ú ,
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" ¡+IntMask ,Ú ADC_ClearStatusFlag ÂÚ ," ¤+ADCx Ú ,
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" ¤+IntMask )Ú ADC_IntMask Ú ," §+ADCx Ú ,
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" §+IntMask &Ú ,"" §+ NewState Ú ADC_IsIntOccured Ú ," «+ADCx Ú ,
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" «+IntMask "Ú ADC_ClearIntFlag !Ú ," ®+ADCx Ú ,
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" ®+IntMask Ú ADC_IsBusy ZÚ ," ±+ADCx Ú ADC_IsDataOverrun Ú ," ³+ADCx Ú ADC_IsDataValid Ú ," µ+ADCx Ú ADC_PowerDown Ú ," ·+ADCx
Ú ADC_PowerOn íÚ ," ¹+ADCx Ú" ADC_SequentialModeDisable GÚ ," »+ADCx Ú ADC_Trigger2Select CÚ ," ½+ADCx Ú ,"" ½+ NewState
Ú ADC_DisableCompare0 üÚ ," À+ADCx |Ú ADC_DisableCompare1 ûÚ ," Â+ADCx zÚ ADC_StartConvert ¾Ú ," Ä+ADCx xÚ ADC_StopConvert (Ú ," Æ+ADCx vÚ ADC_TestModeEnable =Ú ," È+ADCx tÚ ADC_TestModeDisable ÎÚ ," Ê+ADCx rÚ ADC_DmaModeEnable ÍÚ ," Ì+ADCx pÚ ,"" Ì+ NewState vÚ ADC_SetClockDivider ÈÚ ," Ï+ADCx mÚ ,
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" Ï+Divider îÚ ADC_Open +Ú ," Ò+ADCx jÚ ,
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" Ò+ChMask }Ú ADC_SelInputRange Ú ," Õ+ADCx gÚ ,
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" Õ+ EnableHigh âÚ ADC_TriggerDelay êÚ ," Ø+ADCx dÚ ,
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" Ø+Data 8Ú ADC_SetExtraSampleTime Ú ," Û+ADCx aÚ ,
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" Û+ SampleTime ²Ú ADC_IsOneChConvertEnd "Ú ," Þ+ADCx ^Ú ADC_ClearByHw RÚ ," à+ADCx \Ú ,"" à+ NewState bÚ ADC_LeftShiftEn sÚ ," ã+ADCx YÚ ,"" ã+ NewState _Ú ADC_SubtractBiasEn /Ú ," æ+ADCx VÚ ,"" æ+ NewState \Ú ADC_SetBiasData Ú ," é+ADCx SÚ ,
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" é+ BiasData Ú ADC_SetFifoTrigLevel gÚ ," ì+ADCx PÚ ," ì+Level «Ú ADC_SeqModeOneChEn {Ú ," ï+ADCx MÚ ,"" ï+ NewState SÚ , ADCx Ú , buf_en kÚ ADC_Init Ú , ADCx Ú ADC_PrepareVbgCalibData PÚ , ADCx Ú ,
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adc_code Ú ADC_OutputVoltage <Ú , ADCx Ú , sample_buf Ú ,
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sample_cnt ¥Ú ,
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trim_cnt oÚ! ADC_SamplingCodeTrimMean ¾Ú , ADCx Ú" ADC_MeasureSocTemperature
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Ú , ADCx Ú& ADC_MeasureSocTemperatureFast tÚ , ADCx Ú ADC_MeasureSocVbat Ú , ADCx Ú ADC_Disable ÷Ú
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ADC_Close ¹Ú , ADCx Ú ,
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Source bÚ ,
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Param äÚ ADC_EnableHWTrigger áÚ , ADCx Ú ADC_DisableHWTrigger rÚ , ADCx Ú ,
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Mask KÚ ADC_EnableInt 5Ú , ADCx Ú ,
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Mask KÚ ADC_DisableInt ÆÚ , ADCx Ú ,
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SeqTYPE fÚ ,
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ModeSel (Ú ADC_SeqModeEnable ªÚ , ADCx Ú ,
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SeqModeTriSrc ÀÚ ADC_SeqModeTriggerSrc íÚ , ADCx Ú ,
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ChNum úÚ ,
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CmpCondition Ú ,
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CmpData 7Ú ,
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MatchCnt ½Ú ,
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CmpSelect MÚ ADC_CompareEnable Ú , ADCx Ú ,
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Trig AÚ , Level äÚ , DmaEn Ú , HwClrEN eÚ ADC_SeqOneChModeConfig ÄÚ P __PAN_FMC_H__ zÚ P M32 Ú P CMD_ERASE_PAGE Ú P CMD_ERASE_SECTOR ÙÚ P CMD_ERASE_32K ÿÚ P CMD_ERASE_64K úÚ P CMD_ERASE_CHIP Ú P CMD_READ_STATUS_L lÚ P CMD_READ_STATUS_H pÚ P CMD_WRITE_STATUS ªÚ P OPS_WR_STU_REG_NOR ÇÚ P OPS_WR_STU_REG_ALL ÝÚ P CMD_FAST_READ ÕÚ P CMD_NORM_READ ÇÚ P
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CMD_DREAD &Ú P
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CMD_2READ 8Ú P
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CMD_QREAD Ú P
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CMD_4READ 6Ú P CMD_BURST_READ qÚ P BURST_READ_MODE_8 Ú P BURST_READ_MODE_16 RÚ P BURST_READ_MODE_32 TÚ P BURST_READ_MODE_64 OÚ P CMD_TRIG RÚ P CMD_WRITE_ENABLE çÚ P CMD_WRITE_DISABLE Ú P FLASH_X1_MODE ×Ú P FLASH_X2_MODE ÖÚ P FLASH_X4_MODE ÔÚ P QUAD_ENABLE_Pos ëÚ P QUAD_ENABLE_Msk òÚ P Write_Enable_Latch_Pos Ú P Write_Enable_Latch_Msk Ú P Write_In_Process_Pos ³Ú P Write_In_Process_Msk ºÚ P Long_Time_Op_Pos ~Ú P
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PAGE_SIZE Ú P SECTOR_SIZE KÚ 8 _flash_ids ¥Ú " Î,manufacturer_id Ú 8
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<unnamed> SÚ <" Ð,d 7Ú 8
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<unnamed> QÚ " Ò,memory_type_id ÐÚ " Ò,memory_density_id Ú <" Î,uid IÚ FLASH_IDS_T Ú
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flash_ids Ú# FMC_EnterDeepPowerDownMode åÚ ," Ø,fmc oÚ" FMC_ExitDeepPowerDownMode KÚ ," Ú,fmc mÚ , fmc Ú FMC_GetFlashUniqueId YÚ , fmc Ú FMC_GetFlashJedecId ÷Ú , fmc Ú FMC_SetFlashCapacity CÚ , fmc Ú! FMC_GetFlashCodeAreaSize æÚ , fmc Ú , adr Ú FMC_EraseSector 5Ú , fmc Ú , addr 4Ú FMC_EraseBlock32k æÚ , fmc Ú , addr 4Ú FMC_EraseBlock64k áÚ , fmc Ú FMC_EraseChip %Ú , fmc Ú ,
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addr <Ú ,
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len Ú FMC_EraseCodeArea Ú , fmc Ú ,
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mode 2Ú InitIcache Ú , fmc Ú ,
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addr <Ú ,
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count ¬Ú , chksum :Ú FMC_GetCrc32Sum ÃÚ , fmc Ú , adr Ú , sz æÚ BlankCheck Ú , fmc Ú , adr Ú , sz æÚ , buf Ú Verify gÚ , fmc Ú , adr Ú , sz æÚ , buf Ú ProgramPage }Ú , fmc Ú , cmd ¬Ú FMC_ReadStatusReg sÚ , fmc Ú FMC_WriteEnable CÚ , fmc Ú FMC_WriteDisable ÔÚ , fmc Ú , ops Ú ,
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buf Ú FMC_WriteStatusReg âÚ , fmc Ú ,
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Addr \Ú , cmd ¬Ú FMC_ReadByte Ú , fmc Ú ,
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addr <Ú , data DÚ FMC_WriteByte úÚ , fmc Ú ,
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addr <Ú , data ;Ú FMC_WriteHalfWord oÚ , fmc Ú ,
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Addr \Ú , cmd ¬Ú FMC_ReadWord Ú , fmc Ú ,
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Addr \Ú , cmd ¬Ú FMC_ReadPage ¢Ú , fmc Ú ,
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Addr \Ú , cmd ¬Ú , buf Ú ,
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len Ú FMC_ReadStream ¯Ú , fmc Ú ,
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Addr \Ú , buf Ú ,
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len Ú FMC_WriteStream Ú , fmc Ú ,
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Addr \Ú , cmd ¬Ú , buf Ú ,
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len Ú FMC_ReadInfoArea Ú , fmc Ú ,
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Addr \Ú , buf Ú ,
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len Ú FMC_WriteInfoArea Ú , fmc Ú FMC_EraseInfoArea Ú , fmc Ú ,
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mode 2Ú , enhance Ú FMC_SetFlashMode ôÚ , fmc Ú FMC_ExitEnhanceMode ¼Ú , fmc Ú ,
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mode 2Ú FMC_EnterEnhanceMode VÚ , fmc Ú FMC_EnableAutoDp ÿÚ , fmc Ú FMC_DisableAutoDp Ú , fmc Ú ,
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cnt Ú FMC_SetRdpWaitCount Ú , fmc Ú ,
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cnt Ú FMC_SetDpWaitCount Ú , fmc Ú ," IRQn hÚ ," NewState Ú FMC_SetSuspendIrq WÚ , fmc Ú ,
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timeout ÊÚ FMC_SetSuspendTimeout Ú P __PAN_DMAC_H__ 9Ú P DMAC_CHANNEL_NUMBER Ú P DMA_INVLID_CHANNEL XÚ" P DMAC_TransferType_Mem2Mem oÚ" P DMAC_TransferType_Mem2Per gÚ" P DMAC_TransferType_Per2Mem gÚ" P DMAC_TransferType_Per2Per _Ú P DMAC_FlowControl_DMA
Ú$ P DMAC_FlowControl_Peripheral =Ú P DMAC_BurstLen_1 zÚ P DMAC_BurstLen_4 wÚ P DMAC_BurstLen_8 sÚ P DMAC_BurstLen_16 BÚ P DMAC_BurstLen_32 DÚ P DMAC_BurstLen_64 ?Ú P DMAC_BurstLen_128 Ú P DMAC_BurstLen_256
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Ú" P DMAC_AddrChange_Increment `Ú" P DMAC_AddrChange_Decrement nÚ! P DMAC_AddrChange_NoChange Ú P DMAC_DataWidth_8 &Ú P DMAC_DataWidth_16 õÚ P DMAC_DataWidth_32 ÷Ú P DMAC_DataWidth_64 òÚ P DMAC_DataWidth_128 ¿Ú P DMAC_DataWidth_256 ½Ú P DMAC_Peripheral_I2C0_Tx ¥Ú P DMAC_Peripheral_I2C0_Rx §Ú P DMAC_Peripheral_SPI0_Tx wÚ P DMAC_Peripheral_SPI0_Rx yÚ! P DMAC_Peripheral_UART0_Tx %Ú! P DMAC_Peripheral_UART0_Rx 'Ú P DMAC_Peripheral_SPI1_Tx vÚ P DMAC_Peripheral_SPI1_Rx xÚ! P DMAC_Peripheral_UART1_Tx $Ú! P DMAC_Peripheral_UART1_Rx &Ú P DMAC_Peripheral_ADC þÚ P DMAC_Peripheral_USB_Rx Ú P DMAC_Peripheral_USB_Tx «Ú# P DMAC_HandshakePolarity_Low ·Ú$ P DMAC_HandshakePolarity_High gÚ P DMAC_Handshake_Default Ú P DMAC_Handshake_Software øÚ P DMAC_Handshake_Hardware Ú$ P DMAC_LockLevel_Tfr_Complete }Ú& P DMAC_LockLevel_Block_Complete ºÚ, P $DMAC_LockLevel_Transaction_Complete Ú P DMAC_ChannelPriority_0 Ú P DMAC_ChannelPriority_1 Ú P DMAC_ChannelPriority_2 Ú P DMAC_ChannelPriority_3 ~Ú P DMAC_ChannelPriority_4 }Ú P DMAC_ChannelPriority_5 |Ú P DMAC_ChannelPriority_6 {Ú P DMAC_ChannelPriority_7 zÚ P DMAC_CHANNELALL_MASK ÒÚ P DMAC_FLAG_INDEX_TFR õÚ P DMAC_FLAG_INDEX_BLK Ú P DMAC_FLAG_INDEX_SRCTFR Ú P DMAC_FLAG_INDEX_DSTTFR Ú P DMAC_FLAG_INDEX_ERR øÚ P DMAC_FLAG_MASK_TFR CÚ P DMAC_FLAG_MASK_BLK VÚ P DMAC_FLAG_MASK_SRCTFR UÚ P DMAC_FLAG_MASK_DSTTFR RÚ P DMAC_FLAG_MASK_ERR FÚ P DMAC_FLAG_MASK_ALL VÚ$ 8 __DMAC_ChannelConfigTypeDef Ú
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" .CTL_L fÚ
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" .CTL_H jÚ
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" .CFG_L yÚ
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" .CFG_H }Ú$ __DMAC_ChannelConfigTypeDef ÙÚ" 8 DMAC_ChannelConfigTypeDef _Ú
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" £.
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IntEnable tÚ
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" £. DataWidthDst ;Ú
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" £. DataWidthSrc >Ú
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" £.AddrChangeDst òÚ
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" £.AddrChangeSrc õÚ
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" £. BurstLenDst Ú
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" £. BurstLenSrc Ú
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" £. GatherEnSrc ¬Ú
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" £. ScatterEnDst ,Ú
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" £.__Rev0 ÑÚ
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" £. TransferType ùÚ
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" £. FlowControl iÚ
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" £.__Rev1 ÐÚ
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" £.
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BlockSize `Ú
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" £.Done jÚ
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" £.__Rev3 ÎÚ
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" £.__Rev4 ÍÚ
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" £.ChannelPriority ¿Ú
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" £.ChannelSuspend AÚ
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" £.
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FifoEmpty SÚ
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" £. HandshakeDst .Ú
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" £. HandshakeSrc 1Ú
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" £.LockBus 7Ú
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" £. LockChannel Ú
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" £. LockBusLevel 5Ú
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" £.LockChannelLevel Ú
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" £.HandshakePolarityDst ÊÚ
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" £.HandshakePolaritySrc ÍÚ
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" £.__Rev6 ËÚ
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" £.AutoReloadSrc ÆÚ
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" £.AutoReloadDst ÃÚ
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" £.FlowControlMode ÜÚ
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" £. FifoMode ßÚ
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" £.ProtectControl Ú
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" £.__Rev7 ÊÚ
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" £.PeripheralSrc ªÚ
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" £.PeripheralDst §Ú
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" £.__Rev8 ÉÚ" DMAC_ChannelConfigTypeDef Ú DMAC_IsChannelValid õÚ ," Ë.dma ~Ú ,
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" Ë.ChIdx êÚ P DMAC_ChannelMask òÚ DMAC_CombinedIntStatus Ú ," Ï.dma zÚ ,
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" Ï.FlgMsk pÚ DMAC_StatusFlag dÚ ," Ò.dma wÚ ,
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" Ò.ChIdx ãÚ ,
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" Ò.FlgIdx sÚ DMAC_IntFlag ÃÚ ," Ö.dma sÚ ,
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" Ö.ChIdx ßÚ ,
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" Ö.FlgIdx oÚ DMAC_IntFlagMsk Ú ," Ú.dma oÚ ,
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" Ú.ChIdx ÛÚ ,
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" Ú.FlgIdx kÚ DMAC_ClrIntFlag Ú ," Þ.dma kÚ ,
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" Þ.ChIdx ×Ú ,
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" Þ.FlgIdx gÚ , dma Ú
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DMAC_Init ÎÚ , dma Ú DMAC_DeInit !Ú , dma Ú ,
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ChIdx Ú ,
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FlgIdx Ú DMAC_ClrIntFlagMsk _Ú , dma Ú ,
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ChIdx Ú ,
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FlgIdx Ú DMAC_SetIntFlagMsk TÚ , dma Ú ,
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ChIdx Ú , Config oÚ DMAC_SetChannelConfig Ú , dma Ú ,
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ChIdx Ú , Config oÚ DMAC_GetChannelConfig Ú , dma Ú ,
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ChIdx Ú , Src £Ú , Dst Ú ,
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Len ºÚ DMAC_StartChannel Ú , dma Ú ,
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ChIdx Ú DMAC_StopChannel õÚ , dma Ú DMAC_AcquireChannel ËÚ , dma Ú ,
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ChIdx Ú DMAC_ReleaseChannel ÔÚ , dma Ú" DMAC_IsAllChannelReleased Ú P __PAN_GPIO_H__ Ú P GPIO_PIN_MAX ùÚ 8" _GPIO_ModeDef $Ú " /GPIO_MODE_INPUT dÚ " /GPIO_MODE_OUTPUT Ú " /GPIO_MODE_OPEN_DRAIN ëÚ " /GPIO_MODE_QUASI qÚ GPIO_ModeDef ÇÚ 8" _GPIO_IntAttrDef ÝÚ " /GPIO_INT_RISING \Ú " /GPIO_INT_FALLING )Ú " /GPIO_INT_BOTH_EDGE Ú " /GPIO_INT_HIGH Ú " / GPIO_INT_LOW <Ú GPIO_IntAttrDef Ú 8" _GPIO_ClkSrcDef cÚ" " /GPIO_DBCTL_DBCLKSRC_RCL Ú# " /GPIO_DBCTL_DBCLKSRC_HCLK ÈÚ GPIO_ClkSrcDef Ú 8" _GPIO_ClkSelDef gÚ " /GPIO_DBCTL_DBCLKSEL_1 ¿Ú " /GPIO_DBCTL_DBCLKSEL_2 ¾Ú " /GPIO_DBCTL_DBCLKSEL_4 ¼Ú " /GPIO_DBCTL_DBCLKSEL_8 ¸Ú! " /GPIO_DBCTL_DBCLKSEL_16 Ú! " /GPIO_DBCTL_DBCLKSEL_32 Ú! " /GPIO_DBCTL_DBCLKSEL_64 Ú" " /GPIO_DBCTL_DBCLKSEL_128 QÚ" " /GPIO_DBCTL_DBCLKSEL_256 OÚ" " /GPIO_DBCTL_DBCLKSEL_512 TÚ# " /GPIO_DBCTL_DBCLKSEL_1024 #Ú# " /GPIO_DBCTL_DBCLKSEL_2048 Ú# " /GPIO_DBCTL_DBCLKSEL_4096 Ú# " /GPIO_DBCTL_DBCLKSEL_8192 Ú$ " /GPIO_DBCTL_DBCLKSEL_16384 âÚ$ " /GPIO_DBCTL_DBCLKSEL_32768 ÞÚ GPIO_ClkSelDef
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Ú P GPIO_PIN_ADDR ÂÚ P P00 Ú P P01 Ú P P02 Ú P P03 Ú P P04 Ú P P05 Ú P P06 Ú P P07 Ú P P10 Ú P P11 Ú P P12 Ú P P13 Ú P P14 Ú P P15 Ú P P16 Ú P P17 Ú P P20 Ú P P21 Ú P P22 Ú P P23 Ú P P24 Ú P P25 Ú P P26 Ú P P27 Ú P P30 Ú P P31 Ú GPIO_ClrIntFlag Ú ," Æ/gpio Ú ,
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" Æ/ u32PinMask 'Ú GPIO_ClrAllIntFlag cÚ ," É/gpio Ú GPIO_DisableDebounce eÚ ," Ë/gpio þÚ ,
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" Ë/ u32PinMask "Ú GPIO_EnableDebounce ÔÚ ," Î/gpio ûÚ ,
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" Î/ u32PinMask Ú GPIO_DisableDigitalPath 9Ú ," Ñ/gpio øÚ ,
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" Ñ/ u32PinMask Ú GPIO_EnableDigitalPath ¨Ú ," Ô/gpio õÚ ,
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" Ô/ u32PinMask Ú GPIO_DisablePullupPath wÚ ," ×/gpio òÚ ,
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" ×/ u32PinMask Ú GPIO_EnablePullupPath æÚ ," Ú/gpio ïÚ ,
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" Ú/ u32PinMask Ú! GPIO_DisablePulldownPath Ú ," Ý/gpio ìÚ ,
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" Ý/ u32PinMask Ú GPIO_EnablePulldownPath Ú ," à/gpio éÚ ,
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" à/ u32PinMask Ú GPIO_DisableDoutMask bÚ ," ã/gpio æÚ ,
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" ã/ u32PinMask
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Ú GPIO_EnableDoutMask ÑÚ ," æ/gpio ãÚ ,
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" æ/ u32PinMask Ú GPIO_GetIntFlag Ú ," é/gpio àÚ ,
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" é/ u32PinMask Ú GPIO_SetDebounceTime ^Ú ,"" ì/clksrc ÿÚ ,"" ì/clksel Ú GPIO_GetInData ùÚ ," ï/gpio ÚÚ GPIO_SetOutData jÚ ," ñ/gpio ØÚ ,
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" ñ/data ûÚ GPIO_GetOutData vÚ ," ô/gpio ÕÚ GPIO_Toggle îÚ ," ö/gpio ÓÚ ,
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" ö/ u32PinMask ÷Ú GPIO_EnableInt ØÚ ," ù/gpio ÐÚ ,
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" ù/u32Pin Ú ,"" ù/ IntAttribs eÚ GPIO_DisableInt iÚ ," ý/gpio ÌÚ ,
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" ý/u32Pin Ú P GPIO_EnableEINT0 vÚ P GPIO_DisableEINT0 Ú P GPIO_EnableEINT1 uÚ P GPIO_DisableEINT1 Ú , gpio Ú ,
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PinMask Ú ," Mode =Ú GPIO_SetMode Ú P __PAN_SPI_H__ dÚ 8" SPI_Irq :Ú " 0SPI_IRQ_TX_HALF_EMPTY NÚ " 0SPI_IRQ_RX_HALF_FULL ®Ú " 0SPI_IRQ_RX_TIMEOUT 8Ú " 0SPI_IRQ_RX_OVERRUN .Ú " 0 SPI_IRQ_ALL Ú SPI_IrqDef gÚ 8" SPI_Role ÒÚ " 0SPI_RoleMaster ¶Ú " 0SPI_RoleSlave )Ú SPI_RoleDef ÿÚ 8" SPI_DataFrameSize RÚ " 0SPI_DataFrame_4b RÚ " 0SPI_DataFrame_5b QÚ " 0SPI_DataFrame_6b PÚ " 0SPI_DataFrame_7b OÚ " 0SPI_DataFrame_8b NÚ " 0SPI_DataFrame_9b MÚ " 0SPI_DataFrame_10b #Ú " 0SPI_DataFrame_11b "Ú " 0SPI_DataFrame_12b !Ú " 0SPI_DataFrame_13b Ú " 0SPI_DataFrame_14b Ú " 0SPI_DataFrame_15b Ú " 0SPI_DataFrame_16b Ú SPI_DataFrameSizeDef Ú 8" SPI_BaudRateDiv +Ú " £0SPI_BaudRateDiv_2 ßÚ " £0SPI_BaudRateDiv_4 ÝÚ " £0SPI_BaudRateDiv_6 ÛÚ " £0SPI_BaudRateDiv_8 ÙÚ " £0SPI_BaudRateDiv_16 ¨Ú " £0SPI_BaudRateDiv_32 ªÚ " £0SPI_BaudRateDiv_48 £Ú " £0SPI_BaudRateDiv_64 ¥Ú " £0SPI_BaudRateDiv_96 Ú " £0SPI_BaudRateDiv_128 rÚ " £0SPI_BaudRateDiv_160 vÚ " £0SPI_BaudRateDiv_192 qÚ " £0SPI_BaudRateDiv_224 uÚ " £0SPI_BaudRateDiv_240 wÚ " £0SPI_BaudRateDiv_250 vÚ SPI_BaudRateDivDef XÚ P SPI_BAUD_RATE_DIV uÚ 8" SPI_ClockPol EÚ " µ0SPI_ClockPolarityLow Ú " µ0SPI_ClockPolarityHigh ÁÚ SPI_ClockPolDef rÚ 8" SPI_ClockPhase {Ú" " ¹0SPI_ClockPhaseFirstEdge Ú# " ¹0SPI_ClockPhaseSecondEdge ÉÚ SPI_ClockPhaseDef ¨Ú 8" SPI_FrameFormat Ú " ½0SPI_FormatMotorola ÉÚ " ½0 SPI_FormatTi eÚ " ½0SPI_FormatMicrowire cÚ SPI_FrameFormatDef /Ú 8" SPI_WireNum Ú " Â0SPI_WireNumThree ¿Ú " Â0SPI_WireNumFour Ú SPI_WireNumDef ÄÚ 8" SPI_CmdDat 3Ú " Æ0SPI_CommandSelect YÚ " Æ0SPI_DataSelect ¤Ú SPI_CmdDatDef `Ú 8" SPI_WriteReadSel ©Ú " Ê0SPI_3WireRead 6Ú " Ê0SPI_3WireWrite ¥Ú SPI_WriteReadSelDef ÖÚ 8
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<unnamed> QÚ "" Î0 SPI_role ©Ú "" Î0SPI_dataFrameSize )Ú "" Î0 SPI_CPOL -Ú "" Î0 SPI_CPHA ?Ú " Î0SPI_baudRateDiv Ú "" Î0 SPI_format ÎÚ SPI_InitTypeDef SÚ SPI_EnableSpi Ú ," Ö0SPIx =Ú
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" Ö0tmpreg @Ú SPI_DisableSpi Ú ," Ù0SPIx :Ú
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" Ù0tmpreg =Ú SPI_IsSpiEnabled öÚ ," Ü0SPIx 7Ú
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" Ü0tmpreg :Ú SPI_EnableDmaTx fÚ ," ß0SPIx 4Ú
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" ß0tmpreg 7Ú SPI_DisableDmaTx ÷Ú ," â0SPIx 1Ú
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" â0tmpreg 4Ú SPI_IsDmaTxEnabled @Ú ," å0SPIx .Ú
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" å0tmpreg 1Ú SPI_EnableDmaRx hÚ ," è0SPIx +Ú
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" è0tmpreg .Ú SPI_DisableDmaRx ùÚ ," ë0SPIx (Ú
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" ë0tmpreg +Ú SPI_IsDmaRxEnabled BÚ ," î0SPIx %Ú
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" î0tmpreg (Ú SPI_SendData Ú ," ñ0SPIx "Ú ,
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" ñ0Data Ú SPI_ReceiveData NÚ ," ô0SPIx Ú SPI_EnableIrq Ú ," ö0SPIx Ú ,"" ö0irq 0Ú
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" ö0tmpreg Ú SPI_DisableIrq Ú ," ú0SPIx Ú ,"" ú0irq ,Ú
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" ú0tmpreg Ú SPI_IsIrqEnabled öÚ ," þ0SPIx Ú ,"" þ0irq (Ú
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" þ0tmpreg Ú SPI_GetMskedActiveIrq ãÚ ," 1SPIx Ú
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" 1tmpreg Ú SPI_IsIrqActive GÚ ,"
1SPIx Ú ,""
1irq Ú
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"
1tmpreg Ú SPI_IsRawIrqActive Ú ," 1SPIx Ú ,"" 1irq Ú
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" 1tmpreg Ú SPI_ClearIrq ~Ú ," 1SPIx
Ú ,"" 1irq Ú
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" 1tmpreg Ú SPI_GetRawActiveIrq ±Ú ," 1SPIx Ú
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" 1tmpreg Ú SPI_IsTxFifoEmpty lÚ ," 1SPIx ~Ú
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" 1tmpreg Ú SPI_IsTxFifoFull êÚ ," 1SPIx {Ú
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" 1tmpreg ~Ú SPI_IsRxFifoEmpty nÚ ," 1SPIx xÚ
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" 1tmpreg {Ú SPI_IsRxFifoFull ìÚ ," 1SPIx uÚ
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" 1tmpreg xÚ SPI_IsBusy 6Ú ," 1SPIx rÚ
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" 1tmpreg uÚ SPI_TxLsbEnable WÚ ," £1SPIx oÚ ," £1enable }Ú SPI_RxLsbEnable YÚ ," ¦1SPIx lÚ ," ¦1enable zÚ SPI_SetWireNum Ú ," ©1SPIx iÚ ,"" ©1num xÚ SPI_DataCmdLineEnable "Ú ," ¬1SPIx fÚ ,"" ¬1 NewState Ú SPI_DataCmdSelCmdDat ¢Ú ," ¯1SPIx cÚ ,"" ¯1cmdDat oÚ SPI_WriteReadCtrl kÚ ," ²1SPIx `Ú ,"" ²1wr ØÚ , SPIx eÚ , SPI_InitStruct QÚ SPI_Init ùÚ P __PAN_UART_H__ Ú 8" UART_TxTrigger hÚ " ¹1UART_TX_FIFO_EMPTY Ú! " ¹1UART_TX_FIFO_TWO_CHARS ÒÚ$ " ¹1UART_TX_FIFO_QUARTER_FULL àÚ! " ¹1UART_TX_FIFO_HALF_FULL ïÚ UART_TxTriggerDef Ú 8" UART_RxTrigger jÚ " ¿1UART_RX_FIFO_ONE_CHAR ;Ú$ " ¿1UART_RX_FIFO_QUARTER_FULL ÜÚ! " ¿1UART_RX_FIFO_HALF_FULL ëÚ* " ¿1 UART_RX_FIFO_TWO_LESS_THAN_FULL ÚÚ UART_RxTriggerDef Ú 8" UART_LineCtrl íÚ " Å1Uart_Line_5n1 Ú " Å1Uart_Line_5n1_5 }Ú " Å1Uart_Line_5e1 Ú " Å1Uart_Line_5e1_5 Ú " Å1Uart_Line_5o1 Ú " Å1Uart_Line_5o1_5 |Ú " Å1Uart_Line_5s1 Ú " Å1Uart_Line_5s1_5 xÚ " Å1Uart_Line_5m1 Ú " Å1Uart_Line_5m1_5 ~Ú " Å1Uart_Line_6n1 Ú " Å1Uart_Line_6n2 Ú " Å1Uart_Line_6e1 Ú " Å1Uart_Line_6e2 Ú " Å1Uart_Line_6o1 Ú " Å1Uart_Line_6o2 Ú " Å1Uart_Line_6s1 Ú " Å1Uart_Line_6s2 Ú " Å1Uart_Line_6m1 Ú " Å1Uart_Line_6m2 Ú " Å1Uart_Line_7n1 Ú " Å1Uart_Line_7n2 Ú " Å1Uart_Line_7e1 Ú " Å1Uart_Line_7e2 Ú " Å1Uart_Line_7o1 Ú " Å1Uart_Line_7o2 Ú " Å1Uart_Line_7s1 Ú " Å1Uart_Line_7s2 Ú " Å1Uart_Line_7m1 Ú " Å1Uart_Line_7m2 Ú " Å1Uart_Line_8n1 Ú " Å1Uart_Line_8n2 Ú " Å1Uart_Line_8e1 Ú " Å1Uart_Line_8e2 Ú " Å1Uart_Line_8o1 Ú " Å1Uart_Line_8o2 Ú " Å1Uart_Line_8s1 Ú " Å1Uart_Line_8s2 Ú " Å1Uart_Line_8m1 Ú " Å1Uart_Line_8m2 Ú UART_LineCtrlDef Ú 8" UART_Irq èÚ! " ï1UART_IRQ_RECV_DATA_AVL ¾Ú " ï1UART_IRQ_THR_EMPTY ÕÚ " ï1UART_IRQ_LINE_STATUS BÚ " ï1UART_IRQ_MODEM_STATUS öÚ " ï1 UART_IRQ_ALL äÚ UART_IrqDef Ú 8" UART_Event Ú " ö1UART_EVENT_MODEM ¦Ú " ö1UART_EVENT_NONE êÚ " ö1UART_EVENT_THR_EMPTY 4Ú " ö1UART_EVENT_DATA Ú " ö1UART_EVENT_LINE òÚ " ö1UART_EVENT_TIMEOUT íÚ UART_EventDef ;Ú 8" UART_LineStatus úÚ " þ1UART_LINE_DATA_RDY þÚ " þ1UART_LINE_OVERRUN_ERR çÚ " þ1UART_LINE_PARITY_ERR AÚ " þ1UART_LINE_FRAME_ERR ±Ú " þ1UART_LINE_BREAK_INT µÚ " þ1UART_LINE_THRE ;Ú " þ1UART_LINE_TXSR_EMPTY #Ú$ " þ1UART_LINE_RECV_FIFO_EMPTY ·Ú " þ1UART_LINE_ADDR_RCVD »Ú UART_LineStatusDef 'Ú 8" UART_ModemStatus Ú " 2UART_MODEM_DCTS hÚ " 2UART_MODEM_DDSR iÚ " 2UART_MODEM_TERI bÚ " 2UART_MODEM_DDCD Ú " 2UART_MODEM_CTS ®Ú " 2UART_MODEM_DSR ¯Ú " 2UART_MODEM_RI ÿÚ " 2UART_MODEM_DCD ÍÚ UART_ModemStatusDef »Ú 8
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<unnamed> QÚ
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" 2UART_BaudRate GÚ "" 2UART_LineCtrl Ú UART_InitTypeDef Ú UART_EnableStickParity oÚ ," 2UARTx (Ú UART_DisableStickParity Ú ," 2UARTx &Ú UART_GetLineStatus Ú ," 2UARTx $Ú UART_GetModemStatus Ú ," 2UARTx "Ú UART_EnableFifo pÚ ," 2UARTx Ú UART_DisableFifo Ú ," ¡2UARTx Ú UART_IsFifoEnabled JÚ ," £2UARTx Ú UART_ResetRxFifo èÚ ," ¥2UARTx Ú
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" ¥2val ÁÚ UART_ResetTxFifo æÚ ," ¨2UARTx Ú UART_SetTxTrigger kÚ ," ª2UARTx Ú ,"" ª2level ªÚ UART_SetRxTrigger mÚ ," 2UARTx Ú ,"" 2level §Ú UART_GetTxFifoLevel ËÚ ," °2UARTx Ú UART_GetRxFifoLevel ÍÚ ," ²2UARTx Ú UART_EnableAfc ìÚ ," ´2UARTx Ú UART_DisableAfc }Ú ," ¶2UARTx Ú UART_IsAfcEnabled ÆÚ ," ¸2UARTx Ú UART_SendData ;Ú ," º2UARTx Ú ," º2Data VÚ UART_ReceiveData üÚ ," ½2UARTx Ú UART_EnablePtime óÚ ," ¿2UARTx Ú UART_DisablePtime Ú ," Á2UARTx þÚ UART_IsPtimeEnabled ÍÚ ," Ã2UARTx üÚ UART_EnableIrq ÊÚ ," Å2UARTx úÚ ,"" Å2irq _Ú UART_DisableIrq [Ú ," È2UARTx ÷Ú ,"" È2irq \Ú UART_IsIrqEnabled ¤Ú ," Ë2UARTx ôÚ ,"" Ë2irq YÚ UART_GetIrqMasked Ú ," Î2UARTx ñÚ UART_GetActiveEvent µÚ ," Ð2UARTx ïÚ UART_IsTxFifoEmpty Ú ," Ò2UARTx íÚ UART_IsTxFifoFull Ú ," Ô2UARTx ëÚ UART_IsRxFifoEmpty Ú ," Ö2UARTx éÚ UART_IsRxFifoFull Ú ," Ø2UARTx çÚ UART_EnableHaltTX »Ú ," Ú2UARTx åÚ UART_DisableHaltTX LÚ ," Ü2UARTx ãÚ UART_EnableRts ½Ú ," Þ2UARTx áÚ UART_DisableRts NÚ ," à2UARTx ßÚ UART_Enable9BitData Ú ," â2UARTx ÝÚ UART_Disable9BitData «Ú ," ä2UARTx ÛÚ! UART_EnableAddrMatchMode õÚ ," æ2UARTx ÙÚ" UART_DisableAddrMatchMode Ú ," è2UARTx ×Ú UART_SendAddr :Ú ," ê2UARTx ÕÚ UART_SetReceiveAddress xÚ ," ì2UARTx ÓÚ ,
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" ì2addr üÚ UART_SetTransmitAddress çÚ ," ï2UARTx ÐÚ ,
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" ï2addr ùÚ , UARTx Ú , UART_InitStruct ÿÚ
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UART_Init §Ú , UARTx Ú UART_DeInit úÚ , UARTx Ú , Buf ®Ú ,
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BufSize Ú ,
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SendSize ªÚ UART_SendMultipleData ÓÚ , UARTx Ú , Buf ®Ú ,
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BufSize Ú ,
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ExpectSize ÇÚ! UART_ReceiveMultipleData Ú P __PAN_I2C_H__ Ú 8
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<unnamed> QÚ
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" 3I2C_ClockSpeed þÚ " 3 I2C_Mode `Ú " 3I2C_DutyCycle EÚ " 3I2C_OwnAddress1 ¬Ú" " 3I2C_AcknowledgedAddress 9Ú I2C_InitTypeDef Ú P I2C_DYNAMIC_TAR_UPDATE Ú P I2C_MODE_MASTER @Ú P I2C_MODE_SLAVE Ú P IS_I2C_MODE xÚ P I2C_SPEED_STANDARD_MODE ÛÚ P I2C_SPEED_FAST_MODE Ú P I2C_SPEED_HIGH_MODE Ú P I2C_DutyCycle_16_9 Ú P I2C_DutyCycle_2 iÚ P I2C_DutyCycle_1_1 ÖÚ P I2C_DutyCycle_1_2 ÕÚ P IS_I2C_DUTY_CYCLE |Ú" P I2C_Direction_Transmitter ßÚ P I2C_Direction_Receiver MÚ P IS_I2C_DIRECTION òÚ% P I2C_AcknowledgedAddress_7bit Ú& P I2C_AcknowledgedAddress_10bit çÚ# P IS_I2C_ACKNOWLEDGE_ADDRESS öÚ P I2C_CMD_WR ¾Ú P I2C_CMD_RD ÑÚ P I2C_CMD_STOP Ú P I2C_CMD_RESTART 8Ú P I2C_RX_TL_0 `Ú P I2C_RX_TL_1 _Ú P I2C_RX_TL_2 ^Ú P I2C_RX_TL_3 ]Ú P I2C_RX_TL_4 \Ú P I2C_RX_TL_5 [Ú P I2C_RX_TL_6 ZÚ P I2C_RX_TL_7 YÚ P I2C_RX_TL_8 XÚ P I2C_TX_TL_0 ^Ú P I2C_TX_TL_1 ]Ú P I2C_TX_TL_2 \Ú P I2C_TX_TL_3 [Ú P I2C_TX_TL_4 ZÚ P I2C_TX_TL_5 YÚ P I2C_TX_TL_6 XÚ P I2C_TX_TL_7 WÚ P I2C_TX_TL_8 VÚ P I2C_IT_RX_UNDER Ú P I2C_IT_RX_OVER QÚ P I2C_IT_RX_FULL ZÚ P I2C_IT_TX_OVER OÚ P I2C_IT_TX_EMPTY úÚ P I2C_IT_RD_REQ »Ú P I2C_IT_TX_ABORT Ú P I2C_IT_RX_DONE gÚ P I2C_IT_ACTIVITY 'Ú P I2C_IT_STOP_DET Ú P I2C_IT_START_DET ÈÚ P I2C_IT_GEN_CALL ?Ú P I2C_IT_MST_ON_HOLD Ú P I2C_IT_ALL ÅÚ P IS_I2C_CLEAR_IT 2Ú P IS_I2C_GET_IT ½Ú P I2C_FLAG_SLV_ACTIVITY JÚ P I2C_FLAG_MST_ACTIVITY KÚ P I2C_FLAG_RFF ?Ú P I2C_FLAG_RFNE ðÚ P I2C_FLAG_TFE >Ú P I2C_FLAG_TFNF íÚ P I2C_FLAG_ACTIVITY ¦Ú P IS_I2C_CLEAR_FLAG ±Ú P IS_I2C_GET_FLAG <Ú P
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FLAG_MASK Ú P
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ITEN_MASK þÚ P IT_FLAG_MASK Ú I2C_SetMode Ú ," Í3I2Cx qÚ ," Í3Mode .Ú I2C_SetTxTirggerLevel éÚ ," Ð3I2Cx nÚ ," Ð3ThresholdValue ûÚ I2C_SetRxTirggerLevel ëÚ ," Ó3I2Cx kÚ ," Ó3ThresholdValue øÚ I2C_Cmd µÚ ," Ö3I2Cx hÚ ,"" Ö3 NewState dÚ I2C_GeneralCallCmd eÚ ," Ù3I2Cx eÚ ,"" Ù3 NewState aÚ I2C_SendDataCmd ¡Ú ," Ü3I2Cx bÚ ," Ü3Data 3Ú ," Ü3Cmd Ú I2C_SendCmd #Ú ," à3I2Cx ^Ú ," à3Cmd Ú I2C_ReceiveData |Ú ," ã3I2Cx [Ú I2C_AbortTransfer xÚ ," å3I2Cx YÚ I2C_DMACmd ÝÚ ," ç3I2Cx WÚ ,"" ç3 NewState SÚ! I2C_DMATransferDataLevel Ú ," ê3I2Cx TÚ ," ê3Level ¥Ú I2C_DMAReceiveDataLevel ¢Ú ," í3I2Cx QÚ ," í3Level ¢Ú I2C_GetITStatus xÚ ," ð3I2Cx NÚ ," ð3I2C_IT ÒÚ I2C_GetRawITStatus HÚ ," ó3I2Cx KÚ ," ó3I2C_IT ÏÚ I2C_ITConfig ÌÚ ," ö3I2Cx HÚ ," ö3I2C_IT ÌÚ ,"" ö3 NewState DÚ I2C_DisableAllIT MÚ ," ú3I2Cx DÚ! I2C_ClearAllITPendingBit &Ú ," ü3I2Cx BÚ I2C_AbortSrcCheck ·Ú ," þ3I2Cx @Ú ,
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" þ3IC_MSK ªÚ I2C_SetSlaveAddr Ú ," 4I2Cx ¼Ú ,
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" 4addr eÚ , I2Cx Ú , I2C_InitStruct Ú I2C_Init 'Ú , I2Cx Ú , Address Ú I2C_Set7bitAddress ?Ú , I2Cx Ú , Address Ú I2C_Set10bitAddress Ú , I2Cx Ú ,
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I2C_FLAG Ú I2C_GetFlagStatus Ú , I2Cx Ú , I2C_IT Ú I2C_ClearITPendingBit 9Ú , I2Cx Ú , WriteBuf Ú ,
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Size <Ú
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I2C_Write ®Ú , I2Cx Ú , ReadBuf *Ú ,
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Size <Ú I2C_Read ?Ú P __PAN_TIMER_H__ ËÚ 8" _TIMER_CntModeDef ¥Ú " 4TIMER_ONESHOT_MODE cÚ " 4TIMER_PERIODIC_MODE 2Ú " 4TIMER_TOGGLE_MODE ÃÚ " 4TIMER_CONTINUOUS_MODE fÚ TIMER_CntModeDef HÚ 8" _TIMER_CapModeDef ¶Ú+ " ¢4!TIMER_CAPTURE_FREE_COUNTING_MODE Ú. " ¢4$TIMER_CAPTURE_TRIGGER_COUNTING_MODE Ú+ " ¢4!TIMER_CAPTURE_COUNTER_RESET_MODE ìÚ TIMER_CapModeDef YÚ 8" _TIMER_CapEdgeDef ÆÚ% " §4TIMER_CAPTURE_FALLING_EDGE Ú$ " §4TIMER_CAPTURE_RISING_EDGE ;Ú" " §4TIMER_CAPTURE_BOTH_EDGE ÞÚ1 " §4'TIMER_CAPTURE_FALLING_THEN_RISING_EDGE 7Ú1 " §4'TIMER_CAPTURE_RISING_THEN_FALLING_EDGE 7Ú TIMER_CapEdgeDef iÚ 8" _TIMER_EvtCntEdgeDef Ú% " ®4TIMER_COUNTER_FALLING_EDGE õÚ$ " ®4TIMER_COUNTER_RISING_EDGE (Ú TIMER_EvtCntEdgeDef #Ú 8" _TIMER_CapSrcDef Ú' " ²4 TIMER_CAPTURE_SOURCE_EXT_PIN Ú* " ²4 TIMER_CAPTURE_SOURCE_32K_OUTPUT 4Ú TIMER_CapSrcDef ¸Ú 8" _TIMER0_CmpSelDef ÛÚ" " ¶4TMR0_COMPARATOR_SEL_CMP ÇÚ# " ¶4TMR0_COMPARATOR_SEL_CMP1 Ú# " ¶4TMR0_COMPARATOR_SEL_CMP2 Ú TIMER0_CmpSelDef ~Ú P FIXED_DEVIATION ;Ú TIMER_EnableCapture ÓÚ ," ¼4timer Ú ,"" ¼4capMode ðÚ ,"" ¼4capEdge Ú TIMER_DisableCapture dÚ ," À4timer Ú! TIMER_EnableEventCounter »Ú ," Â4timer Ú ,"" Â4 evtCntEdge µÚ" TIMER_DisableEventCounter LÚ ," Å4timer Ú TIMER_SetPrescaleValue Ú ," Ç4timer Ú ,
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" Ç4 u32Value ÛÚ TIMER_SetCountingMode òÚ ," Ê4timer Ú ,"" Ê4cntMode ÏÚ TIMER_IsActive àÚ ," Í4timer Ú TIMER_Start ðÚ ," Ï4timer Ú TIMER_Stop ZÚ ," Ñ4timer Ú TIMER_Reset ûÚ ," Ó4timer }Ú TIMER_EnableWakeup <Ú ," Õ4timer {Ú TIMER_DisableWakeup ÍÚ ," ×4timer yÚ$ TIMER_EnableCaptureDebounce Ú ," Ù4timer wÚ% TIMER_DisableCaptureDebounce /Ú ," Û4timer uÚ) !TIMER_EnableEventCounterDebounce Ú ," Ý4timer sÚ* "TIMER_DisableEventCounterDebounce Ú ," ß4timer qÚ TIMER_EnableInt Ú ," á4timer oÚ TIMER_DisableInt Ú ," ã4timer mÚ TIMER_EnableCaptureInt ¢Ú ," å4timer kÚ TIMER_DisableCaptureInt 3Ú ," ç4timer iÚ TIMER_GetIntFlag /Ú ," é4timer gÚ TIMER_ClearIntFlag dÚ ," ë4timer eÚ TIMER_GetTFFlag ÂÚ ," í4timer cÚ TIMER_ClearTFFlag ÷Ú ," ï4timer aÚ ,
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" ï4 timer_flag lÚ TIMER_GetWakeupFlag çÚ ," ò4timer ^Ú TIMER_ClearWakeupFlag Ú ," ô4timer \Ú ,
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" ô4
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wake_flag âÚ TIMER_GetCaptureIntFlag MÚ ," ÷4timer YÚ" TIMER_ClearCaptureIntFlag Ú ," ù4timer WÚ TIMER_GetCaptureFlag ~Ú ," û4timer UÚ TIMER_ClearCaptureFlag ³Ú ," ý4timer SÚ TIMER_SetCaptureSource wÚ ," ÿ4timer QÚ ,"" ÿ4capSrc
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Ú TIMER_GetCaptureData ~Ú ," 5timer ÍÚ TIMER_GetCounter ôÚ ," 5timer ËÚ TIMER_SetTmrCounterMode "Ú ," 5timer ÉÚ ,
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" 5 u32CntMode jÚ , timer ¦Ú ," cntMode ïÚ ,
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u32Freq iÚ TIMER_Open bÚ , timer ¦Ú TIMER_Close üÚ , timer ¦Ú ,
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u32Usec gÚ TIMER_Delay Ú , timer ¦Ú ," cmp_seq ÔÚ ,
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u32Value øÚ TIMER_SetCmpValue Ú P __PAN_PWM_H__ \Ú P PWM_CHANNEL_NUM Ú P PWM_CH0 ¯Ú P PWM_CH1 ®Ú P PWM_CH2 Ú P PWM_CH3 ¬Ú P PWM_CH4 «Ú P PWM_CH5 ªÚ P PWM_CH6 ©Ú P PWM_CH7 ¨Ú 8" _PWM_ClkSrcSelDef vÚ " 5PWM_CLK_SRC_APB BÚ " 5PWM_CLK_SRC_RCL 4Ú " 5PWM_CLK_SRC_XTL Ú PWM_ClkSrcSelDef Ú 8" _PWM_ClkDivDef ¥Ú " ¥5PWM_CLK_DIV_1 èÚ " ¥5PWM_CLK_DIV_2 çÚ " ¥5PWM_CLK_DIV_4 åÚ " ¥5PWM_CLK_DIV_8 áÚ " ¥5PWM_CLK_DIV_16 °Ú " ¥5PWM_CLK_DIRECT Ú PWM_ClkDivDef HÚ 8" _PWM_AlignedTypeDef Ú " 5PWM_EDGE_ALIGNED Ú " 5PWM_CENTER_ALIGNED nÚ PWM_AlignedTypeDef %Ú 8" _PWM_IntPeriodTypeDef ¤Ú# " ±5PWM_PERIOD_INT_UNDERFLOW PÚ# " ±5PWM_PERIOD_INT_MATCH_CNR WÚ PWM_IntPeriodTypeDef GÚ 8" _PWM_OperateTypeDef fÚ! " µ5OPERATION_EDGE_ALIGNED MÚ# " µ5OPERATION_CENTER_ALIGNED Ú+ " µ5!OPERATION_PRECISE_CENTER_ALIGNED #Ú PWM_OperateTypeDef Ú 8" _PWM_CntModeDef 6Ú " º5PWM_CNTMODE_ONE_SHOT Ú" " º5PWM_CNTMODE_AUTO_RELOAD ³Ú PWM_CntModeDef ÙÚ PWM_EnableOutput ©Ú ," ¾5pwm bÚ ,
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" ¾5u32ChannelMask Ú PWM_DisableOutput :Ú ," Á5pwm _Ú ,
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" Á5u32ChannelMask Ú PWM_StartChannel ºÚ ," Ä5pwm \Ú ,
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" Ä5u32ChannelNum çÚ PWM_StopChannel $Ú ," Ç5pwm YÚ ,
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" Ç5u32ChannelNum äÚ PWM_EnableDeadZone ,Ú ," Ê5pwm VÚ ,
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" Ê5u32ChannelNum áÚ ,
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" Ê5 u32Duration Ú PWM_DisableDeadZone ½Ú ," Î5pwm RÚ ,
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" Î5u32ChannelNum ÝÚ PWM_EnableCMPDInt éÚ ," Ñ5pwm OÚ ,
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" Ñ5u32ChannelNum ÚÚ PWM_DisableCMPDInt zÚ ," Ô5pwm LÚ ,
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" Ô5u32ChannelNum ×Ú PWM_ClearCMPDIntFlag ÉÚ ," ×5pwm IÚ ,
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" ×5u32ChannelNum ÔÚ PWM_GetCMPDIntFlag Ú ," Ú5pwm FÚ ,
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" Ú5u32ChannelNum ÑÚ PWM_EnablePeriodInt ¦Ú ," Ý5pwm CÚ ,
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" Ý5u32ChannelNum ÎÚ PWM_DisablePeriodInt 7Ú ," à5pwm @Ú ,
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" à5u32ChannelNum ËÚ PWM_ClearPeriodIntFlag Ú ," ã5pwm =Ú ,
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" ã5u32ChannelNum ÈÚ PWM_GetPeriodIntFlag QÚ ," æ5pwm :Ú ,
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" æ5u32ChannelNum ÅÚ PWM_EnableZeroInt mÚ ," é5pwm 7Ú ,
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" é5u32ChannelNum ÂÚ PWM_DisableZeroInt þÚ ," ì5pwm 4Ú ,
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" ì5u32ChannelNum ¿Ú PWM_ClearZeroIntFlag MÚ ," ï5pwm 1Ú ,
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" ï5u32ChannelNum ¼Ú PWM_GetZeroIntFlag Ú ," ò5pwm .Ú ,
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" ò5u32ChannelNum ¹Ú PWM_EnableCMPUInt ØÚ ," õ5pwm +Ú ,
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" õ5u32ChannelNum ¶Ú PWM_DisableCMPUInt iÚ ," ø5pwm (Ú ,
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" ø5u32ChannelNum ³Ú PWM_ClearCMPUIntFlag ¸Ú ," û5pwm %Ú ,
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" û5u32ChannelNum °Ú PWM_GetCMPUIntFlag Ú ," þ5pwm "Ú ,
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" þ5u32ChannelNum Ú PWM_EnableCenterInt ¨Ú ," 6pwm Ú ,
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" 6u32ChannelNum )Ú ,"" 6IntPeriodType §Ú PWM_DisableCenterInt 9Ú ,"
6pwm Ú ,
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"
6u32ChannelNum %Ú PWM_ClearCenterIntFlag Ú ," 6pwm Ú ,
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" 6u32ChannelNum "Ú PWM_GetCenterIntFlag SÚ ," 6pwm Ú ,
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" 6u32ChannelNum Ú" PWM_EnableIndependentMode 5Ú ," 6pwm Ú$ PWM_EnableComplementaryMode ?Ú ," 6pwm Ú% PWM_DisableComplementaryMode ÐÚ ," 6pwm Ú PWM_EnableGroupMode ¢Ú ," 6pwm Ú PWM_DisableGroupMode 3Ú ," 6pwm Ú PWM_EnableSyncMode Ú ," 6pwm Ú PWM_DisableSyncMode ¥Ú ," 6pwm
Ú PWM_SetPrescaler ´Ú ," 6pwm Ú ,
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" 6u32ChannelNum Ú ,
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" 6 u32Prescaler XÚ PWM_ResetPrescaler ÙÚ ," 6pwm Ú ,
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" 6u32ChannelNum
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Ú PWM_SetDivider Ú ," £6pwm |Ú ,
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" £6u32ChannelNum Ú ,"" £6Divider úÚ PWM_SetCMR Ú ," §6pwm xÚ ,
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" §6u32ChannelNum Ú ,
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" §6u32CMR Ú PWM_SetCNR ~Ú ," «6pwm tÚ ,
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" «6u32ChannelNum ÿÚ ,
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" «6u32CNR Ú PWM_SetCMRD 9Ú ," ¯6pwm pÚ ,
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" ¯6u32ChannelNum ûÚ ,
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" ¯6u32CMRD ÊÚ PWM_SetAlignedType ûÚ ," ³6pwm lÚ ,
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" ³6u32ChannelMask Ú ,"" ³6 AlignedType SÚ! PWM_EnableAsymmetricMode Ú ," ·6pwm hÚ" PWM_DisableAsymmetricMode Ú ," ¹6pwm fÚ PWM_EnablePCA lÚ ," »6pwm dÚ PWM_DisablePCA ýÚ ," ½6pwm bÚ , pwm wÚ ,
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u32ChannelNum Ú ,
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u32Frequency ;Ú ,
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u32DutyCycle WÚ ," OperateType BÚ PWM_ConfigOutputChannel ÇÚ , pwm wÚ ,
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u32ChannelNum Ú , u16PeriodCycle Ú , u16PulseCycle îÚ PWM_SetPeriodAndDuty %Ú , pwm wÚ ,
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u32ChannelMask ¤Ú
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PWM_Start uÚ , pwm wÚ ,
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u32ChannelMask ¤Ú PWM_Stop ßÚ , pwm wÚ ,
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u32ChannelMask ¤Ú PWM_ForceStop æÚ , pwm wÚ ,
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u32ChannelMask ¤Ú! PWM_EnableOutputInverter >Ú , pwm wÚ ,
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u32ChannelMask ¤Ú" PWM_DisableOutputInverter ÏÚ P __PAN_WDT_H__ aÚ 8" _WDT_Timeout Ú " Ú6WDT_TIMEOUT_2POW4 yÚ " Ú6WDT_TIMEOUT_2POW6 wÚ " Ú6WDT_TIMEOUT_2POW8 uÚ " Ú6WDT_TIMEOUT_2POW10 JÚ " Ú6WDT_TIMEOUT_2POW12 HÚ " Ú6WDT_TIMEOUT_2POW14 FÚ " Ú6WDT_TIMEOUT_2POW15 EÚ " Ú6WDT_TIMEOUT_2POW16 DÚ " Ú6WDT_TIMEOUT_2POW17 CÚ " Ú6WDT_TIMEOUT_2POW18 BÚ " Ú6WDT_TIMEOUT_2POW19 AÚ " Ú6WDT_TIMEOUT_2POW20 IÚ " Ú6WDT_TIMEOUT_2POW21 HÚ " Ú6WDT_TIMEOUT_2POW22 GÚ " Ú6WDT_TIMEOUT_2POW23 FÚ " Ú6WDT_TIMEOUT_2POW24 EÚ WDT_TimeoutDef ¡Ú 8" _WDT_ResetDelay Ú " ì6WDT_RESET_DELAY_2CLK Ú " ì6WDT_RESET_DELAY_17CLK OÚ! " ì6WDT_RESET_DELAY_129CLK Ú" " ì6WDT_RESET_DELAY_1025CLK ëÚ WDT_ResetDelayDef Ú WDT_ClearResetFlag Ú WDT_ClearTimeoutFlag 6Ú WDT_ClearTimeoutIntFlag Ú# WDT_ClearTimeoutWakeupFlag ½Ú WDT_GetResetFlag éÚ WDT_GetTimeoutFlag Ú WDT_GetTimeoutIntFlag ÐÚ! WDT_GetTimeoutWakeupFlag Ú WDT_ResetCounter £Ú ," u32TimeoutInterval Ú ," u32ResetDelay äÚ ,
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u32EnableReset Ú ,
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u32EnableWakeup 3Ú WDT_Open øÚ
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WDT_Close Ú WDT_EnableInt Ú WDT_DisableInt Ú P __PAN_WWDT_H__ Ú 8" _WWDT_Prescale pÚ " 7WWDT_PRESCALER_1 *Ú " 7WWDT_PRESCALER_2 )Ú " 7WWDT_PRESCALER_4 'Ú " 7WWDT_PRESCALER_8 #Ú " 7WWDT_PRESCALER_16 òÚ " 7WWDT_PRESCALER_32 ôÚ " 7WWDT_PRESCALER_64 ïÚ " 7WWDT_PRESCALER_128 ¼Ú " 7WWDT_PRESCALER_192 »Ú " 7WWDT_PRESCALER_256 ºÚ " 7WWDT_PRESCALER_384 ¸Ú " 7WWDT_PRESCALER_512 ¿Ú " 7WWDT_PRESCALER_768 ²Ú " 7WWDT_PRESCALER_1024 Ú " 7WWDT_PRESCALER_1536 Ú " 7WWDT_PRESCALER_2048 Ú WWDT_PrescaleDef þÚ P WWDT_RELOAD_WORD ´Ú WWDT_ClearResetFlag ÅÚ WWDT_ClearIntFlag ¡Ú WWDT_ClearWWDTFFlag <Ú WWDT_GetResetFlag Ú WWDT_GetIntFlag lÚ WWDT_GetWWDTFFlag Ú WWDT_GetCounter 1Ú WWDT_GetCompareValue CÚ WWDT_ReloadCounter ôÚ ," preScale Ú ,
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u32CmpValue ÒÚ ,
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u32EnableInt {Ú
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WWDT_Open Ú WWDT_Close 9Ú P __PAN_LP_H__ ¶Ú P LP_EXT_P56_WK_EN ²Ú P LP_EXT_P56_WK_DISABLE GÚ P LP_EXT_P56_WK_EDGE_LOW ÓÚ P LP_EXT_P56_WK_EDGE_HIGH £Ú" P LP_WKUP_MODE_SEL_EXT_GPIO ²Ú P LP_WKUP_MODE_SEL_32K Ú P LP_WKUP_MODE_SEL_GPIO
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Ú P LP_WKUP_MODE_SEL_WDT LÚ P LP_WKUP_MODE_SEL_TIMER ¶Ú P LP_WKUP_MODE_SEL_BOD fÚ P LP_WKUP_MODE_SEL_LVR GÚ P LP_MODE_SEL_SLEEP_MODE àÚ# P LP_MODE_SEL_DEEPSLEEP_MODE ºÚ$ P LP_MODE_SEL_STANDBY_M1_MODE ]Ú$ P LP_MODE_SEL_STANDBY_M0_MODE ^Ú P LP_DEEPSLEEP_MODE_SEL HÚ P LP_DEEPSLEEP_MODE1 `Ú P LP_DEEPSLEEP_MODE2 _Ú P LP_DEEPSLEEP_MODE3 ^Ú P LP_STANDBY_M1_MODE_SEL ëÚ P LP_STANDBY_M1_MODE1 Ú P LP_STANDBY_M1_MODE2 Ú P LP_STANDBY_M1_MODE3 Ú LP_EnableInt oÚ ," ½7ana
Ú ,"" ½7 NewState yÚ LP_ClearWakeFlag ðÚ ," À7ana Ú ,
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" À7u32Mask RÚ LP_HpldoRdyBypassEn Ú ," Ã7ana Ú ,"" Ã7 NewState sÚ LP_FastClkDelayEn Ú ," Æ7ana |Ú ,"" Æ7 NewState pÚ , ana Ú , WkEdge £Ú LP_SetExternalWake ÒÚ , ana Ú ,
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u32ClkCnt ´Ú , idx Ú LP_SetSleepTime Ú , ana Ú , u16Clk32Cnt GÚ LP_SetLpldohDelay MÚ , ana Ú , u16Clk32Cnt GÚ LP_SetWakeDelay ,Ú , ana Ú , mode 9Ú LP_SetSleepMode %Ú , ana Ú ,
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wkMode lÚ , enterCyclically ¡Ú LP_SetSleepModeConfig ÃÚ , ana Ú ,
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wkMode lÚ , enterCyclically ¡Ú ,
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PowerCtrl 2Ú , dp_mode Ú LP_SetDeepSleepConfig ÊÚ! LP_SetStandbyMode0Config ±Ú' LP_SetStandbyMode0BodLvrConfig \Ú , ana Ú ,
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wkMode lÚ ,
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PowerCtrl 2Ú ,
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slpTimer Ú , spaceIdx ¥Ú ,
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stdy_mode Ú! LP_SetStandbyMode1Config °Ú P __PAN_EFUSE_H__ ÔÚ P EFUSE_CMD_READ Ú P EFUSE_CMD_PROGRAM Ú P EFUSE_CMD_INACTIVE JÚ P EFUSE_STATUS_OK ùÚ P EFUSE_STATUS_FAIL sÚ EFUSE_Init uÚ ," ò7efuse dÚ EFUSE_UnInit ®Ú ," ô7efuse bÚ EFUSE_GetErrorStatus GÚ ," ö7efuse `Ú EFUSE_ClrErrorStatus FÚ ," ø7efuse ^Ú , efuse ¯Ú ,
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addr <Ú EFUSE_ReadByte åÚ , efuse ¯Ú ,
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addr <Ú , data DÚ EFUSE_WriteByte TÚ , efuse ¯Ú ,
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addr <Ú , data /Ú , len Ú EFUSE_Read Ú , efuse ¯Ú ,
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addr <Ú , data /Ú , len Ú EFUSE_Write ðÚ , efuse ¯Ú ,
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addr <Ú , data /Ú , len Ú EFUSE_UserRead ÚÚ , efuse ¯Ú ,
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addr <Ú , data /Ú , len Ú EFUSE_UserWrite IÚ P __PAN_PRI_RF_H__ hÚ P PRI_RF_MODE_SEL_TX óÚ P PRI_RF_MODE_SEL_RX õÚ P PRI_RF_MODE_SEL_TRX Ú P PRI_RF_ADDR_BYTE_LEN_2 áÚ P PRI_RF_ADDR_BYTE_LEN_3 àÚ P PRI_RF_ADDR_BYTE_LEN_4 ßÚ P PRI_RF_ADDR_BYTE_LEN_5 ÞÚ! P PRI_RF_CHIP_MODE_INVALID LÚ P PRI_RF_CHIP_MODE_BLE Ú P PRI_RF_CHIP_MODE_297 ¹Ú P PRI_RF_CHIP_MODE_NORDIC Ú P REG_FILE_OFST ¹Ú P SEQ_RAM_OFST ðÚ P LIST_RAM_OFST Ú P TX_RX_RAM_OFST Ú P CTE_IQ_RAM_OFST þÚ P LLHWC_READ32_REG Ú P LLHWC_WRITE32_REG £Ú P READ_4_BYTES Ú P PRI_RF_WRITE_REG_VALUE ºÚ P PRI_RF_READ_REG_VALUE +Ú P PRI_RF_SET_FUNC_ENABLE áÚ! PRI_RF_AutoAnlsPayloadEn ßÚ ," ¬8rf ïÚ ,"" ¬8 NewState Ú PRI_RF_CrcCheckEn èÚ ," ¯8rf ìÚ ,"" ¯8 NewState Ú PRI_RF_Crc16Select °Ú ," ²8rf éÚ ,"" ²8 NewState Ú PRI_RF_ScambleEn )Ú ," µ8rf æÚ ,"" µ8 NewState Ú PRI_RF_NordicEnhanceEn ÃÚ ," ¸8rf ãÚ ,"" ¸8 NewState }Ú PRI_RF_IsNordicEnhance ºÚ ," »8rf àÚ PRI_RF_EnhanceEn .Ú ," ½8rf ÞÚ ,"" ½8 NewState xÚ PRI_RF_IsEnhance %Ú ," À8rf ÛÚ PRI_RF_BandWidth2mSel QÚ ," Â8rf ÙÚ ,"" Â8 NewState sÚ PRI_RF_ChipModeSel bÚ ," Å8rf ÖÚ ," Å8modeSel ðÚ PRI_RF_GetChipMode fÚ ," È8rf ÓÚ PRI_RF_RxAckEn Ú ," Ê8rf ÑÚ ,"" Ê8 NewState kÚ PRI_RF_IsRxAckEn KÚ ," Í8rf ÎÚ PRI_RF_TxNoAckEn HÚ ," Ï8rf ÌÚ ,"" Ï8 NewState fÚ PRI_RF_IsTxNoAckEn Ú ," Ò8rf ÉÚ PRI_RF_TrxFuncSel £Ú ," Ô8rf ÇÚ ,"" Ô8 NewState aÚ PRI_RF_IsRxSel íÚ ," ×8rf ÄÚ PRI_RF_ClearAllIrqEn ¬Ú ," Ù8rf ÂÚ ,"" Ù8 NewState \Ú PRI_RF_IntMask àÚ ," Ü8rf ¿Ú ,
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" Ü8msk XÚ ,"" Ü8 NewState YÚ PRI_RF_IntFlag òÚ ," à8rf »Ú ,
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" à8msk TÚ PRI_RF_ForceExitRx <Ú ," ã8rf ¸Ú ,"" ã8 NewState RÚ# PRI_RF_SetTrxTransWaitTime éÚ ," æ8rf µÚ ," æ8time æÚ PRI_RF_EnableRxPipeAdr ÑÚ ," é8rf ²Ú ," é8pipe äÚ ,"" é8 NewState LÚ PRI_RF_SetRxGoon
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Ú ," í8rf ®Ú ," í8en_flag ÅÚ PRI_RF_SetAddrMatchBit ÔÚ ," ð8rf «Ú ," ð8value uÚ PRI_RF_SetPayloadEndian @Ú ," ó8rf ¨Ú ," ó8endian Ú PRI_RF_MultiPreamble XÚ ," ö8rf ¥Ú ," ö8 pre_length ZÚ PRI_RF_StopRx )Ú ," ù8rf ¢Ú ," ù8en_flag ¹Ú PRI_RF_RandomNumGenInit FÚ ," ü8rf Ú" PRI_RF_RandomNumGenReinit kÚ ," þ8rf Ú PRI_RF_GetRandomNum ÜÚ ," 9rf Ú ana_prf_ldo_en %Ú ana_prf_ldo_dis ¶Ú , rf õÚ , mode 9Ú , len ¡Ú PRI_RF_SetTrxPayloadLen &Ú , rf õÚ , len ¡Ú PRI_RF_SetAddrByteLen #Ú , rf õÚ , mode 9Ú , pid £Ú PRI_RF_SetPidManual ÚÚ , rf õÚ , time &Ú PRI_RF_SetRxWaitTime eÚ , rf õÚ , mode 9Ú , pipe 0Ú , addr .Ú PRI_RF_SetTrxAddr Ú , rf õÚ , mode 9Ú ,
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addr <Ú" PRI_RF_SetTrxRamStartAddr bÚ , rf õÚ , mode 9Ú PRI_RF_IsTrxRamReady pÚ , rf õÚ , mode 9Ú , ready ÇÚ PRI_RF_SetTrxRamReady þÚ P _PAN_CLKTRIM_H_ ôÚ TRIM_SetIdealCnt Ú ," £9trim Ú ,
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" £9cnt Ú TRIM_GetIdealCnt Ú ," ¦9trim Ú TRIM_GetRealCnt rÚ ," ¨9trim
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Ú TRIM_IsIntStatusOccured ûÚ ," ª9trim Ú ,
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" ª9msk Ú TRIM_ClearIntStatusMsk lÚ ," 9trim Ú ,
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" 9msk Ú TRIM_EnableInt ËÚ ," °9trim Ú ,"" °9 NewState Ú! TRIM_SetRelationIncrease Ú ," ³9trim ÿÚ ,"" ³9 NewState Ú" TRIM_SetEarlyTerminatinEn 0Ú ," ¶9trim üÚ ,"" ¶9 NewState ~Ú TRIM_SetCoarseCode 1Ú ," ¹9trim ùÚ ,
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" ¹9code (Ú TRIM_GetCoarseCode =Ú ," ¼9trim öÚ TRIM_SetFineCode Ú ," ¾9trim ôÚ ,
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" ¾9code #Ú TRIM_GetFineCode Ú ," Á9trim ñÚ TRIM_SetBitWidth îÚ ," Ã9trim ïÚ ,
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" Ã9width Ú TRIM_GetBitWidth úÚ ," Æ9trim ìÚ TRIM_StartTuning ¶Ú ," È9trim êÚ ,
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" È9 function FÚ , trim Ú ,
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cnt Ú TRIM_SetCalWaitCnt 3Ú , trim Ú ,
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cnt Ú TRIM_SetCalCnt ÐÚ , trim Ú TRIM_GetCalCnt ÜÚ , trim Ú ,
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deviation
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Ú TRIM_SetErrRange ëÚ P PAN_POWER__H_ Ú 8
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<unnamed> QÚ " ×9buck_out_trim /Ú " ×9lph_ldo_vref_trim Ú " ×9 lpl_ldo_trim §Ú " ×9 hp_ldo_trim Ú power_param_t wÚ PW_ParamIsHas ÿÚ , p_otp ¥Ú PW_ParamsSet :Ú , temp !Ú PW_AutoOptimizeParams jÚ P __PAN_HAL_H__ {Ú P __PAN_HAL_GPIO_H__ ãÚ P __PAN_HAL_DEF_H__ EÚ DMAC_CallbackFunc ÒÚ UART_CB_FLAG_TX_FINISH Ú UART_CB_FLAG_RX_FINISH Ú UART_CB_FLAG_RX_TIMEOUT §Ú! UART_CB_FLAG_RX_BUFFFULL vÚ UART_CB_FLAG_DMA Ú UART_Cb_Flag_Opt 6Ú I2C_CB_FLAG_STOP Ú I2C_CB_FLAG_DMA Ú I2C_Cb_Flag_Opt ¶Ú ADC_CB_FLAG_DMA Ú ADC_Cb_Flag_Opt ¬Ú SPI_CB_FLAG_INT LÚ SPI_CB_FLAG_DMA eÚ SPI_CbFlagOpt JÚ UART_CallbackFunc «Ú I2C_CallbackFunc +Ú SPI_CallbackFunc ýÚ ADC_CallbackFunc !Ú P GPIO_P0_PIN_NUM
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Ú P GPIO_P1_PIN_NUM Ú P GPIO_P2_PIN_NUM Ú P GPIO_P3_PIN_NUM Ú P GPIO_INTEN_MASK_BASE Ú P GPIO_INTTYPE_MASK_BASE ßÚ P0_0 æÚ P0_1 åÚ P0_2 äÚ P0_3 ãÚ P0_4 âÚ P0_5 áÚ P0_6 àÚ P0_7 ßÚ P1_0 åÚ P1_1 äÚ P1_2 ãÚ P1_3 âÚ P1_4 áÚ P1_5 àÚ P1_6 ßÚ P1_7 ÞÚ P2_0 äÚ P2_1 ãÚ P2_2 âÚ P2_3 áÚ P2_4 àÚ P2_5 ßÚ P2_6 ÞÚ P2_7 ÝÚ P3_0 ãÚ P3_1 âÚ HAL_GPIO_PinId OÚ$ HAL_GPIO_MODE_INPUT_DIGITAL Ú# HAL_GPIO_MODE_INPUT_ANALOG âÚ& HAL_GPIO_MODE_OUTPUT_PUSHPULL °Ú' HAL_GPIO_MODE_OUTPUT_OPENDRAIN Ú* "HAL_GPIO_MODE_QUASI_BIDIRECTIONAL ÚÚ HAL_GPIO_Mode Ú HAL_GPIO_PULL_DISABLE Ú HAL_GPIO_PULL_UP ÚÚ HAL_GPIO_PULL_DOWN CÚ HAL_GPIO_Pull Ú HAL_GPIO_LEVEL_LOW NÚ HAL_GPIO_LEVEL_HIGH Ú HAL_GPIO_Level +Ú HAL_GPIO_INT_RISING ÿÚ HAL_GPIO_INT_FALLING ÌÚ HAL_GPIO_INT_BOTH_EDGE $Ú HAL_GPIO_INT_HIGH ¯Ú HAL_GPIO_INT_LOW ßÚ HAL_GPIO_INT_DISABLE ÕÚ HAL_GPIO_IntMode oÚ HAL_GPIO_CallbackFunc |Ú < hHAL_GPIO_CallbackArray kÚ 8
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<unnamed> QÚ "" ¯:mode Ú "" ¯:pull Ú "" ¯:level ©Ú HAL_GPIO_InitTypeDef ÒÚ 8
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<unnamed> QÚ "" ´:intMode åÚ " ´: callbackFunc üÚ "" ´: debounce qÚ HAL_GPIO_IntInitTypeDef ¡Ú ," pinID ìÚ , initStruct Ú HAL_GPIO_Init xÚ ," pinID ìÚ ," level ¨Ú HAL_GPIO_WritePin ÒÚ ," pinID ìÚ HAL_GPIO_ReadPin cÚ ," pinID ìÚ HAL_GPIO_TogglePin yÚ ," pinID ìÚ ," pull Ú HAL_GPIO_SetPull =Ú ," pinID ìÚ HAL_GPIO_DeInit ËÚ ," pinID ìÚ , intInitStruct SÚ HAL_GPIO_InterruptInit Ú ,
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pinID Ú ," intMode éÚ HAL_GPIO_SetIntMode $Ú ,
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pinID Ú ," debounce uÚ HAL_GPIO_SetIntDebounce |Ú P __PAN_HAL_UART_H__ ÖÚ HAL_UART_CB_TX_EMPTY Ú HAL_UART_CB_TX_FULL æÚ HAL_UART_CB_LINE_ERROR Ú HAL_UART_CB_TX_FINISH TÚ HAL_UART_CB_MODEM ¶Ú HAL_UART_CB_MAX FÚ UART_Callback_Type_Opt Ú# HAL_UART_INT_RECV_DATA_AVL ÅÚ HAL_UART_INT_THR_EMPTY ÜÚ! HAL_UART_INT_LINE_STATUS IÚ" HAL_UART_INT_MODEM_STATUS ýÚ HAL_UART_INT_ALL ëÚ HAL_UART_INT_DISABLE ÈÚ UART_Interrupt_Mode_Opt õÚ P UART_RX_BUF_SIZE Ú P UART_TX_BUF_SIZE Ú < uartRxBuffer RÚ < uartTxBuffer PÚ
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uartRxBufIdx Ú
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uartTxBufIdx Ú uartTxDone àÚ uartAddrRcvd $Ú uartRxIntFlag ½Ú HAL_UART_FMT_5_N_1 RÚ HAL_UART_FMT_5_N_1_5 ºÚ HAL_UART_FMT_5_E_1 [Ú HAL_UART_FMT_5_E_1_5 ÃÚ HAL_UART_FMT_5_O_1 QÚ HAL_UART_FMT_5_O_1_5 ¹Ú HAL_UART_FMT_5_S_1 MÚ HAL_UART_FMT_5_S_1_5 µÚ HAL_UART_FMT_5_M_1 SÚ HAL_UART_FMT_5_M_1_5 »Ú HAL_UART_FMT_6_N_1 QÚ HAL_UART_FMT_6_N_2 PÚ HAL_UART_FMT_6_E_1 ZÚ HAL_UART_FMT_6_E_2 YÚ HAL_UART_FMT_6_O_1 PÚ HAL_UART_FMT_6_O_2 OÚ HAL_UART_FMT_6_S_1 LÚ HAL_UART_FMT_6_S_2 KÚ HAL_UART_FMT_6_M_1 RÚ HAL_UART_FMT_6_M_2 QÚ HAL_UART_FMT_7_N_1 PÚ HAL_UART_FMT_7_N_2 OÚ HAL_UART_FMT_7_E_1 YÚ HAL_UART_FMT_7_E_2 XÚ HAL_UART_FMT_7_O_1 OÚ HAL_UART_FMT_7_O_2 NÚ HAL_UART_FMT_7_S_1 KÚ HAL_UART_FMT_7_S_2 JÚ HAL_UART_FMT_7_M_1 QÚ HAL_UART_FMT_7_M_2 PÚ HAL_UART_FMT_8_N_1 OÚ HAL_UART_FMT_8_N_2 NÚ HAL_UART_FMT_8_E_1 XÚ HAL_UART_FMT_8_E_2 WÚ HAL_UART_FMT_8_O_1 NÚ HAL_UART_FMT_8_O_2 MÚ HAL_UART_FMT_8_S_1 JÚ HAL_UART_FMT_8_S_2 IÚ HAL_UART_FMT_8_M_1 PÚ HAL_UART_FMT_8_M_2 OÚ UART_Format_Opt MÚ 8
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<unnamed> QÚ
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" ; baudRate ÄÚ "" ;format RÚ UART_Init_Opt &Ú 8
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<unnamed> QÚ " ; switchFlag ßÚ " ;interruptMode sÚ "" ; callbackTyp cÚ " ; callbackFunc Ú UART_Interrupt_Opt ãÚ 8
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<unnamed> QÚ " ;pUartx TÚ " ;initObj ÿÚ " ; interruptObj ¼Ú " ; pTxBuffPtr ÛÚ " ; txXferSize ÀÚ " ; txXferCount PÚ " ; pRxBuffPtr ÝÚ " ; rxXferSize ÂÚ " ; rxXferCount RÚ "" ;IRQn {Ú " ;rxIntCallback ¨Ú " ;txIntCallback ¦Ú
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" ;dmaSrc Ú
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" ;dmaDst Ú
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" ;
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errorCode ;Ú UART_HandleTypeDef EÚ P
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UART0_OBJ Ú P
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UART1_OBJ Ú < xUART_Handle_Array îÚ , pUart »Ú HAL_UART_Init kÚ , pUart »Ú , pBuf <Ú ,
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size Ú HAL_UART_SendData óÚ , pUart »Ú , pBuf <Ú ,
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size Ú ,
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timeout ÊÚ HAL_UART_ReceiveData ´Ú , pUart »Ú , pBuf <Ú ,
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size Ú , callback Ú HAL_UART_SendData_INT ¡Ú , pUart »Ú , pBuf <Ú ,
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size Ú ,
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timeout ÊÚ , callback Ú! HAL_UART_ReceiveData_INT bÚ , pUart »Ú , pBuf <Ú ,
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size Ú , callback Ú HAL_UART_SendData_DMA ºÚ , pUart »Ú , pBuf <Ú ,
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size Ú ,
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timeout ÊÚ , callback Ú! HAL_UART_ReceiveData_DMA {Ú , pUart »Ú HAL_UART_Init_INT Ú UART0_IRQHandler SÚ UART1_IRQHandler RÚ
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,
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t iÚ HAL_DelayMs ïÚ P __PAN_HAL_DMAC_H__ ýÚ DMAC_Peri_UART BÚ DMAC_Peri_I2C ÂÚ DMAC_Peri_SPI Ú DMAC_Peri_ADC ¸Ú DMAC_Peri_Mode_Opt cÚ 8
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<unnamed> QÚ " Ý;dma kÚ " Ý;
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ConfigTmp úÚ " Ý; Callback Ú " Ý; XferFlag Ú " Ý; CallbackUart âÚ " Ý; CallbackI2c ¢Ú " Ý; CallbackSpi TÚ " Ý; CallbackAdc xÚ "" Ý; PeriMode wÚ " Ý; pBuffPtr jÚ " Ý; XferSize oÚ DMAC_HandleTypeDef lÚ P DMAC_CHANNEL_NUMS Ú < pDMAC_Channel_Array ®Ú P DMAC_Channel_1 òÚ P DMAC_Channel_2 ñÚ P DMAC_Channel_3 ðÚ dma_uart2mem_config $Ú dma_mem2uart_config $Ú dma_spi2mem_config Ú dma_mem2spi_config Ú dma_mem2i2c_config äÚ dma_i2c2mem_config äÚ dma_adc2mem_config ºÚ dma_mem2i2c_u16_config ¡Ú HAL_DMA_Init ×Ú DMA_IRQHandler ñÚ P _PAN_HAL_SPI_H_ êÚ P SPI_RX_BUF_SIZE âÚ P SPI_TX_BUF_SIZE àÚ 8
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<unnamed> QÚ "" ü;Mode ðÚ SPI_InterruptOptDef Ú BAUDRATE_100K `Ú BAUDRATE_500K \Ú BAUDRATE_1M ÂÚ BAUDRATE_2M ÁÚ BAUDRATE_5M ¾Ú BAUDRATE_10M Ú SPI_BaudRate Ú 8
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<unnamed> QÚ "" <role 8Ú "" < dataSize Ú "" < clkPolarity NÚ "" < clkPhase ·Ú "" < baudrateDiv qÚ "" <format ]Ú SPI_InitOptDef ÄÚ SPI_STAT_NULL ÂÚ SPI_STAT_RX WÚ SPI_STAT_TX UÚ SPI_STAT_RXTX §Ú SPI_XferStatOpt 4Ú 8
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<unnamed> QÚ " <pSpix ÎÚ " <initObj Ú "" < xferStat Ú " < interruptObj ËÚ " < pTxBuffPtr ãÚ " < txXferSize ÈÚ " < txXferCount XÚ " < pRxBuffPtr åÚ " < rxXferSize ÊÚ " < rxXferCount ZÚ "" <IRQn Ú " <rxIntCallback °Ú " <txIntCallback ®Ú
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" <dmaSrc Ú
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" <dmaDst Ú
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" <
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errorCode CÚ SPI_HandleTypeDef Ú < hspiHandleArray ²Ú P SPI0_OBJ eÚ P SPI1_OBJ dÚ , pSpi -Ú HAL_SPI_Init ½Ú , pSpi -Ú HAL_SPI_DeInit Ú , pSpi -Ú HAL_SPI_Init_INT kÚ , pSpi -Ú HAL_SPI_DeInit_INT ¾Ú , pSpi -Ú , pBuf <Ú ,
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size Ú ,
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timeout ÊÚ HAL_SPI_SendData EÚ , pSpi -Ú , pBuf <Ú ,
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size Ú ,
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timeout ÊÚ HAL_SPI_ReceiveData Ú , pSpi -Ú , pSendBuf ªÚ ,
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sendBufSize gÚ , pRecvBuf ¤Ú ,
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recvBufSize aÚ HAL_SPI_SendReceiveData tÚ , pSpi -Ú , pBuf <Ú ,
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size Ú , callback Ú HAL_SPI_SendData_INT óÚ , pSpi -Ú , pBuf <Ú ,
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size Ú , callback Ú HAL_SPI_ReceiveData_INT ´Ú , pSpi -Ú , pSendBuf ªÚ ,
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sendBufSize gÚ , sendCallback Ú , pRecvBuf ¤Ú ,
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recvBufSize aÚ , recvCallback üÚ$ HAL_SPI_SendReceiveData_INT "Ú , pSpi -Ú , pBuf <Ú ,
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size Ú , callback Ú HAL_SPI_SendData_DMA Ú , pSpi -Ú , pBuf <Ú ,
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size Ú , callback Ú HAL_SPI_ReceiveData_DMA ÍÚ , pSpi -Ú , pSendBuf ªÚ ,
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sendBufSize gÚ , sendCallback Ú , pRecvBuf ¤Ú ,
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recvBufSize aÚ , recvCallback üÚ$ HAL_SPI_SendReceiveData_DMA ;Ú P __PAN_HAL_I2C_H Ú I2C_ADDR_7BIT 6Ú I2C_ADDR_10BIT
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Ú I2C_AddressMode_Opt áÚ I2C_ROLE_MASTER eÚ I2C_ROLE_SLAVE ¸Ú I2C_Role_Opt ¨Ú I2C_DUTYCYCLE_16_9 ¨Ú I2C_DUTYCYCLE_2 {Ú I2C_DutyCycle_Opt Ú I2C_DIR_TX âÚ I2C_DIR_RX äÚ I2C_Direction_Opt Ú I2C_ACK_ADDR_7BIT Ú I2C_ACK_ADDR_10BIT ÔÚ I2C_AckAddr_Opt ªÚ I2C_SPEED_100K Ú I2C_SPEED_200K Ú I2C_SPEED_400K Ú I2C_SPEED_500K Ú I2C_SPEED_1M zÚ I2C_SPEED_2M yÚ I2C_ClockSpeed_Opt QÚ 8
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<unnamed> QÚ "" û< ClockSpeed Ú "" û<Role ãÚ "" û<
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DutyCycle ÔÚ " û< OwnAddress Ú "" û< AckAddress Ú "" û< AddressMode Ú I2C_Init_Opt ¦Ú I2C_Tx_Dir Ú I2C_Rx_Dir Ú I2C_Xfer_Dir_Opt Ú 8
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<unnamed> QÚ " =pass NÚ I2C_Interrupt_Opt cÚ 8
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<unnamed> QÚ " =I2Cx ·Ú " = I2C_InitObj Ú " = InterruptObj ôÚ " = pTxBuffPtr ìÚ " = TxXferSize ñÚ " = TxXferCount Ú " = pRxBuffPtr îÚ " = RxXferSize óÚ " = RxXferCount Ú "" =IRQn Ú " =RxIntCallback ÙÚ " =TxIntCallback ×Ú
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" =DMA_SRC ÜÚ
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" =DMA_DST ÙÚ " = StopFlag ÚÚ I2C_HandleTypeDef ÅÚ , i2c ÍÚ HAL_I2C_Init ëÚ , i2c ÍÚ HAL_I2C_DeInit >Ú , i2c ÍÚ HAL_I2C_Init_INT Ú , i2c ÍÚ HAL_I2C_DeInit_INT ìÚ , i2c ÍÚ , DevAddress äÚ , Buf ®Ú ,
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Size <Ú ,
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Timeout êÚ HAL_I2C_Master_SendData Ú , i2c ÍÚ , DevAddress äÚ , Buf ®Ú ,
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Size <Ú ,
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Timeout êÚ# HAL_I2C_Master_ReceiveData [Ú , i2c ÍÚ , DevAddress äÚ , Buf ®Ú ,
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Size <Ú , Callback ´Ú$ HAL_I2C_Master_SendData_INT HÚ , i2c ÍÚ , DevAddress äÚ , Buf ®Ú ,
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Size <Ú , Callback ´Ú' HAL_I2C_Master_ReceiveData_INT Ú , i2c ÍÚ , DevAddress äÚ , Buf ®Ú ,
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Size <Ú , Callback ´Ú$ HAL_I2C_Master_SendData_DMA aÚ , i2c ÍÚ , DevAddress äÚ , Buf ®Ú ,
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Size <Ú , Callback ´Ú' HAL_I2C_Master_ReceiveData_DMA "Ú , i2c ÍÚ , Buf ®Ú ,
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Size <Ú ,
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Timeout êÚ HAL_I2C_Slave_SendData Ú , i2c ÍÚ , Buf ®Ú ,
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Size <Ú ,
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Timeout êÚ" HAL_I2C_Slave_ReceiveData ÎÚ , i2c ÍÚ , Buf ®Ú ,
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Size <Ú , Callback ´Ú# HAL_I2C_Slave_SendData_INT »Ú , i2c ÍÚ , Buf ®Ú ,
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Size <Ú , Callback ´Ú& HAL_I2C_Slave_ReceiveData_INT |Ú , i2c ÍÚ , Buf ®Ú ,
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Size <Ú , Callback ´Ú# HAL_I2C_Slave_SendData_DMA ÔÚ , i2c ÍÚ , Buf ®Ú ,
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Size <Ú , Callback ´Ú& HAL_I2C_Slave_ReceiveData_DMA Ú P __PAN_HAL_WDT_H çÚ 8
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<unnamed> QÚ "" å=Timeout Ú "" å= ResetDelay Ú
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" å= ClockSource 4Ú
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" å= ResetSwitch Ú
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" å= WakeupSwitch °Ú WDT_Init_Opt uÚ WDT_CallbackFunc úÚ 8
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<unnamed> QÚ " í= CallbackFunc àÚ WDT_Interrupt_Opt 2Ú , wdt |Ú HAL_WDT_Init ºÚ HAL_WDT_DeInit Ú , wdt |Ú HAL_WDT_Feed ÚÚ , opt xÚ HAL_WDT_Init_INT hÚ HAL_WDT_DeInit_INT »Ú WDT_IRQHandler ÔÚ P __PAN_HAL_WWDT_H Ú WWDT_CallbackFunc ¡Ú 8
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<unnamed> QÚ "" û=
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Prescaler ÈÚ
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" û= ClockSource Ú
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" û= CmpValue dÚ WWDT_Init_Opt Ú 8
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<unnamed> QÚ " > CallbackFunc LÚ WWDT_Interrupt_Opt ÙÚ , wwdt Ú HAL_WWDT_Init aÚ HAL_WWDT_DeInit ´Ú , wwdt Ú HAL_WWDT_Feed Ú , wwdt Ú HAL_WWDT_Init_INT Ú HAL_WWDT_DeInit_INT bÚ WWDT_IRQHandler {Ú P __PAN_HAL_PWM_H âÚ PWM0_CH0 ¯Ú PWM0_CH1 ®Ú PWM0_CH2 Ú PWM0_CH3 ¬Ú PWM0_CH4 «Ú PWM0_CH5 ªÚ PWM0_CH6 ©Ú PWM0_CH7 ¨Ú PWM_ChId FÚ PWM_MODE_INDEPENDENT ÐÚ PWM_MODE_COMPLEMENTARY Ú PWM_MODE_SYNCHRONIZED \Ú PWM_MODE_GROUP }Ú PWM_ModeOpt àÚ 8
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<unnamed> QÚ
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" >
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frequency Ú
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" >
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dutyCycle (Ú "" > operateType 3Ú "" >mode -Ú " > inverter xÚ " > lowPowerEn ÑÚ PWM_InitOpt ÑÚ! P HAL_PWM_PinConfiguration Ú ," chId JÚ , pInitObj ¢Ú HAL_PWM_Init µÚ ,
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handle gÚ HAL_PWM_DeInit Ú ,
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handle gÚ HAL_PWM_Start 9Ú ,
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handle gÚ , force ÍÚ HAL_PWM_Stop £Ú ,
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handle gÚ ,
|
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frequency ûÚ ,
|
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dutyCycle Ú HAL_PWM_SetFreqAndDuty ÂÚ P __PAN_HAL_TIMER_H QÚ TIMER_CB_FLAG_CNT ¹Ú TIMER_CB_FLAG_CAP ÊÚ TIMER_CB_FLAG_WK þÚ TIMER_Cb_Flag_Opt ïÚ TIMER_CallbackFunc dÚ TIMER_MODE_BASECNT uÚ TIMER_MODE_EVENTCNT Ú TIMER_MODE_INCAP Ú TIMER_MODE_WAKEUP ªÚ TIMER_Mode_Opt îÚ 8
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<unnamed> QÚ " ½>pass Ú TIMER_Interrupt_Opt Ú 8
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<unnamed> QÚ
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" À>freq Ú "" À>mode Ú "" À>cntMode ÛÚ "" À>capMode îÚ
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" À> cmpValue ~Ú "" À>capEdge ÿÚ "" À> evtCntEdge ¹Ú "" À>capSrc KÚ
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" À> prescale lÚ "" À> tmr0CmpSel ÛÚ TIMER_Init_Opt ßÚ 8
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<unnamed> QÚ " Ì>TIMERx ¬Ú " $Ì>initObj °Ú " Ì> interruptObj Ú "" Ì>IRQn HÚ " Ì> callback tÚ TIMER_HandleTypeDef þÚ P TIMER0_OBJ ÌÚ P TIMER1_OBJ ËÚ P TIMER2_OBJ ÊÚ < TIMER_Handle_Array Ú HAL_TIMER_US_TO_CNT ÌÚ ,
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" ×>timeUs %Ú ,(" ×>
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frequency ¢Ú (" ×>cnt _Ú HAL_TIMER_MS_TO_CNT ÔÚ ,
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" Û>timeMs )Ú ,(" Û>
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frequency Ú (" Û>cnt [Ú , pTimer TÚ HAL_TIMER_Init $Ú , pTimer TÚ HAL_TIMER_DeInit wÚ , pTimer TÚ HAL_TIMER_Init_INT ÒÚ , pTimer TÚ HAL_TIMER_DeInit_INT %Ú , pTimer TÚ HAL_TIMER_Start ¨Ú , pTimer TÚ HAL_TIMER_Stop Ú , pTimer TÚ HAL_TIMER_GetRealFreq xÚ P __PAN_HAL_ADC_H Ú ADC_MODE_CONV Ú ADC_MODE_EXTRIG aÚ ADC_MODE_COMPARE +Ú ADC_MODE_PWMSEQ WÚ ADC_MODE_SGLCONVSEQ 'Ú ADC_ModeOpt Ú ADC_CONV_MODE_BASE ~Ú ADC_CONV_MODE_TEMP cÚ ADC_CONV_MODE_VBG ¼Ú ADC_CONV_MODE_VDD4 Ú ADC_ConvertModeOpt Ú ADC_CH0 Ú ADC_CH1 Ú ADC_CH2 Ú ADC_CH3
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Ú ADC_CH4 Ú ADC_CH5 Ú ADC_CH6 Ú ADC_CH7 Ú ADC_CH_TEMP Ú ADC_CH_BATTERY µÚ ADC_IDLE ¨Ú ADC_ChId rÚ ADC_INPUT_RANGE_LOW Ú ADC_INPUT_RANGE_HIGH ÓÚ ADC_InputRangeOpt Ú 8
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<unnamed> QÚ "" ? InputRange ÜÚ "" ?Mode `Ú ADC_InitOpt ýÚ 8
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<unnamed> QÚ " ?initOpt ùÚ "" ?id Ú ADC_HandleTypeDef »Ú , pADC Ú HAL_ADC_Init áÚ , pADC Ú HAL_ADC_DeInit 4Ú , pADC Ú , value ªÚ HAL_ADC_GetValue PÚ PAN_HAL_SUCCESS TÚ PAN_HAL_INVALID_PARAMS 5Ú PAN_HAL_IO_ERROR êÚ PAN_HAL_DEVICE_BUSY Ú PAN_HAL_NO_MEM Ú# PAN_HAL_NO_HARDWARE_SOURCE ÝÚ PAN_HAL_UNKNOWN =Ú PanHalError Ú P NIMBLE_SPARK_SUP »Ú P configUSE_TICKLESS_IDLE üÚ P configCPU_CLOCK_HZ }Ú
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clk_32k_count ðÚ P configTICK_RATE_HZ zÚ P configTOTAL_HEAP_SIZE Ú! P configMINIMAL_STACK_SIZE ¯Ú) P !configSUPPORT_DYNAMIC_ALLOCATION /Ú( P configSUPPORT_STATIC_ALLOCATION nÚ P configMAX_PRIORITIES ÞÚ P configUSE_PREEMPTION ÞÚ P configUSE_TIME_SLICING FÚ P configIDLE_SHOULD_YIELD Ú P configMAX_TASK_NAME_LEN ñÚ P configUSE_16_BIT_TICKS [Ú P configUSE_TIMERS Ú" P configTIMER_TASK_PRIORITY /Ú! P configTIMER_QUEUE_LENGTH Ú% P configTIMER_TASK_STACK_DEPTH aÚ P configUSE_MUTEXES ¼Ú$ P configUSE_RECURSIVE_MUTEXES Ú& P configUSE_COUNTING_SEMAPHORES Ú P configUSE_QUEUE_SETS ¾Ú% P configUSE_TASK_NOTIFICATIONS eÚ. P &configEXPECTED_IDLE_TIME_BEFORE_SLEEP ÄÚ' P configUSE_APPLICATION_TASK_TAG ÌÚ# P configUSE_NEWLIB_REENTRANT Ú P configUSE_CO_ROUTINES uÚ" P configQUEUE_REGISTRY_SIZE ,Ú P configASSERT kÚ P configUSE_IDLE_HOOK 5Ú P configUSE_TICK_HOOK (Ú+ P #configUSE_DAEMON_TASK_STARTUP_HOOK ]Ú% P configUSE_MALLOC_FAILED_HOOK
Ú P configENABLE_MPU =Ú P configENABLE_FPU DÚ P configENABLE_TRUSTZONE EÚ( P configMINIMAL_SECURE_STACK_SIZE {Ú' P configRUN_FREERTOS_SECURE_ONLY Ú2 P *configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES AÚ P configPRIO_BITS lÚ0 P (configLIBRARY_LOWEST_INTERRUPT_PRIORITY ¨Ú5 P -configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY Ú( P configKERNEL_INTERRUPT_PRIORITY IÚ- P %configMAX_SYSCALL_INTERRUPT_PRIORITY Ú! P INCLUDE_vTaskPrioritySet ¡Ú" P INCLUDE_uxTaskPriorityGet 4Ú P INCLUDE_vTaskDelete æÚ P INCLUDE_vTaskSuspend UÚ P INCLUDE_vTaskDelayUntil 6Ú P INCLUDE_vTaskDelay LÚ' P INCLUDE_xTaskGetIdleTaskHandle ¤Ú P INCLUDE_xTaskAbortDelay HÚ% P INCLUDE_xQueueGetMutexHolder "Ú) P !INCLUDE_xSemaphoreGetMutexHolder {Ú P INCLUDE_xTaskGetHandle ÅÚ, P $INCLUDE_uxTaskGetStackHighWaterMark ~Ú- P %INCLUDE_uxTaskGetStackHighWaterMark2 JÚ P INCLUDE_eTaskGetState %Ú# P INCLUDE_xTaskResumeFromISR 6Ú' P INCLUDE_xTimerPendFunctionCall jÚ' P INCLUDE_xTaskGetSchedulerState aÚ* P "INCLUDE_xTaskGetCurrentTaskHandle 9Ú P xPortPendSVHandler Ú P vPortSVCHandler èÚ P xPortSysTickHandler Ú P PROJDEFS_H ³Ú TaskFunction_t 9Ú P pdMS_TO_TICKS ^Ú P pdFALSE ~Ú P pdTRUE «Ú P pdPASS ´Ú P pdFAIL ÏÚ P errQUEUE_EMPTY óÚ P errQUEUE_FULL QÚ. P &errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ÕÚ P errQUEUE_BLOCKED Ú P errQUEUE_YIELD Ú P pdINTEGRITY_CHECK_VALUE qÚ P pdFREERTOS_ERRNO_NONE ïÚ P pdFREERTOS_ERRNO_ENOENT RÚ P pdFREERTOS_ERRNO_EINTR Ú P pdFREERTOS_ERRNO_EIO DÚ P pdFREERTOS_ERRNO_ENXIO Ú P pdFREERTOS_ERRNO_EBADF ËÚ P pdFREERTOS_ERRNO_EAGAIN vÚ% P pdFREERTOS_ERRNO_EWOULDBLOCK ÖÚ P pdFREERTOS_ERRNO_ENOMEM ZÚ P pdFREERTOS_ERRNO_EACCES wÚ P pdFREERTOS_ERRNO_EFAULT ZÚ P pdFREERTOS_ERRNO_EBUSY Ú P pdFREERTOS_ERRNO_EEXIST IÚ P pdFREERTOS_ERRNO_EXDEV ¡Ú P pdFREERTOS_ERRNO_ENODEV ZÚ! P pdFREERTOS_ERRNO_ENOTDIR Ú P pdFREERTOS_ERRNO_EISDIR [Ú P pdFREERTOS_ERRNO_EINVAL \Ú P pdFREERTOS_ERRNO_ENOSPC SÚ P pdFREERTOS_ERRNO_ESPIPE UÚ P pdFREERTOS_ERRNO_EROFS Ú! P pdFREERTOS_ERRNO_EUNATCH Ú P pdFREERTOS_ERRNO_EBADE ÌÚ P pdFREERTOS_ERRNO_EFTYPE NÚ! P pdFREERTOS_ERRNO_ENMFILE Ú# P pdFREERTOS_ERRNO_ENOTEMPTY PÚ& P pdFREERTOS_ERRNO_ENAMETOOLONG Ú$ P pdFREERTOS_ERRNO_EOPNOTSUPP öÚ! P pdFREERTOS_ERRNO_ENOBUFS Ú% P pdFREERTOS_ERRNO_ENOPROTOOPT ¨Ú$ P pdFREERTOS_ERRNO_EADDRINUSE /Ú# P pdFREERTOS_ERRNO_ETIMEDOUT eÚ% P pdFREERTOS_ERRNO_EINPROGRESS ÀÚ" P pdFREERTOS_ERRNO_EALREADY ÐÚ' P pdFREERTOS_ERRNO_EADDRNOTAVAIL OÚ! P pdFREERTOS_ERRNO_EISCONN
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Ú" P pdFREERTOS_ERRNO_ENOTCONN ³Ú# P pdFREERTOS_ERRNO_ENOMEDIUM rÚ P pdFREERTOS_ERRNO_EILSEQ XÚ# P pdFREERTOS_ERRNO_ECANCELED ¡Ú! P pdFREERTOS_LITTLE_ENDIAN "Ú P pdFREERTOS_BIG_ENDIAN $Ú P pdLITTLE_ENDIAN ýÚ P pdBIG_ENDIAN ÿÚ P PORTABLE_H ·Ú! P DEPRECATED_DEFINITIONS_H Ú' P OPEN_WATCOM_INDUSTRIAL_PC_PORT =Ú( P OPEN_WATCOM_FLASH_LITE_186_PORT 3Ú P GCC_MEGA_AVR #Ú P IAR_MEGA_AVR Ú P MPLAB_PIC24_PORT øÚ P MPLAB_DSPIC_PORT ÇÚ P MPLAB_PIC18F_PORT Ú P MPLAB_PIC32MX_PORT PÚ P _FEDPICC lÚ P SDCC_CYGNAL yÚ P GCC_ARM7 vÚ P GCC_ARM7_ECLIPSE Ú P ROWLEY_LPC23xx 8Ú P IAR_MSP430 óÚ P GCC_MSP430 Ú P ROWLEY_MSP430 çÚ P ARM7_LPC21xx_KEIL_RVDS ÓÚ P SAM7_GCC uÚ P SAM7_IAR fÚ P SAM9XE_IAR ÃÚ P LPC2000_IAR ×Ú P STR71X_IAR ÁÚ P STR75X_IAR ½Ú P STR75X_GCC ÌÚ P STR91X_IAR ¿Ú P GCC_H8S ¼Ú P GCC_AT91FR40008 ìÚ P RVDS_ARMCM3_LM3S102 QÚ P GCC_ARMCM3_LM3S102 ÅÚ P GCC_ARMCM3 æÚ P IAR_ARM_CM3 vÚ P IAR_ARMCM3_LM ÙÚ P HCS12_CODE_WARRIOR eÚ P MICROBLAZE_GCC Ú P TERN_EE Ú P
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GCC_HCS12 JÚ P GCC_MCF5235 âÚ P COLDFIRE_V2_GCC PÚ P COLDFIRE_V2_CODEWARRIOR ÌÚ P GCC_PPC405 Ú P GCC_PPC440 Ú P _16FX_SOFTUNE ÈÚ P BCC_INDUSTRIAL_PC_PORT áÚ P BCC_FLASH_LITE_186_PORT ×Ú P __AVR32_AVR32A__ ñÚ P __ICCAVR32__ Ú P __91467D ¬Ú P __96340 ÷Ú P __IAR_V850ES_Fx3__ Ú P __IAR_V850ES_Jx3__ Ú P __IAR_V850ES_Jx3_L__ `Ú P __IAR_V850ES_Jx2__ Ú P __IAR_V850ES_Hx2__ Ú P __IAR_78K0R_Kx3__ _Ú P __IAR_78K0R_Kx3L__ Ú P portENTER_CRITICAL ºÚ P PORTMACRO_H WÚ P portCHAR ØÚ P
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portFLOAT ~Ú P portDOUBLE 7Ú P portLONG ÆÚ P
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portSHORT dÚ P portSTACK_TYPE ÓÚ P portBASE_TYPE 0Ú StackType_t Ú BaseType_t ýÚ UBaseType_t ¦Ú TickType_t íÚ P portMAX_DELAY 8Ú P portTICK_TYPE_IS_ATOMIC õÚ P portSTACK_GROWTH 6Ú P portBYTE_ALIGNMENT °Ú vPortYield ÂÚ P portNVIC_INT_CTRL_REG Ú P portNVIC_PENDSVSET_BIT QÚ P
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portYIELD }Ú P portEND_SWITCHING_ISR ©Ú P portYIELD_FROM_ISR Ú vPortEnterCritical Ú vPortExitCritical æÚ" ulSetInterruptMaskFromISR ÎÚ ,
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ulMask fÚ# vClearInterruptMaskFromISR |Ú( P portSET_INTERRUPT_MASK_FROM_ISR EÚ* P "portCLEAR_INTERRUPT_MASK_FROM_ISR ÆÚ P portDISABLE_INTERRUPTS gÚ P portENABLE_INTERRUPTS ¶Ú P portEXIT_CRITICAL Ú% P portSUPPRESS_TICKS_AND_SLEEP bÚ ,
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xExpectedIdleTime Ú# vPortSuppressTicksAndSleep *Ú P portTASK_FUNCTION_PROTO íÚ P portTASK_FUNCTION ìÚ P portNOP Ú P portBYTE_ALIGNMENT_MASK Ú P portUSING_MPU_WRAPPERS 0Ú% P portNUM_CONFIGURABLE_REGIONS Ú( P portHAS_STACK_OVERFLOW_CHECKING ©Ú P portARCH_NAME NÚ2 P *configSTACK_ALLOCATION_FROM_SEPARATE_HEAP Ú P MPU_WRAPPERS_H CÚ P PRIVILEGED_FUNCTION õÚ P PRIVILEGED_DATA IÚ P FREERTOS_SYSTEM_CALL zÚ , pxTopOfStack óÚ , pxCode bÚ , pvParameters ¿Ú pxPortInitialiseStack 0Ú 8 HeapRegion ÏÚ " ApucStartAddress ¸Ú
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" A xSizeInBytes Ú HeapRegion_t 4Ú 8 xHeapStats ¬Ú%
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" AxAvailableHeapSpaceInBytes §Ú)
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" A xSizeOfLargestFreeBlockInBytes ûÚ*
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" A xSizeOfSmallestFreeBlockInBytes Ú
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" AxNumberOfFreeBlocks `Ú)
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" A xMinimumEverFreeBytesRemaining ·Ú)
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" A xNumberOfSuccessfulAllocations Ú#
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" AxNumberOfSuccessfulFrees !Ú HeapStats_t Ú , pxHeapRegions zÚ vPortDefineHeapRegions Ú , pxHeapStats FÚ vPortGetHeapStats þÚ ,
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xSize ÂÚ pvPortMalloc íÚ ,
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xNum /Ú ,
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xSize ÂÚ pvPortCalloc ÷Ú , pv çÚ
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vPortFree 9Ú vPortInitialiseBlocks :Ú xPortGetFreeHeapSize èÚ( xPortGetMinimumEverFreeHeapSize dÚ P pvPortMallocStack ÐÚ P vPortFreeStack Ú% vApplicationMallocFailedHook Ú xPortStartScheduler øÚ vPortEndScheduler õÚ( P configUSE_C_RUNTIME_TLS_SUPPORT Ú P INCLUDE_xTaskDelayUntil 4Ú0 P (configNUM_THREAD_LOCAL_STORAGE_POINTERS ïÚ" P configUSE_ALTERNATIVE_API _Ú$ P portCRITICAL_NESTING_IN_TCB àÚ P configASSERT_DEFINED Ú P configPRECONDITION £Ú# P configPRECONDITION_DEFINED EÚ P portMEMORY_BARRIER £Ú P portSOFTWARE_BARRIER Ú P portCLEAN_UP_TCB GÚ! P portPRE_TASK_DELETE_HOOK »Ú P portSETUP_TCB #Ú! P configUSE_MINI_LIST_ITEM Ú P portPOINTER_SIZE_TYPE Ú P traceSTART Ú P traceEND ÕÚ P traceTASK_SWITCHED_IN ¯Ú! P traceINCREASE_TICK_COUNT ÐÚ" P traceLOW_POWER_IDLE_BEGIN kÚ P traceLOW_POWER_IDLE_END ýÚ P traceTASK_SWITCHED_OUT LÚ# P traceTASK_PRIORITY_INHERIT Ú& P traceTASK_PRIORITY_DISINHERIT Ú' P traceBLOCKING_ON_QUEUE_RECEIVE õÚ$ P traceBLOCKING_ON_QUEUE_PEEK ÙÚ$ P traceBLOCKING_ON_QUEUE_SEND ÔÚ' P configCHECK_FOR_STACK_OVERFLOW ÍÚ( P configRECORD_STACK_HIGH_ADDRESS Ú2 P *configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H ]Ú' P traceMOVED_TASK_TO_READY_STATE ½Ú, P $tracePOST_MOVED_TASK_TO_READY_STATE Ú P traceQUEUE_CREATE Ú! P traceQUEUE_CREATE_FAILED ðÚ P traceCREATE_MUTEX ôÚ! P traceCREATE_MUTEX_FAILED âÚ" P traceGIVE_MUTEX_RECURSIVE VÚ) P !traceGIVE_MUTEX_RECURSIVE_FAILED DÚ" P traceTAKE_MUTEX_RECURSIVE \Ú) P !traceTAKE_MUTEX_RECURSIVE_FAILED JÚ' P traceCREATE_COUNTING_SEMAPHORE Ú. P &traceCREATE_COUNTING_SEMAPHORE_FAILED ñÚ P traceQUEUE_SET_SEND =Ú P traceQUEUE_SEND Ú P traceQUEUE_SEND_FAILED ~Ú P traceQUEUE_RECEIVE ±Ú P traceQUEUE_PEEK Ú P traceQUEUE_PEEK_FAILED Ú! P traceQUEUE_PEEK_FROM_ISR £Ú" P traceQUEUE_RECEIVE_FAILED Ú! P traceQUEUE_SEND_FROM_ISR Ú( P traceQUEUE_SEND_FROM_ISR_FAILED Ú$ P traceQUEUE_RECEIVE_FROM_ISR ¿Ú+ P #traceQUEUE_RECEIVE_FROM_ISR_FAILED Ú( P traceQUEUE_PEEK_FROM_ISR_FAILED Ú P traceQUEUE_DELETE Ú P traceTASK_CREATE VÚ P traceTASK_CREATE_FAILED DÚ P traceTASK_DELETE WÚ P traceTASK_DELAY_UNTIL ¦Ú P traceTASK_DELAY Ú P traceTASK_PRIORITY_SET 1Ú P traceTASK_SUSPEND æÚ P traceTASK_RESUME 9Ú" P traceTASK_RESUME_FROM_ISR GÚ! P traceTASK_INCREMENT_TICK ËÚ P traceTIMER_CREATE Ú! P traceTIMER_CREATE_FAILED ôÚ P traceTIMER_COMMAND_SEND &Ú P traceTIMER_EXPIRED §Ú$ P traceTIMER_COMMAND_RECEIVED Ú P traceMALLOC îÚ P
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traceFREE Ú P traceEVENT_GROUP_CREATE Ú' P traceEVENT_GROUP_CREATE_FAILED ûÚ$ P traceEVENT_GROUP_SYNC_BLOCK ²Ú" P traceEVENT_GROUP_SYNC_END JÚ) P !traceEVENT_GROUP_WAIT_BITS_BLOCK Ú' P traceEVENT_GROUP_WAIT_BITS_END ·Ú$ P traceEVENT_GROUP_CLEAR_BITS ÁÚ- P %traceEVENT_GROUP_CLEAR_BITS_FROM_ISR ÏÚ" P traceEVENT_GROUP_SET_BITS @Ú+ P #traceEVENT_GROUP_SET_BITS_FROM_ISR NÚ P traceEVENT_GROUP_DELETE Ú P tracePEND_FUNC_CALL iÚ% P tracePEND_FUNC_CALL_FROM_ISR wÚ P traceQUEUE_REGISTRY_ADD Ú$ P traceTASK_NOTIFY_TAKE_BLOCK ÍÚ P traceTASK_NOTIFY_TAKE £Ú$ P traceTASK_NOTIFY_WAIT_BLOCK ½Ú P traceTASK_NOTIFY_WAIT Ú P traceTASK_NOTIFY 1Ú" P traceTASK_NOTIFY_FROM_ISR ?Ú' P traceTASK_NOTIFY_GIVE_FROM_ISR «Ú) P !traceSTREAM_BUFFER_CREATE_FAILED Ú0 P (traceSTREAM_BUFFER_CREATE_STATIC_FAILED KÚ" P traceSTREAM_BUFFER_CREATE Ú" P traceSTREAM_BUFFER_DELETE Ú! P traceSTREAM_BUFFER_RESET ÅÚ, P $traceBLOCKING_ON_STREAM_BUFFER_SEND dÚ P traceSTREAM_BUFFER_SEND Ú' P traceSTREAM_BUFFER_SEND_FAILED Ú) P !traceSTREAM_BUFFER_SEND_FROM_ISR .Ú/ P 'traceBLOCKING_ON_STREAM_BUFFER_RECEIVE
Ú# P traceSTREAM_BUFFER_RECEIVE AÚ* P "traceSTREAM_BUFFER_RECEIVE_FAILED /Ú, P $traceSTREAM_BUFFER_RECEIVE_FROM_ISR OÚ& P configGENERATE_RUN_TIME_STATS Ú/ P 'portCONFIGURE_TIMER_FOR_RUN_TIME_STATS "Ú P portPRIVILEGE_BIT ÿÚ P portYIELD_WITHIN_API üÚ6 P .configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING íÚ# P configPRE_SLEEP_PROCESSING Ú$ P configPOST_SLEEP_PROCESSING ¥Ú% P portTASK_USES_FLOATING_POINT `Ú$ P portALLOCATE_SECURE_CONTEXT áÚ P portDONT_DISCARD XÚ? P 7configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS ¢Ú- P %configUSE_STATS_FORMATTING_FUNCTIONS ÀÚ1 P )portASSERT_IF_INTERRUPT_PRIORITY_INVALID Ú! P configUSE_TRACE_FACILITY ¶Ú P mtCOVERAGE_TEST_MARKER ²Ú P mtCOVERAGE_TEST_DELAY Ú P portASSERT_IF_IN_ISR ÛÚ0 P (configUSE_PORT_OPTIMISED_TASK_SELECTION ÒÚ) P !configAPPLICATION_ALLOCATED_HEAP |Ú. P &configTASK_NOTIFICATION_ARRAY_ENTRIES Ú P configUSE_POSIX_ERRNO gÚ( P configUSE_SB_COMPLETED_CALLBACK ®Ú P configSTACK_DEPTH_TYPE >Ú$ P configRUN_TIME_COUNTER_TYPE |Ú) P !configMESSAGE_BUFFER_LENGTH_TYPE 5Ú! P configINITIAL_TICK_COUNT ©Ú% P portTICK_TYPE_ENTER_CRITICAL {Ú$ P portTICK_TYPE_EXIT_CRITICAL ÁÚ2 P *portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR Ú4 P ,portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR Ú, P $configENABLE_BACKWARD_COMPATIBILITY Ú P configPRINTF jÚ P
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configMAX ]Ú P
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configMIN _Ú P eTaskStateGet Ú P portTickType ÁÚ P xTaskHandle ^Ú P xQueueHandle êÚ P xSemaphoreHandle CÚ P xQueueSetHandle ¸Ú P xQueueSetMemberHandle TÚ P xTimeOutType ÒÚ P xMemoryRegion \Ú P xTaskParameters Ú P xTaskStatusType |Ú P xTimerHandle îÚ P xCoRoutineHandle OÚ P pdTASK_HOOK_CODE Ú P portTICK_RATE_MS 1Ú P pcTaskGetTaskName Ú P pcTimerGetTimerName /Ú P pcQueueGetQueueName 'Ú P vTaskGetTaskInfo cÚ# P xTaskGetIdleRunTimeCounter JÚ P tmrTIMER_CALLBACK IÚ P pdTASK_CODE 4Ú P
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xListItem Ú P xList Ú P pxContainer *Ú# P configUSE_TASK_FPU_SUPPORT ¼Ú P configENABLE_MVE GÚ# P configRUN_ADDITIONAL_TESTS Ú2 P *tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE ÄÚ 8 xSTATIC_LIST_ITEM :Ú
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" ÒBxDummy2 ñÚ <" ÒB pvDummy3 BÚ StaticListItem_t {Ú 8 xSTATIC_MINI_LIST_ITEM ¤Ú
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" ÖBxDummy2 íÚ <" ÖB pvDummy3 FÚ StaticMiniListItem_t æÚ 8 xSTATIC_LIST ÒÚ " ÚB uxDummy2 jÚ " ÚB pvDummy3 jÚ " ÚBxDummy4 ÍÚ StaticList_t Ú 8 xSTATIC_TCB 7Ú " ßB pxDummy1 eÚ <" (ßBxDummy3 Ú " ßB uxDummy5 bÚ " ßB pxDummy6 `Ú <" ßB ucDummy7 ?Ú <" ßB
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uxDummy12 Ú <" ßB
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ulDummy18 Ú <" ßB
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ucDummy19 Ú " ßB
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ucDummy21 VÚ StaticTask_t Ú 8 xSTATIC_QUEUE Ú <" êB pvDummy1 0Ú 8
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<unnamed> SÚ " ìB pvDummy2 YÚ " ìB uxDummy2 XÚ " êBu Ú <" (êBxDummy3 Ú <" êB uxDummy4 &Ú <" êB ucDummy5 DÚ " êB pvDummy7 VÚ StaticQueue_t §Ú StaticSemaphore_t Ú 8 xSTATIC_EVENT_GROUP Ú
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" öBxDummy1 ÎÚ " öBxDummy2 «Ú StaticEventGroup_t Ú 8 xSTATIC_TIMER Ú " úB pvDummy1 LÚ " úBxDummy2 §Ú
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" úBxDummy3 ÈÚ " úB pvDummy5 HÚ " úB pvDummy6 GÚ " úB ucDummy8 hÚ StaticTimer_t «Ú 8 xSTATIC_STREAM_BUFFER Ú <" C uxDummy1 Ú <" C pvDummy2 Ú " C ucDummy3 äÚ StaticStreamBuffer_t ØÚ StaticMessageBuffer_t }Ú P QUEUE_H Ú P INC_TASK_H ¤Ú P LIST_H ÜÚ P configLIST_VOLATILE 4Ú2 P *listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE UÚ3 P +listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE Ú- P %listFIRST_LIST_INTEGRITY_CHECK_VALUE íÚ. P &listSECOND_LIST_INTEGRITY_CHECK_VALUE ·Ú6 P .listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE Ú7 P /listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE ÌÚ- P %listSET_LIST_INTEGRITY_CHECK_1_VALUE ùÚ- P %listSET_LIST_INTEGRITY_CHECK_2_VALUE øÚ% P listTEST_LIST_ITEM_INTEGRITY PÚ P listTEST_LIST_INTEGRITY èÚ 8 xLIST Ú 8 xLIST_ITEM oÚ
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" C xItemValue ×Ú " CpxNext NÚ " C pxPrevious Ú " CpvOwner âÚ " C pvContainer BÚ ListItem_t ïÚ 8 xMINI_LIST_ITEM ÙÚ
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" C xItemValue ÐÚ " CpxNext GÚ " C pxPrevious Ú MiniListItem_t ZÚ " CuxNumberOfItems ½Ú " CpxIndex ôÚ " C xListEnd Ú List_t Ú P listSET_LIST_ITEM_OWNER âÚ P listGET_LIST_ITEM_OWNER îÚ P listSET_LIST_ITEM_VALUE ðÚ P listGET_LIST_ITEM_VALUE üÚ) P !listGET_ITEM_VALUE_OF_HEAD_ENTRY /Ú P listGET_HEAD_ENTRY ©Ú P listGET_NEXT yÚ P listGET_END_MARKER ´Ú P listLIST_IS_EMPTY ÈÚ P listCURRENT_LIST_LENGTH Ú$ P listGET_OWNER_OF_NEXT_ENTRY Ú P listREMOVE_ITEM Ú P listINSERT_END èÚ$ P listGET_OWNER_OF_HEAD_ENTRY ¹Ú P listIS_CONTAINED_WITHIN Ú P listLIST_ITEM_CONTAINER Ú P listLIST_IS_INITIALISED Ú , pxList AÚ vListInitialise Ú , pxItem NÚ vListInitialiseItem Ú , pxList AÚ , pxNewListItem zÚ vListInsert KÚ , pxList AÚ , pxNewListItem zÚ vListInsertEnd .Ú , pxItemToRemove Ú uxListRemove ÙÚ! P tskKERNEL_VERSION_NUMBER ÛÚ P tskKERNEL_VERSION_MAJOR -Ú P tskKERNEL_VERSION_MINOR !Ú P tskKERNEL_VERSION_BUILD 6Ú P tskMPU_REGION_READ_ONLY Ú! P tskMPU_REGION_READ_WRITE ÏÚ$ P tskMPU_REGION_EXECUTE_NEVER ÝÚ$ P tskMPU_REGION_NORMAL_MEMORY ÎÚ$ P tskMPU_REGION_DEVICE_MEMORY çÚ# P tskDEFAULT_INDEX_TO_NOTIFY /Ú 8 tskTaskControlBlock îÚ TaskHandle_t 7Ú TaskHookFunction_t Ú eRunning §Ú eReady Ú eBlocked ÔÚ eSuspended ÙÚ eDeleted ÑÚ eInvalid ÁÚ eTaskState ôÚ
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eNoAction kÚ eSetBits ÊÚ eIncrement ßÚ eSetValueWithOverwrite àÚ" eSetValueWithoutOverwrite Ú eNotifyAction «Ú 8
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xTIME_OUT µÚ " ÞCxOverflowCount ±Ú
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" ÞCxTimeOnEntering Ú
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TimeOut_t UÚ 8 xMEMORY_REGION 5Ú " âCpvBaseAddress UÚ
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" âCulLengthInBytes
Ú
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" âC ulParameters Ú MemoryRegion_t 5Ú 8 xTASK_PARAMETERS §Ú " çC pvTaskCode Ú " çCpcName 1Ú " çC usStackDepth ²Ú " çC pvParameters Ú " çC uxPriority 4Ú " çCpuxStackBuffer ÈÚ <" çC xRegions Ú TaskParameters_t gÚ 8 xTASK_STATUS ¿Ú " ðCxHandle ¶Ú " ðC pcTaskName Ú " ðC xTaskNumber Ú "" ðCeCurrentState Ú " ðCuxCurrentPriority :Ú " ðCuxBasePriority ¨Ú
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" ðCulRunTimeCounter ñÚ " ðC pxStackBase Ú " ðCusStackHighWaterMark Ú TaskStatus_t ÿÚ eAbortSleep Ú eStandardSleep RÚ eNoTasksWaitingTimeout ïÚ eSleepModeStatus zÚ P tskIDLE_PRIORITY ZÚ P
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taskYIELD Ú P taskENTER_CRITICAL ÌÚ$ P taskENTER_CRITICAL_FROM_ISR ÚÚ P taskEXIT_CRITICAL Ú# P taskEXIT_CRITICAL_FROM_ISR Ú P taskDISABLE_INTERRUPTS yÚ P taskENABLE_INTERRUPTS ÈÚ P taskSCHEDULER_SUSPENDED AÚ" P taskSCHEDULER_NOT_STARTED Ú P taskSCHEDULER_RUNNING ÏÚ , pxTaskCode ÇÚ , pcName qÚ , usStackDepth òÚ , pvParameters ¿Ú , uxPriority tÚ , pxCreatedTask Ú xTaskCreate sÚ , xTask ¼Ú ,
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pxRegions Ú vTaskAllocateMPURegions ÃÚ , xTaskToDelete Ú vTaskDelete vÚ ,
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xTicksToDelay Ú vTaskDelay ÜÚ , pxPreviousWakeTime QÚ ,
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xTimeIncrement Ú xTaskDelayUntil ÄÚ P vTaskDelayUntil ©Ú , xTask ¼Ú xTaskAbortDelay ØÚ , xTask ¼Ú uxTaskPriorityGet ÄÚ , xTask ¼Ú! uxTaskPriorityGetFromISR 4Ú , xTask ¼Ú eTaskGetState µÚ , xTask ¼Ú , pxTaskStatus ºÚ , xGetFreeStackSpace ¹Ú ," eState XÚ vTaskGetInfo Ú , xTask ¼Ú , uxNewPriority DÚ vTaskPrioritySet 1Ú , xTaskToSuspend Ú vTaskSuspend åÚ , xTaskToResume xÚ vTaskResume XÚ , xTaskToResume xÚ xTaskResumeFromISR ÆÚ vTaskStartScheduler Ú vTaskEndScheduler Ú vTaskSuspendAll ÆÚ xTaskResumeAll 7Ú xTaskGetTickCount Ú! xTaskGetTickCountFromISR wÚ uxTaskGetNumberOfTasks øÚ , xTaskToQuery ÕÚ pcTaskGetName ÇÚ , pcNameToQuery Ú xTaskGetHandle UÚ , xTask ¼Ú$ uxTaskGetStackHighWaterMark Ú , xTask ¼Ú% uxTaskGetStackHighWaterMark2 ÚÚ , xTask ¼Ú , pvParameter 4Ú% xTaskCallApplicationTaskHook Ú xTaskGetIdleTaskHandle 4Ú , pxTaskStatusArray ±Ú , uxArraySize :Ú , pulTotalRunTime Ú uxTaskGetSystemState Ú , pcWriteBuffer Ú
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vTaskList 1Ú , pcWriteBuffer Ú vTaskGetRunTimeStats ÄÚ$ ulTaskGetIdleRunTimeCounter üÚ$ ulTaskGetIdleRunTimePercent Ú , xTaskToNotify pÚ , uxIndexToNotify Ú ,
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ulValue óÚ ," eAction ùÚ% , pulPreviousNotificationValue Ú xTaskGenericNotify Ú P xTaskNotify 1Ú P xTaskNotifyIndexed bÚ P xTaskNotifyAndQuery øÚ# P xTaskNotifyAndQueryIndexed )Ú , xTaskToNotify pÚ , uxIndexToNotify Ú ,
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ulValue óÚ ," eAction ùÚ% , pulPreviousNotificationValue Ú" , pxHigherPriorityTaskWoken gÚ" xTaskGenericNotifyFromISR óÚ P xTaskNotifyFromISR ¡Ú" P xTaskNotifyIndexedFromISR ÒÚ* P "xTaskNotifyAndQueryIndexedFromISR Ú# P xTaskNotifyAndQueryFromISR hÚ , uxIndexToWaitOn ¿Ú ,
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ulBitsToClearOnEntry ËÚ ,
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ulBitsToClearOnExit EÚ , pulNotificationValue tÚ ,
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xTicksToWait ùÚ xTaskGenericNotifyWait æÚ P xTaskNotifyWait Ú P xTaskNotifyWaitIndexed ÅÚ P xTaskNotifyGive Ú P xTaskNotifyGiveIndexed ÏÚ , xTaskToNotify pÚ , uxIndexToNotify Ú" , pxHigherPriorityTaskWoken gÚ& vTaskGenericNotifyGiveFromISR bÚ P vTaskNotifyGiveFromISR Ú& P vTaskNotifyGiveIndexedFromISR AÚ , uxIndexToWaitOn ¿Ú , xClearCountOnExit øÚ ,
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xTicksToWait ùÚ ulTaskGenericNotifyTake Ú P ulTaskNotifyTake 9Ú P ulTaskNotifyTakeIndexed jÚ , xTask ¼Ú , uxIndexToClear ,Ú% xTaskGenericNotifyStateClear Ú P xTaskNotifyStateClear 5Ú% P xTaskNotifyStateClearIndexed fÚ , xTask ¼Ú , uxIndexToClear ,Ú ,
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ulBitsToClear ¨Ú& ulTaskGenericNotifyValueClear Ú P ulTaskNotifyValueClear ÎÚ& P ulTaskNotifyValueClearIndexed ÿÚ ,
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pxTimeOut Ú vTaskSetTimeOutState ÃÚ ,
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pxTimeOut Ú , pxTicksToWait yÚ xTaskCheckForTimeOut éÚ ,
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xTicksToCatchUp àÚ xTaskCatchUpTicks Ú xTaskIncrementTick Ú , pxEventList 5Ú ,
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xTicksToWait ùÚ vTaskPlaceOnEventList uÚ , pxEventList 5Ú ,
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xItemValue ÇÚ ,
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xTicksToWait ùÚ' vTaskPlaceOnUnorderedEventList »Ú , pxEventList 5Ú ,
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xTicksToWait ùÚ , xWaitIndefinitely ÆÚ( vTaskPlaceOnEventListRestricted HÚ , pxEventList 5Ú! xTaskRemoveFromEventList Ú , pxEventListItem Ú ,
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xItemValue ÇÚ* "vTaskRemoveFromUnorderedEventList UÚ vTaskSwitchContext dÚ" uxTaskResetEventItemValue ¥Ú" xTaskGetCurrentTaskHandle ÉÚ vTaskMissedYield cÚ xTaskGetSchedulerState ñÚ , pxMutexHolder ^Ú xTaskPriorityInherit Ú , pxMutexHolder ^Ú xTaskPriorityDisinherit :Ú , pxMutexHolder ^Ú% , uxHighestPriorityWaitingTask Ú, $vTaskPriorityDisinheritAfterTimeout KÚ , xTask ¼Ú uxTaskGetTaskNumber &Ú , xTask ¼Ú , uxHandle Ú vTaskSetTaskNumber Ú ,
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xTicksToJump òÚ vTaskStepTick Ú$ eTaskConfirmSleepModeStatus êÚ& pvTaskIncrementMutexHeldCount ÷Ú ,
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pxTimeOut Ú% vTaskInternalSetTimeOutState vÚ 8 QueueDefinition Ú QueueHandle_t ÃÚ QueueSetHandle_t Ú QueueSetMemberHandle_t -Ú P queueSEND_TO_BACK èÚ P queueSEND_TO_FRONT nÚ P queueOVERWRITE ÃÚ P queueQUEUE_TYPE_BASE ÞÚ P queueQUEUE_TYPE_SET Ú P queueQUEUE_TYPE_MUTEX dÚ+ P #queueQUEUE_TYPE_COUNTING_SEMAPHORE sÚ) P !queueQUEUE_TYPE_BINARY_SEMAPHORE Ú( P queueQUEUE_TYPE_RECURSIVE_MUTEX 9Ú P xQueueCreate âÚ P xQueueSendToFront ÖÚ P xQueueSendToBack pÚ P xQueueSend °Ú P xQueueOverwrite iÚ , xQueue HÚ , pvItemToQueue zÚ ,
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xTicksToWait ùÚ , xCopyPosition WÚ xQueueGenericSend Ú , xQueue HÚ , pvBuffer Ú ,
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xTicksToWait ùÚ xQueuePeek ÒÚ , xQueue HÚ , pvBuffer Ú xQueuePeekFromISR BÚ , xQueue HÚ , pvBuffer Ú ,
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xTicksToWait ùÚ xQueueReceive Ú , xQueue HÚ uxQueueMessagesWaiting ¿Ú , xQueue HÚ uxQueueSpacesAvailable êÚ , xQueue HÚ vQueueDelete Ú! P xQueueSendToFrontFromISR FÚ P xQueueSendToBackFromISR àÚ P xQueueOverwriteFromISR ÙÚ P xQueueSendFromISR Ú , xQueue HÚ , pvItemToQueue zÚ" , pxHigherPriorityTaskWoken gÚ , xCopyPosition WÚ! xQueueGenericSendFromISR rÚ , xQueue HÚ" , pxHigherPriorityTaskWoken gÚ xQueueGiveFromISR <Ú , xQueue HÚ , pvBuffer Ú" , pxHigherPriorityTaskWoken gÚ xQueueReceiveFromISR þÚ , xQueue HÚ" xQueueIsQueueEmptyFromISR çÚ , xQueue HÚ! xQueueIsQueueFullFromISR eÚ , xQueue HÚ& uxQueueMessagesWaitingFromISR /Ú , xQueue HÚ , pvItemToQueue zÚ" , xCoRoutinePreviouslyWoken QÚ xQueueCRSendFromISR ¤Ú , xQueue HÚ , pvBuffer Ú , pxTaskWoken <Ú xQueueCRReceiveFromISR eÚ , xQueue HÚ , pvItemToQueue zÚ ,
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xTicksToWait ùÚ xQueueCRSend 4Ú , xQueue HÚ , pvBuffer Ú ,
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xTicksToWait ùÚ xQueueCRReceive õÚ , ucQueueType QÚ xQueueCreateMutex âÚ , ucQueueType QÚ , pxStaticQueue bÚ xQueueCreateMutexStatic nÚ , uxMaxCount §Ú , uxInitialCount ûÚ& xQueueCreateCountingSemaphore òÚ , uxMaxCount §Ú , uxInitialCount ûÚ , pxStaticQueue bÚ, $xQueueCreateCountingSemaphoreStatic ~Ú , xQueue HÚ ,
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xTicksToWait ùÚ xQueueSemaphoreTake Ú , xSemaphore ¡Ú xQueueGetMutexHolder ²Ú , xSemaphore ¡Ú$ xQueueGetMutexHolderFromISR "Ú , xMutex :Ú ,
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xTicksToWait ùÚ! xQueueTakeMutexRecursive ëÚ , xMutex :Ú! xQueueGiveMutexRecursive åÚ P xQueueReset 5Ú , xQueue HÚ , pcQueueName bÚ vQueueAddToRegistry "Ú , xQueue HÚ vQueueUnregisterQueue Ú , xQueue HÚ pcQueueGetName SÚ , uxQueueLength iÚ , uxItemSize ¬Ú , ucQueueType QÚ xQueueGenericCreate 4Ú , uxEventQueueLength ]Ú xQueueCreateSet ÍÚ , xQueueOrSemaphore ÍÚ ,
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xQueueSet Ú xQueueAddToSet WÚ , xQueueOrSemaphore ÍÚ ,
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xQueueSet Ú xQueueRemoveFromSet Ú ,
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xQueueSet Ú ,
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xTicksToWait ùÚ xQueueSelectFromSet %Ú ,
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xQueueSet Ú# xQueueSelectFromSetFromISR Ú , xQueue HÚ ,
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xTicksToWait ùÚ , xWaitIndefinitely ÆÚ' vQueueWaitForMessageRestricted Ú , xQueue HÚ ,
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xNewQueue Ú xQueueGenericReset Ú , xQueue HÚ , uxQueueNumber bÚ vQueueSetQueueNumber «Ú , xQueue HÚ uxQueueGetQueueNumber >Ú , xQueue HÚ ucQueueGetQueueType Ú P SEMAPHORE_H jÚ SemaphoreHandle_t Ú) P !semBINARY_SEMAPHORE_QUEUE_LENGTH yÚ' P semSEMAPHORE_QUEUE_ITEM_LENGTH Ú P semGIVE_BLOCK_TIME ßÚ P vSemaphoreCreateBinary ÌÚ P xSemaphoreCreateBinary ÊÚ P xSemaphoreTake Ú P xSemaphoreTakeRecursive DÚ P xSemaphoreGive Ú P xSemaphoreGiveRecursive >Ú P xSemaphoreGiveFromISR xÚ P xSemaphoreTakeFromISR ~Ú P xSemaphoreCreateMutex Ú' P xSemaphoreCreateRecursiveMutex TÚ! P xSemaphoreCreateCounting äÚ P vSemaphoreDelete >Ú! P xSemaphoreGetMutexHolder îÚ( P xSemaphoreGetMutexHolderFromISR ^Ú P uxSemaphoreGetCount ëÚ# P uxSemaphoreGetCountFromISR [Ú P TIMERS_H @Ú- P %tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR SÚ$ P tmrCOMMAND_EXECUTE_CALLBACK EÚ$ P tmrCOMMAND_START_DONT_TRACE ôÚ P tmrCOMMAND_START lÚ P tmrCOMMAND_RESET wÚ P tmrCOMMAND_STOP ¶Ú! P tmrCOMMAND_CHANGE_PERIOD "Ú P tmrCOMMAND_DELETE EÚ" P tmrFIRST_FROM_ISR_COMMAND Ú" P tmrCOMMAND_START_FROM_ISR zÚ" P tmrCOMMAND_RESET_FROM_ISR
Ú! P tmrCOMMAND_STOP_FROM_ISR ÄÚ* P "tmrCOMMAND_CHANGE_PERIOD_FROM_ISR 0Ú 8 tmrTimerControl rÚ TimerHandle_t ÇÚ TimerCallbackFunction_t ¬Ú PendedFunction_t xÚ , pcTimerName fÚ ,
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xTimerPeriodInTicks (Ú , xAutoReload [Ú ,
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pvTimerID KÚ , pxCallbackFunction rÚ xTimerCreate Ú , xTimer LÚ pvTimerGetTimerID 1Ú , xTimer LÚ , pvNewID &Ú vTimerSetTimerID Ú , xTimer LÚ xTimerIsTimerActive 0Ú' xTimerGetTimerDaemonTaskHandle ßÚ P xTimerStart .Ú P xTimerStop Ú P xTimerChangePeriod
Ú P xTimerDelete çÚ P xTimerReset 9Ú P xTimerStartFromISR Ú P xTimerStopFromISR Ú" P xTimerChangePeriodFromISR õÚ P xTimerResetFromISR ©Ú , xFunctionToPend «Ú , pvParameter1 Ú ,
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ulParameter2 Ú" , pxHigherPriorityTaskWoken gÚ& xTimerPendFunctionCallFromISR jÚ , xFunctionToPend «Ú , pvParameter1 Ú ,
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ulParameter2 Ú ,
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xTicksToWait ùÚ xTimerPendFunctionCall úÚ , xTimer LÚ pcTimerGetName WÚ , xTimer LÚ , xAutoReload [Ú vTimerSetReloadMode CÚ , xTimer LÚ xTimerGetReloadMode MÚ , xTimer LÚ uxTimerGetReloadMode ÖÚ , xTimer LÚ xTimerGetPeriod ÎÚ , xTimer LÚ xTimerGetExpiryTime Ú xTimerCreateTimerTask ]Ú , xTimer LÚ , xCommandID Ú ,
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xOptionalValue Ú" , pxHigherPriorityTaskWoken gÚ ,
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xTicksToWait ùÚ xTimerGenericCommand ËÚ P _Static_assert ÷Ú P BLE_NPL_OS_ALIGNMENT Ú P BLE_NPL_TIME_FOREVER Ú ble_npl_time_t (Ú ble_npl_stime_t ³Ú " âqueued VÚ " âfn þÚ " âarg Ú 8 ble_npl_eventq ÛÚ " ¥Gq \Ú 8 ble_npl_callout xÚ " §Ghandle UÚ " §Gevq {Ú " §Gev âÚ 8 ble_npl_mutex =Ú " «Ghandle QÚ 8 ble_npl_sem /Ú " Ghandle OÚ P _NPL_FREERTOS_H_ Ú% npl_freertos_eventq_dflt_get Ú , evq Ú ,
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tmo Ú npl_freertos_eventq_get Ú , evq Ú , ev òÚ npl_freertos_eventq_put ýÚ , evq Ú , ev òÚ# npl_freertos_eventq_remove ÂÚ , mu ëÚ npl_freertos_mutex_init Ú , mu ëÚ ,
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timeout ÊÚ npl_freertos_mutex_pend Ú , mu ëÚ# npl_freertos_mutex_release ÏÚ , sem Ú , tokens =Ú npl_freertos_sem_init ôÚ , sem Ú ,
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timeout ÊÚ npl_freertos_sem_pend Ú , sem Ú! npl_freertos_sem_release ÁÚ , co ûÚ , evq Ú , ev_cb ÈÚ , ev_arg QÚ" npl_freertos_callout_init =Ú , co ûÚ ,
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ticks ·Ú# npl_freertos_callout_reset ÌÚ , co ûÚ ,
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now
Ú- %npl_freertos_callout_remaining_ticks ¤Ú ,
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ms ûÚ ,
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out_ticks êÚ& npl_freertos_time_ms_to_ticks Ú ,
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ticks ·Ú , out_ms .Ú& npl_freertos_time_ticks_to_ms Ú , irqn Ú , addr .Ú npl_freertos_hw_set_isr Ú' npl_freertos_hw_enter_critical 4Ú ,
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ctx Ú& npl_freertos_hw_exit_critical Ú ble_npl_os_started ]Ú$ ble_npl_get_current_task_id £Ú ble_npl_eventq_init íÚ ," âGevq 4Ú ble_npl_eventq_get cÚ ," äGevq 2Ú ,
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" äGtmo <Ú ble_npl_eventq_put JÚ ," çGevq /Ú ," çGev ¢Ú ble_npl_eventq_remove Ú ," êGevq ,Ú ," êGev Ú ble_npl_event_run ÁÚ ," íGev Ú ble_npl_eventq_is_empty /Ú ," ïGevq 'Ú ble_npl_event_init `Ú ," ñGev Ú ," ñGfn Ú ," ñGarg 7Ú ble_npl_event_is_queued FÚ ," õGev Ú ble_npl_event_get_arg 5Ú ," ÷Gev Ú ble_npl_event_set_arg )Ú ," ùGev Ú ," ùGarg /Ú ble_npl_mutex_init OÚ ," üGmu Ú ble_npl_mutex_pend \Ú ," þGmu Ú ,
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" þGtimeout cÚ ble_npl_mutex_release Ú ," Hmu Ú ble_npl_sem_init AÚ ," Hsem Ú ," Htokens PÚ ble_npl_sem_pend NÚ ," Hsem Ú ,
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" Htimeout ÚÚ ble_npl_sem_release Ú ," Hsem Ú ble_npl_sem_get_count #Ú ," Hsem Ú ble_npl_callout_init Ú ," Hco Ú ," Hevq Ú ," Hev_cb ÑÚ ," Hev_arg ZÚ ble_npl_callout_reset Ú ," Hco ÿÚ ,
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" Hticks »Ú ble_npl_callout_stop xÚ ," Hco üÚ" ble_npl_callout_is_active }Ú ," Hco úÚ" ble_npl_callout_get_ticks wÚ ," Hco øÚ( ble_npl_callout_remaining_ticks ñÚ ," Hco öÚ ,
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" Htime #Ú ble_npl_callout_set_arg SÚ ," Hco óÚ ," Harg Ú ble_npl_time_get KÚ! ble_npl_time_ms_to_ticks ÜÚ ,
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" ¢Hms ïÚ ," ¢H
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out_ticks ÞÚ! ble_npl_time_ticks_to_ms ÜÚ ,
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" ¥Hticks ¨Ú ," ¥Hout_ms Ú# ble_npl_time_ms_to_ticks32 sÚ ,
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" ¨Hms éÚ# ble_npl_time_ticks_to_ms32 sÚ ,
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" ªHticks £Ú ble_npl_time_delay xÚ ,
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" ¬Hticks ¡Ú P NIMBLE_CFG_CONTROLLER VÚ ble_npl_hw_set_isr ^Ú ," ¯Hirqn Ú ," ¯Haddr Ú" ble_npl_hw_enter_critical Ú! ble_npl_hw_exit_critical çÚ ,
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" ³Hctx mÚ , evq Ú , evq Ú ,
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tmo Ú , evq Ú , ev òÚ , evq Ú , ev òÚ , ev òÚ , fn ùÚ , arg Ú , ev òÚ , ev òÚ , ev òÚ , arg Ú , evq Ú , ev òÚ , mu ëÚ , mu ëÚ ,
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timeout ÊÚ , mu ëÚ , sem Ú , tokens =Ú , sem Ú ,
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timeout ÊÚ , sem Ú , sem Ú , co ûÚ , evq Ú , ev_cb ÈÚ , ev_arg QÚ , co ûÚ ,
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ticks ·Ú , co ûÚ , co ûÚ , co ûÚ , co ûÚ ,
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time (Ú , co ûÚ , arg Ú ,
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ms ûÚ ,
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out_ticks êÚ ,
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ticks ·Ú , out_ms .Ú ,
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ms ûÚ ,
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ticks ·Ú ,
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ticks ·Ú , irqn Ú , addr .Ú ,
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ctx Ú" ble_npl_hw_is_in_critical Ú P OS_ALIGN OÚ P OS_ALIGNMENT Ú os_sr_t úÚ P OS_ENTER_CRITICAL Ú P OS_EXIT_CRITICAL ÆÚ P OS_ASSERT_CRITICAL *Ú P
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H_ENDIAN_ Ú P __inttypes_h ®Ú P __LP64__ 7Ú P __PRISCN64 ÀÚ P __PRISCNPTR 2Ú P PRId8 :Ú P PRId16 Ú P PRId32 Ú P PRId64 Ú P PRIdLEAST8 ·Ú P PRIdLEAST16 Ú P PRIdLEAST32 Ú P PRIdLEAST64 Ú P
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PRIdFAST8 Ú P PRIdFAST16 ÓÚ P PRIdFAST32 ÕÚ P PRIdFAST64 ÐÚ P PRIdMAX Ú P PRIdPTR xÚ P PRIi8 5Ú P PRIi16 Ú P PRIi32 Ú P PRIi64 Ú P PRIiLEAST8 ²Ú P PRIiLEAST16 Ú P PRIiLEAST32 Ú P PRIiLEAST64 ~Ú P
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PRIiFAST8 ÿÚ P PRIiFAST16 ÎÚ P PRIiFAST32 ÐÚ P PRIiFAST64 ËÚ P PRIiMAX Ú P PRIiPTR sÚ P PRIo8 /Ú P PRIo16 þÚ P PRIo32 Ú P PRIo64 ûÚ P PRIoLEAST8 ¬Ú P PRIoLEAST16 {Ú P PRIoLEAST32 }Ú P PRIoLEAST64 xÚ P
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PRIoFAST8 ùÚ P PRIoFAST16 ÈÚ P PRIoFAST32 ÊÚ P PRIoFAST64 ÅÚ P PRIoMAX }Ú P PRIoPTR mÚ P PRIu8 )Ú P PRIu16 øÚ P PRIu32 úÚ P PRIu64 õÚ P PRIuLEAST8 ¦Ú P PRIuLEAST16 uÚ P PRIuLEAST32 wÚ P PRIuLEAST64 rÚ P
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PRIuFAST8 óÚ P PRIuFAST16 ÂÚ P PRIuFAST32 ÄÚ P PRIuFAST64 ¿Ú P PRIuMAX wÚ P PRIuPTR gÚ P PRIx8 &Ú P PRIx16 õÚ P PRIx32 ÷Ú P PRIx64 òÚ P PRIxLEAST8 £Ú P PRIxLEAST16 rÚ P PRIxLEAST32 tÚ P PRIxLEAST64 oÚ P
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PRIxFAST8 ðÚ P PRIxFAST16 ¿Ú P PRIxFAST32 ÁÚ P PRIxFAST64 ¼Ú P PRIxMAX tÚ P PRIxPTR dÚ P PRIX8 FÚ P PRIX16 Ú P PRIX32 Ú P PRIX64 Ú P PRIXLEAST8 ÃÚ P PRIXLEAST16 Ú P PRIXLEAST32 Ú P PRIXLEAST64 Ú P
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PRIXFAST8 Ú P PRIXFAST16 ßÚ P PRIXFAST32 áÚ P PRIXFAST64 ÜÚ P PRIXMAX Ú P PRIXPTR Ú P SCNd8 AÚ P SCNd16 Ú P SCNd32 Ú P SCNd64 Ú P SCNdLEAST8 ¾Ú P SCNdLEAST16 Ú P SCNdLEAST32 Ú P SCNdLEAST64 Ú P
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SCNdFAST8 Ú P SCNdFAST16 ÚÚ P SCNdFAST32 ÜÚ P SCNdFAST64 ×Ú P SCNdMAX Ú P SCNdPTR Ú P SCNi8 <Ú P SCNi16 Ú P SCNi32 Ú P SCNi64 Ú P SCNiLEAST8 ¹Ú P SCNiLEAST16 Ú P SCNiLEAST32 Ú P SCNiLEAST64
Ú P
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SCNiFAST8 Ú P SCNiFAST16 ÕÚ P SCNiFAST32 ×Ú P SCNiFAST64 ÒÚ P SCNiMAX Ú P SCNiPTR zÚ P SCNo8 6Ú P SCNo16 Ú P SCNo32 Ú P SCNo64 Ú P SCNoLEAST8 ³Ú P SCNoLEAST16 Ú P SCNoLEAST32 Ú P SCNoLEAST64 Ú P
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SCNoFAST8 Ú P SCNoFAST16 ÏÚ P SCNoFAST32 ÑÚ P SCNoFAST64 ÌÚ P SCNoMAX Ú P SCNoPTR tÚ P SCNu8 0Ú P SCNu16 ÿÚ P SCNu32 Ú P SCNu64 üÚ P SCNuLEAST8 Ú P SCNuLEAST16 |Ú P SCNuLEAST32 ~Ú P SCNuLEAST64 yÚ P
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SCNuFAST8 úÚ P SCNuFAST16 ÉÚ P SCNuFAST32 ËÚ P SCNuFAST64 ÆÚ P SCNuMAX ~Ú P SCNuPTR nÚ P SCNx8 -Ú P SCNx16 üÚ P SCNx32 þÚ P SCNx64 ùÚ P SCNxLEAST8 ªÚ P SCNxLEAST16 yÚ P SCNxLEAST32 {Ú P SCNxLEAST64 vÚ P
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SCNxFAST8 ÷Ú P SCNxFAST16 ÆÚ P SCNxFAST32 ÈÚ P SCNxFAST64 ÃÚ P SCNxMAX {Ú P SCNxPTR kÚ 8
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imaxdiv_t îÚ &" Jquot Ú &" Jrem Ú
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imaxdiv_t *Ú
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strtoimax ëÚ
|
strtoumax ßÚ
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wcstoimax ÷Ú
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wcstoumax ëÚ imaxabs õÚ imaxdiv èÚ P os_bswap_64 Ú P os_bswap_32 Ú P os_bswap_16 Ú P ntohll .Ú P htonll .Ú P ntohl Ú P htonl Ú P htons Ú P ntohs Ú P htobe16 DÚ P htole16 :Ú P be16toh DÚ P le16toh :Ú P htobe32 FÚ P htole32 <Ú P be32toh FÚ P le32toh <Ú P htobe64 AÚ P htole64 7Ú P be64toh AÚ P le64toh 7Ú , buf Ú
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, x cÚ put_le16 èÚ , buf Ú
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,
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x eÚ put_le24 éÚ , buf Ú
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,
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x eÚ put_le32 êÚ , buf Ú
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,( x CÚ put_le64 åÚ , buf Ú get_le16 Ú , buf Ú get_le24 Ú , buf Ú get_le32 Ú , buf Ú get_le64 þÚ , buf Ú
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, x cÚ put_be16 òÚ , buf Ú
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,
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x eÚ put_be24 óÚ , buf Ú
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,
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x eÚ put_be32 ôÚ , buf Ú
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,( x CÚ put_be64 ïÚ , buf Ú get_be16 Ú , buf Ú get_be24 Ú , buf Ú get_be32 Ú , buf Ú get_be64 Ú , buf Ú , len Ú swap_in_place yÚ , dst Ú , src Ú , len Ú swap_buf Ú P
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_QUEUE_H_ ÏÚ P SLIST_HEAD ·Ú P SLIST_HEAD_INITIALIZER üÚ P SLIST_ENTRY 5Ú P SLIST_EMPTY 8Ú P SLIST_FIRST ?Ú P SLIST_FOREACH ËÚ P SLIST_INIT Ú P SLIST_INSERT_AFTER Ú P SLIST_INSERT_HEAD uÚ P SLIST_NEXT Ú P SLIST_REMOVE ÷Ú P SLIST_REMOVE_HEAD |Ú P STAILQ_HEAD vÚ P STAILQ_HEAD_INITIALIZER »Ú P STAILQ_ENTRY ôÚ P STAILQ_EMPTY ÷Ú P STAILQ_FIRST þÚ P STAILQ_FOREACH Ú P STAILQ_INIT TÚ P STAILQ_INSERT_AFTER ÒÚ P STAILQ_INSERT_HEAD 4Ú P STAILQ_INSERT_TAIL Ú P STAILQ_LAST TÚ P STAILQ_NEXT IÚ P STAILQ_REMOVE ¶Ú P STAILQ_REMOVE_HEAD ;Ú! P STAILQ_REMOVE_HEAD_UNTIL DÚ P STAILQ_REMOVE_AFTER ÙÚ P
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LIST_HEAD Ú P LIST_HEAD_INITIALIZER QÚ P LIST_ENTRY Ú P LIST_EMPTY Ú P LIST_FIRST Ú P LIST_FOREACH Ú P
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LIST_INIT êÚ P LIST_INSERT_AFTER hÚ P LIST_INSERT_BEFORE %Ú P LIST_INSERT_HEAD ÊÚ P
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LIST_NEXT ßÚ P LIST_REMOVE LÚ P TAILQ_HEAD ËÚ P TAILQ_HEAD_INITIALIZER Ú P TAILQ_ENTRY IÚ P TAILQ_EMPTY LÚ P TAILQ_FIRST SÚ P TAILQ_FOREACH ßÚ P TAILQ_FOREACH_REVERSE TÚ P TAILQ_INIT ©Ú P TAILQ_INSERT_AFTER 'Ú P TAILQ_INSERT_BEFORE äÚ P TAILQ_INSERT_HEAD Ú P TAILQ_INSERT_TAIL qÚ P TAILQ_LAST ©Ú P TAILQ_NEXT Ú P TAILQ_PREV Ú P TAILQ_REMOVE Ú P CIRCLEQ_HEAD ?Ú! P CIRCLEQ_HEAD_INITIALIZER Ú P CIRCLEQ_ENTRY ½Ú P CIRCLEQ_EMPTY ÀÚ P CIRCLEQ_FIRST ÇÚ P CIRCLEQ_FOREACH SÚ P CIRCLEQ_FOREACH_REVERSE ÈÚ P CIRCLEQ_INIT Ú P CIRCLEQ_INSERT_AFTER Ú P CIRCLEQ_INSERT_BEFORE XÚ P CIRCLEQ_INSERT_HEAD ýÚ P CIRCLEQ_INSERT_TAIL åÚ P CIRCLEQ_LAST Ú P CIRCLEQ_NEXT Ú P CIRCLEQ_PREV Ú P CIRCLEQ_REMOVE Ú P H_OS_ERROR_ $Ú 8" os_error DÚ " ¤KOS_OK GÚ " ¤K
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OS_ENOMEM Ú " ¤K
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OS_EINVAL Ú " ¤KOS_INVALID_PARM 7Ú " ¤KOS_MEM_NOT_ALIGNED EÚ " ¤K OS_BAD_MUTEX Ú " ¤K OS_TIMEOUT °Ú " ¤KOS_ERR_IN_ISR ¥Ú " ¤K OS_ERR_PRIV LÚ " ¤KOS_NOT_STARTED hÚ " ¤K
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OS_ENOENT Ú " ¤K OS_EBUSY SÚ " ¤K OS_ERROR QÚ os_error_t ¯Ú ," os_error OÚ os_error_to_sys _Ú P _OS_MEMPOOL_H_ 0Ú 8 os_memblock $Ú 8
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<unnamed> QÚ " ·K sle_next GÚ " ¶Kmb_next »Ú 8 os_mempool wÚ
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" ºKmp_block_size IÚ " ºKmp_num_blocks ?Ú " ºK mp_num_free Ú " ºK mp_min_free +Ú " ºK mp_flags rÚ
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" ºKmp_membuf_addr öÚ 8
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<unnamed> QÚ " ÁK
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stqe_next ÂÚ " ºKmp_list ¬Ú 8
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<unnamed> QÚ " ÄK
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slh_first ÌÚ " ºKname Ú P OS_MEMPOOL_F_EXT Ú 8 os_mempool_ext ¿Ú os_mempool_put_fn ºÚ " ÈKmpe_mp Ú " ÈK mpe_put_cb vÚ " ÈK mpe_put_arg ÿÚ! P OS_MEMPOOL_INFO_NAME_LEN 8Ú 8 os_mempool_info bÚ " ÎKomi_block_size ÍÚ " ÎKomi_num_blocks ÅÚ " ÎK omi_num_free ¥Ú " ÎK omi_min_free ±Ú <" ÎK omi_name Ú! os_mempool_info_get_next ¶Ú P OS_MEMPOOL_BLOCK_SZ µÚ os_membuf_t [Ú P OS_MEMPOOL_SIZE ùÚ P OS_MEMPOOL_BYTES «Ú , mp ðÚ , blocks SÚ ,
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block_size ¦Ú , membuf IÚ , name (Ú os_mempool_init }Ú , mpe Ú , blocks SÚ ,
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block_size ¦Ú , membuf IÚ , name (Ú os_mempool_ext_init ÅÚ , mp ðÚ os_mempool_unregister ÝÚ , mp ðÚ os_mempool_clear (Ú , mp ðÚ os_mempool_is_sane IÚ , mp ðÚ , block_addr ¸Ú os_memblock_from *Ú , mp ðÚ os_memblock_get Ú , mp ðÚ , block_addr ¸Ú os_memblock_put_from_cb @Ú , mp ðÚ , block_addr ¸Ú os_memblock_put Ú 8 os_mbuf_pool ©Ú " öKomp_databuf_len HÚ " öK omp_pool Ú 8
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<unnamed> QÚ " ùK
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stqe_next Ú " öK omp_next üÚ 8 os_mbuf_pkthdr ÒÚ " üKomp_len Ú " üK
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omp_flags ¶Ú 8
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<unnamed> QÚ " ÿK
|
stqe_next Ú " üK omp_next öÚ 8 os_mbuf ÌÚ " Lom_data
|
Ú " L om_flags ªÚ " Lom_pkthdr_len Ú " Lom_len sÚ " Lom_omp ZÚ 8
|
<unnamed> QÚ " L sle_next uÚ " Lom_next áÚ <" L om_databuf §Ú 8
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os_mqueue àÚ 8
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<unnamed> QÚ " L stqh_first Ú " L
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stqh_last ýÚ " Lmq_head þÚ " Lmq_ev µÚ P OS_MBUF_F_MASK TÚ P OS_MBUF_IS_PKTHDR WÚ P OS_MBUF_PKTHDR XÚ P OS_MBUF_PKTHDR_TO_MBUF ½Ú P OS_MBUF_PKTLEN WÚ P OS_MBUF_DATA Ú P OS_MBUF_USRHDR MÚ P OS_MBUF_USRHDR_LEN Ú _os_mbuf_leadingspace AÚ ," Lom éÚ " L startoff Ú " L leadingspace Ú P OS_MBUF_LEADINGSPACE ¹Ú _os_mbuf_trailingspace ¹Ú ," Lom äÚ " Lomp Ú P OS_MBUF_TRAILINGSPACE QÚ , mq ïÚ , ev_cb ÈÚ , arg Ú os_mqueue_init æÚ os_mqueue_get \Ú os_mqueue_put CÚ os_msys_register ÷Ú , dsize ´Ú , leadingspace åÚ os_msys_get &Ú os_msys_reset ?Ú , dsize ´Ú , user_hdr_len ËÚ os_msys_get_pkthdr ,Ú os_msys_count 9Ú os_msys_num_free Ú , mp ðÚ os_mbuf_pool_init ¯Ú , omp Ú os_mbuf_get HÚ , omp Ú , pkthdr_len §Ú os_mbuf_get_pkthdr NÚ
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, m bÚ os_mbuf_dup ?Ú , om ñÚ , off Ú , out_off ÑÚ os_mbuf_off MÚ
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, m bÚ , off Ú , len Ú , dst Ú os_mbuf_copydata )Ú , om ñÚ os_mbuf_len IÚ
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, m bÚ os_mbuf_append
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Ú , dst Ú , src Ú , src_off íÚ , len Ú os_mbuf_appendfrom NÚ , mb þÚ os_mbuf_free äÚ , om ñÚ os_mbuf_free_chain vÚ , mp ðÚ , req_len íÚ os_mbuf_adj YÚ , om ñÚ , off Ú , data /Ú , len Ú os_mbuf_cmpf àÚ , om1 ¾Ú , offset1 Ú , om2 ½Ú , offset2 Ú , len Ú os_mbuf_cmpm ÙÚ , om ñÚ , len Ú os_mbuf_prepend Ú , om ñÚ , len Ú os_mbuf_prepend_pullup Ú , om ñÚ , off Ú , src Ú , len Ú os_mbuf_copyinto Ú , first Ú , second IÚ os_mbuf_concat
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Ú , om ñÚ , len Ú os_mbuf_extend úÚ , om ñÚ , len Ú os_mbuf_pullup àÚ , om ñÚ os_mbuf_trim_front 6Ú , om ñÚ , off Ú , len Ú os_mbuf_widen mÚ , m1 /Ú , m2 .Ú os_mbuf_pack_chains Ú P PANCHIP_MEMPOOL__H &Ú panchip_mem_init 4Ú ,
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size Ú , align ÑÚ panchip_mem_get ªÚ P H_BLE_ æÚ P BLE_ADV_INSTANCES Ú P BLE_ENC_BLOCK_SIZE ;Ú P BLE_ACL_MAX_PKT_SIZE tÚ 8 ble_encryption_block VÚ <" Mkey iÚ <" M plain_text lÚ <" M cipher_text Ú 8 ble_mbuf_hdr_rxinfo ÑÚ " Mflags ÙÚ " Mchannel Ú " Mhandle Ú " Mrssi 2Ú " Mphy ¤Ú " M phy_mode Ú' P BLE_MBUF_HDR_F_CONNECT_IND_TXD _Ú' P BLE_MBUF_HDR_F_CONNECT_REQ_TXD RÚ' P BLE_MBUF_HDR_F_CONNECT_RSP_RXD GÚ# P BLE_MBUF_HDR_F_CONN_CREDIT ²Ú P BLE_MBUF_HDR_F_IGNORED úÚ' P BLE_MBUF_HDR_F_CONN_CREDIT_INT `Ú$ P BLE_MBUF_HDR_F_SCAN_REQ_TXD =Ú& P BLE_MBUF_HDR_F_INITA_RESOLVED ¼Ú( P BLE_MBUF_HDR_F_TARGETA_RESOLVED %Ú# P BLE_MBUF_HDR_F_EXT_ADV_SEC Ú P BLE_MBUF_HDR_F_EXT_ADV ×Ú P BLE_MBUF_HDR_F_RESOLVED Ú$ P BLE_MBUF_HDR_F_AUX_PTR_WAIT !Ú# P BLE_MBUF_HDR_F_AUX_INVALID ¦Ú P BLE_MBUF_HDR_F_CRC_OK 3Ú P BLE_MBUF_HDR_F_DEVMATCH ´Ú# P BLE_MBUF_HDR_F_MIC_FAILURE ºÚ$ P BLE_MBUF_HDR_F_SCAN_RSP_TXD 0Ú$ P BLE_MBUF_HDR_F_SCAN_RSP_RXD 2Ú$ P BLE_MBUF_HDR_F_RXSTATE_MASK BÚ 8 ble_mbuf_hdr_txinfo ÏÚ " ¥Mflags ÇÚ " ¥M hdr_byte }Ú " ¥Moffset BÚ " ¥M pyld_len nÚ 8 ble_mbuf_hdr ÔÚ 8
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<unnamed> SÚ " «Mrxinfo Ú " «Mtxinfo Ú
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" ªM beg_cputime 8Ú
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" ªM
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rem_usecs úÚ P BLE_MBUF_HDR_IGNORED £Ú" P BLE_MBUF_HDR_SCAN_REQ_TXD æÚ! P BLE_MBUF_HDR_EXT_ADV_SEC >Ú P BLE_MBUF_HDR_EXT_ADV Ú P BLE_MBUF_HDR_DEVMATCH ]Ú" P BLE_MBUF_HDR_SCAN_RSP_RXD ÛÚ! P BLE_MBUF_HDR_AUX_INVALID OÚ P BLE_MBUF_HDR_WAIT_AUX 'Ú P BLE_MBUF_HDR_CRC_OK ÜÚ! P BLE_MBUF_HDR_MIC_FAILURE cÚ P BLE_MBUF_HDR_RESOLVED EÚ$ P BLE_MBUF_HDR_INITA_RESOLVED eÚ& P BLE_MBUF_HDR_TARGETA_RESOLVED ÎÚ P BLE_MBUF_HDR_RX_STATE Ú P BLE_MBUF_HDR_PTR ½Ú! P BLE_MBUF_PKTHDR_OVERHEAD fÚ# P BLE_MBUF_MEMBLOCK_OVERHEAD åÚ P BLE_MBUF_HS_HDR_LEN ÔÚ P BLE_DEV_ADDR_LEN âÚ < g_dev_addr ´Ú < g_random_addr lÚ 8" ble_error_codes xÚ " ÅMBLE_ERR_SUCCESS Ú" " ÅMBLE_ERR_UNKNOWN_HCI_CMD Ú " ÅMBLE_ERR_UNK_CONN_ID ÂÚ " ÅMBLE_ERR_HW_FAIL Ú " ÅMBLE_ERR_PAGE_TMO ÃÚ " ÅMBLE_ERR_AUTH_FAIL Ú! " ÅMBLE_ERR_PINKEY_MISSING ÚÚ " ÅMBLE_ERR_MEM_CAPACITY Ú " ÅMBLE_ERR_CONN_SPVN_TMO Ú " ÅMBLE_ERR_CONN_LIMIT Ú# " ÅMBLE_ERR_SYNCH_CONN_LIMIT /Ú" " ÅMBLE_ERR_ACL_CONN_EXISTS
Ú! " ÅMBLE_ERR_CMD_DISALLOWED Ú% " ÅMBLE_ERR_CONN_REJ_RESOURCES Ú$ " ÅMBLE_ERR_CONN_REJ_SECURITY ØÚ# " ÅMBLE_ERR_CONN_REJ_BD_ADDR RÚ" " ÅMBLE_ERR_CONN_ACCEPT_TMO Ú " ÅMBLE_ERR_UNSUPPORTED ÀÚ$ " ÅMBLE_ERR_INV_HCI_CMD_PARMS èÚ% " ÅMBLE_ERR_REM_USER_CONN_TERM uÚ& " ÅM BLE_ERR_RD_CONN_TERM_RESRCS .Ú& " ÅM BLE_ERR_RD_CONN_TERM_PWROFF ,Ú" " ÅMBLE_ERR_CONN_TERM_LOCAL Ú$ " ÅMBLE_ERR_REPEATED_ATTEMPTS Ú " ÅMBLE_ERR_NO_PAIRING %Ú " ÅMBLE_ERR_UNK_LMP ûÚ% " ÅMBLE_ERR_UNSUPP_REM_FEATURE Ú " ÅMBLE_ERR_SCO_OFFSET Ú " ÅMBLE_ERR_SCO_ITVL ¬Ú " ÅMBLE_ERR_SCO_AIR_MODE Ú" " ÅMBLE_ERR_INV_LMP_LL_PARM fÚ " ÅMBLE_ERR_UNSPECIFIED úÚ% " ÅMBLE_ERR_UNSUPP_LMP_LL_PARM bÚ! " ÅMBLE_ERR_NO_ROLE_CHANGE ðÚ! " ÅMBLE_ERR_LMP_LL_RSP_TMO Ú " ÅMBLE_ERR_LMP_COLLISION 1Ú " ÅMBLE_ERR_LMP_PDU Ú" " ÅMBLE_ERR_ENCRYPTION_MODE Ú" " ÅMBLE_ERR_LINK_KEY_CHANGE ¦Ú " ÅMBLE_ERR_UNSUPP_QOS îÚ! " ÅMBLE_ERR_INSTANT_PASSED ãÚ# " ÅMBLE_ERR_UNIT_KEY_PAIRING .Ú" " ÅMBLE_ERR_DIFF_TRANS_COLL Ú " ÅMBLE_ERR_QOS_PARM Ú " ÅMBLE_ERR_QOS_REJECTED Ú " ÅMBLE_ERR_CHAN_CLASS <Ú# " ÅMBLE_ERR_INSUFFICIENT_SEC ^Ú$ " ÅMBLE_ERR_PARM_OUT_OF_RANGE ÖÚ" " ÅMBLE_ERR_PENDING_ROLE_SW Ú " ÅMBLE_ERR_RESERVED_SLOT $Ú " ÅMBLE_ERR_ROLE_SW_FAIL qÚ" " ÅMBLE_ERR_INQ_RSP_TOO_BIG cÚ" " ÅMBLE_ERR_SEC_SIMPLE_PAIR Ú! " ÅMBLE_ERR_HOST_BUSY_PAIR ¸Ú# " ÅMBLE_ERR_CONN_REJ_CHANNEL YÚ " ÅMBLE_ERR_CTLR_BUSY VÚ " ÅMBLE_ERR_CONN_PARMS Ú " ÅMBLE_ERR_DIR_ADV_TMO ÁÚ " ÅMBLE_ERR_CONN_TERM_MIC (Ú% " ÅMBLE_ERR_CONN_ESTABLISHMENT »Ú " ÅMBLE_ERR_MAC_CONN_FAIL LÚ! " ÅMBLE_ERR_COARSE_CLK_ADJ ÿÚ$ " ÅMBLE_ERR_TYPE0_SUBMAP_NDEF Ú! " ÅMBLE_ERR_UNK_ADV_INDENT ÚÚ " ÅMBLE_ERR_LIMIT_REACHED [Ú& " ÅM BLE_ERR_OPERATION_CANCELLED Ú" " ÅMBLE_ERR_PACKET_TOO_LONG Ú " ÅM BLE_ERR_MAX SÚ P BLE_HW_ERR_DO_NOT_USE úÚ! P BLE_HW_ERR_HCI_SYNC_LOSS Ú P BLE_OWN_ADDR_PUBLIC çÚ P BLE_OWN_ADDR_RANDOM åÚ( P BLE_OWN_ADDR_RPA_PUBLIC_DEFAULT )Ú( P BLE_OWN_ADDR_RPA_RANDOM_DEFAULT 'Ú P BLE_ADDR_PUBLIC BÚ P BLE_ADDR_RANDOM @Ú P BLE_ADDR_PUBLIC_ID PÚ P BLE_ADDR_RANDOM_ID NÚ P BLE_ADDR_ANY Ú P BLE_ADDR_IS_RPA #Ú P BLE_ADDR_IS_NRPA ÓÚ P BLE_ADDR_IS_STATIC 8Ú 8
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<unnamed> QÚ " Ntype Ú <" Nval fÚ ble_addr_t íÚ ble_addr_cmp Ú ," Na bÚ ," Nb aÚ " N
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type_diff -Ú P H_BLE_HCI_COMMON_ uÚ P H_NIMBLE_TRANSPORT_ ¼Ú! P H_NIMBLE_TRANSPORT_IMPL_ !Ú hs_thread_init Ú ble_transport_hs_init òÚ ll_init ïÚ , buf Ú% ble_transport_to_ll_cmd_impl Ú , om ñÚ% ble_transport_to_ll_acl_impl Ú , buf Ú% ble_transport_to_hs_evt_impl öÚ , om ñÚ% ble_transport_to_hs_acl_impl Ú P H_BLE_MONITOR_ OÚ P BLE_MONITOR [Ú ble_monitor_log Ú ," °Nlevel Ú ," °Nfmt dÚ ble_transport_to_ll_cmd ;Ú ," ³Nbuf kÚ ble_transport_to_ll_acl ?Ú ," µNom ÌÚ ble_transport_to_hs_evt Ú ," ·Nbuf gÚ ble_transport_to_hs_acl <Ú ," ¹Nom ÈÚ ble_transport_alloc_cmd >Ú , discardable ]Ú ble_transport_alloc_evt #Ú( ble_transport_alloc_acl_from_hs åÚ( ble_transport_alloc_acl_from_ll èÚ , buf Ú ble_transport_free DÚ , cb Ú2 *ble_transport_register_put_acl_from_ll_cb Ú , buf Ú , om ñÚ , buf Ú , om ñÚ ble_transport_init 2Ú P BLE_HCI_MAX_DATA_LEN ¡Ú 8 ble_hci_cmd VÚ " ÊNopcode )Ú " ÊNlength *Ú <" ÊNdata áÚ 8 ble_hci_ev ±Ú " ÎNopcode .Ú " ÎNlength &Ú <" ÎNdata ÝÚ P BLE_HCI_OPCODE_NOP <Ú P BLE_HCI_OP ³Ú P BLE_HCI_OGF tÚ P BLE_HCI_OCF xÚ P BLE_HCI_OGF_LINK_CTRL ?Ú P BLE_HCI_OGF_LINK_POLICY Ú" P BLE_HCI_OGF_CTLR_BASEBAND 5Ú P BLE_HCI_OGF_INFO_PARAMS ®Ú" P BLE_HCI_OGF_STATUS_PARAMS òÚ P BLE_HCI_OGF_TESTING çÚ P BLE_HCI_OGF_LE ~Ú P BLE_HCI_OGF_VENDOR 9Ú P BLE_HCI_NUM_LE_CMDS ÚÚ# P BLE_HCI_OCF_DISCONNECT_CMD ÞÚ! 8 ble_hci_lc_disconnect_cp æÚ " àN conn_handle
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Ú " àNreason Ú$ P BLE_HCI_OCF_RD_REM_VER_INFO IÚ# 8 ble_hci_rd_rem_ver_info_cp
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Ú " äN conn_handle Ú& P BLE_HCI_OCF_CB_SET_EVENT_MASK ¹Ú% 8 ble_hci_cb_set_event_mask_cp :Ú (" çN event_mask 1Ú P BLE_HCI_OCF_CB_RESET Ú# P BLE_HCI_OCF_CB_READ_TX_PWR Ú" 8 ble_hci_cb_read_tx_pwr_cp yÚ " ëN conn_handle ÿÚ " ëNtype ÍÚ" 8 ble_hci_cb_read_tx_pwr_rp jÚ " îN conn_handle üÚ " îN tx_level #Ú+ P #BLE_HCI_OCF_CB_SET_CTLR_TO_HOST_FC Ú& 8 ble_hci_cb_ctlr_to_host_fc_cp ÔÚ " òNenable Ú% P BLE_HCI_OCF_CB_HOST_BUF_SIZE ÿÚ$ 8 ble_hci_cb_host_buf_size_cp Ú " õN acl_data_len ¥Ú " õN sco_data_len Ú " õNacl_num Ú " õNsco_num Ú* P "BLE_HCI_OCF_CB_HOST_NUM_COMP_PKTS MÚ, 8 $ble_hci_cb_host_num_comp_pkts_entry Ú " ûNhandle Ú " ûNcount KÚ) 8 !ble_hci_cb_host_num_comp_pkts_cp nÚ " þNhandles Ú <" þNh åÚ' P BLE_HCI_OCF_CB_SET_EVENT_MASK2
Ú& 8 ble_hci_cb_set_event_mask2_cp Ú (" O event_mask2 aÚ( P BLE_HCI_OCF_CB_RD_AUTH_PYLD_TMO ÿÚ' 8 ble_hci_cb_rd_auth_pyld_tmo_cp `Ú "
O conn_handle dÚ' 8 ble_hci_cb_rd_auth_pyld_tmo_rp QÚ " O conn_handle bÚ " Otmo Ú( P BLE_HCI_OCF_CB_WR_AUTH_PYLD_TMO ìÚ' 8 ble_hci_cb_wr_auth_pyld_tmo_cp MÚ " O conn_handle ^Ú " Otmo Ú' 8 ble_hci_cb_wr_auth_pyld_tmo_rp >Ú " O conn_handle [Ú$ P BLE_HCI_OCF_IP_RD_LOCAL_VER UÚ# 8 ble_hci_ip_rd_local_ver_rp Ú " Ohci_ver Ú " Ohci_rev ùÚ " Olmp_ver íÚ " O manufacturer ÂÚ " O lmp_subver Ú' P BLE_HCI_OCF_IP_RD_LOC_SUPP_CMD NÚ& 8 ble_hci_ip_rd_loc_supp_cmd_rp ÀÚ <" @O commands Ú( P BLE_HCI_OCF_IP_RD_LOC_SUPP_FEAT Ú' 8 ble_hci_ip_rd_loc_supp_feat_rp RÚ (" O features NÚ# P BLE_HCI_OCF_IP_RD_BUF_SIZE Ú" 8 ble_hci_ip_rd_buf_size_rp iÚ " O acl_data_len ûÚ " O sco_data_len ïÚ " Oacl_num íÚ " Osco_num ØÚ" P BLE_HCI_OCF_IP_RD_BD_ADDR Ú! 8 ble_hci_ip_rd_bd_addr_rp Ú <" ¤Oaddr ÿÚ P BLE_HCI_OCF_RD_RSSI ÓÚ 8 ble_hci_rd_rssi_cp TÚ " §Ohandle YÚ 8 ble_hci_rd_rssi_rp EÚ " ©Ohandle WÚ " ©Orssi Ú& P BLE_HCI_OCF_LE_SET_EVENT_MASK Ú% 8 ble_hci_le_set_event_mask_cp .Ú (" O event_mask jÚ# P BLE_HCI_OCF_LE_RD_BUF_SIZE Ú" 8 ble_hci_le_rd_buf_size_rp qÚ " °O data_len Ú " °O data_packets ÕÚ& P BLE_HCI_OCF_LE_RD_BUF_SIZE_V2 ²Ú% 8 ble_hci_le_rd_buf_size_v2_rp dÚ " ´O data_len |Ú " ´O data_packets ÑÚ " ´O iso_data_len ÊÚ " ´Oiso_data_packets Ú( P BLE_HCI_OCF_LE_RD_LOC_SUPP_FEAT Ú' 8 ble_hci_le_rd_loc_supp_feat_rp ZÚ (" ºO features /Ú% P BLE_HCI_OCF_LE_SET_RAND_ADDR Ú$ 8 ble_hci_le_set_rand_addr_cp ¾Ú <" ½Oaddr æÚ& P BLE_HCI_OCF_LE_SET_ADV_PARAMS ¼Ú% 8 ble_hci_le_set_adv_params_cp =Ú " ÀO min_interval Ú " ÀO max_interval Ú " ÀOtype ÷Ú " ÀOown_addr_type 8Ú " ÀOpeer_addr_type ÞÚ <" ÀO
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peer_addr ÎÚ " ÀO chan_map zÚ " ÀOfilter_policy 2Ú) P !BLE_HCI_OCF_LE_RD_ADV_CHAN_TXPWR ²Ú( 8 ble_hci_le_rd_adv_chan_txpwr_rp äÚ " ÊO power_level ÿÚ$ P BLE_HCI_OCF_LE_SET_ADV_DATA jÚ! P BLE_HCI_MAX_ADV_DATA_LEN _Ú# 8 ble_hci_le_set_adv_data_cp +Ú " ÎO adv_data_len ÉÚ <" ÎO adv_data Ú) P !BLE_HCI_OCF_LE_SET_SCAN_RSP_DATA ÂÚ& P BLE_HCI_MAX_SCAN_RSP_DATA_LEN ·Ú( 8 ble_hci_le_set_scan_rsp_data_cp Ú " ÓO scan_rsp_len Ú <" ÓO scan_rsp ñÚ& P BLE_HCI_OCF_LE_SET_ADV_ENABLE ÙÚ% 8 ble_hci_le_set_adv_enable_cp ZÚ " ×Oenable 7Ú' P BLE_HCI_OCF_LE_SET_SCAN_PARAMS pÚ& 8 ble_hci_le_set_scan_params_cp ÑÚ " ÚO
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scan_type ÏÚ " ÚO
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scan_itvl ÉÚ " ÚO scan_window ìÚ " ÚOown_addr_type Ú " ÚOfilter_policy Ú' P BLE_HCI_OCF_LE_SET_SCAN_ENABLE Ú& 8 ble_hci_le_set_scan_enable_cp îÚ " áOenable -Ú " áOfilter_duplicates kÚ# P BLE_HCI_OCF_LE_CREATE_CONN ÊÚ" 8 ble_hci_le_create_conn_cp Ú " åO
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scan_itvl ¾Ú " åO scan_window áÚ " åOfilter_policy Ú " åOpeer_addr_type ¹Ú <" åO
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peer_addr ©Ú " åOown_addr_type Ú " åOmin_conn_itvl
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Ú " åOmax_conn_itvl Ú " åO conn_latency ~Ú " åOtmo =Ú " åOmin_ce Ú " åOmax_ce Ú* P "BLE_HCI_OCF_LE_CREATE_CONN_CANCEL ·Ú* P "BLE_HCI_OCF_LE_RD_WHITE_LIST_SIZE RÚ$ 8 ble_hci_le_rd_white_list_rp Ú " ôOsize ÊÚ( P BLE_HCI_OCF_LE_CLEAR_WHITE_LIST Ú& P BLE_HCI_OCF_LE_ADD_WHITE_LIST ÁÚ$ 8 ble_hci_le_add_whte_list_cp Ú " øO
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addr_type »Ú <" øOaddr «Ú& P BLE_HCI_OCF_LE_RMV_WHITE_LIST Ú% 8 ble_hci_le_rmv_white_list_cp Ú " üO
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addr_type ·Ú <" üOaddr §Ú# P BLE_HCI_OCF_LE_CONN_UPDATE »Ú" 8 ble_hci_le_conn_update_cp |Ú " P conn_handle hÚ " Pconn_itvl_min nÚ " Pconn_itvl_max lÚ " P conn_latency âÚ " Psupervision_timeout ¤Ú " P min_ce_len ÚÚ " P max_ce_len ØÚ+ P #BLE_HCI_OCF_LE_SET_HOST_CHAN_CLASS $Ú* 8 "ble_hci_le_set_host_chan_class_cp %Ú <" P chan_map vÚ# P BLE_HCI_OCF_LE_RD_CHAN_MAP ¿Ú" 8 ble_hci_le_rd_chan_map_cp Ú " P conn_handle \Ú" 8 ble_hci_le_rd_chan_map_rp Ú " P conn_handle ZÚ <" P chan_map qÚ# P BLE_HCI_OCF_LE_RD_REM_FEAT ³Ú" 8 ble_hci_le_rd_rem_feat_cp Ú " P conn_handle VÚ P BLE_HCI_OCF_LE_ENCRYPT îÚ 8 ble_hci_le_encrypt_cp Ú <" Pkey WÚ <" Pdata Ú 8 ble_hci_le_encrypt_rp Ú <" Pdata Ú P BLE_HCI_OCF_LE_RAND ôÚ 8 ble_hci_le_rand_rp fÚ (" Prandom_number 9Ú% P BLE_HCI_OCF_LE_START_ENCRYPT õÚ$ 8 ble_hci_le_start_encrypt_cp vÚ " P conn_handle JÚ (" Prand Ú " Pdiv Ú <" Pltk LÚ( P BLE_HCI_OCF_LE_LT_KEY_REQ_REPLY çÚ' 8 ble_hci_le_lt_key_req_reply_cp HÚ " ¤P conn_handle DÚ <" ¤Pltk FÚ' 8 ble_hci_le_lt_key_req_reply_rp 9Ú " §P conn_handle AÚ, P $BLE_HCI_OCF_LE_LT_KEY_REQ_NEG_REPLY ¦Ú+ 8 #ble_hci_le_lt_key_req_neg_reply_cp §Ú " ªP conn_handle >Ú+ 8 #ble_hci_le_lt_key_req_neg_reply_rp Ú " ¬P conn_handle <Ú& P BLE_HCI_OCF_LE_RD_SUPP_STATES Ú% 8 ble_hci_le_rd_supp_states_rp Ú (" ¯Pstates Ú P BLE_HCI_OCF_LE_RX_TEST ÊÚ 8 ble_hci_le_rx_test_cp Ú " ²Prx_chan ÝÚ P BLE_HCI_OCF_LE_TX_TEST ÈÚ 8 ble_hci_le_tx_test_cp Ú " µPtx_chan ØÚ " µPtest_data_len ZÚ " µPpayload ÓÚ P BLE_HCI_OCF_LE_TEST_END Ú 8 ble_hci_le_test_end_rp Ú " ºP num_packets Ú) P !BLE_HCI_OCF_LE_REM_CONN_PARAM_RR »Ú( 8 ble_hci_le_rem_conn_param_rr_cp üÚ " ½P conn_handle +Ú " ½Pconn_itvl_min 1Ú " ½Pconn_itvl_max /Ú " ½P conn_latency ¥Ú " ½Psupervision_timeout gÚ " ½Pmin_ce CÚ " ½Pmax_ce AÚ( 8 ble_hci_le_rem_conn_param_rr_rp íÚ " ÅP conn_handle #Ú* P "BLE_HCI_OCF_LE_REM_CONN_PARAM_NRR kÚ* 8 "ble_hci_le_rem_conn_params_nrr_cp Ú " ÈP conn_handle Ú " ÈPreason $Ú* 8 "ble_hci_le_rem_conn_params_nrr_rp Ú " ËP conn_handle Ú$ P BLE_HCI_OCF_LE_SET_DATA_LEN fÚ# 8 ble_hci_le_set_data_len_cp 'Ú " ÎP conn_handle Ú " ÎP
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tx_octets ºÚ " ÎPtx_time ¡Ú# 8 ble_hci_le_set_data_len_rp Ú " ÒP conn_handle Ú, P $BLE_HCI_OCF_LE_RD_SUGG_DEF_DATA_LEN éÚ+ 8 #ble_hci_le_rd_sugg_def_data_len_rp ÛÚ " ÕPmax_tx_octets Ú " ÕP max_tx_time íÚ, P $BLE_HCI_OCF_LE_WR_SUGG_DEF_DATA_LEN ÖÚ+ 8 #ble_hci_le_wr_sugg_def_data_len_cp ×Ú " ÙPmax_tx_octets Ú " ÙP max_tx_time éÚ& P BLE_HCI_OCF_LE_RD_P256_PUBKEY ôÚ! P BLE_HCI_OCF_LE_GEN_DHKEY aÚ 8 ble_hci_le_gen_dhkey_cp bÚ <" @ÞPpkey lÚ' P BLE_HCI_OCF_LE_ADD_RESOLV_LIST eÚ& 8 ble_hci_le_add_resolv_list_cp ÆÚ " áPpeer_addr_type ¼Ú <" áP peer_id_addr zÚ <" áP peer_irk ùÚ <" áP
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local_irk Ú' P BLE_HCI_OCF_LE_RMV_RESOLV_LIST 9Ú' 8 ble_hci_le_rmv_resolve_list_cp 3Ú " çPpeer_addr_type ¶Ú <" çP peer_id_addr tÚ' P BLE_HCI_OCF_LE_CLR_RESOLV_LIST MÚ+ P #BLE_HCI_OCF_LE_RD_RESOLV_LIST_SIZE öÚ* 8 "ble_hci_le_rd_resolv_list_size_rp èÚ " ìPsize ÑÚ+ P #BLE_HCI_OCF_LE_RD_PEER_RESOLV_ADDR &Ú* 8 "ble_hci_le_rd_peer_resolv_addr_cp 'Ú " ïPpeer_addr_type ®Ú <" ïP peer_id_addr lÚ* 8 "ble_hci_le_rd_peer_resolv_addr_rp Ú <" òPrpa
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Ú, P $BLE_HCI_OCF_LE_RD_LOCAL_RESOLV_ADDR åÚ+ 8 #ble_hci_le_rd_local_resolv_addr_cp ÆÚ " õPpeer_addr_type ¨Ú <" õP peer_id_addr fÚ+ 8 #ble_hci_le_rd_local_resolv_addr_rp ·Ú <" øPrpa Ú' P BLE_HCI_OCF_LE_SET_ADDR_RES_EN bÚ& 8 ble_hci_le_set_addr_res_en_cp ãÚ " ûPenable Ú# P BLE_HCI_OCF_LE_SET_RPA_TMO Ú" 8 ble_hci_le_set_rpa_tmo_cp oÚ " þP rpa_timeout ºÚ' P BLE_HCI_OCF_LE_RD_MAX_DATA_LEN qÚ& 8 ble_hci_le_rd_max_data_len_rp ãÚ " Qmax_tx_octests äÚ " Q max_tx_time @Ú " Qmax_rx_octests æÚ " Q max_rx_time BÚ P BLE_HCI_OCF_LE_RD_PHY /Ú 8 ble_hci_le_rd_phy_cp Ú " Q conn_handle `Ú 8 ble_hci_le_rd_phy_rp Ú " Q conn_handle ^Ú " Qtx_phy NÚ " Qrx_phy PÚ' P BLE_HCI_OCF_LE_SET_DEFAULT_PHY cÚ& 8 ble_hci_le_set_default_phy_cp ÄÚ " Q all_phys
Ú " Qtx_phys ÔÚ " Qrx_phys ÖÚ P BLE_HCI_OCF_LE_SET_PHY ×Ú 8 ble_hci_le_set_phy_cp Ú " Q conn_handle TÚ " Q all_phys Ú " Qtx_phys ÏÚ " Qrx_phys ÑÚ " Q phy_options Ú" P BLE_HCI_OCF_LE_RX_TEST_V2 ÝÚ! 8 ble_hci_le_rx_test_v2_cp þÚ " Qrx_chan ôÚ " Qphy Ú " Qindex ÃÚ" P BLE_HCI_OCF_LE_TX_TEST_V2 ÛÚ! 8 ble_hci_le_tx_test_v2_cp üÚ " Qtx_chan íÚ " Qtest_data_len oÚ " Qpayload èÚ " Qphy Ú, P $BLE_HCI_OCF_LE_SET_ADV_SET_RND_ADDR ËÚ+ 8 #ble_hci_le_set_adv_set_rnd_addr_cp ÌÚ " ¥Q adv_handle ÀÚ <" ¥Qaddr üÚ) P !BLE_HCI_OCF_LE_SET_EXT_ADV_PARAM ¹Ú) 8 !ble_hci_le_set_ext_adv_params_cp
Ú " ©Q adv_handle ¼Ú " ©Qprops Ú <" ©Q pri_itvl_min zÚ <" ©Q pri_itvl_max xÚ " ©Q pri_chan_map ÝÚ " ©Qown_addr_type MÚ " ©Qpeer_addr_type óÚ <" ©Q
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peer_addr ãÚ " ©Qfilter_policy GÚ " ©Q tx_power PÚ " ©Qpri_phy ÍÚ " ©Q sec_max_skip ÈÚ " ©Qsec_phy ÝÚ " ©Qsid Ú " ©Qscan_req_notif ïÚ) 8 !ble_hci_le_set_ext_adv_params_rp vÚ " ¹Q tx_power @Ú( P BLE_HCI_OCF_LE_SET_EXT_ADV_DATA Ú' 8 ble_hci_le_set_ext_adv_data_cp sÚ " ¼Q adv_handle ©Ú " ¼Q
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operation àÚ " ¼Qfragment_pref IÚ " ¼Q adv_data_len ÙÚ <" ¼Q adv_data JÚ- P %BLE_HCI_OCF_LE_SET_EXT_SCAN_RSP_DATA jÚ, 8 $ble_hci_le_set_ext_scan_rsp_data_cp KÚ " ÃQ adv_handle ¢Ú " ÃQ
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operation ÙÚ " ÃQfragment_pref BÚ " ÃQ scan_rsp_len Ú <" ÃQ scan_rsp Ú* P "BLE_HCI_OCF_LE_SET_EXT_ADV_ENABLE Ú 8 adv_set ÑÚ " ÊQ adv_handle Ú " ÊQ duration 6Ú " ÊQ max_events gÚ) 8 !ble_hci_le_set_ext_adv_enable_cp ¢Ú " ÎQenable >Ú " ÎQ num_sets 3Ú <" ÎQsets µÚ+ P #BLE_HCI_OCF_LE_RD_MAX_ADV_DATA_LEN /Ú* 8 "ble_hci_le_rd_max_adv_data_len_rp AÚ " ÓQmax_adv_data_len Ú* P "BLE_HCI_OCF_LE_RD_NUM_OF_ADV_SETS LÚ) 8 !ble_hci_le_rd_num_of_adv_sets_rp ~Ú " ÖQ num_sets +Ú& P BLE_HCI_OCF_LE_REMOVE_ADV_SET ²Ú% 8 ble_hci_le_remove_adv_set_cp 3Ú " ÙQ adv_handle Ú& P BLE_HCI_OCF_LE_CLEAR_ADV_SETS ÆÚ/ P 'BLE_HCI_OCF_LE_SET_PERIODIC_ADV_PARAMS üÚ. 8 &ble_hci_le_set_periodic_adv_params_cp }Ú " ÝQ adv_handle Ú " ÝQ min_itvl 'Ú " ÝQ max_itvl %Ú " ÝQprops [Ú- P %BLE_HCI_OCF_LE_SET_PERIODIC_ADV_DATA ªÚ, 8 $ble_hci_le_set_periodic_adv_data_cp kÚ " ãQ adv_handle Ú " ãQ
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operation ¹Ú " ãQ adv_data_len ²Ú <" ãQ adv_data #Ú/ P 'BLE_HCI_OCF_LE_SET_PERIODIC_ADV_ENABLE Ú. 8 &ble_hci_le_set_periodic_adv_enable_cp Ú " éQenable #Ú " éQ adv_handle |Ú* P "BLE_HCI_OCF_LE_SET_EXT_SCAN_PARAM mÚ 8 scan_params 'Ú " íQtype ÈÚ " íQitvl ÂÚ " íQwindow åÚ* 8 "ble_hci_le_set_ext_scan_params_cp Ú " ñQown_addr_type Ú " ñQfilter_policy ÿÚ " ñQphys ÂÚ <" ñQscans 7Ú+ P #BLE_HCI_OCF_LE_SET_EXT_SCAN_ENABLE 5Ú* 8 "ble_hci_le_set_ext_scan_enable_cp 6Ú " ÷Qenable Ú " ÷Q filter_dup FÚ " ÷Q duration Ú " ÷Qperiod ðÚ' P BLE_HCI_OCF_LE_EXT_CREATE_CONN rÚ 8 conn_params Ú " ýQ
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scan_itvl ¤Ú " ýQ scan_window ÇÚ " ýQconn_min_itvl ðÚ " ýQconn_max_itvl îÚ " ýQ conn_latency dÚ " ýQsupervision_timeout &Ú " ýQmin_ce Ú " ýQmax_ce Ú& 8 ble_hci_le_ext_create_conn_cp ÓÚ " Rfilter_policy iÚ " Rown_addr_type oÚ " Rpeer_addr_type Ú <" R
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peer_addr Ú " Rinit_phy_mask oÚ <" R conn_params Ú7 P /BLE_HCI_LE_PERIODIC_ADV_CREATE_SYNC_OPT_FILTER kÚ9 P 1BLE_HCI_LE_PERIODIC_ADV_CREATE_SYNC_OPT_DISABLED õÚ; P 3BLE_HCI_LE_PERIODIC_ADV_CREATE_SYNC_OPT_DUPLICATES ;Ú0 P (BLE_HCI_OCF_LE_PERIODIC_ADV_CREATE_SYNC ¹Ú/ 8 'ble_hci_le_periodic_adv_create_sync_cp Ú " Roptions ÓÚ " Rsid §Ú " Rpeer_addr_type
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Ú <" R
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peer_addr úÚ " Rskip %Ú " R sync_timeout ©Ú " Rsync_cte_type ZÚ7 P /BLE_HCI_OCF_LE_PERIODIC_ADV_CREATE_SYNC_CANCEL ¦Ú. P &BLE_HCI_OCF_LE_PERIODIC_ADV_TERM_SYNC 9Ú- 8 %ble_hci_le_periodic_adv_term_sync_cp ÚÚ " R sync_handle <Ú4 P ,BLE_HCI_OCF_LE_ADD_DEV_TO_PERIODIC_ADV_LIST ]Ú3 8 +ble_hci_le_add_dev_to_periodic_adv_list_cp ~Ú " Rpeer_addr_type ýÚ <" R
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peer_addr íÚ " Rsid Ú6 P .BLE_HCI_OCF_LE_REM_DEV_FROM_PERIODIC_ADV_LIST Ú5 8 -ble_hci_le_rem_dev_from_periodic_adv_list_cp Ú " £Rpeer_addr_type øÚ <" £R
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peer_addr èÚ " £Rsid Ú/ P 'BLE_HCI_OCF_LE_CLEAR_PERIODIC_ADV_LIST Ú1 P )BLE_HCI_OCF_LE_RD_PERIODIC_ADV_LIST_SIZE <Ú0 8 (ble_hci_le_rd_periodic_adv_list_size_rp Ú " ©R
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list_size íÚ) P !BLE_HCI_OCF_LE_RD_TRANSMIT_POWER ¬Ú( 8 ble_hci_le_rd_transmit_power_rp ¾Ú " ¬R min_tx_power ¡Ú " ¬R max_tx_power Ú/ P 'BLE_HCI_OCF_LE_RD_RF_PATH_COMPENSATION ëÚ. 8 &ble_hci_le_rd_rf_path_compensation_rp ]Ú " °Rtx_path_compensation 8Ú " °Rrx_path_compensation :Ú/ P 'BLE_HCI_OCF_LE_WR_RF_PATH_COMPENSATION ØÚ. 8 &ble_hci_le_wr_rf_path_compensation_cp YÚ " ´Rtx_path_compensation 4Ú " ´Rrx_path_compensation 6Ú( P BLE_HCI_OCF_LE_SET_PRIVACY_MODE Ú' 8 ble_hci_le_set_privacy_mode_cp UÚ " ¸Rpeer_id_addr_type ±Ú <" ¸R peer_id_addr ¡Ú " ¸Rmode Ú" P BLE_HCI_OCF_LE_RX_TEST_V3 ÜÚ" P BLE_HCI_OCF_LE_TX_TEST_V3 ÚÚ2 P *BLE_HCI_OCF_LE_SET_CONNLESS_CTE_TX_PARAMS ÔÚ2 P *BLE_HCI_OCF_LE_SET_CONNLESS_CTE_TX_ENABLE ñÚ7 P /BLE_HCI_OCF_LE_SET_CONNLESS_IQ_SAMPLING_ENABLE zÚ. P &BLE_HCI_OCF_LE_SET_CONN_CTE_RX_PARAMS Ú. P &BLE_HCI_OCF_LE_SET_CONN_CTE_TX_PARAMS Ú/ P 'BLE_HCI_OCF_LE_SET_CONN_CTE_REQ_ENABLE òÚ0 P (BLE_HCI_OCF_LE_SET_CONN_CTE_RESP_ENABLE Ú' P BLE_HCI_OCF_LE_RD_ANTENNA_INFO ~Ú3 P +BLE_HCI_OCF_LE_PERIODIC_ADV_RECEIVE_ENABLE úÚ2 8 *ble_hci_le_periodic_adv_receive_enable_cp ûÚ " ÇR sync_handle Ú " ÇRenable DÚ2 P *BLE_HCI_OCF_LE_PERIODIC_ADV_SYNC_TRANSFER Ú1 8 )ble_hci_le_periodic_adv_sync_transfer_cp %Ú " ËR conn_handle Ú " ËR service_data ¨Ú " ËR sync_handle Ú1 8 )ble_hci_le_periodic_adv_sync_transfer_rp Ú " ÏR conn_handle Ú6 P .BLE_HCI_OCF_LE_PERIODIC_ADV_SET_INFO_TRANSFER ÂÚ5 8 -ble_hci_le_periodic_adv_set_info_transfer_cp Ú " ÒR conn_handle Ú " ÒR service_data ¡Ú " ÒR adv_handle Ú5 8 -ble_hci_le_periodic_adv_set_info_transfer_rp tÚ " ÖR conn_handle Ú9 P 1BLE_HCI_OCF_LE_PERIODIC_ADV_SYNC_TRANSFER_PARAMS ÓÚ8 8 0ble_hci_le_periodic_adv_sync_transfer_params_cp 4Ú " ÙR conn_handle Ú " ÙRmode øÚ " ÙRskip ÝÚ " ÙR sync_timeout aÚ " ÙRsync_cte_type Ú8 8 0ble_hci_le_periodic_adv_sync_transfer_params_rp %Ú " ßR conn_handle Ú8 P 0BLE_HCI_OCF_LE_SET_DEFAULT_SYNC_TRANSFER_PARAMS Ú@ 8 8ble_hci_le_set_default_periodic_sync_transfer_params_cp ÏÚ " âRmode ïÚ " âRskip ÔÚ " âR sync_timeout XÚ " âRsync_cte_type Ú) P !BLE_HCI_OCF_LE_GENERATE_DHKEY_V2 ùÚ" P BLE_HCI_OCF_LE_MODIFY_SCA Ú$ P BLE_HCI_OCF_LE_REQ_PEER_SCA `Ú' 8 ble_hci_le_request_peer_sca_cp XÚ " êR conn_handle üÚ% P BLE_HCI_OCF_LE_SET_HOST_FEAT ÿÚ$ 8 ble_hci_le_set_host_feat_cp Ú " íRbit_num Ú " íRval HÚ+ P #BLE_HCI_OCF_LE_SET_DEFAULT_SUBRATE 6Ú* 8 "ble_hci_le_set_default_subrate_cp Ú " ñR subrate_min ÕÚ " ñR subrate_max ÓÚ " ñR max_latency ÙÚ " ñR cont_num Ú " ñRsupervision_tmo ðÚ# P BLE_HCI_OCF_LE_SUBRATE_REQ ®Ú" 8 ble_hci_le_subrate_req_cp oÚ " øR conn_handle îÚ " øR subrate_min ÎÚ " øR subrate_max ÌÚ " øR max_latency ÒÚ " øR cont_num
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Ú " øRsupervision_tmo éÚ& P BLE_HCI_OCF_VS_RD_STATIC_ADDR ¶Ú% 8 ble_hci_vs_rd_static_addr_rp (Ú <" Saddr Ú" P BLE_HCI_OCF_VS_SET_TX_PWR ¦Ú! 8 ble_hci_vs_set_tx_pwr_cp §Ú " S tx_power tÚ! 8 ble_hci_vs_set_tx_pwr_rp Ú "
S tx_power rÚ P BLE_HCI_OCF_VS_CSS Ú 8 ble_hci_vs_css_cp »Ú " Sopcode oÚ$ P BLE_HCI_VS_CSS_OP_CONFIGURE @Ú$ 8 ble_hci_vs_css_configure_cp Ú " Sopcode lÚ
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" Sslot_us ÔÚ
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" S period_slots ¼Ú( P BLE_HCI_VS_CSS_OP_SET_NEXT_SLOT ¯Ú( 8 ble_hci_vs_css_set_next_slot_cp µÚ " Sopcode gÚ " S slot_idx nÚ( P BLE_HCI_VS_CSS_OP_SET_CONN_SLOT ÀÚ( 8 ble_hci_vs_css_set_conn_slot_cp ÆÚ " Sopcode cÚ " S conn_handle QÚ " S slot_idx jÚ5 P -BLE_HCI_OCF_LE_ENH_READ_TRANSMIT_POWER_LEVEL ýÚ4 8 ,ble_hci_le_enh_read_transmit_power_level_cp ÞÚ " S conn_handle LÚ " Sphy Ú4 8 ,ble_hci_le_enh_read_transmit_power_level_rp ÏÚ " Sstatus 1Ú " S conn_handle IÚ " Sphy Ú " Scurr_tx_power_level ±Ú " Smax_tx_power_level )Ú8 P 0BLE_HCI_OCF_LE_READ_REMOTE_TRANSMIT_POWER_LEVEL Ú7 8 /ble_hci_le_read_remote_transmit_power_level_cp Ú " £S conn_handle BÚ " £Sphy Ú2 P *BLE_HCI_OCF_LE_SET_PATH_LOSS_REPORT_PARAM ÊÚ1 8 )ble_hci_le_set_path_loss_report_param_cp Ú " §S conn_handle >Ú " §Shigh_threshold îÚ " §Shigh_hysteresis fÚ " §Slow_threshold >Ú " §Slow_hysteresis ¶Ú " §Smin_time_spent ÖÚ3 P +BLE_HCI_OCF_LE_SET_PATH_LOSS_REPORT_ENABLE Ú2 8 *ble_hci_le_set_path_loss_report_enable_cp ³Ú " ¯S conn_handle 6Ú " ¯Senable [Ú3 P +BLE_HCI_OCF_LE_SET_TRANS_PWR_REPORT_ENABLE Ú7 8 /ble_hci_le_set_transmit_power_report_enable_cp xÚ " ³S conn_handle 2Ú " ³S local_enable áÚ " ³Sremote_enable ^Ú$ P BLE_HCI_CTLR_TO_HOST_FC_OFF :Ú$ P BLE_HCI_CTLR_TO_HOST_FC_ACL EÚ% P BLE_HCI_CTLR_TO_HOST_FC_SYNC ÖÚ% P BLE_HCI_CTLR_TO_HOST_FC_BOTH æÚ! P BLE_HCI_ADV_TYPE_ADV_IND FÚ+ P #BLE_HCI_ADV_TYPE_ADV_DIRECT_IND_HD -Ú& P BLE_HCI_ADV_TYPE_ADV_SCAN_IND ¸Ú) P !BLE_HCI_ADV_TYPE_ADV_NONCONN_IND ¾Ú+ P #BLE_HCI_ADV_TYPE_ADV_DIRECT_IND_LD )Ú P BLE_HCI_ADV_TYPE_MAX }Ú P BLE_HCI_ADV_CONN_MASK IÚ P BLE_HCI_ADV_SCAN_MASK RÚ P BLE_HCI_ADV_DIRECT_MASK ¸Ú" P BLE_HCI_ADV_SCAN_RSP_MASK öÚ P BLE_HCI_ADV_LEGACY_MASK ¾Ú) P !BLE_HCI_ADV_DATA_STATUS_COMPLETE ×Ú+ P #BLE_HCI_ADV_DATA_STATUS_INCOMPLETE <Ú* P "BLE_HCI_ADV_DATA_STATUS_TRUNCATED Ú% P BLE_HCI_ADV_DATA_STATUS_MASK Ú$ P BLE_HCI_ADV_OWN_ADDR_PUBLIC jÚ$ P BLE_HCI_ADV_OWN_ADDR_RANDOM hÚ& P BLE_HCI_ADV_OWN_ADDR_PRIV_PUB Ú' P BLE_HCI_ADV_OWN_ADDR_PRIV_RAND ^Ú! P BLE_HCI_ADV_OWN_ADDR_MAX IÚ% P BLE_HCI_ADV_PEER_ADDR_PUBLIC 0Ú% P BLE_HCI_ADV_PEER_ADDR_RANDOM .Ú" P BLE_HCI_ADV_PEER_ADDR_MAX Ú# P BLE_HCI_ADV_CHAN_TXPWR_MIN Ú# P BLE_HCI_ADV_CHAN_TXPWR_MAX Ú& P BLE_HCI_CONN_PEER_ADDR_PUBLIC ÛÚ& P BLE_HCI_CONN_PEER_ADDR_RANDOM ÙÚ, P $BLE_HCI_CONN_PEER_ADDR_PUBLIC_IDENT üÚ, P $BLE_HCI_CONN_PEER_ADDR_RANDOM_IDENT úÚ# P BLE_HCI_CONN_PEER_ADDR_MAX ºÚ P BLE_HCI_ADV_FILT_NONE DÚ P BLE_HCI_ADV_FILT_SCAN OÚ P BLE_HCI_ADV_FILT_CONN FÚ P BLE_HCI_ADV_FILT_BOTH GÚ P BLE_HCI_ADV_FILT_MAX Ú P BLE_HCI_ADV_FILT_DEF §Ú P BLE_HCI_ADV_ITVL ÍÚ P BLE_HCI_ADV_ITVL_MIN Ú P BLE_HCI_ADV_ITVL_MAX Ú% P BLE_HCI_ADV_ITVL_NONCONN_MIN úÚ P BLE_HCI_ADV_ITVL_DEF Ú! P BLE_HCI_ADV_CHANMASK_DEF Ú" P BLE_HCI_SCAN_TYPE_PASSIVE ôÚ! P BLE_HCI_SCAN_TYPE_ACTIVE UÚ P BLE_HCI_SCAN_ITVL Ú P BLE_HCI_SCAN_ITVL_MIN 6Ú P BLE_HCI_SCAN_ITVL_MAX 4Ú" P BLE_HCI_SCAN_ITVL_MAX_EXT ÜÚ P BLE_HCI_SCAN_ITVL_DEF KÚ P BLE_HCI_SCAN_WINDOW_MIN Ú P BLE_HCI_SCAN_WINDOW_MAX Ú$ P BLE_HCI_SCAN_WINDOW_MAX_EXT ?Ú P BLE_HCI_SCAN_WINDOW_DEF ®Ú P BLE_HCI_SCAN_FILT_NO_WL Ú! P BLE_HCI_SCAN_FILT_USE_WL 5Ú& P BLE_HCI_SCAN_FILT_NO_WL_INITA §Ú' P BLE_HCI_SCAN_FILT_USE_WL_INITA UÚ P BLE_HCI_SCAN_FILT_MAX DÚ# P BLE_HCI_ADD_WHITE_LIST_LEN °Ú# P BLE_HCI_RMV_WHITE_LIST_LEN Ú P BLE_HCI_CREATE_CONN_LEN ¹Ú P BLE_HCI_CONN_ITVL xÚ P BLE_HCI_CONN_FILT_NO_WL ~Ú! P BLE_HCI_CONN_FILT_USE_WL ,Ú P BLE_HCI_CONN_FILT_MAX ;Ú P BLE_HCI_CONN_ITVL_MIN -Ú P BLE_HCI_CONN_ITVL_MAX +Ú! P BLE_HCI_CONN_LATENCY_MIN VÚ! P BLE_HCI_CONN_LATENCY_MAX TÚ& P BLE_HCI_CONN_SPVN_TIMEOUT_MIN Ú& P BLE_HCI_CONN_SPVN_TIMEOUT_MAX Ú$ P BLE_HCI_CONN_SPVN_TMO_UNITS Ú* P "BLE_HCI_INITIATOR_FILT_POLICY_MAX oÚ& P BLE_HCI_CONN_PEER_ADDR_PUB_ID ÇÚ' P BLE_HCI_CONN_PEER_ADDR_RAND_ID Ú* P "BLE_HCI_SET_DATALEN_TX_OCTETS_MIN aÚ* P "BLE_HCI_SET_DATALEN_TX_OCTETS_MAX _Ú( P BLE_HCI_SET_DATALEN_TX_TIME_MIN Ú( P BLE_HCI_SET_DATALEN_TX_TIME_MAX Ú P BLE_HCI_LE_PHY_1M Ú P BLE_HCI_LE_PHY_2M
Ú P BLE_HCI_LE_PHY_CODED Ú' P BLE_HCI_LE_PHY_NO_TX_PREF_MASK +Ú' P BLE_HCI_LE_PHY_NO_RX_PREF_MASK -Ú$ P BLE_HCI_LE_PHY_1M_PREF_MASK [Ú$ P BLE_HCI_LE_PHY_2M_PREF_MASK ZÚ' P BLE_HCI_LE_PHY_CODED_PREF_MASK tÚ% P BLE_HCI_LE_PHY_PREF_MASK_ALL þÚ! P BLE_HCI_LE_PHY_CODED_ANY PÚ% P BLE_HCI_LE_PHY_CODED_S2_PREF Ú% P BLE_HCI_LE_PHY_CODED_S8_PREF Ú P BLE_HCI_LE_PHY_CODED_S8 ¯Ú P BLE_HCI_LE_PHY_CODED_S2 µÚ0 P (BLE_HCI_LE_SET_EXT_ADV_PROP_CONNECTABLE Ú. P &BLE_HCI_LE_SET_EXT_ADV_PROP_SCANNABLE 0Ú- P %BLE_HCI_LE_SET_EXT_ADV_PROP_DIRECTED uÚ0 P (BLE_HCI_LE_SET_EXT_ADV_PROP_HD_DIRECTED Ú+ P #BLE_HCI_LE_SET_EXT_ADV_PROP_LEGACY Ú- P %BLE_HCI_LE_SET_EXT_ADV_PROP_ANON_ADV SÚ/ P 'BLE_HCI_LE_SET_EXT_ADV_PROP_INC_TX_PWR xÚ) P !BLE_HCI_LE_SET_EXT_ADV_PROP_MASK Ú/ P 'BLE_HCI_LE_SET_EXT_ADV_PROP_LEGACY_IND ÆÚ2 P *BLE_HCI_LE_SET_EXT_ADV_PROP_LEGACY_LD_DIR ÍÚ2 P *BLE_HCI_LE_SET_EXT_ADV_PROP_LEGACY_HD_DIR ÑÚ0 P (BLE_HCI_LE_SET_EXT_ADV_PROP_LEGACY_SCAN zÚ3 P +BLE_HCI_LE_SET_EXT_ADV_PROP_LEGACY_NONCONN Ú% P BLE_HCI_MAX_EXT_ADV_DATA_LEN Ú% P BLE_HCI_LE_SET_DATA_OPER_INT úÚ' P BLE_HCI_LE_SET_DATA_OPER_FIRST YÚ& P BLE_HCI_LE_SET_DATA_OPER_LAST ¯Ú* P "BLE_HCI_LE_SET_DATA_OPER_COMPLETE Ú+ P #BLE_HCI_LE_SET_DATA_OPER_UNCHANGED LÚ* P "BLE_HCI_MAX_EXT_SCAN_RSP_DATA_LEN _Ú4 P ,BLE_HCI_LE_SET_PERIODIC_ADV_PROP_INC_TX_PWR Ú. P &BLE_HCI_LE_SET_PERIODIC_ADV_PROP_MASK -Ú* P "BLE_HCI_MAX_PERIODIC_ADV_DATA_LEN Ú. P &BLE_HCI_PERIODIC_DATA_STATUS_COMPLETE YÚ0 P (BLE_HCI_PERIODIC_DATA_STATUS_INCOMPLETE ¾Ú/ P 'BLE_HCI_PERIODIC_DATA_STATUS_TRUNCATED Ú P BLE_HCI_PRIVACY_NETWORK Ú P BLE_HCI_PRIVACY_DEVICE Ú# P BLE_HCI_EVCODE_INQUIRY_CMP Ú& P BLE_HCI_EVCODE_INQUIRY_RESULT ¨Ú! P BLE_HCI_EVCODE_CONN_DONE nÚ$ P BLE_HCI_EVCODE_CONN_REQUEST eÚ# P BLE_HCI_EVCODE_DISCONN_CMP ÐÚ 8 ble_hci_ev_disconn_cmp Ú " ¹Tstatus Ú " ¹T conn_handle +Ú " ¹Treason /Ú P BLE_HCI_EVCODE_AUTH_CMP ²Ú( P BLE_HCI_EVCODE_REM_NAME_REQ_CMP )Ú# P BLE_HCI_EVCODE_ENCRYPT_CHG ÇÚ 8 ble_hci_ev_enrypt_chg Ú " ÀTstatus Ú " ÀTconnection_handle Ú " ÀTenabled ãÚ( P BLE_HCI_EVCODE_CHG_LINK_KEY_CMP -Ú+ P #BLE_HCI_EVCODE_MASTER_LINK_KEY_CMP -Ú, P $BLE_HCI_EVCODE_RD_REM_SUPP_FEAT_CMP ÍÚ+ P #BLE_HCI_EVCODE_RD_REM_VER_INFO_CMP Ú' 8 ble_hci_ev_rd_rem_ver_info_cmp [Ú " ÈTstatus Ú " ÈT conn_handle Ú " ÈTversion Ú " ÈT manufacturer Ú " ÈT subversion GÚ% P BLE_HCI_EVCODE_QOS_SETUP_CMP ÷Ú( P BLE_HCI_EVCODE_COMMAND_COMPLETE \Ú$ 8 ble_hci_ev_command_complete Ú " ÐT num_packets üÚ " ÐTopcode Ú " ÐTstatus üÚ <" ÐTreturn_params ÚÚ( 8 ble_hci_ev_command_complete_nop åÚ " ÕT num_packets ÷Ú " ÕTopcode Ú& P BLE_HCI_EVCODE_COMMAND_STATUS ÕÚ" 8 ble_hci_ev_command_status RÚ " ÙTstatus óÚ " ÙT num_packets óÚ " ÙTopcode Ú P BLE_HCI_EVCODE_HW_ERROR Ú 8 ble_hci_ev_hw_error ØÚ " ÞThw_code ·Ú% P BLE_HCI_EVCODE_NUM_COMP_PKTS úÚ 8 comp_pkt XÚ " áThandle Ú " áTpackets Ú! 8 ble_hci_ev_num_comp_pkts ·Ú " äTcount eÚ <" äT
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completed Ú# P BLE_HCI_EVCODE_MODE_CHANGE óÚ( P BLE_HCI_EVCODE_RETURN_LINK_KEYS Ú$ P BLE_HCI_EVCODE_PIN_CODE_REQ sÚ$ P BLE_HCI_EVCODE_LINK_KEY_REQ ^Ú' P BLE_HCI_EVCODE_LINK_KEY_NOTIFY gÚ$ P BLE_HCI_EVCODE_LOOPBACK_CMD Ú) P !BLE_HCI_EVCODE_DATA_BUF_OVERFLOW èÚ% 8 ble_hci_ev_data_buf_overflow %Ú " îT
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link_type Ú% P BLE_HCI_EVCODE_MAX_SLOTS_CHG Ú) P !BLE_HCI_EVCODE_READ_CLK_OFF_COMP ôÚ) P !BLE_HCI_EVCODE_CONN_PKT_TYPE_CHG ÃÚ% P BLE_HCI_EVCODE_QOS_VIOLATION Ú$ P BLE_HCI_EVCODE_PSR_MODE_CHG qÚ& P BLE_HCI_EVCODE_FLOW_SPEC_COMP ÇÚ' P BLE_HCI_EVCODE_INQ_RESULT_RSSI OÚ) P !BLE_HCI_EVCODE_READ_REM_EXT_FEAT ãÚ' P BLE_HCI_EVCODE_SYNCH_CONN_COMP uÚ& P BLE_HCI_EVCODE_SYNCH_CONN_CHG ÔÚ' P BLE_HCI_EVCODE_SNIFF_SUBRATING Ú& P BLE_HCI_EVCODE_EXT_INQ_RESULT ¡Ú' P BLE_HCI_EVCODE_ENC_KEY_REFRESH Ú# 8 ble_hci_ev_enc_key_refresh Ú " ýTstatus ÏÚ " ýT conn_handle çÚ" P BLE_HCI_EVOCDE_IO_CAP_REQ Ú" P BLE_HCI_EVCODE_IO_CAP_RSP Ú( P BLE_HCI_EVCODE_USER_CONFIRM_REQ Ú# P BLE_HCI_EVCODE_PASSKEY_REQ ¶Ú( P BLE_HCI_EVCODE_REM_OOB_DATA_REQ 0Ú( P BLE_HCI_EVCODE_SIMPLE_PAIR_COMP 0Ú( P BLE_HCI_EVCODE_LNK_SPVN_TMO_CHG Ú& P BLE_HCI_EVCODE_ENH_FLUSH_COMP ÍÚ+ P #BLE_HCI_EVCODE_USER_PASSKEY_NOTIFY Ú' P BLE_HCI_EVCODE_KEYPRESS_NOTIFY gÚ* P "BLE_HCI_EVCODE_REM_HOST_SUPP_FEAT hÚ P BLE_HCI_EVCODE_LE_META Ú 8 ble_hci_ev_le_meta kÚ " U subevent sÚ <" Udata Ú& P BLE_HCI_EVCODE_PHYS_LINK_COMP ¸Ú% P BLE_HCI_EVCODE_CHAN_SELECTED WÚ) P !BLE_HCI_EVCODE_DISCONN_PHYS_LINK ÓÚ, P $BLE_HCI_EVCODE_PHYS_LINK_LOSS_EARLY ¾Ú* P "BLE_HCI_EVCODE_PHYS_LINK_RECOVERY pÚ) P !BLE_HCI_EVCODE_LOGICAL_LINK_COMP ûÚ, P $BLE_HCI_EVCODE_DISCONN_LOGICAL_LINK Ú+ P #BLE_HCI_EVCODE_FLOW_SPEC_MODE_COMP 9Ú* P "BLE_HCI_EVCODE_NUM_COMP_DATA_BLKS Ú& P BLE_HCI_EVCODE_AMP_START_TEST Ú$ P BLE_HCI_EVOCDE_AMP_TEST_END hÚ' P BLE_HCI_EVOCDE_AMP_RCVR_REPORT `Ú, P $BLE_HCI_EVCODE_SHORT_RANGE_MODE_CHG úÚ& P BLE_HCI_EVCODE_AMP_STATUS_CHG ÅÚ( P BLE_HCI_EVCODE_TRIG_CLK_CAPTURE 1Ú( P BLE_HCI_EVCODE_SYNCH_TRAIN_COMP #Ú( P BLE_HCI_EVCODE_SYNCH_TRAIN_RCVD #Ú& P BLE_HCI_EVCODE_SLAVE_BCAST_RX ÇÚ' P BLE_HCI_EVCODE_SLAVE_BCAST_TMO Ú' P BLE_HCI_EVCODE_TRUNC_PAGE_COMP Ú* P "BLE_HCI_EVCODE_SLAVE_PAGE_RSP_TMO uÚ, P $BLE_HCI_EVCODE_SLAVE_BCAST_CHAN_MAP Ú& P BLE_HCI_EVCODE_INQ_RSP_NOTIFY £Ú% P BLE_HCI_EVCODE_AUTH_PYLD_TMO Ú! 8 ble_hci_ev_auth_pyld_tmo ½Ú " §U conn_handle <Ú& P BLE_HCI_EVCODE_SAM_STATUS_CHG ÂÚ P BLE_HCI_EVCODE_VS_DEBUG ´Ú 8 ble_hci_ev_vs_debug ñÚ " «Uid ÿÚ <" «Udata ùÚ' P BLE_HCI_LE_SUBEV_CONN_COMPLETE pÚ* 8 "ble_hci_ev_le_subev_conn_complete
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Ú " ¯U subev_code Ú " ¯Ustatus Ú " ¯U conn_handle 4Ú " ¯Urole Ú " ¯Upeer_addr_type éÚ <" ¯U
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peer_addr ÙÚ " ¯U
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conn_itvl åÚ " ¯U conn_latency ®Ú " ¯Usupervision_timeout pÚ " ¯Umca Ú! P BLE_HCI_LE_SUBEV_ADV_RPT 2Ú 8 adv_report {Ú " »Utype öÚ " »U
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addr_type òÚ <" »Uaddr âÚ " »U data_len xÚ <" »Udata éÚ$ 8 ble_hci_ev_le_subev_adv_rpt Ú " ÁU subev_code Ú " ÁU num_reports æÚ <" ÁUreports hÚ+ P #BLE_HCI_LE_SUBEV_CONN_UPD_COMPLETE Ú. 8 &ble_hci_ev_le_subev_conn_upd_complete ZÚ " ÆU subev_code Ú " ÆUstatus Ú " ÆU conn_handle Ú " ÆU
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conn_itvl ÎÚ " ÆU conn_latency Ú " ÆUsupervision_timeout YÚ* P "BLE_HCI_LE_SUBEV_RD_REM_USED_FEAT hÚ- 8 %ble_hci_ev_le_subev_rd_rem_used_feat âÚ " ÎU subev_code zÚ " ÎUstatus ýÚ " ÎU conn_handle Ú <" ÎU features Ú$ P BLE_HCI_LE_SUBEV_LT_KEY_REQ -Ú' 8 ble_hci_ev_le_subev_lt_key_req GÚ " ÔU subev_code tÚ " ÔU conn_handle Ú (" ÔUrand ÑÚ " ÔUdiv UÚ+ P #BLE_HCI_LE_SUBEV_REM_CONN_PARM_REQ Ú/ 8 'ble_hci_ev_le_subev_rem_conn_param_req þÚ " ÚU subev_code nÚ " ÚU conn_handle Ú " ÚU min_interval xÚ " ÚU max_interval vÚ " ÚUlatency Ú " ÚUtimeout Ú& P BLE_HCI_LE_SUBEV_DATA_LEN_CHG ÏÚ) 8 !ble_hci_ev_le_subev_data_len_chg ©Ú " âU subev_code fÚ " âU conn_handle Ú " âUmax_tx_octets ôÚ " âU max_tx_time ÛÚ " âUmax_rx_octets öÚ " âU max_rx_time ÝÚ, P $BLE_HCI_LE_SUBEV_RD_LOC_P256_PUBKEY þÚ/ 8 'ble_hci_ev_le_subev_rd_loc_p256_pubkey Ú " êU subev_code ^Ú " êUstatus áÚ <" @êU public_key áÚ, P $BLE_HCI_LE_SUBEV_GEN_DHKEY_COMPLETE æÚ/ 8 'ble_hci_ev_le_subev_gen_dhkey_complete Ú " ïU subev_code YÚ " ïUstatus ÜÚ <" ïUdh_key ·Ú+ P #BLE_HCI_LE_SUBEV_ENH_CONN_COMPLETE .Ú. 8 &ble_hci_ev_le_subev_enh_conn_complete hÚ " ôU subev_code TÚ " ôUstatus ×Ú " ôU conn_handle ïÚ " ôUrole ÍÚ " ôUpeer_addr_type ¤Ú <" ôU
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peer_addr Ú <" ôU
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local_rpa Ú <" ôU peer_rpa îÚ " ôU
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conn_itvl Ú " ôU conn_latency iÚ " ôUsupervision_timeout +Ú " ôUmca PÚ( P BLE_HCI_LE_SUBEV_DIRECT_ADV_RPT
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Ú 8 dir_adv_report ÕÚ " Vtype .Ú " V
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addr_type *Ú <" Vaddr Ú " Vdir_addr_type Ú <" V dir_addr tÚ " Vrssi 1Ú+ 8 #ble_hci_ev_le_subev_direct_adv_rpt ¤Ú " V subev_code ¾Ú " V num_reports Ú <" Vreports Ú- P %BLE_HCI_LE_SUBEV_PHY_UPDATE_COMPLETE Ú0 8 (ble_hci_ev_le_subev_phy_update_complete yÚ " V subev_code ¹Ú " Vstatus <Ú " V conn_handle TÚ " Vtx_phy DÚ " Vrx_phy FÚ% P BLE_HCI_LE_SUBEV_EXT_ADV_RPT ÚÚ 8 ext_adv_report ÃÚ " V evt_type \Ú " V
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addr_type Ú <" Vaddr Ú " Vpri_phy ÜÚ " Vsec_phy ìÚ " Vsid Ú " V tx_power _Ú " Vrssi Ú " Vperiodic_itvl UÚ " Vdir_addr_type qÚ <" V dir_addr aÚ " V data_len Ú <" Vdata Ú( 8 ble_hci_ev_le_subev_ext_adv_rpt ÔÚ " £V subev_code ¤Ú " £V num_reports Ú <" £Vreports
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