修改bug，io改为不拉

WXK

2025-05-22 035ecb85c3513be2b6ab5c515db082cb7fee8f97

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__DATE__ "Apr 22 2025"
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ôble_l2cap_reconfig'@
ôble_l2cap_disconnect!D
ôble_l2cap_send'L
ôble_l2cap_recv_readyÄøble_l2cap_rxœ
ôble_l2cap_tx!8
ôble_l2cap_init
z

%

.


|}~

SDK_CONFIG_H 
CONFIG_SOC_DCDC_PAN1070 1
CONFIG_SYSTEM_CLOCK 48
(CONFIG_APB1_CLOCK_DIVISOR 2
5CONFIG_APB2_CLOCK_DIVISOR 2
<CONFIG_LOW_SPEED_CLOCK_SRC 1
ACONFIG_FORCE_CALIB_RCL_CLK 0
ECONFIG_RAM_FUNCTION 1
JCONFIG_FLASH_LDO_EN 1
MCONFIG_VECTOR_REMAP_TO_RAM 1
QCONFIG_AUTO_OPTIMIZE_POWER_PARAM 0
TCONFIG_TEMP_SAMPLE_INTERVAL_S 300
WCONFIG_DVDD_VOL_OPTIMIZE_EN 1
bCONFIG_PM 0
eCONFIG_SYSTEM_WATCH_DOG_ENABLE 0
kCONFIG_KEEP_FLASH_POWER_IN_LP_MODE 1
pCONFIG_DEEPSLEEP_MODE_2 0
}CONFIG_SOC_INCREASE_LPLDOH_CALIB_CODE 0
‚
CONFIG_PM_STANDBY_M1_WAKEUP_WITHOUT_RESET 0
…
CONFIG_HCLK_OPTIMIZE_EN 0
Ž
CONFIG_OS_EN 1
‘
configMAX_PRIORITIES 8
”
configTOTAL_HEAP_SIZE 11000
—
CONFIG_MAIN_TASK_STACK_SIZE 400
š
CONFIG_MAIN_TASK_PRIO 3

CONFIG_BLE_HOST_THREAD_STACK_SIZE 400
 
CONFIG_BLE_HOST_THREAD_PRIO 6
£
configUSE_TIMERS 1
¦
configTIMER_TASK_STACK_DEPTH 128
©
configTIMER_TASK_PRIORITY 2
¬
configTIMER_QUEUE_LENGTH 12
¯
configUSE_IDLE_HOOK 0
²
configUSE_TICK_HOOK 0
µ
configUSE_MALLOC_FAILED_HOOK 1
¹
configCHECK_FOR_STACK_OVERFLOW 0
¼
CONFIG_FREERTOS_HEAP_PRINT 0
Æ
CONFIG_USER_CHIP_MAC_ADDR 1
Ó
CONFIG_BT_CTLR_TX_POWER_DFT 0
Ö
CONFIG_BT_MAX_NUM_OF_CENTRAL 1
Ù
CONFIG_BT_MAX_NUM_OF_PERIPHERAL 1
Ü
MYNEWT_VAL_BLE_ROLE_BROADCASTER 1
ß
MYNEWT_VAL_BLE_ROLE_CENTRAL 1
â
MYNEWT_VAL_BLE_ROLE_OBSERVER 1
å
MYNEWT_VAL_BLE_ROLE_PERIPHERAL 1
è
MYNEWT_VAL_BLE_ATT_PREFERRED_MTU 247
ë
MYNEWT_VAL_BLE_TRANSPORT_ACL_FROM_LL_COUNT 8
î
MYNEWT_VAL_BLE_TRANSPORT_ACL_SIZE 251
ñ
MYNEWT_VAL_BLE_TRANSPORT_EVT_COUNT 8
ô
MYNEWT_VAL_BLE_TRANSPORT_EVT_DISCARDABLE_COUNT 6
÷
MYNEWT_VAL_MSYS_1_BLOCK_COUNT 4
ú
MYNEWT_VAL_MSYS_1_BLOCK_SIZE 120
ý
CONFIG_BLE_CONTROLLER_RF_RX_BUF_NUM 8
€CONFIG_BLE_CONTROLLER_RF_TX_BUF_NUM 4
ƒCONFIG_BLE_CONTROLLER_LL_ENC_TIME 300
†CONFIG_BLE_CONTROLLER_MORE_DATA_NUM 6
‰CONFIG_BLE_CONTROLLER_WIHTELIST_NUM 1
ŒCONFIG_BLE_CONTROLLER_RESOLVELIST_NUM 0
CONFIG_BLE_CONTROLLER_MASTER_LINK_MARGIN 10
“CONFIG_BLE_LL_IRQ_PRIO 0
—CONFIG_BLE_EVT_HANDLER_IRQ_PRIO 1
¡MYNEWT_VAL_BLE_SM_SC_LVL 2
¤MYNEWT_VAL_BLE_SM_LEGACY 1
§MYNEWT_VAL_BLE_SM_SC 0
¯CONFIG_HS_IO_CAPABILITY 3
²MYNEWT_VAL_BLE_SM_BONDING 0
µMYNEWT_VAL_BLE_SM_MITM 0
¸MYNEWT_VAL_BLE_SM_OOB_DATA_FLAG 0
¿MYNEWT_VAL_BLE_SM_OUR_KEY_DIST 1
ÆMYNEWT_VAL_BLE_SM_THEIR_KEY_DIST 1
ÉMYNEWT_VAL_BLE_STORE_CONFIG_PERSIST 1
ÌMYNEWT_VAL_BLE_STORE_MAX_BONDS 2
ÏMYNEWT_VAL_BLE_STORE_MAX_CCCDS 8
ÒMYNEWT_VAL_HOST_SOFTWARE_RPA 1
æCONFIG_FLASH_SIZE 0x7F000
íCONFIG_FLASH_PARTITION_BOOTLOADER_ADDR 0x00000
òCONFIG_FLASH_PARTITION_BOOTLOADER_SIZE 0x0A000
÷CONFIG_FLASH_PARTITION_APP_ADDR 0x0A000
üCONFIG_FLASH_PARTITION_APP_SIZE 0x37000
CONFIG_FLASH_PARTITION_APP_BACKUP_ADDR 0x41000
†CONFIG_FLASH_PARTITION_APP_BACKUP_SIZE 0x37000
ŠCONFIG_FLASH_PARTITION_KVSTORE_ADDR 0x78000
CONFIG_FLASH_PARTITION_KVSTORE_SIZE 0x04000
”CONFIG_FLASH_PARTITION_USER_CUSTOM_ADDR 0x7C000
™CONFIG_FLASH_PARTITION_USER_CUSTOM_SIZE 0x03000
ÈCONFIG_APP_USE_IMAGE_HEADER 1
ËCONFIG_APP_IMG_VER_MAJOR 0
ÎCONFIG_APP_IMG_VER_MINOR 0
ÑCONFIG_APP_IMG_VER_REVISION 1
ÔCONFIG_APP_IMG_VER_BUILD 0
áCONFIG_FIRMWARE_ENCRYPTION 0
óAPP_LOG_EN 1
ûAPP_LOG_LVL 4
þAPP_LOG_LVL_OUTPUT_EN 1
APP_LOG_TRACE_OUTPUT_EN 0
„CONFIG_UART_LOG_ENABLE 1
CONFIG_LOG_UART_PIN 2
™CONFIG_LOG_UART_BAUDRATE 921600
 CONFIG_RTT_LOG_ENABLE 0
¤CONFIG_LOG_RTT_UP_BUFFER_SIZE 512
ªCONFIG_IO_TIMING_TRACK 0
±CONFIG_BT_CTLR_LINK_LAYER_DEBUG 0
ÐCONFIG_TRACK_PIN_DEEPSLEEP_MODE 0x22
ïCONFIG_TRACK_PIN_SLEEP_MODE 0x23
ŽCONFIG_TRACK_PIN_LL_IRQ 0x99
®CONFIG_TRACK_PIN_BLE_EVNT_IRQ 0x99
ÍCONFIG_TRACK_PIN_OS_TICK_IRQ 0x99
ìCONFIG_TRACK_PIN_SLPTMR_IRQ 0x99
‹CONFIG_TRACK_PIN_HARDFAULT_IRQ 0x99
ªCONFIG_TRACK_PIN_DMA_IRQ 0x99
ÉCONFIG_TRACK_PIN_GPIO0_IRQ 0x99
èCONFIG_TRACK_PIN_GPIO1_IRQ 0x99
‡CONFIG_TRACK_PIN_GPIO2_IRQ 0x99
¦CONFIG_TRACK_PIN_GPIO3_IRQ 0x99
ÅCONFIG_TRACK_PIN_I2C_IRQ 0x99
äCONFIG_TRACK_PIN_SPI0_IRQ 0x99
ƒCONFIG_TRACK_PIN_SPI1_IRQ 0x99
¢CONFIG_TRACK_PIN_TMR0_IRQ 0x99
ÁCONFIG_TRACK_PIN_TMR1_IRQ 0x99
àCONFIG_TRACK_PIN_TMR2_IRQ 0x99
ÿCONFIG_TRACK_PIN_UART0_IRQ 0x99
ž    CONFIG_TRACK_PIN_UART1_IRQ 0x99
½    CONFIG_TRACK_PIN_WDT_IRQ 0x99
Ü    CONFIG_TRACK_PIN_WWDT_IRQ 0x99
û    CONFIG_TRACK_USER_APP_CHN0 0x99
š
CONFIG_TRACK_USER_APP_CHN1 0x99
¹
CONFIG_TRACK_USER_APP_CHN2 0x99
Ø
CONFIG_TRACK_USER_APP_CHN3 0x99
÷
CONFIG_TRACK_USER_APP_CHN4 0x99
–CONFIG_TRACK_USER_APP_CHN5 0x99
µCONFIG_TRACK_USER_APP_CHN6 0x99
ÔCONFIG_TRACK_USER_APP_CHN7 0x99
ÚCONFIG_STARTUP_LONG_DELAY 0@4
 




.\configuration\sdk_config.h


Ð
.\configuration\sdk_config.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x
€‚

_SOC_CONFIG_H_ 
TCONFIG_RAM_CODE __attribute__((section(".ramfunc")))
™
CONFIG_FLASH_PARTITION_CHIP_INFO_ADDR 0x7F000
š
CONFIG_FLASH_PARTITION_CHIP_INFO_SIZE 0x1000
«
IS_BOOTABLE_APP 0
Ã
ENCRYPT_SECTION dX
 




..\..\..\..\config\.\configuration\soc_config.h
sdk_config.h

Ô
..\..\..\..\config\soc_config.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x
„…†

__string_h 
__ARMCLIB_VERSION 5060037
_ARMABI __declspec(__nothrow)
__STRING_DECLS __CLIBNS
$__CLIBNS 7NULL
8NULL 0PD
 




C:\Keil_v5\ARM\ARMCC\Bin\..\include\string.h


¨C:\Keil_v5\ARM\ARMCC\Bin\..\include\string.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]unsigned intPsize_tŠ
,
ˆ‰Š

 __errno_h 
__ARMCLIB_VERSION 5060037
_ARMABI_PURE __declspec(__nothrow) __attribute__((const))
__ERRNO_DECLS __CLIBNS
__CLIBNS 
/errno (*__CLIBNS __aeabi_errno_addr())
MEDOM 1
XERANGE 2
eEILSEQ 4
rESIGNUM 3
yEINVAL 5
zENOMEM 6LC
 




C:\Keil_v5\ARM\ARMCC\Bin\..\include\errno.h


ˆC:\Keil_v5\ARM\ARMCC\Bin\..\include\errno.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]
ŒŽ

H_MYNEWT_SYSCFG_ 

NIMBLE_BUG_FIXED_EN 1
MYNEWT_VAL(_name) MYNEWT_VAL_ ## _name
MYNEWT_VAL_CHOICE(_name,_val) MYNEWT_VAL_ ## _name ## __ ## _val
MYNEWT_VAL_TINYCRYPT_SYSINIT_STAGE (200)
MYNEWT_VAL_TINYCRYPT_UECC_RNG_TRNG_DEV_NAME ("trng")
 MYNEWT_VAL_TINYCRYPT_UECC_RNG_USE_TRNG (0)
%MYNEWT_VAL_BSP_SIMULATED (1)
*MYNEWT_VAL_HAL_ENABLE_SOFTWARE_BREAKPOINTS (1)
.MYNEWT_VAL_HAL_FLASH_MAX_DEVICE_COUNT (0)
2MYNEWT_VAL_HAL_FLASH_VERIFY_BUF_SZ (16)
6MYNEWT_VAL_HAL_FLASH_VERIFY_ERASES (0)
:MYNEWT_VAL_HAL_FLASH_VERIFY_WRITES (0)
>MYNEWT_VAL_HAL_SBRK (1)
BMYNEWT_VAL_HAL_SYSTEM_RESET_CB (0)
GMYNEWT_VAL_I2C_0 (0)
KMYNEWT_VAL_MCU_FLASH_MIN_WRITE_SIZE (1)
OMYNEWT_VAL_MCU_FLASH_STYLE_NORDIC (0)
SMYNEWT_VAL_MCU_FLASH_STYLE_ST (1)
WMYNEWT_VAL_MCU_NATIVE (1)
[MYNEWT_VAL_MCU_NATIVE_USE_SIGNALS (1)
_MYNEWT_VAL_MCU_TIMER_POLLER_PRIO (0)
cMYNEWT_VAL_MCU_UART_POLLER_PRIO (1)
hMYNEWT_VAL_FLOAT_USER (0)
tMYNEWT_VAL_MSYS_1_SANITY_MIN_COUNT (0)
xMYNEWT_VAL_MSYS_2_BLOCK_COUNT (0)
|MYNEWT_VAL_MSYS_2_BLOCK_SIZE (0)
€
MYNEWT_VAL_MSYS_2_SANITY_MIN_COUNT (0)
„
MYNEWT_VAL_MSYS_SANITY_TIMEOUT (60000)
ˆ
MYNEWT_VAL_OS_ASSERT_CB (0)
Œ
MYNEWT_VAL_OS_CLI (0)

MYNEWT_VAL_OS_COREDUMP (0)
”
MYNEWT_VAL_OS_COREDUMP_CB (0)
˜
MYNEWT_VAL_OS_CPUTIME_FREQ (1000000)
œ
MYNEWT_VAL_OS_CPUTIME_TIMER_NUM (0)
¡
MYNEWT_VAL_OS_CRASH_FILE_LINE (1)
¥
MYNEWT_VAL_OS_CRASH_LOG (0)
©
MYNEWT_VAL_OS_CRASH_RESTORE_REGS (0)
­
MYNEWT_VAL_OS_CRASH_STACKTRACE (0)
±
MYNEWT_VAL_OS_CTX_SW_STACK_CHECK (0)
µ
MYNEWT_VAL_OS_CTX_SW_STACK_GUARD (4)
¹
MYNEWT_VAL_OS_DEBUG_MODE (0)
½
MYNEWT_VAL_OS_EVENTQ_DEBUG (0)
Á
MYNEWT_VAL_OS_EVENTQ_MONITOR (0)
Å
MYNEWT_VAL_OS_IDLE_TICKLESS_MS_MAX (600000)
Ê
MYNEWT_VAL_OS_IDLE_TICKLESS_MS_MIN (1)
Î
MYNEWT_VAL_OS_MAIN_STACK_SIZE (256)
Ò
MYNEWT_VAL_OS_MAIN_TASK_PRIO (127)
Ö
MYNEWT_VAL_OS_MAIN_TASK_SANITY_ITVL_MS (0)
Ú
MYNEWT_VAL_OS_MEMPOOL_CHECK (0)
Þ
MYNEWT_VAL_OS_MEMPOOL_GUARD (0)
â
MYNEWT_VAL_OS_MEMPOOL_POISON (0)
æ
MYNEWT_VAL_OS_SCHEDULING (1)
ê
MYNEWT_VAL_OS_SYSINIT_STAGE (0)
î
MYNEWT_VAL_OS_SYSVIEW (0)
ò
MYNEWT_VAL_OS_SYSVIEW_TRACE_CALLOUT (1)
ö
MYNEWT_VAL_OS_SYSVIEW_TRACE_EVENTQ (1)
ú
MYNEWT_VAL_OS_SYSVIEW_TRACE_MBUF (0)
þ
MYNEWT_VAL_OS_SYSVIEW_TRACE_MEMPOOL (0)
‚MYNEWT_VAL_OS_SYSVIEW_TRACE_MUTEX (1)
†MYNEWT_VAL_OS_SYSVIEW_TRACE_SEM (1)
ŠMYNEWT_VAL_OS_TASK_RUN_TIME_CPUTIME (0)
MYNEWT_VAL_OS_TICKS_PER_SEC (configTICK_RATE_HZ)
“MYNEWT_VAL_OS_TIME_DEBUG (0)
—MYNEWT_VAL_OS_WATCHDOG_MONITOR (0)
›MYNEWT_VAL_SANITY_INTERVAL (15000)
ŸMYNEWT_VAL_WATCHDOG_INTERVAL (30000)
¤MYNEWT_VAL_NATIVE_SOCKETS_MAX (8)
¨MYNEWT_VAL_NATIVE_SOCKETS_MAX_UDP (2048)
¬MYNEWT_VAL_NATIVE_SOCKETS_POLL_INTERVAL_MS (200)¯MYNEWT_VAL_NATIVE_SOCKETS_POLL_ITVL
²MYNEWT_VAL_NATIVE_SOCKETS_PRIO (2)
¶MYNEWT_VAL_NATIVE_SOCKETS_STACK_SZ (4096)
ºMYNEWT_VAL_NATIVE_SOCKETS_SYSINIT_STAGE (200)
¿MYNEWT_VAL_CONSOLE_UART_BAUD (115200)
ÃMYNEWT_VAL_CONSOLE_UART_DEV ("uart0")
ÇMYNEWT_VAL_CONSOLE_UART_FLOW_CONTROL (UART_FLOW_CTL_NONE)
ÌMYNEWT_VAL_FLASH_MAP_MAX_AREAS (10)
ÐMYNEWT_VAL_FLASH_MAP_SUPPORT_MFG (0)
ÔMYNEWT_VAL_FLASH_MAP_SYSINIT_STAGE (9)
ÙMYNEWT_VAL_DFLT_LOG_LVL (1)
ÝMYNEWT_VAL_DFLT_LOG_MOD (0)
áMYNEWT_VAL_LOG_GLOBAL_IDX (1)
æMYNEWT_VAL_MODLOG_CONSOLE_DFLT (1)
êMYNEWT_VAL_MODLOG_LOG_MACROS (0)
îMYNEWT_VAL_MODLOG_MAX_MAPPINGS (16)
òMYNEWT_VAL_MODLOG_MAX_PRINTF_LEN (128)
öMYNEWT_VAL_MODLOG_SYSINIT_STAGE (100)
ûMYNEWT_VAL_LOG_CONSOLE (1)
ÿMYNEWT_VAL_LOG_FCB (0)
ƒMYNEWT_VAL_LOG_FCB_SLOT1 (0)
‡MYNEWT_VAL_LOG_LEVEL (255)
ŒMYNEWT_VAL_DEBUG_PANIC_ENABLED (1)
‘MYNEWT_VAL_SYSDOWN_CONSTRAIN_DOWN (1)
•MYNEWT_VAL_SYSDOWN_PANIC_FILE_LINE (0)
™MYNEWT_VAL_SYSDOWN_PANIC_MESSAGE (0)
MYNEWT_VAL_SYSDOWN_TIMEOUT_MS (10000)
¢MYNEWT_VAL_SYSINIT_CONSTRAIN_INIT (1)
§MYNEWT_VAL_SYSINIT_PANIC_FILE_LINE (1)
¬MYNEWT_VAL_SYSINIT_PANIC_MESSAGE (1)
±MYNEWT_VAL_RWLOCK_DEBUG (0)
¶MYNEWT_VAL_BLE_EXT_ADV (0)
ºMYNEWT_VAL_BLE_EXT_ADV_MAX_SIZE (31)
¾MYNEWT_VAL_BLE_HCI_VS (0)
ÂMYNEWT_VAL_BLE_HCI_VS_OCF_OFFSET (0)
ÆMYNEWT_VAL_BLE_ISO (0)
ÊMYNEWT_VAL_BLE_ISO_TEST (0)
ÎMYNEWT_VAL_BLE_MAX_CONNECTIONS (CONFIG_BT_MAX_NUM_OF_CENTRAL + CONFIG_BT_MAX_NUM_OF_PERIPHERAL)
ÒMYNEWT_VAL_BLE_MAX_PERIODIC_SYNCS (1)
ÖMYNEWT_VAL_BLE_MULTI_ADV_INSTANCES (0)
ÚMYNEWT_VAL_BLE_PERIODIC_ADV (0)
ÞMYNEWT_VAL_BLE_PERIODIC_ADV_SYNC_TRANSFER (0)
òMYNEWT_VAL_BLE_VERSION (50)
öMYNEWT_VAL_BLE_WHITELIST (1)
úMYNEWT_VAL_BLE_POWER_CONTROL (0)
ƒMYNEWT_VAL_BLE_ATT_SVR_FIND_INFO (1)
‡MYNEWT_VAL_BLE_ATT_SVR_FIND_TYPE (1)
‹MYNEWT_VAL_BLE_ATT_SVR_INDICATE (1)
MYNEWT_VAL_BLE_ATT_SVR_MAX_PREP_ENTRIES (16)
“MYNEWT_VAL_BLE_ATT_SVR_NOTIFY (1)
—MYNEWT_VAL_BLE_ATT_SVR_QUEUED_WRITE (1)
›MYNEWT_VAL_BLE_ATT_SVR_QUEUED_WRITE_TMO (30000)
ŸMYNEWT_VAL_BLE_ATT_SVR_READ (1)
£MYNEWT_VAL_BLE_ATT_SVR_READ_BLOB (1)
§MYNEWT_VAL_BLE_ATT_SVR_READ_GROUP_TYPE (1)
«MYNEWT_VAL_BLE_ATT_SVR_READ_MULT (1)
¯MYNEWT_VAL_BLE_ATT_SVR_READ_TYPE (1)
³MYNEWT_VAL_BLE_ATT_SVR_SIGNED_WRITE (1)
·MYNEWT_VAL_BLE_ATT_SVR_WRITE (1)
»MYNEWT_VAL_BLE_ATT_SVR_WRITE_NO_RSP (1)
¿MYNEWT_VAL_BLE_GAP_MAX_PENDING_CONN_PARAM_UPDATE (1)
ÃMYNEWT_VAL_BLE_GATT_DISC_ALL_CHRS (MYNEWT_VAL_BLE_ROLE_CENTRAL)
ÇMYNEWT_VAL_BLE_GATT_DISC_ALL_DSCS (MYNEWT_VAL_BLE_ROLE_CENTRAL)
ËMYNEWT_VAL_BLE_GATT_DISC_ALL_SVCS (MYNEWT_VAL_BLE_ROLE_CENTRAL)
ÏMYNEWT_VAL_BLE_GATT_DISC_CHR_UUID (MYNEWT_VAL_BLE_ROLE_CENTRAL)
ÓMYNEWT_VAL_BLE_GATT_DISC_SVC_UUID (MYNEWT_VAL_BLE_ROLE_CENTRAL)
×MYNEWT_VAL_BLE_GATT_FIND_INC_SVCS (MYNEWT_VAL_BLE_ROLE_CENTRAL)
ÛMYNEWT_VAL_BLE_GATT_INDICATE (1)
ßMYNEWT_VAL_BLE_GATT_MAX_PROCS (4)
ãMYNEWT_VAL_BLE_GATT_NOTIFY (1)
çMYNEWT_VAL_BLE_GATT_READ (MYNEWT_VAL_BLE_ROLE_CENTRAL)
ëMYNEWT_VAL_BLE_GATT_READ_LONG (MYNEWT_VAL_BLE_ROLE_CENTRAL)
ïMYNEWT_VAL_BLE_GATT_READ_MAX_ATTRS (8)
óMYNEWT_VAL_BLE_GATT_READ_MULT (MYNEWT_VAL_BLE_ROLE_CENTRAL)
÷MYNEWT_VAL_BLE_GATT_READ_UUID (MYNEWT_VAL_BLE_ROLE_CENTRAL)
ûMYNEWT_VAL_BLE_GATT_RESUME_RATE (1000)
ÿMYNEWT_VAL_BLE_GATT_SIGNED_WRITE (MYNEWT_VAL_BLE_ROLE_CENTRAL)
ƒMYNEWT_VAL_BLE_GATT_WRITE (MYNEWT_VAL_BLE_ROLE_CENTRAL)
‡MYNEWT_VAL_BLE_GATT_WRITE_LONG (MYNEWT_VAL_BLE_ROLE_CENTRAL)
‹MYNEWT_VAL_BLE_GATT_WRITE_MAX_ATTRS (4)
MYNEWT_VAL_BLE_GATT_WRITE_NO_RSP (MYNEWT_VAL_BLE_ROLE_CENTRAL)
“MYNEWT_VAL_BLE_GATT_WRITE_RELIABLE (MYNEWT_VAL_BLE_ROLE_CENTRAL)
—MYNEWT_VAL_BLE_HOST (1)
›MYNEWT_VAL_BLE_HOST_THREAD_STACK_SIZE (256)
ŸMYNEWT_VAL_BLE_HOST_THREAD_PRIORITY (6)
£MYNEWT_VAL_BLE_HS_AUTO_START (1)
§MYNEWT_VAL_BLE_HS_DEBUG (0)
«MYNEWT_VAL_BLE_HS_FLOW_CTRL (0)
¯MYNEWT_VAL_BLE_HS_FLOW_CTRL_ITVL (1000)
³MYNEWT_VAL_BLE_HS_FLOW_CTRL_THRESH (2)
·MYNEWT_VAL_BLE_HS_FLOW_CTRL_TX_ON_DISCONNECT (0)
»MYNEWT_VAL_BLE_HS_LOG_LVL (1)
¿MYNEWT_VAL_BLE_HS_LOG_MOD (4)
ÃMYNEWT_VAL_BLE_HS_PHONY_HCI_ACKS (0)
ÇMYNEWT_VAL_BLE_HS_REQUIRE_OS (1)
ËMYNEWT_VAL_BLE_HS_STOP_ON_SHUTDOWN (1)
ÏMYNEWT_VAL_BLE_HS_STOP_ON_SHUTDOWN_TIMEOUT (2000)
ÓMYNEWT_VAL_BLE_HS_SYSINIT_STAGE (200)
×MYNEWT_VAL_BLE_L2CAP_COC_MAX_NUM (0)
ÛMYNEWT_VAL_BLE_L2CAP_COC_MPS (MYNEWT_VAL_MSYS_1_BLOCK_SIZE-8)
ßMYNEWT_VAL_BLE_L2CAP_ENHANCED_COC (0)
ãMYNEWT_VAL_BLE_L2CAP_JOIN_RX_FRAGS (1)
çMYNEWT_VAL_BLE_L2CAP_MAX_CHANS (3*MYNEWT_VAL_BLE_MAX_CONNECTIONS)
ëMYNEWT_VAL_BLE_L2CAP_RX_FRAG_TIMEOUT (30000)
ïMYNEWT_VAL_BLE_L2CAP_SIG_MAX_PROCS (1)
óMYNEWT_VAL_BLE_MESH (0)
÷MYNEWT_VAL_BLE_MONITOR_CONSOLE_BUFFER_SIZE (128)
ûMYNEWT_VAL_BLE_MONITOR_RTT (0)
ÿMYNEWT_VAL_BLE_MONITOR_RTT_BUFFERED (1)
ƒMYNEWT_VAL_BLE_MONITOR_RTT_BUFFER_NAME ("btmonitor")
‡MYNEWT_VAL_BLE_MONITOR_RTT_BUFFER_SIZE (256)
‹MYNEWT_VAL_BLE_MONITOR_UART (0)
MYNEWT_VAL_BLE_MONITOR_UART_BAUDRATE (1000000)
“MYNEWT_VAL_BLE_MONITOR_UART_BUFFER_SIZE (64)
—MYNEWT_VAL_BLE_MONITOR_UART_DEV ("uart0")
›MYNEWT_VAL_BLE_RPA_TIMEOUT (300)
£MYNEWT_VAL_BLE_SM_IO_CAP (CONFIG_HS_IO_CAPABILITY)
§MYNEWT_VAL_BLE_SM_KEYPRESS (0)
¯MYNEWT_VAL_BLE_SM_MAX_PROCS (1)
ÃMYNEWT_VAL_BLE_SM_SC_DEBUG_KEYS (0)
ËMYNEWT_VAL_BLE_SM_SC_ONLY (0)
àMYNEWT_VAL_BLE_SVC_ANS_NEW_ALERT_CAT (0)
äMYNEWT_VAL_BLE_SVC_ANS_SYSINIT_STAGE (303)
èMYNEWT_VAL_BLE_SVC_ANS_UNR_ALERT_CAT (0)
íMYNEWT_VAL_BLE_SVC_BAS_BATTERY_LEVEL_NOTIFY_ENABLE (1)
ñMYNEWT_VAL_BLE_SVC_BAS_BATTERY_LEVEL_READ_PERM (0)
õMYNEWT_VAL_BLE_SVC_BAS_SYSINIT_STAGE (303)
úMYNEWT_VAL_BLE_SVC_DIS_DEFAULT_READ_PERM (-1)
þMYNEWT_VAL_BLE_SVC_DIS_FIRMWARE_REVISION_DEFAULT (NULL)
ƒMYNEWT_VAL_BLE_SVC_DIS_FIRMWARE_REVISION_READ_PERM (-1)
‡MYNEWT_VAL_BLE_SVC_DIS_HARDWARE_REVISION_DEFAULT (NULL)
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™MYNEWT_VAL_BLE_SVC_DIS_MODEL_NUMBER_DEFAULT ("Apache Mynewt NimBLE")
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ÍMYNEWT_VAL_BLE_SVC_GAP_DEVICE_NAME ("nimble")
ÑMYNEWT_VAL_BLE_SVC_GAP_DEVICE_NAME_MAX_LENGTH (31)
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ÝMYNEWT_VAL_BLE_SVC_GAP_PPCP_MIN_CONN_INTERVAL (6)
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ïMYNEWT_VAL_BLE_SOCK_TASK_PRIO (9)
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..\..\..\..\config\.\configuration\nimble_syscfg.h
sdk_config.h

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..\..\..\..\config\nimble_syscfg.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x
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__assert_h 
_ARMABI_NORETURN __declspec(__nothrow) __declspec(__noreturn)
__ARMCLIB_VERSION 5060037
!__ARM_PROMISE __promise#__CLIBNS
)__CLIBNS E__promise
Fassert(e) ((e) ? (void)0 : __CLIBNS abort(), (__ARM_PROMISE)((e)?1:0))
J__promise(e) assert(e)2assert3__promiseE__promise
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J__promise(e) assert(e)2assert3__promiseE__promise
Fassert(e) ((e) ? (void)0 : __CLIBNS abort(), (__ARM_PROMISE)((e)?1:0))
J__promise(e) assert(e)PD
 




C:\Keil_v5\ARM\ARMCC\Bin\..\include\assert.h


ˆC:\Keil_v5\ARM\ARMCC\Bin\..\include\assert.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]
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__bool_true_false_are_defined 1
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bool _Bool
true 1
false 0PE
 




C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdbool.h


ŒC:\Keil_v5\ARM\ARMCC\Bin\..\include\stdbool.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]
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C:\Keil_v5\ARM\ARMCC\Bin\..\include\stddef.h
string.h



C:\Keil_v5\ARM\ARMCC\Bin\..\include\stddef.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]intunsigned shortlong doubleunsigned intPptrdiff_tŠ
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#__STDINT_DECLS %__CLIBNS
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sINT8_MIN -128
tINT16_MIN -32768
uINT32_MIN (~0x7fffffff)
vINT64_MIN __INT64_C(~0x7fffffffffffffff)
yINT8_MAX 127
zINT16_MAX 32767
{INT32_MAX 2147483647
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UINT8_MAX 255
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UINT16_MAX 65535
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UINT32_MAX 4294967295u
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INT_LEAST8_MIN -128
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INT_LEAST16_MIN -32768
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INT_LEAST32_MIN (~0x7fffffff)
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INT_LEAST64_MIN __INT64_C(~0x7fffffffffffffff)
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INT_LEAST8_MAX 127
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INT_LEAST16_MAX 32767
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INT_LEAST32_MAX 2147483647
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INT_LEAST64_MAX __INT64_C(9223372036854775807)
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UINT_LEAST8_MAX 255
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UINT_LEAST32_MAX 4294967295u
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UINT_LEAST64_MAX __UINT64_C(18446744073709551615)
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C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h


C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]
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FILENAME_MAX 256
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C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h
string.h


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C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]unsigned intunsigned long long)â
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C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdlib.h
stddef.h
string.h


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..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\cmsis_version.h




..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\cmsis_version.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x
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..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\cmsis_armcc.h


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..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\cmsis_armcc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x;É
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..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\C:\Keil_v5\ARM\ARMCC\Bin\..\include\cmsis_compiler.h
stdint.hcmsis_armcc.h




..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\cmsis_compiler.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x
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B__CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)
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APSR_C_Pos 29U
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APSR_V_Pos 28U
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«CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
ãSCB_CPUID_IMPLEMENTER_Pos 24U
äSCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
æSCB_CPUID_VARIANT_Pos 20U
çSCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
éSCB_CPUID_ARCHITECTURE_Pos 16U
êSCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
ìSCB_CPUID_PARTNO_Pos 4U
íSCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
ïSCB_CPUID_REVISION_Pos 0U
ðSCB_CPUID_REVISION_Msk (0xFUL )
óSCB_ICSR_NMIPENDSET_Pos 31U
ôSCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
öSCB_ICSR_PENDSVSET_Pos 28U
÷SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
ùSCB_ICSR_PENDSVCLR_Pos 27U
úSCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
üSCB_ICSR_PENDSTSET_Pos 26U
ýSCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
ÿSCB_ICSR_PENDSTCLR_Pos 25U
€SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
‚SCB_ICSR_ISRPREEMPT_Pos 23U
ƒSCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
…SCB_ICSR_ISRPENDING_Pos 22U
†SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
ˆSCB_ICSR_VECTPENDING_Pos 12U
‰SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
‹SCB_ICSR_VECTACTIVE_Pos 0U
ŒSCB_ICSR_VECTACTIVE_Msk (0x1FFUL )
SCB_AIRCR_VECTKEY_Pos 16U
SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
’SCB_AIRCR_VECTKEYSTAT_Pos 16U
“SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
•SCB_AIRCR_ENDIANESS_Pos 15U
–SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
˜SCB_AIRCR_SYSRESETREQ_Pos 2U
™SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
›SCB_AIRCR_VECTCLRACTIVE_Pos 1U
œSCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
ŸSCB_SCR_SEVONPEND_Pos 4U
 SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
¢SCB_SCR_SLEEPDEEP_Pos 2U
£SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
¥SCB_SCR_SLEEPONEXIT_Pos 1U
¦SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
©SCB_CCR_STKALIGN_Pos 9U
ªSCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
¬SCB_CCR_UNALIGN_TRP_Pos 3U
­SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
°SCB_SHCSR_SVCALLPENDED_Pos 15U
±SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
ÉSysTick_CTRL_COUNTFLAG_Pos 16U
ÊSysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
ÌSysTick_CTRL_CLKSOURCE_Pos 2U
ÍSysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
ÏSysTick_CTRL_TICKINT_Pos 1U
ÐSysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
ÒSysTick_CTRL_ENABLE_Pos 0U
ÓSysTick_CTRL_ENABLE_Msk (1UL )
ÖSysTick_LOAD_RELOAD_Pos 0U
×SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL )
ÚSysTick_VAL_CURRENT_Pos 0U
ÛSysTick_VAL_CURRENT_Msk (0xFFFFFFUL )
ÞSysTick_CALIB_NOREF_Pos 31U
ßSysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
áSysTick_CALIB_SKEW_Pos 30U
âSysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
äSysTick_CALIB_TENMS_Pos 0U
åSysTick_CALIB_TENMS_Msk (0xFFFFFFUL )
_VAL2FLD(field,value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
‰_FLD2VAL(field,value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
–SCS_BASE (0xE000E000UL)
—SysTick_BASE (SCS_BASE + 0x0010UL)
˜NVIC_BASE (SCS_BASE + 0x0100UL)
™SCB_BASE (SCS_BASE + 0x0D00UL)
›SCB ((SCB_Type *) SCB_BASE )
œSysTick ((SysTick_Type *) SysTick_BASE )
NVIC ((NVIC_Type *) NVIC_BASE )
¿NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
ÀNVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
ÁNVIC_EnableIRQ __NVIC_EnableIRQ
ÂNVIC_GetEnableIRQ __NVIC_GetEnableIRQ
ÃNVIC_DisableIRQ __NVIC_DisableIRQ
ÄNVIC_GetPendingIRQ __NVIC_GetPendingIRQ
ÅNVIC_SetPendingIRQ __NVIC_SetPendingIRQ
ÆNVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
ÈNVIC_SetPriority __NVIC_SetPriority
ÉNVIC_GetPriority __NVIC_GetPriority
ÊNVIC_SystemReset __NVIC_SystemReset
ÓNVIC_SetVector __NVIC_SetVector
ÔNVIC_GetVector __NVIC_GetVector
×NVIC_USER_IRQ_OFFSET 16
ÛEXC_RETURN_HANDLER (0xFFFFFFF1UL)
ÜEXC_RETURN_THREAD_MSP (0xFFFFFFF9UL)
ÝEXC_RETURN_THREAD_PSP (0xFFFFFFFDUL)
â_BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
ã_SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
ä_IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
æ__NVIC_SetPriorityGrouping(X) (void)(X)
ç__NVIC_GetPriorityGrouping() (0U)È¿
 




..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\C:\Keil_v5\ARM\ARMCC\Bin\..\include\core_cm0.h
stdint.hcmsis_version.h
cmsis_compiler.h


ð
..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\core_cm0.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x*Ù!_reserved0Y
#!VY
#
!CY
#
!ZY
#

!NY
#
Sìb
wY
PAPSR_TypeY

Ò
*ª!ISRY
#    !_reserved0Y
#S½b~
wY
PIPSR_Typeª

í
*Ø!ISRY
#    !_reserved0Y
#!TY
#
!_reserved1Y
#!VY
#
!CY
#
!ZY
#

!NY
#
SëbÏ
wY
PxPSR_TypeX
…*Â!_reserved0Y
#
!SPSELY
#
!_reserved1Y
#SÕb}wY
PCONTROL_TypeÂ
§*ë øë
ISERï#Y

RESERVED0#©ë
ICER #€
ÁY

RESERVED16#„
Üë
ISPRS#€ôY

RESERVED2i#„ë
ICPR†#€§Y

RESERVED3œ#„ÄY

?RESERVED4¹#€ßë
IPÖ#€tY
PNVIC_Typeê
Æ*‹    (CPUID‘#ICSRë#RESERVED0Y
#AIRCRë#SCRë#CCRë#RESERVED1Y
#òë

SHPi#SHCSRë#$Y
t‹PSCB_Type
à*Û    CTRLë#LOADë#VALë#CALIB‘#PSysTick_Type¦
Æ<•

ï__NVIC_EnableIRQ$ƒIRQn;Ò

‚__NVIC_GetEnableIRQY
$ƒIRQna__resultY

<ø

•__NVIC_DisableIRQ$ƒIRQn;¶
¨__NVIC_GetPendingIRQY
$ƒIRQna__resultY

<ß
»__NVIC_SetPendingIRQ$ƒIRQn<Š
Ê__NVIC_ClearPendingIRQ$ƒIRQn<À
Ü__NVIC_SetPriority$ƒIRQn$Y
priority;ü
ô__NVIC_GetPriorityY
$ƒIRQna__resultY

;±
NVIC_EncodePriorityY
$Y
PriorityGroup$Y
PreemptPriority$Y
SubPrioritya__resultY

\PriorityGroupTmpY
\PreemptPriorityBitsY
\SubPriorityBitsY
<Þ
¨NVIC_DecodePriority$Y
Priority$Y
PriorityGroup$äpPreemptPriority$äpSubPriority\PriorityGroupTmpY
\PreemptPriorityBitsY
\SubPriorityBitsY
"Y
Þ<¨
À__NVIC_SetVector$ƒIRQn$Y
vector\vectorsY
;ð
Ð__NVIC_GetVectorY
$ƒIRQna__resultY

\vectorsY
<Œ
Û"__NVIC_SystemReset;¹
üSCB_GetFPUTypeY
a__resultY

;ò
›SysTick_ConfigY
$Y
ticksa__resultY


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__SYSTEM_PANSERIES_H__ 
__PAN_STRINGIFY(x) #x
PAN_STRINGIFY(s) __PAN_STRINGIFY(s)
__PAN_CONCAT(x,y) x ## y
PAN_CONCAT(x,y) __PAN_CONCAT(x, y)
#__PAN_COND_CODE_1(_flag,_if_1_code,_else_code) __PAN_COND_CODE(_AAAAA ## _flag, _if_1_code, _else_code)
%__PAN_COND_CODE_0(_flag,_if_0_code,_else_code) __PAN_COND_CODE(_BBBBB ## _flag, _if_0_code, _else_code)
'_AAAAA1 _ZZZZZ,
(_BBBBB0 _ZZZZZ,
)__PAN_COND_CODE(one_or_two_args,_if_code,_else_code) __PAN_GET_ARG2_DEBRACKET(one_or_two_args _if_code, _else_code)
-__PAN_GET_ARG2_DEBRACKET(ignore_this,val,__VA_ARGS__...) __PAN_DEBRACKET val
/__PAN_DEBRACKET(__VA_ARGS__...) __VA_ARGS__
@PAN_COND_CODE_1(_flag,_if_1_code,_else_code) __PAN_COND_CODE_1(_flag, _if_1_code, _else_code)
PPAN_COND_CODE_0(_flag,_if_0_code,_else_code) __PAN_COND_CODE_0(_flag, _if_0_code, _else_code)¸®
 




..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\C:\Keil_v5\ARM\ARMCC\Bin\..\include\system_PanSeries.h
stdint.hstdbool.h

”
..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\system_PanSeries.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xfloat
_Bool*º€°:

rsvd0%
#!pmu_vbg_trim:
#
!rsvd1:
#

!pmu_vbg_volt_l:
#
pmu_vbg_volt_h:
#!hp_ldo_trim:
# 
!hp_ldo_volt_l:
# 
hp_ldo_volt_h:
#!!lph_ldo_trim:
#"
!lph_ldo_volt_l:
#"
lph_ldo_volt_h:
##!lpl_ldo_trim:
#$
!lpl_ldo_volt_l:
#$
lpl_ldo_volt_h:
#%!flash_ldo_trim:
#&
!rsvd2:
#&

!flash_ldo_volt_l:
#&
flash_ldo_volt_h:
#'!ana_ldo_trim:
#(
!rffe_ldo_trim:
#(
!fsyn_ldo_trim:
#)
!adc_ldo_trim:
#)
!vco_ldo_trim:
#*
!ipoly_trim:
#*

!rsvd3:
#*

!bod_vref_trim:
#+
!rsvd4:
#+

!bod_vref_volt_l:
#+
bod_vref_volt_h:
#,rsvd5:
#-!xtl_core:
#.
!xth_icore:
#.

!rch_bias:
#.
!dpll_vco_freq_trim:
#.
!dpll_kvco_ctrl:
#/
!dpll_icp_ctrl:
#/
!dpll_icp_bias:
#/

!rsvd6:
#/

!adc_vbg_1v20_trim:
#0
!ptat_temp_trim:
#0
adc_vbg_1v20_voltI
#1rch_trim:
#3rch_freqY
#4!rcl_coarse_trim:
#8
!lph_ldo_vref_trim:
#8

!rsvd7:
#8

rcl_fine_trim:
#9rcl_freqI
#:analog_temp_voltI
#<Ê:

    rsvd_0x3e¿#>analog_0p6v_voltI
#H€:

    rsvd8õ#J!buck_imax_cal_trim:
#T
!rsvd9:
#T
!buck_zero_cal_trim:
#U
!rsvd10:
#U
!buck_out_trim:
#V
!rsvd11:
#V
buck_vout_voltI
#Wadc_vdd_kI
#Yadc_vdd_bÿ#[adc_vbg_kI
#\adc_vbg_b 
#^adc_temp_voltI
#`current_temp_value 
#bbattery_trim:
#dÕ:

rsvd12J#eî:

uidc#lchip_info:
#ucp_version:
#vft_version:
#wcp_pass_flag:
#xft_pass_flag:
#ycp_checksum:
#zft_checksum:
#{•:

user_rw_data
#|´:

mac_addr)#€
xth_xocap_a
#†
xth_xocap_m
#Š
xth_xocap_n
#Ž
xth_xocap_trim:
#’
xtl_xocap_a
#“
xtl_xocap_m
#—
xtl_xocap_n
#›
xtl_xocap_trim:
#Ÿ
øn

adc_vbg_kbï# 
adc_vbat_kI
#¼
adc_vbat_b 
#¾
adc_vbat_dtemp_k 
#À
adc_vbat_dtemp_b 
#Â
adc_temp_k
#Ä
adc_ctrl2Y
#È
adc_extsmptY
#Ì
xth_fix_code1:
#Ð
xth_fix_code2:
#Ñ
xtl_fix_code1:
#Ò
xtl_fix_code2:
#Ó
“:

*rsvd13
#Ô
ft_checksum2:
#ÿ
Rî_otp_struct€×:

ÿ
d8K
mâ
m_v2 
PADC_VBG_KB_T«

XPOTP_STRUCT_T:

qisFtDataValid


)â_adc_vbg_kbadc_vbg_kI
#adc_vbg_b 
#*–#€
ò:

rsvd0ç
#!pmu_vbg_trim:
#
!rsvd1:
#

!pmu_vbg_volt_l:
#
pmu_vbg_volt_h:
#!hp_ldo_trim:
# 
!hp_ldo_volt_l:
# 
hp_ldo_volt_h:
#!!lph_ldo_trim:
#"
!lph_ldo_volt_l:
#"
lph_ldo_volt_h:
##!lpl_ldo_trim:
#$
!lpl_ldo_volt_l:
#$
lpl_ldo_volt_h:
#%!flash_ldo_trim:
#&
!rsvd2:
#&

!flash_ldo_volt_l:
#&
flash_ldo_volt_h:
#'!ana_ldo_trim:
#(
!rffe_ldo_trim:
#(
!fsyn_ldo_trim:
#)
!adc_ldo_trim:
#)
!vco_ldo_trim:
#*
!ipoly_trim:
#*

!rsvd3:
#*

!bod_vref_trim:
#+
!rsvd4:
#+

!bod_vref_volt_l:
#+
bod_vref_volt_h:
#,!adc_vbg_1v17_trim:
#-
!rsvd5:
#-
adc_vbg_1v17_voltI
#.!adc_vbg_1v20_trim:
#0
!rsvd6:
#0
adc_vbg_1v20_voltI
#1rch_trim:
#3rch_freqY
#4!rcl_coarse_trim:
#8
!rsvd7:
#8
rcl_fine_trim:
#9rcl_freqI
#:xth_xocap_a
#<xth_xocap_m
#@xth_xocap_n
#Dxtl_xocap_a
#Hxtl_xocap_m
#Lxtl_xocap_n
#P!buck_imax_cal_trim:
#T
!rsvd8:
#T
!buck_zero_cal_trim:
#U
!rsvd9:
#U
!buck_out_trim:
#V
!rsvd10:
#V
buck_vout_voltI
#Wadc_vdd_kI
#Yadc_vdd_bÿ#[adc_vbg_kI
#\adc_vbg_b 
#^adc_temp_voltI
#`current_temp_value 
#bbattery_trim:
#d!pa_power_calib_trim_6dbm:
#e
!pa_power_calib_trim_0dbm:
#e
¿!:

mac_addr´#fÚ!:

uidÏ#lchip_info:
#ucp_version:
#vft_version:
#wcp_pass_flag:
#xft_pass_flag:
#ycp_checksum:
#zft_checksum:
#{#:

user_rw_datav#| ˜—
isFtDataValid
¾¿À

__PAN_SYS_LOG_H__ 
DBG_ON 0
INFO_ON 1
WARN_ON 1
ERR_ON 1
TEST_ON 1
ASSERT_ON 1
SYS_ABORT() do { } while (1)
!LOG(flags,__VA_ARGS__...) do { if (flags) printf(__VA_ARGS__); } while (0)
'SYS_DBG(fmt,__VA_ARGS__...) LOG(DBG_ON, "[SYS DBG] %s:%s():%d, " fmt, __FILE__, __FUNCTION__, __LINE__, ## __VA_ARGS__)
(SYS_INFO(fmt,__VA_ARGS__...) LOG(INFO_ON, "[SYS INFO] %s:%s():%d, " fmt, __FILE__, __FUNCTION__, __LINE__, ## __VA_ARGS__)
)SYS_WARN(fmt,__VA_ARGS__...) LOG(WARN_ON, "[SYS WARN] %s:%s():%d, " fmt, __FILE__, __FUNCTION__, __LINE__, ## __VA_ARGS__)
*SYS_TEST(__VA_ARGS__...) LOG(TEST_ON, __VA_ARGS__)
,SYS_ERR(fmt,__VA_ARGS__...) do { LOG(ERR_ON, "[SYS ERR] %s:%s():%d, "fmt, __FILE__, __FUNCTION__, __LINE__, ## __VA_ARGS__); if (ERR_ON) SYS_ABORT(); } while (0)
5SYS_ASSERT(expr) ((expr) ? (void)0u : SYS_AssertError((uint8_t*)__FILE__, __LINE__, (uint8_t*)(#expr)))°§
 




..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\C:\Keil_v5\ARM\ARMCC\Bin\..\include\pan_sys_log.h
stdio.hstdint.h



..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_sys_log.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x
ÂÃÄ

 __PAN_SYS_H__ 
 SYS_MFP_TYPE_Msk(bit) (1UL << ((bit) +16))
!SYS_MFP_ALT_Msk(bit) (1UL << ((bit) + 8))
"SYS_MFP_MFP_Msk(bit) (1UL << ((bit) ))
$SYS_MFP_GPIO 0x00000000UL
'SYS_MFP_P00_GPIO 0x00000000UL
(SYS_MFP_P00_SWD_CLK 0x00000001UL
)SYS_MFP_P00_UART1_RX 0x00000100UL
*SYS_MFP_P00_I2C0_SCL 0x00000101UL
+SYS_MFP_P00_SPI0_CLK 0x00010000UL
,SYS_MFP_P00_LL_DBG_14 0x00010001UL
-SYS_MFP_P00_MDM_DBG_11 0x00010100UL
.SYS_MFP_P00_RESERVED 0x00010101UL
/SYS_MFP_P00_Msk 0x00010101UL
1SYS_MFP_P01_GPIO 0x00000000UL
2SYS_MFP_P01_SWD_DAT 0x00000002UL
3SYS_MFP_P01_UART1_TX 0x00000200UL
4SYS_MFP_P01_I2C0_SDA 0x00000202UL
5SYS_MFP_P01_SPI0_CS 0x00020000UL
6SYS_MFP_P01_LL_DBG_15 0x00020002UL
7SYS_MFP_P01_MDM_DBG_12 0x00020200UL
8SYS_MFP_P01_RESERVED 0x00020202UL
9SYS_MFP_P01_Msk 0x00020202UL
;SYS_MFP_P02_GPIO 0x00000000UL
<SYS_MFP_P02_UART0_CTS 0x00000004UL
=SYS_MFP_P02_SPI1_MISO 0x00000400UL
>SYS_MFP_P02_PWM_CH3 0x00000404UL
?SYS_MFP_P02_UART1_CTS 0x00040000UL
@SYS_MFP_P02_LL_DBG_8 0x00040004UL
ASYS_MFP_P02_MDM_DBG_19 0x00040400UL
BSYS_MFP_P02_RESERVED 0x00040404UL
CSYS_MFP_P02_Msk 0x00040404UL
ESYS_MFP_P03_GPIO 0x00000000UL
FSYS_MFP_P03_UART0_CTS 0x00000008UL
GSYS_MFP_P03_SPI0_CS 0x00000800UL
HSYS_MFP_P03_PWM_CH2 0x00000808UL
ISYS_MFP_P03_TIMER0_CNT_OUT 0x00080000UL
JSYS_MFP_P03_LL_DBG_8 0x00080008UL
KSYS_MFP_P03_MDM_DBG_5 0x00080800UL
LSYS_MFP_P03_RESERVED 0x00080808UL
MSYS_MFP_P03_Msk 0x00080808UL
OSYS_MFP_P04_GPIO 0x00000000UL
PSYS_MFP_P04_UART0_RTS 0x00000010UL
QSYS_MFP_P04_SPI0_CLK 0x00001000UL
RSYS_MFP_P04_PWM_CH3 0x00001010UL
SSYS_MFP_P04_TIMER0_EXT 0x00100000UL
TSYS_MFP_P04_LL_DBG_9 0x00100010UL
USYS_MFP_P04_MDM_DBG_6 0x00101000UL
VSYS_MFP_P04_RESERVED 0x00101010UL
WSYS_MFP_P04_Msk 0x00101010UL
YSYS_MFP_P05_GPIO 0x00000000UL
ZSYS_MFP_P05_UART0_TX 0x00000020UL
[SYS_MFP_P05_SPI0_MISO 0x00002000UL
\SYS_MFP_P05_PWM_CH4 0x00002020UL
]SYS_MFP_P05_EXT_STADC 0x00200000UL
^SYS_MFP_P05_LL_DBG_12 0x00200020UL
_SYS_MFP_P05_MDM_DBG_9 0x00202000UL
`SYS_MFP_P05_RESERVED 0x00202020UL
aSYS_MFP_P05_Msk 0x00202020UL
cSYS_MFP_P06_GPIO 0x00000000UL
dSYS_MFP_P06_UART0_RX 0x00000040UL
eSYS_MFP_P06_SPI0_MISO 0x00004000UL
fSYS_MFP_P06_PWM_CH5 0x00004040UL
gSYS_MFP_P06_TIMER1_EXT 0x00400000UL
hSYS_MFP_P06_LL_DBG_13 0x00400040UL
iSYS_MFP_P06_MDM_DBG_3 0x00404000UL
jSYS_MFP_P06_AHB_CLK 0x00404040UL
kSYS_MFP_P06_Msk 0x00404040UL
mSYS_MFP_P07_GPIO 0x00000000UL
nSYS_MFP_P07_UART1_RX 0x00000080UL
oSYS_MFP_P07_I2C0_SCL 0x00008000UL
pSYS_MFP_P07_SPI0_MOSI 0x00008080UL
qSYS_MFP_P07_PWM_CH0 0x00800000UL
rSYS_MFP_P07_LL_DBG_10 0x00800080UL
sSYS_MFP_P07_MDM_DBG_7 0x00808000UL
tSYS_MFP_P07_RESERVED 0x00808080UL
uSYS_MFP_P07_Msk 0x00808080UL
xSYS_MFP_P10_GPIO 0x00000000UL
ySYS_MFP_P10_UART1_TX 0x00000001UL
zSYS_MFP_P10_I2C0_SDA 0x00000100UL
{SYS_MFP_P10_SPI0_MISO 0x00000101UL
|SYS_MFP_P10_PWM_CH5 0x00010000UL
}SYS_MFP_P10_LL_DBG_11 0x00010001UL
~SYS_MFP_P10_MDM_DBG_8 0x00010100UL
SYS_MFP_P10_RESERVED 0x00010101UL
€
SYS_MFP_P10_Msk 0x00010101UL
‚
SYS_MFP_P11_GPIO 0x00000000UL
ƒ
SYS_MFP_P11_UART1_RTS 0x00000002UL
„
SYS_MFP_P11_SPI0_MOSI 0x00000200UL
…
SYS_MFP_P11_PWM_CH7 0x00000202UL
†
SYS_MFP_P11_CLK_32K 0x00020000UL
‡
SYS_MFP_P11_LL_DBG_9 0x00020002UL
ˆ
SYS_MFP_P11_MDM_DBG_0 0x00020200UL
‰
SYS_MFP_P11_UART0_TX 0x00020202UL
Š
SYS_MFP_P11_Msk 0x00020202UL
Œ
SYS_MFP_P12_GPIO 0x00000000UL

SYS_MFP_P12_UART0_RX 0x00000004UL
Ž
SYS_MFP_P12_PWM_CH4 0x00000400UL

SYS_MFP_P12_TIMER0_CNT_OUT 0x00000404UL

SYS_MFP_P12_UART1_TX 0x00040000UL
‘
SYS_MFP_P12_LL_DBG_4 0x00040004UL
’
SYS_MFP_P12_MDM_DBG_17 0X00040400UL
“
SYS_MFP_P12_SPI0_MISO 0x00040404UL
”
SYS_MFP_P12_Msk 0x00040404UL
–
SYS_MFP_P13_GPIO 0x00000000UL
—
SYS_MFP_P13_UART0_RTS 0x00000008UL
˜
SYS_MFP_P13_I2C0_SDA 0x00000800UL
™
SYS_MFP_P13_PWM_CH3 0x00000808UL
š
SYS_MFP_P13_LL_DBG_3 0x00080000UL
›
SYS_MFP_P13_MDM_DBG_16 0x00080008UL
œ
SYS_MFP_P13_SPI1_CS 0x00080800UL

SYS_MFP_P13_SPI0_CS 0x00080808UL
ž
SYS_MFP_P13_Msk 0x00080808UL
 
SYS_MFP_P14_GPIO 0x00000000UL
¡
SYS_MFP_P14_UART0_CTS 0x00000010UL
¢
SYS_MFP_P14_I2C0_SCL 0x00001000UL
£
SYS_MFP_P14_PWM_CH2 0x00001010UL
¤
SYS_MFP_P14_LL_DEBUG_2 0x00100000UL
¥
SYS_MFP_P14_MDM_DBG_15 0x00100010UL
¦
SYS_MFP_P14_SPI0_CLK 0x00101000UL
§
SYS_MFP_P14_RESERVED 0x00101010UL
¨
SYS_MFP_P14_Msk 0x00101010UL
ª
SYS_MFP_P15_GPIO 0x00000000UL
«
SYS_MFP_P15_SPI0_CS 0x00000020UL
¬
SYS_MFP_P15_PWM_CH5 0x00002000UL
­
SYS_MFP_P15_TIMER0_EXT 0x00002020UL
®
SYS_MFP_P15_UART0_RX 0x00200000UL
¯
SYS_MFP_P15_LL_DBG_5 0x00200020UL
°
SYS_MFP_P15_MDM_DBG_18 0x00202000UL
±
SYS_MFP_P15_RESERVED 0x00202020UL
²
SYS_MFP_P15_Msk 0x00202020UL
´
SYS_MFP_P16_GPIO 0x00000000UL
µ
SYS_MFP_P16_UART0_TX 0x00000040UL
¶
SYS_MFP_P16_TIMER2_CNT_OUT 0x00004000UL
·
SYS_MFP_P16_PWM_CH0 0x00004040UL
¸
SYS_MFP_P16_LL_DBG_0 0x00400000UL
¹
SYS_MFP_P16_MDM_DBG_13 0x00400040UL
º
SYS_MFP_P16_SPI1_CLK 0x00404000UL
»
SYS_MFP_P16_I2C0_SCL 0x00404040UL
¼
SYS_MFP_P16_Msk 0x00404040UL
¾
SYS_MFP_P17_GPIO 0x00000000UL
¿
SYS_MFP_P17_UART0_RX 0x00000080UL
À
SYS_MFP_P17_TIMER2_EXT 0x00008000UL
Á
SYS_MFP_P17_PWM_CH1 0x00008080UL
Â
SYS_MFP_P17_LL_DBG_1 0x00800000UL
Ã
SYS_MFP_P17_MDM_DBG_14 0x00800080UL
Ä
SYS_MFP_P17_RCH 0x00808000UL
Å
SYS_MFP_P17_RESERVED 0x00808080UL
Æ
SYS_MFP_P17_Msk 0x00808080UL
É
SYS_MFP_P20_GPIO 0x00000000UL
Ê
SYS_MFP_P20_SPI1_MISO 0x00000001UL
Ë
SYS_MFP_P20_PWM_CH6 0x00000100UL
Ì
SYS_MFP_P20_TADC_CLK 0x00000101UL
Í
SYS_MFP_P20_LL_DBG_6 0x00010000UL
Î
SYS_MFP_P20_MDM_DBG_2 0x00010001UL
Ï
SYS_MFP_P20_XTL_C1_CLK 0x00010100UL
Ð
SYS_MFP_P20_RESERVED 0x00010101UL
Ñ
SYS_MFP_P20_Msk 0x00010101UL
Ó
SYS_MFP_P21_GPIO 0x00000000UL
Ô
SYS_MFP_P21_SPI1_MOSI 0x00000002UL
Õ
SYS_MFP_P21_PWM_CH7 0x00000200UL
Ö
SYS_MFP_P21_TADC_VLD 0x00000202UL
×
SYS_MFP_P21_LL_DBG_7 0x00020000UL
Ø
SYS_MFP_P21_MDM_DBG_1 0x00020002UL
Ù
SYS_MFP_P21_XTL_C2_CLK 0x00020200UL
Ú
SYS_MFP_P21_RESERVED 0x00020202UL
Û
SYS_MFP_P21_Msk 0x00020202UL
Ý
SYS_MFP_P22_GPIO 0x00000000UL
Þ
SYS_MFP_P22_SPI1_CLK 0x00000004UL
ß
SYS_MFP_P22_PWM_CH0 0x00000400UL
à
SYS_MFP_P22_RESERVED 0x00000404UL
á
SYS_MFP_P22_TADC_DATl 0x00040000UL
â
SYS_MFP_P22_MDM_DBG_0 0x00040004UL
ã
SYS_MFP_P22_SPI0_MOSI 0x00040400UL
ä
SYS_MFP_P22_RESERVED1 0x00040404UL
å
SYS_MFP_P22_Msk 0x00040404UL
ç
SYS_MFP_P23_GPIO 0x00000000UL
è
SYS_MFP_P23_SPI1_CS 0x00000008UL
é
SYS_MFP_P23_PWM_CH1 0x00000800UL
ê
SYS_MFP_P23_DPLL_DIV8 0x00000808UL
ë
SYS_MFP_P23_TADC_DATH 0x00080000UL
ì
SYS_MFP_P23_MDM_DBG_10 0x00080008UL
í
SYS_MFP_P23_I2C0_SCL 0x00080800UL
î
SYS_MFP_P23_RESERVED 0x00080808UL
ï
SYS_MFP_P23_Msk 0x00080808UL
ñ
SYS_MFP_P24_GPIO 0x00000000UL
ò
SYS_MFP_P24_SPI1_MISO 0x00000010UL
ó
SYS_MFP_P24_UART1_RX 0x00001000UL
ô
SYS_MFP_P24_PWM_CH2 0x00001010UL
õ
SYS_MFP_P24_TIMER1_CNT_OUT 0x00100000UL
ö
SYS_MFP_P24_MDM_DBG_4 0x00100010UL
÷
SYS_MFP_P24_RESERVED 0x00101000UL
ø
SYS_MFP_P24_RESERVED1 0x00101010UL
ù
SYS_MFP_P24_Msk 0x00101010UL
û
SYS_MFP_P25_GPIO 0x00000000UL
ü
SYS_MFP_P25_SPI1_MOSI 0x00000020UL
ý
SYS_MFP_P25_UART1_TX 0x00002000UL
þ
SYS_MFP_P25_PWM_CH3 0x00002020UL
ÿ
SYS_MFP_P25_MDM_DBG_5 0x00200000UL
€SYS_MFP_P25_RESERVED 0x00200020UL
SYS_MFP_P25_I2C0_SDA 0x00202000UL
‚SYS_MFP_P25_RESERVED1 0x00202020UL
ƒSYS_MFP_P25_Msk 0x00202020UL
…SYS_MFP_P26_GPIO 0x00000000UL
†SYS_MFP_P26_UART1_RTS 0x00000040UL
‡SYS_MFP_P26_PWM_CH4 0x00004000UL
ˆSYS_MFP_P26_SPI1_CS 0x00004040UL
‰SYS_MFP_P26_MDM_DBG_4 0x00400000UL
ŠSYS_MFP_P26_MDM_DBG_10 0x00400040UL
‹SYS_MFP_P26_RESERVED 0x00404000UL
ŒSYS_MFP_P26_RESERVED1 0x00404040UL
SYS_MFP_P26_Msk 0x00404040UL
SYS_MFP_P27_GPIO 0x00000000UL
SYS_MFP_P27_UART1_CTS 0x00000080UL
‘SYS_MFP_P27_PWM_CH5 0x00008000UL
’SYS_MFP_P27_SPI1_CLK 0x00008080UL
“SYS_MFP_P27_RESERVED 0x00800000UL
”SYS_MFP_P27_MDM_DBG_20 0x00800080UL
•SYS_MFP_P27_XTH 0x00808000UL
–SYS_MFP_P27_RESERVED1 0x00808080UL
—SYS_MFP_P27_Msk 0x00808080UL
šSYS_MFP_P30_GPIO 0x00000000UL
›SYS_MFP_P30_UART1_RX 0x00000001UL
œSYS_MFP_P30_PWM_CH6 0x00000100UL
SYS_MFP_P30_SPI1_MISO 0x00000101UL
žSYS_MFP_P30_MDM_DBG_10 0x00010000UL
ŸSYS_MFP_P30_RESERVED 0x00010001UL
 SYS_MFP_P30_RESERVED1 0x00010100UL
¡SYS_MFP_P30_RESERVED2 0x00010101UL
¢SYS_MFP_P30_Msk 0x00010101UL
¤SYS_MFP_P31_GPIO 0x00000000UL
¥SYS_MFP_P31_UART1_TX 0x00000002UL
¦SYS_MFP_P31_PWM_CH7 0x00000200UL
§SYS_MFP_P31_SPI1_MOSI 0x00000202UL
¨SYS_MFP_P31_RESERVED 0x00020000UL
©SYS_MFP_P31_RESERVED1 0x00020002UL
ªSYS_MFP_P31_RESERVED2 0x00020200UL
«SYS_MFP_P31_RESERVED3 0x00020202UL
¬SYS_MFP_P31_Msk 0x00020202UL
¶SYS_SET_MFP(Port,Bit,Func) (SYS->Port ## _MFP = (SYS->Port ## _MFP & ~SYS_MFP_ ## Port ## Bit ## _Msk) | SYS_MFP_ ## Port ## Bit ## _ ## Func)pg
 




..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_sys.h


0

..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_sys.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x<œ
ÃSYS_UnlockReg<±
ÔSYS_LockReg
ÆÇÈ

__PAN_CLK_H__ 
CLK_APB1_WDTSEL_MILLI_PULSE (0x00010000UL)
CLK_APB1_WDTSEL_RCL32K (0x00000000UL)
CLK_APB1_WWDTSEL_MILLI_PULSE (0x00000000UL)
 CLK_APB1_WWDTSEL_RCL32K (0x00020000UL)
"CLK_APB1_TMR0SEL_APB1CLK (0x00000000UL)
#CLK_APB1_TMR0SEL_RCL32K (0x00040000UL)
$CLK_APB1_TMR0SEL_TM0 (0x00080000UL)
&CLK_APB2_TMR1SEL_APB2CLK (0x00000000UL)
'CLK_APB2_TMR1SEL_RCL32K (0x00000100UL)
(CLK_APB2_TMR1SEL_TM1 (0x00000200UL)
*CLK_APB2_TMR2SEL_APB2CLK (0x00000000UL)
+CLK_APB2_TMR2SEL_RCL32K (0x00000400UL)
,CLK_APB2_TMR2SEL_TM2 (0x00000800UL)
.CLK_APB1_PWM_CH01_SEL_APB (0x00000000UL)
/CLK_APB1_PWM_CH01_SEL_CLK32K (0x00100000UL)
0CLK_APB1_PWM_CH23_SEL_APB (0x00000000UL)
1CLK_APB1_PWM_CH23_SEL_CLK32K (0x00200000UL)
2CLK_APB1_PWM_CH45_SEL_APB (0x00000000UL)
3CLK_APB1_PWM_CH45_SEL_CLK32K (0x00400000UL)
4CLK_APB1_PWM_CH67_SEL_APB (0x00000000UL)
5CLK_APB1_PWM_CH67_SEL_CLK32K (0x00800000UL)
;FREQ_1MHZ (1000000)
<FREQ_8MHZ (8000000)
=FREQ_16MHZ (16000000)
>FREQ_25MHZ (25000000)
?FREQ_32MHZ (32000000)
@FREQ_48MHZ (48000000)
AFREQ_64MHZ (64000000)
BFREQ_96MHZ (96000000)
CFREQ_50MHZ (50000000)
DFREQ_72MHZ (72000000)
EFREQ_100MHZ (100000000)
LCLK_SYS_SRCSEL_RCH ((uint32_t)0x00000000)
MCLK_SYS_SRCSEL_XTH ((uint32_t)0x00000100)
NCLK_SYS_SRCSEL_DPLL ((uint32_t)0x00000200)
UCLK_DPLL_REF_CLKSEL_RCH ((uint32_t)0x00000000)
VCLK_DPLL_REF_CLKSEL_XTH ((uint32_t)0x00000008)
WCLK_DPLL_OUT_48M ((uint32_t)0x00000000)
XCLK_DPLL_OUT_64M ((uint32_t)0x00000004)
`CLK_APB1Periph_I2C0 ((uint32_t)0x00000001)
aCLK_APB1Periph_SPI0 ((uint32_t)0x00000002)
bCLK_APB1Periph_UART0 ((uint32_t)0x00000008)
cCLK_APB1Periph_PWM0_CH01 ((uint32_t)0x00000010)
dCLK_APB1Periph_PWM0_CH23 ((uint32_t)0x00000020)
eCLK_APB1Periph_PWM0_CH45 ((uint32_t)0x00000040)
fCLK_APB1Periph_PWM0_CH67 ((uint32_t)0x00000080)
gCLK_APB1Periph_PWM0_EN ((uint32_t)0x00000100)
hCLK_APB1Periph_ADC ((uint32_t)0x00000200)
iCLK_APB1Periph_WDT ((uint32_t)0x00000400)
jCLK_APB1Periph_WWDT ((uint32_t)0x00000800)
kCLK_APB1Periph_TMR0 ((uint32_t)0x00001000)
lCLK_APB1Periph_MILI_CLK ((uint32_t)0x00002000)
mCLK_APB1Periph_All ((uint32_t)0x00003ffb)
uCLK_APB2Periph_SPI1 ((uint32_t)0x00000002)
vCLK_APB2Periph_UART1 ((uint32_t)0x00000008)
wCLK_APB2Periph_TMR1 ((uint32_t)0x00000010)
xCLK_APB2Periph_TMR2 ((uint32_t)0x00000020)
yCLK_APB2Periph_All ((uint32_t)0x0000003a)
€
CLK_AHBPeriph_DMAC ((uint32_t)0x00000001)

CLK_AHBPeriph_GPIO ((uint32_t)0x00000002)
‚
CLK_AHBPeriph_SYSTICK ((uint32_t)0x00000004)
ƒ
CLK_AHBPeriph_APB1 ((uint32_t)0x00000008)
„
CLK_AHBPeriph_APB2 ((uint32_t)0x00000010)
…
CLK_AHBPeriph_AHB ((uint32_t)0x00000020)
†
CLK_AHBPeriph_BLE_32M ((uint32_t)0x00000040)
‡
CLK_AHBPeriph_BLE_32K ((uint32_t)0x00000080)
‰
CLK_AHBPeriph_ROM ((uint32_t)0x00000400)
Š
CLK_AHBPeriph_EFUSE ((uint32_t)0x00000800)
‹
CLK_AHBPeriph_USB_AHB ((uint32_t)0x00002000)
Œ
CLK_AHBPeriph_USB_48M ((uint32_t)0x00004000)

CLK_AHBPeriph_All ((uint32_t)0x00006CFF)
“
CLK_DivideSource_Ahb (1)
”
CLK_DivideSource_Apb1 (2)
•
CLK_DivideSource_Apb2 (4)
›
CLK_RCL_SELECT (0)
œ
CLK_RCH_SELECT (1)

CLK_XTL_SELECT (2)
ž
CLK_XTH_SELECT (3)
Ÿ
CLK_DPLL_SELECT (4)
¢
CLK_STABLE_STATUS_Pos (24)
£
CLK_STABLE_STATUS_Msk (0x1ul << CLK_STABLE_STATUS_Pos)
¥
CLKTRIM_CALC_CLK_SEL_32K (0)
¦
CLKTRIM_CALC_CLK_SEL_32M (1)
¨
CLKTRIM_QDEC_CLK_SEL_APB (0)
©
CLKTRIM_QDEC_CLK_SEL_32K (1)
«
CLKTRIM_KSCAN_CLK_SEL_APB (0)
¬
CLKTRIM_KSCAN_CLK_SEL_32K (1)
³
DMA_RST ((0x0<<24) | CLK_IPRST0_DMARST_Pos )
´
LL_RST ((0x0<<24) | CLK_IPRST0_RFRST_Pos )
µ
EFUSE_RST ((0x0<<24) | CLK_IPRST0_EFUSERST_Pos )
¶
USB_RST ((0x0<<24) | CLK_IPRST0_USBRST_Pos )
·
MDMSTB_RST ((0x0<<24) | CLK_IPRST0_MDMSTDBYRST_Pos )
¸
MDM_RST ((0x0<<24) | CLK_IPRST0_MDMRST_Pos )
¹
I2C0_RST ((0x4<<24) | CLK_IPRST1_I2C0RST_Pos )
º
SPI0_RST ((0x4<<24) | CLK_IPRST1_SPI0RST_Pos )
»
SPI1_RST ((0x4<<24) | CLK_IPRST1_SPI1RST_Pos )
¼
UART0_RST ((0x4<<24) | CLK_IPRST1_UART0RST_Pos )
½
UART1_RST ((0x4<<24) | CLK_IPRST1_UART1RST_Pos )
¾
PWM0_RST ((0x4<<24) | CLK_IPRST1_PWM0RST_Pos )
¿
ADC_RST ((0x4<<24) | CLK_IPRST1_ADCRST_Pos )
À
WDT_RST ((0x4<<24) | CLK_IPRST1_WDTRST_Pos )
Á
WWDT_RST ((0x4<<24) | CLK_IPRST1_WWDTRST_Pos )
Â
TMR0_RST ((0x4<<24) | CLK_IPRST1_TMR0RST_Pos )
Ã
TMR1_RST ((0x4<<24) | CLK_IPRST1_TMR1RST_Pos )
Ä
TMR2_RST ((0x4<<24) | CLK_IPRST1_TMR2RST_Pos )
Å
GPIO_RST ((0x4<<24) | CLK_IPRST1_GPIORST_Pos )
Æ
CLKTRIM_RST ((0x4<<24) | CLK_IPRST1_TRIMRST_Pos )
Î
CLK_BODCTL_BOD_INT_EN (0UL<<CLK_BODCTL_BODRSTEN_Pos_3v)
Ï
CLK_BODCTL_BOD_RST_EN (1UL<<CLK_BODCTL_BODRSTEN_Pos_3v)
Ð
CLK_BODCTL_BODSEL_1_75V (0UL<<CLK_BODCTL_BODSEL_Pos_3v)
Ñ
CLK_BODCTL_BODSEL_1_95V (1UL<<CLK_BODCTL_BODSEL_Pos_3v)
Ò
CLK_BODCTL_BODSEL_2_15V (2UL<<CLK_BODCTL_BODSEL_Pos_3v)
Ó
CLK_BODCTL_BODSEL_2_35V (3UL<<CLK_BODCTL_BODSEL_Pos_3v)
Ô
CLK_BODCTL_BODSEL_2_55V (4UL<<CLK_BODCTL_BODSEL_Pos_3v)
Õ
CLK_BODCTL_BODSEL_2_75V (5UL<<CLK_BODCTL_BODSEL_Pos_3v)
Ö
CLK_BODCTL_BODSEL_2_95V (6UL<<CLK_BODCTL_BODSEL_Pos_3v)
ß
CLK_BLDBCTL_BODDBSEL_2POW0 0x00000001UL
à
CLK_BLDBCTL_BODDBSEL_2POW1 0x00000002UL
á
CLK_BLDBCTL_BODDBSEL_2POW2 0x00000004UL
â
CLK_BLDBCTL_BODDBSEL_2POW3 0x00000008UL
ã
CLK_BLDBCTL_BODDBSEL_2POW4 0x00000010UL
ä
CLK_BLDBCTL_BODDBSEL_2POW5 0x00000020UL
ì
CLK_BLDBCTL_LVRDBSEL_2POW0 0x00000100UL
í
CLK_BLDBCTL_LVRDBSEL_2POW1 0x00000200UL
î
CLK_BLDBCTL_LVRDBSEL_2POW2 0x00000400UL
ï
CLK_BLDBCTL_LVRDBSEL_2POW3 0x00000800UL
ð
CLK_BLDBCTL_LVRDBSEL_2POW4 0x00001000UL
ñ
CLK_BLDBCTL_LVRDBSEL_2POW5 0x00002000ULpg
 




..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_clk.h



..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_clk.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x
CLK_FLASH_CLKDIV_1CLK_FLASH_CLKDIV_2
CLK_FLASH_CLKDIV_4CLK_FLASH_CLKDIV_8CLK_FLASH_CLKDIV_16CLK_FLASH_CLKDIV_30<®
ø
CLK_XthStartupConfig<Ö
„CLK_HCLKConfig$Y
u32ClkDiv<ÿ
CLK_PCLK1Config$Y
u32ClkDiv<¨
œCLK_PCLK2Config$Y
u32ClkDiv<Ò
¾CLK_SetDpllOutputFreq$Y
freq<ü
áCLK_EnableClkTrim$åNewState<¤
ïCLK_SelectClkTrimSrc$Y
src<Ù
ûCLK_SetClkTrimCalClkDiv$I
div\regY
<‰
•CLK_SetFlashClkDiv$:
div\regY

ÊËÌÍ

 __PAN_ADC_H__ 
ADC_INPUTRANGE_HIGH (1UL)
ADC_INPUTRANGE_LOW (0UL)
ADC_CH8_EXT (0UL)
ADC_CH8_BGP (ADC_CHEN_CH8SEL_Msk)
 ADC_CMP0_LESS_THAN (0UL << ADC_CMP0_CMPCOND_Pos)
!ADC_CMP1_LESS_THAN (0UL << ADC_CMP1_CMPCOND_Pos)
"ADC_CMP0_GREATER_OR_EQUAL_TO (1ul << ADC_CMP0_CMPCOND_Pos)
#ADC_CMP1_GREATER_OR_EQUAL_TO (1ul << ADC_CMP1_CMPCOND_Pos)
$ADC_TRIGGER_BY_EXT_PIN (0UL << ADC_CTL_HWTRGSEL_Pos)
%ADC_TRIGGER_BY_PWM (ADC_CTL_HWTRGSEL_Msk)
&ADC_FALLING_EDGE_TRIGGER (0UL << ADC_CTL_HWTRGCOND_Pos)
'ADC_RISING_EDGE_TRIGGER (ADC_CTL_HWTRGCOND_Msk)
,ADC_ADIF_INT (ADC_STATUS_ADIF_Msk)
-ADC_CMP0_INT (ADC_STATUS_ADCMPIF0_Msk)
.ADC_CMP1_INT (ADC_STATUS_ADCMPIF1_Msk)
/ADC_FIFO_FULL_INT (ADC_STATUS_INTFLG_FULL_Msk)
0ADC_FIFO_EMPTY_INT (ADC_STATUS_INTFLG_EMPTY_Msk)
1ADC_FIFO_OVER_INT (ADC_STATUS_INTFLG_OVER_Msk)
2ADC_FIFO_HALF_INT (ADC_STATUS_INTFLG_HALF_Msk)
8ADC_SAMPLE_CLOCK_0 (0UL)
9ADC_SAMPLE_CLOCK_1 (1UL)
:ADC_SAMPLE_CLOCK_2 (2UL)
;ADC_SAMPLE_CLOCK_4 (3UL)
<ADC_SAMPLE_CLOCK_8 (4UL)
=ADC_SAMPLE_CLOCK_16 (5UL)
>ADC_SAMPLE_CLOCK_32 (6UL)
?ADC_SAMPLE_CLOCK_64 (7UL)
@ADC_SAMPLE_CLOCK_128 (8UL)
AADC_SAMPLE_CLOCK_256 (9UL)
BADC_SAMPLE_CLOCK_512 (10UL)
CADC_SAMPLE_CLOCK_1024 (11UL)
DADC_SEQMODE_TYPE_23SHUNT (0UL)
EADC_SEQMODE_TYPE_1SHUNT (1UL)
FADC_SEQMODE_MODESELECT_CH01 (0UL)
GADC_SEQMODE_MODESELECT_CH12 (1UL)
HADC_SEQMODE_MODESELECT_CH02 (2UL)
IADC_SEQMODE_MODESELECT_ONE (3UL)
JADC_SEQMODE_PWM0_RISING (0UL)
KADC_SEQMODE_PWM0_CENTER (1UL)
LADC_SEQMODE_PWM0_FALLING (2UL)
MADC_SEQMODE_PWM0_PERIOD (3UL)
NADC_SEQMODE_PWM2_RISING (4UL)
OADC_SEQMODE_PWM2_CENTER (5UL)
PADC_SEQMODE_PWM2_FALLING (6UL)
QADC_SEQMODE_PWM2_PERIOD (7UL)
RADC_SEQMODE_PWM4_RISING (8UL)
SADC_SEQMODE_PWM4_CENTER (9UL)
TADC_SEQMODE_PWM4_FALLING (10UL)
UADC_SEQMODE_PWM4_PERIOD (11UL)
VADC_SEQMODE_PWM6_RISING (12UL)
WADC_SEQMODE_PWM6_CENTER (13UL)
XADC_SEQMODE_PWM6_FALLING (14UL)
YADC_SEQMODE_PWM6_PERIOD (15UL)
\ADC_COMPARATOR_0 (0)
]ADC_COMPARATOR_1 (1)
_ADC_FIFO_TRIG_LEVEL_HALF (0)
`ADC_FIFO_TRIG_LEVEL_FULL (1)pg
 




..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_adc.h


ì
..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_adc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xfloat
_BoolPADC_OPT_TZ
vqm_adc_opt


qglobal_calc_vbat_mvY


;‘
‚
ADC_GetConversionDataY
$‘
ADCxa__resultY

"Ï;×
”
ADC_StatusFlag
$‘
ADCx$Y
IntMaska__result

<‹
¦
ADC_ClearStatusFlag$‘
ADCx$Y
IntMask<Æ
¹
ADC_IntMask$‘
ADCx$Y
IntMask$åNewState;ˆ
Ì
ADC_IsIntOccured
$‘
ADCx$Y
IntMaska__result

<¹
ß
ADC_ClearIntFlag$‘
ADCx$Y
IntMask;ç
ë
ADC_IsBusy
$‘
ADCxa__result

;œ
÷
ADC_IsDataOverrun
$‘
ADCxa__result

;Ï
ƒADC_IsDataValid
$‘
ADCxa__result

<ï
ADC_PowerDown$‘
ADCx<
—ADC_PowerOn$‘
ADCx<¹
¡ADC_SequentialModeDisable$‘
ADCx<í
¬ADC_Trigger2Select$‘
ADCx$åNewState<“
¶ADC_DisableCompare0$‘
ADCx<¹
ÀADC_DisableCompare1$‘
ADCx<Ü
ÊADC_StartConvert$‘
ADCx<þ
ÓADC_StopConvert$‘
ADCx<£    
ÞADC_TestModeEnable$‘
ADCx<É    
èADC_TestModeDisable$‘
ADCx<ü    
óADC_DmaModeEnable$‘
ADCx$åNewState<°

ÿADC_SetClockDivider$‘
ADCx$Y
Divider<Ø

ADC_Open$‘
ADCx$Y
ChMask<
˜ADC_SelInputRange$‘
ADCx$Y
EnableHigh<»
¢ADC_TriggerDelay$‘
ADCx$Y
Data<õ
¸ADC_SetExtraSampleTime$‘
ADCx$Y
SampleTime;®
ÃADC_IsOneChConvertEnd
$‘
ADCxa__result

<Ý
ÏADC_ClearByHw$‘
ADCx$åNewState<Ž 
ÛADC_LeftShiftEn$‘
ADCx$åNewState<Â 
çADC_SubtractBiasEn$‘
ADCx$åNewState<ó 
óADC_SetBiasData$‘
ADCx$Y
BiasData<¦
‚ADC_SetFifoTrigLevel$‘
ADCx$:
Level<Ú
ADC_SeqModeOneChEn$‘
ADCx$åNewState*ì@chip_info:
#ft_version:
#
adc_vdd_bÿ#adc_vdd_kI
#adc_vbg_kI
#adc_vbg_b 
#adc_temp_voltI
#
current_temp_value 
#!adc_vbg_1v20_trim:
#
!rsvd_0x30:
#
Ãn

adc_vbg_kb8#adc_vbat_kI
#,adc_vbat_b 
#.adc_vbat_dtemp_k 
#0adc_vbat_dtemp_b 
#2adc_temp_k
#4adc_ctrl2Y
#8adc_extsmptY
#<4ð(
m_adc_opt8
global_calc_vbat_mv
ÏÐÑÒ

 __PAN_FMC_H__ 
M32(adr) (*((vu32 *) (adr)))
CMD_ERASE_PAGE (0X81)
CMD_ERASE_SECTOR (0X20)
 CMD_ERASE_32K (0X52)
!CMD_ERASE_64K (0Xd8)
"CMD_ERASE_CHIP (0xc7)
(CMD_READ_STATUS_L (0x05)
)CMD_READ_STATUS_H (0x35)
*CMD_WRITE_STATUS (0x01)
0OPS_WR_STU_REG_NOR (0x00)
1OPS_WR_STU_REG_ALL (0x01)
7CMD_FAST_READ (0x0b)
8CMD_NORM_READ (0x03)
9CMD_DREAD (0x3B)
:CMD_2READ (0xBB)
;CMD_QREAD (0x6B)
<CMD_4READ (0xEB)
BCMD_BURST_READ (0x77)
CBURST_READ_MODE_8 (0x00)
DBURST_READ_MODE_16 (0x01)
EBURST_READ_MODE_32 (0x02)
FBURST_READ_MODE_64 (0x03)
JCMD_TRIG (0x01)
KCMD_WRITE_ENABLE (0x06)
LCMD_WRITE_DISABLE (0x04)
QFLASH_X1_MODE 0
RFLASH_X2_MODE 1
SFLASH_X4_MODE 2
VQUAD_ENABLE_Pos (9)
WQUAD_ENABLE_Msk (0x1ul << QUAD_ENABLE_Pos)
XWrite_Enable_Latch_Pos (1)
YWrite_Enable_Latch_Msk (0x1ul << Write_Enable_Latch_Pos)
ZWrite_In_Process_Pos (0)
[Write_In_Process_Msk (0x1ul << Write_In_Process_Pos)
\Long_Time_Op_Pos (17)
^PAGE_SIZE (256)
_SECTOR_SIZE (4096)pg
 




..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_fmc.h


\
..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_fmc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x
_Bool;Â
 
FMC_IsBusyWorking
$*fmca__result

*úmemory_type_id:
#memory_density_id:
#
S•‰:


d~
B
)Ü_flash_idsmanufacturer_id:
#z
#
Ð:

uidÅ
#PFLASH_IDS_T•

tqflash_idsÜ


<ª
FMC_EnterDeepPowerDownMode$*fmc"<Û

FMC_ExitDeepPowerDownMode$*fmc`ï
flash_ids
ÔÕÖ

__PAN_DMAC_H__ 
DMAC_CHANNEL_NUMBER 2
DMA_INVLID_CHANNEL (~0ul)
$DMAC_TransferType_Mem2Mem (0)
%DMAC_TransferType_Mem2Per (1)
&DMAC_TransferType_Per2Mem (2)
'DMAC_TransferType_Per2Per (3)
+DMAC_FlowControl_DMA (0)
,DMAC_FlowControl_Peripheral (1)
2DMAC_BurstLen_1 (0)
3DMAC_BurstLen_4 (1)
4DMAC_BurstLen_8 (2)
5DMAC_BurstLen_16 (3)
6DMAC_BurstLen_32 (4)
7DMAC_BurstLen_64 (5)
8DMAC_BurstLen_128 (6)
9DMAC_BurstLen_256 (7)
@DMAC_AddrChange_Increment (0)
ADMAC_AddrChange_Decrement (1)
BDMAC_AddrChange_NoChange (2)
IDMAC_DataWidth_8 (0)
JDMAC_DataWidth_16 (1)
KDMAC_DataWidth_32 (2)
LDMAC_DataWidth_64 (3)
MDMAC_DataWidth_128 (4)
NDMAC_DataWidth_256 (5)
UDMAC_Peripheral_I2C0_Tx 0
VDMAC_Peripheral_I2C0_Rx 1
WDMAC_Peripheral_SPI0_Tx 2
XDMAC_Peripheral_SPI0_Rx 3
YDMAC_Peripheral_UART0_Tx 4
ZDMAC_Peripheral_UART0_Rx 5
]DMAC_Peripheral_SPI1_Tx 8
^DMAC_Peripheral_SPI1_Rx 9
_DMAC_Peripheral_UART1_Tx 10
`DMAC_Peripheral_UART1_Rx 11
aDMAC_Peripheral_ADC 12
bDMAC_Peripheral_USB_Rx 15
cDMAC_Peripheral_USB_Tx 14
hDMAC_HandshakePolarity_Low (1)
iDMAC_HandshakePolarity_High (0)
pDMAC_Handshake_Default (1)
qDMAC_Handshake_Software (1)
rDMAC_Handshake_Hardware (0)
uDMAC_LockLevel_Tfr_Complete (0)
vDMAC_LockLevel_Block_Complete (1)
wDMAC_LockLevel_Transaction_Complete (2)
|DMAC_ChannelPriority_0 (0)
}DMAC_ChannelPriority_1 (1)
~DMAC_ChannelPriority_2 (2)
DMAC_ChannelPriority_3 (3)
€
DMAC_ChannelPriority_4 (4)

DMAC_ChannelPriority_5 (5)
‚
DMAC_ChannelPriority_6 (6)
ƒ
DMAC_ChannelPriority_7 (7)
‡
DMAC_CHANNELALL_MASK (~((~0ul)<<DMAC_CHANNEL_NUMBER))
Œ
DMAC_FLAG_INDEX_TFR (0<<1)

DMAC_FLAG_INDEX_BLK (1<<1)
Ž
DMAC_FLAG_INDEX_SRCTFR (2<<1)

DMAC_FLAG_INDEX_DSTTFR (3<<1)

DMAC_FLAG_INDEX_ERR (4<<1)
˜
DMAC_FLAG_MASK_TFR (1ul<<(DMAC_FLAG_INDEX_TFR >>1))
™
DMAC_FLAG_MASK_BLK (1ul<<(DMAC_FLAG_INDEX_BLK >>1))
š
DMAC_FLAG_MASK_SRCTFR (1ul<<(DMAC_FLAG_INDEX_SRCTFR>>1))
›
DMAC_FLAG_MASK_DSTTFR (1ul<<(DMAC_FLAG_INDEX_DSTTFR>>1))
œ
DMAC_FLAG_MASK_ERR (1ul<<(DMAC_FLAG_INDEX_ERR >>1))

DMAC_FLAG_MASK_ALL (0x1Ful)
ŸDMAC_ChannelMask(idx) (1ul<<(idx))th
 




..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_dmac.h



..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_dmac.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x)ã__DMAC_ChannelConfigTypeDefCTL_LY
#CTL_HY
#CFG_LY
#CFG_HY
#P__DMAC_ChannelConfigTypeDef

¯
)·
DMAC_ChannelConfigTypeDef!IntEnableY
#
!DataWidthDstY
#!DataWidthSrcY
#!AddrChangeDstY
#!AddrChangeSrcY
#!BurstLenDstY
#!BurstLenSrcY
#!GatherEnSrcY
#
!ScatterEnDstY
#
 !__Rev0Y
#
!TransferTypeY
#
!FlowControlY
#
    !__Rev1Y
#    !BlockSizeY
#!DoneY
#
!__Rev3Y
#!__Rev4Y
#!ChannelPriorityY
#!ChannelSuspendY
#
!FifoEmptyY
#
!HandshakeDstY
#
!HandshakeSrcY
#
!LockBusY
#
!LockChannelY
#
!LockBusLevelY
#!LockChannelLevelY
#!HandshakePolarityDstY
#
 !HandshakePolaritySrcY
#
!__Rev6Y
#
!AutoReloadSrcY
#

!AutoReloadDstY
#
!FlowControlModeY
#
!FifoModeY
#
!ProtectControlY
#!__Rev7Y
#!PeripheralSrcY
#!PeripheralDstY
#!__Rev8Y
#PDMAC_ChannelConfigTypeDef‡

;Ÿ
–DMAC_IsChannelValidY
$Ÿdma$Y
ChIdxa__resultY

"S;ï
­DMAC_CombinedIntStatusY
$Ÿdma$Y
FlgMska__resultY

;¾
¾DMAC_StatusFlagY
$Ÿdma$Y
ChIdx$Y
FlgIdxa__resultY

;Š 
ÊDMAC_IntFlagY
$Ÿdma$Y
ChIdx$Y
FlgIdxa__resultY

;Ù 
ÏDMAC_IntFlagMskY
$Ÿdma$Y
ChIdx$Y
FlgIdxa__resultY

<“
ÛDMAC_ClrIntFlag$Ÿdma$Y
ChIdx$Y
FlgIdx
ØÙÚ

 __PAN_GPIO_H__ 
GPIO_PIN_MAX 8
xGPIO_PIN_ADDR(port,pin) (*((volatile uint32_t *)((GPIOBIT0_BASE+(0x20*(port))) + ((pin)<<2))))
yP00 GPIO_PIN_ADDR(0, 0)
zP01 GPIO_PIN_ADDR(0, 1)
{P02 GPIO_PIN_ADDR(0, 2)
|P03 GPIO_PIN_ADDR(0, 3)
}P04 GPIO_PIN_ADDR(0, 4)
~P05 GPIO_PIN_ADDR(0, 5)
P06 GPIO_PIN_ADDR(0, 6)
€
P07 GPIO_PIN_ADDR(0, 7)

P10 GPIO_PIN_ADDR(1, 0)
‚
P11 GPIO_PIN_ADDR(1, 1)
ƒ
P12 GPIO_PIN_ADDR(1, 2)
„
P13 GPIO_PIN_ADDR(1, 3)
…
P14 GPIO_PIN_ADDR(1, 4)
†
P15 GPIO_PIN_ADDR(1, 5)
‡
P16 GPIO_PIN_ADDR(1, 6)
ˆ
P17 GPIO_PIN_ADDR(1, 7)
‰
P20 GPIO_PIN_ADDR(2, 0)
Š
P21 GPIO_PIN_ADDR(2, 1)
‹
P22 GPIO_PIN_ADDR(2, 2)
Œ
P23 GPIO_PIN_ADDR(2, 3)

P24 GPIO_PIN_ADDR(2, 4)
Ž
P25 GPIO_PIN_ADDR(2, 5)

P26 GPIO_PIN_ADDR(2, 6)

P27 GPIO_PIN_ADDR(2, 7)
‘
P30 GPIO_PIN_ADDR(3, 0)
’
P31 GPIO_PIN_ADDR(3, 1)
óGPIO_EnableEINT0 GPIO_EnableInt
€GPIO_DisableEINT0 GPIO_DisableInt
GPIO_EnableEINT1 GPIO_EnableInt
œGPIO_DisableEINT1 GPIO_DisableInt¤™
 




..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\C:\Keil_v5\ARM\ARMCC\Bin\..\include\pan_gpio.h
stdint.h

 
..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_gpio.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x
_Bool;Ó
ëGPIO_GetIntFlag
$9gpio$Y
u32PinMaska__result

<‡
‚GPIO_SetDebounceTime$clksrc$ðclksel;½
GPIO_GetInDataY
$9gpioa__resultY

<ê
ŸGPIO_SetOutData$9gpio$Y
data;¡
­GPIO_GetOutDataY
$9gpioa__resultY

<Ð
¼GPIO_Toggle$9gpio$Y
u32PinMask<
ÑGPIO_EnableInt$9gpio$Y
u32Pin$µIntAttribs<¼
áGPIO_DisableInt$9gpio$Y
u32Pin¡_GPIO_ModeDef
GPIO_MODE_INPUTGPIO_MODE_OUTPUT
GPIO_MODE_OPEN_DRAINGPIO_MODE_QUASIPGPIO_ModeDef¼
)µ_GPIO_IntAttrDefGPIO_INT_RISING
GPIO_INT_FALLING
GPIO_INT_BOTH_EDGE

GPIO_INT_HIGH

GPIO_INT_LOW

PGPIO_IntAttrDef5
7˜_GPIO_ClkSrcDef
GPIO_DBCTL_DBCLKSRC_RCLGPIO_DBCTL_DBCLKSRC_HCLKPGPIO_ClkSrcDefÌ
Cð_GPIO_ClkSelDef
GPIO_DBCTL_DBCLKSEL_1GPIO_DBCTL_DBCLKSEL_2
GPIO_DBCTL_DBCLKSEL_4GPIO_DBCTL_DBCLKSEL_8GPIO_DBCTL_DBCLKSEL_16GPIO_DBCTL_DBCLKSEL_32GPIO_DBCTL_DBCLKSEL_64GPIO_DBCTL_DBCLKSEL_128GPIO_DBCTL_DBCLKSEL_256GPIO_DBCTL_DBCLKSEL_512    GPIO_DBCTL_DBCLKSEL_1024
GPIO_DBCTL_DBCLKSEL_2048GPIO_DBCTL_DBCLKSEL_4096GPIO_DBCTL_DBCLKSEL_8192 GPIO_DBCTL_DBCLKSEL_16384GPIO_DBCTL_DBCLKSEL_32768PGPIO_ClkSelDef.
]<¹
¢
GPIO_ClrIntFlag$9gpio$Y
u32PinMask"ž<ä
»
GPIO_ClrAllIntFlag$9gpio<œ 
Ô
GPIO_DisableDebounce$9gpio$Y
u32PinMask<Ó 
ã
GPIO_EnableDebounce$9gpio$Y
u32PinMask<Ž
ò
GPIO_DisableDigitalPath$9gpio$Y
u32PinMask<È
GPIO_EnableDigitalPath$9gpio$Y
u32PinMask<‚
GPIO_DisablePullupPath$9gpio$Y
u32PinMask<»
ŸGPIO_EnablePullupPath$9gpio$Y
u32PinMask<÷
®GPIO_DisablePulldownPath$9gpio$Y
u32PinMask<²
½GPIO_EnablePulldownPath$9gpio$Y
u32PinMask<ê
ÌGPIO_DisableDoutMask$9gpio$Y
u32PinMask<¡
ÛGPIO_EnableDoutMask$9gpio$Y
u32PinMask
ÜÝÞ

 __PAN_SPI_H__ 
jSPI_BAUD_RATE_DIV(x) ((x)?(x):(256))pg
 




..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_spi.h


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..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_spi.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x
_Bool;Ï
ä
SPI_IsSpiEnabled
$³ SPIxa__result

\tmpregY
<þ
õ
SPI_EnableDmaTx$³ SPIx\tmpregY
<®
„SPI_DisableDmaTx$³ SPIx\tmpregY
;ñ
“SPI_IsDmaTxEnabled
$³ SPIxa__result

\tmpregY
< 
¤SPI_EnableDmaRx$³ SPIx\tmpregY
<Ð
³SPI_DisableDmaRx$³ SPIx\tmpregY
;“
ÂSPI_IsDmaRxEnabled
$³ SPIxa__result

\tmpregY
<½
ÓSPI_SendData$³ SPIx$Y
Data;ô
ÞSPI_ReceiveDataY
$³ SPIxa__resultY

<©
ïSPI_EnableIrq$³ SPIx$Êirq\tmpregY
<ß
„SPI_DisableIrq$³ SPIx$Êirq\tmpregY
;¨
™SPI_IsIrqEnabled
$³ SPIx$Êirqa__result

\tmpregY
;î
¯SPI_GetMskedActiveIrqÊ$³ SPIxa__resultÊ
\tmpregY
;¶
ÅSPI_IsIrqActive
$³ SPIx$Êirqa__result

\tmpregY
;    
ÜSPI_IsRawIrqActive
$³ SPIx$Êirqa__result

\tmpregY
<µ    
ðSPI_ClearIrq$³ SPIx$Êirq\tmpregY
;ù    
ƒSPI_GetRawActiveIrqÊ$³ SPIxa__resultÊ
\tmpregY
;»

“SPI_IsTxFifoEmpty
$³ SPIxa__result

\tmpregY
;ü

£SPI_IsTxFifoFull
$³ SPIxa__result

\tmpregY
;¾
´SPI_IsRxFifoEmpty
$³ SPIxa__result

\tmpregY
;ÿ
ÆSPI_IsRxFifoFull
$³ SPIxa__result

\tmpregY
;º
ØSPI_IsBusy
$³ SPIxa__result

\tmpregY
<ç
éSPI_TxLsbEnable$³ SPIx$
enable<” 
ôSPI_RxLsbEnable$³ SPIx$
enable<½ 
‚SPI_SetWireNum$³ SPIx$<num<ô 
SPI_DataCmdLineEnable$³ SPIx$åNewState<¦
ŸSPI_DataCmdSelCmdDat$³ SPIx$ŠcmdDat<Ñ
­SPI_WriteReadCtrl$³ SPIx$ÙwrÊSPI_Irq
SPI_IRQ_TX_HALF_EMPTYSPI_IRQ_RX_HALF_FULLSPI_IRQ_RX_TIMEOUTSPI_IRQ_RX_OVERRUN
SPI_IRQ_ALLPSPI_IrqDefQ
$SPI_Role
SPI_RoleMasterSPI_RoleSlave
PSPI_RoleDefÜ
.ÂSPI_DataFrameSize
SPI_DataFrame_4bSPI_DataFrame_5bSPI_DataFrame_6bSPI_DataFrame_7bSPI_DataFrame_8bSPI_DataFrame_9bSPI_DataFrame_10b    SPI_DataFrame_11b
SPI_DataFrame_12bSPI_DataFrame_13bSPI_DataFrame_14b SPI_DataFrame_15bSPI_DataFrame_16bPSPI_DataFrameSizeDef 
P¿SPI_BaudRateDiv
SPI_BaudRateDiv_2SPI_BaudRateDiv_4SPI_BaudRateDiv_6SPI_BaudRateDiv_8SPI_BaudRateDiv_16SPI_BaudRateDiv_32 SPI_BaudRateDiv_480SPI_BaudRateDiv_64@SPI_BaudRateDiv_96`SPI_BaudRateDiv_128€SPI_BaudRateDiv_160 SPI_BaudRateDiv_192ÀSPI_BaudRateDiv_224àSPI_BaudRateDiv_240ðSPI_BaudRateDiv_250úPSPI_BaudRateDivDef^    
gœSPI_ClockPol
SPI_ClockPolarityLowSPI_ClockPolarityHigh
PSPI_ClockPolDefÙ

uþSPI_ClockPhase
SPI_ClockPhaseFirstEdgeSPI_ClockPhaseSecondEdge
PSPI_ClockPhaseDef3
éSPI_FrameFormat
SPI_FormatMotorolaSPI_FormatTi
SPI_FormatMicrowirePSPI_FrameFormatDef—
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¼SPI_WireNum
SPI_WireNumThree
SPI_WireNumFourPSPI_WireNumDef
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SPI_CommandSelectSPI_DataSelect
PSPI_CmdDatDefS
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ÙSPI_WriteReadSel
SPI_3WireReadSPI_3WireWrite
PSPI_WriteReadSelDef 
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*îSPI_role #SPI_dataFrameSizeB    #
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#SPI_formaté#PSPI_InitTypeDefõ
½
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SPI_EnableSpi$³ SPIx\tmpregY
"<ç
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SPI_DisableSpi$³ SPIx\tmpregY

àáâ

 __PAN_UART_H__ th
 




..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_uart.h


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..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_uart.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x
_Bool;Æ
”UART_IsFifoEnabled
$óUARTxa__result

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²UART_ResetTxFifo$óUARTx<Ë
ÂUART_SetTxTrigger$óUARTx$ñlevel<ú
ÓUART_SetRxTrigger$óUARTx$‘level;¶
âUART_GetTxFifoLevel:
$óUARTxa__result:

;ò
íUART_GetRxFifoLevel:
$óUARTxa__result:

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øUART_EnableAfc$óUARTx<·
ƒUART_DisableAfc$óUARTx;í
ŽUART_IsAfcEnabled
$óUARTxa__result

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šUART_SendData$óUARTx$:
Data;Ò
¥UART_ReceiveData:
$óUARTxa__result:

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°UART_EnablePtime$óUARTx<›
»UART_DisablePtime$óUARTx;Ó
ÆUART_IsPtimeEnabled
$óUARTxa__result

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ÒUART_EnableIrq$óUARTx$irq<¨
ÞUART_DisableIrq$óUARTx$irq;æ
êUART_IsIrqEnabled
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õUART_GetIrqMasked:
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€UART_GetActiveEvent¤$óUARTxa__result¤
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$óUARTxa__result

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$óUARTxa__result

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$óUARTxa__result

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¬UART_IsRxFifoFull
$óUARTxa__result

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·UART_EnableHaltTX$óUARTx<ý
ÂUART_DisableHaltTX$óUARTx<Ÿ
ÍUART_EnableRts$óUARTx<Â
ØUART_DisableRts$óUARTx<é
ãUART_Enable9BitData$óUARTx<‘ 
îUART_Disable9BitData$óUARTx<½ 
ùUART_EnableAddrMatchMode$óUARTx<ê 
„UART_DisableAddrMatchMode$óUARTx<‹
UART_SendAddr$óUARTx<À
œUART_SetReceiveAddress$óUARTx$Y
addr<ö
¨UART_SetTransmitAddress$óUARTx$Y
addrñUART_TxTrigger
UART_TX_FIFO_EMPTYUART_TX_FIFO_TWO_CHARS
UART_TX_FIFO_QUARTER_FULLUART_TX_FIFO_HALF_FULLPUART_TxTriggerDefv
$‘UART_RxTrigger
UART_RX_FIFO_ONE_CHARUART_RX_FIFO_QUARTER_FULL
UART_RX_FIFO_HALF_FULLUART_RX_FIFO_TWO_LESS_THAN_FULLPUART_RxTriggerDef

0ïUART_LineCtrl
Uart_Line_5n1Uart_Line_5n1_5Uart_Line_5e1Uart_Line_5e1_5Uart_Line_5o1Uart_Line_5o1_5Uart_Line_5s18Uart_Line_5s1_5<Uart_Line_5m1(Uart_Line_5m1_5,Uart_Line_6n1
Uart_Line_6n2Uart_Line_6e1Uart_Line_6e2Uart_Line_6o1    Uart_Line_6o2 Uart_Line_6s19Uart_Line_6s2=Uart_Line_6m1)Uart_Line_6m2-Uart_Line_7n1Uart_Line_7n2Uart_Line_7e1Uart_Line_7e2Uart_Line_7o1
Uart_Line_7o2Uart_Line_7s1:Uart_Line_7s2>Uart_Line_7m1*Uart_Line_7m2.Uart_Line_8n1Uart_Line_8n2Uart_Line_8e1Uart_Line_8e2Uart_Line_8o1Uart_Line_8o2Uart_Line_8s1;Uart_Line_8s2?Uart_Line_8m1+Uart_Line_8m2/PUART_LineCtrlDefª
b†UART_Irq
UART_IRQ_RECV_DATA_AVL
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s¤UART_Event
UART_EVENT_MODEMUART_EVENT_NONE
UART_EVENT_THR_EMPTYUART_EVENT_DATAUART_EVENT_LINEUART_EVENT_TIMEOUTPUART_EventDef
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UART_LINE_OVERRUN_ERRUART_LINE_PARITY_ERRUART_LINE_FRAME_ERRUART_LINE_BREAK_INTUART_LINE_THRE UART_LINE_TXSR_EMPTY@UART_LINE_RX_FIFO_ERR€UART_LINE_ADDR_RCVD
PUART_LineStatusDefº
§
ãUART_ModemStatus
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*°UART_BaudRateY
#UART_LineCtrlo#PUART_InitTypeDef
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UART_DisableStickParity$óUARTx;Û
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UART_EnableFifo$óUARTx<Ú
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äåæ

__PAN_I2C_H__ 
=I2C_DYNAMIC_TAR_UPDATE 0
DI2C_MODE_MASTER ((uint16_t)0x0021)
EI2C_MODE_SLAVE ((uint16_t)0x0000)
LIS_I2C_MODE(MODE) (((MODE) == I2C_MODE_MASTER) || ((MODE) == I2C_MODE_SLAVE))
TI2C_SPEED_STANDARD_MODE (uint16_t)(0x0002)
UI2C_SPEED_FAST_MODE (uint16_t)(0x0004)
VI2C_SPEED_HIGH_MODE (uint16_t)(0x0006)
^I2C_DutyCycle_16_9 ((uint16_t)0x4000)
_I2C_DutyCycle_2 ((uint16_t)0xBFFF)
`I2C_DutyCycle_1_1 ((uint16_t)0x0800)
aI2C_DutyCycle_1_2 ((uint16_t)0x0400)
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mI2C_Direction_Transmitter ((uint16_t)0x0000)
nI2C_Direction_Receiver ((uint16_t)0x0100)
oIS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || ((DIRECTION) == I2C_Direction_Receiver))
vI2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
wI2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
xIS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
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I2C_CMD_RD ((uint8_t)0x01)
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I2C_RX_TL_0 ((uint8_t)0x00)
‰
I2C_RX_TL_1 ((uint8_t)0x01)
Š
I2C_RX_TL_2 ((uint8_t)0x02)
‹
I2C_RX_TL_3 ((uint8_t)0x03)
Œ
I2C_RX_TL_4 ((uint8_t)0x04)

I2C_RX_TL_5 ((uint8_t)0x05)
Ž
I2C_RX_TL_6 ((uint8_t)0x06)

I2C_RX_TL_7 ((uint8_t)0x07)

I2C_RX_TL_8 ((uint8_t)0x08)
–
I2C_TX_TL_0 ((uint8_t)0x00)
—
I2C_TX_TL_1 ((uint8_t)0x01)
˜
I2C_TX_TL_2 ((uint8_t)0x02)
™
I2C_TX_TL_3 ((uint8_t)0x03)
š
I2C_TX_TL_4 ((uint8_t)0x04)
›
I2C_TX_TL_5 ((uint8_t)0x05)
œ
I2C_TX_TL_6 ((uint8_t)0x06)
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I2C_TX_TL_7 ((uint8_t)0x07)
ž
I2C_TX_TL_8 ((uint8_t)0x08)
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I2C_IT_RX_UNDER ((uint16_t)0x0001)
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I2C_IT_RX_OVER ((uint16_t)0x0002)
§
I2C_IT_RX_FULL ((uint16_t)0x0004)
¨
I2C_IT_TX_OVER ((uint16_t)0x0008)
©
I2C_IT_TX_EMPTY ((uint16_t)0x0010)
ª
I2C_IT_RD_REQ ((uint16_t)0x0020)
«
I2C_IT_TX_ABORT ((uint16_t)0x0040)
¬
I2C_IT_RX_DONE ((uint16_t)0x0080)
­
I2C_IT_ACTIVITY ((uint16_t)0x0100)
®
I2C_IT_STOP_DET ((uint16_t)0x0200)
¯
I2C_IT_START_DET ((uint16_t)0x0400)
°
I2C_IT_GEN_CALL ((uint16_t)0x0800)
±
I2C_IT_MST_ON_HOLD ((uint16_t)0x2000)
²
I2C_IT_ALL ((uint16_t)0x2FFF)
´
IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x0FFF) == 0x00) && ((IT) != (uint16_t)0x00))
¶
IS_I2C_GET_IT(IT) (((IT) == I2C_IT_RX_UNDER) || ((IT) == I2C_IT_RX_OVER) || ((IT) == I2C_IT_RX_FULL) || ((IT) == I2C_IT_TX_OVER) || ((IT) == I2C_IT_TX_EMPTY) || ((IT) == I2C_IT_RD_REQ) || ((IT) == I2C_IT_TX_ABORT) || ((IT) == I2C_IT_RX_DONE) || ((IT) == I2C_IT_ACTIVITY) || ((IT) == I2C_IT_STOP_DET) || ((IT) == I2C_IT_START_DET)|| ((IT) == I2C_IT_GEN_CALL))
Á
I2C_FLAG_SLV_ACTIVITY ((uint32_t)0x00000040)
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I2C_FLAG_MST_ACTIVITY ((uint32_t)0x00000020)
Ã
I2C_FLAG_RFF ((uint32_t)0x00000010)
Ä
I2C_FLAG_RFNE ((uint32_t)0x00000008)
Å
I2C_FLAG_TFE ((uint32_t)0x00000004)
Æ
I2C_FLAG_TFNF ((uint32_t)0x00000002)
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I2C_FLAG_ACTIVITY ((uint32_t)0x00000001)
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É
IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_ACTIVITY) || ((FLAG) == I2C_FLAG_TFNF) || ((FLAG) == I2C_FLAG_TFE) || ((FLAG) == I2C_FLAG_RFNE) || ((FLAG) == I2C_FLAG_RFF) || ((FLAG) == I2C_FLAG_MST_ACTIVITY) || ((FLAG) == I2C_FLAG_SLV_ACTIVITY))
Ó
FLAG_MASK ((uint32_t)0x007F0FFF)
Ô
ITEN_MASK ((uint16_t)0x2FFF)
Õ
IT_FLAG_MASK ((uint16_t)0x2FFF)pg
 




..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_i2c.h


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..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_i2c.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x
_Bool;Ð
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__PAN_TIMER_H__ 
aFIXED_DEVIATION (12)ti
 




..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_timer.h



..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_timer.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x
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PWM_CHANNEL_NUM (8)
 PWM_CH0 0x0
!PWM_CH1 0x1
"PWM_CH2 0x2
#PWM_CH3 0x3
$PWM_CH4 0x4
%PWM_CH5 0x5
&PWM_CH6 0x6
'PWM_CH7 0x7pg
 




..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_pwm.h


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..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_pwm.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xÕ_PWM_ClkSrcSelDef
PWM_CLK_SRC_APBPWM_CLK_SRC_RCL
PWM_CLK_SRC_XTLPPWM_ClkSrcSelDef

6é_PWM_ClkDivDef
PWM_CLK_DIV_1PWM_CLK_DIV_2PWM_CLK_DIV_4
PWM_CLK_DIV_8PWM_CLK_DIV_16PWM_CLK_DIRECTPPWM_ClkDivDefm

CÁ_PWM_AlignedTypeDef
PWM_EDGE_ALIGNEDPWM_CENTER_ALIGNED
PPWM_AlignedTypeDefþ

M®_PWM_IntPeriodTypeDef
PWM_PERIOD_INT_UNDERFLOWPWM_PERIOD_INT_MATCH_CNR
PPWM_IntPeriodTypeDef[
W½_PWM_OperateTypeDef
OPERATION_EDGE_ALIGNED
OPERATION_CENTER_ALIGNEDOPERATION_PRECISE_CENTER_ALIGNEDPPWM_OperateTypeDefÊ
bŸ_PWM_CntModeDef
PWM_CNTMODE_ONE_SHOTPWM_CNTMODE_AUTO_RELOAD
PPWM_CntModeDefW
l<ë
vPWM_EnableOutput$ëpwm$Y
u32ChannelMask"ó    <©
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u32ChannelNum$Y
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u32ChannelNum<†
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u32ChannelNum;
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u32ChannelNuma__resultY

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°PWM_EnableIndependentMode$ëpwm<ß
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u32CMRD<ä
ÍPWM_SetAlignedType$ëpwm$Y
u32ChannelMask$AAlignedType<Ž
×PWM_EnableAsymmetricMode$ëpwm<¹
áPWM_DisableAsymmetricMode$ëpwm<Ø
ëPWM_EnablePCA$ëpwm<ø
õPWM_DisablePCA$ëpwm
ðñò

 __PAN_WDT_H__ pg
 




..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_wdt.h


„
..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_wdt.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x
_Bool;¸
hWDT_GetResetFlag
a__result

;ä
tWDT_GetTimeoutFlag
a__result

;”
€
WDT_GetTimeoutIntFlag
a__result

;Ç
Œ
WDT_GetTimeoutWakeupFlag
a__result

<á
—
WDT_ResetCounterß_WDT_TimeoutWDT_TIMEOUT_2POW4WDT_TIMEOUT_2POW6
WDT_TIMEOUT_2POW8WDT_TIMEOUT_2POW10WDT_TIMEOUT_2POW12WDT_TIMEOUT_2POW14WDT_TIMEOUT_2POW15WDT_TIMEOUT_2POW16WDT_TIMEOUT_2POW17WDT_TIMEOUT_2POW18    WDT_TIMEOUT_2POW19
WDT_TIMEOUT_2POW20WDT_TIMEOUT_2POW21WDT_TIMEOUT_2POW22 WDT_TIMEOUT_2POW23WDT_TIMEOUT_2POW24PWDT_TimeoutDefá

.ð_WDT_ResetDelay
WDT_RESET_DELAY_2CLKWDT_RESET_DELAY_17CLKWDT_RESET_DELAY_129CLK
WDT_RESET_DELAY_1025CLKPWDT_ResetDelayDefu
:<¤
AWDT_ClearResetFlag<Á
JWDT_ClearTimeoutFlag<á
SWDT_ClearTimeoutIntFlag<„    
\WDT_ClearTimeoutWakeupFlag
ôõö

 __PAN_WWDT_H__ 
3WWDT_RELOAD_WORD (0x00005AA5)th
 




..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_wwdt.h


ð
..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_wwdt.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x
_Bool;º
^WWDT_GetResetFlag
a__result

;ã
jWWDT_GetIntFlag
a__result

;Ž
vWWDT_GetWWDTFFlag
a__result

;¼

WWDT_GetCounterY
a__resultY

;ï
Œ
WWDT_GetCompareValueY
a__resultY

<‹
š
WWDT_ReloadCounter†_WWDT_PrescaleWWDT_PRESCALER_1WWDT_PRESCALER_2
WWDT_PRESCALER_4WWDT_PRESCALER_8WWDT_PRESCALER_16WWDT_PRESCALER_32WWDT_PRESCALER_64WWDT_PRESCALER_128WWDT_PRESCALER_192WWDT_PRESCALER_256    WWDT_PRESCALER_384
WWDT_PRESCALER_512WWDT_PRESCALER_768WWDT_PRESCALER_1024 WWDT_PRESCALER_1536WWDT_PRESCALER_2048PWWDT_PrescaleDef
0<º
<WWDT_ClearResetFlag<Ô
GWWDT_ClearIntFlag<ð
RWWDT_ClearWWDTFFlag
øùú

__PAN_LP_H__ 
LP_EXT_P56_WK_EN (1)
LP_EXT_P56_WK_DISABLE (0)
LP_EXT_P56_WK_EDGE_LOW (0)
 LP_EXT_P56_WK_EDGE_HIGH (1)
#LP_SLPTMR_CH0 (0)
$LP_SLPTMR_CH1 (1)
%LP_SLPTMR_CH2 (2)
'LP_MODE_SEL_SLEEP_MODE (0)
(LP_MODE_SEL_DEEPSLEEP_MODE (1)
)LP_MODE_SEL_STANDBY_M1_MODE (2)
*LP_MODE_SEL_STANDBY_M0_MODE (3)
,LP_DEEPSLEEP_MODE1 (1)
-LP_DEEPSLEEP_MODE2 (2)
.LP_DEEPSLEEP_MODE3 (3)
0LP_STANDBY_M1_MODE_SEL LP_STANDBY_M1_MODE1
1LP_STANDBY_M1_MODE1 (1)
2LP_STANDBY_M1_MODE2 (2)
3LP_STANDBY_M1_MODE3 (3)
5LP_STBM1_WAKEUP_SRC_GPIO BIT0
6LP_STBM1_WAKEUP_SRC_SLPTMR BIT1
8LP_RETENTION_SRAM_NONE (0)
9LP_RETENTION_SRAM_BLOCK0 BIT0
:LP_RETENTION_SRAM_BLOCK1 BIT1
;LP_RETENTION_SRAM_DECRYPT BIT2
<LP_RETENTION_SRAM_PHY_REGS BIT3
=LP_RETENTION_SRAM_LL BIT4
>LP_RETENTION_SRAM_ALL (BIT0 | BIT1 | BIT2 | BIT3 | BIT4)pf
 




..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_lp.h


È

..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_lp.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x<°
GLP_EnableInt$0
ana$åNewState"e<å
RLP_ClearWakeFlag$0
ana$Y
u32Mask<˜
]LP_HpldoRdyBypassEn$0
ana$åNewState<É
hLP_FastClkDelayEn$0
ana$åNewState
üýþ

 __PAN_EFUSE_H__ 
EFUSE_CMD_READ (0X0)
EFUSE_CMD_PROGRAM (0X1)
EFUSE_CMD_INACTIVE (0X2)
%EFUSE_STATUS_OK (0x0)
&EFUSE_STATUS_FAIL (0x1)ti
 




..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_efuse.h


¬

..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_efuse.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x<¤
1EFUSE_Init$$
efuse"<É
?EFUSE_UnInit$$
efuse;…
LEFUSE_GetErrorStatusY
$$
efusea__resultY

<¬
WEFUSE_ClrErrorStatus$$
efuse






 __PANSERIES_H__ 
J__CM0_REV 0x0000
K__MPU_PRESENT 0
L__NVIC_PRIO_BITS 2
M__Vendor_SysTickConfig 0
N__FPU_PRESENT 0PQU
ZIS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
¹TIMER_CTL_PSC_Pos (0)
ºTIMER_CTL_PSC_Msk (0xfful << TIMER_CTL_PSC_Pos)
¼TIMER_CTL_CAPSRC_Pos (19)
½TIMER_CTL_CAPSRC_Msk (0x1ul << TIMER_CTL_CAPSRC_Pos)
¿TIMER_CTL_WKEN_Pos (23)
ÀTIMER_CTL_WKEN_Msk (0x1ul << TIMER_CTL_WKEN_Pos)
ÂTIMER_CTL_EXTCNTEN_Pos (24)
ÃTIMER_CTL_EXTCNTEN_Msk (0x1ul << TIMER_CTL_EXTCNTEN_Pos)
ÅTIMER_CTL_ACTSTS_Pos (25)
ÆTIMER_CTL_ACTSTS_Msk (0x1ul << TIMER_CTL_ACTSTS_Pos)
ÈTIMER_CTL_RSTCNT_Pos (26)
ÉTIMER_CTL_RSTCNT_Msk (0x1ul << TIMER_CTL_RSTCNT_Pos)
ËTIMER_CTL_OPMODE_Pos (27)
ÌTIMER_CTL_OPMODE_Msk (0x3ul << TIMER_CTL_OPMODE_Pos)
ÎTIMER_CTL_INTEN_Pos (29)
ÏTIMER_CTL_INTEN_Msk (0x1ul << TIMER_CTL_INTEN_Pos)
ÑTIMER_CTL_CNTEN_Pos (30)
ÒTIMER_CTL_CNTEN_Msk (0x1ul << TIMER_CTL_CNTEN_Pos)
ÔTIMER_CTL_ICEDEBUG_Pos (31)
ÕTIMER_CTL_ICEDEBUG_Msk (0x1ul << TIMER_CTL_ICEDEBUG_Pos)
×TIMER_CMP_CMPDAT_Pos (0)
ØTIMER_CMP_CMPDAT_Msk (0xFFfffffful << TIMER_CMP_CMPDAT_Pos)
ÚTIMER_INTSTS_TIF_Pos (0)
ÛTIMER_INTSTS_TIF_Msk (0x1ul << TIMER_INTSTS_TIF_Pos)
ÝTIMER_INTSTS_TWKF0_Pos (1)
ÞTIMER_INTSTS_TWKF0_Msk (0x1ul << TIMER_INTSTS_TWKF0_Pos)
àTIMER_INTSTS_TWKF1_Pos (2)
áTIMER_INTSTS_TWKF1_Msk (0x1ul << TIMER_INTSTS_TWKF1_Pos)
ãTIMER_INTSTS_TWKF2_Pos (3)
äTIMER_INTSTS_TWKF2_Msk (0x1ul << TIMER_INTSTS_TWKF2_Pos)
æTIMER_INTSTS_TF0_Pos (4)
çTIMER_INTSTS_TF0_Msk (0x1ul << TIMER_INTSTS_TF0_Pos)
éTIMER_INTSTS_TF1_Pos (5)
êTIMER_INTSTS_TF1_Msk (0x1ul << TIMER_INTSTS_TF1_Pos)
ìTIMER_INTSTS_TF2_Pos (6)
íTIMER_INTSTS_TF2_Msk (0x1ul << TIMER_INTSTS_TF2_Pos)
ïTIMER_CNT_CNT_Pos (0)
ðTIMER_CNT_CNT_Msk (0xFFfffffful << TIMER_CNT_CNT_Pos)
òTIMER_CAP_CAPDAT_Pos (0)
óTIMER_CAP_CAPDAT_Msk (0xFFfffffful << TIMER_CAP_CAPDAT_Pos)
õTIMER_EXTCTL_CNTPHASE_Pos (0)
öTIMER_EXTCTL_CNTPHASE_Msk (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos)
øTIMER_EXTCTL_CAPEDGE_Pos (1)
ùTIMER_EXTCTL_CAPEDGE_Msk (0x3ul << TIMER_EXTCTL_CAPEDGE_Pos)
ûTIMER_EXTCTL_CAPEN_Pos (3)
üTIMER_EXTCTL_CAPEN_Msk (0x1ul << TIMER_EXTCTL_CAPEN_Pos)
þTIMER_EXTCTL_CAPFUNCS_Pos (4)
ÿTIMER_EXTCTL_CAPFUNCS_Msk (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos)
TIMER_EXTCTL_CAPIEN_Pos (5)
‚TIMER_EXTCTL_CAPIEN_Msk (0x1ul << TIMER_EXTCTL_CAPIEN_Pos)
„TIMER_EXTCTL_CAPDBEN_Pos (6)
…TIMER_EXTCTL_CAPDBEN_Msk (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos)
‡TIMER_EXTCTL_CNTDBEN_Pos (7)
ˆTIMER_EXTCTL_CNTDBEN_Msk (0x1ul << TIMER_EXTCTL_CNTDBEN_Pos)
ŠTIMER_EXTCTL_CAPSEL_Pos (8)
‹TIMER_EXTCTL_CAPSEL_Msk (0x1ul << TIMER_EXTCTL_CAPSEL_Pos)
TIMER_EXTCTL_ACMPSSEL_Pos (9)
ŽTIMER_EXTCTL_ACMPSSEL_Msk (0x1ul << TIMER_EXTCTL_ACMPSSEL_Pos)
TIMER_EINTSTS_CAPIF_Pos (0)
‘TIMER_EINTSTS_CAPIF_Msk (0x1ul << TIMER_EINTSTS_CAPIF_Pos)
“TIMER_EINTSTS_CAPF_Pos (1)
”TIMER_EINTSTS_CAPF_Msk (0x1ul << TIMER_EINTSTS_CAPF_Pos)
§TRIM_MEASURE_TUNING_EN_Pos (0)
¨TRIM_MEASURE_TUNING_EN_Msk (0x1ul << TRIM_MEASURE_TUNING_EN_Pos)
©TRIM_COARSE_TUNING_EN_Pos (1)
ªTRIM_COARSE_TUNING_EN_Msk (0x1ul << TRIM_COARSE_TUNING_EN_Pos)
«TRIM_FINE_TUNING_EN_Pos (2)
¬TRIM_FINE_TUNING_EN_Msk (0x1ul << TRIM_FINE_TUNING_EN_Pos)
¯TRIM_COARSE_CODE_Pos (0)
°TRIM_COARSE_CODE_Msk (0xful << TRIM_COARSE_CODE_Pos)
±TRIM_FINE_CODE_Pos (8)
²TRIM_FINE_CODE_Msk (0xfful << TRIM_FINE_CODE_Pos)
³TRIM_BIT_WIDTH_Pos (16)
´TRIM_BIT_WIDTH_Msk (0x7ul << TRIM_BIT_WIDTH_Pos)
·TRIM_CLRL_RELATION_Pos (0)
¸TRIM_CLRL_RELATION_Msk (0x1ul << TRIM_CLRL_RELATION_Pos)
¹TRIM_CLRL_EARLY_TERM_EN_Pos (1)
ºTRIM_CLRL_EARLY_TERM_EN_Msk (0x1ul << TRIM_CLRL_EARLY_TERM_EN_Pos)
»TRIM_CLRL_FAIL_CLAC_FLAG_Pos (2)
¼TRIM_CLRL_FAIL_CLAC_FLAG_Msk (0x1ul << TRIM_CLRL_FAIL_CLAC_FLAG_Pos)
½TRIM_CLRL_CODE_STEP_Pos (8)
¾TRIM_CLRL_CODE_STEP_Msk (0xfful << TRIM_CLRL_CODE_STEP_Pos)
¿TRIM_CLRL_ERR_RANGE_Pos (16)
ÀTRIM_CLRL_ERR_RANGE_Msk (0xfffful << TRIM_CLRL_ERR_RANGE_Pos)
ÃTRIM_INT_EN_Pos (0)
ÄTRIM_INT_EN_Msk (0x1ul << TRIM_INT_EN_Pos)
ÅTRIM_INT_MEASURE_STOP_Pos (1)
ÆTRIM_INT_MEASURE_STOP_Msk (0x1ul << TRIM_INT_MEASURE_STOP_Pos)
ÇTRIM_FLAG_MEASURE_STOP_Pos (2)
ÈTRIM_FLAG_MEASURE_STOP_Msk (0x1ul << TRIM_FLAG_MEASURE_STOP_Pos)
ÉTRIM_INT_CTUNE_STOP_Pos (3)
ÊTRIM_INT_CTUNE_STOP_Msk (0x1ul << TRIM_INT_CTUNE_STOP_Pos)
ËTRIM_FLAG_CTUNE_STOP_Pos (4)
ÌTRIM_FLAG_CTUNE_STOP_Msk (0x1ul << TRIM_FLAG_CTUNE_STOP_Pos)
ÍTRIM_INT_FTUNE_STOP_Pos (5)
ÎTRIM_INT_FTUNE_STOP_Msk (0x1ul << TRIM_INT_FTUNE_STOP_Pos)
ÏTRIM_FLAG_FTUNE_STOP_Pos (6)
ÐTRIM_FLAG_FTUNE_STOP_Msk (0x1ul << TRIM_FLAG_FTUNE_STOP_Pos)
ÑTRIM_INT_OVERFLOW_Pos (9)
ÒTRIM_INT_OVERFLOW_Msk (0x1ul << TRIM_INT_OVERFLOW_Pos)
ÓTRIM_FLAG_OVERFLOW_Pos (10)
ÔTRIM_FLAG_OVERFLOW_Msk (0x1ul << TRIM_FLAG_OVERFLOW_Pos)
ÚTRIM_CALC_CNT_Pos (0)
ÛTRIM_CALC_CNT_Msk (0xFFFFFFul << TRIM_INT_EN_Pos)
ÜTRIM_CALC_WATI_CNT_Pos (24)
ÝTRIM_CALC_WATI_CNT_Msk (0xFFul << TRIM_CALC_WATI_CNT_Pos)
·GP_MODE_MODE0_Pos (0)
¸GP_MODE_MODE0_Msk (0x3ul << GP_MODE_MODE0_Pos)
ºGP_MODE_MODE1_Pos (2)
»GP_MODE_MODE1_Msk (0x3ul << GP_MODE_MODE1_Pos)
½GP_MODE_MODE2_Pos (4)
¾GP_MODE_MODE2_Msk (0x3ul << GP_MODE_MODE2_Pos)
ÀGP_MODE_MODE3_Pos (6)
ÁGP_MODE_MODE3_Msk (0x3ul << GP_MODE_MODE3_Pos)
ÃGP_MODE_MODE4_Pos (8)
ÄGP_MODE_MODE4_Msk (0x3ul << GP_MODE_MODE4_Pos)
ÆGP_MODE_MODE5_Pos (10)
ÇGP_MODE_MODE5_Msk (0x3ul << GP_MODE_MODE5_Pos)
ÉGP_DINOFF_DINOFF0_Pos (16)
ÊGP_DINOFF_DINOFF0_Msk (0x1ul << GP_DINOFF_DINOFF0_Pos)
ÌGP_DINOFF_DINOFF1_Pos (17)
ÍGP_DINOFF_DINOFF1_Msk (0x1ul << GP_DINOFF_DINOFF1_Pos)
ÏGP_DINOFF_DINOFF2_Pos (18)
ÐGP_DINOFF_DINOFF2_Msk (0x1ul << GP_DINOFF_DINOFF2_Pos)
ÒGP_DINOFF_DINOFF3_Pos (19)
ÓGP_DINOFF_DINOFF3_Msk (0x1ul << GP_DINOFF_DINOFF3_Pos)
ÕGP_DINOFF_DINOFF4_Pos (20)
ÖGP_DINOFF_DINOFF4_Msk (0x1ul << GP_DINOFF_DINOFF4_Pos)
ØGP_DINOFF_DINOFF5_Pos (21)
ÙGP_DINOFF_DINOFF5_Msk (0x1ul << GP_DINOFF_DINOFF5_Pos)
ÛGP_DINOFF_DINOFF6_Pos (22)
ÜGP_DINOFF_DINOFF6_Msk (0x1ul << GP_DINOFF_DINOFF6_Pos)
ÞGP_DINOFF_DINOFF7_Pos (23)
ßGP_DINOFF_DINOFF7_Msk (0x1ul << GP_DINOFF_DINOFF7_Pos)
áGP_DOUT_DOUT0_Pos (0)
âGP_DOUT_DOUT0_Msk (0x1ul << GP_DOUT_DOUT0_Pos)
äGP_DOUT_DOUT1_Pos (1)
åGP_DOUT_DOUT1_Msk (0x1ul << GP_DOUT_DOUT1_Pos)
çGP_DOUT_DOUT2_Pos (2)
èGP_DOUT_DOUT2_Msk (0x1ul << GP_DOUT_DOUT2_Pos)
êGP_DOUT_DOUT3_Pos (3)
ëGP_DOUT_DOUT3_Msk (0x1ul << GP_DOUT_DOUT3_Pos)
íGP_DOUT_DOUT4_Pos (4)
îGP_DOUT_DOUT4_Msk (0x1ul << GP_DOUT_DOUT4_Pos)
ðGP_DOUT_DOUT5_Pos (5)
ñGP_DOUT_DOUT5_Msk (0x1ul << GP_DOUT_DOUT5_Pos)
óGP_DOUT_DOUT6_Pos (6)
ôGP_DOUT_DOUT6_Msk (0x1ul << GP_DOUT_DOUT6_Pos)
öGP_DOUT_DOUT7_Pos (7)
÷GP_DOUT_DOUT7_Msk (0x1ul << GP_DOUT_DOUT7_Pos)
ùGP_DATMSK_DATMSK0_Pos (0)
úGP_DATMSK_DATMSK0_Msk (0x1ul << GP_DATMSK_DATMSK0_Pos)
üGP_DATMSK_DATMSK1_Pos (1)
ýGP_DATMSK_DATMSK1_Msk (0x1ul << GP_DATMSK_DATMSK1_Pos)
ÿGP_DATMSK_DATMSK2_Pos (2)
€GP_DATMSK_DATMSK2_Msk (0x1ul << GP_DATMSK_DATMSK2_Pos)
‚GP_DATMSK_DATMSK3_Pos (3)
ƒGP_DATMSK_DATMSK3_Msk (0x1ul << GP_DATMSK_DATMSK3_Pos)
…GP_DATMSK_DATMSK4_Pos (4)
†GP_DATMSK_DATMSK4_Msk (0x1ul << GP_DATMSK_DATMSK4_Pos)
ˆGP_DATMSK_DATMSK5_Pos (5)
‰GP_DATMSK_DATMSK5_Msk (0x1ul << GP_DATMSK_DATMSK5_Pos)
‹GP_DATMSK_DATMSK6_Pos (6)
ŒGP_DATMSK_DATMSK6_Msk (0x1ul << GP_DATMSK_DATMSK6_Pos)
ŽGP_DATMSK_DATMSK7_Pos (7)
GP_DATMSK_DATMSK7_Msk (0x1ul << GP_DATMSK_DATMSK7_Pos)
‘GP_PIN_PIN0_Pos (0)
’GP_PIN_PIN0_Msk (0x1ul << GP_PIN_PIN0_Pos)
”GP_PIN_PIN1_Pos (1)
•GP_PIN_PIN1_Msk (0x1ul << GP_PIN_PIN1_Pos)
—GP_PIN_PIN2_Pos (2)
˜GP_PIN_PIN2_Msk (0x1ul << GP_PIN_PIN2_Pos)
šGP_PIN_PIN3_Pos (3)
›GP_PIN_PIN3_Msk (0x1ul << GP_PIN_PIN3_Pos)
GP_PIN_PIN4_Pos (4)
žGP_PIN_PIN4_Msk (0x1ul << GP_PIN_PIN4_Pos)
 GP_PIN_PIN5_Pos (5)
¡GP_PIN_PIN5_Msk (0x1ul << GP_PIN_PIN5_Pos)
£GP_PIN_PIN6_Pos (6)
¤GP_PIN_PIN6_Msk (0x1ul << GP_PIN_PIN6_Pos)
¦GP_PIN_PIN7_Pos (7)
§GP_PIN_PIN7_Msk (0x1ul << GP_PIN_PIN7_Pos)
©GP_DBEN_DBEN0_Pos (0)
ªGP_DBEN_DBEN0_Msk (0x1ul << GP_DBEN_DBEN0_Pos)
¬GP_DBEN_DBEN1_Pos (1)
­GP_DBEN_DBEN1_Msk (0x1ul << GP_DBEN_DBEN1_Pos)
¯GP_DBEN_DBEN2_Pos (2)
°GP_DBEN_DBEN2_Msk (0x1ul << GP_DBEN_DBEN2_Pos)
²GP_DBEN_DBEN3_Pos (3)
³GP_DBEN_DBEN3_Msk (0x1ul << GP_DBEN_DBEN3_Pos)
µGP_DBEN_DBEN4_Pos (4)
¶GP_DBEN_DBEN4_Msk (0x1ul << GP_DBEN_DBEN4_Pos)
¸GP_DBEN_DBEN5_Pos (5)
¹GP_DBEN_DBEN5_Msk (0x1ul << GP_DBEN_DBEN5_Pos)
»GP_DBEN_DBEN6_Pos (6)
¼GP_DBEN_DBEN6_Msk (0x1ul << GP_DBEN_DBEN6_Pos)
¾GP_DBEN_DBEN7_Pos (7)
¿GP_DBEN_DBEN7_Msk (0x1ul << GP_DBEN_DBEN7_Pos)
ÁGP_INTTYPE_TYPE0_Pos (0)
ÂGP_INTTYPE_TYPE0_Msk (0x1ul << GP_INTTYPE_TYPE0_Pos)
ÄGP_INTTYPE_TYPE1_Pos (1)
ÅGP_INTTYPE_TYPE1_Msk (0x1ul << GP_INTTYPE_TYPE1_Pos)
ÇGP_INTTYPE_TYPE2_Pos (2)
ÈGP_INTTYPE_TYPE2_Msk (0x1ul << GP_INTTYPE_TYPE2_Pos)
ÊGP_INTTYPE_TYPE3_Pos (3)
ËGP_INTTYPE_TYPE3_Msk (0x1ul << GP_INTTYPE_TYPE3_Pos)
ÍGP_INTTYPE_TYPE4_Pos (4)
ÎGP_INTTYPE_TYPE4_Msk (0x1ul << GP_INTTYPE_TYPE4_Pos)
ÐGP_INTTYPE_TYPE5_Pos (5)
ÑGP_INTTYPE_TYPE5_Msk (0x1ul << GP_INTTYPE_TYPE5_Pos)
ÓGP_INTTYPE_TYPE6_Pos (6)
ÔGP_INTTYPE_TYPE6_Msk (0x1ul << GP_INTTYPE_TYPE6_Pos)
ÖGP_INTTYPE_TYPE7_Pos (7)
×GP_INTTYPE_TYPE7_Msk (0x1ul << GP_INTTYPE_TYPE7_Pos)
ÙGP_INTEN_FLIEN0_Pos (0)
ÚGP_INTEN_FLIEN0_Msk (0x1ul << GP_INTEN_FLIEN0_Pos)
ÜGP_INTEN_FLIEN1_Pos (1)
ÝGP_INTEN_FLIEN1_Msk (0x1ul << GP_INTEN_FLIEN1_Pos)
ßGP_INTEN_FLIEN2_Pos (2)
àGP_INTEN_FLIEN2_Msk (0x1ul << GP_INTEN_FLIEN2_Pos)
âGP_INTEN_FLIEN3_Pos (3)
ãGP_INTEN_FLIEN3_Msk (0x1ul << GP_INTEN_FLIEN3_Pos)
åGP_INTEN_FLIEN4_Pos (4)
æGP_INTEN_FLIEN4_Msk (0x1ul << GP_INTEN_FLIEN4_Pos)
èGP_INTEN_FLIEN5_Pos (5)
éGP_INTEN_FLIEN5_Msk (0x1ul << GP_INTEN_FLIEN5_Pos)
ëGP_INTEN_FLIEN6_Pos (6)
ìGP_INTEN_FLIEN6_Msk (0x1ul << GP_INTEN_FLIEN6_Pos)
îGP_INTEN_FLIEN7_Pos (7)
ïGP_INTEN_FLIEN7_Msk (0x1ul << GP_INTEN_FLIEN7_Pos)
ñGP_INTEN_RHIEN0_Pos (16)
òGP_INTEN_RHIEN0_Msk (0x1ul << GP_INTEN_RHIEN0_Pos)
ôGP_INTEN_RHIEN1_Pos (17)
õGP_INTEN_RHIEN1_Msk (0x1ul << GP_INTEN_RHIEN1_Pos)
÷GP_INTEN_RHIEN2_Pos (18)
øGP_INTEN_RHIEN2_Msk (0x1ul << GP_INTEN_RHIEN2_Pos)
úGP_INTEN_RHIEN3_Pos (19)
ûGP_INTEN_RHIEN3_Msk (0x1ul << GP_INTEN_RHIEN3_Pos)
ýGP_INTEN_RHIEN4_Pos (20)
þGP_INTEN_RHIEN4_Msk (0x1ul << GP_INTEN_RHIEN4_Pos)
€GP_INTEN_RHIEN5_Pos (21)
GP_INTEN_RHIEN5_Msk (0x1ul << GP_INTEN_RHIEN5_Pos)
ƒGP_INTEN_RHIEN6_Pos (22)
„GP_INTEN_RHIEN6_Msk (0x1ul << GP_INTEN_RHIEN6_Pos)
†GP_INTEN_RHIEN7_Pos (23)
‡GP_INTEN_RHIEN7_Msk (0x1ul << GP_INTEN_RHIEN7_Pos)
‰GP_INTSRC_INTSRC0_Pos (0)
ŠGP_INTSRC_INTSRC0_Msk (0x1ul << GP_INTSRC_INTSRC0_Pos)
ŒGP_INTSRC_INTSRC1_Pos (1)
GP_INTSRC_INTSRC1_Msk (0x1ul << GP_INTSRC_INTSRC1_Pos)
GP_INTSRC_INTSRC2_Pos (2)
GP_INTSRC_INTSRC2_Msk (0x1ul << GP_INTSRC_INTSRC2_Pos)
’GP_INTSRC_INTSRC3_Pos (3)
“GP_INTSRC_INTSRC3_Msk (0x1ul << GP_INTSRC_INTSRC3_Pos)
•GP_INTSRC_INTSRC4_Pos (4)
–GP_INTSRC_INTSRC4_Msk (0x1ul << GP_INTSRC_INTSRC4_Pos)
˜GP_INTSRC_INTSRC5_Pos (5)
™GP_INTSRC_INTSRC5_Msk (0x1ul << GP_INTSRC_INTSRC5_Pos)
›GP_INTSRC_INTSRC6_Pos (6)
œGP_INTSRC_INTSRC6_Msk (0x1ul << GP_INTSRC_INTSRC6_Pos)
žGP_INTSRC_INTSRC7_Pos (7)
ŸGP_INTSRC_INTSRC7_Msk (0x1ul << GP_INTSRC_INTSRC7_Pos)
¡GP_INTSRC_INTSRC8_Pos (8)
¢GP_INTSRC_INTSRC8_Msk (0x1ul << GP_INTSRC_INTSRC8_Pos)
¤GP_INTSRC_INTSRC9_Pos (9)
¥GP_INTSRC_INTSRC9_Msk (0x1ul << GP_INTSRC_INTSRC9_Pos)
§GP_INTSRC_INTSRC10_Pos (10)
¨GP_INTSRC_INTSRC10_Msk (0x1ul << GP_INTSRC_INTSRC10_Pos)
ªGP_INTSRC_INTSRC11_Pos (11)
«GP_INTSRC_INTSRC11_Msk (0x1ul << GP_INTSRC_INTSRC11_Pos)
­GP_INTSRC_INTSRC12_Pos (12)
®GP_INTSRC_INTSRC12_Msk (0x1ul << GP_INTSRC_INTSRC12_Pos)
°GP_INTSRC_INTSRC13_Pos (13)
±GP_INTSRC_INTSRC13_Msk (0x1ul << GP_INTSRC_INTSRC13_Pos)
³GP_INTSRC_INTSRC14_Pos (14)
´GP_INTSRC_INTSRC14_Msk (0x1ul << GP_INTSRC_INTSRC14_Pos)
¶GP_INTSRC_INTSRC15_Pos (15)
·GP_INTSRC_INTSRC15_Msk (0x1ul << GP_INTSRC_INTSRC15_Pos)
¹GP_MODE_MODE0_Pos (0)
ºGP_MODE_MODE0_Msk (0x3ul << GP_MODE_MODE0_Pos)
¼GP_MODE_MODE1_Pos (2)
½GP_MODE_MODE1_Msk (0x3ul << GP_MODE_MODE1_Pos)
¿GP_MODE_MODE2_Pos (4)
ÀGP_MODE_MODE2_Msk (0x3ul << GP_MODE_MODE2_Pos)
ÂGP_MODE_MODE3_Pos (6)
ÃGP_MODE_MODE3_Msk (0x3ul << GP_MODE_MODE3_Pos)
ÅGP_MODE_MODE4_Pos (8)
ÆGP_MODE_MODE4_Msk (0x3ul << GP_MODE_MODE4_Pos)
ÈGP_MODE_MODE5_Pos (10)
ÉGP_MODE_MODE5_Msk (0x3ul << GP_MODE_MODE5_Pos)
ËGP_DINOFF_DINOFF0_Pos (16)
ÌGP_DINOFF_DINOFF0_Msk (0x1ul << GP_DINOFF_DINOFF0_Pos)
ÎGP_DINOFF_DINOFF1_Pos (17)
ÏGP_DINOFF_DINOFF1_Msk (0x1ul << GP_DINOFF_DINOFF1_Pos)
ÑGP_DINOFF_DINOFF2_Pos (18)
ÒGP_DINOFF_DINOFF2_Msk (0x1ul << GP_DINOFF_DINOFF2_Pos)
ÔGP_DINOFF_DINOFF3_Pos (19)
ÕGP_DINOFF_DINOFF3_Msk (0x1ul << GP_DINOFF_DINOFF3_Pos)
×GP_DINOFF_DINOFF4_Pos (20)
ØGP_DINOFF_DINOFF4_Msk (0x1ul << GP_DINOFF_DINOFF4_Pos)
ÚGP_DINOFF_DINOFF5_Pos (21)
ÛGP_DINOFF_DINOFF5_Msk (0x1ul << GP_DINOFF_DINOFF5_Pos)
ÝGP_DINOFF_DINOFF6_Pos (22)
ÞGP_DINOFF_DINOFF6_Msk (0x1ul << GP_DINOFF_DINOFF6_Pos)
àGP_DINOFF_DINOFF7_Pos (23)
áGP_DINOFF_DINOFF7_Msk (0x1ul << GP_DINOFF_DINOFF7_Pos)
ãGP_DOUT_DOUT0_Pos (0)
äGP_DOUT_DOUT0_Msk (0x1ul << GP_DOUT_DOUT0_Pos)
æGP_DOUT_DOUT1_Pos (1)
çGP_DOUT_DOUT1_Msk (0x1ul << GP_DOUT_DOUT1_Pos)
éGP_DOUT_DOUT2_Pos (2)
êGP_DOUT_DOUT2_Msk (0x1ul << GP_DOUT_DOUT2_Pos)
ìGP_DOUT_DOUT3_Pos (3)
íGP_DOUT_DOUT3_Msk (0x1ul << GP_DOUT_DOUT3_Pos)
ïGP_DOUT_DOUT4_Pos (4)
ðGP_DOUT_DOUT4_Msk (0x1ul << GP_DOUT_DOUT4_Pos)
òGP_DOUT_DOUT5_Pos (5)
óGP_DOUT_DOUT5_Msk (0x1ul << GP_DOUT_DOUT5_Pos)
õGP_DOUT_DOUT6_Pos (6)
öGP_DOUT_DOUT6_Msk (0x1ul << GP_DOUT_DOUT6_Pos)
øGP_DOUT_DOUT7_Pos (7)
ùGP_DOUT_DOUT7_Msk (0x1ul << GP_DOUT_DOUT7_Pos)
ûGP_DATMSK_DATMSK0_Pos (0)
üGP_DATMSK_DATMSK0_Msk (0x1ul << GP_DATMSK_DATMSK0_Pos)
þGP_DATMSK_DATMSK1_Pos (1)
ÿGP_DATMSK_DATMSK1_Msk (0x1ul << GP_DATMSK_DATMSK1_Pos)
GP_DATMSK_DATMSK2_Pos (2)
‚GP_DATMSK_DATMSK2_Msk (0x1ul << GP_DATMSK_DATMSK2_Pos)
„GP_DATMSK_DATMSK3_Pos (3)
…GP_DATMSK_DATMSK3_Msk (0x1ul << GP_DATMSK_DATMSK3_Pos)
‡GP_DATMSK_DATMSK4_Pos (4)
ˆGP_DATMSK_DATMSK4_Msk (0x1ul << GP_DATMSK_DATMSK4_Pos)
ŠGP_DATMSK_DATMSK5_Pos (5)
‹GP_DATMSK_DATMSK5_Msk (0x1ul << GP_DATMSK_DATMSK5_Pos)
GP_DATMSK_DATMSK6_Pos (6)
ŽGP_DATMSK_DATMSK6_Msk (0x1ul << GP_DATMSK_DATMSK6_Pos)
GP_DATMSK_DATMSK7_Pos (7)
‘GP_DATMSK_DATMSK7_Msk (0x1ul << GP_DATMSK_DATMSK7_Pos)
“GP_PIN_PIN0_Pos (0)
”GP_PIN_PIN0_Msk (0x1ul << GP_PIN_PIN0_Pos)
–GP_PIN_PIN1_Pos (1)
—GP_PIN_PIN1_Msk (0x1ul << GP_PIN_PIN1_Pos)
™GP_PIN_PIN2_Pos (2)
šGP_PIN_PIN2_Msk (0x1ul << GP_PIN_PIN2_Pos)
œGP_PIN_PIN3_Pos (3)
GP_PIN_PIN3_Msk (0x1ul << GP_PIN_PIN3_Pos)
ŸGP_PIN_PIN4_Pos (4)
 GP_PIN_PIN4_Msk (0x1ul << GP_PIN_PIN4_Pos)
¢GP_PIN_PIN5_Pos (5)
£GP_PIN_PIN5_Msk (0x1ul << GP_PIN_PIN5_Pos)
¥GP_PIN_PIN6_Pos (6)
¦GP_PIN_PIN6_Msk (0x1ul << GP_PIN_PIN6_Pos)
¨GP_PIN_PIN7_Pos (7)
©GP_PIN_PIN7_Msk (0x1ul << GP_PIN_PIN7_Pos)
«GP_DBEN_DBEN0_Pos (0)
¬GP_DBEN_DBEN0_Msk (0x1ul << GP_DBEN_DBEN0_Pos)
®GP_DBEN_DBEN1_Pos (1)
¯GP_DBEN_DBEN1_Msk (0x1ul << GP_DBEN_DBEN1_Pos)
±GP_DBEN_DBEN2_Pos (2)
²GP_DBEN_DBEN2_Msk (0x1ul << GP_DBEN_DBEN2_Pos)
´GP_DBEN_DBEN3_Pos (3)
µGP_DBEN_DBEN3_Msk (0x1ul << GP_DBEN_DBEN3_Pos)
·GP_DBEN_DBEN4_Pos (4)
¸GP_DBEN_DBEN4_Msk (0x1ul << GP_DBEN_DBEN4_Pos)
ºGP_DBEN_DBEN5_Pos (5)
»GP_DBEN_DBEN5_Msk (0x1ul << GP_DBEN_DBEN5_Pos)
½GP_DBEN_DBEN6_Pos (6)
¾GP_DBEN_DBEN6_Msk (0x1ul << GP_DBEN_DBEN6_Pos)
ÀGP_DBEN_DBEN7_Pos (7)
ÁGP_DBEN_DBEN7_Msk (0x1ul << GP_DBEN_DBEN7_Pos)
ÃGP_INTTYPE_TYPE0_Pos (0)
ÄGP_INTTYPE_TYPE0_Msk (0x1ul << GP_INTTYPE_TYPE0_Pos)
ÆGP_INTTYPE_TYPE1_Pos (1)
ÇGP_INTTYPE_TYPE1_Msk (0x1ul << GP_INTTYPE_TYPE1_Pos)
ÉGP_INTTYPE_TYPE2_Pos (2)
ÊGP_INTTYPE_TYPE2_Msk (0x1ul << GP_INTTYPE_TYPE2_Pos)
ÌGP_INTTYPE_TYPE3_Pos (3)
ÍGP_INTTYPE_TYPE3_Msk (0x1ul << GP_INTTYPE_TYPE3_Pos)
ÏGP_INTTYPE_TYPE4_Pos (4)
ÐGP_INTTYPE_TYPE4_Msk (0x1ul << GP_INTTYPE_TYPE4_Pos)
ÒGP_INTTYPE_TYPE5_Pos (5)
ÓGP_INTTYPE_TYPE5_Msk (0x1ul << GP_INTTYPE_TYPE5_Pos)
ÕGP_INTTYPE_TYPE6_Pos (6)
ÖGP_INTTYPE_TYPE6_Msk (0x1ul << GP_INTTYPE_TYPE6_Pos)
ØGP_INTTYPE_TYPE7_Pos (7)
ÙGP_INTTYPE_TYPE7_Msk (0x1ul << GP_INTTYPE_TYPE7_Pos)
ÛGP_INTEN_FLIEN0_Pos (0)
ÜGP_INTEN_FLIEN0_Msk (0x1ul << GP_INTEN_FLIEN0_Pos)
ÞGP_INTEN_FLIEN1_Pos (1)
ßGP_INTEN_FLIEN1_Msk (0x1ul << GP_INTEN_FLIEN1_Pos)
áGP_INTEN_FLIEN2_Pos (2)
âGP_INTEN_FLIEN2_Msk (0x1ul << GP_INTEN_FLIEN2_Pos)
äGP_INTEN_FLIEN3_Pos (3)
åGP_INTEN_FLIEN3_Msk (0x1ul << GP_INTEN_FLIEN3_Pos)
çGP_INTEN_FLIEN4_Pos (4)
èGP_INTEN_FLIEN4_Msk (0x1ul << GP_INTEN_FLIEN4_Pos)
êGP_INTEN_FLIEN5_Pos (5)
ëGP_INTEN_FLIEN5_Msk (0x1ul << GP_INTEN_FLIEN5_Pos)
íGP_INTEN_FLIEN6_Pos (6)
îGP_INTEN_FLIEN6_Msk (0x1ul << GP_INTEN_FLIEN6_Pos)
ðGP_INTEN_FLIEN7_Pos (7)
ñGP_INTEN_FLIEN7_Msk (0x1ul << GP_INTEN_FLIEN7_Pos)
óGP_INTEN_RHIEN0_Pos (16)
ôGP_INTEN_RHIEN0_Msk (0x1ul << GP_INTEN_RHIEN0_Pos)
öGP_INTEN_RHIEN1_Pos (17)
÷GP_INTEN_RHIEN1_Msk (0x1ul << GP_INTEN_RHIEN1_Pos)
ùGP_INTEN_RHIEN2_Pos (18)
úGP_INTEN_RHIEN2_Msk (0x1ul << GP_INTEN_RHIEN2_Pos)
üGP_INTEN_RHIEN3_Pos (19)
ýGP_INTEN_RHIEN3_Msk (0x1ul << GP_INTEN_RHIEN3_Pos)
ÿGP_INTEN_RHIEN4_Pos (20)
€GP_INTEN_RHIEN4_Msk (0x1ul << GP_INTEN_RHIEN4_Pos)
‚GP_INTEN_RHIEN5_Pos (21)
ƒGP_INTEN_RHIEN5_Msk (0x1ul << GP_INTEN_RHIEN5_Pos)
…GP_INTEN_RHIEN6_Pos (22)
†GP_INTEN_RHIEN6_Msk (0x1ul << GP_INTEN_RHIEN6_Pos)
ˆGP_INTEN_RHIEN7_Pos (23)
‰GP_INTEN_RHIEN7_Msk (0x1ul << GP_INTEN_RHIEN7_Pos)
‹GP_INTSRC_INTSRC0_Pos (0)
ŒGP_INTSRC_INTSRC0_Msk (0x1ul << GP_INTSRC_INTSRC0_Pos)
ŽGP_INTSRC_INTSRC1_Pos (1)
GP_INTSRC_INTSRC1_Msk (0x1ul << GP_INTSRC_INTSRC1_Pos)
‘GP_INTSRC_INTSRC2_Pos (2)
’GP_INTSRC_INTSRC2_Msk (0x1ul << GP_INTSRC_INTSRC2_Pos)
”GP_INTSRC_INTSRC3_Pos (3)
•GP_INTSRC_INTSRC3_Msk (0x1ul << GP_INTSRC_INTSRC3_Pos)
—GP_INTSRC_INTSRC4_Pos (4)
˜GP_INTSRC_INTSRC4_Msk (0x1ul << GP_INTSRC_INTSRC4_Pos)
šGP_INTSRC_INTSRC5_Pos (5)
›GP_INTSRC_INTSRC5_Msk (0x1ul << GP_INTSRC_INTSRC5_Pos)
GP_INTSRC_INTSRC6_Pos (6)
žGP_INTSRC_INTSRC6_Msk (0x1ul << GP_INTSRC_INTSRC6_Pos)
 GP_INTSRC_INTSRC7_Pos (7)
¡GP_INTSRC_INTSRC7_Msk (0x1ul << GP_INTSRC_INTSRC7_Pos)
£GP_INTSRC_INTSRC8_Pos (8)
¤GP_INTSRC_INTSRC8_Msk (0x1ul << GP_INTSRC_INTSRC8_Pos)
¦GP_INTSRC_INTSRC9_Pos (9)
§GP_INTSRC_INTSRC9_Msk (0x1ul << GP_INTSRC_INTSRC9_Pos)
©GP_INTSRC_INTSRC10_Pos (10)
ªGP_INTSRC_INTSRC10_Msk (0x1ul << GP_INTSRC_INTSRC10_Pos)
¬GP_INTSRC_INTSRC11_Pos (11)
­GP_INTSRC_INTSRC11_Msk (0x1ul << GP_INTSRC_INTSRC11_Pos)
¯GP_INTSRC_INTSRC12_Pos (12)
°GP_INTSRC_INTSRC12_Msk (0x1ul << GP_INTSRC_INTSRC12_Pos)
²GP_INTSRC_INTSRC13_Pos (13)
³GP_INTSRC_INTSRC13_Msk (0x1ul << GP_INTSRC_INTSRC13_Pos)
µGP_INTSRC_INTSRC14_Pos (14)
¶GP_INTSRC_INTSRC14_Msk (0x1ul << GP_INTSRC_INTSRC14_Pos)
¸GP_INTSRC_INTSRC15_Pos (15)
¹GP_INTSRC_INTSRC15_Msk (0x1ul << GP_INTSRC_INTSRC15_Pos)
»GP_MODE_MODE0_Pos (0)
¼GP_MODE_MODE0_Msk (0x3ul << GP_MODE_MODE0_Pos)
¾GP_MODE_MODE1_Pos (2)
¿GP_MODE_MODE1_Msk (0x3ul << GP_MODE_MODE1_Pos)
ÁGP_MODE_MODE2_Pos (4)
ÂGP_MODE_MODE2_Msk (0x3ul << GP_MODE_MODE2_Pos)
ÄGP_MODE_MODE3_Pos (6)
ÅGP_MODE_MODE3_Msk (0x3ul << GP_MODE_MODE3_Pos)
ÇGP_MODE_MODE4_Pos (8)
ÈGP_MODE_MODE4_Msk (0x3ul << GP_MODE_MODE4_Pos)
ÊGP_MODE_MODE5_Pos (10)
ËGP_MODE_MODE5_Msk (0x3ul << GP_MODE_MODE5_Pos)
ÍGP_DINOFF_DINOFF0_Pos (16)
ÎGP_DINOFF_DINOFF0_Msk (0x1ul << GP_DINOFF_DINOFF0_Pos)
ÐGP_DINOFF_DINOFF1_Pos (17)
ÑGP_DINOFF_DINOFF1_Msk (0x1ul << GP_DINOFF_DINOFF1_Pos)
ÓGP_DINOFF_DINOFF2_Pos (18)
ÔGP_DINOFF_DINOFF2_Msk (0x1ul << GP_DINOFF_DINOFF2_Pos)
ÖGP_DINOFF_DINOFF3_Pos (19)
×GP_DINOFF_DINOFF3_Msk (0x1ul << GP_DINOFF_DINOFF3_Pos)
ÙGP_DINOFF_DINOFF4_Pos (20)
ÚGP_DINOFF_DINOFF4_Msk (0x1ul << GP_DINOFF_DINOFF4_Pos)
ÜGP_DINOFF_DINOFF5_Pos (21)
ÝGP_DINOFF_DINOFF5_Msk (0x1ul << GP_DINOFF_DINOFF5_Pos)
ßGP_DINOFF_DINOFF6_Pos (22)
àGP_DINOFF_DINOFF6_Msk (0x1ul << GP_DINOFF_DINOFF6_Pos)
âGP_DINOFF_DINOFF7_Pos (23)
ãGP_DINOFF_DINOFF7_Msk (0x1ul << GP_DINOFF_DINOFF7_Pos)
åGP_DOUT_DOUT0_Pos (0)
æGP_DOUT_DOUT0_Msk (0x1ul << GP_DOUT_DOUT0_Pos)
èGP_DOUT_DOUT1_Pos (1)
éGP_DOUT_DOUT1_Msk (0x1ul << GP_DOUT_DOUT1_Pos)
ëGP_DOUT_DOUT2_Pos (2)
ìGP_DOUT_DOUT2_Msk (0x1ul << GP_DOUT_DOUT2_Pos)
îGP_DOUT_DOUT3_Pos (3)
ïGP_DOUT_DOUT3_Msk (0x1ul << GP_DOUT_DOUT3_Pos)
ñGP_DOUT_DOUT4_Pos (4)
òGP_DOUT_DOUT4_Msk (0x1ul << GP_DOUT_DOUT4_Pos)
ôGP_DOUT_DOUT5_Pos (5)
õGP_DOUT_DOUT5_Msk (0x1ul << GP_DOUT_DOUT5_Pos)
÷GP_DOUT_DOUT6_Pos (6)
øGP_DOUT_DOUT6_Msk (0x1ul << GP_DOUT_DOUT6_Pos)
úGP_DOUT_DOUT7_Pos (7)
ûGP_DOUT_DOUT7_Msk (0x1ul << GP_DOUT_DOUT7_Pos)
ýGP_DATMSK_DATMSK0_Pos (0)
þGP_DATMSK_DATMSK0_Msk (0x1ul << GP_DATMSK_DATMSK0_Pos)
€GP_DATMSK_DATMSK1_Pos (1)
GP_DATMSK_DATMSK1_Msk (0x1ul << GP_DATMSK_DATMSK1_Pos)
ƒGP_DATMSK_DATMSK2_Pos (2)
„GP_DATMSK_DATMSK2_Msk (0x1ul << GP_DATMSK_DATMSK2_Pos)
†GP_DATMSK_DATMSK3_Pos (3)
‡GP_DATMSK_DATMSK3_Msk (0x1ul << GP_DATMSK_DATMSK3_Pos)
‰GP_DATMSK_DATMSK4_Pos (4)
ŠGP_DATMSK_DATMSK4_Msk (0x1ul << GP_DATMSK_DATMSK4_Pos)
ŒGP_DATMSK_DATMSK5_Pos (5)
GP_DATMSK_DATMSK5_Msk (0x1ul << GP_DATMSK_DATMSK5_Pos)
GP_DATMSK_DATMSK6_Pos (6)
GP_DATMSK_DATMSK6_Msk (0x1ul << GP_DATMSK_DATMSK6_Pos)
’GP_DATMSK_DATMSK7_Pos (7)
“GP_DATMSK_DATMSK7_Msk (0x1ul << GP_DATMSK_DATMSK7_Pos)
•GP_PIN_PIN0_Pos (0)
–GP_PIN_PIN0_Msk (0x1ul << GP_PIN_PIN0_Pos)
˜GP_PIN_PIN1_Pos (1)
™GP_PIN_PIN1_Msk (0x1ul << GP_PIN_PIN1_Pos)
›GP_PIN_PIN2_Pos (2)
œGP_PIN_PIN2_Msk (0x1ul << GP_PIN_PIN2_Pos)
žGP_PIN_PIN3_Pos (3)
ŸGP_PIN_PIN3_Msk (0x1ul << GP_PIN_PIN3_Pos)
¡GP_PIN_PIN4_Pos (4)
¢GP_PIN_PIN4_Msk (0x1ul << GP_PIN_PIN4_Pos)
¤GP_PIN_PIN5_Pos (5)
¥GP_PIN_PIN5_Msk (0x1ul << GP_PIN_PIN5_Pos)
§GP_PIN_PIN6_Pos (6)
¨GP_PIN_PIN6_Msk (0x1ul << GP_PIN_PIN6_Pos)
ªGP_PIN_PIN7_Pos (7)
«GP_PIN_PIN7_Msk (0x1ul << GP_PIN_PIN7_Pos)
­GP_DBEN_DBEN0_Pos (0)
®GP_DBEN_DBEN0_Msk (0x1ul << GP_DBEN_DBEN0_Pos)
°GP_DBEN_DBEN1_Pos (1)
±GP_DBEN_DBEN1_Msk (0x1ul << GP_DBEN_DBEN1_Pos)
³GP_DBEN_DBEN2_Pos (2)
´GP_DBEN_DBEN2_Msk (0x1ul << GP_DBEN_DBEN2_Pos)
¶GP_DBEN_DBEN3_Pos (3)
·GP_DBEN_DBEN3_Msk (0x1ul << GP_DBEN_DBEN3_Pos)
¹GP_DBEN_DBEN4_Pos (4)
ºGP_DBEN_DBEN4_Msk (0x1ul << GP_DBEN_DBEN4_Pos)
¼GP_DBEN_DBEN5_Pos (5)
½GP_DBEN_DBEN5_Msk (0x1ul << GP_DBEN_DBEN5_Pos)
¿GP_DBEN_DBEN6_Pos (6)
ÀGP_DBEN_DBEN6_Msk (0x1ul << GP_DBEN_DBEN6_Pos)
ÂGP_DBEN_DBEN7_Pos (7)
ÃGP_DBEN_DBEN7_Msk (0x1ul << GP_DBEN_DBEN7_Pos)
ÅGP_INTTYPE_TYPE0_Pos (0)
ÆGP_INTTYPE_TYPE0_Msk (0x1ul << GP_INTTYPE_TYPE0_Pos)
ÈGP_INTTYPE_TYPE1_Pos (1)
ÉGP_INTTYPE_TYPE1_Msk (0x1ul << GP_INTTYPE_TYPE1_Pos)
ËGP_INTTYPE_TYPE2_Pos (2)
ÌGP_INTTYPE_TYPE2_Msk (0x1ul << GP_INTTYPE_TYPE2_Pos)
ÎGP_INTTYPE_TYPE3_Pos (3)
ÏGP_INTTYPE_TYPE3_Msk (0x1ul << GP_INTTYPE_TYPE3_Pos)
ÑGP_INTTYPE_TYPE4_Pos (4)
ÒGP_INTTYPE_TYPE4_Msk (0x1ul << GP_INTTYPE_TYPE4_Pos)
ÔGP_INTTYPE_TYPE5_Pos (5)
ÕGP_INTTYPE_TYPE5_Msk (0x1ul << GP_INTTYPE_TYPE5_Pos)
×GP_INTTYPE_TYPE6_Pos (6)
ØGP_INTTYPE_TYPE6_Msk (0x1ul << GP_INTTYPE_TYPE6_Pos)
ÚGP_INTTYPE_TYPE7_Pos (7)
ÛGP_INTTYPE_TYPE7_Msk (0x1ul << GP_INTTYPE_TYPE7_Pos)
ÝGP_INTEN_FLIEN0_Pos (0)
ÞGP_INTEN_FLIEN0_Msk (0x1ul << GP_INTEN_FLIEN0_Pos)
àGP_INTEN_FLIEN1_Pos (1)
áGP_INTEN_FLIEN1_Msk (0x1ul << GP_INTEN_FLIEN1_Pos)
ãGP_INTEN_FLIEN2_Pos (2)
äGP_INTEN_FLIEN2_Msk (0x1ul << GP_INTEN_FLIEN2_Pos)
æGP_INTEN_FLIEN3_Pos (3)
çGP_INTEN_FLIEN3_Msk (0x1ul << GP_INTEN_FLIEN3_Pos)
éGP_INTEN_FLIEN4_Pos (4)
êGP_INTEN_FLIEN4_Msk (0x1ul << GP_INTEN_FLIEN4_Pos)
ìGP_INTEN_FLIEN5_Pos (5)
íGP_INTEN_FLIEN5_Msk (0x1ul << GP_INTEN_FLIEN5_Pos)
ïGP_INTEN_FLIEN6_Pos (6)
ðGP_INTEN_FLIEN6_Msk (0x1ul << GP_INTEN_FLIEN6_Pos)
òGP_INTEN_FLIEN7_Pos (7)
óGP_INTEN_FLIEN7_Msk (0x1ul << GP_INTEN_FLIEN7_Pos)
õGP_INTEN_RHIEN0_Pos (16)
öGP_INTEN_RHIEN0_Msk (0x1ul << GP_INTEN_RHIEN0_Pos)
øGP_INTEN_RHIEN1_Pos (17)
ùGP_INTEN_RHIEN1_Msk (0x1ul << GP_INTEN_RHIEN1_Pos)
ûGP_INTEN_RHIEN2_Pos (18)
üGP_INTEN_RHIEN2_Msk (0x1ul << GP_INTEN_RHIEN2_Pos)
þGP_INTEN_RHIEN3_Pos (19)
ÿGP_INTEN_RHIEN3_Msk (0x1ul << GP_INTEN_RHIEN3_Pos)
GP_INTEN_RHIEN4_Pos (20)
‚GP_INTEN_RHIEN4_Msk (0x1ul << GP_INTEN_RHIEN4_Pos)
„GP_INTEN_RHIEN5_Pos (21)
…GP_INTEN_RHIEN5_Msk (0x1ul << GP_INTEN_RHIEN5_Pos)
‡GP_INTEN_RHIEN6_Pos (22)
ˆGP_INTEN_RHIEN6_Msk (0x1ul << GP_INTEN_RHIEN6_Pos)
ŠGP_INTEN_RHIEN7_Pos (23)
‹GP_INTEN_RHIEN7_Msk (0x1ul << GP_INTEN_RHIEN7_Pos)
GP_INTSRC_INTSRC0_Pos (0)
ŽGP_INTSRC_INTSRC0_Msk (0x1ul << GP_INTSRC_INTSRC0_Pos)
GP_INTSRC_INTSRC1_Pos (1)
‘GP_INTSRC_INTSRC1_Msk (0x1ul << GP_INTSRC_INTSRC1_Pos)
“GP_INTSRC_INTSRC2_Pos (2)
”GP_INTSRC_INTSRC2_Msk (0x1ul << GP_INTSRC_INTSRC2_Pos)
–GP_INTSRC_INTSRC3_Pos (3)
—GP_INTSRC_INTSRC3_Msk (0x1ul << GP_INTSRC_INTSRC3_Pos)
™GP_INTSRC_INTSRC4_Pos (4)
šGP_INTSRC_INTSRC4_Msk (0x1ul << GP_INTSRC_INTSRC4_Pos)
œGP_INTSRC_INTSRC5_Pos (5)
GP_INTSRC_INTSRC5_Msk (0x1ul << GP_INTSRC_INTSRC5_Pos)
ŸGP_INTSRC_INTSRC6_Pos (6)
 GP_INTSRC_INTSRC6_Msk (0x1ul << GP_INTSRC_INTSRC6_Pos)
¢GP_INTSRC_INTSRC7_Pos (7)
£GP_INTSRC_INTSRC7_Msk (0x1ul << GP_INTSRC_INTSRC7_Pos)
¥GP_INTSRC_INTSRC8_Pos (8)
¦GP_INTSRC_INTSRC8_Msk (0x1ul << GP_INTSRC_INTSRC8_Pos)
¨GP_INTSRC_INTSRC9_Pos (9)
©GP_INTSRC_INTSRC9_Msk (0x1ul << GP_INTSRC_INTSRC9_Pos)
«GP_INTSRC_INTSRC10_Pos (10)
¬GP_INTSRC_INTSRC10_Msk (0x1ul << GP_INTSRC_INTSRC10_Pos)
®GP_INTSRC_INTSRC11_Pos (11)
¯GP_INTSRC_INTSRC11_Msk (0x1ul << GP_INTSRC_INTSRC11_Pos)
±GP_INTSRC_INTSRC12_Pos (12)
²GP_INTSRC_INTSRC12_Msk (0x1ul << GP_INTSRC_INTSRC12_Pos)
´GP_INTSRC_INTSRC13_Pos (13)
µGP_INTSRC_INTSRC13_Msk (0x1ul << GP_INTSRC_INTSRC13_Pos)
·GP_INTSRC_INTSRC14_Pos (14)
¸GP_INTSRC_INTSRC14_Msk (0x1ul << GP_INTSRC_INTSRC14_Pos)
ºGP_INTSRC_INTSRC15_Pos (15)
»GP_INTSRC_INTSRC15_Msk (0x1ul << GP_INTSRC_INTSRC15_Pos)
½GP_MODE_MODE0_Pos (0)
¾GP_MODE_MODE0_Msk (0x3ul << GP_MODE_MODE0_Pos)
ÀGP_MODE_MODE1_Pos (2)
ÁGP_MODE_MODE1_Msk (0x3ul << GP_MODE_MODE1_Pos)
ÃGP_MODE_MODE2_Pos (4)
ÄGP_MODE_MODE2_Msk (0x3ul << GP_MODE_MODE2_Pos)
ÆGP_MODE_MODE3_Pos (6)
ÇGP_MODE_MODE3_Msk (0x3ul << GP_MODE_MODE3_Pos)
ÉGP_MODE_MODE4_Pos (8)
ÊGP_MODE_MODE4_Msk (0x3ul << GP_MODE_MODE4_Pos)
ÌGP_MODE_MODE5_Pos (10)
ÍGP_MODE_MODE5_Msk (0x3ul << GP_MODE_MODE5_Pos)
ÏGP_DINOFF_DINOFF0_Pos (16)
ÐGP_DINOFF_DINOFF0_Msk (0x1ul << GP_DINOFF_DINOFF0_Pos)
ÒGP_DINOFF_DINOFF1_Pos (17)
ÓGP_DINOFF_DINOFF1_Msk (0x1ul << GP_DINOFF_DINOFF1_Pos)
ÕGP_DINOFF_DINOFF2_Pos (18)
ÖGP_DINOFF_DINOFF2_Msk (0x1ul << GP_DINOFF_DINOFF2_Pos)
ØGP_DINOFF_DINOFF3_Pos (19)
ÙGP_DINOFF_DINOFF3_Msk (0x1ul << GP_DINOFF_DINOFF3_Pos)
ÛGP_DINOFF_DINOFF4_Pos (20)
ÜGP_DINOFF_DINOFF4_Msk (0x1ul << GP_DINOFF_DINOFF4_Pos)
ÞGP_DINOFF_DINOFF5_Pos (21)
ßGP_DINOFF_DINOFF5_Msk (0x1ul << GP_DINOFF_DINOFF5_Pos)
áGP_DINOFF_DINOFF6_Pos (22)
âGP_DINOFF_DINOFF6_Msk (0x1ul << GP_DINOFF_DINOFF6_Pos)
äGP_DINOFF_DINOFF7_Pos (23)
åGP_DINOFF_DINOFF7_Msk (0x1ul << GP_DINOFF_DINOFF7_Pos)
çGP_DOUT_DOUT0_Pos (0)
èGP_DOUT_DOUT0_Msk (0x1ul << GP_DOUT_DOUT0_Pos)
êGP_DOUT_DOUT1_Pos (1)
ëGP_DOUT_DOUT1_Msk (0x1ul << GP_DOUT_DOUT1_Pos)
íGP_DOUT_DOUT2_Pos (2)
îGP_DOUT_DOUT2_Msk (0x1ul << GP_DOUT_DOUT2_Pos)
ðGP_DOUT_DOUT3_Pos (3)
ñGP_DOUT_DOUT3_Msk (0x1ul << GP_DOUT_DOUT3_Pos)
óGP_DOUT_DOUT4_Pos (4)
ôGP_DOUT_DOUT4_Msk (0x1ul << GP_DOUT_DOUT4_Pos)
öGP_DOUT_DOUT5_Pos (5)
÷GP_DOUT_DOUT5_Msk (0x1ul << GP_DOUT_DOUT5_Pos)
ùGP_DOUT_DOUT6_Pos (6)
úGP_DOUT_DOUT6_Msk (0x1ul << GP_DOUT_DOUT6_Pos)
üGP_DOUT_DOUT7_Pos (7)
ýGP_DOUT_DOUT7_Msk (0x1ul << GP_DOUT_DOUT7_Pos)
ÿGP_DATMSK_DATMSK0_Pos (0)
€GP_DATMSK_DATMSK0_Msk (0x1ul << GP_DATMSK_DATMSK0_Pos)
‚GP_DATMSK_DATMSK1_Pos (1)
ƒGP_DATMSK_DATMSK1_Msk (0x1ul << GP_DATMSK_DATMSK1_Pos)
…GP_DATMSK_DATMSK2_Pos (2)
†GP_DATMSK_DATMSK2_Msk (0x1ul << GP_DATMSK_DATMSK2_Pos)
ˆGP_DATMSK_DATMSK3_Pos (3)
‰GP_DATMSK_DATMSK3_Msk (0x1ul << GP_DATMSK_DATMSK3_Pos)
‹GP_DATMSK_DATMSK4_Pos (4)
ŒGP_DATMSK_DATMSK4_Msk (0x1ul << GP_DATMSK_DATMSK4_Pos)
ŽGP_DATMSK_DATMSK5_Pos (5)
GP_DATMSK_DATMSK5_Msk (0x1ul << GP_DATMSK_DATMSK5_Pos)
‘GP_DATMSK_DATMSK6_Pos (6)
’GP_DATMSK_DATMSK6_Msk (0x1ul << GP_DATMSK_DATMSK6_Pos)
”GP_DATMSK_DATMSK7_Pos (7)
•GP_DATMSK_DATMSK7_Msk (0x1ul << GP_DATMSK_DATMSK7_Pos)
—GP_PIN_PIN0_Pos (0)
˜GP_PIN_PIN0_Msk (0x1ul << GP_PIN_PIN0_Pos)
šGP_PIN_PIN1_Pos (1)
›GP_PIN_PIN1_Msk (0x1ul << GP_PIN_PIN1_Pos)
GP_PIN_PIN2_Pos (2)
žGP_PIN_PIN2_Msk (0x1ul << GP_PIN_PIN2_Pos)
 GP_PIN_PIN3_Pos (3)
¡GP_PIN_PIN3_Msk (0x1ul << GP_PIN_PIN3_Pos)
£GP_PIN_PIN4_Pos (4)
¤GP_PIN_PIN4_Msk (0x1ul << GP_PIN_PIN4_Pos)
¦GP_PIN_PIN5_Pos (5)
§GP_PIN_PIN5_Msk (0x1ul << GP_PIN_PIN5_Pos)
©GP_PIN_PIN6_Pos (6)
ªGP_PIN_PIN6_Msk (0x1ul << GP_PIN_PIN6_Pos)
¬GP_PIN_PIN7_Pos (7)
­GP_PIN_PIN7_Msk (0x1ul << GP_PIN_PIN7_Pos)
¯GP_DBEN_DBEN0_Pos (0)
°GP_DBEN_DBEN0_Msk (0x1ul << GP_DBEN_DBEN0_Pos)
²GP_DBEN_DBEN1_Pos (1)
³GP_DBEN_DBEN1_Msk (0x1ul << GP_DBEN_DBEN1_Pos)
µGP_DBEN_DBEN2_Pos (2)
¶GP_DBEN_DBEN2_Msk (0x1ul << GP_DBEN_DBEN2_Pos)
¸GP_DBEN_DBEN3_Pos (3)
¹GP_DBEN_DBEN3_Msk (0x1ul << GP_DBEN_DBEN3_Pos)
»GP_DBEN_DBEN4_Pos (4)
¼GP_DBEN_DBEN4_Msk (0x1ul << GP_DBEN_DBEN4_Pos)
¾GP_DBEN_DBEN5_Pos (5)
¿GP_DBEN_DBEN5_Msk (0x1ul << GP_DBEN_DBEN5_Pos)
ÁGP_DBEN_DBEN6_Pos (6)
ÂGP_DBEN_DBEN6_Msk (0x1ul << GP_DBEN_DBEN6_Pos)
ÄGP_DBEN_DBEN7_Pos (7)
ÅGP_DBEN_DBEN7_Msk (0x1ul << GP_DBEN_DBEN7_Pos)
ÇGP_INTTYPE_TYPE0_Pos (0)
ÈGP_INTTYPE_TYPE0_Msk (0x1ul << GP_INTTYPE_TYPE0_Pos)
ÊGP_INTTYPE_TYPE1_Pos (1)
ËGP_INTTYPE_TYPE1_Msk (0x1ul << GP_INTTYPE_TYPE1_Pos)
ÍGP_INTTYPE_TYPE2_Pos (2)
ÎGP_INTTYPE_TYPE2_Msk (0x1ul << GP_INTTYPE_TYPE2_Pos)
ÐGP_INTTYPE_TYPE3_Pos (3)
ÑGP_INTTYPE_TYPE3_Msk (0x1ul << GP_INTTYPE_TYPE3_Pos)
ÓGP_INTTYPE_TYPE4_Pos (4)
ÔGP_INTTYPE_TYPE4_Msk (0x1ul << GP_INTTYPE_TYPE4_Pos)
ÖGP_INTTYPE_TYPE5_Pos (5)
×GP_INTTYPE_TYPE5_Msk (0x1ul << GP_INTTYPE_TYPE5_Pos)
ÙGP_INTTYPE_TYPE6_Pos (6)
ÚGP_INTTYPE_TYPE6_Msk (0x1ul << GP_INTTYPE_TYPE6_Pos)
ÜGP_INTTYPE_TYPE7_Pos (7)
ÝGP_INTTYPE_TYPE7_Msk (0x1ul << GP_INTTYPE_TYPE7_Pos)
ßGP_INTEN_FLIEN0_Pos (0)
àGP_INTEN_FLIEN0_Msk (0x1ul << GP_INTEN_FLIEN0_Pos)
âGP_INTEN_FLIEN1_Pos (1)
ãGP_INTEN_FLIEN1_Msk (0x1ul << GP_INTEN_FLIEN1_Pos)
åGP_INTEN_FLIEN2_Pos (2)
æGP_INTEN_FLIEN2_Msk (0x1ul << GP_INTEN_FLIEN2_Pos)
èGP_INTEN_FLIEN3_Pos (3)
éGP_INTEN_FLIEN3_Msk (0x1ul << GP_INTEN_FLIEN3_Pos)
ëGP_INTEN_FLIEN4_Pos (4)
ìGP_INTEN_FLIEN4_Msk (0x1ul << GP_INTEN_FLIEN4_Pos)
îGP_INTEN_FLIEN5_Pos (5)
ïGP_INTEN_FLIEN5_Msk (0x1ul << GP_INTEN_FLIEN5_Pos)
ñGP_INTEN_FLIEN6_Pos (6)
òGP_INTEN_FLIEN6_Msk (0x1ul << GP_INTEN_FLIEN6_Pos)
ôGP_INTEN_FLIEN7_Pos (7)
õGP_INTEN_FLIEN7_Msk (0x1ul << GP_INTEN_FLIEN7_Pos)
÷GP_INTEN_RHIEN0_Pos (16)
øGP_INTEN_RHIEN0_Msk (0x1ul << GP_INTEN_RHIEN0_Pos)
úGP_INTEN_RHIEN1_Pos (17)
ûGP_INTEN_RHIEN1_Msk (0x1ul << GP_INTEN_RHIEN1_Pos)
ýGP_INTEN_RHIEN2_Pos (18)
þGP_INTEN_RHIEN2_Msk (0x1ul << GP_INTEN_RHIEN2_Pos)
€GP_INTEN_RHIEN3_Pos (19)
GP_INTEN_RHIEN3_Msk (0x1ul << GP_INTEN_RHIEN3_Pos)
ƒGP_INTEN_RHIEN4_Pos (20)
„GP_INTEN_RHIEN4_Msk (0x1ul << GP_INTEN_RHIEN4_Pos)
†GP_INTEN_RHIEN5_Pos (21)
‡GP_INTEN_RHIEN5_Msk (0x1ul << GP_INTEN_RHIEN5_Pos)
‰GP_INTEN_RHIEN6_Pos (22)
ŠGP_INTEN_RHIEN6_Msk (0x1ul << GP_INTEN_RHIEN6_Pos)
ŒGP_INTEN_RHIEN7_Pos (23)
GP_INTEN_RHIEN7_Msk (0x1ul << GP_INTEN_RHIEN7_Pos)
GP_INTSRC_INTSRC0_Pos (0)
GP_INTSRC_INTSRC0_Msk (0x1ul << GP_INTSRC_INTSRC0_Pos)
’GP_INTSRC_INTSRC1_Pos (1)
“GP_INTSRC_INTSRC1_Msk (0x1ul << GP_INTSRC_INTSRC1_Pos)
•GP_INTSRC_INTSRC2_Pos (2)
–GP_INTSRC_INTSRC2_Msk (0x1ul << GP_INTSRC_INTSRC2_Pos)
˜GP_INTSRC_INTSRC3_Pos (3)
™GP_INTSRC_INTSRC3_Msk (0x1ul << GP_INTSRC_INTSRC3_Pos)
›GP_INTSRC_INTSRC4_Pos (4)
œGP_INTSRC_INTSRC4_Msk (0x1ul << GP_INTSRC_INTSRC4_Pos)
žGP_INTSRC_INTSRC5_Pos (5)
ŸGP_INTSRC_INTSRC5_Msk (0x1ul << GP_INTSRC_INTSRC5_Pos)
¡GP_INTSRC_INTSRC6_Pos (6)
¢GP_INTSRC_INTSRC6_Msk (0x1ul << GP_INTSRC_INTSRC6_Pos)
¤GP_INTSRC_INTSRC7_Pos (7)
¥GP_INTSRC_INTSRC7_Msk (0x1ul << GP_INTSRC_INTSRC7_Pos)
§GP_INTSRC_INTSRC8_Pos (8)
¨GP_INTSRC_INTSRC8_Msk (0x1ul << GP_INTSRC_INTSRC8_Pos)
ªGP_INTSRC_INTSRC9_Pos (9)
«GP_INTSRC_INTSRC9_Msk (0x1ul << GP_INTSRC_INTSRC9_Pos)
­GP_INTSRC_INTSRC10_Pos (10)
®GP_INTSRC_INTSRC10_Msk (0x1ul << GP_INTSRC_INTSRC10_Pos)
°GP_INTSRC_INTSRC11_Pos (11)
±GP_INTSRC_INTSRC11_Msk (0x1ul << GP_INTSRC_INTSRC11_Pos)
³GP_INTSRC_INTSRC12_Pos (12)
´GP_INTSRC_INTSRC12_Msk (0x1ul << GP_INTSRC_INTSRC12_Pos)
¶GP_INTSRC_INTSRC13_Pos (13)
·GP_INTSRC_INTSRC13_Msk (0x1ul << GP_INTSRC_INTSRC13_Pos)
¹GP_INTSRC_INTSRC14_Pos (14)
ºGP_INTSRC_INTSRC14_Msk (0x1ul << GP_INTSRC_INTSRC14_Pos)
¼GP_INTSRC_INTSRC15_Pos (15)
½GP_INTSRC_INTSRC15_Msk (0x1ul << GP_INTSRC_INTSRC15_Pos)
¿GP_MODE_MODE0_Pos (0)
ÀGP_MODE_MODE0_Msk (0x3ul << GP_MODE_MODE0_Pos)
ÂGP_MODE_MODE1_Pos (2)
ÃGP_MODE_MODE1_Msk (0x3ul << GP_MODE_MODE1_Pos)
ÅGP_MODE_MODE2_Pos (4)
ÆGP_MODE_MODE2_Msk (0x3ul << GP_MODE_MODE2_Pos)
ÈGP_MODE_MODE3_Pos (6)
ÉGP_MODE_MODE3_Msk (0x3ul << GP_MODE_MODE3_Pos)
ËGP_MODE_MODE4_Pos (8)
ÌGP_MODE_MODE4_Msk (0x3ul << GP_MODE_MODE4_Pos)
ÎGP_MODE_MODE5_Pos (10)
ÏGP_MODE_MODE5_Msk (0x3ul << GP_MODE_MODE5_Pos)
ÑGP_DINOFF_DINOFF0_Pos (16)
ÒGP_DINOFF_DINOFF0_Msk (0x1ul << GP_DINOFF_DINOFF0_Pos)
ÔGP_DINOFF_DINOFF1_Pos (17)
ÕGP_DINOFF_DINOFF1_Msk (0x1ul << GP_DINOFF_DINOFF1_Pos)
×GP_DINOFF_DINOFF2_Pos (18)
ØGP_DINOFF_DINOFF2_Msk (0x1ul << GP_DINOFF_DINOFF2_Pos)
ÚGP_DINOFF_DINOFF3_Pos (19)
ÛGP_DINOFF_DINOFF3_Msk (0x1ul << GP_DINOFF_DINOFF3_Pos)
ÝGP_DINOFF_DINOFF4_Pos (20)
ÞGP_DINOFF_DINOFF4_Msk (0x1ul << GP_DINOFF_DINOFF4_Pos)
àGP_DINOFF_DINOFF5_Pos (21)
áGP_DINOFF_DINOFF5_Msk (0x1ul << GP_DINOFF_DINOFF5_Pos)
ãGP_DINOFF_DINOFF6_Pos (22)
äGP_DINOFF_DINOFF6_Msk (0x1ul << GP_DINOFF_DINOFF6_Pos)
æGP_DINOFF_DINOFF7_Pos (23)
çGP_DINOFF_DINOFF7_Msk (0x1ul << GP_DINOFF_DINOFF7_Pos)
éGP_DOUT_DOUT0_Pos (0)
êGP_DOUT_DOUT0_Msk (0x1ul << GP_DOUT_DOUT0_Pos)
ìGP_DOUT_DOUT1_Pos (1)
íGP_DOUT_DOUT1_Msk (0x1ul << GP_DOUT_DOUT1_Pos)
ïGP_DOUT_DOUT2_Pos (2)
ðGP_DOUT_DOUT2_Msk (0x1ul << GP_DOUT_DOUT2_Pos)
òGP_DOUT_DOUT3_Pos (3)
óGP_DOUT_DOUT3_Msk (0x1ul << GP_DOUT_DOUT3_Pos)
õGP_DOUT_DOUT4_Pos (4)
öGP_DOUT_DOUT4_Msk (0x1ul << GP_DOUT_DOUT4_Pos)
øGP_DOUT_DOUT5_Pos (5)
ùGP_DOUT_DOUT5_Msk (0x1ul << GP_DOUT_DOUT5_Pos)
ûGP_DOUT_DOUT6_Pos (6)
üGP_DOUT_DOUT6_Msk (0x1ul << GP_DOUT_DOUT6_Pos)
þGP_DOUT_DOUT7_Pos (7)
ÿGP_DOUT_DOUT7_Msk (0x1ul << GP_DOUT_DOUT7_Pos)
GP_DATMSK_DATMSK0_Pos (0)
‚GP_DATMSK_DATMSK0_Msk (0x1ul << GP_DATMSK_DATMSK0_Pos)
„GP_DATMSK_DATMSK1_Pos (1)
…GP_DATMSK_DATMSK1_Msk (0x1ul << GP_DATMSK_DATMSK1_Pos)
‡GP_DATMSK_DATMSK2_Pos (2)
ˆGP_DATMSK_DATMSK2_Msk (0x1ul << GP_DATMSK_DATMSK2_Pos)
ŠGP_DATMSK_DATMSK3_Pos (3)
‹GP_DATMSK_DATMSK3_Msk (0x1ul << GP_DATMSK_DATMSK3_Pos)
GP_DATMSK_DATMSK4_Pos (4)
ŽGP_DATMSK_DATMSK4_Msk (0x1ul << GP_DATMSK_DATMSK4_Pos)
GP_DATMSK_DATMSK5_Pos (5)
‘GP_DATMSK_DATMSK5_Msk (0x1ul << GP_DATMSK_DATMSK5_Pos)
“GP_DATMSK_DATMSK6_Pos (6)
”GP_DATMSK_DATMSK6_Msk (0x1ul << GP_DATMSK_DATMSK6_Pos)
–GP_DATMSK_DATMSK7_Pos (7)
—GP_DATMSK_DATMSK7_Msk (0x1ul << GP_DATMSK_DATMSK7_Pos)
™GP_PIN_PIN0_Pos (0)
šGP_PIN_PIN0_Msk (0x1ul << GP_PIN_PIN0_Pos)
œGP_PIN_PIN1_Pos (1)
GP_PIN_PIN1_Msk (0x1ul << GP_PIN_PIN1_Pos)
ŸGP_PIN_PIN2_Pos (2)
 GP_PIN_PIN2_Msk (0x1ul << GP_PIN_PIN2_Pos)
¢GP_PIN_PIN3_Pos (3)
£GP_PIN_PIN3_Msk (0x1ul << GP_PIN_PIN3_Pos)
¥GP_PIN_PIN4_Pos (4)
¦GP_PIN_PIN4_Msk (0x1ul << GP_PIN_PIN4_Pos)
¨GP_PIN_PIN5_Pos (5)
©GP_PIN_PIN5_Msk (0x1ul << GP_PIN_PIN5_Pos)
«GP_PIN_PIN6_Pos (6)
¬GP_PIN_PIN6_Msk (0x1ul << GP_PIN_PIN6_Pos)
®GP_PIN_PIN7_Pos (7)
¯GP_PIN_PIN7_Msk (0x1ul << GP_PIN_PIN7_Pos)
±GP_DBEN_DBEN0_Pos (0)
²GP_DBEN_DBEN0_Msk (0x1ul << GP_DBEN_DBEN0_Pos)
´GP_DBEN_DBEN1_Pos (1)
µGP_DBEN_DBEN1_Msk (0x1ul << GP_DBEN_DBEN1_Pos)
·GP_DBEN_DBEN2_Pos (2)
¸GP_DBEN_DBEN2_Msk (0x1ul << GP_DBEN_DBEN2_Pos)
ºGP_DBEN_DBEN3_Pos (3)
»GP_DBEN_DBEN3_Msk (0x1ul << GP_DBEN_DBEN3_Pos)
½GP_DBEN_DBEN4_Pos (4)
¾GP_DBEN_DBEN4_Msk (0x1ul << GP_DBEN_DBEN4_Pos)
ÀGP_DBEN_DBEN5_Pos (5)
ÁGP_DBEN_DBEN5_Msk (0x1ul << GP_DBEN_DBEN5_Pos)
ÃGP_DBEN_DBEN6_Pos (6)
ÄGP_DBEN_DBEN6_Msk (0x1ul << GP_DBEN_DBEN6_Pos)
ÆGP_DBEN_DBEN7_Pos (7)
ÇGP_DBEN_DBEN7_Msk (0x1ul << GP_DBEN_DBEN7_Pos)
ÉGP_INTTYPE_TYPE0_Pos (0)
ÊGP_INTTYPE_TYPE0_Msk (0x1ul << GP_INTTYPE_TYPE0_Pos)
ÌGP_INTTYPE_TYPE1_Pos (1)
ÍGP_INTTYPE_TYPE1_Msk (0x1ul << GP_INTTYPE_TYPE1_Pos)
ÏGP_INTTYPE_TYPE2_Pos (2)
ÐGP_INTTYPE_TYPE2_Msk (0x1ul << GP_INTTYPE_TYPE2_Pos)
ÒGP_INTTYPE_TYPE3_Pos (3)
ÓGP_INTTYPE_TYPE3_Msk (0x1ul << GP_INTTYPE_TYPE3_Pos)
ÕGP_INTTYPE_TYPE4_Pos (4)
ÖGP_INTTYPE_TYPE4_Msk (0x1ul << GP_INTTYPE_TYPE4_Pos)
ØGP_INTTYPE_TYPE5_Pos (5)
ÙGP_INTTYPE_TYPE5_Msk (0x1ul << GP_INTTYPE_TYPE5_Pos)
ÛGP_INTTYPE_TYPE6_Pos (6)
ÜGP_INTTYPE_TYPE6_Msk (0x1ul << GP_INTTYPE_TYPE6_Pos)
ÞGP_INTTYPE_TYPE7_Pos (7)
ßGP_INTTYPE_TYPE7_Msk (0x1ul << GP_INTTYPE_TYPE7_Pos)
áGP_INTEN_FLIEN0_Pos (0)
âGP_INTEN_FLIEN0_Msk (0x1ul << GP_INTEN_FLIEN0_Pos)
äGP_INTEN_FLIEN1_Pos (1)
åGP_INTEN_FLIEN1_Msk (0x1ul << GP_INTEN_FLIEN1_Pos)
çGP_INTEN_FLIEN2_Pos (2)
èGP_INTEN_FLIEN2_Msk (0x1ul << GP_INTEN_FLIEN2_Pos)
êGP_INTEN_FLIEN3_Pos (3)
ëGP_INTEN_FLIEN3_Msk (0x1ul << GP_INTEN_FLIEN3_Pos)
íGP_INTEN_FLIEN4_Pos (4)
îGP_INTEN_FLIEN4_Msk (0x1ul << GP_INTEN_FLIEN4_Pos)
ðGP_INTEN_FLIEN5_Pos (5)
ñGP_INTEN_FLIEN5_Msk (0x1ul << GP_INTEN_FLIEN5_Pos)
óGP_INTEN_FLIEN6_Pos (6)
ôGP_INTEN_FLIEN6_Msk (0x1ul << GP_INTEN_FLIEN6_Pos)
öGP_INTEN_FLIEN7_Pos (7)
÷GP_INTEN_FLIEN7_Msk (0x1ul << GP_INTEN_FLIEN7_Pos)
ùGP_INTEN_RHIEN0_Pos (16)
úGP_INTEN_RHIEN0_Msk (0x1ul << GP_INTEN_RHIEN0_Pos)
üGP_INTEN_RHIEN1_Pos (17)
ýGP_INTEN_RHIEN1_Msk (0x1ul << GP_INTEN_RHIEN1_Pos)
ÿGP_INTEN_RHIEN2_Pos (18)
€GP_INTEN_RHIEN2_Msk (0x1ul << GP_INTEN_RHIEN2_Pos)
‚GP_INTEN_RHIEN3_Pos (19)
ƒGP_INTEN_RHIEN3_Msk (0x1ul << GP_INTEN_RHIEN3_Pos)
…GP_INTEN_RHIEN4_Pos (20)
†GP_INTEN_RHIEN4_Msk (0x1ul << GP_INTEN_RHIEN4_Pos)
ˆGP_INTEN_RHIEN5_Pos (21)
‰GP_INTEN_RHIEN5_Msk (0x1ul << GP_INTEN_RHIEN5_Pos)
‹GP_INTEN_RHIEN6_Pos (22)
ŒGP_INTEN_RHIEN6_Msk (0x1ul << GP_INTEN_RHIEN6_Pos)
ŽGP_INTEN_RHIEN7_Pos (23)
GP_INTEN_RHIEN7_Msk (0x1ul << GP_INTEN_RHIEN7_Pos)
‘GP_INTSRC_INTSRC0_Pos (0)
’GP_INTSRC_INTSRC0_Msk (0x1ul << GP_INTSRC_INTSRC0_Pos)
”GP_INTSRC_INTSRC1_Pos (1)
•GP_INTSRC_INTSRC1_Msk (0x1ul << GP_INTSRC_INTSRC1_Pos)
—GP_INTSRC_INTSRC2_Pos (2)
˜GP_INTSRC_INTSRC2_Msk (0x1ul << GP_INTSRC_INTSRC2_Pos)
šGP_INTSRC_INTSRC3_Pos (3)
›GP_INTSRC_INTSRC3_Msk (0x1ul << GP_INTSRC_INTSRC3_Pos)
GP_INTSRC_INTSRC4_Pos (4)
žGP_INTSRC_INTSRC4_Msk (0x1ul << GP_INTSRC_INTSRC4_Pos)
 GP_INTSRC_INTSRC5_Pos (5)
¡GP_INTSRC_INTSRC5_Msk (0x1ul << GP_INTSRC_INTSRC5_Pos)
£GP_INTSRC_INTSRC6_Pos (6)
¤GP_INTSRC_INTSRC6_Msk (0x1ul << GP_INTSRC_INTSRC6_Pos)
¦GP_INTSRC_INTSRC7_Pos (7)
§GP_INTSRC_INTSRC7_Msk (0x1ul << GP_INTSRC_INTSRC7_Pos)
©GP_INTSRC_INTSRC8_Pos (8)
ªGP_INTSRC_INTSRC8_Msk (0x1ul << GP_INTSRC_INTSRC8_Pos)
¬GP_INTSRC_INTSRC9_Pos (9)
­GP_INTSRC_INTSRC9_Msk (0x1ul << GP_INTSRC_INTSRC9_Pos)
¯GP_INTSRC_INTSRC10_Pos (10)
°GP_INTSRC_INTSRC10_Msk (0x1ul << GP_INTSRC_INTSRC10_Pos)
²GP_INTSRC_INTSRC11_Pos (11)
³GP_INTSRC_INTSRC11_Msk (0x1ul << GP_INTSRC_INTSRC11_Pos)
µGP_INTSRC_INTSRC12_Pos (12)
¶GP_INTSRC_INTSRC12_Msk (0x1ul << GP_INTSRC_INTSRC12_Pos)
¸GP_INTSRC_INTSRC13_Pos (13)
¹GP_INTSRC_INTSRC13_Msk (0x1ul << GP_INTSRC_INTSRC13_Pos)
»GP_INTSRC_INTSRC14_Pos (14)
¼GP_INTSRC_INTSRC14_Msk (0x1ul << GP_INTSRC_INTSRC14_Pos)
¾GP_INTSRC_INTSRC15_Pos (15)
¿GP_INTSRC_INTSRC15_Msk (0x1ul << GP_INTSRC_INTSRC15_Pos)
ÁGP_MODE_MODE0_Pos (0)
ÂGP_MODE_MODE0_Msk (0x3ul << GP_MODE_MODE0_Pos)
ÄGP_MODE_MODE1_Pos (2)
ÅGP_MODE_MODE1_Msk (0x3ul << GP_MODE_MODE1_Pos)
ÇGP_MODE_MODE2_Pos (4)
ÈGP_MODE_MODE2_Msk (0x3ul << GP_MODE_MODE2_Pos)
ÊGP_MODE_MODE3_Pos (6)
ËGP_MODE_MODE3_Msk (0x3ul << GP_MODE_MODE3_Pos)
ÍGP_MODE_MODE4_Pos (8)
ÎGP_MODE_MODE4_Msk (0x3ul << GP_MODE_MODE4_Pos)
ÐGP_MODE_MODE5_Pos (10)
ÑGP_MODE_MODE5_Msk (0x3ul << GP_MODE_MODE5_Pos)
ÓGP_DINOFF_DINOFF0_Pos (16)
ÔGP_DINOFF_DINOFF0_Msk (0x1ul << GP_DINOFF_DINOFF0_Pos)
ÖGP_DINOFF_DINOFF1_Pos (17)
×GP_DINOFF_DINOFF1_Msk (0x1ul << GP_DINOFF_DINOFF1_Pos)
ÙGP_DINOFF_DINOFF2_Pos (18)
ÚGP_DINOFF_DINOFF2_Msk (0x1ul << GP_DINOFF_DINOFF2_Pos)
ÜGP_DINOFF_DINOFF3_Pos (19)
ÝGP_DINOFF_DINOFF3_Msk (0x1ul << GP_DINOFF_DINOFF3_Pos)
ßGP_DINOFF_DINOFF4_Pos (20)
àGP_DINOFF_DINOFF4_Msk (0x1ul << GP_DINOFF_DINOFF4_Pos)
âGP_DINOFF_DINOFF5_Pos (21)
ãGP_DINOFF_DINOFF5_Msk (0x1ul << GP_DINOFF_DINOFF5_Pos)
åGP_DINOFF_DINOFF6_Pos (22)
æGP_DINOFF_DINOFF6_Msk (0x1ul << GP_DINOFF_DINOFF6_Pos)
èGP_DINOFF_DINOFF7_Pos (23)
éGP_DINOFF_DINOFF7_Msk (0x1ul << GP_DINOFF_DINOFF7_Pos)
ëGP_DOUT_DOUT0_Pos (0)
ìGP_DOUT_DOUT0_Msk (0x1ul << GP_DOUT_DOUT0_Pos)
îGP_DOUT_DOUT1_Pos (1)
ïGP_DOUT_DOUT1_Msk (0x1ul << GP_DOUT_DOUT1_Pos)
ñGP_DOUT_DOUT2_Pos (2)
òGP_DOUT_DOUT2_Msk (0x1ul << GP_DOUT_DOUT2_Pos)
ôGP_DOUT_DOUT3_Pos (3)
õGP_DOUT_DOUT3_Msk (0x1ul << GP_DOUT_DOUT3_Pos)
÷GP_DOUT_DOUT4_Pos (4)
øGP_DOUT_DOUT4_Msk (0x1ul << GP_DOUT_DOUT4_Pos)
úGP_DOUT_DOUT5_Pos (5)
ûGP_DOUT_DOUT5_Msk (0x1ul << GP_DOUT_DOUT5_Pos)
ýGP_DOUT_DOUT6_Pos (6)
þGP_DOUT_DOUT6_Msk (0x1ul << GP_DOUT_DOUT6_Pos)
€GP_DOUT_DOUT7_Pos (7)
GP_DOUT_DOUT7_Msk (0x1ul << GP_DOUT_DOUT7_Pos)
ƒGP_DATMSK_DATMSK0_Pos (0)
„GP_DATMSK_DATMSK0_Msk (0x1ul << GP_DATMSK_DATMSK0_Pos)
†GP_DATMSK_DATMSK1_Pos (1)
‡GP_DATMSK_DATMSK1_Msk (0x1ul << GP_DATMSK_DATMSK1_Pos)
‰GP_DATMSK_DATMSK2_Pos (2)
ŠGP_DATMSK_DATMSK2_Msk (0x1ul << GP_DATMSK_DATMSK2_Pos)
ŒGP_DATMSK_DATMSK3_Pos (3)
GP_DATMSK_DATMSK3_Msk (0x1ul << GP_DATMSK_DATMSK3_Pos)
GP_DATMSK_DATMSK4_Pos (4)
GP_DATMSK_DATMSK4_Msk (0x1ul << GP_DATMSK_DATMSK4_Pos)
’GP_DATMSK_DATMSK5_Pos (5)
“GP_DATMSK_DATMSK5_Msk (0x1ul << GP_DATMSK_DATMSK5_Pos)
•GP_DATMSK_DATMSK6_Pos (6)
–GP_DATMSK_DATMSK6_Msk (0x1ul << GP_DATMSK_DATMSK6_Pos)
˜GP_DATMSK_DATMSK7_Pos (7)
™GP_DATMSK_DATMSK7_Msk (0x1ul << GP_DATMSK_DATMSK7_Pos)
›GP_PIN_PIN0_Pos (0)
œGP_PIN_PIN0_Msk (0x1ul << GP_PIN_PIN0_Pos)
žGP_PIN_PIN1_Pos (1)
ŸGP_PIN_PIN1_Msk (0x1ul << GP_PIN_PIN1_Pos)
¡GP_PIN_PIN2_Pos (2)
¢GP_PIN_PIN2_Msk (0x1ul << GP_PIN_PIN2_Pos)
¤GP_PIN_PIN3_Pos (3)
¥GP_PIN_PIN3_Msk (0x1ul << GP_PIN_PIN3_Pos)
§GP_PIN_PIN4_Pos (4)
¨GP_PIN_PIN4_Msk (0x1ul << GP_PIN_PIN4_Pos)
ªGP_PIN_PIN5_Pos (5)
«GP_PIN_PIN5_Msk (0x1ul << GP_PIN_PIN5_Pos)
­GP_PIN_PIN6_Pos (6)
®GP_PIN_PIN6_Msk (0x1ul << GP_PIN_PIN6_Pos)
°GP_PIN_PIN7_Pos (7)
±GP_PIN_PIN7_Msk (0x1ul << GP_PIN_PIN7_Pos)
³GP_DBEN_DBEN0_Pos (0)
´GP_DBEN_DBEN0_Msk (0x1ul << GP_DBEN_DBEN0_Pos)
¶GP_DBEN_DBEN1_Pos (1)
·GP_DBEN_DBEN1_Msk (0x1ul << GP_DBEN_DBEN1_Pos)
¹GP_DBEN_DBEN2_Pos (2)
ºGP_DBEN_DBEN2_Msk (0x1ul << GP_DBEN_DBEN2_Pos)
¼GP_DBEN_DBEN3_Pos (3)
½GP_DBEN_DBEN3_Msk (0x1ul << GP_DBEN_DBEN3_Pos)
¿GP_DBEN_DBEN4_Pos (4)
ÀGP_DBEN_DBEN4_Msk (0x1ul << GP_DBEN_DBEN4_Pos)
ÂGP_DBEN_DBEN5_Pos (5)
ÃGP_DBEN_DBEN5_Msk (0x1ul << GP_DBEN_DBEN5_Pos)
ÅGP_DBEN_DBEN6_Pos (6)
ÆGP_DBEN_DBEN6_Msk (0x1ul << GP_DBEN_DBEN6_Pos)
ÈGP_DBEN_DBEN7_Pos (7)
ÉGP_DBEN_DBEN7_Msk (0x1ul << GP_DBEN_DBEN7_Pos)
ËGP_INTTYPE_TYPE0_Pos (0)
ÌGP_INTTYPE_TYPE0_Msk (0x1ul << GP_INTTYPE_TYPE0_Pos)
ÎGP_INTTYPE_TYPE1_Pos (1)
ÏGP_INTTYPE_TYPE1_Msk (0x1ul << GP_INTTYPE_TYPE1_Pos)
ÑGP_INTTYPE_TYPE2_Pos (2)
ÒGP_INTTYPE_TYPE2_Msk (0x1ul << GP_INTTYPE_TYPE2_Pos)
ÔGP_INTTYPE_TYPE3_Pos (3)
ÕGP_INTTYPE_TYPE3_Msk (0x1ul << GP_INTTYPE_TYPE3_Pos)
×GP_INTTYPE_TYPE4_Pos (4)
ØGP_INTTYPE_TYPE4_Msk (0x1ul << GP_INTTYPE_TYPE4_Pos)
ÚGP_INTTYPE_TYPE5_Pos (5)
ÛGP_INTTYPE_TYPE5_Msk (0x1ul << GP_INTTYPE_TYPE5_Pos)
ÝGP_INTTYPE_TYPE6_Pos (6)
ÞGP_INTTYPE_TYPE6_Msk (0x1ul << GP_INTTYPE_TYPE6_Pos)
àGP_INTTYPE_TYPE7_Pos (7)
áGP_INTTYPE_TYPE7_Msk (0x1ul << GP_INTTYPE_TYPE7_Pos)
ãGP_INTEN_FLIEN0_Pos (0)
äGP_INTEN_FLIEN0_Msk (0x1ul << GP_INTEN_FLIEN0_Pos)
æGP_INTEN_FLIEN1_Pos (1)
çGP_INTEN_FLIEN1_Msk (0x1ul << GP_INTEN_FLIEN1_Pos)
éGP_INTEN_FLIEN2_Pos (2)
êGP_INTEN_FLIEN2_Msk (0x1ul << GP_INTEN_FLIEN2_Pos)
ìGP_INTEN_FLIEN3_Pos (3)
íGP_INTEN_FLIEN3_Msk (0x1ul << GP_INTEN_FLIEN3_Pos)
ïGP_INTEN_FLIEN4_Pos (4)
ðGP_INTEN_FLIEN4_Msk (0x1ul << GP_INTEN_FLIEN4_Pos)
òGP_INTEN_FLIEN5_Pos (5)
óGP_INTEN_FLIEN5_Msk (0x1ul << GP_INTEN_FLIEN5_Pos)
õGP_INTEN_FLIEN6_Pos (6)
öGP_INTEN_FLIEN6_Msk (0x1ul << GP_INTEN_FLIEN6_Pos)
øGP_INTEN_FLIEN7_Pos (7)
ùGP_INTEN_FLIEN7_Msk (0x1ul << GP_INTEN_FLIEN7_Pos)
ûGP_INTEN_RHIEN0_Pos (16)
üGP_INTEN_RHIEN0_Msk (0x1ul << GP_INTEN_RHIEN0_Pos)
þGP_INTEN_RHIEN1_Pos (17)
ÿGP_INTEN_RHIEN1_Msk (0x1ul << GP_INTEN_RHIEN1_Pos)
GP_INTEN_RHIEN2_Pos (18)
‚GP_INTEN_RHIEN2_Msk (0x1ul << GP_INTEN_RHIEN2_Pos)
„GP_INTEN_RHIEN3_Pos (19)
…GP_INTEN_RHIEN3_Msk (0x1ul << GP_INTEN_RHIEN3_Pos)
‡GP_INTEN_RHIEN4_Pos (20)
ˆGP_INTEN_RHIEN4_Msk (0x1ul << GP_INTEN_RHIEN4_Pos)
ŠGP_INTEN_RHIEN5_Pos (21)
‹GP_INTEN_RHIEN5_Msk (0x1ul << GP_INTEN_RHIEN5_Pos)
GP_INTEN_RHIEN6_Pos (22)
ŽGP_INTEN_RHIEN6_Msk (0x1ul << GP_INTEN_RHIEN6_Pos)
GP_INTEN_RHIEN7_Pos (23)
‘GP_INTEN_RHIEN7_Msk (0x1ul << GP_INTEN_RHIEN7_Pos)
“GP_INTSRC_INTSRC0_Pos (0)
”GP_INTSRC_INTSRC0_Msk (0x1ul << GP_INTSRC_INTSRC0_Pos)
–GP_INTSRC_INTSRC1_Pos (1)
—GP_INTSRC_INTSRC1_Msk (0x1ul << GP_INTSRC_INTSRC1_Pos)
™GP_INTSRC_INTSRC2_Pos (2)
šGP_INTSRC_INTSRC2_Msk (0x1ul << GP_INTSRC_INTSRC2_Pos)
œGP_INTSRC_INTSRC3_Pos (3)
GP_INTSRC_INTSRC3_Msk (0x1ul << GP_INTSRC_INTSRC3_Pos)
ŸGP_INTSRC_INTSRC4_Pos (4)
 GP_INTSRC_INTSRC4_Msk (0x1ul << GP_INTSRC_INTSRC4_Pos)
¢GP_INTSRC_INTSRC5_Pos (5)
£GP_INTSRC_INTSRC5_Msk (0x1ul << GP_INTSRC_INTSRC5_Pos)
¥GP_INTSRC_INTSRC6_Pos (6)
¦GP_INTSRC_INTSRC6_Msk (0x1ul << GP_INTSRC_INTSRC6_Pos)
¨GP_INTSRC_INTSRC7_Pos (7)
©GP_INTSRC_INTSRC7_Msk (0x1ul << GP_INTSRC_INTSRC7_Pos)
«GP_INTSRC_INTSRC8_Pos (8)
¬GP_INTSRC_INTSRC8_Msk (0x1ul << GP_INTSRC_INTSRC8_Pos)
®GP_INTSRC_INTSRC9_Pos (9)
¯GP_INTSRC_INTSRC9_Msk (0x1ul << GP_INTSRC_INTSRC9_Pos)
±GP_INTSRC_INTSRC10_Pos (10)
²GP_INTSRC_INTSRC10_Msk (0x1ul << GP_INTSRC_INTSRC10_Pos)
´GP_INTSRC_INTSRC11_Pos (11)
µGP_INTSRC_INTSRC11_Msk (0x1ul << GP_INTSRC_INTSRC11_Pos)
·GP_INTSRC_INTSRC12_Pos (12)
¸GP_INTSRC_INTSRC12_Msk (0x1ul << GP_INTSRC_INTSRC12_Pos)
ºGP_INTSRC_INTSRC13_Pos (13)
»GP_INTSRC_INTSRC13_Msk (0x1ul << GP_INTSRC_INTSRC13_Pos)
½GP_INTSRC_INTSRC14_Pos (14)
¾GP_INTSRC_INTSRC14_Msk (0x1ul << GP_INTSRC_INTSRC14_Pos)
ÀGP_INTSRC_INTSRC15_Pos (15)
ÁGP_INTSRC_INTSRC15_Msk (0x1ul << GP_INTSRC_INTSRC15_Pos)
ÃGP_DBCTL_DBCLKSEL_Pos (0)
ÄGP_DBCTL_DBCLKSEL_Msk (0xful << GP_DBCTL_DBCLKSEL_Pos)
ÆGP_DBCTL_DBCLKSRC_Pos (4)
ÇGP_DBCTL_DBCLKSRC_Msk (0x1ul << GP_DBCTL_DBCLKSRC_Pos)
ÉGP_DBCTL_ICLKON_Pos (5)
ÊGP_DBCTL_ICLKON_Msk (0x1ul << GP_DBCTL_ICLKON_Pos)
ÇADC_DAT_RESULT_Pos (0)
ÈADC_DAT_RESULT_Msk (0xfffful << ADC_DAT_RESULT_Pos)
ÉADC_DAT_OV_Pos (16)
ÊADC_DAT_OV_Msk (0x1ul << ADC_DAT_OV_Pos)
ËADC_DAT_VALID_Pos (17)
ÌADC_DAT_VALID_Msk (0x1ul << ADC_DAT_VALID_Pos)
ÎADC_CTL_ADCEN_Pos (0)
ÏADC_CTL_ADCEN_Msk (0x1ul << ADC_CTL_ADCEN_Pos)
ÐADC_CTL_ADCIEN_Pos (1)
ÑADC_CTL_ADCIEN_Msk (0x1ul << ADC_CTL_ADCIEN_Pos)
ÒADC_CTL_HWTRGSEL_Pos (4)
ÓADC_CTL_HWTRGSEL_Msk (0x3ul << ADC_CTL_HWTRGSEL_Pos)
ÔADC_CTL_HWTRGCOND_Pos (6)
ÕADC_CTL_HWTRGCOND_Msk (0x1ul << ADC_CTL_HWTRGCOND_Pos)
ÖADC_CTL_HWTRGEN_Pos (8)
×ADC_CTL_HWTRGEN_Msk (0x1ul << ADC_CTL_HWTRGEN_Pos)
ØADC_CTL_FIFO_EN_Pos (9)
ÙADC_CTL_FIFO_EN_Msk (0x1ul << ADC_CTL_FIFO_EN_Pos)
ÚADC_CTL_FIFO_THRE_STATE_Pos (10)
ÛADC_CTL_FIFO_THRE_STATE_Msk (0x1ul << ADC_CTL_FIFO_THRE_STATE_Pos)
ÜADC_CTL_SWTRG_Pos (11)
ÝADC_CTL_SWTRG_Msk (0x1ul << ADC_CTL_SWTRG_Pos)
ÞADC_CTL_SWTRG_Pos (11)
ßADC_CTL_SWTRG_Msk (0x1ul << ADC_CTL_SWTRG_Pos)
àADC_CTL_SWTRG_Pos (11)
áADC_CTL_SWTRG_Msk (0x1ul << ADC_CTL_SWTRG_Pos)
âADC_CTL_LEFT_SHIFT_EN_Pos (12)
ãADC_CTL_LEFT_SHIFT_EN_Msk (0x1ul << ADC_CTL_LEFT_SHIFT_EN_Pos)
äADC_CTL_SUB_BIAS_EN_Pos (13)
åADC_CTL_SUB_BIAS_EN_Msk (0x1ul << ADC_CTL_SUB_BIAS_EN_Pos)
æADC_CTL_BIAS_VALUE_Pos (16)
çADC_CTL_BIAS_VALUE_Msk (0xffful << ADC_CTL_BIAS_VALUE_Pos)
êADC_CHEN_CHEN0_Pos (0)
ëADC_CHEN_CHEN0_Msk (0x1ul << ADC_CHEN_CHEN0_Pos)
ìADC_CHEN_CHEN1_Pos (1)
íADC_CHEN_CHEN1_Msk (0x1ul << ADC_CHEN_CHEN1_Pos)
îADC_CHEN_CHEN2_Pos (2)
ïADC_CHEN_CHEN2_Msk (0x1ul << ADC_CHEN_CHEN2_Pos)
ðADC_CHEN_CHEN3_Pos (3)
ñADC_CHEN_CHEN3_Msk (0x1ul << ADC_CHEN_CHEN3_Pos)
òADC_CHEN_CHEN4_Pos (4)
óADC_CHEN_CHEN4_Msk (0x1ul << ADC_CHEN_CHEN4_Pos)
ôADC_CHEN_CHEN5_Pos (5)
õADC_CHEN_CHEN5_Msk (0x1ul << ADC_CHEN_CHEN5_Pos)
öADC_CHEN_CHEN6_Pos (6)
÷ADC_CHEN_CHEN6_Msk (0x1ul << ADC_CHEN_CHEN6_Pos)
øADC_CHEN_CHEN7_Pos (7)
ùADC_CHEN_CHEN7_Msk (0x1ul << ADC_CHEN_CHEN7_Pos)
úADC_CHEN_CHEN8_VBG_Pos (8)
ûADC_CHEN_CHEN8_VBG_Msk (0x1ul << ADC_CHEN_CHEN8_VBG_Pos)
üADC_CHEN_CH9_TMP_Pos (9)
ýADC_CHEN_CH9_TMP_Msk (0x1ul << ADC_CHEN_CH9_TMP_Pos)
þADC_CHEN_CH10_VDD_4_Pos (10)
ÿADC_CHEN_CH10_VDD_4_Msk (0x1ul << ADC_CHEN_CH10_VDD_4_Pos)
€ADC_CHEN_CH11_VBG_2_Pos (11)
ADC_CHEN_CH11_VBG_2_Msk (0x1ul << ADC_CHEN_CH11_VBG_2_Pos)
‚ADC_CHEN_ALL_Msk (0xFFFul)
„ADC_CMP0_ADCMPEN_Pos (0)
…ADC_CMP0_ADCMPEN_Msk (0x1ul << ADC_CMP0_ADCMPEN_Pos)
†ADC_CMP0_ADCMPIE_Pos (1)
‡ADC_CMP0_ADCMPIE_Msk (0x1ul << ADC_CMP0_ADCMPIE_Pos)
ˆADC_CMP0_CMPCOND_Pos (2)
‰ADC_CMP0_CMPCOND_Msk (0x1ul << ADC_CMP0_CMPCOND_Pos)
ŠADC_CMP0_CMPCH_Pos (3)
‹ADC_CMP0_CMPCH_Msk (0x7ul << ADC_CMP0_CMPCH_Pos)
ŒADC_CMP0_CMPMCNT_Pos (8)
ADC_CMP0_CMPMCNT_Msk (0xful << ADC_CMP0_CMPMCNT_Pos)
ŽADC_CMP0_CMPDAT_Pos (16)
ADC_CMP0_CMPDAT_Msk (0xffful << ADC_CMP0_CMPDAT_Pos)
‘ADC_CMP1_ADCMPEN_Pos (0)
’ADC_CMP1_ADCMPEN_Msk (0x1ul << ADC_CMP1_ADCMPEN_Pos)
“ADC_CMP1_ADCMPIE_Pos (1)
”ADC_CMP1_ADCMPIE_Msk (0x1ul << ADC_CMP1_ADCMPIE_Pos)
•ADC_CMP1_CMPCOND_Pos (2)
–ADC_CMP1_CMPCOND_Msk (0x1ul << ADC_CMP1_CMPCOND_Pos)
—ADC_CMP1_CMPCH_Pos (3)
˜ADC_CMP1_CMPCH_Msk (0x7ul << ADC_CMP1_CMPCH_Pos)
™ADC_CMP1_CMPMCNT_Pos (8)
šADC_CMP1_CMPMCNT_Msk (0xful << ADC_CMP1_CMPMCNT_Pos)
›ADC_CMP1_CMPDAT_Pos (16)
œADC_CMP1_CMPDAT_Msk (0xffful << ADC_CMP1_CMPDAT_Pos)
žADC_STATUS_ADIF_Pos (0)
ŸADC_STATUS_ADIF_Msk (0x1ul << ADC_STATUS_ADIF_Pos)
 ADC_STATUS_ADCMPIF0_Pos (1)
¡ADC_STATUS_ADCMPIF0_Msk (0x1ul << ADC_STATUS_ADCMPIF0_Pos)
¢ADC_STATUS_ADCMPIF1_Pos (2)
£ADC_STATUS_ADCMPIF1_Msk (0x1ul << ADC_STATUS_ADCMPIF1_Pos)
¤ADC_STATUS_BUSY_Pos (3)
¥ADC_STATUS_BUSY_Msk (0x1ul << ADC_STATUS_BUSY_Pos)
¦ADC_STATUS_CHANNEL_Pos (4)
§ADC_STATUS_CHANNEL_Msk (0x7ul << ADC_STATUS_CHANNEL_Pos)
¨ADC_STATUS_VALID_Pos (8)
©ADC_STATUS_VALID_Msk (0x1ul << ADC_STATUS_VALID_Pos)
ªADC_STATUS_INTMSK_FULL_Pos (9)
«ADC_STATUS_INTMSK_FULL_Msk (0x1ul << ADC_STATUS_INTMSK_FULL_Pos)
¬ADC_STATUS_INTMSK_EMPTY_Pos (10)
­ADC_STATUS_INTMSK_EMPTY_Msk (0x1ul << ADC_STATUS_INTMSK_EMPTY_Pos)
®ADC_STATUS_INTMSK_OVER_Pos (11)
¯ADC_STATUS_INTMSK_OVER_Msk (0x1ul << ADC_STATUS_INTMSK_OVER_Pos)
°ADC_STATUS_INTMSK_HALF_Pos (12)
±ADC_STATUS_INTMSK_HALF_Msk (0x1ul << ADC_STATUS_INTMSK_HALF_Pos)
²ADC_STATUS_INTMSK_AD_Pos (13)
³ADC_STATUS_INTMSK_AD_Msk (0x1ul << ADC_STATUS_INTMSK_AD_Pos)
´ADC_STATUS_INTMSK_CMP0_Pos (14)
µADC_STATUS_INTMSK_CMP0_Msk (0x1ul << ADC_STATUS_INTMSK_CMP0_Pos)
¶ADC_STATUS_INTMSK_CMP1_Pos (15)
·ADC_STATUS_INTMSK_CMP1_Msk (0x1ul << ADC_STATUS_INTMSK_CMP1_Pos)
¸ADC_STATUS_OV_Pos (16)
¹ADC_STATUS_OV_Msk (0x1ul << ADC_STATUS_OV_Pos)
ºADC_STATUS_ONE_CH_CLR_SEL_Pos (17)
»ADC_STATUS_ONE_CH_CLR_SEL_Msk (0x1ul << ADC_STATUS_ONE_CH_CLR_SEL_Pos)
¼ADC_STATUS_ONE_CH_FLAG_Pos (18)
½ADC_STATUS_ONE_CH_FLAG_Msk (0x1ul << ADC_STATUS_ONE_CH_FLAG_Pos)
¾ADC_STATUS_INTFLG_FULL_Pos (19)
¿ADC_STATUS_INTFLG_FULL_Msk (0x1ul << ADC_STATUS_INTFLG_FULL_Pos)
ÀADC_STATUS_INTFLG_EMPTY_Pos (20)
ÁADC_STATUS_INTFLG_EMPTY_Msk (0x1ul << ADC_STATUS_INTFLG_EMPTY_Pos)
ÂADC_STATUS_INTFLG_OVER_Pos (21)
ÃADC_STATUS_INTFLG_OVER_Msk (0x1ul << ADC_STATUS_INTFLG_OVER_Pos)
ÄADC_STATUS_INTFLG_HALF_Pos (22)
ÅADC_STATUS_INTFLG_HALF_Msk (0x1ul << ADC_STATUS_INTFLG_HALF_Pos)
ÆADC_STATUS_ADCF_Pos (24)
ÇADC_STATUS_ADCF_Msk (0x1ul << ADC_STATUS_ADCF_Pos)
ÈADC_STATUS_ADCMPF0_Pos (25)
ÉADC_STATUS_ADCMPF0_Msk (0x1ul << ADC_STATUS_ADCMPF0_Pos)
ÊADC_STATUS_ADCMPF1_Pos (26)
ËADC_STATUS_ADCMPF1_Msk (0x1ul << ADC_STATUS_ADCMPF1_Pos)
ÌADC_STATUS_FLAG_FULL_Pos (27)
ÍADC_STATUS_FLAG_FULL_Msk (0x1ul << ADC_STATUS_FLAG_FULL_Pos)
ÎADC_STATUS_FLAG_EMPTY_Pos (28)
ÏADC_STATUS_FLAG_EMPTY_Msk (0x1ul << ADC_STATUS_FLAG_EMPTY_Pos)
ÐADC_STATUS_FLAG_OVER_Pos (29)
ÑADC_STATUS_FLAG_OVER_Msk (0x1ul << ADC_STATUS_FLAG_OVER_Pos)
ÒADC_STATUS_FLAG_HALF_Pos (30)
ÓADC_STATUS_FLAG_HALF_Msk (0x1ul << ADC_STATUS_FLAG_HALF_Pos)
ÕADC_TRGDLY_DELAY_Pos (0)
ÖADC_TRGDLY_DELAY_Msk (0xfful << ADC_TRGDLY_DELAY_Pos)
ØADC_EXTSMPT_EXTSMPT_Pos (0)
ÙADC_EXTSMPT_EXTSMPT_Msk (0x3fful << ADC_EXTSMPT_EXTSMPT_Pos)
ÛADC_SEQCTL_SEQEN_Pos (0)
ÜADC_SEQCTL_SEQEN_Msk (0x1ul << ADC_SEQCTL_SEQEN_Pos)
ÝADC_SEQCTL_SEQTYPE_Pos (1)
ÞADC_SEQCTL_SEQTYPE_Msk (0x1ul << ADC_SEQCTL_SEQTYPE_Pos)
ßADC_SEQCTL_MODESEL_Pos (2)
àADC_SEQCTL_MODESEL_Msk (0x3ul << ADC_SEQCTL_MODESEL_Pos)
áADC_SEQCTL_DELAY_EN_Pos (4)
âADC_SEQCTL_DELAY_EN_Msk (0x1ul << ADC_SEQCTL_DELAY_EN_Pos)
ãADC_SEQCTL_TRG_SEL_Pos (5)
äADC_SEQCTL_TRG_SEL_Msk (0x1ul << ADC_SEQCTL_TRG_SEL_Pos)
åADC_SEQCTL_ONE_CH_EN_Pos (6)
æADC_SEQCTL_ONE_CH_EN_Msk (0x1ul << ADC_SEQCTL_ONE_CH_EN_Pos)
çADC_SEQCTL_TRG1CTL_Pos (8)
èADC_SEQCTL_TRG1CTL_Msk (0xful << ADC_SEQCTL_TRG1CTL_Pos)
éADC_SEQCTL_TRG2CTL_Pos (16)
êADC_SEQCTL_TRG2CTL_Msk (0xful << ADC_SEQCTL_TRG2CTL_Pos)
ìADC_SEQDAT1_RESULT_Pos (0)
íADC_SEQDAT1_RESULT_Msk (0x3fful << ADC_SEQDAT1_RESULT_Pos)
îADC_SEQDAT1_OV_Pos (16)
ïADC_SEQDAT1_OV_Msk (0x1ul << ADC_SEQDAT1_OV_Pos)
ðADC_SEQDAT1_VALID_Pos (17)
ñADC_SEQDAT1_VALID_Msk (0x1ul << ADC_SEQDAT1_VALID_Pos)
óADC_SEQDAT2_RESULT_Pos (0)
ôADC_SEQDAT2_RESULT_Msk (0x3fful << ADC_SEQDAT2_RESULT_Pos)
õADC_SEQDAT2_OV_Pos (16)
öADC_SEQDAT2_OV_Msk (0x1ul << ADC_SEQDAT2_OV_Pos)
÷ADC_SEQDAT2_VALID_Pos (17)
øADC_SEQDAT2_VALID_Msk (0x1ul << ADC_SEQDAT2_VALID_Pos)
úADC_CTL2_TESTMODE_Pos (0)
ûADC_CTL2_TESTMODE_Msk (0x1ul << ADC_CTL2_TESTMODE_Pos)
üADC_CTL2_SHSEL_Pos (1)
ýADC_CTL2_SHSEL_Msk (0x1ul << ADC_CTL2_SHSEL_Pos)
þADC_CTL2_DMA_EN_Pos (2)
ÿADC_CTL2_DMA_EN_Msk (0x1ul << ADC_CTL2_DMA_EN_Pos)
€ADC_CTL2_CLKDIV_Pos (8)
ADC_CTL2_CLKDIV_Msk (0x7ul << ADC_CTL2_CLKDIV_Pos)
‚ADC_SEL_VREF_Pos (17)
ƒADC_SEL_VREF_Msk (0x1ul << ADC_SEL_VREF_Pos)
„ADC_CTL2_CMPCTL_Pos (24)
…ADC_CTL2_CMPCTL_Msk (0x3ul << ADC_CTL2_CMPCTL_Pos)
†ADC_CTL2_DRVCTL_Pos (26)
‡ADC_CTL2_DRVCTL_Msk (0x3ul << ADC_CTL2_DRVCTL_Pos)
«SYS_P0_MFP_MFP_Pos (0)
¬SYS_P0_MFP_MFP_Msk (0xfful << SYS_P0_MFP_MFP_Pos)
®SYS_P0_MFP_ALT0_Pos (8)
¯SYS_P0_MFP_ALT0_Msk (0x1ul << SYS_P0_MFP_ALT0_Pos)
±SYS_P0_MFP_ALT1_Pos (9)
²SYS_P0_MFP_ALT1_Msk (0x1ul << SYS_P0_MFP_ALT1_Pos)
´SYS_P0_MFP_ALT2_Pos (10)
µSYS_P0_MFP_ALT2_Msk (0x1ul << SYS_P0_MFP_ALT2_Pos)
·SYS_P0_MFP_ALT3_Pos (11)
¸SYS_P0_MFP_ALT3_Msk (0x1ul << SYS_P0_MFP_ALT3_Pos)
ºSYS_P0_MFP_ALT4_Pos (12)
»SYS_P0_MFP_ALT4_Msk (0x1ul << SYS_P0_MFP_ALT4_Pos)
½SYS_P0_MFP_ALT5_Pos (13)
¾SYS_P0_MFP_ALT5_Msk (0x1ul << SYS_P0_MFP_ALT5_Pos)
ÀSYS_P0_MFP_ALT6_Pos (14)
ÁSYS_P0_MFP_ALT6_Msk (0x1ul << SYS_P0_MFP_ALT6_Pos)
ÃSYS_P0_MFP_ALT7_Pos (15)
ÄSYS_P0_MFP_ALT7_Msk (0x1ul << SYS_P0_MFP_ALT7_Pos)
ÆSYS_P1_MFP_MFP_Pos (0)
ÇSYS_P1_MFP_MFP_Msk (0xfful << SYS_P1_MFP_MFP_Pos)
ÉSYS_P1_MFP_ALT0_Pos (8)
ÊSYS_P1_MFP_ALT0_Msk (0x1ul << SYS_P1_MFP_ALT0_Pos)
ÌSYS_P1_MFP_ALT1_Pos (9)
ÍSYS_P1_MFP_ALT1_Msk (0x1ul << SYS_P1_MFP_ALT1_Pos)
ÏSYS_P1_MFP_ALT2_Pos (10)
ÐSYS_P1_MFP_ALT2_Msk (0x1ul << SYS_P1_MFP_ALT2_Pos)
ÒSYS_P1_MFP_ALT3_Pos (11)
ÓSYS_P1_MFP_ALT3_Msk (0x1ul << SYS_P1_MFP_ALT3_Pos)
ÕSYS_P1_MFP_ALT4_Pos (12)
ÖSYS_P1_MFP_ALT4_Msk (0x1ul << SYS_P1_MFP_ALT4_Pos)
ØSYS_P1_MFP_ALT5_Pos (13)
ÙSYS_P1_MFP_ALT5_Msk (0x1ul << SYS_P1_MFP_ALT5_Pos)
ÛSYS_P1_MFP_ALT6_Pos (14)
ÜSYS_P1_MFP_ALT6_Msk (0x1ul << SYS_P1_MFP_ALT6_Pos)
ÞSYS_P1_MFP_ALT7_Pos (15)
ßSYS_P1_MFP_ALT7_Msk (0x1ul << SYS_P1_MFP_ALT7_Pos)
áSYS_P1_MFP_TYPE_Pos (16)
âSYS_P1_MFP_TYPE_Msk (0xfful << SYS_P1_MFP_TYPE_Pos)
äSYS_P1_MFP_P12EXT_Pos (26)
åSYS_P1_MFP_P12EXT_Msk (0x1ul << SYS_P1_MFP_P12EXT_Pos)
çSYS_P1_MFP_P13EXT_Pos (27)
èSYS_P1_MFP_P13EXT_Msk (0x1ul << SYS_P1_MFP_P13EXT_Pos)
êSYS_P1_MFP_P14EXT_Pos (28)
ëSYS_P1_MFP_P14EXT_Msk (0x1ul << SYS_P1_MFP_P14EXT_Pos)
îSYS_P2_MFP_ALT0_Pos (8)
ïSYS_P2_MFP_ALT0_Msk (0x1ul << SYS_P2_MFP_ALT0_Pos)
ñSYS_P2_MFP_ALT1_Pos (9)
òSYS_P2_MFP_ALT1_Msk (0x1ul << SYS_P2_MFP_ALT1_Pos)
õSYS_P2_MFP_ALT2_Pos (10)
öSYS_P2_MFP_ALT2_Msk (0x1ul << SYS_P2_MFP_ALT2_Pos)
øSYS_P2_MFP_ALT3_Pos (11)
ùSYS_P2_MFP_ALT3_Msk (0x1ul << SYS_P2_MFP_ALT3_Pos)
ûSYS_P2_MFP_ALT4_Pos (12)
üSYS_P2_MFP_ALT4_Msk (0x1ul << SYS_P2_MFP_ALT4_Pos)
þSYS_P2_MFP_ALT5_Pos (13)
ÿSYS_P2_MFP_ALT5_Msk (0x1ul << SYS_P2_MFP_ALT5_Pos)
 SYS_P2_MFP_ALT6_Pos (14)
‚ SYS_P2_MFP_ALT6_Msk (0x1ul << SYS_P2_MFP_ALT6_Pos)
… SYS_P2_MFP_ALT7_Pos (15)
† SYS_P2_MFP_ALT7_Msk (0x1ul << SYS_P2_MFP_ALT7_Pos)
‰ SYS_P3_MFP_MFP_Pos (0)
Š SYS_P3_MFP_MFP_Msk (0xfful << SYS_P3_MFP_MFP_Pos)
Œ SYS_P3_MFP_ALT0_Pos (8)
 SYS_P3_MFP_ALT0_Msk (0x1ul << SYS_P3_MFP_ALT0_Pos)
 SYS_P3_MFP_ALT1_Pos (9)
 SYS_P3_MFP_ALT1_Msk (0x1ul << SYS_P3_MFP_ALT1_Pos)
’ SYS_P3_MFP_ALT2_Pos (10)
“ SYS_P3_MFP_ALT2_Msk (0x1ul << SYS_P3_MFP_ALT2_Pos)
• SYS_P3_MFP_ALT4_Pos (12)
– SYS_P3_MFP_ALT4_Msk (0x1ul << SYS_P3_MFP_ALT4_Pos)
˜ SYS_P3_MFP_ALT5_Pos (13)
™ SYS_P3_MFP_ALT5_Msk (0x1ul << SYS_P3_MFP_ALT5_Pos)
› SYS_P3_MFP_ALT6_Pos (14)
œ SYS_P3_MFP_ALT6_Msk (0x1ul << SYS_P3_MFP_ALT6_Pos)
ž SYS_P3_MFP_P32EXT_Pos (26)
Ÿ SYS_P3_MFP_P32EXT_Msk (0x1ul << SYS_P3_MFP_P32EXT_Pos)
¡ SYS_P4_MFP_MFP_Pos (0)
¢ SYS_P4_MFP_MFP_Msk (0xfful << SYS_P4_MFP_MFP_Pos)
¤ SYS_P4_MFP_ALT6_Pos (14)
¥ SYS_P4_MFP_ALT6_Msk (0x1ul << SYS_P4_MFP_ALT6_Pos)
§ SYS_P4_MFP_ALT7_Pos (15)
¨ SYS_P4_MFP_ALT7_Msk (0x1ul << SYS_P4_MFP_ALT7_Pos)
ª SYS_P5_MFP_MFP_Pos (0)
« SYS_P5_MFP_MFP_Msk (0xfful << SYS_P5_MFP_MFP_Pos)
­ SYS_P5_MFP_ALT0_Pos (8)
® SYS_P5_MFP_ALT0_Msk (0x1ul << SYS_P5_MFP_ALT0_Pos)
° SYS_P5_MFP_ALT1_Pos (9)
± SYS_P5_MFP_ALT1_Msk (0x1ul << SYS_P5_MFP_ALT1_Pos)
³ SYS_P5_MFP_ALT2_Pos (10)
´ SYS_P5_MFP_ALT2_Msk (0x1ul << SYS_P5_MFP_ALT2_Pos)
¶ SYS_P5_MFP_ALT3_Pos (11)
· SYS_P5_MFP_ALT3_Msk (0x1ul << SYS_P5_MFP_ALT3_Pos)
¹ SYS_P5_MFP_ALT4_Pos (12)
º SYS_P5_MFP_ALT4_Msk (0x1ul << SYS_P5_MFP_ALT4_Pos)
¼ SYS_P5_MFP_ALT5_Pos (13)
½ SYS_P5_MFP_ALT5_Msk (0x1ul << SYS_P5_MFP_ALT5_Pos)
¿ SYS_P5_MFP_ALT6_Pos (14)
À SYS_P5_MFP_ALT6_Msk (0x1ul << SYS_P5_MFP_ALT5_Pos)
 SYS_P5_MFP_ALT7_Pos (15)
àSYS_P5_MFP_ALT7_Msk (0x1ul << SYS_P5_MFP_ALT5_Pos)
Å SYS_P5_MFP_P50EXT_Pos (24)
Æ SYS_P5_MFP_P50EXT_Msk (0x1ul << SYS_P5_MFP_P50EXT_Pos)
È SYS_P5_MFP_P51EXT_Pos (25)
É SYS_P5_MFP_P51EXT_Msk (0x1ul << SYS_P5_MFP_P51EXT_Pos)
Ë SYS_REGLCTL_REGLCTL_Pos (0)
Ì SYS_REGLCTL_REGLCTL_Msk (0xfful << SYS_REGLCTL_REGLCTL_Pos)
õ CLK_RSTSTS_CHIPRF_Pos (0)
ö CLK_RSTSTS_CHIPRF_Msk (0x1ul << CLK_RSTSTS_CHIPRF_Pos)
÷ CLK_RSTSTS_PINRF_Pos (1)
ø CLK_RSTSTS_PINRF_Msk (0x1ul << CLK_RSTSTS_PINRF_Pos)
ù CLK_RSTSTS_WDTRF_Pos (2)
ú CLK_RSTSTS_WDTRF_Msk (0x1ul << CLK_RSTSTS_WDTRF_Pos)
û CLK_RSTSTS_LVRRF_Pos (3)
ü CLK_RSTSTS_LVRRF_Msk (0x1ul << CLK_RSTSTS_LVRRF_Pos)
ý CLK_RSTSTS_BODRF_Pos (4)
þ CLK_RSTSTS_BODRF_Msk (0x1ul << CLK_RSTSTS_BODRF_Pos)
ÿ CLK_RSTSTS_SYSRF_Pos (5)
€!CLK_RSTSTS_SYSRF_Msk (0x1ul << CLK_RSTSTS_SYSRF_Pos)
!CLK_RSTSTS_PORRF_Pos (6)
‚!CLK_RSTSTS_PORRF_Msk (0x1ul << CLK_RSTSTS_PORRF_Pos)
ƒ!CLK_RSTSTS_CPURF_Pos (7)
„!CLK_RSTSTS_CPURF_Msk (0x1ul << CLK_RSTSTS_CPURF_Pos)
‡!CLK_IPRST0_CHIPRST_Pos (0)
ˆ!CLK_IPRST0_CHIPRST_Msk (0x1ul << CLK_IPRST0_CHIPRST_Pos)
‰!CLK_IPRST0_CPURST_Pos (1)
Š!CLK_IPRST0_CPURST_Msk (0x1ul << CLK_IPRST0_CPURST_Pos)
‹!CLK_IPRST0_DMARST_Pos (2)
Œ!CLK_IPRST0_DMARST_Msk (0x1ul << CLK_IPRST0_DMARST_Pos)
!CLK_IPRST0_RFRST_Pos (3)
Ž!CLK_IPRST0_RFRST_Msk (0x1ul << CLK_IPRST0_RFRST_Pos)
!CLK_IPRST0_EFUSERST_Pos (4)
!CLK_IPRST0_EFUSERST_Msk (0x1ul << CLK_IPRST0_EFUSERST_Pos)
‘!CLK_IPRST0_USBRST_Pos (6)
’!CLK_IPRST0_USBRST_Msk (0x1ul << CLK_IPRST0_USBRST_Pos)
“!CLK_IPRST0_MDMSTDBYRST_Pos (7)
”!CLK_IPRST0_MDMSTDBYRST_Msk (0x1ul << CLK_IPRST0_MDMSTDBYRST_Pos)
•!CLK_IPRST0_MDMRST_Pos (8)
–!CLK_IPRST0_MDMRST_Msk (0x1ul << CLK_IPRST0_MDMRST_Pos)
—!CLK_IPRST0_CHIPSCOPEEN_Pos (9)
˜!CLK_IPRST0_CHIPSCOPEEN_Msk (0x1ul << CLK_IPRST0_CHIPSCOPEEN_Pos)
™!CLK_IPRST0_FTORRST_Pos (10)
š!CLK_IPRST0_FTORRST_Msk (0x1ul << CLK_IPRST0_FTORRST_Pos)
!CLK_IPRST1_I2C0RST_Pos (0)
ž!CLK_IPRST1_I2C0RST_Msk (0x1ul << CLK_IPRST1_I2C0RST_Pos)
Ÿ!CLK_IPRST1_SPI0RST_Pos (2)
 !CLK_IPRST1_SPI0RST_Msk (0x1ul << CLK_IPRST1_SPI0RST_Pos)
¡!CLK_IPRST1_SPI1RST_Pos (3)
¢!CLK_IPRST1_SPI1RST_Msk (0x1ul << CLK_IPRST1_SPI1RST_Pos)
£!CLK_IPRST1_UART0RST_Pos (6)
¤!CLK_IPRST1_UART0RST_Msk (0x1ul << CLK_IPRST1_UART0RST_Pos)
¥!CLK_IPRST1_UART1RST_Pos (7)
¦!CLK_IPRST1_UART1RST_Msk (0x1ul << CLK_IPRST1_UART1RST_Pos)
§!CLK_IPRST1_PWM0RST_Pos (8)
¨!CLK_IPRST1_PWM0RST_Msk (0x1ul << CLK_IPRST1_PWM0RST_Pos)
©!CLK_IPRST1_ADCRST_Pos (9)
ª!CLK_IPRST1_ADCRST_Msk (0x1ul << CLK_IPRST1_ADCRST_Pos)
«!CLK_IPRST1_WDTRST_Pos (10)
¬!CLK_IPRST1_WDTRST_Msk (0x1ul << CLK_IPRST1_WDTRST_Pos)
­!CLK_IPRST1_WWDTRST_Pos (11)
®!CLK_IPRST1_WWDTRST_Msk (0x1ul << CLK_IPRST1_WWDTRST_Pos)
¯!CLK_IPRST1_TMR0RST_Pos (12)
°!CLK_IPRST1_TMR0RST_Msk (0x1ul << CLK_IPRST1_TMR0RST_Pos)
±!CLK_IPRST1_TMR1RST_Pos (13)
²!CLK_IPRST1_TMR1RST_Msk (0x1ul << CLK_IPRST1_TMR1RST_Pos)
³!CLK_IPRST1_TMR2RST_Pos (14)
´!CLK_IPRST1_TMR2RST_Msk (0x1ul << CLK_IPRST1_TMR2RST_Pos)
µ!CLK_IPRST1_GPIORST_Pos (15)
¶!CLK_IPRST1_GPIORST_Msk (0x1ul << CLK_IPRST1_GPIORST_Pos)
·!CLK_IPRST1_TRIMRST_Pos (16)
¸!CLK_IPRST1_TRIMRST_Msk (0x1ul << CLK_IPRST1_TRIMRST_Pos)
»!CLK_BODCTL_BODRSTEN_Pos_3v (3)
¼!CLK_BODCTL_BODRSTEN_Msk_3v (0x1ul << CLK_BODCTL_BODRSTEN_Pos_3v)
½!CLK_BODCTL_BODIF_Pos (4)
¾!CLK_BODCTL_BODIF_Msk (0x1ul << CLK_BODCTL_BODIF_Pos)
¿!CLK_BODCTL_BODOUT_Pos (6)
À!CLK_BODCTL_BODOUT_Msk (0x1ul << CLK_BODCTL_BODOUT_Pos)
Á!CLK_BODCTL_LVREN_Pos_3v (16)
Â!CLK_BODCTL_LVREN_Msk_3v (0x1ul << CLK_BODCTL_LVREN_Pos_3v)
Ã!CLK_BODCTL_BODEN_Pos_3v (17)
Ä!CLK_BODCTL_BODEN_Msk_3v (0x1ul << CLK_BODCTL_BODEN_Pos_3v)
Å!CLK_BODCTL_BODSEL_Pos_3v (18)
Æ!CLK_BODCTL_BODSEL_Msk_3v (0x7ul << CLK_BODCTL_BODSEL_Pos_3v)
Ç!CLK_BODCTL_LVR_TEST_Pos_3v (21)
È!CLK_BODCTL_LVR_TEST_Msk_3v (0x1ul << CLK_BODCTL_LVR_TEST_Pos_3v)
É!CLK_BODCTL_BOD_TEST_Pos_3v (22)
Ê!CLK_BODCTL_BOD_TEST_Msk_3v (0x1ul << CLK_BODCTL_BOD_TEST_Pos_3v)
Í!CLK_BLDBCTL_LVRDB_SEL_Pos_3v (8)
Î!CLK_BLDBCTL_LVRDB_SEL_Msk_3v (0x3Ful << CLK_BLDBCTL_LVRDB_SEL_Pos_3v)
Ï!CLK_BLDBCTL_BODDB_SEL_Pos_3v (0)
Ð!CLK_BLDBCTL_BODDB_SEL_Msk_3v (0x3Ful << CLK_BLDBCTL_BODDB_SEL_Pos_3v)
Ó!CLK_TOPCTL_RSICV_SYSCNT_EN_Pos (0)
Ô!CLK_TOPCTL_RSICV_SYSCNT_EN_Msk (0x1ul << CLK_TOPCTL_RSICV_SYSCNT_EN_Pos)
Õ!CLK_TOPCTL_SYS_CLK_SEL_Pos (8)
Ö!CLK_TOPCTL_SYS_CLK_SEL_Msk (0x3ul << CLK_TOPCTL_SYS_CLK_SEL_Pos)
×!CLK_TOPCTL_32K_CLK_SEL_Pos_3v (10)
Ø!CLK_TOPCTL_32K_CLK_SEL_Msk_3v (0x1ul << CLK_TOPCTL_32K_CLK_SEL_Pos_3v)
Ù!CLK_TOPCTL_AHB_DIV_Pos (12)
Ú!CLK_TOPCTL_AHB_DIV_Msk (0xFul << CLK_TOPCTL_AHB_DIV_Pos)
Û!CLK_TOPCTL_APB1_DIV_Pos (16)
Ü!CLK_TOPCTL_APB1_DIV_Msk (0xFul << CLK_TOPCTL_APB1_DIV_Pos)
Ý!CLK_TOPCTL_APB2_DIV_Pos (20)
Þ!CLK_TOPCTL_APB2_DIV_Msk (0xFul << CLK_TOPCTL_APB2_DIV_Pos)
á!CLK_RCLCTL_RC32K_EN_Pos_3v (0)
â!CLK_RCLCTL_RC32K_EN_Msk_3v (0x1ul << CLK_RCLCTL_RC32K_EN_Pos_3v)
ã!CLK_RCLCTL_RC32K_TST_EN_Pos (1)
ä!CLK_RCLCTL_RC32K_TST_EN_Msk (0x1ul << CLK_RCLCTL_RC32K_TST_EN_Pos)
å!CLK_RCLCTL_CLK_SEL_Pos_3v (2)
æ!CLK_RCLCTL_CLK_SEL_Msk_3v (0x1ul << CLK_RCLCTL_CLK_SEL_Pos_3v)
ç!CLK_RCLCTL_RC32K_COARSE_Pos_3v (4)
è!CLK_RCLCTL_RC32K_COARSE_Msk_3v (0xFul << CLK_RCLCTL_RC32K_COARSE_Pos_3v)
é!CLK_RCLCTL_RC32K_FINE_Pos_3v (8)
ê!CLK_RCLCTL_RC32K_FINE_Msk_3v (0xFFul << CLK_RCLCTL_RC32K_FINE_Pos_3v)
ë!CLK_RCLCTL_RC32K_DELAY_Pos_3v (16)
ì!CLK_RCLCTL_RC32K_DELAY_Msk_3v (0x3ul << CLK_RCLCTL_RC32K_DELAY_Pos_3v)
í!CLK_RCLCTL_STABLE_Pos (24)
î!CLK_RCLCTL_STABLE_Msk (0x1ul << CLK_RCLCTL_STABLE_Pos)
ñ!CLK_RCHCTL_RCH_EN_Pos (0)
ò!CLK_RCHCTL_RCH_EN_Msk (0x1ul << CLK_RCHCTL_RCH_EN_Pos)
ó!CLK_RCHCTL_RCH_TST_EN_Pos (1)
ô!CLK_RCHCTL_RCH_TST_EN_Msk (0x1ul << CLK_RCHCTL_RCH_TST_EN_Pos)
õ!CLK_RCHCTL_CLK_SEL_Pos (2)
ö!CLK_RCHCTL_CLK_SEL_Msk (0x1ul << CLK_RCHCTL_CLK_SEL_Pos)
÷!CLK_RCHCTL_BIAS_Pos (4)
ø!CLK_RCHCTL_BIAS_Msk (0x3ul << CLK_RCHCTL_BIAS_Pos)
ù!CLK_RCHCTL_RCH_FREQ_Pos (8)
ú!CLK_RCHCTL_RCH_FREQ_Msk (0xFFul << CLK_RCHCTL_RCH_FREQ_Pos)
û!CLK_RCHCTL_DELAY_Pos (16)
ü!CLK_RCHCTL_DELAY_Msk (0x3ul << CLK_RCHCTL_DELAY_Pos)
ý!CLK_RCHCTL_STABLE_Pos (24)
þ!CLK_RCHCTL_STABLE_Msk (0x1ul << CLK_RCHCTL_STABLE_Pos)
"CLK_XTLCTL_XTL_EN_Pos_3v (0)
‚"CLK_XTLCTL_XTL_EN_Msk_3v (0x1ul << CLK_XTLCTL_XTL_EN_Pos_3v)
ƒ"CLK_XTLCTL_XTL_TST_EN_Pos (1)
„"CLK_XTLCTL_XTL_TST_EN_Msk (0x1ul << CLK_XTLCTL_XTL_TST_EN_Pos)
…"CLK_XTLCTL_CORE_BIAS_Pos_3v (4)
†"CLK_XTLCTL_CORE_BIAS_Msk_3v (0x7ul << CLK_XTLCTL_CORE_BIAS_Pos_3v)
‡"CLK_XTLCTL_XTL_TRIM_Pos_3v (7)
ˆ"CLK_XTLCTL_XTL_TRIM_Msk_3v (0x3Ful << CLK_XTLCTL_XTL_TRIM_Pos_3v)
‰"CLK_XTLCTL_XTL_CAP_EN_Pos_3v (13)
Š"CLK_XTLCTL_XTL_CAP_EN_Msk_3v (0x1ul << CLK_XTLCTL_XTL_CAP_EN_Pos_3v)
‹"CLK_XTLCTL_DELAY_Pos_3v (16)
Œ"CLK_XTLCTL_DELAY_Msk_3v (0x3ul << CLK_XTLCTL_DELAY_Pos_3v)
"CLK_XTLCTL_STABLE_Pos (24)
Ž"CLK_XTLCTL_STABLE_Msk (0x1ul << CLK_XTLCTL_STABLE_Pos)
‘"CLK_XTHCTL_XTH_EN_Pos (0)
’"CLK_XTHCTL_XTH_EN_Msk (0x1ul << CLK_XTHCTL_XTH_EN_Pos)
“"CLK_XTHCTL_XTH_TST_EN_Pos (1)
”"CLK_XTHCTL_XTH_TST_EN_Msk (0x1ul << CLK_XTHCTL_XTH_TST_EN_Pos)
•"CLK_XTHCTL_START_FAST_Pos (2)
–"CLK_XTHCTL_START_FAST_Msk (0x1ul << CLK_XTHCTL_START_FAST_Pos)
—"CLK_XTHCTL_DEGLITCH_EN_Pos (3)
˜"CLK_XTHCTL_DEGLITCH_EN_Msk (0x1ul << CLK_XTHCTL_DEGLITCH_EN_Pos)
™"CLK_XTHCTL_XO_CAP_SEL_Pos (4)
š"CLK_XTHCTL_XO_CAP_SEL_Msk (0x3ful << CLK_XTHCTL_XO_CAP_SEL_Pos)
›"CLK_XTHCTL_DELAY_Pos (16)
œ"CLK_XTHCTL_DELAY_Msk (0x1ul << CLK_XTHCTL_DELAY_Pos)
"CLK_XTHCTL_STABLE_Pos (24)
ž"CLK_XTHCTL_STABLE_Msk (0x1ul << CLK_XTHCTL_STABLE_Pos)
¡"CLK_DPLLCTL_DPLL_EN_Pos (0)
¢"CLK_DPLLCTL_DPLL_EN_Msk (0x1ul << CLK_DPLLCTL_DPLL_EN_Pos)
£"CLK_DPLLCTL_DPLL_TST_EN_Pos (1)
¤"CLK_DPLLCTL_DPLL_TST_EN_Msk (0x1ul << CLK_DPLLCTL_DPLL_TST_EN_Pos)
¥"CLK_DPLLCTL_FREQ_OUT_Pos (2)
¦"CLK_DPLLCTL_FREQ_OUT_Msk (0x1ul << CLK_DPLLCTL_FREQ_OUT_Pos)
§"CLK_DPLLCTL_RCLK_SEL_Pos (3)
¨"CLK_DPLLCTL_RCLK_SEL_Msk (0x1ul << CLK_DPLLCTL_RCLK_SEL_Pos)
©"CLK_DPLLCTL_ICP_BIAS_Pos (4)
ª"CLK_DPLLCTL_ICP_BIAS_Msk (0x3ul << CLK_DPLLCTL_ICP_BIAS_Pos)
«"CLK_DPLLCTL_ICP_CTRL_Pos (6)
¬"CLK_DPLLCTL_ICP_CTRL_Msk (0x3ul << CLK_DPLLCTL_ICP_CTRL_Pos)
­"CLK_DPLLCTL_KVCO_CTRL_Pos (8)
®"CLK_DPLLCTL_KVCO_CTRL_Msk (0x7ul << CLK_DPLLCTL_KVCO_CTRL_Pos)
¯"CLK_DPLLCTL_VCO_FREQ_TRIM_Pos (11)
°"CLK_DPLLCTL_VCO_FREQ_TRIM_Msk (0x3ul << CLK_DPLLCTL_VCO_FREQ_TRIM_Pos)
±"CLK_DPLLCTL_DIV_SEL_Pos (13)
²"CLK_DPLLCTL_DIV_SEL_Msk (0x1ul << CLK_DPLLCTL_DIV_SEL_Pos)
³"CLK_DPLLCTL_DELAY_Pos (16)
´"CLK_DPLLCTL_DELAY_Msk (0x3ul << CLK_DPLLCTL_STARTUP_Pos)
µ"CLK_DPLLCTL_STABLE_Pos (24)
¶"CLK_DPLLCTL_STABLE_Msk (0x1ul << CLK_DPLLCTL_STABLE_Pos)
¹"CLK_AHBCLK_DMAEN_Pos (0)
º"CLK_AHBCLK_DMAEN_Msk (0x1ul << CLK_AHBCLK_DMAEN_Pos)
»"CLK_AHBCLK_GPIOEN_Pos (1)
¼"CLK_AHBCLK_GPIOEN_Msk (0x1ul << CLK_AHBCLK_GPIOEN_Pos)
½"CLK_AHBCLK_SYSTICK_EN_Pos (2)
¾"CLK_AHBCLK_SYSTICK_EN_Msk (0x1ul << CLK_AHBCLK_SYSTICK_EN_Pos)
¿"CLK_AHBCLK_APB1EN_Pos (3)
À"CLK_AHBCLK_APB1EN_Msk (0x1ul << CLK_AHBCLK_APB1EN_Pos)
Á"CLK_AHBCLK_APB2EN_Pos (4)
Â"CLK_AHBCLK_APB2EN_Msk (0x1ul << CLK_AHBCLK_APB2EN_Pos)
Ã"CLK_AHBCLK_AHBEN_Pos (5)
Ä"CLK_AHBCLK_AHBEN_Msk (0x1ul << CLK_AHBCLK_AHBEN_Pos)
Å"CLK_AHBCLK_BLE32M_EN_Pos (6)
Æ"CLK_AHBCLK_BLE32M_EN_Msk (0x1ul << CLK_AHBCLK_BLE32M_EN_Pos)
Ç"CLK_AHBCLK_BLE32K_EN_Pos (7)
È"CLK_AHBCLK_BLE32K_EN_Msk (0x1ul << CLK_AHBCLK_BLE32K_EN_Pos)
É"CLK_AHBCLK_BLE32M_SEL_Pos (8)
Ê"CLK_AHBCLK_BLE32M_SEL_Msk (0x3ul << CLK_AHBCLK_BLE32M_SEL_Pos)
Ë"CLK_AHBCLK_ROM_CLK_EN_Pos (10)
Ì"CLK_AHBCLK_ROM_CLK_EN_Msk (0x1ul << CLK_AHBCLK_ROM_CLK_EN_Pos)
Í"CLK_AHBCLK_EFUSE_CLK_EN_Pos (11)
Î"CLK_AHBCLK_EFUSE_CLK_EN_Msk (0x1ul << CLK_AHBCLK_EFUSE_CLK_EN_Pos)
Ï"CLK_AHBCLK_USB_AHB_CLK_EN_Pos (13)
Ð"CLK_AHBCLK_USB_AHB_CLK_EN_Msk (0x1ul << CLK_AHBCLK_USB_AHB_CLK_EN_Pos)
Ñ"CLK_AHBCLK_USB_48M_CLK_EN_Pos (14)
Ò"CLK_AHBCLK_USB_48M_CLK_EN_Msk (0x1ul << CLK_AHBCLK_USB_48M_CLK_EN_Pos)
Ó"CLK_AHBCLK_SPI_FLASH_DIV_Pos (16)
Ô"CLK_AHBCLK_SPI_FLASH_DIV_Msk (0xFul << CLK_AHBCLK_SPI_FLASH_DIV_Pos)
Õ"CLK_AHBCLK_SPI_FLASH_CLK_SEL_Pos (20)
Ö"CLK_AHBCLK_SPI_FLASH_CLK_SEL_Msk (0x1ul << CLK_AHBCLK_SPI_FLASH_CLK_SEL_Pos)
×"CLK_AHBCLK_DPLL_CLK_TST_EN_Pos (21)
Ø"CLK_AHBCLK_DPLL_CLK_TST_EN_Msk (0x1ul << CLK_AHBCLK_DPLL_CLK_TST_EN_Pos)
Ù"CLK_AHBCLK_SPI_CLK_SEL_FPGA_Pos (24)
Ú"CLK_AHBCLK_SPI_CLK_SEL_FPGA_Msk (0x1ul << CLK_AHBCLK_SPI_CLK_SEL_FPGA_Pos)
Ý"CLK_APB1CLK_WDTSRC_SEL_Pos (16)
Þ"CLK_APB1CLK_WDTSRC_SEL_Msk (0x1ul << CLK_APB1CLK_WDTSRC_SEL_Pos)
ß"CLK_APB1CLK_WWDTSRC_SEL_Pos (17)
à"CLK_APB1CLK_WWDTSRC_SEL_Msk (0x1ul << CLK_APB1CLK_WWDTSRC_SEL_Pos)
á"CLK_APB1CLK_TMR0SRC_SEL_Pos (18)
â"CLK_APB1CLK_TMR0SRC_SEL_Msk (0x3ul << CLK_APB1CLK_TMR0SRC_SEL_Pos)
ã"CLK_APB1CLK_PWM01_CLK_SEL_Pos (20)
ä"CLK_APB1CLK_PWM01_CLK_SEL_Msk (0x1ul << CLK_APB1CLK_PWM01_CLK_SEL_Pos)
å"CLK_APB1CLK_PWM23_CLK_SEL_Pos (21)
æ"CLK_APB1CLK_PWM23_CLK_SEL_Msk (0x1ul << CLK_APB1CLK_PWM23_CLK_SEL_Pos)
ç"CLK_APB1CLK_PWM45_CLK_SEL_Pos (22)
è"CLK_APB1CLK_PWM45_CLK_SEL_Msk (0x1ul << CLK_APB1CLK_PWM45_CLK_SEL_Pos)
é"CLK_APB1CLK_PWM67_CLK_SEL_Pos (23)
ê"CLK_APB1CLK_PWM67_CLK_SEL_Msk (0x1ul << CLK_APB1CLK_PWM67_CLK_SEL_Pos)
ë"CLK_APB1CLK_ADC_CLK_SEL_Pos (24)
ì"CLK_APB1CLK_ADC_CLK_SEL_Msk (0x1ul << CLK_APB1CLK_ADC_CLK_SEL_Pos)
ï"CLK_APB2CLK_TMR1SRC_SEL_Pos (8)
ð"CLK_APB2CLK_TMR1SRC_SEL_Msk (0x3ul << CLK_APB2CLK_TMR1SRC_SEL_Pos)
ñ"CLK_APB2CLK_TMR2SRC_SEL_Pos (10)
ò"CLK_APB2CLK_TMR2SRC_SEL_Msk (0x3ul << CLK_APB2CLK_TMR2SRC_SEL_Pos)
ö"CLK_MEASCLK_TRIM_CLK_EN_Pos (1)
÷"CLK_MEASCLK_TRIM_CLK_EN_Msk (0x1ul << CLK_MEASCLK_TRIM_CLK_EN_Pos)
ø"CLK_MEASCLK_TRIM_CLK_SEL_Pos (2)
ù"CLK_MEASCLK_TRIM_CLK_SEL_Msk (0x1ul << CLK_MEASCLK_TRIM_CLK_SEL_Pos)
ú"CLK_MEASCLK_TRIM_CLK_DIV_Pos (4)
û"CLK_MEASCLK_TRIM_CLK_DIV_Msk (0x1fful << CLK_MEASCLK_TRIM_CLK_DIV_Pos)
ü"CLK_MEASCLK_XTL_QUICK_EN_Pos (14)
ý"CLK_MEASCLK_XTL_QUICK_EN_Msk (0x1ul << CLK_MEASCLK_XTL_QUICK_EN_Pos)
þ"CLK_MEASCLK_XTH_DIV_Pos (15)
ÿ"CLK_MEASCLK_XTH_DIV_Msk (0x1fful << CLK_MEASCLK_XTH_DIV_Pos)
ó#WDT_CTL_RSTCNT_Pos (0)
ô#WDT_CTL_RSTCNT_Msk (0x1ul << WDT_CTL_RSTCNT_Pos)
ö#WDT_CTL_RSTEN_Pos (1)
÷#WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos)
ù#WDT_CTL_RSTF_Pos (2)
ú#WDT_CTL_RSTF_Msk (0x1ul << WDT_CTL_RSTF_Pos)
ü#WDT_CTL_IF_Pos (3)
ý#WDT_CTL_IF_Msk (0x1ul << WDT_CTL_IF_Pos)
ÿ#WDT_CTL_WKEN_Pos (4)
€$WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos)
‚$WDT_CTL_WKF_Pos (5)
ƒ$WDT_CTL_WKF_Msk (0x1ul << WDT_CTL_WKF_Pos)
…$WDT_CTL_INTEN_Pos (6)
†$WDT_CTL_INTEN_Msk (0x1ul << WDT_CTL_INTEN_Pos)
ˆ$WDT_CTL_WDTEN_Pos (7)
‰$WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos)
‹$WDT_CTL_TOUTSEL_Pos (8)
Œ$WDT_CTL_TOUTSEL_Msk (0xful << WDT_CTL_TOUTSEL_Pos)
Ž$WDT_CTL_RST_REGION_SEL_Pos (12)
$WDT_CTL_RST_REGION_SEL_Msk (0x1ul << WDT_CTL_RST_REGION_SEL_Pos)
‘$WDT_CTL_TOF_Pos (16)
’$WDT_CTL_TOF_Msk (0x1ul << WDT_CTL_TOF_Pos)
”$WDT_CTL_ICEDEBUG_Pos (31)
•$WDT_CTL_ICEDEBUG_Msk (0x1ul << WDT_CTL_ICEDEBUG_Pos)
—$WDT_ALTCTL_RSTDSEL_Pos (0)
˜$WDT_ALTCTL_RSTDSEL_Msk (0x3ul << WDT_ALTCTL_RSTDSEL_Pos)
•%WWDT_RLDCNT_RLDCNT_Pos (0)
–%WWDT_RLDCNT_RLDCNT_Msk (0xfffffffful << WWDT_RLDCNT_RLDCNT_Pos)
˜%WWDT_CTL_WWDTEN_Pos (0)
™%WWDT_CTL_WWDTEN_Msk (0x1ul << WWDT_CTL_WWDTEN_Pos)
›%WWDT_CTL_INTEN_Pos (1)
œ%WWDT_CTL_INTEN_Msk (0x1ul << WWDT_CTL_INTEN_Pos)
ž%WWDT_CTL_PSCSEL_Pos (8)
Ÿ%WWDT_CTL_PSCSEL_Msk (0xful << WWDT_CTL_PSCSEL_Pos)
¡%WWDT_CTL_CMPDAT_Pos (16)
¢%WWDT_CTL_CMPDAT_Msk (0x3ful << WWDT_CTL_CMPDAT_Pos)
¤%WWDT_CTL_ICEDEBUG_Pos (31)
¥%WWDT_CTL_ICEDEBUG_Msk (0x1ul << WWDT_CTL_ICEDEBUG_Pos)
§%WWDT_STATUS_WWDTIF_Pos (0)
¨%WWDT_STATUS_WWDTIF_Msk (0x1ul << WWDT_STATUS_WWDTIF_Pos)
ª%WWDT_STATUS_WWDTRF_Pos (1)
«%WWDT_STATUS_WWDTRF_Msk (0x1ul << WWDT_STATUS_WWDTRF_Pos)
­%WWDT_STATUS_WWDTF_Pos (2)
®%WWDT_STATUS_WWDTF_Msk (0x1ul << WWDT_STATUS_WWDTF_Pos)
°%WWDT_CNT_CNTDAT_Pos (0)
±%WWDT_CNT_CNTDAT_Msk (0x3ful << WWDT_CNT_CNTDAT_Pos)
¹.PWM_CLKPSC_CLKPSC01_Pos (0)
º.PWM_CLKPSC_CLKPSC01_Msk (0xfful << PWM_CLKPSC_CLKPSC01_Pos)
¼.PWM_CLKPSC_CLKPSC23_Pos (8)
½.PWM_CLKPSC_CLKPSC23_Msk (0xfful << PWM_CLKPSC_CLKPSC23_Pos)
¿.PWM_CLKPSC_CLKPSC45_Pos (16)
À.PWM_CLKPSC_CLKPSC45_Msk (0xfful << PWM_CLKPSC_CLKPSC45_Pos)
Â.PWM_CLKPSC_CLKPSC67_Pos (24)
Ã.PWM_CLKPSC_CLKPSC67_Msk (0xfful << PWM_CLKPSC_CLKPSC67_Pos)
Å.PWM_CLKDIV_CLKDIV0_Pos (0)
Æ.PWM_CLKDIV_CLKDIV0_Msk (0x7ul << PWM_CLKDIV_CLKDIV0_Pos)
È.PWM_CLKDIV_CLKDIV1_Pos (4)
É.PWM_CLKDIV_CLKDIV1_Msk (0x7ul << PWM_CLKDIV_CLKDIV1_Pos)
Ë.PWM_CLKDIV_CLKDIV2_Pos (8)
Ì.PWM_CLKDIV_CLKDIV2_Msk (0x7ul << PWM_CLKDIV_CLKDIV2_Pos)
Î.PWM_CLKDIV_CLKDIV3_Pos (12)
Ï.PWM_CLKDIV_CLKDIV3_Msk (0x7ul << PWM_CLKDIV_CLKDIV3_Pos)
Ñ.PWM_CLKDIV_CLKDIV4_Pos (16)
Ò.PWM_CLKDIV_CLKDIV4_Msk (0x7ul << PWM_CLKDIV_CLKDIV4_Pos)
Ô.PWM_CLKDIV_CLKDIV5_Pos (20)
Õ.PWM_CLKDIV_CLKDIV5_Msk (0x7ul << PWM_CLKDIV_CLKDIV5_Pos)
Ø.PWM_CLKDIV_CLKDIV6_Pos (24)
Ù.PWM_CLKDIV_CLKDIV6_Msk (0x7ul << PWM_CLKDIV_CLKDIV6_Pos)
Û.PWM_CLKDIV_CLKDIV7_Pos (28)
Ü.PWM_CLKDIV_CLKDIV7_Msk (0x7ul << PWM_CLKDIV_CLKDIV7_Pos)
Þ.PWM_CTL_CNTEN0_Pos (0)
ß.PWM_CTL_CNTEN0_Msk (0x1ul << PWM_CTL_CNTEN0_Pos)
á.PWM_CTL_PINV0_Pos (2)
â.PWM_CTL_PINV0_Msk (0x1ul << PWM_CTL_PINV0_Pos)
ä.PWM_CTL_CNTMODE0_Pos (3)
å.PWM_CTL_CNTMODE0_Msk (0x1ul << PWM_CTL_CNTMODE0_Pos)
ç.PWM_CTL_CNTEN1_Pos (4)
è.PWM_CTL_CNTEN1_Msk (0x1ul << PWM_CTL_CNTEN1_Pos)
ê.PWM_CTL_HCUPDT_Pos (5)
ë.PWM_CTL_HCUPDT_Msk (0x1ul << PWM_CTL_HCUPDT_Pos)
í.PWM_CTL_PINV1_Pos (6)
î.PWM_CTL_PINV1_Msk (0x1ul << PWM_CTL_PINV1_Pos)
ð.PWM_CTL_CNTMODE1_Pos (7)
ñ.PWM_CTL_CNTMODE1_Msk (0x1ul << PWM_CTL_CNTMODE1_Pos)
ó.PWM_CTL_CNTEN2_Pos (8)
ô.PWM_CTL_CNTEN2_Msk (0x1ul << PWM_CTL_CNTEN2_Pos)
ö.PWM_CTL_PINV2_Pos (10)
÷.PWM_CTL_PINV2_Msk (0x1ul << PWM_CTL_PINV2_Pos)
ù.PWM_CTL_CNTMODE2_Pos (11)
ú.PWM_CTL_CNTMODE2_Msk (0x1ul << PWM_CTL_CNTMODE2_Pos)
ü.PWM_CTL_CNTEN3_Pos (12)
ý.PWM_CTL_CNTEN3_Msk (0x1ul << PWM_CTL_CNTEN3_Pos)
ÿ.PWM_CTL_PINV3_Pos (14)
€/PWM_CTL_PINV3_Msk (0x1ul << PWM_CTL_PINV3_Pos)
‚/PWM_CTL_CNTMODE3_Pos (15)
ƒ/PWM_CTL_CNTMODE3_Msk (0x1ul << PWM_CTL_CNTMODE3_Pos)
…/PWM_CTL_CNTEN4_Pos (16)
†/PWM_CTL_CNTEN4_Msk (0x1ul << PWM_CTL_CNTEN4_Pos)
ˆ/PWM_CTL_PINV4_Pos (18)
‰/PWM_CTL_PINV4_Msk (0x1ul << PWM_CTL_PINV4_Pos)
‹/PWM_CTL_CNTMODE4_Pos (19)
Œ/PWM_CTL_CNTMODE4_Msk (0x1ul << PWM_CTL_CNTMODE4_Pos)
Ž/PWM_CTL_CNTEN5_Pos (20)
/PWM_CTL_CNTEN5_Msk (0x1ul << PWM_CTL_CNTEN5_Pos)
‘/PWM_CTL_ASYMEN_Pos (21)
’/PWM_CTL_ASYMEN_Msk (0x1ul << PWM_CTL_ASYMEN_Pos)
”/PWM_CTL_PINV5_Pos (22)
•/PWM_CTL_PINV5_Msk (0x1ul << PWM_CTL_PINV5_Pos)
—/PWM_CTL_CNTMODE5_Pos (23)
˜/PWM_CTL_CNTMODE5_Msk (0x1ul << PWM_CTL_CNTMODE5_Pos)
š/PWM_CTL_CNTEN6_Pos (24)
›/PWM_CTL_CNTEN6_Msk (0x1ul << PWM_CTL_CNTEN6_Pos)
/PWM_CTL_PINV6_Pos (26)
ž/PWM_CTL_PINV6_Msk (0x1ul << PWM_CTL_PINV6_Pos)
 /PWM_CTL_CNTMODE6_Pos (27)
¡/PWM_CTL_CNTMODE6_Msk (0x1ul << PWM_CTL_CNTMODE6_Pos)
£/PWM_CTL_CNTEN7_Pos (28)
¤/PWM_CTL_CNTEN7_Msk (0x1ul << PWM_CTL_CNTEN7_Pos)
¦/PWM_CTL_PINV7_Pos (30)
§/PWM_CTL_PINV7_Msk (0x1ul << PWM_CTL_PINV7_Pos)
©/PWM_CTL_CNTMODE7_Pos (31)
ª/PWM_CTL_CNTMODE7_Msk (0x1ul << PWM_CTL_CNTMODE7_Pos)
¬/PWM_PERIOD0_PERIOD0_Pos (0)
­/PWM_PERIOD0_PERIOD0_Msk (0xfffful << PWM_PERIOD0_PERIOD0_Pos)
¯/PWM_PERIOD0_PERIOD1_Pos (0)
°/PWM_PERIOD0_PERIOD1_Msk (0xfffful << PWM_PERIOD0_PERIOD1_Pos)
²/PWM_PERIOD0_PERIOD2_Pos (0)
³/PWM_PERIOD0_PERIOD2_Msk (0xfffful << PWM_PERIOD0_PERIOD2_Pos)
µ/PWM_PERIOD0_PERIOD3_Pos (0)
¶/PWM_PERIOD0_PERIOD3_Msk (0xfffful << PWM_PERIOD0_PERIOD3_Pos)
¸/PWM_PERIOD0_PERIOD4_Pos (0)
¹/PWM_PERIOD0_PERIOD4_Msk (0xfffful << PWM_PERIOD0_PERIOD4_Pos)
»/PWM_PERIOD0_PERIOD5_Pos (0)
¼/PWM_PERIOD0_PERIOD5_Msk (0xfffful << PWM_PERIOD0_PERIOD5_Pos)
¾/PWM_PERIOD0_PERIOD6_Pos (0)
¿/PWM_PERIOD0_PERIOD6_Msk (0xfffful << PWM_PERIOD0_PERIOD6_Pos)
Á/PWM_PERIOD0_PERIOD7_Pos (0)
Â/PWM_PERIOD0_PERIOD7_Msk (0xfffful << PWM_PERIOD0_PERIOD7_Pos)
Ä/PWM_PERIOD1_PERIOD0_Pos (0)
Å/PWM_PERIOD1_PERIOD0_Msk (0xfffful << PWM_PERIOD1_PERIOD0_Pos)
Ç/PWM_PERIOD1_PERIOD1_Pos (0)
È/PWM_PERIOD1_PERIOD1_Msk (0xfffful << PWM_PERIOD1_PERIOD1_Pos)
Ê/PWM_PERIOD1_PERIOD2_Pos (0)
Ë/PWM_PERIOD1_PERIOD2_Msk (0xfffful << PWM_PERIOD1_PERIOD2_Pos)
Í/PWM_PERIOD1_PERIOD3_Pos (0)
Î/PWM_PERIOD1_PERIOD3_Msk (0xfffful << PWM_PERIOD1_PERIOD3_Pos)
Ð/PWM_PERIOD1_PERIOD4_Pos (0)
Ñ/PWM_PERIOD1_PERIOD4_Msk (0xfffful << PWM_PERIOD1_PERIOD4_Pos)
Ó/PWM_PERIOD1_PERIOD5_Pos (0)
Ô/PWM_PERIOD1_PERIOD5_Msk (0xfffful << PWM_PERIOD1_PERIOD5_Pos)
Ö/PWM_PERIOD1_PERIOD6_Pos (0)
×/PWM_PERIOD1_PERIOD6_Msk (0xfffful << PWM_PERIOD1_PERIOD6_Pos)
Ù/PWM_PERIOD1_PERIOD7_Pos (0)
Ú/PWM_PERIOD1_PERIOD7_Msk (0xfffful << PWM_PERIOD1_PERIOD7_Pos)
Ü/PWM_PERIOD2_PERIOD0_Pos (0)
Ý/PWM_PERIOD2_PERIOD0_Msk (0xfffful << PWM_PERIOD2_PERIOD0_Pos)
ß/PWM_PERIOD2_PERIOD1_Pos (0)
à/PWM_PERIOD2_PERIOD1_Msk (0xfffful << PWM_PERIOD2_PERIOD1_Pos)
â/PWM_PERIOD2_PERIOD2_Pos (0)
ã/PWM_PERIOD2_PERIOD2_Msk (0xfffful << PWM_PERIOD2_PERIOD2_Pos)
å/PWM_PERIOD2_PERIOD3_Pos (0)
æ/PWM_PERIOD2_PERIOD3_Msk (0xfffful << PWM_PERIOD2_PERIOD3_Pos)
è/PWM_PERIOD2_PERIOD4_Pos (0)
é/PWM_PERIOD2_PERIOD4_Msk (0xfffful << PWM_PERIOD2_PERIOD4_Pos)
ë/PWM_PERIOD2_PERIOD5_Pos (0)
ì/PWM_PERIOD2_PERIOD5_Msk (0xfffful << PWM_PERIOD2_PERIOD5_Pos)
î/PWM_PERIOD2_PERIOD6_Pos (0)
ï/PWM_PERIOD2_PERIOD6_Msk (0xfffful << PWM_PERIOD2_PERIOD6_Pos)
ñ/PWM_PERIOD2_PERIOD7_Pos (0)
ò/PWM_PERIOD2_PERIOD7_Msk (0xfffful << PWM_PERIOD2_PERIOD7_Pos)
ô/PWM_PERIOD3_PERIOD0_Pos (0)
õ/PWM_PERIOD3_PERIOD0_Msk (0xfffful << PWM_PERIOD3_PERIOD0_Pos)
÷/PWM_PERIOD3_PERIOD1_Pos (0)
ø/PWM_PERIOD3_PERIOD1_Msk (0xfffful << PWM_PERIOD3_PERIOD1_Pos)
ú/PWM_PERIOD3_PERIOD2_Pos (0)
û/PWM_PERIOD3_PERIOD2_Msk (0xfffful << PWM_PERIOD3_PERIOD2_Pos)
ý/PWM_PERIOD3_PERIOD3_Pos (0)
þ/PWM_PERIOD3_PERIOD3_Msk (0xfffful << PWM_PERIOD3_PERIOD3_Pos)
€0PWM_PERIOD3_PERIOD4_Pos (0)
0PWM_PERIOD3_PERIOD4_Msk (0xfffful << PWM_PERIOD3_PERIOD4_Pos)
ƒ0PWM_PERIOD3_PERIOD5_Pos (0)
„0PWM_PERIOD3_PERIOD5_Msk (0xfffful << PWM_PERIOD3_PERIOD5_Pos)
†0PWM_PERIOD3_PERIOD6_Pos (0)
‡0PWM_PERIOD3_PERIOD6_Msk (0xfffful << PWM_PERIOD3_PERIOD6_Pos)
‰0PWM_PERIOD3_PERIOD7_Pos (0)
Š0PWM_PERIOD3_PERIOD7_Msk (0xfffful << PWM_PERIOD3_PERIOD7_Pos)
Œ0PWM_PERIOD4_PERIOD0_Pos (0)
0PWM_PERIOD4_PERIOD0_Msk (0xfffful << PWM_PERIOD4_PERIOD0_Pos)
0PWM_PERIOD4_PERIOD1_Pos (0)
0PWM_PERIOD4_PERIOD1_Msk (0xfffful << PWM_PERIOD4_PERIOD1_Pos)
’0PWM_PERIOD4_PERIOD2_Pos (0)
“0PWM_PERIOD4_PERIOD2_Msk (0xfffful << PWM_PERIOD4_PERIOD2_Pos)
•0PWM_PERIOD4_PERIOD3_Pos (0)
–0PWM_PERIOD4_PERIOD3_Msk (0xfffful << PWM_PERIOD4_PERIOD3_Pos)
˜0PWM_PERIOD4_PERIOD4_Pos (0)
™0PWM_PERIOD4_PERIOD4_Msk (0xfffful << PWM_PERIOD4_PERIOD4_Pos)
›0PWM_PERIOD4_PERIOD5_Pos (0)
œ0PWM_PERIOD4_PERIOD5_Msk (0xfffful << PWM_PERIOD4_PERIOD5_Pos)
ž0PWM_PERIOD4_PERIOD6_Pos (0)
Ÿ0PWM_PERIOD4_PERIOD6_Msk (0xfffful << PWM_PERIOD4_PERIOD6_Pos)
¡0PWM_PERIOD4_PERIOD7_Pos (0)
¢0PWM_PERIOD4_PERIOD7_Msk (0xfffful << PWM_PERIOD4_PERIOD7_Pos)
¤0PWM_PERIOD5_PERIOD0_Pos (0)
¥0PWM_PERIOD5_PERIOD0_Msk (0xfffful << PWM_PERIOD5_PERIOD0_Pos)
§0PWM_PERIOD5_PERIOD1_Pos (0)
¨0PWM_PERIOD5_PERIOD1_Msk (0xfffful << PWM_PERIOD5_PERIOD1_Pos)
ª0PWM_PERIOD5_PERIOD2_Pos (0)
«0PWM_PERIOD5_PERIOD2_Msk (0xfffful << PWM_PERIOD5_PERIOD2_Pos)
­0PWM_PERIOD5_PERIOD3_Pos (0)
®0PWM_PERIOD5_PERIOD3_Msk (0xfffful << PWM_PERIOD5_PERIOD3_Pos)
°0PWM_PERIOD5_PERIOD4_Pos (0)
±0PWM_PERIOD5_PERIOD4_Msk (0xfffful << PWM_PERIOD5_PERIOD4_Pos)
³0PWM_PERIOD5_PERIOD5_Pos (0)
´0PWM_PERIOD5_PERIOD5_Msk (0xfffful << PWM_PERIOD5_PERIOD5_Pos)
¶0PWM_PERIOD5_PERIOD6_Pos (0)
·0PWM_PERIOD5_PERIOD6_Msk (0xfffful << PWM_PERIOD6_PERIOD6_Pos)
¹0PWM_PERIOD5_PERIOD7_Pos (0)
º0PWM_PERIOD5_PERIOD7_Msk (0xfffful << PWM_PERIOD6_PERIOD7_Pos)
¼0PWM_PERIOD6_PERIOD0_Pos (0)
½0PWM_PERIOD6_PERIOD0_Msk (0xfffful << PWM_PERIOD6_PERIOD0_Pos)
¿0PWM_PERIOD6_PERIOD1_Pos (0)
À0PWM_PERIOD6_PERIOD1_Msk (0xfffful << PWM_PERIOD6_PERIOD1_Pos)
Â0PWM_PERIOD6_PERIOD2_Pos (0)
Ã0PWM_PERIOD6_PERIOD2_Msk (0xfffful << PWM_PERIOD6_PERIOD2_Pos)
Å0PWM_PERIOD6_PERIOD3_Pos (0)
Æ0PWM_PERIOD6_PERIOD3_Msk (0xfffful << PWM_PERIOD6_PERIOD3_Pos)
È0PWM_PERIOD6_PERIOD4_Pos (0)
É0PWM_PERIOD6_PERIOD4_Msk (0xfffful << PWM_PERIOD6_PERIOD4_Pos)
Ë0PWM_PERIOD6_PERIOD5_Pos (0)
Ì0PWM_PERIOD6_PERIOD5_Msk (0xfffful << PWM_PERIOD6_PERIOD5_Pos)
Î0PWM_PERIOD6_PERIOD6_Pos (0)
Ï0PWM_PERIOD6_PERIOD6_Msk (0xfffful << PWM_PERIOD6_PERIOD6_Pos)
Ñ0PWM_PERIOD6_PERIOD7_Pos (0)
Ò0PWM_PERIOD6_PERIOD7_Msk (0xfffful << PWM_PERIOD6_PERIOD7_Pos)
Ô0PWM_PERIOD7_PERIOD0_Pos (0)
Õ0PWM_PERIOD7_PERIOD0_Msk (0xfffful << PWM_PERIOD7_PERIOD0_Pos)
×0PWM_PERIOD7_PERIOD1_Pos (0)
Ø0PWM_PERIOD7_PERIOD1_Msk (0xfffful << PWM_PERIOD7_PERIOD1_Pos)
Ú0PWM_PERIOD7_PERIOD2_Pos (0)
Û0PWM_PERIOD7_PERIOD2_Msk (0xfffful << PWM_PERIOD7_PERIOD2_Pos)
Ý0PWM_PERIOD7_PERIOD3_Pos (0)
Þ0PWM_PERIOD7_PERIOD3_Msk (0xfffful << PWM_PERIOD7_PERIOD3_Pos)
à0PWM_PERIOD7_PERIOD4_Pos (0)
á0PWM_PERIOD7_PERIOD4_Msk (0xfffful << PWM_PERIOD7_PERIOD4_Pos)
ã0PWM_PERIOD7_PERIOD5_Pos (0)
ä0PWM_PERIOD7_PERIOD5_Msk (0xfffful << PWM_PERIOD7_PERIOD5_Pos)
æ0PWM_PERIOD7_PERIOD6_Pos (0)
ç0PWM_PERIOD7_PERIOD6_Msk (0xfffful << PWM_PERIOD7_PERIOD6_Pos)
é0PWM_PERIOD7_PERIOD7_Pos (0)
ê0PWM_PERIOD7_PERIOD7_Msk (0xfffful << PWM_PERIOD7_PERIOD7_Pos)
ì0PWM_CMPDAT0_CMP0_Pos (0)
í0PWM_CMPDAT0_CMP0_Msk (0xfffful << PWM_CMPDAT0_CMP0_Pos)
ï0PWM_CMPDAT0_CMP1_Pos (0)
ð0PWM_CMPDAT0_CMP1_Msk (0xfffful << PWM_CMPDAT0_CMP1_Pos)
ò0PWM_CMPDAT0_CMP2_Pos (0)
ó0PWM_CMPDAT0_CMP2_Msk (0xfffful << PWM_CMPDAT0_CMP2_Pos)
õ0PWM_CMPDAT0_CMP3_Pos (0)
ö0PWM_CMPDAT0_CMP3_Msk (0xfffful << PWM_CMPDAT0_CMP3_Pos)
ø0PWM_CMPDAT0_CMP4_Pos (0)
ù0PWM_CMPDAT0_CMP4_Msk (0xfffful << PWM_CMPDAT0_CMP4_Pos)
û0PWM_CMPDAT0_CMP5_Pos (0)
ü0PWM_CMPDAT0_CMP5_Msk (0xfffful << PWM_CMPDAT0_CMP5_Pos)
þ0PWM_CMPDAT0_CMP6_Pos (0)
ÿ0PWM_CMPDAT0_CMP6_Msk (0xfffful << PWM_CMPDAT0_CMP6_Pos)
1PWM_CMPDAT0_CMP7_Pos (0)
‚1PWM_CMPDAT0_CMP7_Msk (0xfffful << PWM_CMPDAT0_CMP7_Pos)
„1PWM_CMPDAT0_CMPD0_Pos (16)
…1PWM_CMPDAT0_CMPD0_Msk (0xfffful << PWM_CMPDAT0_CMPD0_Pos)
‡1PWM_CMPDAT0_CMPD1_Pos (16)
ˆ1PWM_CMPDAT0_CMPD1_Msk (0xfffful << PWM_CMPDAT0_CMPD1_Pos)
Š1PWM_CMPDAT0_CMPD2_Pos (16)
‹1PWM_CMPDAT0_CMPD2_Msk (0xfffful << PWM_CMPDAT0_CMPD2_Pos)
1PWM_CMPDAT0_CMPD3_Pos (16)
Ž1PWM_CMPDAT0_CMPD3_Msk (0xfffful << PWM_CMPDAT0_CMPD3_Pos)
1PWM_CMPDAT0_CMPD4_Pos (16)
‘1PWM_CMPDAT0_CMPD4_Msk (0xfffful << PWM_CMPDAT0_CMPD4_Pos)
“1PWM_CMPDAT0_CMPD5_Pos (16)
”1PWM_CMPDAT0_CMPD5_Msk (0xfffful << PWM_CMPDAT0_CMPD5_Pos)
–1PWM_CMPDAT0_CMPD6_Pos (16)
—1PWM_CMPDAT0_CMPD6_Msk (0xfffful << PWM_CMPDAT0_CMPD6_Pos)
™1PWM_CMPDAT0_CMPD7_Pos (16)
š1PWM_CMPDAT0_CMPD7_Msk (0xfffful << PWM_CMPDAT0_CMPD7_Pos)
œ1PWM_CMPDAT1_CMP0_Pos (0)
1PWM_CMPDAT1_CMP0_Msk (0xfffful << PWM_CMPDAT1_CMP0_Pos)
Ÿ1PWM_CMPDAT1_CMP1_Pos (0)
 1PWM_CMPDAT1_CMP1_Msk (0xfffful << PWM_CMPDAT1_CMP1_Pos)
¢1PWM_CMPDAT1_CMP2_Pos (0)
£1PWM_CMPDAT1_CMP2_Msk (0xfffful << PWM_CMPDAT1_CMP2_Pos)
¥1PWM_CMPDAT1_CMP3_Pos (0)
¦1PWM_CMPDAT1_CMP3_Msk (0xfffful << PWM_CMPDAT1_CMP3_Pos)
¨1PWM_CMPDAT1_CMP4_Pos (0)
©1PWM_CMPDAT1_CMP4_Msk (0xfffful << PWM_CMPDAT1_CMP4_Pos)
«1PWM_CMPDAT1_CMP5_Pos (0)
¬1PWM_CMPDAT1_CMP5_Msk (0xfffful << PWM_CMPDAT1_CMP5_Pos)
®1PWM_CMPDAT1_CMP6_Pos (0)
¯1PWM_CMPDAT1_CMP6_Msk (0xfffful << PWM_CMPDAT1_CMP6_Pos)
±1PWM_CMPDAT1_CMP7_Pos (0)
²1PWM_CMPDAT1_CMP7_Msk (0xfffful << PWM_CMPDAT1_CMP7_Pos)
´1PWM_CMPDAT1_CMPD0_Pos (16)
µ1PWM_CMPDAT1_CMPD0_Msk (0xfffful << PWM_CMPDAT1_CMPD0_Pos)
·1PWM_CMPDAT1_CMPD1_Pos (16)
¸1PWM_CMPDAT1_CMPD1_Msk (0xfffful << PWM_CMPDAT1_CMPD1_Pos)
º1PWM_CMPDAT1_CMPD2_Pos (16)
»1PWM_CMPDAT1_CMPD2_Msk (0xfffful << PWM_CMPDAT1_CMPD2_Pos)
½1PWM_CMPDAT1_CMPD3_Pos (16)
¾1PWM_CMPDAT1_CMPD3_Msk (0xfffful << PWM_CMPDAT1_CMPD3_Pos)
À1PWM_CMPDAT1_CMPD4_Pos (16)
Á1PWM_CMPDAT1_CMPD4_Msk (0xfffful << PWM_CMPDAT1_CMPD4_Pos)
Ã1PWM_CMPDAT1_CMPD5_Pos (16)
Ä1PWM_CMPDAT1_CMPD5_Msk (0xfffful << PWM_CMPDAT1_CMPD5_Pos)
Æ1PWM_CMPDAT1_CMPD6_Pos (16)
Ç1PWM_CMPDAT1_CMPD6_Msk (0xfffful << PWM_CMPDAT1_CMPD6_Pos)
É1PWM_CMPDAT1_CMPD7_Pos (16)
Ê1PWM_CMPDAT1_CMPD7_Msk (0xfffful << PWM_CMPDAT1_CMPD7_Pos)
Ì1PWM_CMPDAT2_CMP0_Pos (0)
Í1PWM_CMPDAT2_CMP0_Msk (0xfffful << PWM_CMPDAT2_CMP0_Pos)
Ï1PWM_CMPDAT2_CMP1_Pos (0)
Ð1PWM_CMPDAT2_CMP1_Msk (0xfffful << PWM_CMPDAT2_CMP1_Pos)
Ò1PWM_CMPDAT2_CMP2_Pos (0)
Ó1PWM_CMPDAT2_CMP2_Msk (0xfffful << PWM_CMPDAT2_CMP2_Pos)
Õ1PWM_CMPDAT2_CMP3_Pos (0)
Ö1PWM_CMPDAT2_CMP3_Msk (0xfffful << PWM_CMPDAT2_CMP3_Pos)
Ø1PWM_CMPDAT2_CMP4_Pos (0)
Ù1PWM_CMPDAT2_CMP4_Msk (0xfffful << PWM_CMPDAT2_CMP4_Pos)
Û1PWM_CMPDAT2_CMP5_Pos (0)
Ü1PWM_CMPDAT2_CMP5_Msk (0xfffful << PWM_CMPDAT2_CMP5_Pos)
Þ1PWM_CMPDAT2_CMP6_Pos (0)
ß1PWM_CMPDAT2_CMP6_Msk (0xfffful << PWM_CMPDAT2_CMP6_Pos)
á1PWM_CMPDAT2_CMP7_Pos (0)
â1PWM_CMPDAT2_CMP7_Msk (0xfffful << PWM_CMPDAT2_CMP7_Pos)
ä1PWM_CMPDAT2_CMPD0_Pos (16)
å1PWM_CMPDAT2_CMPD0_Msk (0xfffful << PWM_CMPDAT2_CMPD0_Pos)
ç1PWM_CMPDAT2_CMPD1_Pos (16)
è1PWM_CMPDAT2_CMPD1_Msk (0xfffful << PWM_CMPDAT2_CMPD1_Pos)
ê1PWM_CMPDAT2_CMPD2_Pos (16)
ë1PWM_CMPDAT2_CMPD2_Msk (0xfffful << PWM_CMPDAT2_CMPD2_Pos)
í1PWM_CMPDAT2_CMPD3_Pos (16)
î1PWM_CMPDAT2_CMPD3_Msk (0xfffful << PWM_CMPDAT2_CMPD3_Pos)
ð1PWM_CMPDAT2_CMPD4_Pos (16)
ñ1PWM_CMPDAT2_CMPD4_Msk (0xfffful << PWM_CMPDAT2_CMPD4_Pos)
ó1PWM_CMPDAT2_CMPD5_Pos (16)
ô1PWM_CMPDAT2_CMPD5_Msk (0xfffful << PWM_CMPDAT2_CMPD5_Pos)
ö1PWM_CMPDAT2_CMPD6_Pos (16)
÷1PWM_CMPDAT2_CMPD6_Msk (0xfffful << PWM_CMPDAT2_CMPD6_Pos)
ù1PWM_CMPDAT2_CMPD7_Pos (16)
ú1PWM_CMPDAT2_CMPD7_Msk (0xfffful << PWM_CMPDAT2_CMPD7_Pos)
ü1PWM_CMPDAT3_CMP0_Pos (0)
ý1PWM_CMPDAT3_CMP0_Msk (0xfffful << PWM_CMPDAT3_CMP0_Pos)
ÿ1PWM_CMPDAT3_CMP1_Pos (0)
€2PWM_CMPDAT3_CMP1_Msk (0xfffful << PWM_CMPDAT3_CMP1_Pos)
‚2PWM_CMPDAT3_CMP2_Pos (0)
ƒ2PWM_CMPDAT3_CMP2_Msk (0xfffful << PWM_CMPDAT3_CMP2_Pos)
…2PWM_CMPDAT3_CMP3_Pos (0)
†2PWM_CMPDAT3_CMP3_Msk (0xfffful << PWM_CMPDAT3_CMP3_Pos)
ˆ2PWM_CMPDAT3_CMP4_Pos (0)
‰2PWM_CMPDAT3_CMP4_Msk (0xfffful << PWM_CMPDAT3_CMP4_Pos)
‹2PWM_CMPDAT3_CMP5_Pos (0)
Œ2PWM_CMPDAT3_CMP5_Msk (0xfffful << PWM_CMPDAT3_CMP5_Pos)
Ž2PWM_CMPDAT3_CMP6_Pos (0)
2PWM_CMPDAT3_CMP6_Msk (0xfffful << PWM_CMPDAT3_CMP6_Pos)
‘2PWM_CMPDAT3_CMP7_Pos (0)
’2PWM_CMPDAT3_CMP7_Msk (0xfffful << PWM_CMPDAT3_CMP7_Pos)
”2PWM_CMPDAT3_CMPD0_Pos (16)
•2PWM_CMPDAT3_CMPD0_Msk (0xfffful << PWM_CMPDAT3_CMPD0_Pos)
—2PWM_CMPDAT3_CMPD1_Pos (16)
˜2PWM_CMPDAT3_CMPD1_Msk (0xfffful << PWM_CMPDAT3_CMPD1_Pos)
š2PWM_CMPDAT3_CMPD2_Pos (16)
›2PWM_CMPDAT3_CMPD2_Msk (0xfffful << PWM_CMPDAT3_CMPD2_Pos)
2PWM_CMPDAT3_CMPD3_Pos (16)
ž2PWM_CMPDAT3_CMPD3_Msk (0xfffful << PWM_CMPDAT3_CMPD3_Pos)
 2PWM_CMPDAT3_CMPD4_Pos (16)
¡2PWM_CMPDAT3_CMPD4_Msk (0xfffful << PWM_CMPDAT3_CMPD4_Pos)
£2PWM_CMPDAT3_CMPD5_Pos (16)
¤2PWM_CMPDAT3_CMPD5_Msk (0xfffful << PWM_CMPDAT3_CMPD5_Pos)
¦2PWM_CMPDAT3_CMPD6_Pos (16)
§2PWM_CMPDAT3_CMPD6_Msk (0xfffful << PWM_CMPDAT3_CMPD4_Pos)
©2PWM_CMPDAT3_CMPD7_Pos (16)
ª2PWM_CMPDAT3_CMPD7_Msk (0xfffful << PWM_CMPDAT3_CMPD7_Pos)
¬2PWM_CMPDAT4_CMP0_Pos (0)
­2PWM_CMPDAT4_CMP0_Msk (0xfffful << PWM_CMPDAT4_CMP0_Pos)
¯2PWM_CMPDAT4_CMP1_Pos (0)
°2PWM_CMPDAT4_CMP1_Msk (0xfffful << PWM_CMPDAT4_CMP1_Pos)
²2PWM_CMPDAT4_CMP2_Pos (0)
³2PWM_CMPDAT4_CMP2_Msk (0xfffful << PWM_CMPDAT4_CMP2_Pos)
µ2PWM_CMPDAT4_CMP3_Pos (0)
¶2PWM_CMPDAT4_CMP3_Msk (0xfffful << PWM_CMPDAT4_CMP3_Pos)
¸2PWM_CMPDAT4_CMP4_Pos (0)
¹2PWM_CMPDAT4_CMP4_Msk (0xfffful << PWM_CMPDAT4_CMP4_Pos)
»2PWM_CMPDAT4_CMP5_Pos (0)
¼2PWM_CMPDAT4_CMP5_Msk (0xfffful << PWM_CMPDAT4_CMP5_Pos)
¾2PWM_CMPDAT4_CMP6_Pos (0)
¿2PWM_CMPDAT4_CMP6_Msk (0xfffful << PWM_CMPDAT4_CMP6_Pos)
Á2PWM_CMPDAT4_CMP7_Pos (0)
Â2PWM_CMPDAT4_CMP7_Msk (0xfffful << PWM_CMPDAT4_CMP7_Pos)
Ä2PWM_CMPDAT4_CMPD0_Pos (16)
Å2PWM_CMPDAT4_CMPD0_Msk (0xfffful << PWM_CMPDAT4_CMPD0_Pos)
Ç2PWM_CMPDAT4_CMPD1_Pos (16)
È2PWM_CMPDAT4_CMPD1_Msk (0xfffful << PWM_CMPDAT4_CMPD1_Pos)
Ê2PWM_CMPDAT4_CMPD2_Pos (16)
Ë2PWM_CMPDAT4_CMPD2_Msk (0xfffful << PWM_CMPDAT4_CMPD2_Pos)
Í2PWM_CMPDAT4_CMPD3_Pos (16)
Î2PWM_CMPDAT4_CMPD3_Msk (0xfffful << PWM_CMPDAT4_CMPD3_Pos)
Ð2PWM_CMPDAT4_CMPD4_Pos (16)
Ñ2PWM_CMPDAT4_CMPD4_Msk (0xfffful << PWM_CMPDAT4_CMPD4_Pos)
Ó2PWM_CMPDAT4_CMPD5_Pos (16)
Ô2PWM_CMPDAT4_CMPD5_Msk (0xfffful << PWM_CMPDAT4_CMPD5_Pos)
Ö2PWM_CMPDAT4_CMPD6_Pos (16)
×2PWM_CMPDAT4_CMPD6_Msk (0xfffful << PWM_CMPDAT4_CMPD6_Pos)
Ù2PWM_CMPDAT4_CMPD7_Pos (16)
Ú2PWM_CMPDAT4_CMPD7_Msk (0xfffful << PWM_CMPDAT4_CMPD7_Pos)
Ü2PWM_CMPDAT5_CMP0_Pos (0)
Ý2PWM_CMPDAT5_CMP0_Msk (0xfffful << PWM_CMPDAT5_CMP0_Pos)
ß2PWM_CMPDAT5_CMP1_Pos (0)
à2PWM_CMPDAT5_CMP1_Msk (0xfffful << PWM_CMPDAT5_CMP1_Pos)
â2PWM_CMPDAT5_CMP2_Pos (0)
ã2PWM_CMPDAT5_CMP2_Msk (0xfffful << PWM_CMPDAT5_CMP2_Pos)
å2PWM_CMPDAT5_CMP3_Pos (0)
æ2PWM_CMPDAT5_CMP3_Msk (0xfffful << PWM_CMPDAT5_CMP3_Pos)
è2PWM_CMPDAT5_CMP4_Pos (0)
é2PWM_CMPDAT5_CMP4_Msk (0xfffful << PWM_CMPDAT5_CMP4_Pos)
ë2PWM_CMPDAT5_CMP5_Pos (0)
ì2PWM_CMPDAT5_CMP5_Msk (0xfffful << PWM_CMPDAT5_CMP5_Pos)
î2PWM_CMPDAT5_CMP6_Pos (0)
ï2PWM_CMPDAT5_CMP6_Msk (0xfffful << PWM_CMPDAT5_CMP6_Pos)
ñ2PWM_CMPDAT5_CMP7_Pos (0)
ò2PWM_CMPDAT5_CMP7_Msk (0xfffful << PWM_CMPDAT5_CMP7_Pos)
ô2PWM_CMPDAT5_CMPD0_Pos (16)
õ2PWM_CMPDAT5_CMPD0_Msk (0xfffful << PWM_CMPDAT5_CMPD0_Pos)
÷2PWM_CMPDAT5_CMPD1_Pos (16)
ø2PWM_CMPDAT5_CMPD1_Msk (0xfffful << PWM_CMPDAT5_CMPD1_Pos)
ú2PWM_CMPDAT5_CMPD2_Pos (16)
û2PWM_CMPDAT5_CMPD2_Msk (0xfffful << PWM_CMPDAT5_CMPD2_Pos)
ý2PWM_CMPDAT5_CMPD3_Pos (16)
þ2PWM_CMPDAT5_CMPD3_Msk (0xfffful << PWM_CMPDAT5_CMPD3_Pos)
€3PWM_CMPDAT5_CMPD4_Pos (16)
3PWM_CMPDAT5_CMPD4_Msk (0xfffful << PWM_CMPDAT5_CMPD4_Pos)
ƒ3PWM_CMPDAT5_CMPD5_Pos (16)
„3PWM_CMPDAT5_CMPD5_Msk (0xfffful << PWM_CMPDAT5_CMPD5_Pos)
†3PWM_CMPDAT5_CMPD6_Pos (16)
‡3PWM_CMPDAT5_CMPD6_Msk (0xfffful << PWM_CMPDAT5_CMPD6_Pos)
‰3PWM_CMPDAT5_CMPD7_Pos (16)
Š3PWM_CMPDAT5_CMPD7_Msk (0xfffful << PWM_CMPDAT5_CMPD7_Pos)
Œ3PWM_CMPDAT6_CMP0_Pos (0)
3PWM_CMPDAT6_CMP0_Msk (0xfffful << PWM_CMPDAT6_CMP0_Pos)
3PWM_CMPDAT6_CMP1_Pos (0)
3PWM_CMPDAT6_CMP1_Msk (0xfffful << PWM_CMPDAT6_CMP1_Pos)
’3PWM_CMPDAT6_CMP2_Pos (0)
“3PWM_CMPDAT6_CMP2_Msk (0xfffful << PWM_CMPDAT6_CMP2_Pos)
•3PWM_CMPDAT6_CMP3_Pos (0)
–3PWM_CMPDAT6_CMP3_Msk (0xfffful << PWM_CMPDAT6_CMP3_Pos)
˜3PWM_CMPDAT6_CMP4_Pos (0)
™3PWM_CMPDAT6_CMP4_Msk (0xfffful << PWM_CMPDAT6_CMP4_Pos)
›3PWM_CMPDAT6_CMP5_Pos (0)
œ3PWM_CMPDAT6_CMP5_Msk (0xfffful << PWM_CMPDAT6_CMP5_Pos)
ž3PWM_CMPDAT6_CMP6_Pos (0)
Ÿ3PWM_CMPDAT6_CMP6_Msk (0xfffful << PWM_CMPDAT6_CMP6_Pos)
¡3PWM_CMPDAT6_CMP7_Pos (0)
¢3PWM_CMPDAT6_CMP7_Msk (0xfffful << PWM_CMPDAT6_CMP7_Pos)
¤3PWM_CMPDAT6_CMPD0_Pos (16)
¥3PWM_CMPDAT6_CMPD0_Msk (0xfffful << PWM_CMPDAT6_CMPD0_Pos)
§3PWM_CMPDAT6_CMPD1_Pos (16)
¨3PWM_CMPDAT6_CMPD1_Msk (0xfffful << PWM_CMPDAT6_CMPD1_Pos)
ª3PWM_CMPDAT6_CMPD2_Pos (16)
«3PWM_CMPDAT6_CMPD2_Msk (0xfffful << PWM_CMPDAT6_CMPD2_Pos)
­3PWM_CMPDAT6_CMPD3_Pos (16)
®3PWM_CMPDAT6_CMPD3_Msk (0xfffful << PWM_CMPDAT6_CMPD3_Pos)
°3PWM_CMPDAT6_CMPD4_Pos (16)
±3PWM_CMPDAT6_CMPD4_Msk (0xfffful << PWM_CMPDAT6_CMPD4_Pos)
³3PWM_CMPDAT6_CMPD5_Pos (16)
´3PWM_CMPDAT6_CMPD5_Msk (0xfffful << PWM_CMPDAT6_CMPD5_Pos)
¶3PWM_CMPDAT6_CMPD6_Pos (16)
·3PWM_CMPDAT6_CMPD6_Msk (0xfffful << PWM_CMPDAT6_CMPD6_Pos)
¹3PWM_CMPDAT6_CMPD7_Pos (16)
º3PWM_CMPDAT6_CMPD7_Msk (0xfffful << PWM_CMPDAT6_CMPD7_Pos)
¼3PWM_CMPDAT7_CMP0_Pos (0)
½3PWM_CMPDAT7_CMP0_Msk (0xfffful << PWM_CMPDAT7_CMP0_Pos)
¿3PWM_CMPDAT7_CMP1_Pos (0)
À3PWM_CMPDAT7_CMP1_Msk (0xfffful << PWM_CMPDAT7_CMP1_Pos)
Â3PWM_CMPDAT7_CMP2_Pos (0)
Ã3PWM_CMPDAT7_CMP2_Msk (0xfffful << PWM_CMPDAT7_CMP2_Pos)
Å3PWM_CMPDAT7_CMP3_Pos (0)
Æ3PWM_CMPDAT7_CMP3_Msk (0xfffful << PWM_CMPDAT7_CMP3_Pos)
È3PWM_CMPDAT7_CMP4_Pos (0)
É3PWM_CMPDAT7_CMP4_Msk (0xfffful << PWM_CMPDAT7_CMP4_Pos)
Ë3PWM_CMPDAT7_CMP5_Pos (0)
Ì3PWM_CMPDAT7_CMP5_Msk (0xfffful << PWM_CMPDAT7_CMP5_Pos)
Î3PWM_CMPDAT7_CMP6_Pos (0)
Ï3PWM_CMPDAT7_CMP6_Msk (0xfffful << PWM_CMPDAT7_CMP6_Pos)
Ñ3PWM_CMPDAT7_CMP7_Pos (0)
Ò3PWM_CMPDAT7_CMP7_Msk (0xfffful << PWM_CMPDAT7_CMP7_Pos)
Ô3PWM_CMPDAT7_CMPD0_Pos (16)
Õ3PWM_CMPDAT7_CMPD0_Msk (0xfffful << PWM_CMPDAT7_CMPD0_Pos)
×3PWM_CMPDAT7_CMPD1_Pos (16)
Ø3PWM_CMPDAT7_CMPD1_Msk (0xfffful << PWM_CMPDAT7_CMPD1_Pos)
Ú3PWM_CMPDAT7_CMPD2_Pos (16)
Û3PWM_CMPDAT7_CMPD2_Msk (0xfffful << PWM_CMPDAT7_CMPD2_Pos)
Ý3PWM_CMPDAT7_CMPD3_Pos (16)
Þ3PWM_CMPDAT7_CMPD3_Msk (0xfffful << PWM_CMPDAT7_CMPD3_Pos)
à3PWM_CMPDAT7_CMPD4_Pos (16)
á3PWM_CMPDAT7_CMPD4_Msk (0xfffful << PWM_CMPDAT7_CMPD4_Pos)
ã3PWM_CMPDAT7_CMPD5_Pos (16)
ä3PWM_CMPDAT7_CMPD5_Msk (0xfffful << PWM_CMPDAT7_CMPD5_Pos)
æ3PWM_CMPDAT7_CMPD6_Pos (16)
ç3PWM_CMPDAT7_CMPD6_Msk (0xfffful << PWM_CMPDAT7_CMPD6_Pos)
é3PWM_CMPDAT7_CMPD7_Pos (16)
ê3PWM_CMPDAT7_CMPD7_Msk (0xfffful << PWM_CMPDAT7_CMPD7_Pos)
ì3PWM_CTL2_BRKIEN_Pos (16)
í3PWM_CTL2_BRKIEN_Msk (0x1ul << PWM_CTL2_BRKIEN_Pos)
ï3PWM_CTL2_PINTTYPE_Pos (17)
ð3PWM_CTL2_PINTTYPE_Msk (0x1ul << PWM_CTL2_PINTTYPE_Pos)
ò3PWM_CTL2_DTCNT01_Pos (24)
ó3PWM_CTL2_DTCNT01_Msk (0x1ul << PWM_CTL2_DTCNT01_Pos)
õ3PWM_CTL2_DTCNT23_Pos (25)
ö3PWM_CTL2_DTCNT23_Msk (0x1ul << PWM_CTL2_DTCNT23_Pos)
ø3PWM_CTL2_DTCNT45_Pos (26)
ù3PWM_CTL2_DTCNT45_Msk (0x1ul << PWM_CTL2_DTCNT45_Pos)
û3PWM_CTL2_DTCNT67_Pos (27)
ü3PWM_CTL2_DTCNT67_Msk (0x1ul << PWM_CTL2_DTCNT67_Pos)
þ3PWM_CTL2_CNTCLR_Pos (27)
ÿ3PWM_CTL2_CNTCLR_Msk (0x1ul << PWM_CTL2_CNTCLR_Pos)
4PWM_CTL2_MODE_Pos (28)
‚4PWM_CTL2_MODE_Msk (0x3ul << PWM_CTL2_MODE_Pos)
„4PWM_CTL2_GROUPEN_Pos (30)
…4PWM_CTL2_GROUPEN_Msk (0x1ul << PWM_CTL2_GROUPEN_Pos)
‡4PWM_CTL2_CNTTYPE_Pos (31)
ˆ4PWM_CTL2_CNTTYPE_Msk (0x1ul << PWM_CTL2_CNTTYPE_Pos)
Š4PWM_FLAG_ZF0_Pos (0)
‹4PWM_FLAG_ZF0_Msk (0x1ul << PWM_FLAG_ZF0_Pos)
4PWM_FLAG_ZF1_Pos (1)
Ž4PWM_FLAG_ZF1_Msk (0x1ul << PWM_FLAG_ZF1_Pos)
4PWM_FLAG_ZF2_Pos (2)
‘4PWM_FLAG_ZF2_Msk (0x1ul << PWM_FLAG_ZF2_Pos)
“4PWM_FLAG_ZF3_Pos (3)
”4PWM_FLAG_ZF3_Msk (0x1ul << PWM_FLAG_ZF3_Pos)
–4PWM_FLAG_ZF4_Pos (4)
—4PWM_FLAG_ZF4_Msk (0x1ul << PWM_FLAG_ZF4_Pos)
™4PWM_FLAG_ZF5_Pos (5)
š4PWM_FLAG_ZF5_Msk (0x1ul << PWM_FLAG_ZF5_Pos)
œ4PWM_FLAG_ZF6_Pos (6)
4PWM_FLAG_ZF6_Msk (0x1ul << PWM_FLAG_ZF6_Pos)
Ÿ4PWM_FLAG_ZF7_Pos (7)
 4PWM_FLAG_ZF7_Msk (0x1ul << PWM_FLAG_ZF7_Pos)
¢4PWM_FLAG_CMPDF0_Pos (8)
£4PWM_FLAG_CMPDF0_Msk (0x1ul << PWM_FLAG_CMPDF0_Pos)
¥4PWM_FLAG_CMPDF1_Pos (9)
¦4PWM_FLAG_CMPDF1_Msk (0x1ul << PWM_FLAG_CMPDF1_Pos)
¨4PWM_FLAG_CMPDF2_Pos (10)
©4PWM_FLAG_CMPDF2_Msk (0x1ul << PWM_FLAG_CMPDF2_Pos)
«4PWM_FLAG_CMPDF3_Pos (11)
¬4PWM_FLAG_CMPDF3_Msk (0x1ul << PWM_FLAG_CMPDF3_Pos)
®4PWM_FLAG_CMPDF4_Pos (12)
¯4PWM_FLAG_CMPDF4_Msk (0x1ul << PWM_FLAG_CMPDF4_Pos)
±4PWM_FLAG_CMPDF5_Pos (13)
²4PWM_FLAG_CMPDF5_Msk (0x1ul << PWM_FLAG_CMPDF5_Pos)
´4PWM_FLAG_CMPDF6_Pos (14)
µ4PWM_FLAG_CMPDF6_Msk (0x1ul << PWM_FLAG_CMPDF6_Pos)
·4PWM_FLAG_CMPDF7_Pos (15)
¸4PWM_FLAG_CMPDF7_Msk (0x1ul << PWM_FLAG_CMPDF7_Pos)
º4PWM_FLAG_PF0_Pos (16)
»4PWM_FLAG_PF0_Msk (0x1ul << PWM_FLAG_PF0_Pos)
½4PWM_FLAG_PF1_Pos (17)
¾4PWM_FLAG_PF1_Msk (0x1ul << PWM_FLAG_PF1_Pos)
À4PWM_FLAG_PF2_Pos (18)
Á4PWM_FLAG_PF2_Msk (0x1ul << PWM_FLAG_PF2_Pos)
Ã4PWM_FLAG_PF3_Pos (19)
Ä4PWM_FLAG_PF3_Msk (0x1ul << PWM_FLAG_PF3_Pos)
Æ4PWM_FLAG_PF4_Pos (20)
Ç4PWM_FLAG_PF4_Msk (0x1ul << PWM_FLAG_PF4_Pos)
É4PWM_FLAG_PF5_Pos (21)
Ê4PWM_FLAG_PF5_Msk (0x1ul << PWM_FLAG_PF5_Pos)
Ì4PWM_FLAG_PF6_Pos (22)
Í4PWM_FLAG_PF6_Msk (0x1ul << PWM_FLAG_PF6_Pos)
Ï4PWM_FLAG_PF7_Pos (23)
Ð4PWM_FLAG_PF7_Msk (0x1ul << PWM_FLAG_PF7_Pos)
Ò4PWM_FLAG_CMPUF0_Pos (24)
Ó4PWM_FLAG_CMPUF0_Msk (0x1ul << PWM_FLAG_CMPUF0_Pos)
Õ4PWM_FLAG_CMPUF1_Pos (25)
Ö4PWM_FLAG_CMPUF1_Msk (0x1ul << PWM_FLAG_CMPUF1_Pos)
Ø4PWM_FLAG_CMPUF2_Pos (26)
Ù4PWM_FLAG_CMPUF2_Msk (0x1ul << PWM_FLAG_CMPUF2_Pos)
Û4PWM_FLAG_CMPUF3_Pos (27)
Ü4PWM_FLAG_CMPUF3_Msk (0x1ul << PWM_FLAG_CMPUF3_Pos)
Þ4PWM_FLAG_CMPUF4_Pos (28)
ß4PWM_FLAG_CMPUF4_Msk (0x1ul << PWM_FLAG_CMPUF4_Pos)
á4PWM_FLAG_CMPUF5_Pos (29)
â4PWM_FLAG_CMPUF5_Msk (0x1ul << PWM_FLAG_CMPUF5_Pos)
ä4PWM_FLAG_CMPUF6_Pos (30)
å4PWM_FLAG_CMPUF6_Msk (0x1ul << PWM_FLAG_CMPUF6_Pos)
ç4PWM_FLAG_CMPUF7_Pos (31)
è4PWM_FLAG_CMPUF7_Msk (0x1ul << PWM_FLAG_CMPUF7_Pos)
ê4PWM_INTEN_ZIEN0_Pos (0)
ë4PWM_INTEN_ZIEN0_Msk (0x1ul << PWM_INTEN_ZIEN0_Pos)
í4PWM_INTEN_ZIEN1_Pos (1)
î4PWM_INTEN_ZIEN1_Msk (0x1ul << PWM_INTEN_ZIEN1_Pos)
ð4PWM_INTEN_ZIEN2_Pos (2)
ñ4PWM_INTEN_ZIEN2_Msk (0x1ul << PWM_INTEN_ZIEN2_Pos)
ó4PWM_INTEN_ZIEN3_Pos (3)
ô4PWM_INTEN_ZIEN3_Msk (0x1ul << PWM_INTEN_ZIEN3_Pos)
ö4PWM_INTEN_ZIEN4_Pos (4)
÷4PWM_INTEN_ZIEN4_Msk (0x1ul << PWM_INTEN_ZIEN4_Pos)
ù4PWM_INTEN_ZIEN5_Pos (5)
ú4PWM_INTEN_ZIEN5_Msk (0x1ul << PWM_INTEN_ZIEN5_Pos)
ý4PWM_INTEN_ZIEN6_Pos (6)
þ4PWM_INTEN_ZIEN6_Msk (0x1ul << PWM_INTEN_ZIEN6_Pos)
5PWM_INTEN_ZIEN7_Pos (7)
‚5PWM_INTEN_ZIEN7_Msk (0x1ul << PWM_INTEN_ZIEN7_Pos)
„5PWM_INTEN_CMPDIEN0_Pos (8)
…5PWM_INTEN_CMPDIEN0_Msk (0x1ul << PWM_INTEN_CMPDIEN0_Pos)
‡5PWM_INTEN_CMPDIEN1_Pos (9)
ˆ5PWM_INTEN_CMPDIEN1_Msk (0x1ul << PWM_INTEN_CMPDIEN1_Pos)
Š5PWM_INTEN_CMPDIEN2_Pos (10)
‹5PWM_INTEN_CMPDIEN2_Msk (0x1ul << PWM_INTEN_CMPDIEN2_Pos)
5PWM_INTEN_CMPDIEN3_Pos (11)
Ž5PWM_INTEN_CMPDIEN3_Msk (0x1ul << PWM_INTEN_CMPDIEN3_Pos)
5PWM_INTEN_CMPDIEN4_Pos (12)
‘5PWM_INTEN_CMPDIEN4_Msk (0x1ul << PWM_INTEN_CMPDIEN4_Pos)
“5PWM_INTEN_CMPDIEN5_Pos (13)
”5PWM_INTEN_CMPDIEN5_Msk (0x1ul << PWM_INTEN_CMPDIEN5_Pos)
—5PWM_INTEN_CMPDIEN6_Pos (14)
˜5PWM_INTEN_CMPDIEN6_Msk (0x1ul << PWM_INTEN_CMPDIEN6_Pos)
š5PWM_INTEN_CMPDIEN7_Pos (15)
›5PWM_INTEN_CMPDIEN7_Msk (0x1ul << PWM_INTEN_CMPDIEN7_Pos)
5PWM_INTEN_PIEN0_Pos (16)
ž5PWM_INTEN_PIEN0_Msk (0x1ul << PWM_INTEN_PIEN0_Pos)
 5PWM_INTEN_PIEN1_Pos (17)
¡5PWM_INTEN_PIEN1_Msk (0x1ul << PWM_INTEN_PIEN1_Pos)
£5PWM_INTEN_PIEN2_Pos (18)
¤5PWM_INTEN_PIEN2_Msk (0x1ul << PWM_INTEN_PIEN2_Pos)
¦5PWM_INTEN_PIEN3_Pos (19)
§5PWM_INTEN_PIEN3_Msk (0x1ul << PWM_INTEN_PIEN3_Pos)
©5PWM_INTEN_PIEN4_Pos (20)
ª5PWM_INTEN_PIEN4_Msk (0x1ul << PWM_INTEN_PIEN4_Pos)
¬5PWM_INTEN_PIEN5_Pos (21)
­5PWM_INTEN_PIEN5_Msk (0x1ul << PWM_INTEN_PIEN5_Pos)
°5PWM_INTEN_PIEN6_Pos (22)
±5PWM_INTEN_PIEN6_Msk (0x1ul << PWM_INTEN_PIEN6_Pos)
´5PWM_INTEN_PIEN7_Pos (23)
µ5PWM_INTEN_PIEN7_Msk (0x1ul << PWM_INTEN_PIEN7_Pos)
·5PWM_INTEN_CMPUIEN0_Pos (24)
¸5PWM_INTEN_CMPUIEN0_Msk (0x1ul << PWM_INTEN_CMPUIEN0_Pos)
º5PWM_INTEN_CMPUIEN1_Pos (25)
»5PWM_INTEN_CMPUIEN1_Msk (0x1ul << PWM_INTEN_CMPUIEN1_Pos)
½5PWM_INTEN_CMPUIEN2_Pos (26)
¾5PWM_INTEN_CMPUIEN2_Msk (0x1ul << PWM_INTEN_CMPUIEN2_Pos)
À5PWM_INTEN_CMPUIEN3_Pos (27)
Á5PWM_INTEN_CMPUIEN3_Msk (0x1ul << PWM_INTEN_CMPUIEN3_Pos)
Ã5PWM_INTEN_CMPUIEN4_Pos (28)
Ä5PWM_INTEN_CMPUIEN4_Msk (0x1ul << PWM_INTEN_CMPUIEN4_Pos)
Æ5PWM_INTEN_CMPUIEN5_Pos (29)
Ç5PWM_INTEN_CMPUIEN5_Msk (0x1ul << PWM_INTEN_CMPUIEN5_Pos)
É5PWM_INTEN_CMPUIEN6_Pos (30)
Ê5PWM_INTEN_CMPUIEN6_Msk (0x1ul << PWM_INTEN_CMPUIEN6_Pos)
Ì5PWM_INTEN_CMPUIEN7_Pos (31)
Í5PWM_INTEN_CMPUIEN7_Msk (0x1ul << PWM_INTEN_CMPUIEN7_Pos)
Ï5PWM_INTSTS_ZIF0_Pos (0)
Ð5PWM_INTSTS_ZIF0_Msk (0x1ul << PWM_INTSTS_ZIF0_Pos)
Ò5PWM_INTSTS_ZIF1_Pos (1)
Ó5PWM_INTSTS_ZIF1_Msk (0x1ul << PWM_INTSTS_ZIF1_Pos)
Õ5PWM_INTSTS_ZIF2_Pos (2)
Ö5PWM_INTSTS_ZIF2_Msk (0x1ul << PWM_INTSTS_ZIF2_Pos)
Ø5PWM_INTSTS_ZIF3_Pos (3)
Ù5PWM_INTSTS_ZIF3_Msk (0x1ul << PWM_INTSTS_ZIF3_Pos)
Û5PWM_INTSTS_ZIF4_Pos (4)
Ü5PWM_INTSTS_ZIF4_Msk (0x1ul << PWM_INTSTS_ZIF4_Pos)
Þ5PWM_INTSTS_ZIF5_Pos (5)
ß5PWM_INTSTS_ZIF5_Msk (0x1ul << PWM_INTSTS_ZIF5_Pos)
á5PWM_INTSTS_ZIF6_Pos (6)
â5PWM_INTSTS_ZIF6_Msk (0x1ul << PWM_INTSTS_ZIF6_Pos)
ä5PWM_INTSTS_ZIF7_Pos (7)
å5PWM_INTSTS_ZIF7_Msk (0x1ul << PWM_INTSTS_ZIF7_Pos)
ç5PWM_INTSTS_CMPDIF0_Pos (8)
è5PWM_INTSTS_CMPDIF0_Msk (0x1ul << PWM_INTSTS_CMPDIF0_Pos)
ê5PWM_INTSTS_CMPDIF1_Pos (9)
ë5PWM_INTSTS_CMPDIF1_Msk (0x1ul << PWM_INTSTS_CMPDIF1_Pos)
í5PWM_INTSTS_CMPDIF2_Pos (10)
î5PWM_INTSTS_CMPDIF2_Msk (0x1ul << PWM_INTSTS_CMPDIF2_Pos)
ð5PWM_INTSTS_CMPDIF3_Pos (11)
ñ5PWM_INTSTS_CMPDIF3_Msk (0x1ul << PWM_INTSTS_CMPDIF3_Pos)
ó5PWM_INTSTS_CMPDIF4_Pos (12)
ô5PWM_INTSTS_CMPDIF4_Msk (0x1ul << PWM_INTSTS_CMPDIF4_Pos)
ö5PWM_INTSTS_CMPDIF5_Pos (13)
÷5PWM_INTSTS_CMPDIF5_Msk (0x1ul << PWM_INTSTS_CMPDIF5_Pos)
ù5PWM_INTSTS_CMPDIF6_Pos (14)
ú5PWM_INTSTS_CMPDIF6_Msk (0x1ul << PWM_INTSTS_CMPDIF6_Pos)
ü5PWM_INTSTS_CMPDIF7_Pos (15)
ý5PWM_INTSTS_CMPDIF7_Msk (0x1ul << PWM_INTSTS_CMPDIF7_Pos)
ÿ5PWM_INTSTS_PIF0_Pos (16)
€6PWM_INTSTS_PIF0_Msk (0x1ul << PWM_INTSTS_PIF0_Pos)
‚6PWM_INTSTS_PIF1_Pos (17)
ƒ6PWM_INTSTS_PIF1_Msk (0x1ul << PWM_INTSTS_PIF1_Pos)
…6PWM_INTSTS_PIF2_Pos (18)
†6PWM_INTSTS_PIF2_Msk (0x1ul << PWM_INTSTS_PIF2_Pos)
ˆ6PWM_INTSTS_PIF3_Pos (19)
‰6PWM_INTSTS_PIF3_Msk (0x1ul << PWM_INTSTS_PIF3_Pos)
‹6PWM_INTSTS_PIF4_Pos (20)
Œ6PWM_INTSTS_PIF4_Msk (0x1ul << PWM_INTSTS_PIF4_Pos)
Ž6PWM_INTSTS_PIF5_Pos (21)
6PWM_INTSTS_PIF5_Msk (0x1ul << PWM_INTSTS_PIF5_Pos)
‘6PWM_INTSTS_PIF6_Pos (22)
’6PWM_INTSTS_PIF6_Msk (0x1ul << PWM_INTSTS_PIF6_Pos)
”6PWM_INTSTS_PIF7_Pos (23)
•6PWM_INTSTS_PIF7_Msk (0x1ul << PWM_INTSTS_PIF7_Pos)
—6PWM_INTSTS_CMPUIF0_Pos (24)
˜6PWM_INTSTS_CMPUIF0_Msk (0x1ul << PWM_INTSTS_CMPUIF0_Pos)
š6PWM_INTSTS_CMPUIF1_Pos (25)
›6PWM_INTSTS_CMPUIF1_Msk (0x1ul << PWM_INTSTS_CMPUIF1_Pos)
6PWM_INTSTS_CMPUIF2_Pos (26)
ž6PWM_INTSTS_CMPUIF2_Msk (0x1ul << PWM_INTSTS_CMPUIF2_Pos)
 6PWM_INTSTS_CMPUIF3_Pos (27)
¡6PWM_INTSTS_CMPUIF3_Msk (0x1ul << PWM_INTSTS_CMPUIF3_Pos)
£6PWM_INTSTS_CMPUIF4_Pos (28)
¤6PWM_INTSTS_CMPUIF4_Msk (0x1ul << PWM_INTSTS_CMPUIF4_Pos)
¦6PWM_INTSTS_CMPUIF5_Pos (29)
§6PWM_INTSTS_CMPUIF5_Msk (0x1ul << PWM_INTSTS_CMPUIF5_Pos)
©6PWM_INTSTS_CMPUIF6_Pos (30)
ª6PWM_INTSTS_CMPUIF6_Msk (0x1ul << PWM_INTSTS_CMPUIF6_Pos)
¬6PWM_INTSTS_CMPUIF7_Pos (31)
­6PWM_INTSTS_CMPUIF7_Msk (0x1ul << PWM_INTSTS_CMPUIF7_Pos)
¯6PWM_POEN_POEN0_Pos (0)
°6PWM_POEN_POEN0_Msk (0x1ul << PWM_POEN_POEN0_Pos)
²6PWM_POEN_POEN1_Pos (1)
³6PWM_POEN_POEN1_Msk (0x1ul << PWM_POEN_POEN1_Pos)
µ6PWM_POEN_POEN2_Pos (2)
¶6PWM_POEN_POEN2_Msk (0x1ul << PWM_POEN_POEN2_Pos)
¸6PWM_POEN_POEN3_Pos (3)
¹6PWM_POEN_POEN3_Msk (0x1ul << PWM_POEN_POEN3_Pos)
»6PWM_POEN_POEN4_Pos (4)
¼6PWM_POEN_POEN4_Msk (0x1ul << PWM_POEN_POEN4_Pos)
¾6PWM_POEN_POEN5_Pos (5)
¿6PWM_POEN_POEN5_Msk (0x1ul << PWM_POEN_POEN5_Pos)
Á6PWM_POEN_POEN6_Pos (6)
Â6PWM_POEN_POEN6_Msk (0x1ul << PWM_POEN_POEN4_Pos)
Ä6PWM_POEN_POEN7_Pos (7)
Å6PWM_POEN_POEN7_Msk (0x1ul << PWM_POEN_POEN7_Pos)
Ç6PWM_BRKCTL_BRK0EN_Pos (0)
È6PWM_BRKCTL_BRK0EN_Msk (0x1ul << PWM_BRKCTL_BRK0EN_Pos)
Ê6PWM_BRKCTL_BRK1EN_Pos (1)
Ë6PWM_BRKCTL_BRK1EN_Msk (0x1ul << PWM_BRKCTL_BRK1EN_Pos)
Í6PWM_BRKCTL_BRK0SEL_Pos (2)
Î6PWM_BRKCTL_BRK0SEL_Msk (0x1ul << PWM_BRKCTL_BRK0SEL_Pos)
Ð6PWM_BRKCTL_BRK1SEL_Pos (3)
Ñ6PWM_BRKCTL_BRK1SEL_Msk (0x1ul << PWM_BRKCTL_BRK1SEL_Pos)
Ó6PWM_BRKCTL_BRKSTS_Pos (7)
Ô6PWM_BRKCTL_BRKSTS_Msk (0x1ul << PWM_BRKCTL_BRKSTS_Pos)
Ö6PWM_BRKCTL_BRKACT_Pos (8)
×6PWM_BRKCTL_BRKACT_Msk (0x1ul << PWM_BRKCTL_BRKACT_Pos)
Ù6PWM_BRKCTL_SWBRK_Pos (9)
Ú6PWM_BRKCTL_SWBRK_Msk (0x1ul << PWM_BRKCTL_SWBRK_Pos)
Ü6PWM_BRKCTL_BRKIF0_Pos (16)
Ý6PWM_BRKCTL_BRKIF0_Msk (0x1ul << PWM_BRKCTL_BRKIF0_Pos)
ß6PWM_BRKCTL_BRKIF1_Pos (17)
à6PWM_BRKCTL_BRKIF1_Msk (0x1ul << PWM_BRKCTL_BRKIF1_Pos)
â6PWM_BRKCTL_BRKF0_Pos (18)
ã6PWM_BRKCTL_BRKF0_Msk (0x1ul << PWM_BRKCTL_BRKF0_Pos)
å6PWM_BRKCTL_BRKF1_Pos (19)
æ6PWM_BRKCTL_BRKF1_Msk (0x1ul << PWM_BRKCTL_BRKF1_Pos)
è6PWM_BRKCTL_BKOD0_Pos (24)
é6PWM_BRKCTL_BKOD0_Msk (0x1ul << PWM_BRKCTL_BKOD0_Pos)
ë6PWM_BRKCTL_BKOD1_Pos (25)
ì6PWM_BRKCTL_BKOD1_Msk (0x1ul << PWM_BRKCTL_BKOD1_Pos)
î6PWM_BRKCTL_BKOD2_Pos (26)
ï6PWM_BRKCTL_BKOD2_Msk (0x1ul << PWM_BRKCTL_BKOD2_Pos)
ñ6PWM_BRKCTL_BKOD3_Pos (27)
ò6PWM_BRKCTL_BKOD3_Msk (0x1ul << PWM_BRKCTL_BKOD3_Pos)
ô6PWM_BRKCTL_BKOD4_Pos (28)
õ6PWM_BRKCTL_BKOD4_Msk (0x1ul << PWM_BRKCTL_BKOD4_Pos)
÷6PWM_BRKCTL_BKOD5_Pos (29)
ø6PWM_BRKCTL_BKOD5_Msk (0x1ul << PWM_BRKCTL_BKOD5_Pos)
ú6PWM_BRKCTL_D6BKOD_Pos (30)
û6PWM_BRKCTL_D6BKOD_Msk (0x1ul << PWM_BRKCTL_D6BKOD_Pos)
ý6PWM_BRKCTL_D7BKOD_Pos (31)
þ6PWM_BRKCTL_D7BKOD_Msk (0x1ul << PWM_BRKCTL_D7BKOD_Pos)
€7PWM_DTCTL_DTI01_Pos (0)
7PWM_DTCTL_DTI01_Msk (0xfful << PWM_DTCTL_DTI01_Pos)
ƒ7PWM_DTCTL_DTI23_Pos (8)
„7PWM_DTCTL_DTI23_Msk (0xfful << PWM_DTCTL_DTI23_Pos)
†7PWM_DTCTL_DTI45_Pos (16)
‡7PWM_DTCTL_DTI45_Msk (0xfful << PWM_DTCTL_DTI45_Pos)
‰7PWM_DTCTL_DTI67_Pos (24)
Š7PWM_DTCTL_DTI67_Msk (0xfful << PWM_DTCTL_DTI67_Pos)
Œ7PWM_ADCTCTL0_CUTRGEN0_Pos (0)
7PWM_ADCTCTL0_CUTRGEN0_Msk (0x1ul << PWM_ADCTCTL0_CUTRGEN0_Pos)
7PWM_ADCTCTL0_CPTRGEN0_Pos (1)
7PWM_ADCTCTL0_CPTRGEN0_Msk (0x1ul << PWM_ADCTCTL0_CPTRGEN0_Pos)
’7PWM_ADCTCTL0_CDTRGEN0_Pos (2)
“7PWM_ADCTCTL0_CDTRGEN0_Msk (0x1ul << PWM_ADCTCTL0_CDTRGEN0_Pos)
•7PWM_ADCTCTL0_ZPTRGEN0_Pos (3)
–7PWM_ADCTCTL0_ZPTRGEN0_Msk (0x1ul << PWM_ADCTCTL0_ZPTRGEN0_Pos)
˜7PWM_ADCTCTL0_CUTRGEN1_Pos (8)
™7PWM_ADCTCTL0_CUTRGEN1_Msk (0x1ul << PWM_ADCTCTL0_CUTRGEN1_Pos)
›7PWM_ADCTCTL0_CPTRGEN1_Pos (9)
œ7PWM_ADCTCTL0_CPTRGEN1_Msk (0x1ul << PWM_ADCTCTL0_CPTRGEN1_Pos)
ž7PWM_ADCTCTL0_CDTRGEN1_Pos (10)
Ÿ7PWM_ADCTCTL0_CDTRGEN1_Msk (0x1ul << PWM_ADCTCTL0_CDTRGEN1_Pos)
¡7PWM_ADCTCTL0_ZPTRGEN1_Pos (11)
¢7PWM_ADCTCTL0_ZPTRGEN1_Msk (0x1ul << PWM_ADCTCTL0_ZPTRGEN1_Pos)
¤7PWM_ADCTCTL0_CUTRGEN2_Pos (16)
¥7PWM_ADCTCTL0_CUTRGEN2_Msk (0x1ul << PWM_ADCTCTL0_CUTRGEN2_Pos)
§7PWM_ADCTCTL0_CPTRGEN2_Pos (17)
¨7PWM_ADCTCTL0_CPTRGEN2_Msk (0x1ul << PWM_ADCTCTL0_CPTRGEN2_Pos)
ª7PWM_ADCTCTL0_CDTRGEN2_Pos (18)
«7PWM_ADCTCTL0_CDTRGEN2_Msk (0x1ul << PWM_ADCTCTL0_CDTRGEN2_Pos)
­7PWM_ADCTCTL0_ZPTRGEN2_Pos (19)
®7PWM_ADCTCTL0_ZPTRGEN2_Msk (0x1ul << PWM_ADCTCTL0_ZPTRGEN2_Pos)
°7PWM_ADCTCTL0_CUTRGEN3_Pos (24)
±7PWM_ADCTCTL0_CUTRGEN3_Msk (0x1ul << PWM_ADCTCTL0_CUTRGEN3_Pos)
³7PWM_ADCTCTL0_CPTRGEN3_Pos (25)
´7PWM_ADCTCTL0_CPTRGEN3_Msk (0x1ul << PWM_ADCTCTL0_CPTRGEN3_Pos)
¶7PWM_ADCTCTL0_CDTRGEN3_Pos (26)
·7PWM_ADCTCTL0_CDTRGEN3_Msk (0x1ul << PWM_ADCTCTL0_CDTRGEN3_Pos)
¹7PWM_ADCTCTL0_ZPTRGEN3_Pos (27)
º7PWM_ADCTCTL0_ZPTRGEN3_Msk (0x1ul << PWM_ADCTCTL0_ZPTRGEN3_Pos)
¼7PWM_ADCTCTL1_CUTRGEN4_Pos (0)
½7PWM_ADCTCTL1_CUTRGEN4_Msk (0x1ul << PWM_ADCTCTL1_CUTRGEN4_Pos)
¿7PWM_ADCTCTL1_CPTRGEN4_Pos (1)
À7PWM_ADCTCTL1_CPTRGEN4_Msk (0x1ul << PWM_ADCTCTL1_CPTRGEN4_Pos)
Â7PWM_ADCTCTL1_CDTRGEN4_Pos (2)
Ã7PWM_ADCTCTL1_CDTRGEN4_Msk (0x1ul << PWM_ADCTCTL1_CDTRGEN4_Pos)
Å7PWM_ADCTCTL1_ZPTRGEN4_Pos (3)
Æ7PWM_ADCTCTL1_ZPTRGEN4_Msk (0x1ul << PWM_ADCTCTL1_ZPTRGEN4_Pos)
È7PWM_ADCTCTL1_CUTRGEN5_Pos (8)
É7PWM_ADCTCTL1_CUTRGEN5_Msk (0x1ul << PWM_ADCTCTL1_CUTRGEN5_Pos)
Ë7PWM_ADCTCTL1_CPTRGEN5_Pos (9)
Ì7PWM_ADCTCTL1_CPTRGEN5_Msk (0x1ul << PWM_ADCTCTL1_CPTRGEN5_Pos)
Î7PWM_ADCTCTL1_CDTRGEN5_Pos (10)
Ï7PWM_ADCTCTL1_CDTRGEN5_Msk (0x1ul << PWM_ADCTCTL1_CDTRGEN5_Pos)
Ñ7PWM_ADCTCTL1_ZPTRGEN5_Pos (11)
Ò7PWM_ADCTCTL1_ZPTRGEN5_Msk (0x1ul << PWM_ADCTCTL1_ZPTRGEN5_Pos)
Ô7PWM_ADCTCTL1_CUTRGEN6_Pos (16)
Õ7PWM_ADCTCTL1_CUTRGEN6_Msk (0x1ul << PWM_ADCTCTL1_CUTRGEN2_Pos)
×7PWM_ADCTCTL1_CPTRGEN6_Pos (17)
Ø7PWM_ADCTCTL1_CPTRGEN6_Msk (0x1ul << PWM_ADCTCTL1_CPTRGEN2_Pos)
Ú7PWM_ADCTCTL1_CDTRGEN6_Pos (18)
Û7PWM_ADCTCTL1_CDTRGEN6_Msk (0x1ul << PWM_ADCTCTL1_CDTRGEN2_Pos)
Ý7PWM_ADCTCTL1_ZPTRGEN6_Pos (19)
Þ7PWM_ADCTCTL1_ZPTRGEN6_Msk (0x1ul << PWM_ADCTCTL1_ZPTRGEN2_Pos)
à7PWM_ADCTCTL1_CUTRGEN7_Pos (24)
á7PWM_ADCTCTL1_CUTRGEN7_Msk (0x1ul << PWM_ADCTCTL1_CUTRGEN7_Pos)
ã7PWM_ADCTCTL1_CPTRGEN7_Pos (25)
ä7PWM_ADCTCTL1_CPTRGEN7_Msk (0x1ul << PWM_ADCTCTL1_CPTRGEN7_Pos)
æ7PWM_ADCTCTL1_CDTRGEN7_Pos (26)
ç7PWM_ADCTCTL1_CDTRGEN7_Msk (0x1ul << PWM_ADCTCTL1_CDTRGEN7_Pos)
é7PWM_ADCTCTL1_ZPTRGEN7_Pos (27)
ê7PWM_ADCTCTL1_ZPTRGEN7_Msk (0x1ul << PWM_ADCTCTL1_ZPTRGEN7_Pos)
ì7PWM_ADCTSTS0_CUTRGF0_Pos (0)
í7PWM_ADCTSTS0_CUTRGF0_Msk (0x1ul << PWM_ADCTSTS0_CUTRGF0_Pos)
ï7PWM_ADCTSTS0_CPTRGF0_Pos (1)
ð7PWM_ADCTSTS0_CPTRGF0_Msk (0x1ul << PWM_ADCTSTS0_CPTRGF0_Pos)
ò7PWM_ADCTSTS0_CDTRGF0_Pos (2)
ó7PWM_ADCTSTS0_CDTRGF0_Msk (0x1ul << PWM_ADCTSTS0_CDTRGF0_Pos)
õ7PWM_ADCTSTS0_ZPTRGF0_Pos (3)
ö7PWM_ADCTSTS0_ZPTRGF0_Msk (0x1ul << PWM_ADCTSTS0_ZPTRGF0_Pos)
ø7PWM_ADCTSTS0_CUTRGF1_Pos (8)
ù7PWM_ADCTSTS0_CUTRGF1_Msk (0x1ul << PWM_ADCTSTS0_CUTRGF1_Pos)
û7PWM_ADCTSTS0_CPTRGF1_Pos (9)
ü7PWM_ADCTSTS0_CPTRGF1_Msk (0x1ul << PWM_ADCTSTS0_CPTRGF1_Pos)
þ7PWM_ADCTSTS0_CDTRGF1_Pos (10)
ÿ7PWM_ADCTSTS0_CDTRGF1_Msk (0x1ul << PWM_ADCTSTS0_CDTRGF1_Pos)
8PWM_ADCTSTS0_ZPTRGF1_Pos (11)
‚8PWM_ADCTSTS0_ZPTRGF1_Msk (0x1ul << PWM_ADCTSTS0_ZPTRGF1_Pos)
„8PWM_ADCTSTS0_CUTRGF2_Pos (16)
…8PWM_ADCTSTS0_CUTRGF2_Msk (0x1ul << PWM_ADCTSTS0_CUTRGF2_Pos)
‡8PWM_ADCTSTS0_CPTRGF2_Pos (17)
ˆ8PWM_ADCTSTS0_CPTRGF2_Msk (0x1ul << PWM_ADCTSTS0_CPTRGF2_Pos)
Š8PWM_ADCTSTS0_CDTRGF2_Pos (18)
‹8PWM_ADCTSTS0_CDTRGF2_Msk (0x1ul << PWM_ADCTSTS0_CDTRGF2_Pos)
8PWM_ADCTSTS0_ZPTRGF2_Pos (19)
Ž8PWM_ADCTSTS0_ZPTRGF2_Msk (0x1ul << PWM_ADCTSTS0_ZPTRGF2_Pos)
8PWM_ADCTSTS0_CUTRGF3_Pos (24)
‘8PWM_ADCTSTS0_CUTRGF3_Msk (0x1ul << PWM_ADCTSTS0_CUTRGF3_Pos)
“8PWM_ADCTSTS0_CPTRGF3_Pos (25)
”8PWM_ADCTSTS0_CPTRGF3_Msk (0x1ul << PWM_ADCTSTS0_CPTRGF3_Pos)
–8PWM_ADCTSTS0_CDTRGF3_Pos (26)
—8PWM_ADCTSTS0_CDTRGF3_Msk (0x1ul << PWM_ADCTSTS0_CDTRGF3_Pos)
™8PWM_ADCTSTS0_ZPTRGF3_Pos (27)
š8PWM_ADCTSTS0_ZPTRGF3_Msk (0x1ul << PWM_ADCTSTS0_ZPTRGF3_Pos)
œ8PWM_ADCTSTS1_CUTRGF4_Pos (0)
8PWM_ADCTSTS1_CUTRGF4_Msk (0x1ul << PWM_ADCTSTS1_CUTRGF4_Pos)
Ÿ8PWM_ADCTSTS1_CPTRGF4_Pos (1)
 8PWM_ADCTSTS1_CPTRGF4_Msk (0x1ul << PWM_ADCTSTS1_CPTRGF4_Pos)
¢8PWM_ADCTSTS1_CDTRGF4_Pos (2)
£8PWM_ADCTSTS1_CDTRGF4_Msk (0x1ul << PWM_ADCTSTS1_CDTRGF4_Pos)
¥8PWM_ADCTSTS1_ZPTRGF4_Pos (3)
¦8PWM_ADCTSTS1_ZPTRGF4_Msk (0x1ul << PWM_ADCTSTS1_ZPTRGF4_Pos)
¨8PWM_ADCTSTS1_CUTRGF5_Pos (8)
©8PWM_ADCTSTS1_CUTRGF5_Msk (0x1ul << PWM_ADCTSTS1_CUTRGF5_Pos)
«8PWM_ADCTSTS1_CPTRGF5_Pos (9)
¬8PWM_ADCTSTS1_CPTRGF5_Msk (0x1ul << PWM_ADCTSTS1_CPTRGF5_Pos)
®8PWM_ADCTSTS1_CDTRGF5_Pos (10)
¯8PWM_ADCTSTS1_CDTRGF5_Msk (0x1ul << PWM_ADCTSTS1_CDTRGF5_Pos)
±8PWM_ADCTSTS1_ZPTRGF5_Pos (11)
²8PWM_ADCTSTS1_ZPTRGF5_Msk (0x1ul << PWM_ADCTSTS1_ZPTRGF5_Pos)
µ8PWM_ADCTSTS1_CUTRGF6_Pos (16)
¶8PWM_ADCTSTS1_CUTRGF6_Msk (0x1ul << PWM_ADCTSTS7_CUTRGF6_Pos)
¸8PWM_ADCTSTS1_CPTRGF6_Pos (17)
¹8PWM_ADCTSTS1_CPTRGF6_Msk (0x1ul << PWM_ADCTSTS7_CPTRGF6_Pos)
»8PWM_ADCTSTS1_CDTRGF6_Pos (18)
¼8PWM_ADCTSTS1_CDTRGF6_Msk (0x1ul << PWM_ADCTSTS7_CDTRGF6_Pos)
¾8PWM_ADCTSTS1_ZPTRGF6_Pos (19)
¿8PWM_ADCTSTS1_ZPTRGF6_Msk (0x1ul << PWM_ADCTSTS7_ZPTRGF6_Pos)
Á8PWM_ADCTSTS1_CUTRGF7_Pos (24)
Â8PWM_ADCTSTS1_CUTRGF7_Msk (0x1ul << PWM_ADCTSTS7_CUTRGF7_Pos)
Ä8PWM_ADCTSTS1_CPTRGF7_Pos (25)
Å8PWM_ADCTSTS1_CPTRGF7_Msk (0x1ul << PWM_ADCTSTS7_CPTRGF7_Pos)
Ç8PWM_ADCTSTS1_CDTRGF7_Pos (26)
È8PWM_ADCTSTS1_CDTRGF7_Msk (0x1ul << PWM_ADCTSTS7_CDTRGF7_Pos)
Ê8PWM_ADCTSTS1_ZPTRGF7_Pos (27)
Ë8PWM_ADCTSTS1_ZPTRGF7_Msk (0x1ul << PWM_ADCTSTS7_ZPTRGF7_Pos)
Í8PWM_PCACTL_PCAEN_Pos (0)
Î8PWM_PCACTL_PCAEN_Msk (0x1ul << PWM_PCACTL_PCAEN_Pos)
÷8FLCTL_CTL_BYTES_NUM_R_Pos (8)
ø8FLCTL_CTL_BYTES_NUM_R_Msk (0xFFFFFFul << FLCTL_CTL_BYTES_NUM_R_Pos)
ù8FLCTL_CTL_BYTES_NUM_W_Pos (0)
ú8FLCTL_CTL_BYTES_NUM_W_Msk (0x7ul << FLCTL_CTL_BYTES_NUM_W_Pos)
ý8FLCTL_TRIG_TRG_Pos (0)
þ8FLCTL_TRIG_TRG_Msk (0x1ul << FLCTL_TRIG_TRG_Pos)
9FLCTL_CONFIG_FLASH_CAP_Pos (3)
‚9FLCTL_CONFIG_FLASH_CAP_Msk (0x7ul << FLCTL_CONFIG_FLASH_CAP_Pos)
ƒ9FLCTL_CONFIG_TX_ADDR_TRANS_Pos (2)
„9FLCTL_CONFIG_TX_ADDR_TRANS_Msk (0x1ul << FLCTL_CONFIG_TX_ADDR_TRANS_Pos)
…9FLCTL_CONFIG_INFO_EN_Pos (1)
†9FLCTL_CONFIG_INFO_EN_Msk (0x1ul << FLCTL_CONFIG_INFO_EN_Pos)
‡9FLCTL_CONFIG_PP_ACTIVE_Pos (0)
ˆ9FLCTL_CONFIG_PP_ACTIVE_Msk (0x1ul << FLCTL_CONFIG_PP_ACTIVE_Pos)
‹9FLCTL_W_DATA_Pos (0)
Œ9FLCTL_W_DATA_Msk (0xFFul << FLCTL_W_DATA_Pos)
9FLCTL_X_MODE_TIMEOUT_CNT_Pos (26)
9FLCTL_X_MODE_TIMEOUT_CNT_Msk (0x3Ful << FLCTL_X_MODE_TIMEOUT_CNT_Pos)
‘9FLCTL_X_MODE_RESUME_EN_Pos (25)
’9FLCTL_X_MODE_RESUME_EN_Msk (0x1ul << FLCTL_X_MODE_RESUME_EN_Pos)
“9FLCTL_X_MODE_SUS_SUCCESS_Pos (24)
”9FLCTL_X_MODE_SUS_SUCCESS_Msk (0x1ul << FLCTL_X_MODE_SUS_SUCCESS_Pos)
–9FLCTL_X_MODE_CLK_DLY_Pos (21)
—9FLCTL_X_MODE_CLK_DLY_Msk (0x7ul << FLCTL_X_MODE_CLK_DLY_Pos)
˜9FLCTL_X_MODE_RX_NEG_Pos (20)
™9FLCTL_X_MODE_RX_NEG_Msk (0x1ul << FLCTL_X_MODE_RX_NEG_Pos)
š9FLCTL_X_MODE_CRC32_EN_Pos (19)
›9FLCTL_X_MODE_CRC32_EN_Msk (0x1ul << FLCTL_X_MODE_CRC32_EN_Pos)
œ9FLCTL_X_MODE_ENHANCE_MODE_Pos (18)
9FLCTL_X_MODE_ENHANCE_MODE_Msk (0x1ul << FLCTL_X_MODE_ENHANCE_MODE_Pos)
ž9FLCTL_X_MODE_LONG_TIME_OP_Pos (17)
Ÿ9FLCTL_X_MODE_LONG_TIME_OP_Msk (0x1ul << FLCTL_X_MODE_LONG_TIME_OP_Pos)
 9FLCTL_X_MODE_EN_BURST_WRAP_Pos (16)
¡9FLCTL_X_MODE_EN_BURST_WRAP_Msk (0x1ul << FLCTL_X_MODE_EN_BURST_WRAP_Pos)
¢9FLCTL_X_MODE_CS_IDLE_CYCLE_Pos (8)
£9FLCTL_X_MODE_CS_IDLE_CYCLE_Msk (0xFFul << FLCTL_X_MODE_CS_IDLE_CYCLE_Pos)
¤9FLCTL_X_MODE_X_MODE_Pos (0)
¥9FLCTL_X_MODE_X_MODE_Msk (0x3ul << FLCTL_X_MODE_X_MODE_Pos)
¨9FLCTL_X2_CMD_Pos (0)
©9FLCTL_X2_CMD_Msk (0xFFul << FLCTL_X2_CMD_Pos)
¬9FLCTL_X4_CMD_Pos (0)
­9FLCTL_X4_CMD_Msk (0xFFul << FLCTL_X4_CMD_Pos)
°9FLCTL_DP_CMD_Pos (0)
±9FLCTL_DP_CMD_Msk (0xFFul << FLCTL_DP_CMD_Pos)
´9FLCTL_RDP_CMD_Pos (0)
µ9FLCTL_RDP_CMD_Msk (0xFFul << FLCTL_RDP_CMD_Pos)
¸9FLCTL_REMAP_ADDR_Pos (0)
¹9FLCTL_REMAP_ADDR_Msk (0xFFul << FLCTL_REMAP_ADDR_Pos)
¼9FLCTL_DP_CTL_RDP_WT_CNT_Pos (16)
½9FLCTL_DP_CTL_RDP_WT_CNT_Msk (0xFFFFul << FLCTL_DP_CTL_RDP_WT_CNT_Pos)
¾9FLCTL_DP_CTL_DP_WT_CNT_Pos (4)
¿9FLCTL_DP_CTL_DP_WT_CNT_Msk (0xFFFul << FLCTL_DP_CTL_DP_WT_CNT_Pos)
À9FLCTL_DP_CTL_DP_EN_Pos (0)
Á9FLCTL_DP_CTL_DP_EN_Msk (0x1ul << FLCTL_DP_CTL_DP_EN_Pos)
Ä9FLCTL_PROGRAM_SUS_CMD_Pos (24)
Å9FLCTL_PROGRAM_SUS_CMD_Msk (0xFFul << FLCTL_PROGRAM_SUS_CMD_Pos)
Æ9FLCTL_PROGRAM_RESUME_CMD_Pos (16)
Ç9FLCTL_PROGRAM_RESUME_CMD_Msk (0xFFul << FLCTL_PROGRAM_RESUME_CMD_Pos)
È9FLCTL_ERASE_SUS_CMD_Pos (8)
É9FLCTL_ERASE_SUS_CMD_Msk (0xFFul << FLCTL_ERASE_SUS_CMD_Pos)
Ê9FLCTL_ERASE_RESUME_CMD_Pos (0)
Ë9FLCTL_ERASE_RESUME_CMD_Msk (0xFFul << FLCTL_ERASE_RESUME_CMD_Pos)
ò9SPI_CR0_SCR_Pos (8)
ó9SPI_CR0_SCR_Msk (0xFFul << SPI_CR0_SCR_Pos)
õ9SPI_CR0_SPH_Pos (7)
ö9SPI_CR0_SPH_Msk (0x1ul << SPI_CR0_SPH_Pos)
ø9SPI_CR0_SPO_Pos (6)
ù9SPI_CR0_SPO_Msk (0x1ul << SPI_CR0_SPO_Pos)
û9SPI_CR0_FRF_Pos (4)
ü9SPI_CR0_FRF_Msk (0x3ul << SPI_CR0_FRF_Pos)
þ9SPI_CR0_DSS_Pos (0)
ÿ9SPI_CR0_DSS_Msk (0xFul << SPI_CR0_DSS_Pos)
:SPI_CR1_SPI_MODE_SEL_Pos (10)
‚:SPI_CR1_SPI_MODE_SEL_Msk (0x1ul << SPI_CR1_SPI_MODE_SEL_Pos)
ƒ:SPI_CR1_CMD_DAT_EN_Pos (9)
„:SPI_CR1_CMD_DAT_EN_Msk (0x1ul << SPI_CR1_CMD_DAT_EN_Pos)
…:SPI_CR1_CMD_DAT_CTRL_Pos (8)
†:SPI_CR1_CMD_DAT_CTRL_Msk (0x1ul << SPI_CR1_CMD_DAT_CTRL_Pos)
‡:SPI_CR1_WR_CTRL_Pos (7)
ˆ:SPI_CR1_WR_CTRL_Msk (0x1ul << SPI_CR1_WR_CTRL_Pos)
Š:SPI_CR1_RX_LSB_EN_Pos (5)
‹:SPI_CR1_RX_LSB_EN_Msk (0x1ul << SPI_CR1_RX_LSB_EN_Pos)
:SPI_CR1_TX_LSB_EN_Pos (4)
Ž:SPI_CR1_TX_LSB_EN_Msk (0x1ul << SPI_CR1_TX_LSB_EN_Pos)
:SPI_CR1_SOD_Pos (3)
‘:SPI_CR1_SOD_Msk (0x1ul << SPI_CR1_SOD_Pos)
“:SPI_CR1_MS_Pos (2)
”:SPI_CR1_MS_Msk (0x1ul << SPI_CR1_MS_Pos)
–:SPI_CR1_SSE_Pos (1)
—:SPI_CR1_SSE_Msk (0x1ul << SPI_CR1_SSE_Pos)
™:SPI_CR1_LBM_Pos (0)
š:SPI_CR1_LBM_Msk (0x1ul << SPI_CR1_LBM_Pos)
œ:SPI_DR_Pos (0)
:SPI_DR_Msk (0xFFul << SPI_DR_Pos)
 :SPI_SR_BUSY_Pos (4)
¡:SPI_SR_BUSY_Msk (0x1ul << SPI_SR_BUSY_Pos)
£:SPI_SR_RFF_Pos (3)
¤:SPI_SR_RFF_Msk (0x1ul << SPI_SR_RFF_Pos)
¦:SPI_SR_RFNE_Pos (2)
§:SPI_SR_RFNE_Msk (0x1ul << SPI_SR_RFNE_Pos)
©:SPI_SR_TFNF_Pos (1)
ª:SPI_SR_TFNF_Msk (0x1ul << SPI_SR_TFNF_Pos)
¬:SPI_SR_TFE_Pos (0)
­:SPI_SR_TFE_Msk (0x1ul << SPI_SR_TFE_Pos)
°:SPI_CPSR_DIV_Pos (0)
±:SPI_CPSR_DIV_Msk (0xFul << SPI_CPSR_DIV_Pos)
´:SPI_IMSC_TXIM_Pos (3)
µ:SPI_IMSC_TXIM_Msk (0x1ul << SPI_IMSC_TXIM_Pos)
·:SPI_IMSC_RXIM_Pos (2)
¸:SPI_IMSC_RXIM_Msk (0x1ul << SPI_IMSC_RXIM_Pos)
º:SPI_IMSC_RTIM_Pos (1)
»:SPI_IMSC_RTIM_Msk (0x1ul << SPI_IMSC_RTIM_Pos)
¾:SPI_RIS_TXIS_Pos (3)
¿:SPI_RIS_TXIS_Msk (0x1ul << SPI_RIS_TXIS_Pos)
Á:SPI_RIS_RXIS_Pos (2)
Â:SPI_RIS_RXIS_Msk (0x1ul << SPI_RIS_RXIS_Pos)
Ä:SPI_RIS_RTIS_Pos (1)
Å:SPI_RIS_RTIS_Msk (0x1ul << SPI_RIS_RTIS_Pos)
Ç:SPI_RIS_RORIS_Pos (0)
È:SPI_RIS_RORIS_Msk (0x1ul << SPI_RIS_RORIS_Pos)
Ê:SPI_MIS_TXMIS_Pos (3)
Ë:SPI_MIS_TXMIS_Msk (0x1ul << SPI_MIS_TXMIS_Pos)
Í:SPI_MIS_RXMIS_Pos (2)
Î:SPI_MIS_RXMIS_Msk (0x1ul << SPI_MIS_RXMIS_Pos)
Ð:SPI_MIS_RTMIS_Pos (1)
Ñ:SPI_MIS_RTMIS_Msk (0x1ul << SPI_MIS_RTMIS_Pos)
Ó:SPI_MIS_RORMIS_Pos (0)
Ô:SPI_MIS_RORMIS_Msk (0x1ul << SPI_MIS_RORMIS_Pos)
×:SPI_ICR_RTICR_Pos (1)
Ø:SPI_ICR_RTICR_Msk (0x1ul << SPI_ICR_RTICR_Pos)
Ú:SPI_ICR_RORICR_Pos (0)
Û:SPI_ICR_RORICR_Msk (0x1ul << SPI_ICR_RORICR_Pos)
Þ:SPI_DMACR_TDMAE_Pos (1)
ß:SPI_DMACR_TDMAE_Msk (0x1ul << SPI_DMACR_TDMAE_Pos)
á:SPI_DMACR_RDMAE_Pos (0)
â:SPI_DMACR_RDMAE_Msk (0x1ul << SPI_DMACR_RDMAE_Pos)
”>UART_RBR_MSB9_Pos (8)
•>UART_RBR_MSB9_Msk (0x1ul << UART_RBR_MSB9_Pos)
—>UART_RBR_DAT_Pos (0)
˜>UART_RBR_DAT_Msk (0xfful << UART_RBR_DAT_Pos)
š>UART_THR_MSB9_Pos (8)
›>UART_THR_MSB9_Msk (0x1ul << UART_THR_MSB9_Pos)
>UART_THR_DAT_Pos (0)
ž>UART_THR_DAT_Msk (0xfful << UART_THR_DAT_Pos)
 >UART_DLH_Pos (0)
¡>UART_DLH_Msk (0xfful << UART_DLH_Pos)
£>UART_DLL_Pos (0)
¤>UART_DLL_Msk (0xfful << UART_DLL_Pos)
¦>UART_IER_EPTI_Pos (7)
§>UART_IER_EPTI_Msk (0x1ul << UART_IER_EPTI_Pos)
©>UART_IER_EMSI_Pos (3)
ª>UART_IER_EMSI_Msk (0x1ul << UART_IER_EMSI_Pos)
«>UART_IER_ERLSI_Pos (2)
¬>UART_IER_ERLSI_Msk (0x1ul << UART_IER_ERLSI_Pos)
­>UART_IER_ETHREI_Pos (1)
®>UART_IER_ETHREI_Msk (0x1ul << UART_IER_ETHREI_Pos)
¯>UART_IER_ERDAI_Pos (0)
°>UART_IER_ERDAI_Msk (0x1ul << UART_IER_ERDAI_Pos)
²>UART_IER_ALL_IRQ_Pos (0)
³>UART_IER_ALL_IRQ_Msk (0xful << UART_IER_ALL_IRQ_Pos)
µ>UART_IIR_FIFOSE_Pos (6)
¶>UART_IIR_FIFOSE_Msk (0x3ul << UART_IIR_FIFOSE_Pos)
¸>UART_IIR_IID_Pos (0)
¹>UART_IIR_IID_Msk (0xful << UART_IIR_IID_Pos)
¼>UART_FCR_RT_Pos (6)
½>UART_FCR_RT_Msk (0x3ul << UART_FCR_RT_Pos)
¾>UART_FCR_TET_Pos (4)
¿>UART_FCR_TET_Msk (0x3ul << UART_FCR_TET_Pos)
À>UART_FCR_DMAM_Pos (3)
Á>UART_FCR_DMAM_Msk (0x1ul << UART_FCR_DMAM_Pos)
Â>UART_FCR_XFIFOR_Pos (2)
Ã>UART_FCR_XFIFOR_Msk (0x1ul << UART_FCR_XFIFOR_Pos)
Ä>UART_FCR_RFIFOR_Pos (1)
Å>UART_FCR_RFIFOR_Msk (0x1ul << UART_FCR_RFIFOR_Pos)
Æ>UART_FCR_FIFOE_Pos (0)
Ç>UART_FCR_FIFOE_Msk (0x1ul << UART_FCR_FIFOE_Pos)
Ê>UART_LCR_DLAB_Pos (7)
Ë>UART_LCR_DLAB_Msk (0x1ul << UART_LCR_DLAB_Pos)
Ì>UART_LCR_BC_Pos (6)
Í>UART_LCR_BC_Msk (0x1ul << UART_LCR_BC_Pos)
Î>UART_LCR_SP_Pos (5)
Ï>UART_LCR_SP_Msk (0x1ul << UART_LCR_SP_Pos)
Ð>UART_LCR_EPS_Pos (4)
Ñ>UART_LCR_EPS_Msk (0x1ul << UART_LCR_EPS_Pos)
Ò>UART_LCR_PEN_Pos (3)
Ó>UART_LCR_PEN_Msk (0x1ul << UART_LCR_PEN_Pos)
Ô>UART_LCR_STOP_Pos (2)
Õ>UART_LCR_STOP_Msk (0x1ul << UART_LCR_STOP_Pos)
Ö>UART_LCR_DLS_Pos (0)
×>UART_LCR_DLS_Msk (0x3ul << UART_LCR_DLS_Pos)
Ú>UART_MCR_SIRE_Pos (6)
Û>UART_MCR_SIRE_Msk (0x1ul << UART_MCR_SIRE_Pos)
Ü>UART_MCR_AFCE_Pos (5)
Ý>UART_MCR_AFCE_Msk (0x1ul << UART_MCR_AFCE_Pos)
Þ>UART_MCR_LB_Pos (4)
ß>UART_MCR_LB_Msk (0x1ul << UART_MCR_LB_Pos)
à>UART_MCR_OUT2_Pos (3)
á>UART_MCR_OUT2_Msk (0x1ul << UART_MCR_OUT2_Pos)
â>UART_MCR_OUT1_Pos (2)
ã>UART_MCR_OUT1_Msk (0x1ul << UART_MCR_OUT1_Pos)
ä>UART_MCR_RTS_Pos (1)
å>UART_MCR_RTS_Msk (0x1ul << UART_MCR_RTS_Pos)
æ>UART_MCR_DTR_Pos (0)
ç>UART_MCR_DTR_Msk (0x1ul << UART_MCR_DTR_Pos)
ê>UART_LSR_ADDR_RCVD_Pos (8)
ë>UART_LSR_ADDR_RCVD_Msk (0x1ul << UART_LSR_ADDR_RCVD_Pos)
ì>UART_LSR_RFE_Pos (7)
í>UART_LSR_RFE_Msk (0x1ul << UART_LSR_RFE_Pos)
î>UART_LSR_TEMT_Pos (6)
ï>UART_LSR_TEMT_Msk (0x1ul << UART_LSR_TEMT_Pos)
ð>UART_LSR_THRE_Pos (5)
ñ>UART_LSR_THRE_Msk (0x1ul << UART_LSR_THRE_Pos)
ò>UART_LSR_BI_Pos (4)
ó>UART_LSR_BI_Msk (0x1ul << UART_LSR_BI_Pos)
ô>UART_LSR_FE_Pos (3)
õ>UART_LSR_FE_Msk (0x1ul << UART_LSR_FE_Pos)
ö>UART_LSR_PE_Pos (2)
÷>UART_LSR_PE_Msk (0x1ul << UART_LSR_PE_Pos)
ø>UART_LSR_OE_Pos (1)
ù>UART_LSR_OE_Msk (0x1ul << UART_LSR_OE_Pos)
ú>UART_LSR_DR_Pos (0)
û>UART_LSR_DR_Msk (0x1ul << UART_LSR_DR_Pos)
ý>UART_LSR_LINE_STATUS_Pos (0)
þ>UART_LSR_LINE_STATUS_Msk (0x1FFul << UART_LSR_LINE_STATUS_Pos)
?UART_MSR_DCD_Pos (7)
‚?UART_MSR_DCD_Msk (0x1ul << UART_MSR_DCD_Pos)
ƒ?UART_MSR_RI_Pos (6)
„?UART_MSR_RI_Msk (0x1ul << UART_MSR_RI_Pos)
…?UART_MSR_DSR_Pos (5)
†?UART_MSR_DSR_Msk (0x1ul << UART_MSR_DSR_Pos)
‡?UART_MSR_CTS_Pos (4)
ˆ?UART_MSR_CTS_Msk (0x1ul << UART_MSR_CTS_Pos)
‰?UART_MSR_DDCD_Pos (3)
Š?UART_MSR_DDCD_Msk (0x1ul << UART_MSR_DDCD_Pos)
‹?UART_MSR_TERI_Pos (2)
Œ?UART_MSR_TERI_Msk (0x1ul << UART_MSR_TERI_Pos)
?UART_MSR_DDSR_Pos (1)
Ž?UART_MSR_DDSR_Msk (0x1ul << UART_MSR_DDSR_Pos)
?UART_MSR_DCTS_Pos (0)
?UART_MSR_DCTS_Msk (0x1ul << UART_MSR_DCTS_Pos)
’?UART_MSR_MODEM_STATUS_Pos (0)
“?UART_MSR_MODEM_STATUS_Msk (0xFFul << UART_MSR_MODEM_STATUS_Pos)
–?UART_SCR_Pos (0)
—?UART_SCR_Msk (0xFFFFFFFFul << UART_SCR_Pos)
š?UART_LPDLL_Pos (0)
›?UART_LPDLL_Msk (0xFFul << UART_LPDLL_Pos)
ž?UART_LPDLH_Pos (0)
Ÿ?UART_LPDLH_Msk (0xFFul << UART_LPDLH_Pos)
¢?UART_USR_RFF_Pos (4)
£?UART_USR_RFF_Msk (0x1ul << UART_USR_RFF_Pos)
¤?UART_USR_RFNE_Pos (3)
¥?UART_USR_RFNE_Msk (0x1ul << UART_USR_RFNE_Pos)
¦?UART_USR_TFE_Pos (2)
§?UART_USR_TFE_Msk (0x1ul << UART_USR_TFE_Pos)
¨?UART_USR_TFNF_Pos (1)
©?UART_USR_TFNF_Msk (0x1ul << UART_USR_TFNF_Pos)
¬?UART_TFL_Pos (0)
­?UART_TFL_Msk (0x1Ful << UART_TFL_Pos)
°?UART_RFL_Pos (0)
±?UART_RFL_Msk (0x1Ful << UART_RFL_Pos)
´?UART_DMASA_Pos (0)
µ?UART_DMASA_Msk (0x1ul << UART_DMASA_Pos)
¸?UART_DLF_Pos (0)
¹?UART_DLF_Msk (0xFul << UART_DLF_Pos)
¼?UART_RAR_Pos (0)
½?UART_RAR_Msk (0xFFul << UART_RAR_Pos)
À?UART_TAR_Pos (0)
Á?UART_TAR_Msk (0xFFul << UART_TAR_Pos)
Æ?UART_LCR_EXT_TRANSMIT_MODE_Pos (3)
Ç?UART_LCR_EXT_TRANSMIT_MODE_Msk (0x1ul << UART_LCR_EXT_TRANSMIT_MODE_Pos)
È?UART_LCR_EXT_SEND_ADDR_Pos (2)
É?UART_LCR_EXT_SEND_ADDR_Msk (0x1ul << UART_LCR_EXT_SEND_ADDR_Pos)
Ê?UART_LCR_EXT_ADDR_MATCH_Pos (1)
Ë?UART_LCR_EXT_ADDR_MATCH_Msk (0x1ul << UART_LCR_EXT_ADDR_MATCH_Pos)
Ì?UART_LCR_EXT_DLS_E_Pos (0)
Í?UART_LCR_EXT_DLS_E_Msk (0x1ul << UART_LCR_EXT_DLS_E_Pos)
Ø?UART_DR_OE ((uint32_t)0x00000800)
Ù?UART_DR_BE ((uint32_t)0x00000400)
Ú?UART_DR_PE ((uint32_t)0x00000200)
Û?UART_DR_FE ((uint32_t)0x00000100)
Ü?UART_DR_DATA ((uint32_t)0x000000FF)
à?UART_RSCR_OE ((uint32_t)0x00000008)
á?UART_RSCR_BE ((uint32_t)0x00000004)
â?UART_RSCR_PE ((uint32_t)0x00000002)
ã?UART_RSCR_FE ((uint32_t)0x00000001)
å?UART_RSCR_CLR_ERR ((uint32_t)0x000000ff)
ê?UART_STATUS_RI ((uint32_t)0x00000100)
ë?UART_STATUS_TXFE ((uint32_t)0x00000080)
ì?UART_STATUS_RXFF ((uint32_t)0x00000040)
í?UART_STATUS_TXFF ((uint32_t)0x00000020)
î?UART_STATUS_RXFE ((uint32_t)0x00000010)
ï?UART_STATUS_BUSY ((uint32_t)0x00000008)
ð?UART_STATUS_DCD ((uint32_t)0x00000004)
ñ?UART_STATUS_DSR ((uint32_t)0x00000002)
ò?UART_STATUS_CTS ((uint32_t)0x00000001)
õ?UART_IRDA_LP_DIV ((uint32_t)0x000000FF)
ø?UART_BRD_IBRD ((uint32_t)0x0000FFFF)
û?UART_BRD_FBRD ((uint32_t)0x0000003F)
þ?UART_LC_CLEAR_MSK ((uint32_t)0x000000FF)
€@UART_LC_SPS ((uint32_t)0x00000080)
@UART_LC_WLEN ((uint32_t)0x00000060)
‚@UART_LC_FEN ((uint32_t)0x00000010)
ƒ@UART_LC_STP2 ((uint32_t)0x00000008)
„@UART_LC_EPS ((uint32_t)0x00000004)
…@UART_LC_PEN ((uint32_t)0x00000002)
†@UART_LC_BRK ((uint32_t)0x00000001)
‰@UART_CR_CLEAR_MSK ((uint32_t)0x0000FF87)
‹@UART_CR_CTSEN ((uint32_t)0x00008000)
Œ@UART_CR_RTSEN ((uint32_t)0x00004000)
@UART_CR_OUT2 ((uint32_t)0x00002000)
Ž@UART_CR_OUT1 ((uint32_t)0x00001000)
@UART_CR_RTS ((uint32_t)0x00000800)
@UART_CR_DTR ((uint32_t)0x00000400)
‘@UART_CR_RXE ((uint32_t)0x00000200)
’@UART_CR_TXE ((uint32_t)0x00000100)
“@UART_CR_LBE ((uint32_t)0x00000080)
”@UART_CR_SIRLP ((uint32_t)0x00000004)
•@UART_CR_SIREN ((uint32_t)0x00000002)
–@UART_CR_UARTEN ((uint32_t)0x00000001)
™@UART_INT_FIFO_RXIFLSEL ((uint32_t)0x00000038)
š@UART_INT_FIFO_TXIFLSEL ((uint32_t)0x00000007)
@UART_INT_MSK_OEIM ((uint32_t)0x00000400)
ž@UART_INT_MSK_BEIM ((uint32_t)0x00000200)
Ÿ@UART_INT_MSK_PEIM ((uint32_t)0x00000100)
 @UART_INT_MSK_FEIM ((uint32_t)0x00000080)
¡@UART_INT_MSK_RTIM ((uint32_t)0x00000040)
¢@UART_INT_MSK_TXIM ((uint32_t)0x00000020)
£@UART_INT_MSK_RXIM ((uint32_t)0x00000010)
¤@UART_INT_MSK_DSRMIM ((uint32_t)0x00000008)
¥@UART_INT_MSK_DCDMIM ((uint32_t)0x00000004)
¦@UART_INT_MSK_CTSMIM ((uint32_t)0x00000002)
§@UART_INT_MSK_RIMIM ((uint32_t)0x00000001)
ª@UART_RAW_INT_MSK_OEIM ((uint32_t)0x00000400)
«@UART_RAW_INT_MSK_BEIM ((uint32_t)0x00000200)
¬@UART_RAW_INT_MSK_PEIM ((uint32_t)0x00000100)
­@UART_RAW_INT_MSK_FEIM ((uint32_t)0x00000080)
®@UART_RAW_INT_MSK_RTIM ((uint32_t)0x00000040)
¯@UART_RAW_INT_MSK_TXIM ((uint32_t)0x00000020)
°@UART_RAW_INT_MSK_RXIM ((uint32_t)0x00000010)
±@UART_RAW_INT_MSK_DSRMIM ((uint32_t)0x00000008)
²@UART_RAW_INT_MSK_DCDMIM ((uint32_t)0x00000004)
³@UART_RAW_INT_MSK_CTSMIM ((uint32_t)0x00000002)
´@UART_RAW_INT_MSK_RIMIM ((uint32_t)0x00000001)
·@UART_MASKED_INT_STAT_OEIM ((uint32_t)0x00000400)
¸@UART_MASKED_INT_STAT_BEIM ((uint32_t)0x00000200)
¹@UART_MASKED_INT_STAT_PEIM ((uint32_t)0x00000100)
º@UART_MASKED_INT_STAT_FEIM ((uint32_t)0x00000080)
»@UART_MASKED_INT_STAT_RTIM ((uint32_t)0x00000040)
¼@UART_MASKED_INT_STAT_TXIM ((uint32_t)0x00000020)
½@UART_MASKED_INT_STAT_RXIM ((uint32_t)0x00000010)
¾@UART_MASKED_INT_STAT_DSRMIM ((uint32_t)0x00000008)
¿@UART_MASKED_INT_STAT_DCDMIM ((uint32_t)0x00000004)
À@UART_MASKED_INT_STAT_CTSMIM ((uint32_t)0x00000002)
Á@UART_MASKED_INT_STAT_RIMIM ((uint32_t)0x00000001)
Ä@UART_CLR_INT_OEIM ((uint32_t)0x00000400)
Å@UART_CLR_INT_BEIM ((uint32_t)0x00000200)
Æ@UART_CLR_INT_PEIM ((uint32_t)0x00000100)
Ç@UART_CLR_INT_FEIM ((uint32_t)0x00000080)
È@UART_CLR_INT_RTIM ((uint32_t)0x00000040)
É@UART_CLR_INT_TXIM ((uint32_t)0x00000020)
Ê@UART_CLR_INT_RXIM ((uint32_t)0x00000010)
Ë@UART_CLR_INT_DSRMIM ((uint32_t)0x00000008)
Ì@UART_CLR_INT_DCDMIM ((uint32_t)0x00000004)
Í@UART_CLR_INT_CTSMIM ((uint32_t)0x00000002)
Î@UART_CLR_INT_RIMIM ((uint32_t)0x00000001)
Ñ@UART_DMA_CR_DMAONERR ((uint32_t)0x00000004)
Ò@UART_DMA_CR_TXDMAE ((uint32_t)0x00000002)
Ó@UART_DMA_CR_RXDMAE ((uint32_t)0x00000001)
ÎADMAC_DMACFGREG_L_DMA_EN_Pos (0)
ÏADMAC_DMACFGREG_L_DMA_EN_Msk (0x1ul << DMAC_DMACFGREG_L_DMA_EN_Pos)
ÑADMAC_CHENREG_L_CH_EN_Pos(ch) (ch)
ÒADMAC_CHENREG_L_CH_EN_Msk(ch) (0x1ul << DMAC_CHENREG_L_CH_EN_Pos(ch))
ÔADMAC_CHENREG_L_CH_EN_ALL_Pos (0)
ÕADMAC_CHENREG_L_CH_EN_ALL_Msk (0xfful << DMAC_CHENREG_L_CH_EN_ALL_Pos)
×ADMAC_CHENREG_L_CH_EN_WE_Pos(ch) ((ch)+8)
ØADMAC_CHENREG_L_CH_EN_WE_Msk(ch) (0x1ul << DMAC_CHENREG_L_CH_EN_WE_Pos(ch))
ÚADMAC_CHENREG_L_CH_EN_WE_ALL_Pos (8)
ÛADMAC_CHENREG_L_CH_EN_WE_ALL_Msk (0xfful << DMAC_CHENREG_L_CH_EN_WE_ALL_Pos)
ÝADMAC_SAR_L_SAR_Pos (0)
ÞADMAC_SAR_L_SAR_Msk (0xfffffffful << DMAC_SAR_L_SAR_Pos)
àADMAC_DAR_L_DAR_Pos (0)
áADMAC_DAR_L_DAR_Msk (0xfffffffful << DMAC_DAR_L_DAR_Pos)
ãADMAC_CTL_L_INT_EN_Pos (0)
äADMAC_CTL_L_INT_EN_Msk (0x1ul << DMAC_CTL_L_INT_EN_Pos)
æADMAC_CTL_L_DST_TR_WIDTH_Pos (1)
çADMAC_CTL_L_DST_TR_WIDTH_Msk (0x3ul << DMAC_CTL_L_DST_TR_WIDTH_Pos)
éADMAC_CTL_L_SRC_TR_WIDTH_Pos (4)
êADMAC_CTL_L_SRC_TR_WIDTH_Msk (0x3ul << DMAC_CTL_L_SRC_TR_WIDTH_Pos)
ìADMAC_CTL_L_DINC_Pos (7)
íADMAC_CTL_L_DINC_Msk (0x3ul << DMAC_CTL_L_DINC_Pos)
ïADMAC_CTL_L_SINC_Pos (9)
ðADMAC_CTL_L_SINC_Msk (0x3ul << DMAC_CTL_L_SINC_Pos)
òADMAC_CTL_L_DEST_MSIZE_Pos (11)
óADMAC_CTL_L_DEST_MSIZE_Msk (0x7ul << DMAC_CTL_L_DEST_MSIZE_Pos)
õADMAC_CTL_L_SRC_MSIZE_Pos (14)
öADMAC_CTL_L_SRC_MSIZE_Msk (0x7ul << DMAC_CTL_L_SRC_MSIZE_Pos)
øADMAC_CTL_L_TT_FC_Pos (20)
ùADMAC_CTL_L_TT_FC_Msk (0x7ul << DMAC_CTL_L_TT_FC_Pos)
ûADMAC_CTL_H_BLOCK_TS_Pos (0)
üADMAC_CTL_H_BLOCK_TS_Msk (0xffful << DMAC_CTL_H_BLOCK_TS_Pos)
þADMAC_CTL_H_DONE_Pos (12)
ÿADMAC_CTL_H_DONE_Msk (0x1ul << DMAC_CTL_H_DONE_Pos)
BDMAC_CFG_L_CH_PRIOR_Pos (5)
‚BDMAC_CFG_L_CH_PRIOR_Msk (0x7 << DMAC_CFG_L_CH_PRIOR_Pos)
„BDMAC_CFG_L_CH_SUSP_Pos (8)
…BDMAC_CFG_L_CH_SUSP_Msk (0x1ul << DMAC_CFG_L_CH_SUSP_Pos)
‡BDMAC_CFG_L_FIFO_EMPTY_Pos (9)
ˆBDMAC_CFG_L_FIFO_EMPTY_Msk (0x1ul << DMAC_CFG_L_FIFO_EMPTY_Pos)
ŠBDMAC_CFG_L_HS_SEL_DST_Pos (10)
‹BDMAC_CFG_L_HS_SEL_DST_Msk (0x1ul << DMAC_CFG_L_HS_SEL_DST_Pos)
BDMAC_CFG_L_HS_SEL_SRC_Pos (11)
ŽBDMAC_CFG_L_HS_SEL_SRC_Msk (0x1ul << DMAC_CFG_L_HS_SEL_SRC_Pos)
‘BDMAC_CFG_L_DST_HS_POL_Pos (18)
’BDMAC_CFG_L_DST_HS_POL_Msk (0x1ul << DMAC_CFG_L_DST_HS_POL_Pos)
”BDMAC_CFG_L_SRC_HS_POL_Pos (19)
•BDMAC_CFG_L_SRC_HS_POL_Msk (0x1ul << DMAC_CFG_L_SRC_HS_POL_Pos)
™BDMAC_CFG_H_FCMODE_Pos (0)
šBDMAC_CFG_H_FCMODE_Msk (0x1ul << DMAC_CFG_H_FCMODE_Pos)
œBDMAC_CFG_H_FIFO_MODE_Pos (1)
BDMAC_CFG_H_FIFO_MODE_Msk (0x1ul << DMAC_CFG_H_FIFO_MODE_Pos)
ŸBDMAC_CFG_H_PROTCTL_Pos (2)
 BDMAC_CFG_H_PROTCTL_Msk (0x7ul << DMAC_CFG_H_PROTCTL_Pos)
¢BDMAC_CFG_H_SRC_PER_Pos (7)
£BDMAC_CFG_H_SRC_PER_Msk (0xful << DMAC_CFG_H_SRC_PER_Pos)
¥BDMAC_CFG_H_DEST_PER_Pos (11)
¦BDMAC_CFG_H_DEST_PER_Msk (0xful << DMAC_CFG_H_DEST_PER_Pos)
¨BDMAC_INT_RAW_STAT_CLR_Pos(ch) (ch)
©BDMAC_INT_RAW_STAT_CLR_Msk(ch) (0x1ul << DMAC_INT_RAW_STAT_CLR_Pos(ch))
«BDMAC_INT_RAW_STAT_CLR_ALL_Pos (0)
¬BDMAC_INT_RAW_STAT_CLR_ALL_Msk (0xfful << DMAC_INT_RAW_STAT_CLR_ALL_Pos)
®BDMAC_INT_MASK_L_Pos(ch) (ch)
¯BDMAC_INT_MASK_L_Msk(ch) (0x1ul << DMAC_INT_MASK_L_Pos(ch))
±BDMAC_INT_MASK_L_ALL_Pos (0)
²BDMAC_INT_MASK_L_ALL_Msk (0xfful << DMAC_INT_MASK_L_ALL_Pos)
´BDMAC_INT_MASK_L_WE_Pos(ch) ((ch)+8)
µBDMAC_INT_MASK_L_WE_Msk(ch) (0x1ul << DMAC_INT_MASK_L_WE_Pos(ch))
·BDMAC_INT_MASK_L_WE_ALL_Pos (8)
¸BDMAC_INT_MASK_L_WE_ALL_Msk (0xfful << DMAC_INT_MASK_L_WE_ALL_Pos)
ºBDMAC_STATUSINT_L_TFR_Pos (0)
»BDMAC_STATUSINT_L_TFR_Msk (0x1ul << DMAC_STATUSINT_L_TFR_Pos)
½BDMAC_STATUSINT_L_BLOCK_Pos (1)
¾BDMAC_STATUSINT_L_BLOCK_Msk (0x1ul << DMAC_STATUSINT_L_BLOCK_Pos)
ÀBDMAC_STATUSINT_L_SRCTRAN_Pos (2)
ÁBDMAC_STATUSINT_L_SRCTRAN_Msk (0x1ul << DMAC_STATUSINT_L_SRCTRAN_Pos)
ÃBDMAC_STATUSINT_L_DSTTRAN_Pos (3)
ÄBDMAC_STATUSINT_L_DSTTRAN_Msk (0x1ul << DMAC_STATUSINT_L_DSTTRAN_Pos)
ÆBDMAC_STATUSINT_L_ERR_Pos (4)
ÇBDMAC_STATUSINT_L_ERR_Msk (0x1ul << DMAC_STATUSINT_L_ERR_Pos)
‰CI2C_CON_MASTER_MODE ((uint16_t)0x0001)
‹CI2C_CON_SPEED ((uint16_t)0x0006)
ŒCI2C_CON_SPEED_0 ((uint16_t)0x0002)
CI2C_CON_SPEED_1 ((uint16_t)0x0004)
CI2C_CON_IC_10BITADDR_SLAVE ((uint16_t)0x0008)
CI2C_CON_IC_10BITADDR_MASTER ((uint16_t)0x0010)
‘CI2C_CON_IC_RESTART_EN ((uint16_t)0x0020)
’CI2C_CON_IC_SLAVE_DISABLE ((uint16_t)0x0040)
“CI2C_CON_STOP_DET_IFADDRESSED ((uint16_t)0x0080)
”CI2C_CON_TX_EMPTY_CTRL ((uint16_t)0x0100)
—CI2C_TAR_TAR ((uint16_t)0x03ff)
˜CI2C_TAR_IC_TAR_0 ((uint16_t)0x0001)
™CI2C_TAR_IC_TAR_1 ((uint16_t)0x0002)
šCI2C_TAR_IC_TAR_2 ((uint16_t)0x0004)
›CI2C_TAR_IC_TAR_3 ((uint16_t)0x0008)
œCI2C_TAR_IC_TAR_4 ((uint16_t)0x0010)
CI2C_TAR_IC_TAR_5 ((uint16_t)0x0020)
žCI2C_TAR_IC_TAR_6 ((uint16_t)0x0040)
ŸCI2C_TAR_IC_TAR_7 ((uint16_t)0x0080)
 CI2C_TAR_IC_TAR_8 ((uint16_t)0x0100)
¡CI2C_TAR_IC_TAR_9 ((uint16_t)0x0200)
£CI2C_TAR_GC_OR_START ((uint16_t)0x0400)
¤CI2C_TAR_SPECIAL ((uint16_t)0x0800)
¥CI2C_TAR_IC_10BITADDR_MASTER ((uint16_t)0x1000)
¨CI2C_SAR_IC_SAR ((uint16_t)0x03ff)
ªCI2C_HS_MADDR_IC_HS_MAR ((uint16_t)0x0007)
¬CI2C_DATA_CMD_DAT ((uint16_t)0x00ff)
­CI2C_DATA_CMD_CMD_R ((uint16_t)0x0100)
®CI2C_DATA_CMD_STOP ((uint16_t)0x0200)
¯CI2C_DATA_CMD_RESTART ((uint16_t)0x0400)
²CI2C_SS_SCL_HCNT ((uint16_t)0xffff)
µCI2C_SS_SCL_LCNT ((uint16_t)0xffff)
¸CI2C_FS_SCL_HCNT ((uint16_t)0xffff)
»CI2C_FS_SCL_LCNT ((uint16_t)0xffff)
¾CI2C_HS_SCL_HCNT ((uint16_t)0xffff)
ÁCI2C_HS_SCL_LCNT ((uint16_t)0xffff)
ÄCI2C_INTR_STAT_R_RX_UNDER ((uint16_t)0x0001)
ÅCI2C_INTR_STAT_R_RX_OVER ((uint16_t)0x0002)
ÆCI2C_INTR_STAT_R_RX_FULL ((uint16_t)0x0004)
ÇCI2C_INTR_STAT_R_TX_OVER ((uint16_t)0x0008)
ÈCI2C_INTR_STAT_R_TX_EMPTY ((uint16_t)0x0010)
ÉCI2C_INTR_STAT_R_RD_REQ ((uint16_t)0x0020)
ÊCI2C_INTR_STAT_R_TX_ABRT ((uint16_t)0x0040)
ËCI2C_INTR_STAT_R_RX_DONE ((uint16_t)0x0080)
ÌCI2C_INTR_STAT_R_ACTIVITY ((uint16_t)0x0100)
ÍCI2C_INTR_STAT_R_STOP_DET ((uint16_t)0x0200)
ÎCI2C_INTR_STAT_R_START_DET ((uint16_t)0x0400)
ÏCI2C_INTR_STAT_R_GEN_CALL ((uint16_t)0x0800)
ÐCI2C_INTR_STAT_R_RESTART_DET ((uint16_t)0x1000)
ÑCI2C_INTR_STAT_R_MST_ON_HOLD ((uint16_t)0x2000)
ÕCI2C_INTR_MASK_M_RX_UNDER ((uint16_t)0x0001)
ÖCI2C_INTR_MASK_M_RX_OVER ((uint16_t)0x0002)
×CI2C_INTR_MASK_M_RX_FULL ((uint16_t)0x0004)
ØCI2C_INTR_MASK_M_TX_OVER ((uint16_t)0x0008)
ÙCI2C_INTR_MASK_M_TX_EMPTY ((uint16_t)0x0010)
ÚCI2C_INTR_MASK_M_RD_REQ ((uint16_t)0x0020)
ÛCI2C_INTR_MASK_M_TX_ABRT ((uint16_t)0x0040)
ÜCI2C_INTR_MASK_M_RX_DONE ((uint16_t)0x0080)
ÝCI2C_INTR_MASK_M_ACTIVITY ((uint16_t)0x0100)
ÞCI2C_INTR_MASK_M_STOP_DET ((uint16_t)0x0200)
ßCI2C_INTR_MASK_M_START_DET ((uint16_t)0x0400)
àCI2C_INTR_MASK_M_GEN_CALL ((uint16_t)0x0800)
áCI2C_INTR_MASK_M_RESTART_DET ((uint16_t)0x1000)
âCI2C_INTR_MASK_M_MST_ON_HOLD ((uint16_t)0x2000)
åCI2C_RAW_INTR_STAT_RX_UNDER ((uint16_t)0x0001)
æCI2C_RAW_INTR_STAT_RX_OVER ((uint16_t)0x0002)
çCI2C_RAW_INTR_STAT_RX_FULL ((uint16_t)0x0004)
èCI2C_RAW_INTR_STAT_TX_OVER ((uint16_t)0x0008)
éCI2C_RAW_INTR_STAT_TX_EMPTY ((uint16_t)0x0010)
êCI2C_RAW_INTR_STAT_RD_REQ ((uint16_t)0x0020)
ëCI2C_RAW_INTR_STAT_TX_ABRT ((uint16_t)0x0040)
ìCI2C_RAW_INTR_STAT_RX_DONE ((uint16_t)0x0080)
íCI2C_RAW_INTR_STAT_ACTIVITY ((uint16_t)0x0100)
îCI2C_RAW_INTR_STAT_STOP_DET ((uint16_t)0x0200)
ïCI2C_RAW_INTR_STAT_START_DET ((uint16_t)0x0400)
ðCI2C_RAW_INTR_STAT_GEN_CALL ((uint16_t)0x0800)
ñCI2C_RAW_INTR_STAT_RESTART_DET ((uint16_t)0x1000)
òCI2C_RAW_INTR_STAT_MST_ON_HOLD ((uint16_t)0x2000)
õCI2C_RX_TL ((uint16_t)0x00ff)
øCI2C_TX_TL ((uint16_t)0x00ff)
ûCI2C_CLR_INTR ((uint16_t)0x0001)
þCI2C_CLR_RX_UNDER ((uint16_t)0x0001)
DI2C_CLR_RX_UNDER ((uint16_t)0x0001)
„DI2C_CLR_TX_OVER ((uint16_t)0x0001)
‡DI2C_CLR_RD_REQ ((uint16_t)0x0001)
ŠDI2C_CLR_TX_ABORT ((uint16_t)0x0001)
DI2C_CLR_RX_DONE ((uint16_t)0x0001)
DI2C_CLR_ACTIVITY ((uint16_t)0x0001)
“DI2C_CLR_STOP_DET ((uint16_t)0x0001)
–DI2C_CLR_START_DET ((uint16_t)0x0001)
™DI2C_CLR_GEN_CALL ((uint16_t)0x0001)
›DI2C_CLR_RESTART_DET ((uint16_t)0x0001)
DI2C_CLR_MST_ON_HOLD ((uint16_t)0x0001)
¡DI2C_ENABLE_ENABLE ((uint16_t)0x0001)
¢DI2C_ENABLE_ABORT ((uint16_t)0x0002)
¤DI2C_STATUS_ACTIVITY ((uint16_t)0x0001)
¥DI2C_STATUS_TFNF ((uint16_t)0x0002)
¦DI2C_STATUS_TFE ((uint16_t)0x0004)
§DI2C_STATUS_RFNE ((uint16_t)0x0008)
¨DI2C_STATUS_RFE ((uint16_t)0x0010)
©DI2C_STATUS_MST_ACTIVITY ((uint16_t)0x0020)
ªDI2C_STATUS_SLV_ACTIVITY ((uint16_t)0x0040)
­DI2C_TXFLR ((uint32_t)0x0000000f)
°DI2C_RXFLR ((uint32_t)0x0000000f)
³DI2C_SDA_HOLD ((uint32_t)0x0000ffff)
¶DI2C_TX_ABRT_SOURCE_7B_ADDR_NOACK ((uint32_t)0x00000001)
·DI2C_TX_ABRT_SOURCE_10ADDR1_NOACK ((uint32_t)0x00000002)
¸DI2C_TX_ABRT_SOURCE_10ADDR2_NOACK ((uint32_t)0x00000004)
¹DI2C_TX_ABRT_SOURCE_TXDATA_NOACK ((uint32_t)0x00000008)
ºDI2C_TX_ABRT_SOURCE_GCALL_NOACK ((uint32_t)0x00000010)
»DI2C_TX_ABRT_SOURCE_GCALL_READ ((uint32_t)0x00000020)
¼DI2C_TX_ABRT_SOURCE_HS_ACKDET ((uint32_t)0x00000040)
½DI2C_TX_ABRT_SOURCE_SBYTE_ACKDET ((uint32_t)0x00000080)
¾DI2C_TX_ABRT_SOURCE_HS_NORSTRT ((uint32_t)0x00000100)
¿DI2C_TX_ABRT_SOURCE_SBYTE_NORSTRT ((uint32_t)0x00000200)
ÀDI2C_TX_ABRT_SOURCE_10B_RD_NORSTRT ((uint32_t)0x00000400)
ÁDI2C_TX_ABRT_SOURCE_MASTER_DIS ((uint32_t)0x00000800)
ÂDI2C_TX_ABRT_SOURCE_ARB_LOST ((uint32_t)0x00001000)
ÃDI2C_TX_ABRT_SOURCE_SLVFLUSH_TXFIFO ((uint32_t)0x00002000)
ÄDI2C_TX_ABRT_SOURCE_SLV_ARBLOST ((uint32_t)0x00004000)
ÅDI2C_TX_ABRT_SOURCE_SLVRD_INTX ((uint32_t)0x00008000)
ÆDI2C_TX_ABRT_SOURCE_USER_ABRT ((uint32_t)0x00010000)
ÈDI2C_TX_ABRT_SOURCE_TX_FLUSH_CNT ((uint32_t)0xff000000)
ËDI2C_SLV_DATA_NACK_ONLY ((uint32_t)0x00000001)
ÎDI2C_DMA_CR_RDMAE ((uint32_t)0x00000001)
ÏDI2C_DMA_CR_TDMAE ((uint32_t)0x00000002)
ÒDI2C_DMA_TDLR ((uint32_t)0x00000007)
ÕDI2C_DMA_RDLR ((uint32_t)0x00000007)
ØDI2C_SDA_SETUP ((uint32_t)0x000000ff)
ÛDI2C_ACK_GENERAL_CALL ((uint32_t)0x00000001)
ÞDI2C_ENABLE_STATUS_IC_EN ((uint32_t)0x00000001)
ßDI2C_ENABLE_STATUS_SLV_RX_ABORTED ((uint32_t)0x00000002)
àDI2C_ENABLE_STATUS_SLV_FIFO_FILLED_AND_FLUSHED ((uint32_t)0x00000004)
ãDI2C_FS_SPKLEN ((uint32_t)0x0000000ff)
æDI2C_HS_SPKLEN ((uint32_t)0x0000000ff)
éDI2C_COMP_PARAM1_APB_DATA_WIDTH ((uint32_t)0x000000003)
êDI2C_COMP_PARAM1_MAX_SPEED_MODE ((uint32_t)0x000000006)
ëDI2C_COMP_PARAM1_HC_COUNT_VALUES ((uint32_t)0x000000010)
ìDI2C_COMP_PARAM1_INTR_IO ((uint32_t)0x000000020)
íDI2C_COMP_PARAM1_HAS_DMA ((uint32_t)0x000000040)
îDI2C_COMP_PARAM1_ADD_ENCODED_PARAMS ((uint32_t)0x000000080)
ïDI2C_COMP_PARAM1_RX_BUFFER_DEPTH ((uint32_t)0x00000ff00)
ðDI2C_COMP_PARAM1_TX_BUFFER_DEPTH ((uint32_t)0x000ff0000)
óDI2C_COMP_VERSION ((uint32_t)0xffffffffff)
öDI2C_COMP_TYPE ((uint32_t)0xffffffffff)
–EANAC_LP_REG_SYNC_3V_Pos (0)
—EANAC_LP_REG_SYNC_3V_Msk (0x1ul << ANAC_LP_REG_SYNC_3V_Pos)
˜EANAC_LP_REG_SYNC_3V_TRG_Pos (1)
™EANAC_LP_REG_SYNC_3V_TRG_Msk (0x1ul << ANAC_LP_REG_SYNC_3V_TRG_Pos)
›EANAC_FL_SLEEP_MODE_SEL_Pos (0)
œEANAC_FL_SLEEP_MODE_SEL_Msk (0x3ul << ANAC_FL_SLEEP_MODE_SEL_Pos)
EANAC_FL_EXT_WAKEUP_SEL_Pos_3v (2)
žEANAC_FL_EXT_WAKEUP_SEL_Msk_3v (0x1ul << ANAC_FL_EXT_WAKEUP_SEL_Pos_3v)
ŸEANAC_FL_SLEEP_CNT_EN_Pos (3)
 EANAC_FL_SLEEP_CNT_EN_Msk (0x1ul << ANAC_FL_SLEEP_CNT_EN_Pos)
¡EANAC_FL_CPU_RETENTION_EN_Pos (4)
¢EANAC_FL_CPU_RETENTION_EN_Msk (0x1ul << ANAC_FL_CPU_RETENTION_EN_Pos)
£EANAC_FL_LDO_ISOLATE_EN_Pos (5)
¤EANAC_FL_LDO_ISOLATE_EN_Msk (0x1ul << ANAC_FL_LDO_ISOLATE_EN_Pos)
¥EANAC_FL_RCL_GATE_EN_Pos (6)
¦EANAC_FL_RCL_GATE_EN_Msk (0x1ul << ANAC_FL_RCL_GATE_EN_Pos)
§EANAC_FL_PWR_CTL_EN_Pos (7)
¨EANAC_FL_PWR_CTL_EN_Msk (0x1ul << ANAC_FL_PWR_CTL_EN_Pos)
©EANAC_FL_FLASH_BP_EN_Pos (12)
ªEANAC_FL_FLASH_BP_EN_Msk (0x1ul << ANAC_FL_FLASH_BP_EN_Pos)
«EANAC_FL_FLASH_LP_EN_Pos (13)
¬EANAC_FL_FLASH_LP_EN_Msk (0x1ul << ANAC_FL_FLASH_LP_EN_Pos)
­EANAC_FL_BUCK_BP_EN_Pos (14)
®EANAC_FL_BUCK_BP_EN_Msk (0x1ul << ANAC_FL_BUCK_BP_EN_Pos)
¯EANAC_FL_BUCK_EN_Pos (15)
°EANAC_FL_BUCK_EN_Msk (0x1ul << ANAC_FL_BUCK_EN_Pos)
±EANAC_FL_DPLL_EN_Pos (16)
²EANAC_FL_DPLL_EN_Msk (0x1ul << ANAC_FL_DPLL_EN_Pos)
³EANAC_FL_RCH_EN_Pos (17)
´EANAC_FL_RCH_EN_Msk (0x1ul << ANAC_FL_RCH_EN_Pos)
µEANAC_FL_XTH_EN_Pos (18)
¶EANAC_FL_XTH_EN_Msk (0x1ul << ANAC_FL_XTH_EN_Pos)
·EANAC_FL_XTAL32K_EN_Pos_3v (19)
¸EANAC_FL_XTAL32K_EN_Msk_3v (0x1ul << ANAC_FL_XTAL32K_EN_Pos_3v)
¹EANAC_FL_RC32K_EN_Pos_3v (20)
ºEANAC_FL_RC32K_EN_Msk_3v (0x1ul << ANAC_FL_RC32K_EN_Pos_3v)
»EANAC_FL_LDO_HP_EN_Pos (22)
¼EANAC_FL_LDO_HP_EN_Msk (0x1ul << ANAC_FL_LDO_HP_EN_Pos)
½EANAC_FL_PMU_EN_Pos (23)
¾EANAC_FL_PMU_EN_Msk (0x1ul << ANAC_FL_PMU_EN_Pos)
¿EANAC_SRAM0_POWER_CTL_Pos (24)
ÀEANAC_SRAM0_POWER_CTL_Msk (0x1ul << ANAC_SRAM0_POWER_CTL_Pos)
ÁEANAC_SRAM1_POWER_CTL_Pos (25)
ÂEANAC_SRAM1_POWER_CTL_Msk (0x1ul << ANAC_SRAM1_POWER_CTL_Pos)
ÃEANAC_CPU_POWER_CTL_Pos (26)
ÄEANAC_CPU_POWER_CTL_Msk (0x1ul << ANAC_CPU_POWER_CTL_Pos)
ÅEANAC_PHY_POWER_CTL_Pos (27)
ÆEANAC_PHY_POWER_CTL_Msk (0x1ul << ANAC_PHY_POWER_CTL_Pos)
ÇEANAC_LL_SRAM_POWER_CTL_Pos (28)
ÈEANAC_LL_SRAM_POWER_CTL_Msk (0x1ul << ANAC_LL_SRAM_POWER_CTL_Pos)
ÉEANAC_FLASH_POWER_CTL_Pos (29)
ÊEANAC_FLASH_POWER_CTL_Msk (0x1ul << ANAC_FLASH_POWER_CTL_Pos)
ËEANAC_LDO_POWER_CTL_Pos (30)
ÌEANAC_LDO_POWER_CTL_Msk (0x1ul << ANAC_LDO_POWER_CTL_Pos)
ÍEANAC_LDOL_POWER_CTL_Pos (31)
ÎEANAC_LDOL_POWER_CTL_Msk (0x1ul << ANAC_LDOL_POWER_CTL_Pos)
ÒEANAC_INT_LP_INT_EN_Pos (0)
ÓEANAC_INT_LP_INT_EN_Msk (0x1ul << ANAC_INT_LP_INT_EN_Pos)
ÔEANAC_INT_DP_FLAG_Pos (1)
ÕEANAC_INT_DP_FLAG_Msk (0x1ul << ANAC_INT_DP_FLAG_Pos)
ÖEANAC_INT_STANDBY_M1_FLAG_Pos (2)
×EANAC_INT_STANDBY_M1_FLAG_Msk (0x1ul << ANAC_INT_STANDBY_M1_FLAG_Pos)
ØEANAC_INT_STANDBY_M0_FLAG_Pos (3)
ÙEANAC_INT_STANDBY_M0_FLAG_Msk (0x1ul << ANAC_INT_STANDBY_M0_FLAG_Pos)
ÚEANAC_INT_SRAM_RET_FLAG_Pos (4)
ÛEANAC_INT_SRAM_RET_FLAG_Msk (0x1ul << ANAC_INT_SRAM_RET_FLAG_Pos)
ÜEANAC_INT_SLEEP_TMR_INT_EN_Pos (16)
ÝEANAC_INT_SLEEP_TMR_INT_EN_Msk (0x1ul << ANAC_INT_SLEEP_TMR_INT_EN_Pos)
ÞEANAC_INT_SLEEP_TMR0_Pos (17)
ßEANAC_INT_SLEEP_TMR0_Msk (0x1ul << ANAC_INT_SLEEP_TMR0_Pos)
àEANAC_INT_SLEEP_TMR1_Pos (18)
áEANAC_INT_SLEEP_TMR1_Msk (0x1ul << ANAC_INT_SLEEP_TMR1_Pos)
âEANAC_INT_SLEEP_TMR2_Pos (19)
ãEANAC_INT_SLEEP_TMR2_Msk (0x1ul << ANAC_INT_SLEEP_TMR2_Pos)
äEANAC_INT_SLEEP_TMR_WK_EN_Pos (20)
åEANAC_INT_SLEEP_TMR_WK_EN_Msk (0x1ul << ANAC_INT_SLEEP_TMR_WK_EN_Pos)
èEANAC_32KCLK_DLY_TIME_Pos (0)
éEANAC_32KCLK_DLY_TIME_Msk (0x3FFul << ANAC_32KCLK_DLY_TIME_Pos)
êEANAC_32KCLK_DLY_EN_Pos (10)
ëEANAC_32KCLK_DLY_EN_Msk (0x1ul << ANAC_32KCLK_DLY_EN_Pos)
ìEANAC_HPLDO_RDY_BYPASS_Pos (11)
íEANAC_HPLDO_RDY_BYPASS_Msk (0x1ul << ANAC_HPLDO_RDY_BYPASS_Pos)
îEANAC_LPLDOH_DLY_TIME_Pos_3v (16)
ïEANAC_LPLDOH_DLY_TIME_Msk_3v (0x3FFul << ANAC_LPLDOH_DLY_TIME_Pos_3v)
òEANAC_PTAT_CORE_EN_Pos (0)
óEANAC_PTAT_CORE_EN_Msk (0x1ul << ANAC_PTAT_CORE_EN_Pos)
ôEANAC_PTAT_TMP_TRIM_Pos (1)
õEANAC_PTAT_TMP_TRIM_Msk (0x3ul << ANAC_PTAT_TMP_TRIM_Pos)
öEANAC_PTAT_TRIM_Pos (3)
÷EANAC_PTAT_TRIM_Msk (0x7ul << ANAC_PTAT_TRIM_Pos)
øEANAC_PTAT_FLT_SHIFT_EN_Pos (6)
ùEANAC_PTAT_FLT_SHIFT_EN_Msk (0x1ul << ANAC_PTAT_FLT_SHIFT_EN_Pos)
úEANAC_PTAT_FLT_ACT_EN_Pos (7)
ûEANAC_PTAT_FLT_ACT_EN_Msk (0x1ul << ANAC_PTAT_FLT_ACT_EN_Pos)
üEANAC_POLY_EN_Pos (8)
ýEANAC_POLY_EN_Msk (0x1ul << ANAC_POLY_EN_Pos)
þEANAC_IPOLY_TRIM_Pos (16)
ÿEANAC_IPOLY_TRIM_Msk (0x3ul << ANAC_IPOLY_TRIM_Pos)
‚FANAC_HPLDO_EN_Pos (0)
ƒFANAC_HPLDO_EN_Msk (0x1ul << ANAC_HPLDO_EN_Pos)
„FANAC_HPLDO_BYPASS_Pos (2)
…FANAC_HPLDO_BYPASS_Msk (0x1ul << ANAC_HPLDO_BYPASS_Pos)
†FANAC_HPLDO_TRIM_Pos (3)
‡FANAC_HPLDO_TRIM_Msk (0xFul << ANAC_HPLDO_TRIM_Pos)
ˆFANAC_HPLDO_SEL_Pos (9)
‰FANAC_HPLDO_SEL_Msk (0x1ul << ANAC_HPLDO_SEL_Pos)
ŠFANAC_HPLDO_FLASHLDO_BP_Pos_3v (16)
‹FANAC_HPLDO_FLASHLDO_BP_Msk_3v (0x1ul << ANAC_HPLDO_FLASHLDO_BP_Pos_3v)
ŒFANAC_HPLDO_FLASHLDO_EN_Pos_3v (17)
FANAC_HPLDO_FLASHLDO_EN_Msk_3v (0x1ul << ANAC_HPLDO_FLASHLDO_EN_Pos_3v)
ŽFANAC_HPLDO_FLASHLDO_LP_EN_Pos (18)
FANAC_HPLDO_FLASHLDO_LP_EN_Msk (0x1ul << ANAC_HPLDO_FLASHLDO_LP_EN_Pos)
FANAC_HPLDO_FLASHLDO_CAP_SEL_Pos (19)
‘FANAC_HPLDO_FLASHLDO_CAP_SEL_Msk (0x1ul << ANAC_HPLDO_FLASHLDO_CAP_SEL_Pos)
’FANAC_HPLDO_FLASHLDO_TRIM_Pos (20)
“FANAC_HPLDO_FLASHLDO_TRIM_Msk (0x7ul << ANAC_HPLDO_FLASHLDO_TRIM_Pos)
•FANAC_LPLDO_L_EN_Pos (0)
–FANAC_LPLDO_L_EN_Msk (0x1ul << ANAC_LPLDO_L_EN_Pos)
—FANAC_LPLDO_L_DVDD_SEL_Pos (1)
˜FANAC_LPLDO_L_DVDD_SEL_Msk (0xFul << ANAC_LPLDO_L_DVDD_SEL_Pos)
™FANAC_LPLDO_H_EN_Pos_3v (16)
šFANAC_LPLDO_H_EN_Msk_3v (0x1ul << ANAC_LPLDO_H_EN_Pos_3v)
›FANAC_LPLDO_H_DVDD_SEL_Pos_3v (17)
œFANAC_LPLDO_H_DVDD_SEL_Msk_3v (0xFul << ANAC_LPLDO_H_DVDD_SEL_Pos_3v)
FANAC_LPLDO_H_REF_TRIM_Pos_3v (21)
žFANAC_LPLDO_H_REF_TRIM_Msk_3v (0x7ul << ANAC_LPLDO_H_REF_TRIM_Pos_3v)
ŸFANAC_LPLDO_H_MODE_SEL_Pos_3v (24)
 FANAC_LPLDO_H_MODE_SEL_Msk_3v (0x1ul << ANAC_LPLDO_H_MODE_SEL_Pos_3v)
£FANAC_ANA_LDO_EN_Pos (0)
¤FANAC_ANA_LDO_EN_Msk (0x1ul << ANAC_ANA_LDO_EN_Pos)
¥FANAC_ANA_LDO_TRIM_Pos (3)
¦FANAC_ANA_LDO_TRIM_Msk (0xFul << ANAC_ANA_LDO_TRIM_Pos)
¨FANAC_FSYN_LDO_EN_Pos (0)
©FANAC_FSYN_LDO_EN_Msk (0x1ul << ANAC_FSYN_LDO_EN_Pos)
ªFANAC_FSYN_LDO_TRIM_Pos (3)
«FANAC_FSYN_LDO_TRIM_Msk (0xFul << ANAC_FSYN_LDO_TRIM_Pos)
­FANAC_HP_DVDD_PD_Pos (0)
®FANAC_HP_DVDD_PD_Msk (0x1ul << ANAC_HP_DVDD_PD_Pos)
¯FANAC_HP_DVDD_EN_Pos (1)
°FANAC_HP_DVDD_EN_Msk (0x1ul << ANAC_HP_DVDD_EN_Pos)
±FANAC_DVDD_SRAM0_EN_Pos (2)
²FANAC_DVDD_SRAM0_EN_Msk (0x1ul << ANAC_DVDD_SRAM0_EN_Pos)
³FANAC_DVDD_SRAM1_EN_Pos (3)
´FANAC_DVDD_SRAM1_EN_Msk (0x1ul << ANAC_DVDD_SRAM1_EN_Pos)
µFANAC_DVDD_LPLDO_EN_Pos (4)
¶FANAC_DVDD_LPLDO_EN_Msk (0x1ul << ANAC_DVDD_LPLDO_EN_Pos)
·FANAC_VDD_FLASH_EN_Pos (5)
¸FANAC_VDD_FLASH_EN_Msk (0x1ul << ANAC_VDD_FLASH_EN_Pos)
¹FANAC_DVDD_DLL_EN_Pos (6)
ºFANAC_DVDD_DLL_EN_Msk (0x1ul << ANAC_DVDD_DLL_EN_Pos)
»FANAC_DVDD_PHY_EN_Pos (7)
¼FANAC_DVDD_PHY_EN_Msk (0x1ul << ANAC_DVDD_PHY_EN_Pos)
½FANAC_DVDD_CPU_EN_Pos (8)
¾FANAC_DVDD_CPU_EN_Msk (0x1ul << ANAC_DVDD_CPU_EN_Pos)
ÁFANAC_BUCK_BYPASS_EN_Pos_3v (0)
ÂFANAC_BUCK_BYPASS_EN_Msk_3v (0x1ul << ANAC_BUCK_BYPASS_EN_Pos_3v)
ÃFANAC_BUCK_EN_Pos_3v (1)
ÄFANAC_BUCK_EN_Msk_3v (0x1ul << ANAC_BUCK_EN_Pos_3v)
ÅFANAC_BUCK_VOUT_Pos_3v (2)
ÆFANAC_BUCK_VOUT_Msk_3v (0xful << ANAC_BUCK_VOUT_Pos_3v)
ÇFANAC_BUCK_IMAX_Pos_3v (6)
ÈFANAC_BUCK_IMAX_Msk_3v (0x7ul << ANAC_BUCK_IMAX_Pos_3v)
ÉFANAC_BUCK_IMAX_CAL_Pos_3v (9)
ÊFANAC_BUCK_IMAX_CAL_Msk_3v (0x1Ful << ANAC_BUCK_IMAX_CAL_Pos_3v)
ËFANAC_BUCK_ZERO_CAL_Pos_3v (14)
ÌFANAC_BUCK_ZERO_CAL_Msk_3v (0x1Ful << ANAC_BUCK_ZERO_CAL_Pos_3v)
ÍFANAC_BUCK_DLY_MODE_EN_Pos_3v (19)
ÎFANAC_BUCK_DLY_MODE_EN_Msk_3v (0x1ul << ANAC_BUCK_DLY_MODE_EN_Pos_3v)
ÏFANAC_BUCK_TEST_EN_Pos (20)
ÐFANAC_BUCK_TEST_EN_Msk (0x1ul << ANAC_BUCK_TEST_EN_Pos)
ÑFANAC_BUCK_DEBOUNCE_EN_Pos_3v (21)
ÒFANAC_BUCK_DEBOUNCE_EN_Msk_3v (0x1ul << ANAC_BUCK_DEBOUNCE_EN_Pos_3v)
ÓFANAC_BUCK_CAL_EN_Pos_3v (22)
ÔFANAC_BUCK_CAL_EN_Msk_3v (0x3ul << ANAC_BUCK_CAL_EN_Pos_3v)
ÕFANAC_BUCK_CAL_OUT_Pos (24)
ÖFANAC_BUCK_CAL_OUT_Msk (0x1ul << ANAC_BUCK_CAL_OUT_Pos)
×FANAC_BUCK_VOL_LIMIT_EN_Pos_3v (25)
ØFANAC_BUCK_VOL_LIMIT_EN_Msk_3v (0x1ul << ANAC_BUCK_VOL_LIMIT_EN_Pos_3v)
ÛFANAC_ADC_LDO_EN_Pos (0)
ÜFANAC_ADC_LDO_EN_Msk (0x1ul << ANAC_ADC_LDO_EN_Pos)
ÝFANAC_ADC_LDO_TRIM_Pos (3)
ÞFANAC_ADC_LDO_TRIM_Msk (0xFul << ANAC_ADC_LDO_TRIM_Pos)
áFANAC_RFFE_LDO_EN_Pos (0)
âFANAC_RFFE_LDO_EN_Msk (0x1ul << ANAC_RFFE_LDO_EN_Pos)
ãFANAC_RFFE_LDO_TRIM_Pos (3)
äFANAC_RFFE_LDO_TRIM_Msk (0xFul << ANAC_RFFE_LDO_TRIM_Pos)
æFANAC_VCO_LDO_EN_Pos (0)
çFANAC_VCO_LDO_EN_Msk (0x1ul << ANAC_VCO_LDO_EN_Pos)
èFANAC_VCO_LDO_TRIM_Pos (3)
éFANAC_VCO_LDO_TRIM_Msk (0xFul << ANAC_VCO_LDO_TRIM_Pos)
ìFANAC_DFT_BUF_BYPASS_Pos (0)
íFANAC_DFT_BUF_BYPASS_Msk (0x1ul << ANAC_DFT_BUF_BYPASS_Pos)
îFANAC_DFT_FLAG_SEL_Pos (1)
ïFANAC_DFT_FLAG_SEL_Msk (0x3ul << ANAC_DFT_FLAG_SEL_Pos)
ðFANAC_DFT_CLK_SEL_Pos (3)
ñFANAC_DFT_CLK_SEL_Msk (0x7ul << ANAC_DFT_CLK_SEL_Pos)
òFANAC_DFT_I_SEL_Pos (6)
óFANAC_DFT_I_SEL_Msk (0x1ul << ANAC_DFT_I_SEL_Pos)
ôFANAC_DFT_V_SEL_Pos (7)
õFANAC_DFT_V_SEL_Msk (0xFul << ANAC_DFT_V_SEL_Pos)
öFANAC_DFT_FLAG_OUTPUT_EN_Pos (11)
÷FANAC_DFT_FLAG_OUTPUT_EN_Msk (0x1ul << ANAC_DFT_FLAG_OUTPUT_EN_Pos)
øFANAC_DFT_CLK_OUTPUT_EN_Pos (12)
ùFANAC_DFT_CLK_OUTPUT_EN_Msk (0x1ul << ANAC_DFT_CLK_OUTPUT_EN_Pos)
úFANAC_DFT_I_OUTPUT_EN_Pos (13)
ûFANAC_DFT_I_OUTPUT_EN_Msk (0x1ul << ANAC_DFT_I_OUTPUT_EN_Pos)
üFANAC_DFT_V_OUTPUT_EN_Pos (14)
ýFANAC_DFT_V_OUTPUT_EN_Msk (0x1ul << ANAC_DFT_V_OUTPUT_EN_Pos)
þFANAC_DFT_PAD_TEST_SEL_Pos (15)
ÿFANAC_DFT_PAD_TEST_SEL_Msk (0x3ul << ANAC_DFT_PAD_TEST_SEL_Pos)
€GANAC_DFT_BATTERY_TEST_EN_Pos (22)
GANAC_DFT_BATTERY_TEST_EN_Msk (0x1ul << ANAC_DFT_BATTERY_TEST_EN_Pos)
‚GANAC_DFT_BATTERY_TEST_SEL_Pos (23)
ƒGANAC_DFT_BATTERY_TEST_SEL_Msk (0x1ul << ANAC_DFT_BATTERY_TEST_SEL_Pos)
„GANAC_DFT_BATTERY_TEST_TRIM_Pos (24)
…GANAC_DFT_BATTERY_TEST_TRIM_Msk (0xfful << ANAC_DFT_BATTERY_TEST_TRIM_Pos)
ˆGANAC_MISC_RST_VREF_TRIM_Pos_3v (0)
‰GANAC_MISC_RST_VREF_TRIM_Msk_3v (0x7ul << ANAC_MISC_RST_VREF_TRIM_Pos_3v)
ŠGANAC_MISC_PMU_LDO_TST_Pos (3)
‹GANAC_MISC_PMU_LDO_TST_Msk (0x1ul << ANAC_MISC_PMU_LDO_TST_Pos)
ŒGANAC_MISC_PMU_VBG_BUF_EN_Pos (4)
GANAC_MISC_PMU_VBG_BUF_EN_Msk (0x1ul << ANAC_MISC_PMU_VBG_BUF_EN_Pos)
ŽGANAC_MISC_LPLDO_LEVEL_SHIFT_EN_Pos_3v (6)
GANAC_MISC_LPLDO_LEVEL_SHIFT_EN_Msk_3v (0x1ul << ANAC_MISC_LPLDO_LEVEL_SHIFT_EN_Pos_3v)
GANAC_MISC_HPLDO_LEVEL_SHIFT_EN_Pos (7)
‘GANAC_MISC_HPLDO_LEVEL_SHIFT_EN_Msk (0x1ul << ANAC_MISC_HPLDO_LEVEL_SHIFT_EN_Pos)
’GANAC_MISC_FLASH_PAD_PUEN_Pos (14)
“GANAC_MISC_FLASH_PAD_PUEN_Msk (0x3Ful << ANAC_MISC_FLASH_PAD_PUEN_Pos)
”GANAC_MISC_FLASH_PAD_PDEN_Pos (20)
•GANAC_MISC_FLASH_PAD_PDEN_Msk (0x3Ful << ANAC_MISC_FLASH_PAD_PDEN_Pos)
–GANAC_MISC_USB_EN_Pos (26)
—GANAC_MISC_USB_EN_Msk (0x1ul << ANAC_MISC_USB_EN_Pos)
˜GANAC_MISC_USB_DP_PU_Pos (27)
™GANAC_MISC_USB_DP_PU_Msk (0x1ul << ANAC_MISC_USB_DP_PU_Pos)
šGANAC_MISC_USB_DM_PU_Pos (28)
›GANAC_MISC_USB_DM_PU_Msk (0x1ul << ANAC_MISC_USB_DM_PU_Pos)
ŸGANAC_ACT_32K_EN_Pos (0)
 GANAC_ACT_32K_EN_Msk (0x1ul << ANAC_ACT_32K_EN_Pos)
¡GANAC_ACT_32K_SEL_Pos (1)
¢GANAC_ACT_32K_SEL_Msk (0x1ul << ANAC_ACT_32K_SEL_Pos)
£GANAC_ACT_32K_UP_DONE_Pos (3)
¤GANAC_ACT_32K_UP_DONE_Msk (0x1ul << ANAC_ACT_32K_UP_DONE_Pos)
¥GANAC_ACT_32K_FINE_OFFSET_Pos (12)
¦GANAC_ACT_32K_FINE_OFFSET_Msk (0x3FFul << ANAC_ACT_32K_FINE_OFFSET_Pos)
§GANAC_ACT_32K_FINE_CORRECT_Pos (22)
¨GANAC_ACT_32K_FINE_CORRECT_Msk (0x3FFul << ANAC_ACT_32K_FINE_CORRECT_Pos)
«GANAC_CPU_REMAP_ADR_Pos (0)
¬GANAC_CPU_REMAP_ADR_Msk (0xFFFFFFul << ANAC_CPU_REMAP_ADR_Pos)
­GANAC_CPU_ADR_REMAP_EN_Pos (31)
®GANAC_CPU_ADR_REMAP_EN_Msk (0x1ul << ANAC_CPU_ADR_REMAP_EN_Pos)
±GANAC_RCL_HW_CAL_TIME_Pos (0)
²GANAC_RCL_HW_CAL_TIME_Msk (0xFFul << ANAC_RCL_HW_CAL_TIME_Pos)
³GANAC_RCL_HW_CAL_EN_Pos (8)
´GANAC_RCL_HW_CAL_EN_Msk (0x1ul << ANAC_RCL_HW_CAL_EN_Pos)
µGANAC_RCL_HW_CAL_BUSY_Pos (9)
¶GANAC_RCL_HW_CAL_BUSY_Msk (0x1ul << ANAC_RCL_HW_CAL_BUSY_Pos)
ÒGEFUSE_CTL_EFUSE_EN_Pos (0)
ÓGEFUSE_CTL_EFUSE_EN_Msk (0x1ul << EFUSE_CTL_EFUSE_EN_Pos)
ÕGEFUSE_CTL_THR_DVDD_Pos (1)
ÖGEFUSE_CTL_THR_DVDD_Msk (0x1ul << EFUSE_CTL_THR_DVDD_Pos)
ØGEFUSE_CTL_TAEN_RD_CTL_Pos (2)
ÙGEFUSE_CTL_TAEN_RD_CTL_Msk (0x1ul << EFUSE_CTL_TAEN_RD_CTL_Pos)
ÛGEFUSE_CTL_THR_RD_CTL_Pos (3)
ÜGEFUSE_CTL_THR_RD_CTL_Msk (0x1ul << EFUSE_CTL_THR_RD_CTL_Pos)
ÞGEFUSE_CTL_TRD_CTL_Pos (4)
ßGEFUSE_CTL_TRD_CTL_Msk (0x1ul << EFUSE_CTL_TRD_CTL_Pos)
áGEFUSE_CTL_TSR_RD_CTL_Pos (5)
âGEFUSE_CTL_TSR_RD_CTL_Msk (0x1ul << EFUSE_CTL_TSR_RD_CTL_Pos)
äGEFUSE_CTL_TSR_DVDD_CTL_Pos (6)
åGEFUSE_CTL_TSR_DVDD_CTL_Msk (0x1ul << EFUSE_CTL_TSR_DVDD_CTL_Pos)
çGEFUSE_CTL_THP_RD_CTL_Pos (7)
èGEFUSE_CTL_THP_RD_CTL_Msk (0x1ul << EFUSE_CTL_THP_RD_CTL_Pos)
êGEFUSE_CTL_THP_PG_AVDD_CTL_Pos (8)
ëGEFUSE_CTL_THP_PG_AVDD_CTL_Msk (0x1ul << EFUSE_CTL_THP_PG_AVDD_CTL_Pos)
íGEFUSE_CTL_TAEN_PGM_CTL_Pos (9)
îGEFUSE_CTL_TAEN_PGM_CTL_Msk (0x1ul << EFUSE_CTL_TAEN_PGM_CTL_Pos)
ðGEFUSE_CTL_THP_PGM_CTL_Pos (10)
ñGEFUSE_CTL_THP_PGM_CTL_Msk (0x1ul << EFUSE_CTL_THP_PGM_CTL_Pos)
óGEFUSE_CTL_TPGM_CTL_Pos (11)
ôGEFUSE_CTL_TPGM_CTL_Msk (0x1ul << EFUSE_CTL_TPGM_CTL_Pos)
öGEFUSE_CTL_TSP_PGM_CTL_Pos (12)
÷GEFUSE_CTL_TSP_PGM_CTL_Msk (0x1ul << EFUSE_CTL_TSP_PGM_CTL_Pos)
ùGEFUSE_CTL_TSP_PG_AVDD_CTL_Pos (13)
úGEFUSE_CTL_TSP_PG_AVDD_CTL_Msk (0x1ul << EFUSE_CTL_TSP_PG_AVDD_CTL_Pos)
üGEFUSE_CTL_TSP_RD_CTL_Pos (14)
ýGEFUSE_CTL_TSP_TSP_RD_CTL_Msk (0x1ul << EFUSE_CTL_TSP_RD_CTL_Pos)
€HEFUSE_ADDR_EFUSEADDR_ADR_Pos (0)
HEFUSE_ADDR_EFUSEADDR_ADR_Msk (0xfful << EFUSE_ADDR_EFUSEADDR_ADR_Pos)
„HEFUSE_DAT_EFUSEDAT_DAT_Pos (0)
…HEFUSE_DAT_EFUSEDAT_DAT_Msk (0xfful << EFUSE_DAT_EFUSEDAT_DAT_Pos)
‡HEFUSE_DAT_EFUSEDAT_DAT_CONFIRM_Pos (8)
ˆHEFUSE_DAT_EFUSEDAT_DAT_CONFIRM_Msk (0xfful << EFUSE_DAT_EFUSEDAT_DAT_CONFIRM_Pos)
‹HEFUSE_VDD_DVDD_REG_Pos (0)
ŒHEFUSE_VDD_DVDD_REG_Msk (0x1ul << EFUSE_VDD_DVDD_REG_Pos)
ŽHEFUSE_VDD_AVDD_REG_Pos (1)
HEFUSE_VDD_AVDD_REG_Msk (0x1ul << EFUSE_VDD_AVDD_REG_Pos)
’HEFUSE_CMD_EFUSECMD_CMD_Pos (0)
“HEFUSE_CMD_EFUSECMD_CMD_Msk (0x3ul << EFUSE_CMD_EFUSECMD_CMD_Pos)
–HEFUSE_TRG_EFUSETRG_GO_Pos (0)
—HEFUSE_TRG_EFUSETRG_GO_Msk (0x1ul << EFUSE_TRG_EFUSETRG_GO_Pos)
šHEFUSE_PROG_TIMING1_TSP_RD_SET_Pos (0)
›HEFUSE_PROG_TIMING1_TSP_RD_SET_Msk (0x1fful << EFUSE_PROG_TIMING1_TSP_RD_SET_Pos)
HEFUSE_PROG_TIMING1_TSP_PG_AVDD_SET_Pos (9)
žHEFUSE_PROG_TIMING1_TSP_PG_AVDD_SET_Msk (0x1fful << EFUSE_PROG_TIMING1_TSP_PG_AVDD_SET_Pos)
 HEFUSE_PROG_TIMING1_TSP_PGM_SET_Pos (18)
¡HEFUSE_PROG_TIMING1_TSP_PGM_SET_Msk (0x1fful << EFUSE_PROG_TIMING1_TSP_PGM_SET_Pos)
¤HEFUSE_PROG_TIMING2_TPGM_SET_Pos (0)
¥HEFUSE_PROG_TIMING2_TPGM_SET_Msk (0x1fful << EFUSE_PROG_TIMING2_TPGM_SET_Pos)
§HEFUSE_PROG_TIMING2_THP_PGM_SET_Pos (9)
¨HEFUSE_PROG_TIMING2_THP_PGM_SET_Msk (0x1fful << EFUSE_PROG_TIMING2_THP_PGM_SET_Pos)
ªHEFUSE_PROG_TIMING2_TAEN_PGM_SET_Pos (18)
«HEFUSE_PROG_TIMING2_TAEN_PGM_SET_Msk (0x1fful << EFUSE_PROG_TIMING2_TAEN_PGM_SET_Pos)
®HEFUSE_PROG_TIMING3_THP_PG_AVDD_SET_Pos (0)
¯HEFUSE_PROG_TIMING3_THP_PG_AVDD_SET_Msk (0x1fful << EFUSE_PROG_TIMING3_THP_PG_AVDD_SET_Pos)
±HEFUSE_PROG_TIMING3_THP_RD_SET_Pos (9)
²HEFUSE_PROG_TIMING3_THP_RD_SET_Msk (0x1fful << EFUSE_PROG_TIMING3_THP_RD_SET_Pos)
µHEFUSE_READ_TIMING4_TSR_DVDD_SET_Pos (0)
¶HEFUSE_READ_TIMING4_TSR_DVDD_SET_Msk (0x1fful << EFUSE_READ_TIMING4_TSR_DVDD_SET_Pos)
¸HEFUSE_READ_TIMING4_TSR_RD_SET_Pos (9)
¹HEFUSE_READ_TIMING4_TSR_RD_SET_Msk (0x1fful << EFUSE_READ_TIMING4_TSR_RD_SET_Pos)
»HEFUSE_READ_TIMING4_TRD_SET_Pos (18)
¼HEFUSE_READ_TIMING4_TRD_SET_Msk (0x1fful << EFUSE_READ_TIMING4_TRD_SET_Pos)
¿HEFUSE_READ_TIMING5_THR_RD_SET_Pos (0)
ÀHEFUSE_READ_TIMING5_THR_RD_SET_Msk (0x1fful << EFUSE_READ_TIMING5_THR_RD_SET_Pos)
ÂHEFUSE_READ_TIMING5_TAEN_RD_SET_Pos (9)
ÃHEFUSE_READ_TIMING5_TAEN_RD_SET_Msk (0x1fful << EFUSE_READ_TIMING5_TAEN_RD_SET_Pos)
ÅHEFUSE_READ_TIMING5_THR_DVDD_SET_Pos (18)
ÆHEFUSE_READ_TIMING5_THR_DVDD_SET_Msk (0x1fful << EFUSE_READ_TIMING5_THR_DVDD_SET_Pos)
ÉHEFUSE_OP_ERROR_OP_ERROR_Pos (0)
ÊHEFUSE_OP_ERROR_OP_ERROR_Msk (0x1ul << EFUSE_OP_ERROR_OP_ERROR_Pos)
ÍHEFUSE_VERIFY_DEBUG1_VERIFY_DBG_KEY1_Pos (0)
ÎHEFUSE_VERIFY_DEBUG1_VERIFY_DBG_KEY1_Msk (0xfffffffful << EFUSE_VERIFY_DEBUG1_VERIFY_DBG_KEY1_Pos)
ÑHEFUSE_VERIFY_DEBUG2_VERIFY_DBG_KEY2_Pos (0)
ÒHEFUSE_VERIFY_DEBUG2_VERIFY_DBG_KEY2_Msk (0xfffffffful << EFUSE_VERIFY_DEBUG2_VERIFY_DBG_KEY2_Pos)
ÕHEFUSE_VERIFY_DEBUG3_VERIFY_DBG_KEY3_Pos (0)
ÖHEFUSE_VERIFY_DEBUG3_VERIFY_DBG_KEY3_Msk (0xfffffffful << EFUSE_VERIFY_DEBUG3_VERIFY_DBG_KEY3_Pos)
ÙHEFUSE_VERIFY_DEBUG4_VERIFY_DBG_KEY4_Pos (0)
ÚHEFUSE_VERIFY_DEBUG4_VERIFY_DBG_KEY4_Msk (0xfffffffful << EFUSE_VERIFY_DEBUG4_VERIFY_DBG_KEY4_Pos)
ÝHEFUSE_FLASH_PERMISSION_CTRL_Pos (0)
ÞHEFUSE_FLASH_PERMISSION_CTRL_Msk (0x1ul << EFUSE_FLASH_PERMISSION_CTRL_Pos)
’IUSB_DMA_REQUEST_Pos (0)
“IUSB_DMA_REQUEST_Msk (0x1ul << USB_DMA_REQUEST_Pos)
”IUSB_DMA_DIRECTION_Pos (1)
•IUSB_DMA_DIRECTION_Msk (0x1ul << USB_DMA_DIRECTION_Pos)
–IUSB_DMA_MODE_SEL_Pos (2)
—IUSB_DMA_MODE_SEL_Msk (0x1ul << USB_DMA_MODE_SEL_Pos)
˜IUSB_DMA_EP_NUM_Pos (4)
™IUSB_DMA_EP_NUM_Msk (0xful << USB_DMA_EP_NUM_Pos)
àIFSM5_SM_STP_Pos 6
áIFSM5_SM_STP_Msk (0x1ul<<FSM5_SM_STP_Pos)
âIFSM5_SM_TX_LATENCY_Pos 0
ãIFSM5_SM_TX_LATENCY_Msk (0x3ful<<FSM5_SM_TX_LATENCY_Pos)
åIFSM6_SM_RX_LATENCY_Pos 0
æIFSM6_SM_RX_LATENCY_Msk (0xful<<FSM6_SM_RX_LATENCY_Pos)
èIFSM13_SM_RX_PACKET_ADDR_1_Pos 16
éIFSM13_SM_RX_PACKET_ADDR_1_Msk (0xfffful<<FSM13_SM_RX_PACKET_ADDR_1_Pos)
êIFSM13_SM_TX_PACKET_ADDR_1_Pos 0
ëIFSM13_SM_TX_PACKET_ADDR_1_Msk (0xfffful<<FSM13_SM_TX_PACKET_ADDR_1_Pos)
íIFSM14_SM_RX_PACKET_ADDR_2_Pos 16
îIFSM14_SM_RX_PACKET_ADDR_2_Msk (0xfffful<<FSM14_SM_RX_PACKET_ADDR_2_Pos)
ïIFSM14_SM_TX_PACKET_ADDR_2_Pos 0
ðIFSM14_SM_TX_PACKET_ADDR_2_Msk (0xfffful<<FSM14_SM_TX_PACKET_ADDR_2_Pos)
òIFSM15_SM_RX_PACKET_ADDR_3_Pos 16
óIFSM15_SM_RX_PACKET_ADDR_3_Msk (0xfffful<<FSM15_SM_RX_PACKET_ADDR_3_Pos)
ôIFSM15_SM_TX_PACKET_ADDR_3_Pos 0
õIFSM15_SM_TX_PACKET_ADDR_3_Msk (0xfffful<<FSM15_SM_TX_PACKET_ADDR_3_Pos)
÷IFSM16_SM_RX_PACKET_ADDR_4_Pos 16
øIFSM16_SM_RX_PACKET_ADDR_4_Msk (0xfffful<<FSM16_SM_RX_PACKET_ADDR_4_Pos)
ùIFSM16_SM_TX_PACKET_ADDR_4_Pos 0
úIFSM16_SM_TX_PACKET_ADDR_4_Msk (0xfffful<<FSM16_SM_TX_PACKET_ADDR_4_Pos)
üIFSM17_SM_RX_PACKET_ADDR_5_Pos 16
ýIFSM17_SM_RX_PACKET_ADDR_5_Msk (0xfffful<<FSM17_SM_RX_PACKET_ADDR_5_Pos)
þIFSM17_SM_TX_PACKET_ADDR_5_Pos 0
ÿIFSM17_SM_TX_PACKET_ADDR_5_Msk (0xfffful<<FSM17_SM_TX_PACKET_ADDR_5_Pos)
JFSM18_SM_RX_PACKET_ADDR_6_Pos 16
‚JFSM18_SM_RX_PACKET_ADDR_6_Msk (0xfffful<<FSM18_SM_RX_PACKET_ADDR_6_Pos)
ƒJFSM18_SM_TX_PACKET_ADDR_6_Pos 0
„JFSM18_SM_TX_PACKET_ADDR_6_Msk (0xfffful<<FSM18_SM_TX_PACKET_ADDR_6_Pos)
†JFSM19_SM_RX_PACKET_ADDR_7_Pos 16
‡JFSM19_SM_RX_PACKET_ADDR_7_Msk (0xfffful<<FSM19_SM_RX_PACKET_ADDR_7_Pos)
ˆJFSM19_SM_TX_PACKET_ADDR_7_Pos 0
‰JFSM19_SM_TX_PACKET_ADDR_7_Msk (0xfffful<<FSM19_SM_TX_PACKET_ADDR_7_Pos)
‹JPHY1_PHY_DRV_RSP_BUF_FULL_Pos 22
ŒJPHY1_PHY_DRV_RSP_BUF_FULL_Msk (0x1ul<<PHY1_PHY_DRV_RSP_BUF_FULL_Pos)
JPHY1_PHY_DRV_RSP_BUF_EMPTY_Pos 21
ŽJPHY1_PHY_DRV_RSP_BUF_EMPTY_Msk (0x1ul<<PHY1_PHY_DRV_RSP_BUF_EMPTY_Pos)
JPHY1_PHY_DRV_CFG_BUF_ERROR_Pos 20
JPHY1_PHY_DRV_CFG_BUF_ERROR_Msk (0x1ul<<PHY1_PHY_DRV_CFG_BUF_ERROR_Pos)
‘JPHY1_PHY_DRV_CFG_BUF_FULL_Pos 19
’JPHY1_PHY_DRV_CFG_BUF_FULL_Msk (0x1ul<<PHY1_PHY_DRV_CFG_BUF_FULL_Pos)
“JPHY1_PHY_DRV_CFG_BUF_EMPTY_Pos 18
”JPHY1_PHY_DRV_CFG_BUF_EMPTY_Msk (0x1ul<<PHY1_PHY_DRV_CFG_BUF_EMPTY_Pos)
•JPHY1_IF_CLK_PRESCALE_Pos 13
–JPHY1_IF_CLK_PRESCALE_Msk (0x1ful<<PHY1_IF_CLK_PRESCALE_Pos)
—JPHY1_PHY_DRV_RSSI_REG_ADDR_Pos 5
˜JPHY1_PHY_DRV_RSSI_REG_ADDR_Msk (0xfful<<PHY1_PHY_DRV_RSSI_REG_ADDR_Pos)
™JPHY1_PHY_DRV_CFG_TRG_Pos 4
šJPHY1_PHY_DRV_CFG_TRG_Msk (0x1ul<<PHY1_PHY_DRV_CFG_TRG_Pos)
›JPHY1_PHY_DRV_CFG_REG_Pos 2
œJPHY1_PHY_DRV_CFG_REG_Msk (0x3ul<<PHY1_PHY_DRV_CFG_REG_Pos)
JPHY1_PHY_DRV_RSP_BUF_FLUSH_Pos 1
žJPHY1_PHY_DRV_RSP_BUF_FLUSH_Msk (0x1ul<<PHY1_PHY_DRV_RSP_BUF_FLUSH_Pos)
ŸJPHY1_PHY_DRV_CFG_BUF_FLUSH_Pos 0
 JPHY1_PHY_DRV_CFG_BUF_FLUSH_Msk (0x1ul<<PHY1_PHY_DRV_CFG_BUF_FLUSH_Pos)
¢JPHY2_PHY_DRV_RSP_BUF_ERROR_Pos 28
£JPHY2_PHY_DRV_RSP_BUF_ERROR_Msk (0x1ul<<PHY2_PHY_DRV_RSP_BUF_ERROR_Pos)
¤JPHY2_PHY_DRV_SEQ_RX_END_ADDR_Pos 21
¥JPHY2_PHY_DRV_SEQ_RX_END_ADDR_Msk (0x7ful<<PHY2_PHY_DRV_SEQ_RX_END_ADDR_Pos)
¦JPHY2_PHY_DRV_SEQ_TX_END_ADDR_Pos 14
§JPHY2_PHY_DRV_SEQ_TX_END_ADDR_Msk (0x7ful<<PHY2_PHY_DRV_SEQ_TX_END_ADDR_Pos)
¨JPHY2_PHY_DRV_SEQ_RX_STRT_ADDR_Pos 7
©JPHY2_PHY_DRV_SEQ_RX_STRT_ADDR_Msk (0x7ful<<PHY2_PHY_DRV_SEQ_RX_STRT_ADDR_Pos)
ªJPHY2_PHY_DRV_SEQ_TX_STRT_ADDR_Pos 0
«JPHY2_PHY_DRV_SEQ_TX_STRT_ADDR_Msk (0x7ful<<PHY2_PHY_DRV_SEQ_TX_STRT_ADDR_Pos)
­JPHY3_PHY_DRV_CFG_BUF_DIN_Pos 0
®JPHY3_PHY_DRV_CFG_BUF_DIN_Msk (0xfffffffful<<PHY3_PHY_DRV_CFG_BUF_DIN_Pos)
°JPHY4_PHY_DRV_RSP_BUF_DOUT_Pos 0
±JPHY4_PHY_DRV_RSP_BUF_DOUT_Msk (0xfffffffful<<PHY4_PHY_DRV_RSP_BUF_DOUT_Pos)
³JPHY5_PHY_DRV_SET_CHAN_REG_ADDR_Pos 0
´JPHY5_PHY_DRV_SET_CHAN_REG_ADDR_Msk (0xfful<<PHY5_PHY_DRV_SET_CHAN_REG_ADDR_Pos)
¶JINTR1_IC_RNG_DONE_Pos 3
·JINTR1_IC_RNG_DONE_Msk (0x1ul<<INTR1_IC_RNG_DONE_Pos)
¸JINTR1_IC_SEC_DONE_Pos 2
¹JINTR1_IC_SEC_DONE_Msk (0x1ul<<INTR1_IC_SEC_DONE_Pos)
ºJINTR1_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_Pos 1
»JINTR1_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_Msk (0x1ul<<INTR1_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_Pos)
¼JINTR1_IC_PHY_DRV_CFG_DONE_Pos 0
½JINTR1_IC_PHY_DRV_CFG_DONE_Msk (0x1ul<<INTR1_IC_PHY_DRV_CFG_DONE_Pos)
¿JINTCLR_IC_RNG_DONE_CLR_Pos 3
ÀJINTCLR_IC_RNG_DONE_CLR_Msk (0x1ul<<INTCLR_IC_RNG_DONE_CLR_Pos)
ÁJINTCLR_IC_SEC_DONE_CLR_Pos 2
ÂJINTCLR_IC_SEC_DONE_CLR_Msk (0x1ul<<INTCLR_IC_SEC_DONE_CLR_Pos)
ÃJINTCLR_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_CLR_Pos 1
ÄJINTCLR_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_CLR_Msk (0x1ul<<INTCLR_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_CLR_Pos)
ÅJINTCLR_IC_PHY_DRV_CFG_DONE_CLR_Pos 0
ÆJINTCLR_IC_PHY_DRV_CFG_DONE_CLR_Msk (0x1ul<<INTCLR_IC_PHY_DRV_CFG_DONE_CLR_Pos)
ÈJINTMSK_IC_RNG_DONE_MASK_Pos 3
ÉJINTMSK_IC_RNG_DONE_MASK_Msk (0x1ul<<INTMSK_IC_RNG_DONE_MASK_Pos)
ÊJINTMSK_IC_SEC_DONE_MASK_Pos 2
ËJINTMSK_IC_SEC_DONE_MASK_Msk (0x1ul<<INTMSK_IC_SEC_DONE_MASK_Pos)
ÌJINTMSK_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_MASK_Pos 1
ÍJINTMSK_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_MASK_Msk (0x1ul<<INTMSK_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_MASK_Pos)
ÎJINTMSK_IC_PHY_DRV_CFG_DONE_MASK_Pos 0
ÏJINTMSK_IC_PHY_DRV_CFG_DONE_MASK_Msk (0x1ul<<INTMSK_IC_PHY_DRV_CFG_DONE_MASK_Pos)
ÑJINTR4_IC_CLR_IRQ_Pos 6
ÒJINTR4_IC_CLR_IRQ_Msk (0x1ul<<INTR4_IC_CLR_IRQ_Pos)
ÓJINTR4_IC_ONE_PULSE_FLAG_IRQ_Pos 5
ÔJINTR4_IC_ONE_PULSE_FLAG_IRQ_Msk (0x1ul<<INTR4_IC_ONE_PULSE_FLAG_IRQ_Pos)
ÕJINTR4_IC_MODE_IRQ_Pos 4
ÖJINTR4_IC_MODE_IRQ_Msk (0x1ul<<INTR4_IC_MODE_IRQ_Pos)
×JINTR4_IC_PULSE_CNT_Pos 0
ØJINTR4_IC_PULSE_CNT_Msk (0xful<<INTR4_IC_PULSE_CNT_Pos)
ÚJACTTMR1_ACTTMR_CMPR_MAX_EVENT_DIN_Pos 0
ÛJACTTMR1_ACTTMR_CMPR_MAX_EVENT_DIN_Msk (0xfffffffful<<ACTTMR1_ACTTMR_CMPR_MAX_EVENT_DIN_Pos)
ÝJACTTMR2_ACTTMR_DISABLE_FLG_Pos 2
ÞJACTTMR2_ACTTMR_DISABLE_FLG_Msk (0x1ul<<ACTTMR2_ACTTMR_DISABLE_FLG_Pos)
ßJACTTMR2_ACT_CLK_ACCUR_FLG_Pos 1
àJACTTMR2_ACT_CLK_ACCUR_FLG_Msk (0x1ul<<ACTTMR2_ACT_CLK_ACCUR_FLG_Pos)
áJACTTMR2_ACTTMR_CMPR_MAX_EVENT_EN_Pos 0
âJACTTMR2_ACTTMR_CMPR_MAX_EVENT_EN_Msk (0x1ul<<ACTTMR2_ACTTMR_CMPR_MAX_EVENT_EN_Pos)
äJACTTMR6_ACTTMR_CMPR_STRT_EVENT_DIN_Pos 0
åJACTTMR6_ACTTMR_CMPR_STRT_EVENT_DIN_Msk (0xfffffffful<<ACTTMR6_ACTTMR_CMPR_STRT_EVENT_DIN_Pos)
çJACTTMR7_ACTTMR_CPTUR_BUS_DOUT_Pos 0
èJACTTMR7_ACTTMR_CPTUR_BUS_DOUT_Msk (0xfffffffful<<ACTTMR7_ACTTMR_CPTUR_BUS_DOUT_Pos)
êJSECURE1_SEC_DECRYPT_EN_Pos 26
ëJSECURE1_SEC_DECRYPT_EN_Msk (0x1ul<<SECURE1_SEC_DECRYPT_EN_Pos)
ìJSECURE1_SEC_AD_LEN_Pos 19
íJSECURE1_SEC_AD_LEN_Msk (0x7ful<<SECURE1_SEC_AD_LEN_Pos)
îJSECURE1_SEC_MIC_LEN_Pos 17
ïJSECURE1_SEC_MIC_LEN_Msk (0x3ul<<SECURE1_SEC_MIC_LEN_Pos)
ðJSECURE1_SEC_VLD_MAC_Pos 10
ñJSECURE1_SEC_VLD_MAC_Msk (0x7ful<<SECURE1_SEC_VLD_MAC_Pos)
òJSECURE1_SEC_PKT_ENABLES_Pos 3
óJSECURE1_SEC_PKT_ENABLES_Msk (0x7ful<<SECURE1_SEC_PKT_ENABLES_Pos)
ôJSECURE1_SEC_MODE_Pos 1
õJSECURE1_SEC_MODE_Msk (0x3ul<<SECURE1_SEC_MODE_Pos)
öJSECURE1_SEC_ENABLE_Pos 0
÷JSECURE1_SEC_ENABLE_Msk (0x1ul<<SECURE1_SEC_ENABLE_Pos)
ùJSECURE2_SEC_IV3_Pos 24
úJSECURE2_SEC_IV3_Msk (0xfful<<SECURE2_SEC_IV3_Pos)
ûJSECURE2_SEC_IV2_Pos 16
üJSECURE2_SEC_IV2_Msk (0xfful<<SECURE2_SEC_IV2_Pos)
ýJSECURE2_SEC_IV1_Pos 8
þJSECURE2_SEC_IV1_Msk (0xfful<<SECURE2_SEC_IV1_Pos)
ÿJSECURE2_SEC_IV0_Pos 0
€KSECURE2_SEC_IV0_Msk (0xfful<<SECURE2_SEC_IV0_Pos)
‚KSECURE3_SEC_IV7_Pos 24
ƒKSECURE3_SEC_IV7_Msk (0xfful<<SECURE3_SEC_IV7_Pos)
„KSECURE3_SEC_IV6_Pos 16
…KSECURE3_SEC_IV6_Msk (0xfful<<SECURE3_SEC_IV6_Pos)
†KSECURE3_SEC_IV5_Pos 8
‡KSECURE3_SEC_IV5_Msk (0xfful<<SECURE3_SEC_IV5_Pos)
ˆKSECURE3_SEC_IV4_Pos 0
‰KSECURE3_SEC_IV4_Msk (0xfful<<SECURE3_SEC_IV4_Pos)
‹KSECURE4_SEC_KEY2_RX_ADDR_Pos 16
ŒKSECURE4_SEC_KEY2_RX_ADDR_Msk (0xfffful<<SECURE4_SEC_KEY2_RX_ADDR_Pos)
KSECURE4_SEC_KEY1_RX_ADDR_Pos 0
ŽKSECURE4_SEC_KEY1_RX_ADDR_Msk (0xfffful<<SECURE4_SEC_KEY1_RX_ADDR_Pos)
KSECURE5_SEC_KEY4_RX_ADDR_Pos 16
‘KSECURE5_SEC_KEY4_RX_ADDR_Msk (0xfffful<<SECURE5_SEC_KEY4_RX_ADDR_Pos)
’KSECURE5_SEC_KEY3_RX_ADDR_Pos 0
“KSECURE5_SEC_KEY3_RX_ADDR_Msk (0xfffful<<SECURE5_SEC_KEY3_RX_ADDR_Pos)
•KSECURE6_SEC_KEY6_RX_ADDR_Pos 16
–KSECURE6_SEC_KEY6_RX_ADDR_Msk (0xfffful<<SECURE6_SEC_KEY6_RX_ADDR_Pos)
—KSECURE6_SEC_KEY5_RX_ADDR_Pos 0
˜KSECURE6_SEC_KEY5_RX_ADDR_Msk (0xfffful<<SECURE6_SEC_KEY5_RX_ADDR_Pos)
šKSECURE7_SEC_MD_LEN_Pos 24
›KSECURE7_SEC_MD_LEN_Msk (0x7ful<<SECURE7_SEC_MD_LEN_Pos)
œKSECURE7_SEC_KEY7_RX_ADDR_Pos 8
KSECURE7_SEC_KEY7_RX_ADDR_Msk (0xfffful<<SECURE7_SEC_KEY7_RX_ADDR_Pos)
žKSECURE7_SEC_PKT_CNT_TX_MSB_Pos 0
ŸKSECURE7_SEC_PKT_CNT_TX_MSB_Msk (0xfful<<SECURE7_SEC_PKT_CNT_TX_MSB_Pos)
¡KSECURE8_SEC_PKT_CNT_TX_LSB_Pos 0
¢KSECURE8_SEC_PKT_CNT_TX_LSB_Msk (0xfffffffful<<SECURE8_SEC_PKT_CNT_TX_LSB_Pos)
¤KSECURE9_SEC_PKT_CNT_RX_MSB_Pos 0
¥KSECURE9_SEC_PKT_CNT_RX_MSB_Msk (0xfful<<SECURE9_SEC_PKT_CNT_RX_MSB_Pos)
§KSECURE10_SEC_PKT_CNT_RX_LSB_Pos 0
¨KSECURE10_SEC_PKT_CNT_RX_LSB_Msk (0xfffffffful<<SECURE10_SEC_PKT_CNT_RX_LSB_Pos)
ªKTEST_MUX00_TST_MUX_SELECT_03_Pos 18
«KTEST_MUX00_TST_MUX_SELECT_03_Msk (0x3ful<<TEST_MUX00_TST_MUX_SELECT_03_Pos)
¬KTEST_MUX00_TST_MUX_SELECT_02_Pos 12
­KTEST_MUX00_TST_MUX_SELECT_02_Msk (0x3ful<<TEST_MUX00_TST_MUX_SELECT_02_Pos)
®KTEST_MUX00_TST_MUX_SELECT_01_Pos 6
¯KTEST_MUX00_TST_MUX_SELECT_01_Msk (0x3ful<<TEST_MUX00_TST_MUX_SELECT_01_Pos)
°KTEST_MUX00_TST_MUX_SELECT_00_Pos 0
±KTEST_MUX00_TST_MUX_SELECT_00_Msk (0x3ful<<TEST_MUX00_TST_MUX_SELECT_00_Pos)
³KRNG1_RNG_RING_SCRMB_SEL_Pos 1
´KRNG1_RNG_RING_SCRMB_SEL_Msk (0x1ul<<RNG1_RNG_RING_SCRMB_SEL_Pos)
µKRNG1_RNG_EN_Pos 0
¶KRNG1_RNG_EN_Msk (0x1ul<<RNG1_RNG_EN_Pos)
¸KRNG2_RNG_DATA_Pos 0
¹KRNG2_RNG_DATA_Msk (0xfffffffful<<RNG2_RNG_DATA_Pos)
»KLL_MAC_CTRL_CTRL_LL_EN_Pos 0
¼KLL_MAC_CTRL_CTRL_LL_EN_Msk (0x1ul<<LL_MAC_CTRL_CTRL_LL_EN_Pos)
¾KTEST_MUX01_TST_MUX_SELECT_07_Pos 18
¿KTEST_MUX01_TST_MUX_SELECT_07_Msk (0x3ful<<TEST_MUX01_TST_MUX_SELECT_07_Pos)
ÀKTEST_MUX01_TST_MUX_SELECT_06_Pos 12
ÁKTEST_MUX01_TST_MUX_SELECT_06_Msk (0x3ful<<TEST_MUX01_TST_MUX_SELECT_06_Pos)
ÂKTEST_MUX01_TST_MUX_SELECT_05_Pos 6
ÃKTEST_MUX01_TST_MUX_SELECT_05_Msk (0x3ful<<TEST_MUX01_TST_MUX_SELECT_05_Pos)
ÄKTEST_MUX01_TST_MUX_SELECT_04_Pos 0
ÅKTEST_MUX01_TST_MUX_SELECT_04_Msk (0x3ful<<TEST_MUX01_TST_MUX_SELECT_04_Pos)
ÇKTEST_MUX02_TST_MUX_SELECT_11_Pos 18
ÈKTEST_MUX02_TST_MUX_SELECT_11_Msk (0x3ful<<TEST_MUX02_TST_MUX_SELECT_11_Pos)
ÉKTEST_MUX02_TST_MUX_SELECT_10_Pos 12
ÊKTEST_MUX02_TST_MUX_SELECT_10_Msk (0x3ful<<TEST_MUX02_TST_MUX_SELECT_10_Pos)
ËKTEST_MUX02_TST_MUX_SELECT_09_Pos 6
ÌKTEST_MUX02_TST_MUX_SELECT_09_Msk (0x3ful<<TEST_MUX02_TST_MUX_SELECT_09_Pos)
ÍKTEST_MUX02_TST_MUX_SELECT_08_Pos 0
ÎKTEST_MUX02_TST_MUX_SELECT_08_Msk (0x3ful<<TEST_MUX02_TST_MUX_SELECT_08_Pos)
ÐKTEST_MUX03_TST_MUX_SELECT_15_Pos 18
ÑKTEST_MUX03_TST_MUX_SELECT_15_Msk (0x3ful<<TEST_MUX03_TST_MUX_SELECT_15_Pos)
ÒKTEST_MUX03_TST_MUX_SELECT_14_Pos 12
ÓKTEST_MUX03_TST_MUX_SELECT_14_Msk (0x3ful<<TEST_MUX03_TST_MUX_SELECT_14_Pos)
ÔKTEST_MUX03_TST_MUX_SELECT_13_Pos 6
ÕKTEST_MUX03_TST_MUX_SELECT_13_Msk (0x3ful<<TEST_MUX03_TST_MUX_SELECT_13_Pos)
ÖKTEST_MUX03_TST_MUX_SELECT_12_Pos 0
×KTEST_MUX03_TST_MUX_SELECT_12_Msk (0x3ful<<TEST_MUX03_TST_MUX_SELECT_12_Pos)
ÚKR00_CTL_TX_PAYLOAD_LEN_Pos 24
ÛKR00_CTL_TX_PAYLOAD_LEN_Msk (0xFFul<<R00_CTL_TX_PAYLOAD_LEN_Pos)
ÜKR00_CTL_RX_PAYLOAD_LEN_Pos 16
ÝKR00_CTL_RX_PAYLOAD_LEN_Msk (0xFFul<<R00_CTL_RX_PAYLOAD_LEN_Pos)
ÞKR00_CTL_CRC_ACCESS_ADR_Pos 15
ßKR00_CTL_CRC_ACCESS_ADR_Msk (0x1ul<<R00_CTL_CRC_ACCESS_ADR_Pos)
àKR00_CTL_CRC24_EN_Pos 14
áKR00_CTL_CRC24_EN_Msk (0x1ul<<R00_CTL_CRC24_EN_Pos)
âKR00_CTL_ADDR_BYTE_LEN_Pos 12
ãKR00_CTL_ADDR_BYTE_LEN_Msk (0x3ul<<R00_CTL_ADDR_BYTE_LEN_Pos)
äKR00_CTL_DPY_EN_Pos 11
åKR00_CTL_DPY_EN_Msk (0x1ul<<R00_CTL_DPY_EN_Pos)
æKR00_CTL_CRC_EN_Pos 10
çKR00_CTL_CRC_EN_Msk (0x1ul<<R00_CTL_CRC_EN_Pos)
èKR00_CTL_CRC_SEL16_Pos 9
éKR00_CTL_CRC_SEL16_Msk (0x1ul<<R00_CTL_CRC_SEL16_Pos)
êKR00_CTL_SCR_EN_Pos 8
ëKR00_CTL_SCR_EN_Msk (0x1ul<<R00_CTL_SCR_EN_Pos)
ìKR00_CTL_NRF_ENHANCE_Pos 7
íKR00_CTL_NRF_ENHANCE_Msk (0x1ul<<R00_CTL_NRF_ENHANCE_Pos)
îKR00_CTL_ENHANCE_Pos 6
ïKR00_CTL_ENHANCE_Msk (0x1ul<<R00_CTL_ENHANCE_Pos)
ðKR00_CTL_BW_MODE_Pos 5
ñKR00_CTL_BW_MODE_Msk (0x1ul<<R00_CTL_BW_MODE_Pos)
òKR00_CTL_CHIP_MODE_Pos 3
óKR00_CTL_CHIP_MODE_Msk (0x3ul<<R00_CTL_CHIP_MODE_Pos)
ôKR00_CTL_RX_ACK_PAYLOAD_EN_Pos 2
õKR00_CTL_RX_ACK_PAYLOAD_EN_Msk (0x1ul<<R00_CTL_RX_ACK_PAYLOAD_EN_Pos)
öKR00_CTL_TX_NOACK_EN_Pos 1
÷KR00_CTL_TX_NOACK_EN_Msk (0x1ul<<R00_CTL_TX_NOACK_EN_Pos)
øKR00_CTL_PRI_RX_Pos 0
ùKR00_CTL_PRI_RX_Msk (0x1ul<<R00_CTL_PRI_RX_Pos)
ûKR01_INT_PRI_RX_PID_Pos 29
üKR01_INT_PRI_RX_PID_Msk (0x3ul<<R01_INT_PRI_RX_PID_Pos)
ýKR01_INT_PRI_TX_PID_Pos 27
þKR01_INT_PRI_TX_PID_Msk (0x3ul<<R01_INT_PRI_TX_PID_Pos)
ÿKR01_INT_RX_LENGTH_ERR_Pos 26
€LR01_INT_RX_LENGTH_ERR_Msk (0x1ul<<R01_INT_RX_LENGTH_ERR_Pos)
LR01_INT_RX_ACCADDR_ERR_Pos 25
‚LR01_INT_RX_ACCADDR_ERR_Msk (0x1ul<<R01_INT_RX_ACCADDR_ERR_Pos)
ƒLR01_INT_RX_ACCADDR_ERR_MASK_Pos 23
„LR01_INT_RX_ACCADDR_ERR_MASK_Msk (0x1ul<<R01_INT_RX_ACCADDR_ERR_MASK_Pos)
…LR01_INT_RX_LENGTH_ERR_MASK_Pos 22
†LR01_INT_RX_LENGTH_ERR_MASK_Msk (0x1ul<<R01_INT_RX_LENGTH_ERR_MASK_Pos)
‡LR01_INT_PRI_ENDIAN_Pos 21
ˆLR01_INT_PRI_ENDIAN_Msk (0x1ul<<R01_INT_PRI_ENDIAN_Pos)
‰LR01_INT_PRI_TX_DONE_IRQ_EN_Pos 20
ŠLR01_INT_PRI_TX_DONE_IRQ_EN_Msk (0x1ul<<R01_INT_PRI_TX_DONE_IRQ_EN_Pos)
‹LR01_INT_PRI_RX_DONE_IRQ_EN_Pos 19
ŒLR01_INT_PRI_RX_DONE_IRQ_EN_Msk (0x1ul<<R01_INT_PRI_RX_DONE_IRQ_EN_Pos)
LR01_INT_PRI_RX_GOON_Pos 18
ŽLR01_INT_PRI_RX_GOON_Msk (0x1ul<<R01_INT_PRI_RX_GOON_Pos)
LR01_INT_PRI_RST_Pos 17
LR01_INT_PRI_RST_Msk (0x1ul<<R01_INT_PRI_RST_Pos)
‘LR01_INT_EXIT_RX_Pos 16
’LR01_INT_EXIT_RX_Msk (0x1ul<<R01_INT_EXIT_RX_Pos)
“LR01_INT_TX_DONE_IRQ_FLAG_Pos 15
”LR01_INT_TX_DONE_IRQ_FLAG_Msk (0x1ul<<R01_INT_TX_DONE_IRQ_FLAG_Pos)
•LR01_INT_RX_DONE_IRQ_FLAG_Pos 14
–LR01_INT_RX_DONE_IRQ_FLAG_Msk (0x1ul<<R01_INT_RX_DONE_IRQ_FLAG_Pos)
—LR01_INT_RX_PID_ERR_IRQ_FLAG_Pos 13
˜LR01_INT_RX_PID_ERR_IRQ_FLAG_Msk (0x1ul<<R01_INT_RX_PID_ERR_IRQ_FLAG_Pos)
™LR01_INT_RX_CRC_ERR_Pos 12
šLR01_INT_RX_CRC_ERR_Msk (0x1ul<<R01_INT_RX_CRC_ERR_Pos)
›LR01_INT_TX_TIMEOUT_IRQ_Pos 11
œLR01_INT_TX_TIMEOUT_IRQ_Msk (0x1ul<<R01_INT_TX_TIMEOUT_IRQ_Pos)
LR01_INT_TX_IRQ_Pos 10
žLR01_INT_TX_IRQ_Msk (0x1ul<<R01_INT_TX_IRQ_Pos)
ŸLR01_INT_RX_IRQ_Pos 9
 LR01_INT_RX_IRQ_Msk (0x1ul<<R01_INT_RX_IRQ_Pos)
¡LR01_INT_IRQ_CLR_EN_Pos 8
¢LR01_INT_IRQ_CLR_EN_Msk (0x1ul<<R01_INT_IRQ_CLR_EN_Pos)
£LR01_INT_RX_CRC_ERR_MASK_Pos 7
¤LR01_INT_RX_CRC_ERR_MASK_Msk (0x1ul<<R01_INT_RX_CRC_ERR_MASK_Pos)
¥LR01_INT_PID_ERR_MASK_Pos 6
¦LR01_INT_PID_ERR_MASK_Msk (0x1ul<<R01_INT_PID_ERR_MASK_Pos)
§LR01_INT_TX_TIMEOUT_IRQ_MASK_Pos 5
¨LR01_INT_TX_TIMEOUT_IRQ_MASK_Msk (0x1ul<<R01_INT_TX_TIMEOUT_IRQ_MASK_Pos)
©LR01_INT_TX_IRQ_MASK_Pos 4
ªLR01_INT_TX_IRQ_MASK_Msk (0x1ul<<R01_INT_TX_IRQ_MASK_Pos)
«LR01_INT_RX_IRQ_MASK_Pos 3
¬LR01_INT_RX_IRQ_MASK_Msk (0x1ul<<R01_INT_RX_IRQ_MASK_Pos)
­LR01_INT_MULTI_RX_ACC_ADR_Pos 0
®LR01_INT_MULTI_RX_ACC_ADR_Msk (0x7ul<<R01_INT_MULTI_RX_ACC_ADR_Pos)
±LR02_TMR_CTL_RX_WAIT_TIME_Pos 16
²LR02_TMR_CTL_RX_WAIT_TIME_Msk (0xFFFFul<<R02_TMR_CTL_RX_WAIT_TIME_Pos)
³LR02_TMR_CTL_RX_WAIT_TIME_EN_Pos 15
´LR02_TMR_CTL_RX_WAIT_TIME_EN_Msk (0X1ul<<R02_TMR_CTL_RX_WAIT_TIME_EN_Pos)
µLR02_TMR_CTL_TRX_TRANS_WAIT_TIME_Pos 0
¶LR02_TMR_CTL_TRX_TRANS_WAIT_TIME_Msk (0x7FFFul<<R02_TMR_CTL_TRX_TRANS_WAIT_TIME_Pos)
¸LR03_RX_ADDR_L_L32B_Pos 0
¹LR03_RX_ADDR_L_L32B_Msk (0xFFFFFFFFul<<R03_RX_ADDR_L_L32B_Pos)
½LR04_RX_CTL_RX_HEADER1_Pos 24
¾LR04_RX_CTL_RX_HEADER1_Msk (0xFFul<<R04_RX_CTL_RX_HEADER1_Pos)
¿LR04_RX_CTL_RX_HEADER_Pos 16
ÀLR04_RX_CTL_RX_HEADER_Msk (0xFFul<<R04_RX_CTL_RX_HEADER_Pos)
ÁLR04_RX_CTL_RX_FEC_Pos 15
ÂLR04_RX_CTL_RX_FEC_Msk (0x1ul<<R04_RX_CTL_RX_FEC_Pos)
ÃLR04_RX_CTL_TX_FEC_Pos 14
ÄLR04_RX_CTL_TX_FEC_Msk (0x1ul<<R04_RX_CTL_TX_FEC_Pos)
ÅLR04_RX_CTL_CI_MODE_Pos 12
ÆLR04_RX_CTL_CI_MODE_Msk (0x3ul<<R04_RX_CTL_CI_MODE_Pos)
ÇLR04_RX_CTL_NORMAL_M1_Pos 11
ÈLR04_RX_CTL_NORMAL_M1_Msk (0x1ul<<R04_RX_CTL_NORMAL_M1_Pos)
ÉLR04_RX_CTL_HDR_LEN_NUMB_Pos 9
ÊLR04_RX_CTL_HDR_LEN_NUMB_Msk (0x3ul<<R04_RX_CTL_HDR_LEN_NUMB_Pos)
ËLR04_RX_CTL_HDR_LEN_EXIST_Pos 8
ÌLR04_RX_CTL_HDR_LEN_EXIST_Msk (0x1ul<<R04_RX_CTL_HDR_LEN_EXIST_Pos)
ÍLR04_RX_CTL_M8B_Pos 0
ÎLR04_RX_CTL_M8B_Msk (0xFFul<<R04_RX_CTL_M8B_Pos)
ÐLR05_TX_ADDR_L_L32B_Pos 0
ÑLR05_TX_ADDR_L_L32B_Msk (0xFFFFFFFFul<<R05_TX_ADDR_L_L32B_Pos)
ÓLR06_TX_CTL_RX_HEADER1_Pos 24
ÔLR06_TX_CTL_RX_HEADER1_Msk (0xFFul<<R06_TX_CTL_RX_HEADER1_Pos)
ÕLR06_TX_CTL_RX_HEADER_Pos 16
ÖLR06_TX_CTL_RX_HEADER_Msk (0xFFul<<R06_TX_CTL_RX_HEADER_Pos)
×LR06_TX_CTL_MAX_LENGTH_EN_Pos 15
ØLR06_TX_CTL_MAX_LENGTH_EN_Msk (0x1ul<<R06_TX_CTL_MAX_LENGTH_EN_Pos)
ÙLR06_TX_CTL_WHITENING_INIT_Pos 8
ÚLR06_TX_CTL_WHITENING_INIT_Msk (0x7Ful<<R06_TX_CTL_WHITENING_INIT_Pos)
ÛLR06_TX_CTL_M8B_Pos 0
ÜLR06_TX_CTL_M8B_Msk (0xFFul<<R06_TX_CTL_M8B_Pos)
ÞLR07_SRAM_CTL_RX_START_ADDR_Pos 17
ßLR07_SRAM_CTL_RX_START_ADDR_Msk (0x7FFul<<R07_SRAM_CTL_RX_START_ADDR_Pos)
àLR07_SRAM_CTL_RX_READY_Pos 16
áLR07_SRAM_CTL_RX_READY_Msk (0x1ul<<R07_SRAM_CTL_RX_READY_Pos)
âLR07_SRAM_CTL_TX_START_ADDR_Pos 1
ãLR07_SRAM_CTL_TX_START_ADDR_Msk (0x7FFul<<R07_SRAM_CTL_TX_START_ADDR_Pos)
äLR07_SRAM_CTL_TX_READY_Pos 0
åLR07_SRAM_CTL_TX_READY_Msk (0x1<<R07_SRAM_CTL_TX_READY_Pos)
èLR0F_RX_ADDR4_M8B_Pos 24
éLR0F_RX_ADDR4_M8B_Msk (0xFFul<<R0F_RX_ADDR4_M8B_Pos)
êLR0F_RX_ADDR3_M8B_Pos 16
ëLR0F_RX_ADDR3_M8B_Msk (0xFFul<<R0F_RX_ADDR3_M8B_Pos)
ìLR0F_RX_ADDR2_M8B_Pos 8
íLR0F_RX_ADDR2_M8B_Msk (0xFFul<<R0F_RX_ADDR2_M8B_Pos)
îLR0F_RX_ADDR1_M8B_Pos 0
ïLR0F_RX_ADDR1_M8B_Msk (0xFFul<<R0F_RX_ADDR1_M8B_Pos)
òLR10_RX_ADDR7_EN_Pos 31
óLR10_RX_ADDR7_EN_Msk (0x1ul<<R0F_RX_ADDR7_EN_Pos)
ôLR10_RX_ADDR6_EN_Pos 30
õLR10_RX_ADDR6_EN_Msk (0x1ul<<R0F_RX_ADDR6_EN_Pos)
öLR10_RX_ADDR5_EN_Pos 29
÷LR10_RX_ADDR5_EN_Msk (0x1ul<<R0F_RX_ADDR5_EN_Pos)
øLR10_RX_ADDR4_EN_Pos 28
ùLR10_RX_ADDR4_EN_Msk (0x1ul<<R0F_RX_ADDR4_EN_Pos)
úLR10_RX_ADDR3_EN_Pos 27
ûLR10_RX_ADDR3_EN_Msk (0x1ul<<R0F_RX_ADDR3_EN_Pos)
üLR10_RX_ADDR2_EN_Pos 26
ýLR10_RX_ADDR2_EN_Msk (0x1ul<<R0F_RX_ADDR2_EN_Pos)
þLR10_RX_ADDR1_EN_Pos 25
ÿLR10_RX_ADDR1_EN_Msk (0x1ul<<R0F_RX_ADDR1_EN_Pos)
€MR10_RX_ADDR0_EN_Pos 24
MR10_RX_ADDR0_EN_Msk (0x1ul<<R0F_RX_ADDR0_EN_Pos)
‚MR10_RX_ADDR7_M8B_Pos 16
ƒMR10_RX_ADDR7_M8B_Msk (0xFFul<<R0F_RX_ADDR3_M8B_Pos)
„MR10_RX_ADDR6_M8B_Pos 8
…MR10_RX_ADDR6_M8B_Msk (0xFFul<<R0F_RX_ADDR2_M8B_Pos)
†MR10_RX_ADDR5_M8B_Pos 0
‡MR10_RX_ADDR5_M8B_Msk (0xFFul<<R0F_RX_ADDR1_M8B_Pos)
‹MR11_CFG_NRF_PRE_SEL_Pos 25
ŒMR11_CFG_NRF_PRE_SEL_Msk (0x1ul<<R11_CFG_NRF_PRE_SEL_Pos)
MR11_CFG_RX_DATA_REV_EN_Pos 24
ŽMR11_CFG_RX_DATA_REV_EN_Msk (0x1ul<<R11_CFG_RX_DATA_REV_EN_Pos)
MR11_CFG_PRE_SYNC_12B_EN_Pos 23
MR11_CFG_PRE_SYNC_12B_EN_Msk (0x1ul<<R11_CFG_PRE_SYNC_12B_EN_Pos)
‘MR11_CFG_PRE_SYNC_8B_EN_Pos 22
’MR11_CFG_PRE_SYNC_8B_EN_Msk (0x1ul<<R11_CFG_PRE_SYNC_8B_EN_Pos)
“MR11_CFG_PRE_SYNC_4B_EN_Pos 21
”MR11_CFG_PRE_SYNC_4B_EN_Msk (0x1ul<<R11_CFG_PRE_SYNC_4B_EN_Pos)
•MR11_CFG_PRE_SYNC_EN_Pos 20
–MR11_CFG_PRE_SYNC_EN_Msk (0x1ul<<R11_CFG_PRE_SYNC_EN_Pos)
—MR11_CFG_250K_MODE_EN_Pos 19
˜MR11_CFG_250K_MODE_EN_Msk (0x1ul<<R11_CFG_250K_MODE_EN_Pos)
™MR11_CFG_B250K_PRE_SEL_Pos 18
šMR11_CFG_B250K_PRE_SEL_Msk (0x1ul<<R11_CFG_B250K_PRE_SEL_Pos)
›MR11_CFG_LQI_EN_Pos 17
œMR11_CFG_LQI_EN_Msk (0x1ul<<R11_CFG_LQI_EN_Pos)
MR11_CFG_RX_PID_MANUAL_Pos 15
žMR11_CFG_RX_PID_MANUAL_Msk (0x3ul<<R11_CFG_RX_PID_MANUAL_Pos)
ŸMR11_CFG_TX_PID_MANUAL_Pos 13
 MR11_CFG_TX_PID_MANUAL_Msk (0x3ul<<R11_CFG_TX_PID_MANUAL_Pos)
¡MR11_CFG_PREAM_2BYTE_EN_Pos 12
¢MR11_CFG_PREAM_2BYTE_EN_Msk (0x1ul<<R11_CFG_PREAM_2BYTE_EN_Pos)
£MR11_CFG_B250K_INVERT_EN_Pos 11
¤MR11_CFG_B250K_INVERT_EN_Msk (0x1ul<<R11_CFG_B250K_INVERT_EN_Pos)
¥MR11_CFG_B250K_SCR_INIT_VALUE_Pos 9
¦MR11_CFG_B250K_SCR_INIT_VALUE_Msk (0x3ul<<R11_CFG_B250K_SCR_INIT_VALUE_Pos)
§MR11_CFG_B250K_PREAM_Pos 6
¨MR11_CFG_B250K_PREAM_Msk (0x7ul<<R11_CFG_B250K_PREAM_Pos)
©MR11_CFG_B250K_MODE_Pos 5
ªMR11_CFG_B250K_MODE_Msk (0x1ul<<R11_CFG_B250K_MODE_Pos)
«MR11_CFG_ADDR_ERR_THR_Pos 2
¬MR11_CFG_ADDR_ERR_THR_Msk (0x7ul<<R11_CFG_ADDR_ERR_THR_Pos)
­MR11_CFG_PID_MANUAL_EN_Pos 1
®MR11_CFG_PID_MANUAL_EN_Msk (0x1ul<<R11_CFG_PID_MANUAL_EN_Pos)
¯MR11_CFG_ADDR_SCR_DIS_Pos 0
°MR11_CFG_ADDR_SCR_DIS_Msk (0x1ul<<R11_CFG_ADDR_SCR_DIS_Pos)
ºMCR_BASE (0x00400000Ul)
»MSRAM_BASE (0x20000000UL)
½MAHB1_PERIPH_BASE (0x40000000UL)
ÀMAPB1_PERIPH_BASE (0x40000000UL)
ÁMAPB2_PERIPH_BASE (0x40010000UL)
ÃMBLE_PERIPH_BASE (0x50020000UL)
ÈMI2C0_BASE (APB1_PERIPH_BASE + 0x00000000UL)
ÉMSPI0_BASE (APB1_PERIPH_BASE + 0x00001000UL)
ÊMUART0_BASE (APB1_PERIPH_BASE + 0x00003000UL)
ËMPWM_BASE (APB1_PERIPH_BASE + 0x00004000UL)
ÌMADC_BASE (APB1_PERIPH_BASE + 0x00005000UL)
ÍMWDT_BASE (APB1_PERIPH_BASE + 0x00006000UL)
ÎMWWDT_BASE (APB1_PERIPH_BASE + 0x00007000UL)
ÏMTIMER0_BASE (APB1_PERIPH_BASE + 0x00008000UL)
ÓMSPI1_BASE (APB2_PERIPH_BASE + 0x00001000UL)
ÔMUART1_BASE (APB2_PERIPH_BASE + 0x00003000UL)
ÕMTIMER1_BASE (APB2_PERIPH_BASE + 0x00004000UL)
ÖMTIMER2_BASE (APB2_PERIPH_BASE + 0x00005000UL)
×MTRIM_BASE (APB2_PERIPH_BASE + 0x00006000UL)
ÜMGPIO_BASE (AHB1_PERIPH_BASE + 0x00020000UL)
ÝMP0_BASE (GPIO_BASE + 0x00000000UL)
ÞMP1_BASE (GPIO_BASE + 0x00000040UL)
ßMP2_BASE (GPIO_BASE + 0x00000080UL)
àMP3_BASE (GPIO_BASE + 0x000000C0UL)
áMGPIO_DBNCECON_BASE (GPIO_BASE + 0x00000180UL)
âMGPIOBIT0_BASE (GPIO_BASE + 0x00000200UL)
ãMGPIOBIT1_BASE (GPIO_BASE + 0x00000220UL)
äMGPIOBIT2_BASE (GPIO_BASE + 0x00000240UL)
åMGPIOBIT3_BASE (GPIO_BASE + 0x00000260UL)
çMSYS_BASE (AHB1_PERIPH_BASE + 0x00030000UL)
èMCLK_BASE (AHB1_PERIPH_BASE + 0x00040000UL)
éMFLCTL_BASE (AHB1_PERIPH_BASE + 0x00050000UL)
êMFLCTL_BASE1 (AHB1_PERIPH_BASE + 0x00050400UL)
ëMDMA_BASE (AHB1_PERIPH_BASE + 0x00060000UL)
ìMANA_BASE (AHB1_PERIPH_BASE + 0x00070000UL)
íMEFUSE_BASE (AHB1_PERIPH_BASE + 0x00080000UL)
îMUSB_BASE (AHB1_PERIPH_BASE + 0x000A0000UL)
ïMUSBDMA_BASE (AHB1_PERIPH_BASE + 0x000A0200UL)
òMPRI_RF_BASE (BLE_PERIPH_BASE + 0X00000400UL)
öMCR ((CR_T *) CR_BASE)
ùMI2C0 ((I2C_T *) I2C0_BASE )
úMSPI0 ((SPI_T *) SPI0_BASE )
ûMUART0 ((UART_T *) UART0_BASE )
üMPWM ((PWM_T *) PWM_BASE )
ýMADC ((ADC_T *) ADC_BASE )
þMWDT ((WDT_T *) WDT_BASE )
ÿMWWDT ((WWDT_T *) WWDT_BASE )
€NTIMER0 ((TIMER_T *) TIMER0_BASE )
„NSPI1 ((SPI_T *) SPI1_BASE )
…NUART1 ((UART_T *) UART1_BASE )
†NTIMER1 ((TIMER_T *) TIMER1_BASE )
‡NTIMER2 ((TIMER_T *) TIMER2_BASE )
ˆNTRIM ((TRIM_T *) TRIM_BASE )
‹NGPIO ((GPIO_T *) GPIO_BASE )
ŒNP0 ((GPIO_T *) P0_BASE )
NP1 ((GPIO_T *) P1_BASE )
ŽNP2 ((GPIO_T *) P2_BASE )
NP3 ((GPIO_T *) P3_BASE )
NGPIO_DB ((GPIO_DB_T *) GPIO_DBNCECON_BASE)
’NSYS ((SYS_T *) SYS_BASE )
“NCLK ((CLK_T *) CLK_BASE )
”NFLCTL ((FLCTL_T *) FLCTL_BASE )
•NFLCTL_BUFF ((FLCTL_W_BUFF_T *)FLCTL_BASE1 )
–NDMA ((DMA_T *) DMA_BASE )
—NANA ((ANA_T *) ANA_BASE )
˜NEFUSE ((EFUSE_T *) EFUSE_BASE )
™NUSB ((USB_T *) USB_BASE )
šNUSBDMA ((USBDMA_T *) USBDMA_BASE )
NPRI_RF ((PRI_RF_T *) PRI_RF_BASE )
¶NTRUE (1)
ºNFALSE (0)
¾NBIT0 (0x00000001UL)
¿NBIT1 (0x00000002UL)
ÀNBIT2 (0x00000004UL)
ÁNBIT3 (0x00000008UL)
ÂNBIT4 (0x00000010UL)
ÃNBIT5 (0x00000020UL)
ÄNBIT6 (0x00000040UL)
ÅNBIT7 (0x00000080UL)
ÆNBIT8 (0x00000100UL)
ÇNBIT9 (0x00000200UL)
ÈNBIT10 (0x00000400UL)
ÉNBIT11 (0x00000800UL)
ÊNBIT12 (0x00001000UL)
ËNBIT13 (0x00002000UL)
ÌNBIT14 (0x00004000UL)
ÍNBIT15 (0x00008000UL)
ÎNBIT16 (0x00010000UL)
ÏNBIT17 (0x00020000UL)
ÐNBIT18 (0x00040000UL)
ÑNBIT19 (0x00080000UL)
ÒNBIT20 (0x00100000UL)
ÓNBIT21 (0x00200000UL)
ÔNBIT22 (0x00400000UL)
ÕNBIT23 (0x00800000UL)
ÖNBIT24 (0x01000000UL)
×NBIT25 (0x02000000UL)
ØNBIT26 (0x04000000UL)
ÙNBIT27 (0x08000000UL)
ÚNBIT28 (0x10000000UL)
ÛNBIT29 (0x20000000UL)
ÜNBIT30 (0x40000000UL)
ÝNBIT31 (0x80000000UL)
àNBIT(x) (0x1UL << (x))
äNBYTE0_Msk (0x000000FF)
åNBYTE1_Msk (0x0000FF00)
æNBYTE2_Msk (0x00FF0000)
çNBYTE3_Msk (0xFF000000)
éNGET_BYTE0(u32Param) ((u32Param & BYTE0_Msk) )
êNGET_BYTE1(u32Param) ((u32Param & BYTE1_Msk) >> 8)
ëNGET_BYTE2(u32Param) ((u32Param & BYTE2_Msk) >> 16)
ìNGET_BYTE3(u32Param) ((u32Param & BYTE3_Msk) >> 24)
ïNSET_BIT(REG,BIT) ((REG) |= (BIT))
ñNCLEAR_BIT(REG,BIT) ((REG) &= ~(BIT))
óNREAD_BIT(REG,BIT) ((REG) & (BIT))
õNCLEAR_REG(REG) ((REG) = (0x0))
÷NWRITE_REG(REG,VAL) ((REG) = (VAL))
ùNREAD_REG(REG) ((REG))
ûNMODIFY_REG(REG,CLEARMASK,SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
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OFREQ_RCL 32000
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..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\C:\Keil_v5\ARM\ARMCC\Bin\..\include\..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\radio\prf_lib\include\PanSeries.h
stdio.hstdlib.hstdint.hstring.hcore_cm0.hsystem_PanSeries.h
stdbool.hpan_sys_log.h
pan_sys.h
pan_clk.h
pan_adc.hpan_fmc.hpan_dmac.hpan_gpio.hpan_spi.hpan_uart.hpan_i2c.hpan_timer.hpan_pwm.hpan_wdt.hpan_wwdt.hpan_lp.h
pan_efuse.h
pan_pri_rf.hpan_clktrim.h
pan_power.h
pan_hal.h

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R00_CTLp#À
R01_INTp#Ä
R02_TMR_CTLp#È
R03_RX_ADDR_Lp#Ì
R04_RX_CTLp#Ð
R05_TX_ADDR_Lp#Ô
R06_TX_CTLp#Ø
R07_SRAM_CTLp#Ü
R08_RX_ADDR1_Lp#à
R09_RX_ADDR2_Lp#ä
R0A_RX_ADDR3_Lp#è
R0B_RX_ADDR4_Lp#ì
R0C_RX_ADDR5_Lp#ð
R0D_RX_ADDR6_Lp#ô
R0E_RX_ADDR7_Lp#ø
R0F_RX_ADDR_Hp#ü
R10_RX_ADDR_ENp#€R11_CFGp#„PPRI_RF_T
ÝI<Ò?
”O'NVIC_SystemReset





__PAN_PRI_RF_H__ 
 PRI_RF_MODE_SEL_TX (0)
!PRI_RF_MODE_SEL_RX (1)
"PRI_RF_MODE_SEL_TRX (2)
(PRI_RF_ADDR_BYTE_LEN_2 (0)
)PRI_RF_ADDR_BYTE_LEN_3 (1)
*PRI_RF_ADDR_BYTE_LEN_4 (2)
+PRI_RF_ADDR_BYTE_LEN_5 (3)
1PRI_RF_CHIP_MODE_INVALID (0)
2PRI_RF_CHIP_MODE_BLE (1)
3PRI_RF_CHIP_MODE_297 (2)
4PRI_RF_CHIP_MODE_NORDIC (3)
:REG_FILE_OFST 0x0000
;SEQ_RAM_OFST 0x1000
<LIST_RAM_OFST 0x8000
=TX_RX_RAM_OFST 0x8200
>CTE_IQ_RAM_OFST 0xB7FC
GLLHWC_READ32_REG(base_addr,reg_ofst) (*(volatile uint32_t *)((0x50020000) + (base_addr) + (reg_ofst)))
PLLHWC_WRITE32_REG(base_addr,reg_ofst,data) (*(volatile uint32_t *)(((0x50020000) + (base_addr) + (reg_ofst))) = (data))
XREAD_4_BYTES(pckt,pos) (((uint32_t) (pckt)[pos]) | (((uint32_t) (pckt)[pos + 1]) << 8) | (((uint32_t) (pckt)[pos + 2]) << 16) | (((uint32_t) (pckt)[pos + 3]) << 24))
ePRI_RF_WRITE_REG_VALUE(base,Reg,Func,Value) (base->Reg = (base->Reg & ~(Reg ## _ ## Func ## _Msk)) | ((Value << Reg ## _ ## Func ## _Pos) & Reg ## _ ## Func ## _Msk))
nPRI_RF_READ_REG_VALUE(base,Reg,Func) ((base->Reg & (Reg ## _ ## Func ## _Msk)) >> Reg ## _ ## Func ## _Pos)
xPRI_RF_SET_FUNC_ENABLE(base,Reg,Func,State) ((State == ENABLE) ? (base->Reg |= Reg ## _ ## Func ## _Msk) : (base->Reg &= ~Reg ## _ ## Func ## _Msk))ÐÇ
 




..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\radio\prf_lib\include\..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_pri_rf.h
PanSeries.h

d
..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\radio\prf_lib\include\pan_pri_rf.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x
_Bool;Ò
ÒPRI_RF_IntFlag
$·rf$Y
mska__result

<„
ÝPRI_RF_ForceExitRx$·rf$åNewState<º
èPRI_RF_SetTrxTransWaitTime$·rf$I
time<û
õPRI_RF_EnableRxPipeAdr$·rf$I
pipe$åNewState<ª
ÿPRI_RF_SetRxGoon$·rf$:
en_flag<Ý
„PRI_RF_SetAddrMatchBit$·rf$:
value<’
‰PRI_RF_SetPayloadEndian$·rf$:
endian<È
ŽPRI_RF_MultiPreamble$·rf$:
pre_length<ô
”PRI_RF_StopRx$·rf$:
en_flag<œ
™PRI_RF_RandomNumGenInit$·rf<Æ
žPRI_RF_RandomNumGenReinit$·rf;ÿ
£PRI_RF_GetRandomNumY
$·rfa__resultY

<·
€
PRI_RF_AutoAnlsPayloadEn$·rf$åNewState"§<î
‹
PRI_RF_CrcCheckEn$·rf$åNewState< 
–
PRI_RF_Crc16Select$·rf$åNewState<Ð
 
PRI_RF_ScambleEn$·rf$åNewState<†    
«
PRI_RF_NordicEnhanceEn$·rf$åNewState;    
´
PRI_RF_IsNordicEnhance:
$·rfa__result:

<ò    
¾
PRI_RF_EnhanceEn$·rf$åNewState;¨

Ç
PRI_RF_IsEnhance:
$·rfa__result:

<Ý

Ñ
PRI_RF_BandWidth2mSel$·rf$åNewState<Ž
à
PRI_RF_ChipModeSel$·rf$:
modeSel;Æ
é
PRI_RF_GetChipMode:
$·rfa__result:

<ô
ô
PRI_RF_RxAckEn$·rf$åNewState;ª
ý
PRI_RF_IsRxAckEn:
$·rfa__result:

<Ú
ˆPRI_RF_TxNoAckEn$·rf$åNewState;’ 
‘PRI_RF_IsTxNoAckEn:
$·rfa__result:

<Ã 
PRI_RF_TrxFuncSel$·rf$åNewState;÷ 
§PRI_RF_IsRxSel:
$·rfa__result:

<«
±PRI_RF_ClearAllIrqEn$·rf$åNewState<ã
ÂPRI_RF_IntMask$·rf$Y
msk$åNewState

    




 _PAN_CLKTRIM_H_ tk
 




..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_clktrim.h


4
..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_clktrim.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x
_Bool;Ö
KTRIM_IsIntStatusOccured    
$Àtrim$Y
mska__result    

<ˆ
bTRIM_ClearIntStatusMsk$Àtrim$Y
msk<·
mTRIM_EnableInt$Àtrim$åNewState<ð
xTRIM_SetRelationIncrease$Àtrim$åNewState<«
ƒ
TRIM_SetEarlyTerminatinEn$Àtrim$åNewState<Û

TRIM_SetCoarseCode$Àtrim$Y
code;•
š
TRIM_GetCoarseCodeY
$Àtrima__resultY

<Ã
¤
TRIM_SetFineCode$Àtrim$Y
code;û
­
TRIM_GetFineCodeY
$Àtrima__resultY

<ª
¸
TRIM_SetBitWidth$Àtrim$Y
width;â
¼
TRIM_GetBitWidthY
$Àtrima__resultY

<”
Ê
TRIM_StartTuning$Àtrim$Y
function<À
TRIM_SetIdealCnt$Àtrim$Y
cnt";ý
)TRIM_GetIdealCntY
$Àtrima__resultY

;³
3TRIM_GetRealCntY
$Àtrima__resultY



 



PAN_POWER__H_ „x
 




..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_power.h
PanSeries.h


|

..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_power.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x*ébuck_out_trim:
#lph_ldo_vref_trim:
#
lpl_ldo_trim:
#hp_ldo_trim:
#Ppower_param_t








__PAN_HAL_DEF_H__  
ÿ
 




..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\C:\Keil_v5\ARM\ARMCC\Bin\..\include\..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_hal_def.h
stdbool.hstdint.hPanSeries.h

H
..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_def.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xO“%:
"    
PDMAC_CallbackFunc

´
UART_CB_FLAG_TX_FINISHUART_CB_FLAG_RX_FINISHUART_CB_FLAG_RX_TIMEOUTUART_CB_FLAG_RX_BUFFFULLUART_CB_FLAG_DMAPUART_Cb_Flag_Opt0

ø
I2C_CB_FLAG_STOPI2C_CB_FLAG_DMA#PI2C_Cb_Flag_OptÌ

§
ADC_CB_FLAG_DMABPADC_Cb_Flag_Opt
"é
SPI_CB_FLAG_INTSPI_CB_FLAG_DMA#PSPI_CbFlagOpt>
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%%I
":
"~PUART_CallbackFunc–
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%%I
"³PI2C_CallbackFuncÅ
*Oó%i%ó%I
"I
"áPSPI_CallbackFuncù
+O§%'%'%I
"Y
"PADC_CallbackFunc-
,







__PAN_HAL_GPIO_H__ 
GPIO_P0_PIN_NUM 8
GPIO_P1_PIN_NUM 8
GPIO_P2_PIN_NUM 8
GPIO_P3_PIN_NUM 2
GPIO_INTEN_MASK_BASE 0x00010001UL
GPIO_INTTYPE_MASK_BASE 0x00000001ULˆ}
 




..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_gpio.h
pan_hal_def.h


ü
..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_gpio.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xß
P0_0P0_1
P0_2P0_3P0_4P0_5P0_6P0_7P1_0P1_1P1_2P1_3P1_4P1_5P1_6P1_7P2_0 P2_1!P2_2"P2_3#P2_4$P2_5%P2_6&P2_7'P3_00P3_11PHAL_GPIO_PinId


9¢HAL_GPIO_MODE_INPUT_DIGITALHAL_GPIO_MODE_INPUT_ANALOG
HAL_GPIO_MODE_OUTPUT_PUSHPULL
HAL_GPIO_MODE_OUTPUT_OPENDRAINHAL_GPIO_MODE_QUASI_BIDIRECTIONALPHAL_GPIO_Modeõ

Eÿ
HAL_GPIO_PULL_DISABLEHAL_GPIO_PULL_UP
HAL_GPIO_PULL_DOWNPHAL_GPIO_Pull·
OÆ
HAL_GPIO_LEVEL_LOWHAL_GPIO_LEVEL_HIGH
PHAL_GPIO_Level
X÷HAL_GPIO_INT_RISING
HAL_GPIO_INT_FALLING
HAL_GPIO_INT_BOTH_EDGE

HAL_GPIO_INT_HIGH

HAL_GPIO_INT_LOW

HAL_GPIO_INT_DISABLEPHAL_GPIO_IntMode\
eO—%÷"PHAL_GPIO_CallbackFunc
j*âmode¢#pullÿ#levelF#PHAL_GPIO_InitTypeDef8
}*¸    intMode÷#callbackFunc#debounceå#PHAL_GPIO_IntInitTypeDef~
ˆ
á    
qHAL_GPIO_CallbackArrayØ

)áHAL_GPIO_CallbackArray







__PAN_HAL_UART_H__ 
Æ
PAN_HAL_UART_INST_COUNT 2
Ç
UART0_OBJ UART_Handle_Array[0]
È
UART1_OBJ UART_Handle_Array[1]ˆ}
 




..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_uart.h
pan_hal_def.h


t
 
..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_uart.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x
_Boolt

PHAL_UART_EventOptx
PHAL_UART_IntModeOptc
(PHAL_UART_TxTrigOpt
0PHAL_UART_RxTrigOpt
8PHAL_UART_DmaDirOpt    
>PHAL_UART_FormatOpt4
pPHAL_UART_HandleTypeDef)
‰
(PHAL_UART_CallbackFuncÓ    
‹
PHAL_UART_InitTypeDef×    
”
PHAL_UART_IntTypeDefü    
¥
)Ë_HAL_UART_HandleTypeDef4pUartxK#initObjð
#interruptObj #pTxBuffPtrÍ    #txXferSizeI
#txXferCountQ#pRxBuffPtrÍ    # rxXferSizeI
#$rxXferCountQ#&isTxBusy
#(isRxBusy
#)txDmaCh:
#*rxDmaCh:
#+dmaSrcY
#,dmaDstY
#0"k tI
à³


qUART_Handle_ArrayW

ã
HAL_UART_EVT_TX_FINISHHAL_UART_EVT_RX_FINISH
HAL_UART_EVT_CONTI_RX_TIMEOUTHAL_UART_EVT_CONTI_RX_BUFF_FULLHAL_UART_EVT_RX_ERR_PARITYHAL_UART_EVT_RX_ERR_FRAMEHAL_UART_EVT_RX_ERR_OVERRUNHAL_UART_EVT_MAX…

HAL_UART_INT_RECV_DATA_AVL
HAL_UART_INT_THR_EMPTYHAL_UART_INT_LINE_STATUSHAL_UART_INT_MODEM_STATUSHAL_UART_INT_ALLHAL_UART_INT_DISABLE
HAL_UART_TX_FIFO_EMPTYHAL_UART_TX_FIFO_TWO_CHARS
HAL_UART_TX_FIFO_QUARTER_FULLHAL_UART_TX_FIFO_HALF_FULL‰
HAL_UART_RX_FIFO_ONE_CHARHAL_UART_RX_FIFO_QUARTER_FULL
HAL_UART_RX_FIFO_HALF_FULLHAL_UART_RX_FIFO_TWO_LESS_THAN_FULL´
HAL_UART_DMA_TXHAL_UART_DMA_RX
³
HAL_UART_FMT_5_N_1HAL_UART_FMT_5_N_1_5HAL_UART_FMT_5_E_1HAL_UART_FMT_5_E_1_5HAL_UART_FMT_5_O_1HAL_UART_FMT_5_O_1_5HAL_UART_FMT_5_S_18HAL_UART_FMT_5_S_1_5<HAL_UART_FMT_5_M_1(HAL_UART_FMT_5_M_1_5,HAL_UART_FMT_6_N_1
HAL_UART_FMT_6_N_2HAL_UART_FMT_6_E_1HAL_UART_FMT_6_E_2HAL_UART_FMT_6_O_1    HAL_UART_FMT_6_O_2 HAL_UART_FMT_6_S_19HAL_UART_FMT_6_S_2=HAL_UART_FMT_6_M_1)HAL_UART_FMT_6_M_2-HAL_UART_FMT_7_N_1HAL_UART_FMT_7_N_2HAL_UART_FMT_7_E_1HAL_UART_FMT_7_E_2HAL_UART_FMT_7_O_1
HAL_UART_FMT_7_O_2HAL_UART_FMT_7_S_1:HAL_UART_FMT_7_S_2>HAL_UART_FMT_7_M_1*HAL_UART_FMT_7_M_2.HAL_UART_FMT_8_N_1HAL_UART_FMT_8_N_2HAL_UART_FMT_8_E_1HAL_UART_FMT_8_E_2HAL_UART_FMT_8_O_1HAL_UART_FMT_8_O_2HAL_UART_FMT_8_S_1;HAL_UART_FMT_8_S_2?HAL_UART_FMT_8_M_1+HAL_UART_FMT_8_M_2/OÉ%É    %
%Í    %I
"³
":
"³    *übaudRateY
#format™
#*ötxTrigLevelK
#rxTrigLevele
#
IRQnƒ#IrqPriority:
#continuousRxMode
#callbackFuncÒ
#$x
`UART_Handle_Array


 
!


__PAN_HAL_DMAC_H__ 
;DMAC_CHANNEL_NUMS 2
=DMAC_Channel_0 DMAC_Channel_Array[0]
>DMAC_Channel_1 DMAC_Channel_Array[1]ˆ}
 




..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_dmac.h
pan_hal_def.h


|
..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_dmac.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xuvoid"

"Y
PDMAC_Peri_Mode_OptN
PDMAC_HandleTypeDef˜
9×4


qDMAC_Channel_ArrayN


qdma_uart2mem_config7

qdma_mem2uart_config7

qdma_spi2mem_config7

qdma_mem2spi_config7

qdma_mem2i2c_config7

qdma_i2c2mem_config7

qdma_adc2mem_config7

qdma_mem2i2c_u16_config7

˜
DMAC_Peri_UART
DMAC_Peri_I2CDMAC_Peri_SPIDMAC_Peri_ADC*õ8dmau#periph
#ConfigTmp7#Callback
#CallbackUartš#CallbackI2cÉ# CallbackSpiý#$CallbackAdc1#(PeriMode
#,pBuffPtr
#0XferSizeI
#4XferCountI
#6"Sã€W
DMAC_Channel_Arrayp
dma_uart2mem_configŒ
dma_mem2uart_config¨
dma_spi2mem_configÃ
dma_mem2spi_configÞ
dma_mem2i2c_configù
dma_i2c2mem_configdma_adc2mem_config/dma_mem2i2c_u16_config
#
$
%
&


 _PAN_HAL_SPI_H_ 
SPI_RX_BUF_SIZE 256
SPI_TX_BUF_SIZE 256
oSPI0_OBJ spiHandleArray[0]
vSPI1_OBJ spiHandleArray[1]ˆ|
 




..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_spi.h
pan_hal_def.h



..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_spi.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x*œ
ModeÊ#PSPI_InterruptOptDef    

!­BAUDRATE_100K †
BAUDRATE_500K ¡BAUDRATE_1M@BBAUDRATE_2M€„BAUDRATE_5M@KLBAUDRATE_10M€–˜PSPI_BaudRate7

-*²role #dataSizeB    #
clkPolarity#clkPhase~#baudrateDiv¿
#formaté#PSPI_InitOptDefÁ

;
SPI_STAT_NULLSPI_STAT_RXSPI_STAT_TX
SPI_STAT_RXTXPSPI_XferStatOptH
C*È4pSpixÈ#initObj2#xferStat#
interruptObj
#pTxBuffPtrÎ#txXferSizeI
#txXferCountÔ#pRxBuffPtrÎ#rxXferSizeI
#rxXferCountÔ#IRQnƒ#rxIntCallbacký# txIntCallbacký#$dmaSrcY
#(dmaDstY
#,errorCodeÚ#0""I
tI
tY
PSPI_HandleTypeDef¤
a‚à

qspiHandleArrayù

!spiHandleArray
(
)
*


__PAN_HAL_I2C_H ˆ|
 




..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_i2c.h
pan_hal_def.h



..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_i2c.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x±
I2C_ADDR_7BITI2C_ADDR_10BIT
PI2C_AddressMode_Opt    

ö
I2C_ROLE_MASTER!I2C_ROLE_SLAVEPI2C_Role_OptL

'ºI2C_DUTYCYCLE_16_9@I2C_DUTYCYCLE_2ÿ¿PI2C_DutyCycle_OptŠ

2õI2C_DIR_TXI2C_DIR_RX
PI2C_Direction_OptÓ

=ÀI2C_ACK_ADDR_7BIT@I2C_ACK_ADDR_10BITÀPI2C_AckAddr_Opt
HÖI2C_SPEED_100K †
I2C_SPEED_200K@ I2C_SPEED_400K€I2C_SPEED_500K ¡I2C_SPEED_1M@BI2C_SPEED_2M€„PI2C_ClockSpeed_OptW
W*ÝClockSpeedÖ#Rolev
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AddressMode1
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o’
I2C_Tx_DirI2C_Rx_Dir
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t*½
pass:
#PI2C_Interrupt_Optª
y*ð    @I2Cxð#I2C_InitObj]#InterruptObj½#pTxBuffPtrö#TxXferSizeI
#TxXferCountü#pRxBuffPtrö# RxXferSizeI
#$RxXferCountü#&IRQnƒ#(RxIntCallbackÉ#,TxIntCallbackÉ#0DMA_SRCY
#4DMA_DSTY
#8StopFlag:
#<"Z":
tI
PI2C_HandleTypeDefÖ
™

,
-
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__PAN_HAL_WDT_H ˆ|
 




..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_wdt.h
pan_hal_def.h


Ø

..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_wdt.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x*óTimeout_#ResetDelayð#ClockSourceY
#ResetSwitchY
#WakeupSwitchY
#PWDT_Init_Opt    

!O‹"‡
PWDT_CallbackFunc‹

&*ÀCallbackFunc
#PWDT_Interrupt_Opt§

/
0
1
2


 __PAN_HAL_WWDT_H ˆ}
 




..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_wwdt.h
pan_hal_def.h


°

..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_wwdt.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xOŽ"

PWWDT_CallbackFunc

*êPrescaler†#ClockSourceY
#CmpValueY
#PWWDT_Init_Opt+

$*˜CallbackFunc
#PWWDT_Interrupt_Opt

-
4
5
6


__PAN_HAL_PWM_H 
JHAL_PWM_PinConfiguration(port,bit,chId) (SYS->port ## _MFP = (SYS->port ## _MFP & ~SYS_MFP_ ## port ## bit ## _Msk) | SYS_MFP_ ## port ## bit ## _ ## chId)ˆ|
 




..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_pwm.h
pan_hal_def.h


|
..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_pwm.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x
_BoolPPWM_ChIdH

#PPWM_ModeOpt­

0PPWM_InitOpt
?­
PWM0_CH0PWM0_CH1
PWM0_CH2PWM0_CH3PWM0_CH4PWM0_CH5PWM0_CH6PWM0_CH7PWM_MODE_INDEPENDENTPWM_MODE_COMPLEMENTARY
PWM_MODE_SYNCHRONIZEDPWM_MODE_GROUP
*þfrequencyY
#dutyCycleY
#operateType=#mode"
#
inverter    
#lowPowerEn    
# 
8
9
:
;


__PAN_HAL_TIMER_H 
_TIMER0_OBJ TIMER_Handle_Array[0]
`TIMER1_OBJ TIMER_Handle_Array[1]
aTIMER2_OBJ TIMER_Handle_Array[2]ˆ~
 




..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_timer.h
pan_hal_def.h


8
..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_timer.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xÎ
TIMER_CB_FLAG_CNT
TIMER_CB_FLAG_CAPTIMER_CB_FLAG_WKPTIMER_Cb_Flag_Opt

!Oï%N
"g
PTIMER_CallbackFunco

(è
TIMER_MODE_BASECNTTIMER_MODE_EVENTCNT
TIMER_MODE_INCAPTIMER_MODE_WAKEUPPTIMER_Mode_Opt

5*‘
pass:
#PTIMER_Interrupt_Optþ

;*Ú$freqY
#modeè
#cntModeÈ#capModeg#cmpValueY
#capEdge@#evtCntEdge­#capSrc$    #prescaleY
#tmr0CmpSel¥    # PTIMER_Init_Opt,
N*Ä0TIMERxD#initObjÚ#interruptObj#(IRQnƒ#)callbacks
#,"€PTIMER_HandleTypeDefð
]îJ
qTIMER_Handle_Arraye

;ß
eHAL_TIMER_US_TO_CNTY
$Y
timeUs$i
frequencya__resultY

\cnti
;·
lHAL_TIMER_MS_TO_CNTY
$Y
timeMs$i
frequencya__resultY

\cnti
%<nTIMER_Handle_Array
=
>
?


 __PAN_HAL_ADC_H ˆ|
 




..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_adc.h
pan_hal_def.h


L
..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_adc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xð
ADC_MODE_CONVADC_MODE_EXTRIG
ADC_MODE_COMPAREADC_MODE_PWMSEQADC_MODE_SGLCONVSEQPADC_ModeOpt    

#ß
ADC_CONV_MODE_BASEADC_CONV_MODE_TEMP
ADC_CONV_MODE_VBGADC_CONV_MODE_VDD4PADC_ConvertModeOptƒ

0ƒ
ADC_CH0ADC_CH1
ADC_CH2ADC_CH3ADC_CH4ADC_CH5ADC_CH6ADC_CH7ADC_CH_TEMP    ADC_CH_BATTERY
ADC_IDLEÿPADC_ChIdù

EÇ
ADC_INPUT_RANGE_LOWADC_INPUT_RANGE_HIGH
PADC_InputRangeOpt“
R*ƒInputRangeÇ#Modep
#
PADC_InitOptà
`*´initOpt#idƒ#PADC_HandleTypeDef
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__PAN_HAL_H__ 
HAL_TIME_FOREVER 0xFFFFFFFFU
HAL_ASSERT SYS_ASSERT!"#$%'(    )
*+

PAN_IO_TIMING_TRACK_INIT_PIN(__VA_ARGS__...) 
Ž
PAN_IO_TIMING_TRACK_LEVEL(__VA_ARGS__...) 

PAN_IO_TIMING_TRACK_TOGGLE(__VA_ARGS__...) T
H

 




..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\C:\Keil_v5\ARM\ARMCC\Bin\..\include\pan_hal.h
stdint.hpan_hal_gpio.h
pan_hal_uart.h
pan_hal_dmac.h
pan_hal_spi.h
pan_hal_i2c.h
pan_hal_wdt.h
pan_hal_wwdt.h
pan_hal_pwm.h
pan_hal_timer.h
pan_hal_adc.h


ä

..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x‰
HAL_SUCCESSHAL_INVALID_PARAMS
HAL_IO_ERRORHAL_DEVICE_BUSYHAL_NO_MEMHAL_NO_HARDWARE_SOURCEHAL_UNKNOWNPHAL_Error

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HAL_OKHAL_ERROR
HAL_BUSYHAL_TIMEOUTPHAL_Statusš


E
F
G
H


FREERTOS_CONFIG_H -34
6configUSE_TICKLESS_IDLE CONFIG_PM
9configCPU_CLOCK_HZ (SystemCoreClock)
EconfigTICK_RATE_HZ ((TickType_t)1000)
MconfigMINIMAL_STACK_SIZE ((uint16_t)64)
OconfigSUPPORT_DYNAMIC_ALLOCATION 1
PconfigSUPPORT_STATIC_ALLOCATION 0
WconfigUSE_PREEMPTION 1
XconfigUSE_TIME_SLICING 1
YconfigIDLE_SHOULD_YIELD 1
ZconfigMAX_TASK_NAME_LEN (16)
[configUSE_16_BIT_TICKS 0
qconfigUSE_MUTEXES 1
rconfigUSE_RECURSIVE_MUTEXES 1
sconfigUSE_COUNTING_SEMAPHORES 1
tconfigUSE_QUEUE_SETS 1
uconfigUSE_TASK_NOTIFICATIONS 1
wconfigEXPECTED_IDLE_TIME_BEFORE_SLEEP 3
xconfigUSE_APPLICATION_TASK_TAG 0
yconfigUSE_NEWLIB_REENTRANT 0
zconfigUSE_CO_ROUTINES 0
~configQUEUE_REGISTRY_SIZE 10

configASSERT(x) {if((x) == 0) {while(1){};}}

configUSE_DAEMON_TASK_STARTUP_HOOK 0
–
configENABLE_MPU 0
—
configENABLE_FPU 0
˜
configENABLE_TRUSTZONE 1
™
configMINIMAL_SECURE_STACK_SIZE ((uint32_t)1024)
š
configRUN_FREERTOS_SECURE_ONLY 0

configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES 0
¢
configPRIO_BITS __NVIC_PRIO_BITS
©
configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x03
¯
configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 0
³
configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
·
configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
½
INCLUDE_vTaskPrioritySet 1
¾
INCLUDE_uxTaskPriorityGet 1
¿
INCLUDE_vTaskDelete 1
À
INCLUDE_vTaskSuspend 1
Á
INCLUDE_vTaskDelayUntil 1
Â
INCLUDE_vTaskDelay 1
Ã
INCLUDE_xTaskGetIdleTaskHandle 1
Ä
INCLUDE_xTaskAbortDelay 1
Å
INCLUDE_xQueueGetMutexHolder 1
Æ
INCLUDE_xSemaphoreGetMutexHolder 1
Ç
INCLUDE_xTaskGetHandle 1
È
INCLUDE_uxTaskGetStackHighWaterMark 1
É
INCLUDE_uxTaskGetStackHighWaterMark2 1
Ê
INCLUDE_eTaskGetState 1
Ë
INCLUDE_xTaskResumeFromISR 1
Ì
INCLUDE_xTimerPendFunctionCall 1
Í
INCLUDE_xTaskGetSchedulerState 1
Î
INCLUDE_xTaskGetCurrentTaskHandle 1
Ò
xPortPendSVHandler PendSV_Handler
Ó
vPortSVCHandler SVC_Handler
Ô
xPortSysTickHandler SysTick_Handlerìã
 




..\..\..\..\config\C:\Keil_v5\ARM\ARMCC\Bin\..\include\..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\.\configuration\FreeRTOSConfig.h
stdint.hPanSeries.hsdk_config.h



..\..\..\..\config\FreeRTOSConfig.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xqSystemCoreClockY


qclk_32k_freqY


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ÙSystemCoreClockñclk_32k_freq
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PROJDEFS_H 
*pdMS_TO_TICKS(xTimeInMs) ( ( TickType_t ) ( ( ( TickType_t ) ( xTimeInMs ) * ( TickType_t ) configTICK_RATE_HZ ) / ( TickType_t ) 1000U ) )
-pdFALSE ( ( BaseType_t ) 0 )
.pdTRUE ( ( BaseType_t ) 1 )
0pdPASS ( pdTRUE )
1pdFAIL ( pdFALSE )
2errQUEUE_EMPTY ( ( BaseType_t ) 0 )
3errQUEUE_FULL ( ( BaseType_t ) 0 )
6errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ( -1 )
7errQUEUE_BLOCKED ( -4 )
8errQUEUE_YIELD ( -5 )
BpdINTEGRITY_CHECK_VALUE 0x5a5a5a5aUL
GpdFREERTOS_ERRNO_NONE 0
HpdFREERTOS_ERRNO_ENOENT 2
IpdFREERTOS_ERRNO_EINTR 4
JpdFREERTOS_ERRNO_EIO 5
KpdFREERTOS_ERRNO_ENXIO 6
LpdFREERTOS_ERRNO_EBADF 9
MpdFREERTOS_ERRNO_EAGAIN 11
NpdFREERTOS_ERRNO_EWOULDBLOCK 11
OpdFREERTOS_ERRNO_ENOMEM 12
PpdFREERTOS_ERRNO_EACCES 13
QpdFREERTOS_ERRNO_EFAULT 14
RpdFREERTOS_ERRNO_EBUSY 16
SpdFREERTOS_ERRNO_EEXIST 17
TpdFREERTOS_ERRNO_EXDEV 18
UpdFREERTOS_ERRNO_ENODEV 19
VpdFREERTOS_ERRNO_ENOTDIR 20
WpdFREERTOS_ERRNO_EISDIR 21
XpdFREERTOS_ERRNO_EINVAL 22
YpdFREERTOS_ERRNO_ENOSPC 28
ZpdFREERTOS_ERRNO_ESPIPE 29
[pdFREERTOS_ERRNO_EROFS 30
\pdFREERTOS_ERRNO_EUNATCH 42
]pdFREERTOS_ERRNO_EBADE 50
^pdFREERTOS_ERRNO_EFTYPE 79
_pdFREERTOS_ERRNO_ENMFILE 89
`pdFREERTOS_ERRNO_ENOTEMPTY 90
apdFREERTOS_ERRNO_ENAMETOOLONG 91
bpdFREERTOS_ERRNO_EOPNOTSUPP 95
cpdFREERTOS_ERRNO_ENOBUFS 105
dpdFREERTOS_ERRNO_ENOPROTOOPT 109
epdFREERTOS_ERRNO_EADDRINUSE 112
fpdFREERTOS_ERRNO_ETIMEDOUT 116
gpdFREERTOS_ERRNO_EINPROGRESS 119
hpdFREERTOS_ERRNO_EALREADY 120
ipdFREERTOS_ERRNO_EADDRNOTAVAIL 125
jpdFREERTOS_ERRNO_EISCONN 127
kpdFREERTOS_ERRNO_ENOTCONN 128
lpdFREERTOS_ERRNO_ENOMEDIUM 135
mpdFREERTOS_ERRNO_EILSEQ 138
npdFREERTOS_ERRNO_ECANCELED 140
rpdFREERTOS_LITTLE_ENDIAN 1
spdFREERTOS_BIG_ENDIAN 0
vpdLITTLE_ENDIAN pdFREERTOS_LITTLE_ENDIAN
wpdBIG_ENDIAN pdFREERTOS_BIG_ENDIANLB
 




..\..\..\..\os\freertos\include\projdefs.h




..\..\..\..\os\freertos\include\projdefs.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xuvoid"à"
PTaskFunction_tê
$OŒ%æ
N
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P


DEPRECATED_DEFINITIONS_H \P
 




..\..\..\..\os\freertos\include\deprecated_definitions.h


ì
..\..\..\..\os\freertos\include\deprecated_definitions.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x
R
S
T


PORTMACRO_H 1
4portCHAR char
5portFLOAT float
6portDOUBLE double
7portLONG long
8portSHORT short
9portSTACK_TYPE uint32_t
:portBASE_TYPE long
IportMAX_DELAY ( TickType_t ) 0xffffffffUL
NportTICK_TYPE_IS_ATOMIC 1
SportSTACK_GROWTH ( -1 )
VportBYTE_ALIGNMENT 8
\portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
]portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
^portYIELD() vPortYield()
_portEND_SWITCHING_ISR(xSwitchRequired) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
`portYIELD_FROM_ISR(x) portEND_SWITCHING_ISR( x )
iportSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()
jportCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )
kportDISABLE_INTERRUPTS() __set_PRIMASK(1)
lportENABLE_INTERRUPTS() __set_PRIMASK(0)
mportENTER_CRITICAL() vPortEnterCritical()
nportEXIT_CRITICAL() vPortExitCritical()
uportSUPPRESS_TICKS_AND_SLEEP(xExpectedIdleTime) vPortSuppressTicksAndSleep( xExpectedIdleTime )
zportTASK_FUNCTION_PROTO(vFunction,pvParameters) void vFunction( void * pvParameters )
{portTASK_FUNCTION(vFunction,pvParameters) void vFunction( void * pvParameters )
}portNOP() „y
 




..\..\..\..\os\freertos\portable\RVDS\ARM_CM0\..\..\..\..\config\portmacro.h
FreeRTOSConfig.h

T

..\..\..\..\os\freertos\portable\RVDS\ARM_CM0\portmacro.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xlongunsigned longPStackType_tY

<PBaseType_tï
=PUBaseType_t÷
>PTickType_tY

H
V
W
X


MPU_WRAPPERS_H 
±
PRIVILEGED_FUNCTION 
²
PRIVILEGED_DATA 
³
FREERTOS_SYSTEM_CALL PF
 




..\..\..\..\os\freertos\include\mpu_wrappers.h


ä
..\..\..\..\os\freertos\include\mpu_wrappers.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x
Z
[
\


"PORTABLE_H .5
=portBYTE_ALIGNMENT_MASK ( 0x0007 )
IportUSING_MPU_WRAPPERS 0
MportNUM_CONFIGURABLE_REGIONS 1
QportHAS_STACK_OVERFLOW_CHECKING 0
UportARCH_NAME NULL
ZconfigSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0c
»
pvPortMallocStack pvPortMalloc
¼
vPortFreeStack vPortFree
è
LPTMR_CURR_CNT_VAL_REG (0x50020014)¸®
 




..\..\..\..\os\freertos\include\..\..\..\..\os\freertos\portable\RVDS\ARM_CM0\portable.h
deprecated_definitions.h
portmacro.hmpu_wrappers.h



..\..\..\..\os\freertos\include\portable.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x)HeapRegionpucStartAddress
#xSizeInBytesš#":
PHeapRegion_tà
‹
)ÌxHeapStatsxAvailableHeapSpaceInBytesš#xSizeOfLargestFreeBlockInBytesš#xSizeOfSmallestFreeBlockInBytesš#xNumberOfFreeBlocksš#xMinimumEverFreeBytesRemainingš#xNumberOfSuccessfulAllocationsš#xNumberOfSuccessfulFreesš#PHeapStats_t8

—
;’
é
lp_get_curr_tmr_cntY
a__resultY


^
_
`


INC_FREERTOS_H #2;>A
jconfigUSE_C_RUNTIME_TLS_SUPPORT 0
È
INCLUDE_xTaskDelayUntil INCLUDE_vTaskDelayUntil
“configNUM_THREAD_LOCAL_STORAGE_POINTERS 0
§configUSE_ALTERNATIVE_API 0
«portCRITICAL_NESTING_IN_TCB 0
¾configASSERT_DEFINED 1
ÇconfigPRECONDITION(X) configASSERT( X )
ÈconfigPRECONDITION_DEFINED 0
ÎportMEMORY_BARRIER() 
ÒportSOFTWARE_BARRIER() 
ïportCLEAN_UP_TCB(pxTCB) ( void ) ( pxTCB )
óportPRE_TASK_DELETE_HOOK(pvTaskToDelete,pxYieldPending) 
÷portSETUP_TCB(pxTCB) ( void ) ( pxTCB )
…configUSE_MINI_LIST_ITEM 1
‰portPOINTER_SIZE_TYPE uint32_t
‘traceSTART() 
˜traceEND() 
ŸtraceTASK_SWITCHED_IN() 
¦traceINCREASE_TICK_COUNT(x) 
«traceLOW_POWER_IDLE_BEGIN() 
°traceLOW_POWER_IDLE_END() 
·traceTASK_SWITCHED_OUT() 
ÁtraceTASK_PRIORITY_INHERIT(pxTCBOfMutexHolder,uxInheritedPriority) 
ÊtraceTASK_PRIORITY_DISINHERIT(pxTCBOfMutexHolder,uxOriginalPriority) 
ÓtraceBLOCKING_ON_QUEUE_RECEIVE(pxQueue) 
ÜtraceBLOCKING_ON_QUEUE_PEEK(pxQueue) 
åtraceBLOCKING_ON_QUEUE_SEND(pxQueue) 
íconfigRECORD_STACK_HIGH_ADDRESS 0
ñconfigINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 0
÷traceMOVED_TASK_TO_READY_STATE(pxTCB) 
ûtracePOST_MOVED_TASK_TO_READY_STATE(pxTCB) 
ÿtraceQUEUE_CREATE(pxNewQueue) 
ƒtraceQUEUE_CREATE_FAILED(ucQueueType) 
‡traceCREATE_MUTEX(pxNewQueue) 
‹traceCREATE_MUTEX_FAILED() 
traceGIVE_MUTEX_RECURSIVE(pxMutex) 
“traceGIVE_MUTEX_RECURSIVE_FAILED(pxMutex) 
—traceTAKE_MUTEX_RECURSIVE(pxMutex) 
›traceTAKE_MUTEX_RECURSIVE_FAILED(pxMutex) 
ŸtraceCREATE_COUNTING_SEMAPHORE() 
£traceCREATE_COUNTING_SEMAPHORE_FAILED() 
§traceQUEUE_SET_SEND traceQUEUE_SEND
«traceQUEUE_SEND(pxQueue) 
¯traceQUEUE_SEND_FAILED(pxQueue) 
³traceQUEUE_RECEIVE(pxQueue) 
·traceQUEUE_PEEK(pxQueue) 
»traceQUEUE_PEEK_FAILED(pxQueue) 
¿traceQUEUE_PEEK_FROM_ISR(pxQueue) 
ÃtraceQUEUE_RECEIVE_FAILED(pxQueue) 
ÇtraceQUEUE_SEND_FROM_ISR(pxQueue) 
ËtraceQUEUE_SEND_FROM_ISR_FAILED(pxQueue) 
ÏtraceQUEUE_RECEIVE_FROM_ISR(pxQueue) 
ÓtraceQUEUE_RECEIVE_FROM_ISR_FAILED(pxQueue) 
×traceQUEUE_PEEK_FROM_ISR_FAILED(pxQueue) 
ÛtraceQUEUE_DELETE(pxQueue) 
ßtraceTASK_CREATE(pxNewTCB) 
ãtraceTASK_CREATE_FAILED() 
çtraceTASK_DELETE(pxTaskToDelete) 
ëtraceTASK_DELAY_UNTIL(x) 
ïtraceTASK_DELAY() 
ótraceTASK_PRIORITY_SET(pxTask,uxNewPriority) 
÷traceTASK_SUSPEND(pxTaskToSuspend) 
ûtraceTASK_RESUME(pxTaskToResume) 
ÿtraceTASK_RESUME_FROM_ISR(pxTaskToResume) 
ƒtraceTASK_INCREMENT_TICK(xTickCount) 
‡traceTIMER_CREATE(pxNewTimer) 
‹traceTIMER_CREATE_FAILED() 
traceTIMER_COMMAND_SEND(xTimer,xMessageID,xMessageValueValue,xReturn) 
“traceTIMER_EXPIRED(pxTimer) 
—traceTIMER_COMMAND_RECEIVED(pxTimer,xMessageID,xMessageValue) 
›traceMALLOC(pvAddress,uiSize) 
ŸtraceFREE(pvAddress,uiSize) 
£traceEVENT_GROUP_CREATE(xEventGroup) 
§traceEVENT_GROUP_CREATE_FAILED() 
«traceEVENT_GROUP_SYNC_BLOCK(xEventGroup,uxBitsToSet,uxBitsToWaitFor) 
¯traceEVENT_GROUP_SYNC_END(xEventGroup,uxBitsToSet,uxBitsToWaitFor,xTimeoutOccurred) ( void ) ( xTimeoutOccurred )
³traceEVENT_GROUP_WAIT_BITS_BLOCK(xEventGroup,uxBitsToWaitFor) 
·traceEVENT_GROUP_WAIT_BITS_END(xEventGroup,uxBitsToWaitFor,xTimeoutOccurred) ( void ) ( xTimeoutOccurred )
»traceEVENT_GROUP_CLEAR_BITS(xEventGroup,uxBitsToClear) 
¿traceEVENT_GROUP_CLEAR_BITS_FROM_ISR(xEventGroup,uxBitsToClear) 
ÃtraceEVENT_GROUP_SET_BITS(xEventGroup,uxBitsToSet) 
ÇtraceEVENT_GROUP_SET_BITS_FROM_ISR(xEventGroup,uxBitsToSet) 
ËtraceEVENT_GROUP_DELETE(xEventGroup) 
ÏtracePEND_FUNC_CALL(xFunctionToPend,pvParameter1,ulParameter2,ret) 
ÓtracePEND_FUNC_CALL_FROM_ISR(xFunctionToPend,pvParameter1,ulParameter2,ret) 
×traceQUEUE_REGISTRY_ADD(xQueue,pcQueueName) 
ÛtraceTASK_NOTIFY_TAKE_BLOCK(uxIndexToWait) 
ßtraceTASK_NOTIFY_TAKE(uxIndexToWait) 
ãtraceTASK_NOTIFY_WAIT_BLOCK(uxIndexToWait) 
çtraceTASK_NOTIFY_WAIT(uxIndexToWait) 
ëtraceTASK_NOTIFY(uxIndexToNotify) 
ïtraceTASK_NOTIFY_FROM_ISR(uxIndexToNotify) 
ótraceTASK_NOTIFY_GIVE_FROM_ISR(uxIndexToNotify) 
÷traceSTREAM_BUFFER_CREATE_FAILED(xIsMessageBuffer) 
ûtraceSTREAM_BUFFER_CREATE_STATIC_FAILED(xReturn,xIsMessageBuffer) 
ÿtraceSTREAM_BUFFER_CREATE(pxStreamBuffer,xIsMessageBuffer) 
ƒtraceSTREAM_BUFFER_DELETE(xStreamBuffer) 
‡traceSTREAM_BUFFER_RESET(xStreamBuffer) 
‹traceBLOCKING_ON_STREAM_BUFFER_SEND(xStreamBuffer) 
traceSTREAM_BUFFER_SEND(xStreamBuffer,xBytesSent) 
“traceSTREAM_BUFFER_SEND_FAILED(xStreamBuffer) 
—traceSTREAM_BUFFER_SEND_FROM_ISR(xStreamBuffer,xBytesSent) 
›traceBLOCKING_ON_STREAM_BUFFER_RECEIVE(xStreamBuffer) 
ŸtraceSTREAM_BUFFER_RECEIVE(xStreamBuffer,xReceivedLength) 
£traceSTREAM_BUFFER_RECEIVE_FAILED(xStreamBuffer) 
§traceSTREAM_BUFFER_RECEIVE_FROM_ISR(xStreamBuffer,xReceivedLength) 
«configGENERATE_RUN_TIME_STATS 0
½portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() 
ÅportPRIVILEGE_BIT ( ( UBaseType_t ) 0x00 )
ÉportYIELD_WITHIN_API portYIELD
ÝconfigPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING(x) 
áconfigPRE_SLEEP_PROCESSING(x) 
åconfigPOST_SLEEP_PROCESSING(x) 
íportTASK_USES_FLOATING_POINT() 
ñportALLOCATE_SECURE_CONTEXT(ulSecureStackSize) 
õportDONT_DISCARD 
ýconfigINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS 0
configUSE_STATS_FORMATTING_FUNCTIONS 0
…portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 
‰configUSE_TRACE_FACILITY 0
mtCOVERAGE_TEST_MARKER() 
‘mtCOVERAGE_TEST_DELAY() 
•portASSERT_IF_IN_ISR() 
™configUSE_PORT_OPTIMISED_TASK_SELECTION 0
configAPPLICATION_ALLOCATED_HEAP 0
¥configTASK_NOTIFICATION_ARRAY_ENTRIES 1
­configUSE_POSIX_ERRNO 0
³configUSE_SB_COMPLETED_CALLBACK 0
ÒconfigSTACK_DEPTH_TYPE uint16_t
ÚconfigRUN_TIME_COUNTER_TYPE uint32_t
âconfigMESSAGE_BUFFER_LENGTH_TYPE size_t
ïconfigINITIAL_TICK_COUNT 0
ÿportTICK_TYPE_ENTER_CRITICAL() 
€portTICK_TYPE_EXIT_CRITICAL() 
portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() 0
‚portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR(x) ( void ) ( x )
ˆconfigENABLE_BACKWARD_COMPATIBILITY 1
—configPRINTF(X) 
žconfigMAX(a,b) ( ( ( a ) > ( b ) ) ? ( a ) : ( b ) )
¥configMIN(a,b) ( ( ( a ) < ( b ) ) ? ( a ) : ( b ) )
©eTaskStateGet eTaskGetState
ªportTickType TickType_t
«xTaskHandle TaskHandle_t
¬xQueueHandle QueueHandle_t
­xSemaphoreHandle SemaphoreHandle_t
®xQueueSetHandle QueueSetHandle_t
¯xQueueSetMemberHandle QueueSetMemberHandle_t
°xTimeOutType TimeOut_t
±xMemoryRegion MemoryRegion_t
²xTaskParameters TaskParameters_t
³xTaskStatusType TaskStatus_t
´xTimerHandle TimerHandle_t
µxCoRoutineHandle CoRoutineHandle_t
¶pdTASK_HOOK_CODE TaskHookFunction_t
·portTICK_RATE_MS portTICK_PERIOD_MS
¸pcTaskGetTaskName pcTaskGetName
¹pcTimerGetTimerName pcTimerGetName
ºpcQueueGetQueueName pcQueueGetName
»vTaskGetTaskInfo vTaskGetInfo
¼xTaskGetIdleRunTimeCounter ulTaskGetIdleRunTimeCounter
ÀtmrTIMER_CALLBACK TimerCallbackFunction_t
ÁpdTASK_CODE TaskFunction_t
ÂxListItem ListItem_t
ÃxList List_t
ÇpxContainer pvContainer
ÓconfigUSE_TASK_FPU_SUPPORT 1
åconfigENABLE_MVE 0
õconfigRUN_ADDITIONAL_TESTS 0
£    tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE ( ( ( portUSING_MPU_WRAPPERS == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) || ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) )ÌÃ
 




..\..\..\..\os\freertos\include\C:\Keil_v5\ARM\ARMCC\Bin\..\include\..\..\..\..\config\FreeRTOS.h
stddef.hstdint.hFreeRTOSConfig.hprojdefs.h
portable.h


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..\..\..\..\os\freertos\include\FreeRTOS.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xuvoid"àPStaticListItem_t
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;LIST_H 
^configLIST_VOLATILE 
nlistFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE 
olistSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE 
plistFIRST_LIST_INTEGRITY_CHECK_VALUE 
qlistSECOND_LIST_INTEGRITY_CHECK_VALUE 
rlistSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE(pxItem) 
slistSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE(pxItem) 
tlistSET_LIST_INTEGRITY_CHECK_1_VALUE(pxList) 
ulistSET_LIST_INTEGRITY_CHECK_2_VALUE(pxList) 
vlistTEST_LIST_ITEM_INTEGRITY(pxItem) 
wlistTEST_LIST_INTEGRITY(pxList) 
¼
listSET_LIST_ITEM_OWNER(pxListItem,pxOwner) ( ( pxListItem )->pvOwner = ( void * ) ( pxOwner ) )
Å
listGET_LIST_ITEM_OWNER(pxListItem) ( ( pxListItem )->pvOwner )
Î
listSET_LIST_ITEM_VALUE(pxListItem,xValue) ( ( pxListItem )->xItemValue = ( xValue ) )
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listGET_LIST_ITEM_VALUE(pxListItem) ( ( pxListItem )->xItemValue )
á
listGET_ITEM_VALUE_OF_HEAD_ENTRY(pxList) ( ( ( pxList )->xListEnd ).pxNext->xItemValue )
é
listGET_HEAD_ENTRY(pxList) ( ( ( pxList )->xListEnd ).pxNext )
ñ
listGET_NEXT(pxListItem) ( ( pxListItem )->pxNext )
ù
listGET_END_MARKER(pxList) ( ( ListItem_t const * ) ( &( ( pxList )->xListEnd ) ) )
‚listLIST_IS_EMPTY(pxList) ( ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) ? pdTRUE : pdFALSE )
‡listCURRENT_LIST_LENGTH(pxList) ( ( pxList )->uxNumberOfItems )
listGET_OWNER_OF_NEXT_ENTRY(pxTCB,pxList) { List_t * const pxConstList = ( pxList ); ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; if( ( void * ) ( pxConstList )->pxIndex == ( void * ) &( ( pxConstList )->xListEnd ) ) { ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; } ( pxTCB ) = ( pxConstList )->pxIndex->pvOwner; }
ºlistREMOVE_ITEM(pxItemToRemove) { List_t * const pxList = ( pxItemToRemove )->pxContainer; ( pxItemToRemove )->pxNext->pxPrevious = ( pxItemToRemove )->pxPrevious; ( pxItemToRemove )->pxPrevious->pxNext = ( pxItemToRemove )->pxNext; if( pxList->pxIndex == ( pxItemToRemove ) ) { pxList->pxIndex = ( pxItemToRemove )->pxPrevious; } ( pxItemToRemove )->pxContainer = NULL; ( pxList->uxNumberOfItems )--; }
âlistINSERT_END(pxList,pxNewListItem) { ListItem_t * const pxIndex = ( pxList )->pxIndex; listTEST_LIST_INTEGRITY( ( pxList ) ); listTEST_LIST_ITEM_INTEGRITY( ( pxNewListItem ) ); ( pxNewListItem )->pxNext = pxIndex; ( pxNewListItem )->pxPrevious = pxIndex->pxPrevious; pxIndex->pxPrevious->pxNext = ( pxNewListItem ); pxIndex->pxPrevious = ( pxNewListItem ); ( pxNewListItem )->pxContainer = ( pxList ); ( ( pxList )->uxNumberOfItems )++; }
‹listGET_OWNER_OF_HEAD_ENTRY(pxList) ( ( &( ( pxList )->xListEnd ) )->pxNext->pvOwner )
–listIS_CONTAINED_WITHIN(pxList,pxListItem) ( ( ( pxListItem )->pxContainer == ( pxList ) ) ? ( pdTRUE ) : ( pdFALSE ) )
žlistLIST_ITEM_CONTAINER(pxListItem) ( ( pxListItem )->pxContainer )
¥listLIST_IS_INITIALISED(pxList) ( ( pxList )->xListEnd.xItemValue == portMAX_DELAY )H>
 




..\..\..\..\os\freertos\include\list.h


 
..\..\..\..\os\freertos\include\list.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xuvoid"ÜPListItem_t³

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)ÂxMINI_LIST_ITEMxItemValueB
#pxNext#pxPrevious#PMiniListItem_tù
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INC_TASK_H %
8tskKERNEL_VERSION_NUMBER "V10.5.1"
9tskKERNEL_VERSION_MAJOR 10
:tskKERNEL_VERSION_MINOR 5
;tskKERNEL_VERSION_BUILD 1
?tskMPU_REGION_READ_ONLY ( 1UL << 0UL )
@tskMPU_REGION_READ_WRITE ( 1UL << 1UL )
AtskMPU_REGION_EXECUTE_NEVER ( 1UL << 2UL )
BtskMPU_REGION_NORMAL_MEMORY ( 1UL << 3UL )
CtskMPU_REGION_DEVICE_MEMORY ( 1UL << 4UL )
JtskDEFAULT_INDEX_TO_NOTIFY ( 0 )
º
tskIDLE_PRIORITY ( ( UBaseType_t ) 0U )
Ä
taskYIELD() portYIELD()
Ò
taskENTER_CRITICAL() portENTER_CRITICAL()
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taskENTER_CRITICAL_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR()
á
taskEXIT_CRITICAL() portEXIT_CRITICAL()
â
taskEXIT_CRITICAL_FROM_ISR(x) portCLEAR_INTERRUPT_MASK_FROM_ISR( x )
ì
taskDISABLE_INTERRUPTS() portDISABLE_INTERRUPTS()
ö
taskENABLE_INTERRUPTS() portENABLE_INTERRUPTS()
û
taskSCHEDULER_SUSPENDED ( ( BaseType_t ) 0 )
ü
taskSCHEDULER_NOT_STARTED ( ( BaseType_t ) 1 )
ý
taskSCHEDULER_RUNNING ( ( BaseType_t ) 2 )
ävTaskDelayUntil(pxPreviousWakeTime,xTimeIncrement) do { ( void ) xTaskDelayUntil( ( pxPreviousWakeTime ), ( xTimeIncrement ) ); } while( 0 )
™xTaskNotify(xTaskToNotify,ulValue,eAction) xTaskGenericNotify( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), NULL )
›xTaskNotifyIndexed(xTaskToNotify,uxIndexToNotify,ulValue,eAction) xTaskGenericNotify( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), NULL )
¶xTaskNotifyAndQuery(xTaskToNotify,ulValue,eAction,pulPreviousNotifyValue) xTaskGenericNotify( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) )
¸xTaskNotifyAndQueryIndexed(xTaskToNotify,uxIndexToNotify,ulValue,eAction,pulPreviousNotifyValue) xTaskGenericNotify( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) )
²xTaskNotifyFromISR(xTaskToNotify,ulValue,eAction,pxHigherPriorityTaskWoken) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), NULL, ( pxHigherPriorityTaskWoken ) )
´xTaskNotifyIndexedFromISR(xTaskToNotify,uxIndexToNotify,ulValue,eAction,pxHigherPriorityTaskWoken) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), NULL, ( pxHigherPriorityTaskWoken ) )
ÏxTaskNotifyAndQueryIndexedFromISR(xTaskToNotify,uxIndexToNotify,ulValue,eAction,pulPreviousNotificationValue,pxHigherPriorityTaskWoken) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotificationValue ), ( pxHigherPriorityTaskWoken ) )
ÑxTaskNotifyAndQueryFromISR(xTaskToNotify,ulValue,eAction,pulPreviousNotificationValue,pxHigherPriorityTaskWoken) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), ( pulPreviousNotificationValue ), ( pxHigherPriorityTaskWoken ) )
ÁxTaskNotifyWait(ulBitsToClearOnEntry,ulBitsToClearOnExit,pulNotificationValue,xTicksToWait) xTaskGenericNotifyWait( tskDEFAULT_INDEX_TO_NOTIFY, ( ulBitsToClearOnEntry ), ( ulBitsToClearOnExit ), ( pulNotificationValue ), ( xTicksToWait ) )
ÃxTaskNotifyWaitIndexed(uxIndexToWaitOn,ulBitsToClearOnEntry,ulBitsToClearOnExit,pulNotificationValue,xTicksToWait) xTaskGenericNotifyWait( ( uxIndexToWaitOn ), ( ulBitsToClearOnEntry ), ( ulBitsToClearOnExit ), ( pulNotificationValue ), ( xTicksToWait ) )
ŽxTaskNotifyGive(xTaskToNotify) xTaskGenericNotify( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( 0 ), eIncrement, NULL )
xTaskNotifyGiveIndexed(xTaskToNotify,uxIndexToNotify) xTaskGenericNotify( ( xTaskToNotify ), ( uxIndexToNotify ), ( 0 ), eIncrement, NULL )
åvTaskNotifyGiveFromISR(xTaskToNotify,pxHigherPriorityTaskWoken) vTaskGenericNotifyGiveFromISR( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( pxHigherPriorityTaskWoken ) )
çvTaskNotifyGiveIndexedFromISR(xTaskToNotify,uxIndexToNotify,pxHigherPriorityTaskWoken) vTaskGenericNotifyGiveFromISR( ( xTaskToNotify ), ( uxIndexToNotify ), ( pxHigherPriorityTaskWoken ) )
ÏulTaskNotifyTake(xClearCountOnExit,xTicksToWait) ulTaskGenericNotifyTake( ( tskDEFAULT_INDEX_TO_NOTIFY ), ( xClearCountOnExit ), ( xTicksToWait ) )
ÑulTaskNotifyTakeIndexed(uxIndexToWaitOn,xClearCountOnExit,xTicksToWait) ulTaskGenericNotifyTake( ( uxIndexToWaitOn ), ( xClearCountOnExit ), ( xTicksToWait ) )
xTaskNotifyStateClear(xTask) xTaskGenericNotifyStateClear( ( xTask ), ( tskDEFAULT_INDEX_TO_NOTIFY ) )
‘xTaskNotifyStateClearIndexed(xTask,uxIndexToClear) xTaskGenericNotifyStateClear( ( xTask ), ( uxIndexToClear ) )
ÑulTaskNotifyValueClear(xTask,ulBitsToClear) ulTaskGenericNotifyValueClear( ( xTask ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulBitsToClear ) )
ÓulTaskNotifyValueClearIndexed(xTask,uxIndexToClear,ulBitsToClear) ulTaskGenericNotifyValueClear( ( xTask ), ( uxIndexToClear ), ( ulBitsToClear ) )TH
 




..\..\..\..\os\freertos\include\task.h
list.h


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..\..\..\..\os\freertos\include\task.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xuvoid
char"Ü"åPTaskHandle_tá
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QUEUE_H +
DqueueSEND_TO_BACK ( ( BaseType_t ) 0 )
EqueueSEND_TO_FRONT ( ( BaseType_t ) 1 )
FqueueOVERWRITE ( ( BaseType_t ) 2 )
IqueueQUEUE_TYPE_BASE ( ( uint8_t ) 0U )
JqueueQUEUE_TYPE_SET ( ( uint8_t ) 0U )
KqueueQUEUE_TYPE_MUTEX ( ( uint8_t ) 1U )
LqueueQUEUE_TYPE_COUNTING_SEMAPHORE ( ( uint8_t ) 2U )
MqueueQUEUE_TYPE_BINARY_SEMAPHORE ( ( uint8_t ) 3U )
NqueueQUEUE_TYPE_RECURSIVE_MUTEX ( ( uint8_t ) 4U )
•
xQueueCreate(uxQueueLength,uxItemSize) xQueueGenericCreate( ( uxQueueLength ), ( uxItemSize ), ( queueQUEUE_TYPE_BASE ) )
¼xQueueSendToFront(xQueue,pvItemToQueue,xTicksToWait) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT )
xQueueSendToBack(xQueue,pvItemToQueue,xTicksToWait) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )
äxQueueSend(xQueue,pvItemToQueue,xTicksToWait) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )
¸xQueueOverwrite(xQueue,pvItemToQueue) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), 0, queueOVERWRITE )
ðxQueueSendToFrontFromISR(xQueue,pvItemToQueue,pxHigherPriorityTaskWoken) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_FRONT )
¸xQueueSendToBackFromISR(xQueue,pvItemToQueue,pxHigherPriorityTaskWoken) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )
    xQueueOverwriteFromISR(xQueue,pvItemToQueue,pxHigherPriorityTaskWoken) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueOVERWRITE )
Û    xQueueSendFromISR(xQueue,pvItemToQueue,pxHigherPriorityTaskWoken) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )
ÉxQueueReset(xQueue) xQueueGenericReset( ( xQueue ), pdFALSE )TI
 




..\..\..\..\os\freertos\include\queue.h
task.h


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SEMAPHORE_H $
(semBINARY_SEMAPHORE_QUEUE_LENGTH ( ( uint8_t ) 1U )
)semSEMAPHORE_QUEUE_ITEM_LENGTH ( ( uint8_t ) 0U )
*semGIVE_BLOCK_TIME ( ( TickType_t ) 0U )
avSemaphoreCreateBinary(xSemaphore) { ( xSemaphore ) = xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE ); if( ( xSemaphore ) != NULL ) { ( void ) xSemaphoreGive( ( xSemaphore ) ); } }
§
xSemaphoreCreateBinary() xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE )
ªxSemaphoreTake(xSemaphore,xBlockTime) xQueueSemaphoreTake( ( xSemaphore ), ( xBlockTime ) )
ŠxSemaphoreTakeRecursive(xMutex,xBlockTime) xQueueTakeMutexRecursive( ( xMutex ), ( xBlockTime ) )
ÌxSemaphoreGive(xSemaphore) xQueueGenericSend( ( QueueHandle_t ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK )
£xSemaphoreGiveRecursive(xMutex) xQueueGiveMutexRecursive( ( xMutex ) )
€xSemaphoreGiveFromISR(xSemaphore,pxHigherPriorityTaskWoken) xQueueGiveFromISR( ( QueueHandle_t ) ( xSemaphore ), ( pxHigherPriorityTaskWoken ) )
£xSemaphoreTakeFromISR(xSemaphore,pxHigherPriorityTaskWoken) xQueueReceiveFromISR( ( QueueHandle_t ) ( xSemaphore ), NULL, ( pxHigherPriorityTaskWoken ) )
ßxSemaphoreCreateMutex() xQueueCreateMutex( queueQUEUE_TYPE_MUTEX )
äxSemaphoreCreateRecursiveMutex() xQueueCreateMutex( queueQUEUE_TYPE_RECURSIVE_MUTEX )
xSemaphoreCreateCounting(uxMaxCount,uxInitialCount) xQueueCreateCountingSemaphore( ( uxMaxCount ), ( uxInitialCount ) )
évSemaphoreDelete(xSemaphore) vQueueDelete( ( QueueHandle_t ) ( xSemaphore ) )
ûxSemaphoreGetMutexHolder(xSemaphore) xQueueGetMutexHolder( ( xSemaphore ) )
Š    xSemaphoreGetMutexHolderFromISR(xSemaphore) xQueueGetMutexHolderFromISR( ( xSemaphore ) )
™    uxSemaphoreGetCount(xSemaphore) uxQueueMessagesWaiting( ( QueueHandle_t ) ( xSemaphore ) )
§    uxSemaphoreGetCountFromISR(xSemaphore) uxQueueMessagesWaitingFromISR( ( QueueHandle_t ) ( xSemaphore ) )TK
 




..\..\..\..\os\freertos\include\semphr.h
queue.h


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..\..\..\..\os\freertos\include\semphr.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xPSemaphoreHandle_tò
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TIMERS_H '
9tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR ( ( BaseType_t ) -2 )
:tmrCOMMAND_EXECUTE_CALLBACK ( ( BaseType_t ) -1 )
;tmrCOMMAND_START_DONT_TRACE ( ( BaseType_t ) 0 )
<tmrCOMMAND_START ( ( BaseType_t ) 1 )
=tmrCOMMAND_RESET ( ( BaseType_t ) 2 )
>tmrCOMMAND_STOP ( ( BaseType_t ) 3 )
?tmrCOMMAND_CHANGE_PERIOD ( ( BaseType_t ) 4 )
@tmrCOMMAND_DELETE ( ( BaseType_t ) 5 )
BtmrFIRST_FROM_ISR_COMMAND ( ( BaseType_t ) 6 )
CtmrCOMMAND_START_FROM_ISR ( ( BaseType_t ) 6 )
DtmrCOMMAND_RESET_FROM_ISR ( ( BaseType_t ) 7 )
EtmrCOMMAND_STOP_FROM_ISR ( ( BaseType_t ) 8 )
FtmrCOMMAND_CHANGE_PERIOD_FROM_ISR ( ( BaseType_t ) 9 )
ýxTimerStart(xTimer,xTicksToWait) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )
¨xTimerStop(xTimer,xTicksToWait) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP, 0U, NULL, ( xTicksToWait ) )
ùxTimerChangePeriod(xTimer,xNewPeriod,xTicksToWait) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD, ( xNewPeriod ), NULL, ( xTicksToWait ) )
 xTimerDelete(xTimer,xTicksToWait) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_DELETE, 0U, NULL, ( xTicksToWait ) )
xTimerReset(xTimer,xTicksToWait) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )
ôxTimerStartFromISR(xTimer,pxHigherPriorityTaskWoken) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )
´xTimerStopFromISR(xTimer,pxHigherPriorityTaskWoken) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP_FROM_ISR, 0, ( pxHigherPriorityTaskWoken ), 0U )
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..\..\..\..\os\freertos\include\timers.h
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fPRIxLEAST16 "x"
gPRIxLEAST32 "x"
hPRIxLEAST64 __PRISCN64 "x"
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C:\Keil_v5\ARM\ARMCC\Bin\..\include\inttypes.h
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¸LIST_INSERT_HEAD(head,elm,field) do { if ((LIST_NEXT((elm), field) = LIST_FIRST((head))) != NULL) LIST_FIRST((head))->field.le_prev = &LIST_NEXT((elm), field); LIST_FIRST((head)) = (elm); (elm)->field.le_prev = &LIST_FIRST((head)); } while (0)
¿LIST_NEXT(elm,field) ((elm)->field.le_next)
ÁLIST_REMOVE(elm,field) do { if (LIST_NEXT((elm), field) != NULL) LIST_NEXT((elm), field)->field.le_prev = (elm)->field.le_prev; *(elm)->field.le_prev = LIST_NEXT((elm), field); } while (0)
ËTAILQ_HEAD(name,type) struct name { struct type *tqh_first; struct type **tqh_last; }
ÑTAILQ_HEAD_INITIALIZER(head) { NULL, &(head).tqh_first }
ÔTAILQ_ENTRY(type) struct { struct type *tqe_next; struct type **tqe_prev; }
ÝTAILQ_EMPTY(head) ((head)->tqh_first == NULL)
ßTAILQ_FIRST(head) ((head)->tqh_first)
áTAILQ_FOREACH(var,head,field) for ((var) = TAILQ_FIRST((head)); (var); (var) = TAILQ_NEXT((var), field))
æTAILQ_FOREACH_REVERSE(var,head,headname,field) for ((var) = TAILQ_LAST((head), headname); (var); (var) = TAILQ_PREV((var), headname, field))
ëTAILQ_INIT(head) do { TAILQ_FIRST((head)) = NULL; (head)->tqh_last = &TAILQ_FIRST((head)); } while (0)
ðTAILQ_INSERT_AFTER(head,listelm,elm,field) do { if ((TAILQ_NEXT((elm), field) = TAILQ_NEXT((listelm), field)) != NULL) TAILQ_NEXT((elm), field)->field.tqe_prev = &TAILQ_NEXT((elm), field); else (head)->tqh_last = &TAILQ_NEXT((elm), field); TAILQ_NEXT((listelm), field) = (elm); (elm)->field.tqe_prev = &TAILQ_NEXT((listelm), field); } while (0)
úTAILQ_INSERT_BEFORE(listelm,elm,field) do { (elm)->field.tqe_prev = (listelm)->field.tqe_prev; TAILQ_NEXT((elm), field) = (listelm); *(listelm)->field.tqe_prev = (elm); (listelm)->field.tqe_prev = &TAILQ_NEXT((elm), field); } while (0)
TAILQ_INSERT_HEAD(head,elm,field) do { if ((TAILQ_NEXT((elm), field) = TAILQ_FIRST((head))) != NULL) TAILQ_FIRST((head))->field.tqe_prev = &TAILQ_NEXT((elm), field); else (head)->tqh_last = &TAILQ_NEXT((elm), field); TAILQ_FIRST((head)) = (elm); (elm)->field.tqe_prev = &TAILQ_FIRST((head)); } while (0)
‹TAILQ_INSERT_TAIL(head,elm,field) do { TAILQ_NEXT((elm), field) = NULL; (elm)->field.tqe_prev = (head)->tqh_last; *(head)->tqh_last = (elm); (head)->tqh_last = &TAILQ_NEXT((elm), field); } while (0)
’TAILQ_LAST(head,headname) (*(((struct headname *)((head)->tqh_last))->tqh_last))
•TAILQ_NEXT(elm,field) ((elm)->field.tqe_next)
—TAILQ_PREV(elm,headname,field) (*(((struct headname *)((elm)->field.tqe_prev))->tqh_last))
šTAILQ_REMOVE(head,elm,field) do { if ((TAILQ_NEXT((elm), field)) != NULL) TAILQ_NEXT((elm), field)->field.tqe_prev = (elm)->field.tqe_prev; else (head)->tqh_last = (elm)->field.tqe_prev; *(elm)->field.tqe_prev = TAILQ_NEXT((elm), field); } while (0)
¦CIRCLEQ_HEAD(name,type) struct name { struct type *cqh_first; struct type *cqh_last; }
¬CIRCLEQ_HEAD_INITIALIZER(head) { (void *)&(head), (void *)&(head) }
¯CIRCLEQ_ENTRY(type) struct { struct type *cqe_next; struct type *cqe_prev; }
¸CIRCLEQ_EMPTY(head) ((head)->cqh_first == (void *)(head))
ºCIRCLEQ_FIRST(head) ((head)->cqh_first)
¼CIRCLEQ_FOREACH(var,head,field) for ((var) = CIRCLEQ_FIRST((head)); (var) != (void *)(head) || ((var) = NULL); (var) = CIRCLEQ_NEXT((var), field))
ÁCIRCLEQ_FOREACH_REVERSE(var,head,field) for ((var) = CIRCLEQ_LAST((head)); (var) != (void *)(head) || ((var) = NULL); (var) = CIRCLEQ_PREV((var), field))
ÆCIRCLEQ_INIT(head) do { CIRCLEQ_FIRST((head)) = (void *)(head); CIRCLEQ_LAST((head)) = (void *)(head); } while (0)
ËCIRCLEQ_INSERT_AFTER(head,listelm,elm,field) do { CIRCLEQ_NEXT((elm), field) = CIRCLEQ_NEXT((listelm), field); CIRCLEQ_PREV((elm), field) = (listelm); if (CIRCLEQ_NEXT((listelm), field) == (void *)(head)) CIRCLEQ_LAST((head)) = (elm); else CIRCLEQ_PREV(CIRCLEQ_NEXT((listelm), field), field) = (elm); CIRCLEQ_NEXT((listelm), field) = (elm); } while (0)
ÕCIRCLEQ_INSERT_BEFORE(head,listelm,elm,field) do { CIRCLEQ_NEXT((elm), field) = (listelm); CIRCLEQ_PREV((elm), field) = CIRCLEQ_PREV((listelm), field); if (CIRCLEQ_PREV((listelm), field) == (void *)(head)) CIRCLEQ_FIRST((head)) = (elm); else CIRCLEQ_NEXT(CIRCLEQ_PREV((listelm), field), field) = (elm); CIRCLEQ_PREV((listelm), field) = (elm); } while (0)
ßCIRCLEQ_INSERT_HEAD(head,elm,field) do { CIRCLEQ_NEXT((elm), field) = CIRCLEQ_FIRST((head)); CIRCLEQ_PREV((elm), field) = (void *)(head); if (CIRCLEQ_LAST((head)) == (void *)(head)) CIRCLEQ_LAST((head)) = (elm); else CIRCLEQ_PREV(CIRCLEQ_FIRST((head)), field) = (elm); CIRCLEQ_FIRST((head)) = (elm); } while (0)
éCIRCLEQ_INSERT_TAIL(head,elm,field) do { CIRCLEQ_NEXT((elm), field) = (void *)(head); CIRCLEQ_PREV((elm), field) = CIRCLEQ_LAST((head)); if (CIRCLEQ_FIRST((head)) == (void *)(head)) CIRCLEQ_FIRST((head)) = (elm); else CIRCLEQ_NEXT(CIRCLEQ_LAST((head)), field) = (elm); CIRCLEQ_LAST((head)) = (elm); } while (0)
óCIRCLEQ_LAST(head) ((head)->cqh_last)
õCIRCLEQ_NEXT(elm,field) ((elm)->field.cqe_next)
÷CIRCLEQ_PREV(elm,field) ((elm)->field.cqe_prev)
ùCIRCLEQ_REMOVE(head,elm,field) do { if (CIRCLEQ_NEXT((elm), field) == (void *)(head)) CIRCLEQ_LAST((head)) = CIRCLEQ_PREV((elm), field); else CIRCLEQ_PREV(CIRCLEQ_NEXT((elm), field), field) = CIRCLEQ_PREV((elm), field); if (CIRCLEQ_PREV((elm), field) == (void *)(head)) CIRCLEQ_FIRST((head)) = CIRCLEQ_NEXT((elm), field); else CIRCLEQ_NEXT(CIRCLEQ_PREV((elm), field), field) = CIRCLEQ_NEXT((elm), field); } while (0)\Q
 




..\..\..\..\host\nimble\porting\nimble\include\os/queue.h


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..\..\..\..\host\nimble\porting\nimble\include\os/queue.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x
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_OS_H 
min(a,b) ((a)<(b)?(a):(b))
"max(a,b) ((a)>(b)?(a):(b))%&
(OS_ALIGN(__n,__a) ( (((__n) & ((__a) - 1)) == 0) ? (__n) : ((__n) + ((__a) - ((__n) & ((__a) - 1)))) )
-OS_ALIGNMENT (BLE_NPL_OS_ALIGNMENT)
0OS_ENTER_CRITICAL(_sr) (_sr = ble_npl_hw_enter_critical())
1OS_EXIT_CRITICAL(_sr) (ble_npl_hw_exit_critical(_sr))
2OS_ASSERT_CRITICAL() assert(ble_npl_hw_is_in_critical())56789    <

=nimble_mem_alloc(size) pvPortMalloc(size)
>nimble_mem_free(p) vPortFree(p)d
Z

 




..\..\..\..\host\nimble\porting\nimble\include\C:\Keil_v5\ARM\ARMCC\Bin\..\include\..\..\..\..\config\..\..\..\..\host\nimble\nimble\include\..\..\..\..\utilities\os/os.h
assert.hnimble_syscfg.hnimble/nimble_npl.hos/endian.h
os/queue.h
os/os_error.h
os/os_mbuf.h
os/os_mempool.h
utility.h

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..\..\..\..\host\nimble\porting\nimble\include\os/os.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xPos_sr_tY

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H_OS_ERROR_ h_
 




..\..\..\..\host\nimble\porting\nimble\include\os/os_error.h
os/os.h


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..\..\..\..\host\nimble\porting\nimble\include\os/os_error.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xÁos_error
OS_OKOS_ENOMEM
OS_EINVALOS_INVALID_PARMOS_MEM_NOT_ALIGNEDOS_BAD_MUTEXOS_TIMEOUTOS_ERR_IN_ISROS_ERR_PRIVOS_NOT_STARTED    OS_ENOENT
OS_EBUSYOS_ERRORPos_error_tò
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_OS_MBUF_H  
|OS_MBUF_F_MASK(__n) (1 << (__n))
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OS_MBUF_IS_PKTHDR(__om) ((__om)->om_pkthdr_len >= sizeof (struct os_mbuf_pkthdr))
‡
OS_MBUF_PKTHDR(__om) ((struct os_mbuf_pkthdr *) (void *)((uint8_t *)&(__om)->om_data + sizeof(struct os_mbuf)))
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OS_MBUF_PKTHDR_TO_MBUF(__hdr) (struct os_mbuf *)(void *)((uint8_t *)(__hdr) - sizeof(struct os_mbuf))
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OS_MBUF_PKTLEN(__om) (OS_MBUF_PKTHDR(__om)->omp_len)
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OS_MBUF_DATA(__om,__type) (__type) ((__om)->om_data)
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OS_MBUF_USRHDR(om) (void *)((uint8_t *)om + sizeof (struct os_mbuf) + sizeof (struct os_mbuf_pkthdr))
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OS_MBUF_USRHDR_LEN(om) ((om)->om_pkthdr_len - sizeof (struct os_mbuf_pkthdr))
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OS_MBUF_LEADINGSPACE(__om) _os_mbuf_leadingspace(__om)
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OS_MBUF_TRAILINGSPACE(__om) _os_mbuf_trailingspace(__om)h^
 




..\..\..\..\host\nimble\porting\nimble\include\os/os_mbuf.h
os/os.h


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..\..\..\..\host\nimble\porting\nimble\include\os/os_mbuf.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x*‹"
stqe_nextõ#)Üos_mbuf_poolomp_databuf_lenI
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_OS_MEMPOOL_H_  !
POS_MEMPOOL_F_EXT 0x01
qOS_MEMPOOL_INFO_NAME_LEN (32)
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OS_MEMPOOL_BLOCK_SZ(sz) (sz)
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OS_MEMPOOL_SIZE(n,blksize) ((((blksize) + ((OS_ALIGNMENT)-1)) / (OS_ALIGNMENT)) * (n))
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OS_MEMPOOL_BYTES(n,blksize) (sizeof (os_membuf_t) * OS_MEMPOOL_SIZE((n), (blksize)))¬¡
 




..\..\..\..\host\nimble\porting\nimble\include\C:\Keil_v5\ARM\ARMCC\Bin\..\include\os/os_mempool.h
stdbool.hos/os.h
os/queue.h


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..\..\..\..\host\nimble\porting\nimble\include\os/os_mempool.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x
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BYTES_H pf
 




..\..\..\..\utilities\C:\Keil_v5\ARM\ARMCC\Bin\..\include\bytes.h
stdint.h

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..\..\..\..\utilities\bytes.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x
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OS_WRAPPER 
OS_MS_TO_TICK(ms) pdMS_TO_TICKS(ms)
OS_TICK_TO_MS(t) ((t) * 1000/configTICK_RATE_HZ)ȼ
 




..\..\..\..\utilities\C:\Keil_v5\ARM\ARMCC\Bin\..\include\..\..\..\..\os\freertos\include\os_wrapper.h
stdint.hFreeRTOS.htask.hsemphr.htimers.h

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..\..\..\..\utilities\os_wrapper.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x
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UTILITY_H     
CRITICAL_REGION_ENTER(state) state = critical_region_enter()
CRITICAL_REGION_EXIT(state) critical_region_exit(state)œ
 




..\..\..\..\utilities\C:\Keil_v5\ARM\ARMCC\Bin\..\include\utility.h
stdint.hstdbool.hbytes.h
os_wrapper.h


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..\..\..\..\utilities\utility.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x
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H_NIMBLE_OPT_AUTO_ $NIMBLE_BLE_ADVERTISE
%NIMBLE_BLE_ADVERTISE (MYNEWT_VAL(BLE_ROLE_BROADCASTER) || MYNEWT_VAL(BLE_ROLE_PERIPHERAL))(NIMBLE_BLE_SCAN
)NIMBLE_BLE_SCAN (MYNEWT_VAL(BLE_ROLE_CENTRAL) || MYNEWT_VAL(BLE_ROLE_OBSERVER)),NIMBLE_BLE_CONNECT
-NIMBLE_BLE_CONNECT (MYNEWT_VAL(BLE_ROLE_CENTRAL) || MYNEWT_VAL(BLE_ROLE_PERIPHERAL))3NIMBLE_BLE_ATT_CLT_FIND_INFO
4NIMBLE_BLE_ATT_CLT_FIND_INFO (MYNEWT_VAL(BLE_GATT_DISC_ALL_DSCS))7NIMBLE_BLE_ATT_CLT_FIND_TYPE
8NIMBLE_BLE_ATT_CLT_FIND_TYPE (MYNEWT_VAL(BLE_GATT_DISC_SVC_UUID));NIMBLE_BLE_ATT_CLT_READ_TYPE
<NIMBLE_BLE_ATT_CLT_READ_TYPE (MYNEWT_VAL(BLE_GATT_FIND_INC_SVCS) || MYNEWT_VAL(BLE_GATT_DISC_ALL_CHRS) || MYNEWT_VAL(BLE_GATT_DISC_CHRS_UUID) || MYNEWT_VAL(BLE_GATT_READ_UUID))BNIMBLE_BLE_ATT_CLT_READ
CNIMBLE_BLE_ATT_CLT_READ (MYNEWT_VAL(BLE_GATT_READ) || MYNEWT_VAL(BLE_GATT_READ_LONG) || MYNEWT_VAL(BLE_GATT_FIND_INC_SVCS))HNIMBLE_BLE_ATT_CLT_READ_BLOB
INIMBLE_BLE_ATT_CLT_READ_BLOB (MYNEWT_VAL(BLE_GATT_READ_LONG))LNIMBLE_BLE_ATT_CLT_READ_MULT
MNIMBLE_BLE_ATT_CLT_READ_MULT (MYNEWT_VAL(BLE_GATT_READ_MULT))PNIMBLE_BLE_ATT_CLT_READ_GROUP_TYPE
QNIMBLE_BLE_ATT_CLT_READ_GROUP_TYPE (MYNEWT_VAL(BLE_GATT_DISC_ALL_SVCS))TNIMBLE_BLE_ATT_CLT_WRITE
UNIMBLE_BLE_ATT_CLT_WRITE (MYNEWT_VAL(BLE_GATT_WRITE))XNIMBLE_BLE_ATT_CLT_WRITE_NO_RSP
YNIMBLE_BLE_ATT_CLT_WRITE_NO_RSP (MYNEWT_VAL(BLE_GATT_WRITE_NO_RSP))\NIMBLE_BLE_ATT_CLT_PREP_WRITE
]NIMBLE_BLE_ATT_CLT_PREP_WRITE (MYNEWT_VAL(BLE_GATT_WRITE_LONG))`NIMBLE_BLE_ATT_CLT_EXEC_WRITE
aNIMBLE_BLE_ATT_CLT_EXEC_WRITE (MYNEWT_VAL(BLE_GATT_WRITE_LONG))dNIMBLE_BLE_ATT_CLT_NOTIFY
eNIMBLE_BLE_ATT_CLT_NOTIFY (MYNEWT_VAL(BLE_GATT_NOTIFY))hNIMBLE_BLE_ATT_CLT_INDICATE
iNIMBLE_BLE_ATT_CLT_INDICATE (MYNEWT_VAL(BLE_GATT_INDICATE))nNIMBLE_BLE_SM
oNIMBLE_BLE_SM (MYNEWT_VAL(BLE_SM_LEGACY) || MYNEWT_VAL(BLE_SM_SC))ˆ~
 




..\..\..\..\host\nimble\nimble\include\..\..\..\..\config\nimble/nimble_opt_auto.h
nimble_syscfg.h

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..\..\..\..\host\nimble\nimble\include\nimble/nimble_opt_auto.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x
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H_NIMBLE_OPT_ xn
 




..\..\..\..\host\nimble\nimble\include\nimble/nimble_opt.h
nimble/nimble_opt_auto.h


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..\..\..\..\host\nimble\nimble\include\nimble/nimble_opt.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x
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H_BLE_L2CAP_ 
BLE_L2CAP_CID_ATT 4
 BLE_L2CAP_CID_SIG 5
!BLE_L2CAP_CID_SM 6
#BLE_L2CAP_SIG_OP_REJECT 0x01
$BLE_L2CAP_SIG_OP_CONNECT_REQ 0x02
%BLE_L2CAP_SIG_OP_CONNECT_RSP 0x03
&BLE_L2CAP_SIG_OP_CONFIG_REQ 0x04
'BLE_L2CAP_SIG_OP_CONFIG_RSP 0x05
(BLE_L2CAP_SIG_OP_DISCONN_REQ 0x06
)BLE_L2CAP_SIG_OP_DISCONN_RSP 0x07
*BLE_L2CAP_SIG_OP_ECHO_REQ 0x08
+BLE_L2CAP_SIG_OP_ECHO_RSP 0x09
,BLE_L2CAP_SIG_OP_INFO_REQ 0x0a
-BLE_L2CAP_SIG_OP_INFO_RSP 0x0b
.BLE_L2CAP_SIG_OP_CREATE_CHAN_REQ 0x0c
/BLE_L2CAP_SIG_OP_CREATE_CHAN_RSP 0x0d
0BLE_L2CAP_SIG_OP_MOVE_CHAN_REQ 0x0e
1BLE_L2CAP_SIG_OP_MOVE_CHAN_RSP 0x0f
2BLE_L2CAP_SIG_OP_MOVE_CHAN_CONF_REQ 0x10
3BLE_L2CAP_SIG_OP_MOVE_CHAN_CONF_RSP 0x11
4BLE_L2CAP_SIG_OP_UPDATE_REQ 0x12
5BLE_L2CAP_SIG_OP_UPDATE_RSP 0x13
6BLE_L2CAP_SIG_OP_LE_CREDIT_CONNECT_REQ 0x14
7BLE_L2CAP_SIG_OP_LE_CREDIT_CONNECT_RSP 0x15
8BLE_L2CAP_SIG_OP_FLOW_CTRL_CREDIT 0x16
9BLE_L2CAP_SIG_OP_CREDIT_CONNECT_REQ 0x17
:BLE_L2CAP_SIG_OP_CREDIT_CONNECT_RSP 0x18
;BLE_L2CAP_SIG_OP_CREDIT_RECONFIG_REQ 0x19
<BLE_L2CAP_SIG_OP_CREDIT_RECONFIG_RSP 0x1A
=BLE_L2CAP_SIG_OP_MAX 0x1B
?BLE_L2CAP_SIG_ERR_CMD_NOT_UNDERSTOOD 0x0000
@BLE_L2CAP_SIG_ERR_MTU_EXCEEDED 0x0001
ABLE_L2CAP_SIG_ERR_INVALID_CID 0x0002
CBLE_L2CAP_COC_ERR_CONNECTION_SUCCESS 0x0000
DBLE_L2CAP_COC_ERR_UNKNOWN_LE_PSM 0x0002
EBLE_L2CAP_COC_ERR_NO_RESOURCES 0x0004
FBLE_L2CAP_COC_ERR_INSUFFICIENT_AUTHEN 0x0005
GBLE_L2CAP_COC_ERR_INSUFFICIENT_AUTHOR 0x0006
HBLE_L2CAP_COC_ERR_INSUFFICIENT_KEY_SZ 0x0007
IBLE_L2CAP_COC_ERR_INSUFFICIENT_ENC 0x0008
JBLE_L2CAP_COC_ERR_INVALID_SOURCE_CID 0x0009
KBLE_L2CAP_COC_ERR_SOURCE_CID_ALREADY_USED 0x000A
LBLE_L2CAP_COC_ERR_UNACCEPTABLE_PARAMETERS 0x000B
MBLE_L2CAP_COC_ERR_INVALID_PARAMETERS 0x000C
OBLE_L2CAP_ERR_RECONFIG_SUCCEED 0x0000
PBLE_L2CAP_ERR_RECONFIG_REDUCTION_MTU_NOT_ALLOWED 0x0001
QBLE_L2CAP_ERR_RECONFIG_REDUCTION_MPS_NOT_ALLOWED 0x0002
RBLE_L2CAP_ERR_RECONFIG_INVALID_DCID 0x0003
SBLE_L2CAP_ERR_RECONFIG_UNACCAPTED_PARAM 0x0004
UBLE_L2CAP_EVENT_COC_CONNECTED 0
VBLE_L2CAP_EVENT_COC_DISCONNECTED 1
WBLE_L2CAP_EVENT_COC_ACCEPT 2
XBLE_L2CAP_EVENT_COC_DATA_RECEIVED 3
YBLE_L2CAP_EVENT_COC_TX_UNSTALLED 4
ZBLE_L2CAP_EVENT_COC_RECONFIG_COMPLETED 5
[BLE_L2CAP_EVENT_COC_PEER_RECONFIGURED 6œ“
 




..\..\..\..\host\nimble\nimble\host\include\..\..\..\..\host\nimble\nimble\include\host/ble_l2cap.h
nimble/nimble_opt.h

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aBLE_MBUF_HDR_F_SCAN_REQ_TXD (0x4000)
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cBLE_MBUF_HDR_F_TARGETA_RESOLVED (0x2000)
dBLE_MBUF_HDR_F_EXT_ADV_SEC (0x1000)
eBLE_MBUF_HDR_F_EXT_ADV (0x0800)
fBLE_MBUF_HDR_F_RESOLVED (0x0400)
gBLE_MBUF_HDR_F_AUX_PTR_WAIT (0x0200)
hBLE_MBUF_HDR_F_AUX_INVALID (0x0100)
iBLE_MBUF_HDR_F_CRC_OK (0x0080)
jBLE_MBUF_HDR_F_DEVMATCH (0x0040)
kBLE_MBUF_HDR_F_MIC_FAILURE (0x0020)
lBLE_MBUF_HDR_F_SCAN_RSP_TXD (0x0010)
mBLE_MBUF_HDR_F_SCAN_RSP_RXD (0x0008)
nBLE_MBUF_HDR_F_RXSTATE_MASK (0x0007)
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BLE_MBUF_HDR_INITA_RESOLVED(hdr) (!!((hdr)->rxinfo.flags & BLE_MBUF_HDR_F_INITA_RESOLVED))
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²
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“BLE_OWN_ADDR_RPA_PUBLIC_DEFAULT (0x02)
”BLE_OWN_ADDR_RPA_RANDOM_DEFAULT (0x03)
—BLE_ADDR_PUBLIC (0x00)
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™BLE_ADDR_PUBLIC_ID (0x02)
šBLE_ADDR_RANDOM_ID (0x03)
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¢BLE_ADDR_IS_STATIC(addr) (((addr)->type == BLE_ADDR_RANDOM) && ((addr)->val[5] & 0xc0) == 0xc0)0
$

 




..\..\..\..\host\nimble\nimble\include\C:\Keil_v5\ARM\ARMCC\Bin\..\include\..\..\..\..\config\..\..\..\..\host\nimble\porting\nimble\include\..\..\..\..\host\nimble\nimble\include\nimble/nimble/ble.h
inttypes.hstring.hnimble_syscfg.hos/os.hble.h


 
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..\..\..\..\host\nimble\nimble\transport\include\..\..\..\..\config\nimble/transport/monitor.h
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2BLE_HCI_OP(ogf,ocf) ((ocf) | ((ogf) << 10))
5BLE_HCI_OGF(opcode) (((opcode) >> 10) & 0x003F)
6BLE_HCI_OCF(opcode) ((opcode) & 0x03FF)
9BLE_HCI_OGF_LINK_CTRL (0x01)
:BLE_HCI_OGF_LINK_POLICY (0x02)
;BLE_HCI_OGF_CTLR_BASEBAND (0x03)
<BLE_HCI_OGF_INFO_PARAMS (0x04)
=BLE_HCI_OGF_STATUS_PARAMS (0x05)
>BLE_HCI_OGF_TESTING (0x06)
?BLE_HCI_OGF_LE (0x08)
@BLE_HCI_OGF_VENDOR (0x3F)
FBLE_HCI_NUM_LE_CMDS (79)
IBLE_HCI_OCF_DISCONNECT_CMD (0x0006)
OBLE_HCI_OCF_RD_REM_VER_INFO (0x001D)
UBLE_HCI_OCF_CB_SET_EVENT_MASK (0x0001)
ZBLE_HCI_OCF_CB_RESET (0x0003)
\BLE_HCI_OCF_CB_READ_TX_PWR (0x002D)
hBLE_HCI_OCF_CB_SET_CTLR_TO_HOST_FC (0x0031)
mBLE_HCI_OCF_CB_HOST_BUF_SIZE (0x0033)
uBLE_HCI_OCF_CB_HOST_NUM_COMP_PKTS (0x0035)
BLE_HCI_OCF_CB_SET_EVENT_MASK2 (0x0063)
„
BLE_HCI_OCF_CB_RD_AUTH_PYLD_TMO (0x007B)

BLE_HCI_OCF_CB_WR_AUTH_PYLD_TMO (0x007C)
—
BLE_HCI_OCF_IP_RD_LOCAL_VER (0x0001)
 
BLE_HCI_OCF_IP_RD_LOC_SUPP_CMD (0x0002)
¥
BLE_HCI_OCF_IP_RD_LOC_SUPP_FEAT (0x0003)
ª
BLE_HCI_OCF_IP_RD_BUF_SIZE (0x0005)
²
BLE_HCI_OCF_IP_RD_BD_ADDR (0x0009)
¸
BLE_HCI_OCF_RD_RSSI (0x0005)
Â
BLE_HCI_OCF_LE_SET_EVENT_MASK (0x0001)
Ç
BLE_HCI_OCF_LE_RD_BUF_SIZE (0x0002)
Í
BLE_HCI_OCF_LE_RD_BUF_SIZE_V2 (0x0060)
Õ
BLE_HCI_OCF_LE_RD_LOC_SUPP_FEAT (0x0003)
Û
BLE_HCI_OCF_LE_SET_RAND_ADDR (0x0005)
à
BLE_HCI_OCF_LE_SET_ADV_PARAMS (0x0006)
ì
BLE_HCI_OCF_LE_RD_ADV_CHAN_TXPWR (0x0007)
ñ
BLE_HCI_OCF_LE_SET_ADV_DATA (0x0008)
ò
BLE_HCI_MAX_ADV_DATA_LEN (31)
ø
BLE_HCI_OCF_LE_SET_SCAN_RSP_DATA (0x0009)
ù
BLE_HCI_MAX_SCAN_RSP_DATA_LEN (31)
ÿ
BLE_HCI_OCF_LE_SET_ADV_ENABLE (0x000A)
„BLE_HCI_OCF_LE_SET_SCAN_PARAMS (0x000B)
BLE_HCI_OCF_LE_SET_SCAN_ENABLE (0x000C)
“BLE_HCI_OCF_LE_CREATE_CONN (0x000D)
£BLE_HCI_OCF_LE_CREATE_CONN_CANCEL (0x000E)
¥BLE_HCI_OCF_LE_RD_WHITE_LIST_SIZE (0x000F)
ªBLE_HCI_OCF_LE_CLEAR_WHITE_LIST (0x0010)
¬BLE_HCI_OCF_LE_ADD_WHITE_LIST (0x0011)
²BLE_HCI_OCF_LE_RMV_WHITE_LIST (0x0012)
¸BLE_HCI_OCF_LE_CONN_UPDATE (0x0013)
ÃBLE_HCI_OCF_LE_SET_HOST_CHAN_CLASS (0x0014)
ÈBLE_HCI_OCF_LE_RD_CHAN_MAP (0x0015)
ÑBLE_HCI_OCF_LE_RD_REM_FEAT (0x0016)
ÖBLE_HCI_OCF_LE_ENCRYPT (0x0017)
ßBLE_HCI_OCF_LE_RAND (0x0018)
äBLE_HCI_OCF_LE_START_ENCRYPT (0x0019)
ìBLE_HCI_OCF_LE_LT_KEY_REQ_REPLY (0x001A)
õBLE_HCI_OCF_LE_LT_KEY_REQ_NEG_REPLY (0x001B)
ýBLE_HCI_OCF_LE_RD_SUPP_STATES (0x001C)
‚BLE_HCI_OCF_LE_RX_TEST (0x001D)
‡BLE_HCI_OCF_LE_TX_TEST (0x001E)
—BLE_HCI_OCF_LE_TEST_END (0x001F)
œBLE_HCI_OCF_LE_REM_CONN_PARAM_RR (0x0020)
ªBLE_HCI_OCF_LE_REM_CONN_PARAM_NRR (0x0021)
³BLE_HCI_OCF_LE_SET_DATA_LEN (0x0022)
½BLE_HCI_OCF_LE_RD_SUGG_DEF_DATA_LEN (0x0023)
ÃBLE_HCI_OCF_LE_WR_SUGG_DEF_DATA_LEN (0x0024)
ÉBLE_HCI_OCF_LE_RD_P256_PUBKEY (0x0025)
ËBLE_HCI_OCF_LE_GEN_DHKEY (0x0026)
ÐBLE_HCI_OCF_LE_ADD_RESOLV_LIST (0x0027)
ØBLE_HCI_OCF_LE_RMV_RESOLV_LIST (0x0028)
ÞBLE_HCI_OCF_LE_CLR_RESOLV_LIST (0x0029)
àBLE_HCI_OCF_LE_RD_RESOLV_LIST_SIZE (0x002A)
åBLE_HCI_OCF_LE_RD_PEER_RESOLV_ADDR (0x002B)
îBLE_HCI_OCF_LE_RD_LOCAL_RESOLV_ADDR (0x002C)
÷BLE_HCI_OCF_LE_SET_ADDR_RES_EN (0x002D)
üBLE_HCI_OCF_LE_SET_RPA_TMO (0x002E)
BLE_HCI_OCF_LE_RD_MAX_DATA_LEN (0x002F)
‰BLE_HCI_OCF_LE_RD_PHY (0x0030)
“BLE_HCI_OCF_LE_SET_DEFAULT_PHY (0x0031)
šBLE_HCI_OCF_LE_SET_PHY (0x0032)
£BLE_HCI_OCF_LE_RX_TEST_V2 (0x0033)
ªBLE_HCI_OCF_LE_TX_TEST_V2 (0x0034)
¼BLE_HCI_OCF_LE_SET_ADV_SET_RND_ADDR (0x0035)
ÂBLE_HCI_OCF_LE_SET_EXT_ADV_PARAM (0x0036)
ØBLE_HCI_OCF_LE_SET_EXT_ADV_DATA (0x0037)
áBLE_HCI_OCF_LE_SET_EXT_SCAN_RSP_DATA (0x0038)
êBLE_HCI_OCF_LE_SET_EXT_ADV_ENABLE (0x0039)
öBLE_HCI_OCF_LE_RD_MAX_ADV_DATA_LEN (0x003A)
ûBLE_HCI_OCF_LE_RD_NUM_OF_ADV_SETS (0x003B)
€BLE_HCI_OCF_LE_REMOVE_ADV_SET (0x003C)
…BLE_HCI_OCF_LE_CLEAR_ADV_SETS (0x003D)
‡BLE_HCI_OCF_LE_SET_PERIODIC_ADV_PARAMS (0x003E)
BLE_HCI_OCF_LE_SET_PERIODIC_ADV_DATA (0x003F)
—BLE_HCI_OCF_LE_SET_PERIODIC_ADV_ENABLE (0x0040)
BLE_HCI_OCF_LE_SET_EXT_SCAN_PARAM (0x0041)
ªBLE_HCI_OCF_LE_SET_EXT_SCAN_ENABLE (0x0042)
²BLE_HCI_OCF_LE_EXT_CREATE_CONN (0x0043)
ÆBLE_HCI_LE_PERIODIC_ADV_CREATE_SYNC_OPT_FILTER 0x01
ÇBLE_HCI_LE_PERIODIC_ADV_CREATE_SYNC_OPT_DISABLED 0x02
ÈBLE_HCI_LE_PERIODIC_ADV_CREATE_SYNC_OPT_DUPLICATES 0x04
ÊBLE_HCI_OCF_LE_PERIODIC_ADV_CREATE_SYNC (0x0044)
ÕBLE_HCI_OCF_LE_PERIODIC_ADV_CREATE_SYNC_CANCEL (0x0045)
×BLE_HCI_OCF_LE_PERIODIC_ADV_TERM_SYNC (0x0046)
ÜBLE_HCI_OCF_LE_ADD_DEV_TO_PERIODIC_ADV_LIST (0x0047)
ãBLE_HCI_OCF_LE_REM_DEV_FROM_PERIODIC_ADV_LIST (0x0048)
êBLE_HCI_OCF_LE_CLEAR_PERIODIC_ADV_LIST (0x0049)
ìBLE_HCI_OCF_LE_RD_PERIODIC_ADV_LIST_SIZE (0x004A)
ñBLE_HCI_OCF_LE_RD_TRANSMIT_POWER (0x004B)
÷BLE_HCI_OCF_LE_RD_RF_PATH_COMPENSATION (0x004C)
ýBLE_HCI_OCF_LE_WR_RF_PATH_COMPENSATION (0x004D)
ƒBLE_HCI_OCF_LE_SET_PRIVACY_MODE (0x004E)
ŠBLE_HCI_OCF_LE_RX_TEST_V3 (0x004F)
‹BLE_HCI_OCF_LE_TX_TEST_V3 (0x0050)
ŒBLE_HCI_OCF_LE_SET_CONNLESS_CTE_TX_PARAMS (0x0051)
BLE_HCI_OCF_LE_SET_CONNLESS_CTE_TX_ENABLE (0x0052)
ŽBLE_HCI_OCF_LE_SET_CONNLESS_IQ_SAMPLING_ENABLE (0x0053)
BLE_HCI_OCF_LE_SET_CONN_CTE_RX_PARAMS (0x0054)
BLE_HCI_OCF_LE_SET_CONN_CTE_TX_PARAMS (0x0055)
‘BLE_HCI_OCF_LE_SET_CONN_CTE_REQ_ENABLE (0x0056)
’BLE_HCI_OCF_LE_SET_CONN_CTE_RESP_ENABLE (0x0057)
“BLE_HCI_OCF_LE_RD_ANTENNA_INFO (0x0058)
•BLE_HCI_OCF_LE_PERIODIC_ADV_RECEIVE_ENABLE (0x0059)
›BLE_HCI_OCF_LE_PERIODIC_ADV_SYNC_TRANSFER (0x005A)
¥BLE_HCI_OCF_LE_PERIODIC_ADV_SET_INFO_TRANSFER (0x005B)
¯BLE_HCI_OCF_LE_PERIODIC_ADV_SYNC_TRANSFER_PARAMS (0x005C)
»BLE_HCI_OCF_LE_SET_DEFAULT_SYNC_TRANSFER_PARAMS (0x005D)
ÃBLE_HCI_OCF_LE_GENERATE_DHKEY_V2 (0x005E)
ÄBLE_HCI_OCF_LE_MODIFY_SCA (0x005F)
óBLE_HCI_OCF_LE_REQ_PEER_SCA (0x006d)
¤BLE_HCI_OCF_LE_SET_HOST_FEAT (0x0074)
ªBLE_HCI_OCF_LE_SET_DEFAULT_SUBRATE (0x007D)
³BLE_HCI_OCF_LE_SUBRATE_REQ (0x007E)
¿BLE_HCI_OCF_VS_RD_STATIC_ADDR (MYNEWT_VAL(BLE_HCI_VS_OCF_OFFSET) + (0x0001))
ÇBLE_HCI_OCF_VS_SET_TX_PWR (MYNEWT_VAL(BLE_HCI_VS_OCF_OFFSET) + (0x0002))
ÏBLE_HCI_OCF_VS_CSS (0x0003)
ÓBLE_HCI_VS_CSS_OP_CONFIGURE 0x01
ÙBLE_HCI_VS_CSS_OP_SET_NEXT_SLOT 0x02
ÞBLE_HCI_VS_CSS_OP_SET_CONN_SLOT 0x03
åBLE_HCI_OCF_LE_ENH_READ_TRANSMIT_POWER_LEVEL (0x0076)
òBLE_HCI_OCF_LE_READ_REMOTE_TRANSMIT_POWER_LEVEL (0x0077)
øBLE_HCI_OCF_LE_SET_PATH_LOSS_REPORT_PARAM (0x0078)
‚    BLE_HCI_OCF_LE_SET_PATH_LOSS_REPORT_ENABLE (0x0079)
ˆ    BLE_HCI_OCF_LE_SET_TRANS_PWR_REPORT_ENABLE (0x007A)
’    BLE_HCI_CTLR_TO_HOST_FC_OFF (0)
“    BLE_HCI_CTLR_TO_HOST_FC_ACL (1)
”    BLE_HCI_CTLR_TO_HOST_FC_SYNC (2)
•    BLE_HCI_CTLR_TO_HOST_FC_BOTH (3)
™    BLE_HCI_ADV_TYPE_ADV_IND (0)
š    BLE_HCI_ADV_TYPE_ADV_DIRECT_IND_HD (1)
›    BLE_HCI_ADV_TYPE_ADV_SCAN_IND (2)
œ    BLE_HCI_ADV_TYPE_ADV_NONCONN_IND (3)
    BLE_HCI_ADV_TYPE_ADV_DIRECT_IND_LD (4)
ž    BLE_HCI_ADV_TYPE_MAX (4)
     BLE_HCI_ADV_CONN_MASK (0x0001)
¡    BLE_HCI_ADV_SCAN_MASK (0x0002)
¢    BLE_HCI_ADV_DIRECT_MASK (0x0004)
£    BLE_HCI_ADV_SCAN_RSP_MASK (0x0008)
¤    BLE_HCI_ADV_LEGACY_MASK (0x0010)
¦    BLE_HCI_ADV_DATA_STATUS_COMPLETE (0x0000)
§    BLE_HCI_ADV_DATA_STATUS_INCOMPLETE (0x0020)
¨    BLE_HCI_ADV_DATA_STATUS_TRUNCATED (0x0040)
©    BLE_HCI_ADV_DATA_STATUS_MASK (0x0060)
¬    BLE_HCI_ADV_OWN_ADDR_PUBLIC (0)
­    BLE_HCI_ADV_OWN_ADDR_RANDOM (1)
®    BLE_HCI_ADV_OWN_ADDR_PRIV_PUB (2)
¯    BLE_HCI_ADV_OWN_ADDR_PRIV_RAND (3)
°    BLE_HCI_ADV_OWN_ADDR_MAX (3)
³    BLE_HCI_ADV_PEER_ADDR_PUBLIC (0)
´    BLE_HCI_ADV_PEER_ADDR_RANDOM (1)
µ    BLE_HCI_ADV_PEER_ADDR_MAX (1)
¸    BLE_HCI_ADV_CHAN_TXPWR_MIN (-20)
¹    BLE_HCI_ADV_CHAN_TXPWR_MAX (10)
¾    BLE_HCI_CONN_PEER_ADDR_PUBLIC (0)
¿    BLE_HCI_CONN_PEER_ADDR_RANDOM (1)
À    BLE_HCI_CONN_PEER_ADDR_PUBLIC_IDENT (2)
Á    BLE_HCI_CONN_PEER_ADDR_RANDOM_IDENT (3)
    BLE_HCI_CONN_PEER_ADDR_MAX (3)
Π   BLE_HCI_ADV_FILT_NONE (0)
Ï    BLE_HCI_ADV_FILT_SCAN (1)
Р   BLE_HCI_ADV_FILT_CONN (2)
Ñ    BLE_HCI_ADV_FILT_BOTH (3)
Ò    BLE_HCI_ADV_FILT_MAX (3)
Ô    BLE_HCI_ADV_FILT_DEF (BLE_HCI_ADV_FILT_NONE)
×    BLE_HCI_ADV_ITVL (625)
Ø    BLE_HCI_ADV_ITVL_MIN (32)
Ù    BLE_HCI_ADV_ITVL_MAX (16384)
Ú    BLE_HCI_ADV_ITVL_NONCONN_MIN (160)
Ü    BLE_HCI_ADV_ITVL_DEF (0x800)
Ý    BLE_HCI_ADV_CHANMASK_DEF (0x7)
à    BLE_HCI_SCAN_TYPE_PASSIVE (0)
á    BLE_HCI_SCAN_TYPE_ACTIVE (1)
ä    BLE_HCI_SCAN_ITVL (625)
å    BLE_HCI_SCAN_ITVL_MIN (0x0004)
æ    BLE_HCI_SCAN_ITVL_MAX (0x4000)
ç    BLE_HCI_SCAN_ITVL_MAX_EXT (0xffff)
è    BLE_HCI_SCAN_ITVL_DEF (16)
é    BLE_HCI_SCAN_WINDOW_MIN (0x0004)
ê    BLE_HCI_SCAN_WINDOW_MAX (0x4000)
ë    BLE_HCI_SCAN_WINDOW_MAX_EXT (0xffff)
ì    BLE_HCI_SCAN_WINDOW_DEF (16)
ÿ    BLE_HCI_SCAN_FILT_NO_WL (0)
€
BLE_HCI_SCAN_FILT_USE_WL (1)

BLE_HCI_SCAN_FILT_NO_WL_INITA (2)
‚
BLE_HCI_SCAN_FILT_USE_WL_INITA (3)
ƒ
BLE_HCI_SCAN_FILT_MAX (3)
†
BLE_HCI_ADD_WHITE_LIST_LEN (7)
‡
BLE_HCI_RMV_WHITE_LIST_LEN (7)
Š
BLE_HCI_CREATE_CONN_LEN (25)
‹
BLE_HCI_CONN_ITVL (1250)
Œ
BLE_HCI_CONN_FILT_NO_WL (0)

BLE_HCI_CONN_FILT_USE_WL (1)
Ž
BLE_HCI_CONN_FILT_MAX (1)

BLE_HCI_CONN_ITVL_MIN (0x0006)

BLE_HCI_CONN_ITVL_MAX (0x0c80)
‘
BLE_HCI_CONN_LATENCY_MIN (0x0000)
’
BLE_HCI_CONN_LATENCY_MAX (0x01f3)
“
BLE_HCI_CONN_SPVN_TIMEOUT_MIN (0x000a)
”
BLE_HCI_CONN_SPVN_TIMEOUT_MAX (0x0c80)
•
BLE_HCI_CONN_SPVN_TMO_UNITS (10)
–
BLE_HCI_INITIATOR_FILT_POLICY_MAX (1)
™
BLE_HCI_CONN_PEER_ADDR_PUBLIC (0)
š
BLE_HCI_CONN_PEER_ADDR_RANDOM (1)
›
BLE_HCI_CONN_PEER_ADDR_PUB_ID (2)
œ
BLE_HCI_CONN_PEER_ADDR_RAND_ID (3)

BLE_HCI_CONN_PEER_ADDR_MAX (3)
¡
BLE_HCI_SET_DATALEN_TX_OCTETS_MIN (0x001b)
¢
BLE_HCI_SET_DATALEN_TX_OCTETS_MAX (0x00fb)
£
BLE_HCI_SET_DATALEN_TX_TIME_MIN (0x0148)
¤
BLE_HCI_SET_DATALEN_TX_TIME_MAX (0x4290)
§
BLE_HCI_LE_PHY_1M (1)
¨
BLE_HCI_LE_PHY_2M (2)
©
BLE_HCI_LE_PHY_CODED (3)
¬
BLE_HCI_LE_PHY_NO_TX_PREF_MASK (0x01)
­
BLE_HCI_LE_PHY_NO_RX_PREF_MASK (0x02)
®
BLE_HCI_LE_PHY_1M_PREF_MASK (0x01)
¯
BLE_HCI_LE_PHY_2M_PREF_MASK (0x02)
°
BLE_HCI_LE_PHY_CODED_PREF_MASK (0x04)
²
BLE_HCI_LE_PHY_PREF_MASK_ALL (BLE_HCI_LE_PHY_1M_PREF_MASK | BLE_HCI_LE_PHY_2M_PREF_MASK | BLE_HCI_LE_PHY_CODED_PREF_MASK)
·
BLE_HCI_LE_PHY_CODED_ANY (0x0000)
¸
BLE_HCI_LE_PHY_CODED_S2_PREF (0x0001)
¹
BLE_HCI_LE_PHY_CODED_S8_PREF (0x0002)
¼
BLE_HCI_LE_PHY_1M (1)
½
BLE_HCI_LE_PHY_2M (2)
¾
BLE_HCI_LE_PHY_CODED (3)
Á
BLE_HCI_LE_PHY_CODED_S8 (3)
Â
BLE_HCI_LE_PHY_CODED_S2 (4)
Å
BLE_HCI_LE_SET_EXT_ADV_PROP_CONNECTABLE (0x0001)
Æ
BLE_HCI_LE_SET_EXT_ADV_PROP_SCANNABLE (0x0002)
Ç
BLE_HCI_LE_SET_EXT_ADV_PROP_DIRECTED (0x0004)
È
BLE_HCI_LE_SET_EXT_ADV_PROP_HD_DIRECTED (0x0008)
É
BLE_HCI_LE_SET_EXT_ADV_PROP_LEGACY (0x0010)
Ê
BLE_HCI_LE_SET_EXT_ADV_PROP_ANON_ADV (0x0020)
Ë
BLE_HCI_LE_SET_EXT_ADV_PROP_INC_TX_PWR (0x0040)
Ì
BLE_HCI_LE_SET_EXT_ADV_PROP_MASK (0x7F)
Î
BLE_HCI_LE_SET_EXT_ADV_PROP_LEGACY_IND (0x0013)
Ï
BLE_HCI_LE_SET_EXT_ADV_PROP_LEGACY_LD_DIR (0x0015)
Ð
BLE_HCI_LE_SET_EXT_ADV_PROP_LEGACY_HD_DIR (0x001d)
Ñ
BLE_HCI_LE_SET_EXT_ADV_PROP_LEGACY_SCAN (0x0012)
Ò
BLE_HCI_LE_SET_EXT_ADV_PROP_LEGACY_NONCONN (0x0010)
Õ
BLE_HCI_MAX_EXT_ADV_DATA_LEN (251)
×
BLE_HCI_LE_SET_DATA_OPER_INT (0)
Ø
BLE_HCI_LE_SET_DATA_OPER_FIRST (1)
Ù
BLE_HCI_LE_SET_DATA_OPER_LAST (2)
Ú
BLE_HCI_LE_SET_DATA_OPER_COMPLETE (3)
Û
BLE_HCI_LE_SET_DATA_OPER_UNCHANGED (4)
Þ
BLE_HCI_MAX_EXT_SCAN_RSP_DATA_LEN (251)
á
BLE_HCI_LE_SET_PERIODIC_ADV_PROP_INC_TX_PWR (0x0040)
â
BLE_HCI_LE_SET_PERIODIC_ADV_PROP_MASK (0x0040)
å
BLE_HCI_MAX_PERIODIC_ADV_DATA_LEN (252)
è
BLE_HCI_PERIODIC_DATA_STATUS_COMPLETE 0x00
é
BLE_HCI_PERIODIC_DATA_STATUS_INCOMPLETE 0x01
ê
BLE_HCI_PERIODIC_DATA_STATUS_TRUNCATED 0x02
í
BLE_HCI_PRIVACY_NETWORK (0)
î
BLE_HCI_PRIVACY_DEVICE (1)
ñ
BLE_HCI_EVCODE_INQUIRY_CMP (0x01)
ò
BLE_HCI_EVCODE_INQUIRY_RESULT (0x02)
ó
BLE_HCI_EVCODE_CONN_DONE (0x03)
ô
BLE_HCI_EVCODE_CONN_REQUEST (0x04)
õ
BLE_HCI_EVCODE_DISCONN_CMP (0x05)
ü
BLE_HCI_EVCODE_AUTH_CMP (0x06)
ý
BLE_HCI_EVCODE_REM_NAME_REQ_CMP (0x07)
ÿ
BLE_HCI_EVCODE_ENCRYPT_CHG (0x08)
†BLE_HCI_EVCODE_CHG_LINK_KEY_CMP (0x09)
‡BLE_HCI_EVCODE_MASTER_LINK_KEY_CMP (0x0A)
ˆBLE_HCI_EVCODE_RD_REM_SUPP_FEAT_CMP (0x0B)
‰BLE_HCI_EVCODE_RD_REM_VER_INFO_CMP (0x0C)
’BLE_HCI_EVCODE_QOS_SETUP_CMP (0x0D)
”BLE_HCI_EVCODE_COMMAND_COMPLETE (0x0E)
¡BLE_HCI_EVCODE_COMMAND_STATUS (0x0F)
¨BLE_HCI_EVCODE_HW_ERROR (0x10)
­BLE_HCI_EVCODE_NUM_COMP_PKTS (0x13)
·BLE_HCI_EVCODE_MODE_CHANGE (0x14)
¸BLE_HCI_EVCODE_RETURN_LINK_KEYS (0x15)
¹BLE_HCI_EVCODE_PIN_CODE_REQ (0x16)
ºBLE_HCI_EVCODE_LINK_KEY_REQ (0x17)
»BLE_HCI_EVCODE_LINK_KEY_NOTIFY (0x18)
¼BLE_HCI_EVCODE_LOOPBACK_CMD (0x19)
¾BLE_HCI_EVCODE_DATA_BUF_OVERFLOW (0x1A)
ÃBLE_HCI_EVCODE_MAX_SLOTS_CHG (0x1B)
ÄBLE_HCI_EVCODE_READ_CLK_OFF_COMP (0x1C)
ÅBLE_HCI_EVCODE_CONN_PKT_TYPE_CHG (0x1D)
ÆBLE_HCI_EVCODE_QOS_VIOLATION (0x1E)
ÈBLE_HCI_EVCODE_PSR_MODE_CHG (0x20)
ÉBLE_HCI_EVCODE_FLOW_SPEC_COMP (0x21)
ÊBLE_HCI_EVCODE_INQ_RESULT_RSSI (0x22)
ËBLE_HCI_EVCODE_READ_REM_EXT_FEAT (0x23)
ÍBLE_HCI_EVCODE_SYNCH_CONN_COMP (0x2C)
ÎBLE_HCI_EVCODE_SYNCH_CONN_CHG (0x2D)
ÏBLE_HCI_EVCODE_SNIFF_SUBRATING (0x2E)
ÐBLE_HCI_EVCODE_EXT_INQ_RESULT (0x2F)
ÒBLE_HCI_EVCODE_ENC_KEY_REFRESH (0x30)
ØBLE_HCI_EVOCDE_IO_CAP_REQ (0x31)
ÙBLE_HCI_EVCODE_IO_CAP_RSP (0x32)
ÚBLE_HCI_EVCODE_USER_CONFIRM_REQ (0x33)
ÛBLE_HCI_EVCODE_PASSKEY_REQ (0x34)
ÜBLE_HCI_EVCODE_REM_OOB_DATA_REQ (0x35)
ÝBLE_HCI_EVCODE_SIMPLE_PAIR_COMP (0x36)
ßBLE_HCI_EVCODE_LNK_SPVN_TMO_CHG (0x38)
àBLE_HCI_EVCODE_ENH_FLUSH_COMP (0x39)
áBLE_HCI_EVCODE_USER_PASSKEY_NOTIFY (0x3B)
âBLE_HCI_EVCODE_KEYPRESS_NOTIFY (0x3C)
ãBLE_HCI_EVCODE_REM_HOST_SUPP_FEAT (0x3D)
åBLE_HCI_EVCODE_LE_META (0x3E)
ìBLE_HCI_EVCODE_PHYS_LINK_COMP (0x40)
íBLE_HCI_EVCODE_CHAN_SELECTED (0x41)
îBLE_HCI_EVCODE_DISCONN_PHYS_LINK (0x42)
ïBLE_HCI_EVCODE_PHYS_LINK_LOSS_EARLY (0x43)
ðBLE_HCI_EVCODE_PHYS_LINK_RECOVERY (0x44)
ñBLE_HCI_EVCODE_LOGICAL_LINK_COMP (0x45)
òBLE_HCI_EVCODE_DISCONN_LOGICAL_LINK (0x46)
óBLE_HCI_EVCODE_FLOW_SPEC_MODE_COMP (0x47)
ôBLE_HCI_EVCODE_NUM_COMP_DATA_BLKS (0x48)
õBLE_HCI_EVCODE_AMP_START_TEST (0x49)
öBLE_HCI_EVOCDE_AMP_TEST_END (0x4A)
÷BLE_HCI_EVOCDE_AMP_RCVR_REPORT (0x4B)
øBLE_HCI_EVCODE_SHORT_RANGE_MODE_CHG (0x4C)
ùBLE_HCI_EVCODE_AMP_STATUS_CHG (0x4D)
úBLE_HCI_EVCODE_TRIG_CLK_CAPTURE (0x4E)
ûBLE_HCI_EVCODE_SYNCH_TRAIN_COMP (0x4F)
üBLE_HCI_EVCODE_SYNCH_TRAIN_RCVD (0x50)
ýBLE_HCI_EVCODE_SLAVE_BCAST_RX (0x51)
þBLE_HCI_EVCODE_SLAVE_BCAST_TMO (0x52)
ÿBLE_HCI_EVCODE_TRUNC_PAGE_COMP (0x53)
€BLE_HCI_EVCODE_SLAVE_PAGE_RSP_TMO (0x54)
BLE_HCI_EVCODE_SLAVE_BCAST_CHAN_MAP (0x55)
‚BLE_HCI_EVCODE_INQ_RSP_NOTIFY (0x56)
„BLE_HCI_EVCODE_AUTH_PYLD_TMO (0x57)
‰BLE_HCI_EVCODE_SAM_STATUS_CHG (0x58)
‹BLE_HCI_EVCODE_VS_DEBUG (0xFF)
’BLE_HCI_LE_SUBEV_CONN_COMPLETE (0x01)
 BLE_HCI_LE_SUBEV_ADV_RPT (0x02)
®BLE_HCI_LE_SUBEV_CONN_UPD_COMPLETE (0x03)
¸BLE_HCI_LE_SUBEV_RD_REM_USED_FEAT (0x04)
ÀBLE_HCI_LE_SUBEV_LT_KEY_REQ (0x05)
ÈBLE_HCI_LE_SUBEV_REM_CONN_PARM_REQ (0x06)
ÒBLE_HCI_LE_SUBEV_DATA_LEN_CHG (0x07)
ÜBLE_HCI_LE_SUBEV_RD_LOC_P256_PUBKEY (0x08)
ãBLE_HCI_LE_SUBEV_GEN_DHKEY_COMPLETE (0x09)
êBLE_HCI_LE_SUBEV_ENH_CONN_COMPLETE (0x0A)
úBLE_HCI_LE_SUBEV_DIRECT_ADV_RPT (0x0B)
‰ BLE_HCI_LE_SUBEV_PHY_UPDATE_COMPLETE (0x0C)
’ BLE_HCI_LE_SUBEV_EXT_ADV_RPT (0x0D)
¨ BLE_HCI_LE_SUBEV_PERIODIC_ADV_SYNC_ESTAB (0x0E)
µ BLE_HCI_LE_SUBEV_PERIODIC_ADV_RPT (0x0F)
Á BLE_HCI_LE_SUBEV_PERIODIC_ADV_SYNC_LOST (0x10)
Ç BLE_HCI_LE_SUBEV_SCAN_TIMEOUT (0x11)
Ì BLE_HCI_LE_SUBEV_ADV_SET_TERMINATED (0x12)
Õ BLE_HCI_LE_SUBEV_SCAN_REQ_RCVD (0x13)
Ý BLE_HCI_LE_SUBEV_CHAN_SEL_ALG (0x14)
ä BLE_HCI_LE_SUBEV_CONNLESS_IQ_RPT (0x15)
å BLE_HCI_LE_SUBEV_CONN_IQ_RPT (0x16)
æ BLE_HCI_LE_SUBEV_CTE_REQ_FAILED (0x17)
è BLE_HCI_LE_SUBEV_PERIODIC_ADV_SYNC_TRANSFER (0x18)
÷ BLE_HCI_LE_SUBEV_CIS_ESTAB (0x19)
ŒBLE_HCI_LE_SUBEV_CIS_REQUEST (0x1A)
•BLE_HCI_LE_SUBEV_BIG_COMP (0x1B)
§BLE_HCI_LE_SUBEV_BIG_TERMINATE_COMP (0x1C)
®BLE_HCI_LE_SUBEV_BIG_SYNC_ESTAB (0x1D)
¾BLE_HCI_LE_SUBEV_BIG_SYNC_LOST (0x1E)
ÅBLE_HCI_LE_SUBEV_REQ_PEER_SCA_COMP (0x1F)
ÍBLE_HCI_LE_SUBEV_PATH_LOSS_THRESHOLD (0x20)
ÕBLE_HCI_LE_SUBEV_TRANSMIT_POWER_REPORT (0x21)
áBLE_HCI_LE_SUBEV_BIGINFO_ADV_REPORT (0x22)
óBLE_HCI_LE_SUBEV_SUBRATE_CHANGE (0x23)
ÿBLE_HCI_EVENT_ACL_BUF_OVERFLOW (0x01)
‚BLE_HCI_ADV_RPT_EVTYPE_ADV_IND (0)
ƒBLE_HCI_ADV_RPT_EVTYPE_DIR_IND (1)
„BLE_HCI_ADV_RPT_EVTYPE_SCAN_IND (2)
…BLE_HCI_ADV_RPT_EVTYPE_NONCONN_IND (3)
†BLE_HCI_ADV_RPT_EVTYPE_SCAN_RSP (4)
‰BLE_HCI_LEGACY_ADV_EVTYPE_ADV_IND (0x13)
ŠBLE_HCI_LEGACY_ADV_EVTYPE_ADV_DIRECT_IND (0x15)
‹BLE_HCI_LEGACY_ADV_EVTYPE_ADV_SCAN_IND (0x12)
ŒBLE_HCI_LEGACY_ADV_EVTYPE_ADV_NONCON_IND (0x10)
BLE_HCI_LEGACY_ADV_EVTYPE_SCAN_RSP_ADV_IND (0x1b)
ŽBLE_HCI_LEGACY_ADV_EVTYPE_SCAN_RSP_ADV_SCAN_IND (0x1a)
‘BLE_HCI_LE_CONN_COMPLETE_ROLE_MASTER (0x00)
’BLE_HCI_LE_CONN_COMPLETE_ROLE_SLAVE (0x01)
•BLE_HCI_LE_CONN_HANDLE_MAX (0x0eff)
˜BLE_HCI_LE_ADV_RPT_NUM_RPTS_MIN (1)
™BLE_HCI_LE_ADV_RPT_NUM_RPTS_MAX (0x19)
œBLE_HCI_VER_BCS_1_0b (0)
BLE_HCI_VER_BCS_1_1 (1)
žBLE_HCI_VER_BCS_1_2 (2)
ŸBLE_HCI_VER_BCS_2_0_EDR (3)
 BLE_HCI_VER_BCS_2_1_EDR (4)
¡BLE_HCI_VER_BCS_3_0_HCS (5)
¢BLE_HCI_VER_BCS_4_0 (6)
£BLE_HCI_VER_BCS_4_1 (7)
¤BLE_HCI_VER_BCS_4_2 (8)
¥BLE_HCI_VER_BCS_5_0 (9)
¦BLE_HCI_VER_BCS_5_1 (10)
§BLE_HCI_VER_BCS_5_2 (11)
¨BLE_HCI_VER_BCS_5_3 (12)
ªBLE_LMP_VER_BCS_1_0b (0)
«BLE_LMP_VER_BCS_1_1 (1)
¬BLE_LMP_VER_BCS_1_2 (2)
­BLE_LMP_VER_BCS_2_0_EDR (3)
®BLE_LMP_VER_BCS_2_1_EDR (4)
¯BLE_LMP_VER_BCS_3_0_HCS (5)
°BLE_LMP_VER_BCS_4_0 (6)
±BLE_LMP_VER_BCS_4_1 (7)
²BLE_LMP_VER_BCS_4_2 (8)
³BLE_LMP_VER_BCS_5_0 (9)
´BLE_LMP_VER_BCS_5_1 (10)
µBLE_LMP_VER_BCS_5_2 (11)
¶BLE_LMP_VER_BCS_5_3 (12)
ºBLE_HCI_VER_BCS BLE_HCI_VER_BCS_5_0
»BLE_LMP_VER_BCS BLE_LMP_VER_BCS_5_0
ÇBLE_HCI_DATA_HDR_SZ 4
ÈBLE_HCI_DATA_HANDLE(handle_pb_bc) (((handle_pb_bc) & 0x0fff) >> 0)
ÉBLE_HCI_DATA_PB(handle_pb_bc) (((handle_pb_bc) & 0x3000) >> 12)
ÊBLE_HCI_DATA_BC(handle_pb_bc) (((handle_pb_bc) & 0xc000) >> 14)
ÒBLE_HCI_PB_FIRST_NON_FLUSH 0
ÓBLE_HCI_PB_MIDDLE 1
ÔBLE_HCI_PB_FIRST_FLUSH 2
ÕBLE_HCI_PB_FULL 3ÜÒ
 




..\..\..\..\host\nimble\nimble\include\..\..\..\..\host\nimble\nimble\include\nimble/..\..\..\..\host\nimble\nimble\transport\include\nimble/hci_common.h
ble.hnimble/transport.h

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..\..\..\..\host\nimble\nimble\include\nimble/hci_common.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x)·ble_hci_cmdopcodeI
#length:
#ª:
data 
#)ýble_hci_evopcode:
#length:
#
ð:
dataf
#)Àble_hci_lc_disconnect_cpconn_handleI
#reason:
#)õble_hci_rd_rem_ver_info_cpconn_handleI
#)«ble_hci_cb_set_event_mask_cpevent_maski
#)íble_hci_cb_read_tx_pwr_cpconn_handleI
#type:
#)³ble_hci_cb_read_tx_pwr_rpconn_handleI
#tx_levelÿ#)æble_hci_cb_ctlr_to_host_fc_cp
enable:
#)Õble_hci_cb_host_buf_size_cpacl_data_lenI
#sco_data_len:
#acl_numI
#sco_numI
#)ble_hci_cb_host_num_comp_pkts_entryhandleI
#countI
#)åble_hci_cb_host_num_comp_pkts_cp
handles:
#ÛUhÓ#
)ble_hci_cb_set_event_mask2_cpevent_mask2i
#)Öble_hci_cb_rd_auth_pyld_tmo_cpconn_handleI
#)œ    ble_hci_cb_rd_auth_pyld_tmo_rpconn_handleI
#tmoI
#)â    ble_hci_cb_wr_auth_pyld_tmo_cpconn_handleI
#tmoI
#)›
ble_hci_cb_wr_auth_pyld_tmo_rpconn_handleI
#)˜ble_hci_ip_rd_local_ver_rphci_ver:
#hci_revI
#
lmp_ver:
#manufacturerI
#lmp_subverI
#)Öble_hci_ip_rd_loc_supp_cmd_rp@Å:

?commandsº#)Œble_hci_ip_rd_loc_supp_feat_rpfeaturesi
#)ùble_hci_ip_rd_buf_size_rpacl_data_lenI
#sco_data_len:
#acl_numI
#sco_numI
#)® ble_hci_ip_rd_bd_addr_rp¡ :

addr–#)Ö ble_hci_rd_rssi_cphandleI
#)Œble_hci_rd_rssi_rphandleI
#rssiÿ#)Âble_hci_le_set_event_mask_cpevent_maski
#)‰ble_hci_le_rd_buf_size_rpdata_lenI
#data_packets:
#)ƒble_hci_le_rd_buf_size_v2_rpdata_lenI
#data_packets:
#iso_data_lenI
#iso_data_packets:
#)¹ble_hci_le_rd_loc_supp_feat_rpfeaturesi
#)ñble_hci_le_set_rand_addr_cpä:

addrY#)Áble_hci_le_set_adv_params_cpmin_intervalI
#max_intervalI
#type:
#own_addr_type:
#peer_addr_type:
#†:

peer_addrû#chan_map:
# filter_policy:
#)ûble_hci_le_rd_adv_chan_txpwr_rp
power_levelÿ#)Ìble_hci_le_set_adv_data_cp adv_data_len:
#»:

adv_data°    #
)¢ble_hci_le_set_scan_rsp_data_cp scan_rsp_len:
#‘:

scan_rsp
#
)Ôble_hci_le_set_adv_enable_cp
enable:
#)àble_hci_le_set_scan_params_cpscan_type:
#scan_itvlI
#
scan_windowI
#own_addr_type:
#filter_policy:
#)®ble_hci_le_set_scan_enable_cpenable:
#filter_duplicates:
#
)Èble_hci_le_create_conn_cpscan_itvlI
#scan_windowI
#filter_policy:
#peer_addr_type:
#®:

peer_addr£#own_addr_type:
#min_conn_itvlI
# max_conn_itvlI
#conn_latencyI
#tmoI
#min_ceI
#max_ceI
#)÷ble_hci_le_rd_white_list_rp
size:
#)Âble_hci_le_add_whte_list_cpaddr_type:
#µ:

addrª#
)Žble_hci_le_rmv_white_list_cpaddr_type:
#:

addrö#
)Ëble_hci_le_conn_update_cpconn_handleI
#conn_itvl_minI
#conn_itvl_maxI
#conn_latencyI
#supervision_timeoutI
#min_ce_lenI
#
max_ce_lenI
#)ble_hci_le_set_host_chan_class_cpü:

chan_mapñ #)Áble_hci_le_rd_chan_map_cpconn_handleI
#)ble_hci_le_rd_chan_map_rpconn_handleI
#ÿ:

chan_mapt#)Äble_hci_le_rd_rem_feat_cpconn_handleI
#)Œble_hci_le_encrypt_cp é:

keyÞ#ÿ:

dataô#)¾ble_hci_le_encrypt_rp±:

data&#)íble_hci_le_rand_rprandom_numberi
#)Ôble_hci_le_start_encrypt_cpconn_handleI
#randi
#divI
#
È:

ltk½#)£ ble_hci_le_lt_key_req_reply_cpconn_handleI
#— :

ltk#)Ü ble_hci_le_lt_key_req_reply_rpconn_handleI
#)™!ble_hci_le_lt_key_req_neg_reply_cpconn_handleI
#)Ö!ble_hci_le_lt_key_req_neg_reply_rpconn_handleI
#)ˆ"ble_hci_le_rd_supp_states_rpstatesi
#)´"ble_hci_le_rx_test_cp
rx_chan:
#)ˆ#ble_hci_le_tx_test_cptx_chan:
#test_data_len:
#
payload:
#)¹#ble_hci_le_test_end_rpnum_packetsI
#)ô$ble_hci_le_rem_conn_param_rr_cpconn_handleI
#conn_itvl_minI
#conn_itvl_maxI
#conn_latencyI
#supervision_timeoutI
#min_ceI
#
max_ceI
#)®%ble_hci_le_rem_conn_param_rr_rpconn_handleI
#)ú%ble_hci_le_rem_conn_params_nrr_cpconn_handleI
#reason:
#)¶&ble_hci_le_rem_conn_params_nrr_rpconn_handleI
#)'ble_hci_le_set_data_len_cpconn_handleI
#tx_octetsI
#tx_timeI
#)Ä'ble_hci_le_set_data_len_rpconn_handleI
#)˜(ble_hci_le_rd_sugg_def_data_len_rpmax_tx_octetsI
#max_tx_timeI
#)ì(ble_hci_le_wr_sugg_def_data_len_cpmax_tx_octetsI
#max_tx_timeI
#) )ble_hci_le_gen_dhkey_cp@“):

?pkeyˆ#)±*ble_hci_le_add_resolv_list_cp'peer_addr_type:
#å):

peer_id_addrÚ#
„*:

peer_irkù#Ÿ*:

local_irk#)Œ+ble_hci_le_rmv_resolve_list_cppeer_addr_type:
#÷*:

peer_id_addrl#
)Á+ble_hci_le_rd_resolv_list_size_rp
size:
#)Ÿ,ble_hci_le_rd_peer_resolv_addr_cppeer_addr_type:
#Š,:

peer_id_addrÿ#
)Ü,ble_hci_le_rd_peer_resolv_addr_rpÐ,:

rpaE#)»-ble_hci_le_rd_local_resolv_addr_cppeer_addr_type:
#¦-:

peer_id_addr›#
)ù-ble_hci_le_rd_local_resolv_addr_rpí-:

rpaâ#)¬.ble_hci_le_set_addr_res_en_cp
enable:
#)à.ble_hci_le_set_rpa_tmo_cprpa_timeoutI
#)Ý/ble_hci_le_rd_max_data_len_rpmax_tx_octestsI
#max_tx_timeI
#max_rx_octestsI
#max_rx_timeI
#)Œ0ble_hci_le_rd_phy_cpconn_handleI
#)Û0ble_hci_le_rd_phy_rpconn_handleI
#tx_phy:
#rx_phy:
#)²1ble_hci_le_set_default_phy_cpall_phys:
#tx_phys:
#
rx_phys:
#)«2ble_hci_le_set_phy_cpconn_handleI
#all_phys:
#tx_phys:
#rx_phys:
#phy_optionsI
#)ö2ble_hci_le_rx_test_v2_cprx_chan:
#phy:
#
index:
#)Ú3ble_hci_le_tx_test_v2_cptx_chan:
#test_data_len:
#
payload:
#phy:
#)­4ble_hci_le_set_adv_set_rnd_addr_cpadv_handle:
# 4:

addr#
)›7ble_hci_le_set_ext_adv_params_cpadv_handle:
#propsI
#
€5:

pri_itvl_minu#Ÿ5:

pri_itvl_max”#pri_chan_map:
#    own_addr_type:
#
peer_addr_type:
#ƒ6:

peer_addrø#filter_policy:
#tx_powerÿ#pri_phy:
#sec_max_skip:
#sec_phy:
#sid:
#scan_req_notif:
#)Ó7ble_hci_le_set_ext_adv_params_rp
tx_powerÿ#)å8ble_hci_le_set_ext_adv_data_cpadv_handle:
#operation:
#
fragment_pref:
#adv_data_len:
#Ô8:
adv_dataJ#)ü9ble_hci_le_set_ext_scan_rsp_data_cpadv_handle:
#operation:
#
fragment_pref:
#scan_rsp_len:
#ë9:
scan_rspá#)Ã:adv_setadv_handle:
#durationI
#
max_events:
#)Ÿ;ble_hci_le_set_ext_adv_enable_cpenable:
#num_sets:
#
’;üsetsŠ#)à;ble_hci_le_rd_max_adv_data_len_rpmax_adv_data_lenI
#)˜<ble_hci_le_rd_num_of_adv_sets_rp
num_sets:
#)Î<ble_hci_le_remove_adv_set_cp
adv_handle:
#)À=ble_hci_le_set_periodic_adv_params_cpadv_handle:
#min_itvlI
#
max_itvlI
#propsI
#)À>ble_hci_le_set_periodic_adv_data_cpadv_handle:
#operation:
#
adv_data_len:
#¯>:
adv_data%#)?ble_hci_le_set_periodic_adv_enable_cpenable:
#adv_handle:
#
)Ì?scan_paramstype:
#itvlI
#
windowI
#)Ä@ble_hci_le_set_ext_scan_params_cpown_addr_type:
#filter_policy:
#
phys:
#¶@scans. #)±Able_hci_le_set_ext_scan_enable_cpenable:
#filter_dup:
#
durationI
#periodI
#)ëBconn_paramsscan_itvlI
#scan_windowI
#conn_min_itvlI
#conn_max_itvlI
#conn_latencyI
#supervision_timeoutI
#
min_ceI
#max_ceI
#)¢Dble_hci_le_ext_create_conn_cp
filter_policy:
#own_addr_type:
#
peer_addr_type:
#ÞC:

peer_addrÓ!#init_phy_mask:
#    ŽD± conn_params"#
)ÛEble_hci_le_periodic_adv_create_sync_cpoptions:
#sid:
#
peer_addr_type:
#ŽE:

peer_addrƒ"#skipI
#    sync_timeoutI
#sync_cte_type:
# )šFble_hci_le_periodic_adv_term_sync_cpsync_handleI
#)‹Gble_hci_le_add_dev_to_periodic_adv_list_cppeer_addr_type:
#ìF:

peer_addra##
sid:
#)þGble_hci_le_rem_dev_from_periodic_adv_list_cppeer_addr_type:
#ßG:

peer_addrÔ##
sid:
#)¾Hble_hci_le_rd_periodic_adv_list_size_rp
list_size:
#)Ible_hci_le_rd_transmit_power_rpmin_tx_powerÿ#max_tx_powerÿ#
)öIble_hci_le_rd_rf_path_compensation_rptx_path_compensation 
#rx_path_compensation 
#)ÝJble_hci_le_wr_rf_path_compensation_cptx_path_compensation 
#rx_path_compensation 
#)ÉKble_hci_le_set_privacy_mode_cppeer_id_addr_type:
#¦K:

peer_id_addr›%#
mode:
#)Lble_hci_le_periodic_adv_receive_enable_cpsync_handleI
#enable:
#)‹Mble_hci_le_periodic_adv_sync_transfer_cpconn_handleI
#service_dataI
#sync_handleI
#)ÎMble_hci_le_periodic_adv_sync_transfer_rpconn_handleI
#)¿Nble_hci_le_periodic_adv_set_info_transfer_cpconn_handleI
#service_dataI
#adv_handle:
#)†Oble_hci_le_periodic_adv_set_info_transfer_rpconn_handleI
#)™Pble_hci_le_periodic_adv_sync_transfer_params_cpconn_handleI
#mode:
#skipI
#sync_timeoutI
#sync_cte_type:
#)ãPble_hci_le_periodic_adv_sync_transfer_params_rpconn_handleI
#)éQble_hci_le_set_default_periodic_sync_transfer_params_cpmode:
#skipI
#
sync_timeoutI
#sync_cte_type:
#)¢Rble_hci_le_request_peer_sca_cpconn_handleI
#)áRble_hci_le_set_host_feat_cpbit_num:
#val:
#
)òSble_hci_le_set_default_subrate_cp
subrate_minI
#subrate_maxI
#max_latencyI
#cont_numI
#supervision_tmoI
#)Uble_hci_le_subrate_req_cpconn_handleI
#subrate_minI
#subrate_maxI
#max_latencyI
#cont_numI
#supervision_tmoI
#
)ÉUble_hci_vs_rd_static_addr_rp¼U:

addr±*#)ùUble_hci_vs_set_tx_pwr_cp
tx_powerÿ#)©Vble_hci_vs_set_tx_pwr_rp
tx_powerÿ#)ÐVble_hci_vs_css_cp
opcode:
#)¨Wble_hci_vs_css_configure_cp    opcode:
#slot_usY
#
period_slotsY
#)ïWble_hci_vs_css_set_next_slot_cpopcode:
#slot_idxI
#
)ËXble_hci_vs_css_set_conn_slot_cpopcode:
#conn_handleI
#
slot_idxI
#)žYble_hci_le_enh_read_transmit_power_level_cpconn_handleI
#phy:
#)ºZble_hci_le_enh_read_transmit_power_level_rpstatus:
#conn_handleI
#
phy:
#curr_tx_power_level:
#max_tx_power_level:
#)[ble_hci_le_read_remote_transmit_power_level_cpconn_handleI
#phy:
#)Ë\ble_hci_le_set_path_loss_report_param_cpconn_handleI
#high_threshold:
#high_hysteresis:
#low_threshold:
#low_hysteresis:
#min_time_spentI
#)Ÿ]ble_hci_le_set_path_loss_report_enable_cpconn_handleI
#enable:
#)•^ble_hci_le_set_transmit_power_report_enable_cpconn_handleI
#local_enable:
#remote_enable:
#)æ^ble_hci_ev_disconn_cmpstatus:
#conn_handleI
#
reason:
#)½_ble_hci_ev_enrypt_chgstatus:
#connection_handleI
#
enabled:
#)Á`ble_hci_ev_rd_rem_ver_info_cmpstatus:
#conn_handleI
#
version:
#manufacturerI
#subversionI
#)¶able_hci_ev_command_completenum_packets:
#opcodeI
#
status:
# a:
return_params–0#)€bble_hci_ev_command_complete_nopnum_packets:
#opcodeI
#
)Ôbble_hci_ev_command_statusstatus:
#num_packets:
#
opcodeI
#)þbble_hci_ev_hw_error
hw_code:
#)­ccomp_pkthandleI
#packetsI
#)ócble_hci_ev_num_comp_pkts
count:
#ác~1completedÙ1#
)¨dble_hci_ev_data_buf_overflow
link_type:
#)ídble_hci_ev_enc_key_refreshstatus:
#conn_handleI
#
)­eble_hci_ev_le_meta
subevent:
# e:
data–2#
)àeble_hci_ev_auth_pyld_tmoconn_handleI
#)›fble_hci_ev_vs_debug
id:
#Žf:
data3#
)hble_hci_ev_le_subev_conn_completesubev_code:
#status:
#
conn_handleI
#role:
#peer_addr_type:
#«g:

peer_addr 3#conn_itvlI
#conn_latencyI
#supervision_timeoutI
#mca:
#)€iadv_report    type:
#addr_type:
#
Ëh:

addr@4#data_len:
#óh:
datai4#    )áible_hci_ev_le_subev_adv_rptsubev_code:
#num_reports:
#
Ñi4reportsÉ4#)‹kble_hci_ev_le_subev_conn_upd_complete
subev_code:
#status:
#
conn_handleI
#conn_itvlI
#conn_latencyI
#supervision_timeoutI
#)‰lble_hci_ev_le_subev_rd_rem_used_featsubev_code:
#status:
#
conn_handleI
#øk:

featuresí5#)ñlble_hci_ev_le_subev_lt_key_req subev_code:
#conn_handleI
#
randi
#divI
#)”nble_hci_ev_le_subev_rem_conn_param_reqsubev_code:
#conn_handleI
#
min_intervalI
#max_intervalI
#latencyI
#timeoutI
#    )»oble_hci_ev_le_subev_data_len_chgsubev_code:
#conn_handleI
#
max_tx_octetsI
#max_tx_timeI
#max_rx_octetsI
#max_rx_timeI
#    )¨pble_hci_ev_le_subev_rd_loc_p256_pubkeyBsubev_code:
#status:
#
•p:

?public_key
8#)‘qble_hci_ev_le_subev_gen_dhkey_complete"subev_code:
#status:
#
‚q:

dh_keyw8#)Ásble_hci_ev_le_subev_enh_conn_completesubev_code:
#status:
#
conn_handleI
#role:
#peer_addr_type:
#¥r:

peer_addr9#Ár:

local_rpa69#Ýr:

peer_rpaR9#conn_itvlI
#conn_latencyI
#supervision_timeoutI
#mca:
#)Ítdir_adv_reporttype:
#addr_type:
#
€t:

addrõ9#dir_addr_type:
#®t:

dir_addr#:#    rssiÿ#)µuble_hci_ev_le_subev_direct_adv_rptsubev_code:
#num_reports:
#
¥uÁ9reports:#)»vble_hci_ev_le_subev_phy_update_completesubev_code:
#status:
#
conn_handleI
#tx_phy:
#rx_phy:
#)Ëxext_adv_reportevt_typeI
#addr_type:
#þv:

addrs;#pri_phy:
#    sec_phy:
#
sid:
#tx_powerÿ#rssiÿ# periodic_itvlI
#dir_addr_type:
#’x:

dir_addr<#data_len:
#¾x:
data4<#)°yble_hci_ev_le_subev_ext_adv_rptsubev_code:
#num_reports:
#
 y;;reports˜<#)‡{ble_hci_ev_le_subev_periodic_adv_sync_estabsubev_code:
#status:
#
sync_handleI
#sid:
#peer_addr_type:
#Éz:

peer_addr>=#phy:
#intervalI
# aca:
#)É|ble_hci_ev_le_subev_periodic_adv_rptsubev_code:
#sync_handleI
#
tx_powerÿ#rssiÿ#cte_type:
#data_status:
#data_len:
#¼|:
data2>#)¢}ble_hci_ev_le_subev_periodic_adv_sync_lostsubev_code:
#sync_handleI
#
)Ü}ble_hci_ev_le_subev_scan_timeout
subev_code:
#)é~ble_hci_ev_le_subev_adv_set_terminatedsubev_code:
#status:
#
adv_handle:
#conn_handleI
#num_events:
#)ìble_hci_ev_le_subev_scan_req_rcvd    subev_code:
#adv_handle:
#
peer_addr_type:
#Ú:

peer_addrÏ?#)ɀ
ble_hci_ev_le_subev_chan_sel_algsubev_code:
#conn_handleI
#
csa:
#)Ђ
ble_hci_ev_le_subev_periodic_adv_sync_transfersubev_code:
#status:
#
conn_handleI
#service_dataI
#sync_handleI
#sid:
#peer_addr_type:
#    ’‚
:

peer_addrA#
phy:
#intervalI
#aca:
#)ù…
ble_hci_ev_le_subev_cis_establishedsubev_code:
#status:
#
cis_handleI
#½ƒ
:

cig_sync_delay±A#߃
:

cis_sync_delayÓA#„
:

trans_latency_mtosõA#
§„
:

trans_latency_stomB# phy_mtos:
#phy_stom:
#nse:
#bn_mtos:
#bn_stom:
#ft_mtos:
#ft_stom:
#max_pdu_mtosI
#max_pdu_stomI
#iso_intervalI
#)ü†
ble_hci_ev_le_subev_cis_requestsubev_code:
#conn_handleI
#
cis_handleI
#cig_id:
#cis_id:
#)°‰
ble_hci_ev_le_subev_big_completesubev_code:
#status:
#
big_handle:
#æ‡
:

big_sync_delayÚC#ˆˆ
:

transport_latencyüC#phy:
#    nse:
#
bn:
#pto:
#irc:
# max_pduI
#iso_intervalI
#bis_cnt:
#¤‰
I
bis™D#)™Š
ble_hci_ev_le_subev_big_terminate_completesubev_code:
#big_handle:
#
reason:
#)®Œ
ble_hci_ev_le_subev_big_sync_establishedsubev_code:
#status:
#
big_handle:
#‹‹
:

transport_latencyE#nse:
#bn:
#pto:
#irc:
#    max_pduI
#
iso_intervalI
#bis_cnt:
#šŒ
I
bis_handlesF#)Ž
ble_hci_ev_le_subev_big_sync_lostsubev_code:
#big_handle:
#
reason:
#)€Ž
ble_hci_ev_le_subev_peer_sca_completesubev_code:
#status:
#
conn_handleI
#sca:
#)ˆ
ble_hci_ev_le_subev_path_loss_thresholdsubev_code:
#conn_handleI
#
current_path_loss:
#zone_entered:
#)ސ
ble_hci_ev_le_subev_transmit_power_report    subev_code:
#status:
#
conn_handleI
#reason:
#phy:
#transmit_power_level:
#transmit_power_level_flag:
#delta:
#)‚“
ble_hci_ev_le_subev_biginfo_adv_reportsubev_code:
#sync_handleI
#
bis_cnt:
#nse:
#iso_intervalI
#bn:
#pto:
#irc:
#    max_pduI
#
ª’
:

sdu_intervalI#max_sduI
#phy:
#framing:
#encryption:
#)¿”
ble_hci_ev_le_subev_subrate_changesubev_code:
#status:
#
conn_handleI
#subrate_factorI
#periph_latencyI
#cont_numI
#supervision_tmoI
#
)ý”
hci_data_hdrhdh_handle_pb_bcI
#hdh_lenI
#
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H_BLE_ATT_CMD_ 
,BLE_ATT_ERROR_RSP_SZ 5
9BLE_ATT_MTU_CMD_SZ 3
EBLE_ATT_FIND_INFO_REQ_SZ 5
RBLE_ATT_FIND_INFO_RSP_BASE_SZ 2
XBLE_ATT_FIND_INFO_RSP_FORMAT_16BIT 1
YBLE_ATT_FIND_INFO_RSP_FORMAT_128BIT 2
[BLE_ATT_FIND_INFO_IDATA_16_SZ 4
\BLE_ATT_FIND_INFO_IDATA_128_SZ 18
gBLE_ATT_FIND_TYPE_VALUE_REQ_BASE_SZ 7
uBLE_ATT_FIND_TYPE_VALUE_RSP_BASE_SZ 1
vBLE_ATT_FIND_TYPE_VALUE_HINFO_BASE_SZ 4
‰
BLE_ATT_READ_TYPE_REQ_BASE_SZ 5
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BLE_ATT_READ_TYPE_REQ_SZ_16 7
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BLE_ATT_READ_TYPE_REQ_SZ_128 21
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BLE_ATT_READ_TYPE_RSP_BASE_SZ 2
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BLE_ATT_READ_TYPE_ADATA_BASE_SZ 2
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BLE_ATT_READ_TYPE_ADATA_SZ_16 6
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BLE_ATT_READ_TYPE_ADATA_SZ_128 20
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BLE_ATT_READ_REQ_SZ 3
º
BLE_ATT_READ_RSP_BASE_SZ 1
Ã
BLE_ATT_READ_BLOB_REQ_SZ 5
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BLE_ATT_READ_BLOB_RSP_BASE_SZ 1
×
BLE_ATT_READ_MULT_REQ_BASE_SZ 1
â
BLE_ATT_READ_MULT_RSP_BASE_SZ 1
ì
BLE_ATT_READ_GROUP_TYPE_REQ_BASE_SZ 5
í
BLE_ATT_READ_GROUP_TYPE_REQ_SZ_16 7
î
BLE_ATT_READ_GROUP_TYPE_REQ_SZ_128 21
ü
BLE_ATT_READ_GROUP_TYPE_RSP_BASE_SZ 2
BLE_ATT_READ_GROUP_TYPE_ADATA_BASE_SZ 4
‚BLE_ATT_READ_GROUP_TYPE_ADATA_SZ_16 6
ƒBLE_ATT_READ_GROUP_TYPE_ADATA_SZ_128 20
ŒBLE_ATT_WRITE_REQ_BASE_SZ 3
’BLE_ATT_WRITE_RSP_SZ 1
œBLE_ATT_PREP_WRITE_CMD_BASE_SZ 5
©BLE_ATT_EXEC_WRITE_REQ_SZ 2
®BLE_ATT_EXEC_WRITE_F_CANCEL 0x00
¯BLE_ATT_EXEC_WRITE_F_EXECUTE 0x01
¶BLE_ATT_EXEC_WRITE_RSP_SZ 1
¿BLE_ATT_NOTIFY_REQ_BASE_SZ 3
ËBLE_ATT_INDICATE_REQ_BASE_SZ 3
ÕBLE_ATT_INDICATE_RSP_SZ 1
ÞBLE_ATT_WRITE_CMD_BASE_SZ 3ÜÑ
 




..\..\..\..\host\nimble\nimble\host\src\C:\Keil_v5\ARM\ARMCC\Bin\..\include\..\..\..\..\host\nimble\porting\nimble\include\ble_att_cmd_priv.h
inttypes.hstddef.hos/os_mbuf.h

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..\..\..\..\host\nimble\nimble\host\src\ble_att_cmd_priv.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x)§ble_att_hdr
opcode:
#š:
data
#
)ble_att_error_rspbaep_req_op:
#baep_handleI
#
baep_error_code:
#)¨ble_att_mtu_cmdbamc_mtuI
#)÷ble_att_find_info_reqbafq_start_handleI
#bafq_end_handleI
#)§ble_att_find_info_rsp
bafp_format:
#)°ble_att_find_type_value_reqbavq_start_handleI
#bavq_end_handleI
#bavq_attr_typeI
#I
bavq_value“#)ùble_att_handle_groupattr_handleI
#group_end_handleI
#+­ble_att_find_type_value_rsp °list#)’ble_att_read_type_reqbatq_start_handleI
#batq_end_handleI
#…:
uuid{#)Õble_att_attr_data_listhandleI
#Ç:
value½#)žble_att_read_type_rsp
batp_length:
#Œ’batp_list#
)Éble_att_read_reqbarq_handleI
#)Ž    ble_att_read_blob_reqbabq_handleI
#babq_offsetI
#+Á    ble_att_read_mult_req±    I
handles§#)¬
ble_att_read_group_type_reqbagq_start_handleI
#bagq_end_handleI
#Ÿ
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uuid#)â
ble_att_read_group_type_rsp
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#)¥ble_att_write_reqbawq_handleI
#—:
value#)‡ble_att_prep_write_cmdbapc_handleI
#bapc_offsetI
#ôI
bapc_valueê#)·ble_att_exec_write_req
baeq_flags:
#)äble_att_notify_reqbanq_handleI
#)“ ble_att_indicate_reqbaiq_handleI
#)Ñ ble_att_write_cmdhandleI
#Ã :
value¹#
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__STATS_H__ 
STATS_SECT_DECL(__name) struct stats_ ## __name
STATS_SECT_END };
 STATS_SECT_START(__name) STATS_SECT_DECL(__name) {
!STATS_SECT_VAR(__var) 
#STATS_HDR(__sectname) NULL
%STATS_SECT_ENTRY(__var) 
&STATS_SECT_ENTRY16(__var) 
'STATS_SECT_ENTRY32(__var) 
(STATS_SECT_ENTRY64(__var) 
)STATS_RESET(__var) 
+STATS_SIZE_INIT_PARMS(__sectvarname,__size) 0, 0
.STATS_INC(__sectvarname,__var) 
/STATS_INCN(__sectvarname,__var,__n) 
0STATS_CLEAR(__sectvarname,__var) 
2STATS_NAME_START(__name) 
3STATS_NAME(__name,__entry) 
4STATS_NAME_END(__name) 
5STATS_NAME_INIT_PARMS(__name) NULL, 0…
 




..\..\..\..\host\nimble\porting\nimble\include\C:\Keil_v5\ARM\ARMCC\Bin\..\include\stats/stats.h
stdint.h

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..\..\..\..\host\nimble\porting\nimble\include\stats/stats.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xintuvoid;Ç
8
stats_initò$G
a$:
b$:
c$G
d$:
ea__resultò
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stats_registerò$G
a$G
ba__resultò
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F
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b$:
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d$:
e$G
fa__resultò

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H_BLE_ATT_ 
%BLE_ATT_UUID_PRIMARY_SERVICE 0x2800
&BLE_ATT_UUID_SECONDARY_SERVICE 0x2801
'BLE_ATT_UUID_INCLUDE 0x2802
(BLE_ATT_UUID_CHARACTERISTIC 0x2803
*BLE_ATT_ERR_INVALID_HANDLE 0x01
+BLE_ATT_ERR_READ_NOT_PERMITTED 0x02
,BLE_ATT_ERR_WRITE_NOT_PERMITTED 0x03
-BLE_ATT_ERR_INVALID_PDU 0x04
.BLE_ATT_ERR_INSUFFICIENT_AUTHEN 0x05
/BLE_ATT_ERR_REQ_NOT_SUPPORTED 0x06
0BLE_ATT_ERR_INVALID_OFFSET 0x07
1BLE_ATT_ERR_INSUFFICIENT_AUTHOR 0x08
2BLE_ATT_ERR_PREPARE_QUEUE_FULL 0x09
3BLE_ATT_ERR_ATTR_NOT_FOUND 0x0a
4BLE_ATT_ERR_ATTR_NOT_LONG 0x0b
5BLE_ATT_ERR_INSUFFICIENT_KEY_SZ 0x0c
6BLE_ATT_ERR_INVALID_ATTR_VALUE_LEN 0x0d
7BLE_ATT_ERR_UNLIKELY 0x0e
8BLE_ATT_ERR_INSUFFICIENT_ENC 0x0f
9BLE_ATT_ERR_UNSUPPORTED_GROUP 0x10
:BLE_ATT_ERR_INSUFFICIENT_RES 0x11
<BLE_ATT_OP_ERROR_RSP 0x01
=BLE_ATT_OP_MTU_REQ 0x02
>BLE_ATT_OP_MTU_RSP 0x03
?BLE_ATT_OP_FIND_INFO_REQ 0x04
@BLE_ATT_OP_FIND_INFO_RSP 0x05
ABLE_ATT_OP_FIND_TYPE_VALUE_REQ 0x06
BBLE_ATT_OP_FIND_TYPE_VALUE_RSP 0x07
CBLE_ATT_OP_READ_TYPE_REQ 0x08
DBLE_ATT_OP_READ_TYPE_RSP 0x09
EBLE_ATT_OP_READ_REQ 0x0a
FBLE_ATT_OP_READ_RSP 0x0b
GBLE_ATT_OP_READ_BLOB_REQ 0x0c
HBLE_ATT_OP_READ_BLOB_RSP 0x0d
IBLE_ATT_OP_READ_MULT_REQ 0x0e
JBLE_ATT_OP_READ_MULT_RSP 0x0f
KBLE_ATT_OP_READ_GROUP_TYPE_REQ 0x10
LBLE_ATT_OP_READ_GROUP_TYPE_RSP 0x11
MBLE_ATT_OP_WRITE_REQ 0x12
NBLE_ATT_OP_WRITE_RSP 0x13
OBLE_ATT_OP_PREP_WRITE_REQ 0x16
PBLE_ATT_OP_PREP_WRITE_RSP 0x17
QBLE_ATT_OP_EXEC_WRITE_REQ 0x18
RBLE_ATT_OP_EXEC_WRITE_RSP 0x19
SBLE_ATT_OP_NOTIFY_REQ 0x1b
TBLE_ATT_OP_INDICATE_REQ 0x1d
UBLE_ATT_OP_INDICATE_RSP 0x1e
VBLE_ATT_OP_WRITE_CMD 0x52
XBLE_ATT_ATTR_MAX_LEN 512
ZBLE_ATT_F_READ 0x01
[BLE_ATT_F_WRITE 0x02
\BLE_ATT_F_READ_ENC 0x04
]BLE_ATT_F_READ_AUTHEN 0x08
^BLE_ATT_F_READ_AUTHOR 0x10
_BLE_ATT_F_WRITE_ENC 0x20
`BLE_ATT_F_WRITE_AUTHEN 0x40
aBLE_ATT_F_WRITE_AUTHOR 0x80
cHA_FLAG_PERM_RW (BLE_ATT_F_READ | BLE_ATT_F_WRITE)
eBLE_ATT_ACCESS_OP_READ 1
fBLE_ATT_ACCESS_OP_WRITE 2
iBLE_ATT_MTU_DFLT 23
oBLE_ATT_MTU_MAX 527œ
 




..\..\..\..\host\nimble\nimble\host\include\..\..\..\..\host\nimble\porting\nimble\include\host/ble_att.h
os/queue.h

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..\..\..\..\host\nimble\nimble\host\include\host/ble_att.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x
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H_BLE_UUID_ 
SBLE_UUID16_INIT(uuid16) { .u.type = BLE_UUID_TYPE_16, .value = (uuid16), }
YBLE_UUID32_INIT(uuid32) { .u.type = BLE_UUID_TYPE_32, .value = (uuid32), }
_BLE_UUID128_INIT(uuid128...) { .u.type = BLE_UUID_TYPE_128, .value = { uuid128 }, }
eBLE_UUID16_DECLARE(uuid16) ((ble_uuid_t *) (&(ble_uuid16_t) BLE_UUID16_INIT(uuid16)))
hBLE_UUID32_DECLARE(uuid32) ((ble_uuid_t *) (&(ble_uuid32_t) BLE_UUID32_INIT(uuid32)))
kBLE_UUID128_DECLARE(uuid128...) ((ble_uuid_t *) (&(ble_uuid128_t) BLE_UUID128_INIT(uuid128)))
nBLE_UUID16(u) ((ble_uuid16_t *) (u))
qBLE_UUID32(u) ((ble_uuid32_t *) (u))
tBLE_UUID128(u) ((ble_uuid128_t *) (u))
zBLE_UUID_STR_LEN (37)œ’
 




..\..\..\..\host\nimble\nimble\host\include\C:\Keil_v5\ARM\ARMCC\Bin\..\include\host/ble_uuid.h
inttypes.hstddef.h

0
..\..\..\..\host\nimble\nimble\host\include\host/ble_uuid.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x³
BLE_UUID_TYPE_16BLE_UUID_TYPE_32 BLE_UUID_TYPE_128€*Æ
type:
#Pble_uuid_t3

7*õuF
#valueI
#Pble_uuid16_tX

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#Pble_uuid32_t‰

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H_BLE_ATT_PRIV_ \
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..\..\..\..\host\nimble\nimble\host\src\C:\Keil_v5\ARM\ARMCC\Bin\..\include\..\..\..\..\host\nimble\porting\nimble\include\..\..\..\..\host\nimble\nimble\host\include\..\..\..\..\host\nimble\nimble\include\ble_att_priv.h
inttypes.hstats/stats.hhost/ble_att.hhost/ble_uuid.hnimble/nimble_npl.h

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..\..\..\..\host\nimble\nimble\host\src\ble_att_priv.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xintuvoidN ì%I
%I
%:
%I
% 
%$
"C"óPble_att_svr_access_fnù
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 *à"`
stqe_nextJ
#)ôble_att_svr_entryha_nextF
#ha_uuidú
#ha_flags:
#ha_min_key_size:
#    ha_handle_idI
#
ha_cbþ
#ha_cb_arg$
#F
"ô
"(
-ble_att_clt_entry)Âble_att_clt_entry_listslh_firstB#")†ble_att_find_info_idataattr_handleI
#uuid#)Øble_att_find_type_value_hinfoattr_handleI
#group_end_handleI
#)§ble_att_read_type_adataatt_handleI
#value_lenì#value'#":
)œble_att_read_group_type_adataatt_handleI
#end_group_handleI
#value_lenì#value'#qble_att_stats°

-stats_ble_att_stats*Þ"Þsle_nextÉ#)Ãble_att_prep_entrybape_nextÅ#bape_handleI
#bape_offsetI
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)÷ble_att_prep_entry_listslh_firstw#"Þ)Å    ble_att_svr_connbasc_prep_listI#basc_prep_timeout_at6    # Èœble_att_stats
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H_BLE_EDDYSTONE_ 
%BLE_EDDYSTONE_MAX_UUIDS16 3
&BLE_EDDYSTONE_URL_MAX_LEN 17
(BLE_EDDYSTONE_URL_SCHEME_HTTP_WWW 0
)BLE_EDDYSTONE_URL_SCHEME_HTTPS_WWW 1
*BLE_EDDYSTONE_URL_SCHEME_HTTP 2
+BLE_EDDYSTONE_URL_SCHEME_HTTPS 3
-BLE_EDDYSTONE_URL_SUFFIX_COM_SLASH 0x00
.BLE_EDDYSTONE_URL_SUFFIX_ORG_SLASH 0x01
/BLE_EDDYSTONE_URL_SUFFIX_EDU_SLASH 0x02
0BLE_EDDYSTONE_URL_SUFFIX_NET_SLASH 0x03
1BLE_EDDYSTONE_URL_SUFFIX_INFO_SLASH 0x04
2BLE_EDDYSTONE_URL_SUFFIX_BIZ_SLASH 0x05
3BLE_EDDYSTONE_URL_SUFFIX_GOV_SLASH 0x06
4BLE_EDDYSTONE_URL_SUFFIX_COM 0x07
5BLE_EDDYSTONE_URL_SUFFIX_ORG 0x08
6BLE_EDDYSTONE_URL_SUFFIX_EDU 0x09
7BLE_EDDYSTONE_URL_SUFFIX_NET 0x0a
8BLE_EDDYSTONE_URL_SUFFIX_INFO 0x0b
9BLE_EDDYSTONE_URL_SUFFIX_BIZ 0x0c
:BLE_EDDYSTONE_URL_SUFFIX_GOV 0x0d
;BLE_EDDYSTONE_URL_SUFFIX_NONE 0xff”‹
 




..\..\..\..\host\nimble\nimble\host\include\C:\Keil_v5\ARM\ARMCC\Bin\..\include\host/ble_eddystone.h
inttypes.h

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..\..\..\..\host\nimble\nimble\host\include\host/ble_eddystone.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x
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å
æ


H_BLE_GAP_  !
*BLE_GAP_ADV_ITVL_MS(t) ((t) * 1000 / BLE_HCI_ADV_ITVL)
+BLE_GAP_SCAN_ITVL_MS(t) ((t) * 1000 / BLE_HCI_SCAN_ITVL)
,BLE_GAP_SCAN_WIN_MS(t) ((t) * 1000 / BLE_HCI_SCAN_ITVL)
-BLE_GAP_CONN_ITVL_MS(t) ((t) * 1000 / BLE_HCI_CONN_ITVL)
.BLE_GAP_SUPERVISION_TIMEOUT_MS(t) ((t) / 10)
1BLE_GAP_ADV_FAST_INTERVAL1_MIN BLE_GAP_ADV_ITVL_MS(30)
4BLE_GAP_ADV_FAST_INTERVAL1_MAX BLE_GAP_ADV_ITVL_MS(60)
7BLE_GAP_ADV_FAST_INTERVAL2_MIN BLE_GAP_ADV_ITVL_MS(100)
:BLE_GAP_ADV_FAST_INTERVAL2_MAX BLE_GAP_ADV_ITVL_MS(150)
=BLE_GAP_SCAN_FAST_INTERVAL_MIN BLE_GAP_SCAN_ITVL_MS(30)
@BLE_GAP_SCAN_FAST_INTERVAL_MAX BLE_GAP_SCAN_ITVL_MS(60)
CBLE_GAP_LIM_DISC_SCAN_INT BLE_GAP_SCAN_ITVL_MS(11.25)
FBLE_GAP_LIM_DISC_SCAN_WINDOW BLE_GAP_SCAN_WIN_MS(11.25)
IBLE_GAP_SCAN_FAST_WINDOW BLE_GAP_SCAN_WIN_MS(30)
LBLE_GAP_SCAN_FAST_PERIOD BLE_GAP_SCAN_ITVL_MS(30.72)
OBLE_GAP_SCAN_SLOW_INTERVAL1 BLE_GAP_SCAN_ITVL_MS(1280)
RBLE_GAP_SCAN_SLOW_WINDOW1 BLE_GAP_SCAN_WIN_MS(11.25)
UBLE_GAP_DISC_DUR_DFLT (10.24 * 1000)
XBLE_GAP_CONN_DUR_DFLT (30 * 1000)
[BLE_GAP_CONN_PAUSE_CENTRAL (1 * 1000)
^BLE_GAP_CONN_PAUSE_PERIPHERAL (5 * 1000)
aBLE_GAP_INITIAL_CONN_ITVL_MIN BLE_GAP_CONN_ITVL_MS(30)
dBLE_GAP_INITIAL_CONN_ITVL_MAX BLE_GAP_CONN_ITVL_MS(50)
gBLE_GAP_ADV_DFLT_CHANNEL_MAP 0x07
iBLE_GAP_INITIAL_CONN_LATENCY 0
jBLE_GAP_INITIAL_SUPERVISION_TIMEOUT 0x0100
kBLE_GAP_INITIAL_CONN_MIN_CE_LEN 0x0000
lBLE_GAP_INITIAL_CONN_MAX_CE_LEN 0x0000
nBLE_GAP_ROLE_MASTER 0
oBLE_GAP_ROLE_SLAVE 1
qBLE_GAP_EVENT_CONNECT 0
rBLE_GAP_EVENT_DISCONNECT 1
tBLE_GAP_EVENT_CONN_UPDATE 3
uBLE_GAP_EVENT_CONN_UPDATE_REQ 4
vBLE_GAP_EVENT_L2CAP_UPDATE_REQ 5
wBLE_GAP_EVENT_TERM_FAILURE 6
xBLE_GAP_EVENT_DISC 7
yBLE_GAP_EVENT_DISC_COMPLETE 8
zBLE_GAP_EVENT_ADV_COMPLETE 9
{BLE_GAP_EVENT_ENC_CHANGE 10
|BLE_GAP_EVENT_PASSKEY_ACTION 11
}BLE_GAP_EVENT_NOTIFY_RX 12
~BLE_GAP_EVENT_NOTIFY_TX 13
BLE_GAP_EVENT_SUBSCRIBE 14
€
BLE_GAP_EVENT_MTU 15

BLE_GAP_EVENT_IDENTITY_RESOLVED 16
‚
BLE_GAP_EVENT_REPEAT_PAIRING 17
ƒ
BLE_GAP_EVENT_PHY_UPDATE_COMPLETE 18
„
BLE_GAP_EVENT_EXT_DISC 19
…
BLE_GAP_EVENT_PERIODIC_SYNC 20
†
BLE_GAP_EVENT_PERIODIC_REPORT 21
‡
BLE_GAP_EVENT_PERIODIC_SYNC_LOST 22
ˆ
BLE_GAP_EVENT_SCAN_REQ_RCVD 23
‰
BLE_GAP_EVENT_PERIODIC_TRANSFER 24
Š
BLE_GAP_EVENT_PATHLOSS_THRESHOLD 25
‹
BLE_GAP_EVENT_TRANSMIT_POWER 26

BLE_GAP_SUBSCRIBE_REASON_WRITE 1
“
BLE_GAP_SUBSCRIBE_REASON_TERM 2
™
BLE_GAP_SUBSCRIBE_REASON_RESTORE 3
›
BLE_GAP_REPEAT_PAIRING_RETRY 1
œ
BLE_GAP_REPEAT_PAIRING_IGNORE 2
‡BLE_GAP_CONN_MODE_NON 0
ˆBLE_GAP_CONN_MODE_DIR 1
‰BLE_GAP_CONN_MODE_UND 2
‹BLE_GAP_DISC_MODE_NON 0
ŒBLE_GAP_DISC_MODE_LTD 1
BLE_GAP_DISC_MODE_GEN 2
çBLE_GAP_PRIVATE_MODE_NETWORK 0
èBLE_GAP_PRIVATE_MODE_DEVICE 1
÷BLE_GAP_LE_PHY_1M 1
øBLE_GAP_LE_PHY_2M 2
ùBLE_GAP_LE_PHY_CODED 3
BLE_GAP_LE_PHY_1M_MASK 0x01
ŽBLE_GAP_LE_PHY_2M_MASK 0x02
BLE_GAP_LE_PHY_CODED_MASK 0x04
BLE_GAP_LE_PHY_ANY_MASK 0x0F
¦BLE_GAP_LE_PHY_CODED_ANY 0
§BLE_GAP_LE_PHY_CODED_S2 1
¨BLE_GAP_LE_PHY_CODED_S8 2ÜÒ
 




..\..\..\..\host\nimble\nimble\host\include\C:\Keil_v5\ARM\ARMCC\Bin\..\include\..\..\..\..\config\host/ble_gap.h
inttypes.hhost/ble_hs.h
host/ble_hs_adv.h
nimble_syscfg.h


..\..\..\..\host\nimble\nimble\host\include\host/ble_gap.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xunsigned intintuvoid)·ble_gap_adv_params
conn_mode:
#disc_mode:
#
itvl_minI
#itvl_maxI
#channel_map:
#filter_policy:
#!high_duty_cycle:
#

)¿ble_gap_conn_desc,sec_state­#our_id_addrÌ    #peer_id_addrÌ    #our_ota_addrÌ    #peer_ota_addrÌ    #conn_handleI
# conn_itvlI
#"conn_latencyI
#$supervision_timeoutI
#&role:
#(master_clock_accuracy:
#))úble_gap_conn_paramsscan_itvlI
#scan_windowI
#itvl_minI
#itvl_maxI
#latencyI
#supervision_timeoutI
#
min_ce_lenI
#max_ce_lenI
#)Éble_gap_ext_disc_paramsitvlI
#windowI
#!passive:
#

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#filter_policy:
#!limited:
#

!passive:
#

!filter_duplicates:
#

)ï    ble_gap_upd_paramsitvl_minI
#itvl_maxI
#latencyI
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#min_ce_lenI
#max_ce_lenI
#
)«
ble_gap_passkey_paramsaction:
#numcmpY
#)¨ble_gap_disc_descevent_type:
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"¨)‰ ble_gap_repeat_pairingconn_handleI
#cur_key_size:
#!cur_authenticated:
#

!cur_sc:
#

new_key_size:
#!new_authenticated:
#

!new_sc:
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!new_bonding:
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#SÓ0connect‰disconnect±disc+disc_completeÐadv_completeãconn_updateöconn_update_reqterm_failurejenc_change’passkeyºnotify_rxânotify_tx8subscribeŒmtu-    identity_resolvedj    repeat_pairing²phy_updated„    )üble_gap_event4type:
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H_BLE_GATT_  
)BLE_GATT_REGISTER_OP_SVC 1
*BLE_GATT_REGISTER_OP_CHR 2
+BLE_GATT_REGISTER_OP_DSC 3
-BLE_GATT_SVC_UUID16 0x1801
.BLE_GATT_DSC_CLT_CFG_UUID16 0x2902
0BLE_GATT_CHR_PROP_BROADCAST 0x01
1BLE_GATT_CHR_PROP_READ 0x02
2BLE_GATT_CHR_PROP_WRITE_NO_RSP 0x04
3BLE_GATT_CHR_PROP_WRITE 0x08
4BLE_GATT_CHR_PROP_NOTIFY 0x10
5BLE_GATT_CHR_PROP_INDICATE 0x20
6BLE_GATT_CHR_PROP_AUTH_SIGN_WRITE 0x40
7BLE_GATT_CHR_PROP_EXTENDED 0x80
9BLE_GATT_ACCESS_OP_READ_CHR 0
:BLE_GATT_ACCESS_OP_WRITE_CHR 1
;BLE_GATT_ACCESS_OP_READ_DSC 2
<BLE_GATT_ACCESS_OP_WRITE_DSC 3
>BLE_GATT_CHR_F_BROADCAST 0x0001
?BLE_GATT_CHR_F_READ 0x0002
@BLE_GATT_CHR_F_WRITE_NO_RSP 0x0004
ABLE_GATT_CHR_F_WRITE 0x0008
BBLE_GATT_CHR_F_NOTIFY 0x0010
CBLE_GATT_CHR_F_INDICATE 0x0020
DBLE_GATT_CHR_F_AUTH_SIGN_WRITE 0x0040
EBLE_GATT_CHR_F_RELIABLE_WRITE 0x0080
FBLE_GATT_CHR_F_AUX_WRITE 0x0100
GBLE_GATT_CHR_F_READ_ENC 0x0200
HBLE_GATT_CHR_F_READ_AUTHEN 0x0400
IBLE_GATT_CHR_F_READ_AUTHOR 0x0800
JBLE_GATT_CHR_F_WRITE_ENC 0x1000
KBLE_GATT_CHR_F_WRITE_AUTHEN 0x2000
LBLE_GATT_CHR_F_WRITE_AUTHOR 0x4000
NBLE_GATT_SVC_TYPE_END 0
OBLE_GATT_SVC_TYPE_PRIMARY 1
PBLE_GATT_SVC_TYPE_SECONDARY 2´«
 




..\..\..\..\host\nimble\nimble\host\include\C:\Keil_v5\ARM\ARMCC\Bin\..\include\host/ble_gatt.h
inttypes.hhost/ble_att.h
host/ble_uuid.h


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..\..\..\..\host\nimble\nimble\host\include\host/ble_gatt.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xintuvoidN™ñ%I
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H_BLE_HS_ADV_ 
BLE_HS_ADV_MAX_SZ BLE_HCI_MAX_ADV_DATA_LEN
!BLE_HS_ADV_MAX_FIELD_SZ (BLE_HS_ADV_MAX_SZ - 2)
lBLE_HS_ADV_TYPE_FLAGS 0x01
mBLE_HS_ADV_TYPE_INCOMP_UUIDS16 0x02
nBLE_HS_ADV_TYPE_COMP_UUIDS16 0x03
oBLE_HS_ADV_TYPE_INCOMP_UUIDS32 0x04
pBLE_HS_ADV_TYPE_COMP_UUIDS32 0x05
qBLE_HS_ADV_TYPE_INCOMP_UUIDS128 0x06
rBLE_HS_ADV_TYPE_COMP_UUIDS128 0x07
sBLE_HS_ADV_TYPE_INCOMP_NAME 0x08
tBLE_HS_ADV_TYPE_COMP_NAME 0x09
uBLE_HS_ADV_TYPE_TX_PWR_LVL 0x0a
vBLE_HS_ADV_TYPE_SLAVE_ITVL_RANGE 0x12
wBLE_HS_ADV_TYPE_SOL_UUIDS16 0x14
xBLE_HS_ADV_TYPE_SOL_UUIDS128 0x15
yBLE_HS_ADV_TYPE_SVC_DATA_UUID16 0x16
zBLE_HS_ADV_TYPE_PUBLIC_TGT_ADDR 0x17
{BLE_HS_ADV_TYPE_RANDOM_TGT_ADDR 0x18
|BLE_HS_ADV_TYPE_APPEARANCE 0x19
}BLE_HS_ADV_TYPE_ADV_ITVL 0x1a
~BLE_HS_ADV_TYPE_SVC_DATA_UUID32 0x20
BLE_HS_ADV_TYPE_SVC_DATA_UUID128 0x21
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BLE_HS_ADV_TYPE_URI 0x24

BLE_HS_ADV_TYPE_MESH_PROV 0x29
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BLE_HS_ADV_TYPE_MESH_MESSAGE 0x2a
ƒ
BLE_HS_ADV_TYPE_MESH_BEACON 0x2b
„
BLE_HS_ADV_TYPE_MFG_DATA 0xff
†
BLE_HS_ADV_FLAGS_LEN 1
‡
BLE_HS_ADV_F_DISC_LTD 0x01
ˆ
BLE_HS_ADV_F_DISC_GEN 0x02
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BLE_HS_ADV_F_BREDR_UNSUP 0x04
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BLE_HS_ADV_TX_PWR_LVL_LEN 1
‘
BLE_HS_ADV_TX_PWR_LVL_AUTO (-128)
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BLE_HS_ADV_SLAVE_ITVL_RANGE_LEN 4
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BLE_HS_ADV_SVC_DATA_UUID16_MIN_LEN 2
—
BLE_HS_ADV_PUBLIC_TGT_ADDR_ENTRY_LEN 6
™
BLE_HS_ADV_APPEARANCE_LEN 2
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BLE_HS_ADV_ADV_ITVL_LEN 2
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BLE_HS_ADV_SVC_DATA_UUID32_MIN_LEN 4
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BLE_HS_ADV_SVC_DATA_UUID128_MIN_LEN 16¤›
 




..\..\..\..\host\nimble\nimble\host\include\C:\Keil_v5\ARM\ARMCC\Bin\..\include\host/ble_hs_adv.h
inttypes.hhost/ble_uuid.h


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..\..\..\..\host\nimble\nimble\host\include\host/ble_hs_adv.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xintuvoidunsigned intNŸó%#
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Pble_hs_adv_parse_func_t+

))»ble_hs_adv_fields`flags:
#uuids16A#num_uuids16:
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#
uuids32K#num_uuids32:
#!uuids32_is_complete
#
uuids128U#num_uuids128:
#!uuids128_is_complete
#
name_#name_len:
# !name_is_complete
# 
tx_pwr_lvlÿ#"!tx_pwr_lvl_is_present
# 
slave_itvl_range_#$svc_data_uuid16_#(svc_data_uuid16_len:
#,public_tgt_addr_#0num_public_tgt_addrs:
#4appearanceI
#6!appearance_is_present
#8
adv_itvlI
#:!adv_itvl_is_present
#<
svc_data_uuid32_#@svc_data_uuid32_len:
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#Luri_#Puri_len:
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H_BLE_HS_ID_ È¿
 




..\..\..\..\host\nimble\nimble\host\include\C:\Keil_v5\ARM\ARMCC\Bin\..\include\..\..\..\..\host\nimble\nimble\include\host/ble_hs_id.h
inttypes.hnimble/ble.h

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..\..\..\..\host\nimble\nimble\host\include\host/ble_hs_id.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x
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H_BLE_HS_HCI_ ”ˆ
 




..\..\..\..\host\nimble\nimble\host\include\C:\Keil_v5\ARM\ARMCC\Bin\..\include\host/ble_hs_hci.h
inttypes.h

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..\..\..\..\host\nimble\nimble\host\include\host/ble_hs_hci.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x
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H_IGNORE_ 
 IGN_1(X) ((void)(X))
!IGN_2(X,__VA_ARGS__...) ((void)(X));IGN_1(__VA_ARGS__)
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#IGN_4(X,__VA_ARGS__...) ((void)(X));IGN_3(__VA_ARGS__)
$IGN_5(X,__VA_ARGS__...) ((void)(X));IGN_4(__VA_ARGS__)
%IGN_6(X,__VA_ARGS__...) ((void)(X));IGN_5(__VA_ARGS__)
&IGN_7(X,__VA_ARGS__...) ((void)(X));IGN_6(__VA_ARGS__)
'IGN_8(X,__VA_ARGS__...) ((void)(X));IGN_7(__VA_ARGS__)
(IGN_9(X,__VA_ARGS__...) ((void)(X));IGN_8(__VA_ARGS__)
)IGN_10(X,__VA_ARGS__...) ((void)(X));IGN_9(__VA_ARGS__)
*IGN_11(X,__VA_ARGS__...) ((void)(X));IGN_10(__VA_ARGS__)
+IGN_12(X,__VA_ARGS__...) ((void)(X));IGN_11(__VA_ARGS__)
,IGN_13(X,__VA_ARGS__...) ((void)(X));IGN_12(__VA_ARGS__)
-IGN_14(X,__VA_ARGS__...) ((void)(X));IGN_13(__VA_ARGS__)
.IGN_15(X,__VA_ARGS__...) ((void)(X));IGN_14(__VA_ARGS__)
/IGN_16(X,__VA_ARGS__...) ((void)(X));IGN_15(__VA_ARGS__)
0IGN_17(X,__VA_ARGS__...) ((void)(X));IGN_16(__VA_ARGS__)
1IGN_18(X,__VA_ARGS__...) ((void)(X));IGN_17(__VA_ARGS__)
2IGN_19(X,__VA_ARGS__...) ((void)(X));IGN_18(__VA_ARGS__)
3IGN_20(X,__VA_ARGS__...) ((void)(X));IGN_19(__VA_ARGS__)
5GET_MACRO(_1,_2,_3,_4,_5,_6,_7,_8,_9,_10,_11,_12,_13,_14,_15,_16,_17,_18,_19,_20,NAME,__VA_ARGS__...) NAME
7IGNORE(__VA_ARGS__...) GET_MACRO(__VA_ARGS__, IGN_20, IGN_19, IGN_18, IGN_17, IGN_16, IGN_15, IGN_14, IGN_13, IGN_12, IGN_11, IGN_10, IGN_9, IGN_8, IGN_7, IGN_6, IGN_5, IGN_4, IGN_3, IGN_2, IGN_1)(__VA_ARGS__)dZ
 




..\..\..\..\host\nimble\porting\nimble\include\log_common/ignore.h


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..\..\..\..\host\nimble\porting\nimble\include\log_common/ignore.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x
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H_LOG_COMMON_ 
 LOG_VERSION_V3 3
"LOG_TYPE_STREAM (0)
#LOG_TYPE_MEMORY (1)
$LOG_TYPE_STORAGE (2)
&LOG_LEVEL_DEBUG (0)
'LOG_LEVEL_INFO (1)
(LOG_LEVEL_WARN (2)
)LOG_LEVEL_ERROR (3)
*LOG_LEVEL_CRITICAL (4)
,LOG_LEVEL_MAX (15)
.LOG_LEVEL_STR(level) (LOG_LEVEL_DEBUG == level ? "DEBUG" : (LOG_LEVEL_INFO == level ? "INFO" : (LOG_LEVEL_WARN == level ? "WARN" : (LOG_LEVEL_ERROR == level ? "ERROR" : (LOG_LEVEL_CRITICAL == level ? "CRITICAL" : "UNKNOWN")))))
:LOG_MODULE_DEFAULT 0
;LOG_MODULE_OS 1
<LOG_MODULE_NEWTMGR 2
=LOG_MODULE_NIMBLE_CTLR 3
>LOG_MODULE_NIMBLE_HOST 4
?LOG_MODULE_NFFS 5
@LOG_MODULE_REBOOT 6
ALOG_MODULE_IOTIVITY 7
BLOG_MODULE_TEST 8
DLOG_MODULE_PERUSER 64
ELOG_MODULE_MAX (255)
GLOG_ETYPE_STRING (0)
HLOG_ETYPE_CBOR (1)
ILOG_ETYPE_BINARY (2)
LUTC01_01_2016 1451606400
NLOG_NAME_MAX_LEN (64)
SLOG_SYSLEVEL ((uint8_t)MYNEWT_VAL_LOG_LEVEL)
cLOG_MOD_LEVEL_IS_ACTIVE(mod_level,entry_level) (LOG_LEVEL <= (entry_level) && (mod_level) <= (entry_level))
gLOGS_NMGR_OP_READ (0)
hLOGS_NMGR_OP_CLEAR (1)
iLOGS_NMGR_OP_APPEND (2)
jLOGS_NMGR_OP_MODULE_LIST (3)
kLOGS_NMGR_OP_LEVEL_LIST (4)
lLOGS_NMGR_OP_LOGS_LIST (5)
mLOGS_NMGR_OP_SET_WATERMARK (6)
nLOGS_NMGR_OP_MODLEVEL (8)
pLOG_PRINTF_MAX_ENTRY_LEN (128)°¦
 




..\..\..\..\host\nimble\porting\nimble\include\C:\Keil_v5\ARM\ARMCC\Bin\..\include\log_common/log_common.h
stdint.hlog_common/ignore.h


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..\..\..\..\host\nimble\porting\nimble\include\log_common/log_common.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x)µlog_infoli_next_indexY
#li_version:
#OÓ%Ÿ
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g_log_info



__LOG_H__ \P
 




..\..\..\..\host\nimble\porting\nimble\include\log/log.h




..\..\..\..\host\nimble\porting\nimble\include\log/log.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xuvoid"î-log<˜

log_dummy$ôlogV


H_MODLOG_ 
MODLOG_MODULE_DFLT 255
"MODLOG_DEBUG(ml_mod_,__VA_ARGS__...) IGNORE(__VA_ARGS__)
)MODLOG_INFO(ml_mod_,__VA_ARGS__...) IGNORE(__VA_ARGS__)
0MODLOG_WARN(ml_mod_,__VA_ARGS__...) IGNORE(__VA_ARGS__)
7MODLOG_ERROR(ml_mod_,__VA_ARGS__...) IGNORE(__VA_ARGS__)
>MODLOG_CRITICAL(ml_mod_,__VA_ARGS__...) IGNORE(__VA_ARGS__)
AMODLOG(ml_lvl_,ml_mod_,__VA_ARGS__...) MODLOG_ ## ml_lvl_((ml_mod_), __VA_ARGS__)¸®
 




..\..\..\..\host\nimble\porting\nimble\include\C:\Keil_v5\ARM\ARMCC\Bin\..\include\modlog/modlog.h
stdio.hlog_common/log_common.h
log/log.h


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..\..\..\..\host\nimble\porting\nimble\include\modlog/modlog.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x
    


H_MYNEWT_LOGCFG_     
BLE_HS_LOG_DEBUG(__VA_ARGS__...) IGNORE(__VA_ARGS__)
BLE_HS_LOG_INFO(__VA_ARGS__...) MODLOG_INFO(4, __VA_ARGS__)
BLE_HS_LOG_WARN(__VA_ARGS__...) MODLOG_WARN(4, __VA_ARGS__)
BLE_HS_LOG_ERROR(__VA_ARGS__...) MODLOG_ERROR(4, __VA_ARGS__)
BLE_HS_LOG_CRITICAL(__VA_ARGS__...) MODLOG_CRITICAL(4, __VA_ARGS__)
BLE_HS_LOG_DISABLED(__VA_ARGS__...) MODLOG_DISABLED(4, __VA_ARGS__)
DFLT_LOG_DEBUG(__VA_ARGS__...) IGNORE(__VA_ARGS__)
DFLT_LOG_INFO(__VA_ARGS__...) MODLOG_INFO(0, __VA_ARGS__)
DFLT_LOG_WARN(__VA_ARGS__...) MODLOG_WARN(0, __VA_ARGS__)
DFLT_LOG_ERROR(__VA_ARGS__...) MODLOG_ERROR(0, __VA_ARGS__)
DFLT_LOG_CRITICAL(__VA_ARGS__...) MODLOG_CRITICAL(0, __VA_ARGS__)
DFLT_LOG_DISABLED(__VA_ARGS__...) MODLOG_DISABLED(0, __VA_ARGS__)„
 




..\..\..\..\host\nimble\porting\nimble\include\logcfg/logcfg.h
modlog/modlog.h
log_common/log_common.h


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..\..\..\..\host\nimble\porting\nimble\include\logcfg/logcfg.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x
 

H_BLE_HS_LOG_ 
%BLE_HS_LOG(lvl,__VA_ARGS__...) BLE_HS_LOG_ ## lvl(__VA_ARGS__)
(BLE_HS_LOG_ADDR(lvl,addr) BLE_HS_LOG_ ## lvl("%02x:%02x:%02x:%02x:%02x:%02x", (addr)[5], (addr)[4], (addr)[3], (addr)[2], (addr)[1], (addr)[0])ĸ
 




..\..\..\..\host\nimble\nimble\host\include\..\..\..\..\host\nimble\porting\nimble\include\host/ble_hs_log.h
modlog/modlog.hlog/log.hlogcfg/logcfg.h

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..\..\..\..\host\nimble\nimble\host\include\host/ble_hs_log.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x


H_BLE_HS_MBUF_ ”‰
 




..\..\..\..\host\nimble\nimble\host\include\C:\Keil_v5\ARM\ARMCC\Bin\..\include\host/ble_hs_mbuf.h
inttypes.h

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..\..\..\..\host\nimble\nimble\host\include\host/ble_hs_mbuf.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x


H_BLE_HS_STOP_ `V
 




..\..\..\..\host\nimble\nimble\host\include\host/ble_hs_stop.h


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..\..\..\..\host\nimble\nimble\host\include\host/ble_hs_stop.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xintuvoid"ûPble_hs_stop_fns

!*´"4
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H_BLE_IBEACON_ `V
 




..\..\..\..\host\nimble\nimble\host\include\host/ble_ibeacon.h


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..\..\..\..\host\nimble\nimble\host\include\host/ble_ibeacon.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x


H_BLE_SM_ 
BLE_SM_ERR_PASSKEY 0x01
BLE_SM_ERR_OOB 0x02
 BLE_SM_ERR_AUTHREQ 0x03
!BLE_SM_ERR_CONFIRM_MISMATCH 0x04
"BLE_SM_ERR_PAIR_NOT_SUPP 0x05
#BLE_SM_ERR_ENC_KEY_SZ 0x06
$BLE_SM_ERR_CMD_NOT_SUPP 0x07
%BLE_SM_ERR_UNSPECIFIED 0x08
&BLE_SM_ERR_REPEATED 0x09
'BLE_SM_ERR_INVAL 0x0a
(BLE_SM_ERR_DHKEY 0x0b
)BLE_SM_ERR_NUMCMP 0x0c
*BLE_SM_ERR_ALREADY 0x0d
+BLE_SM_ERR_CROSS_TRANS 0x0e
,BLE_SM_ERR_MAX_PLUS_1 0x0f
.BLE_SM_PAIR_ALG_JW 0
/BLE_SM_PAIR_ALG_PASSKEY 1
0BLE_SM_PAIR_ALG_OOB 2
1BLE_SM_PAIR_ALG_NUMCMP 3
3BLE_SM_PAIR_KEY_DIST_ENC 0x01
4BLE_SM_PAIR_KEY_DIST_ID 0x02
5BLE_SM_PAIR_KEY_DIST_SIGN 0x04
6BLE_SM_PAIR_KEY_DIST_LINK 0x08
7BLE_SM_PAIR_KEY_DIST_RESERVED 0xf0
9BLE_SM_IO_CAP_DISP_ONLY 0x00
:BLE_SM_IO_CAP_DISP_YES_NO 0x01
;BLE_SM_IO_CAP_KEYBOARD_ONLY 0x02
<BLE_SM_IO_CAP_NO_IO 0x03
=BLE_SM_IO_CAP_KEYBOARD_DISP 0x04
>BLE_SM_IO_CAP_RESERVED 0x05
@BLE_SM_PAIR_OOB_NO 0x00
ABLE_SM_PAIR_OOB_YES 0x01
BBLE_SM_PAIR_OOB_RESERVED 0x02
DBLE_SM_PAIR_AUTHREQ_BOND 0x01
EBLE_SM_PAIR_AUTHREQ_MITM 0x04
FBLE_SM_PAIR_AUTHREQ_SC 0x08
GBLE_SM_PAIR_AUTHREQ_KEYPRESS 0x10
HBLE_SM_PAIR_AUTHREQ_RESERVED 0xe2
JBLE_SM_PAIR_KEY_SZ_MIN 7
KBLE_SM_PAIR_KEY_SZ_MAX 16
RBLE_SM_IOACT_NONE 0
SBLE_SM_IOACT_OOB 1
TBLE_SM_IOACT_INPUT 2
UBLE_SM_IOACT_DISP 3
VBLE_SM_IOACT_NUMCMP 4
WBLE_SM_IOACT_OOB_SC 5
XBLE_SM_IOACT_MAX_PLUS_ONE 6´«
 




..\..\..\..\host\nimble\nimble\host\include\C:\Keil_v5\ARM\ARMCC\Bin\..\include\..\..\..\..\config\host/ble_sm.h
inttypes.hnimble_syscfg.h

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..\..\..\..\host\nimble\nimble\host\include\host/ble_sm.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x)¯ble_sm_sc_oob_data ‘:

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BLE_STORE_OBJ_TYPE_OUR_SEC 1
BLE_STORE_OBJ_TYPE_PEER_SEC 2
 BLE_STORE_OBJ_TYPE_CCCD 3
#BLE_STORE_EVENT_OVERFLOW 1
&BLE_STORE_EVENT_FULL 2È¿
 




..\..\..\..\host\nimble\nimble\host\include\C:\Keil_v5\ARM\ARMCC\Bin\..\include\..\..\..\..\host\nimble\nimble\include\host/ble_store.h
inttypes.hnimble/ble.h

0
..\..\..\..\host\nimble\nimble\host\include\host/ble_store.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xunsigned intintuvoid) ble_store_value_secPpeer_addrÌ    #key_size:
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&'( )*+,-.
7BLE_HS_FOREVER INT32_MAX
;BLE_HS_CONN_HANDLE_NONE 0xffff
GBLE_HS_EAGAIN 1
HBLE_HS_EALREADY 2
IBLE_HS_EINVAL 3
JBLE_HS_EMSGSIZE 4
KBLE_HS_ENOENT 5
LBLE_HS_ENOMEM 6
MBLE_HS_ENOTCONN 7
NBLE_HS_ENOTSUP 8
OBLE_HS_EAPP 9
PBLE_HS_EBADDATA 10
QBLE_HS_EOS 11
RBLE_HS_ECONTROLLER 12
SBLE_HS_ETIMEOUT 13
TBLE_HS_EDONE 14
UBLE_HS_EBUSY 15
VBLE_HS_EREJECT 16
WBLE_HS_EUNKNOWN 17
XBLE_HS_EROLE 18
YBLE_HS_ETIMEOUT_HCI 19
ZBLE_HS_ENOMEM_EVT 20
[BLE_HS_ENOADDR 21
\BLE_HS_ENOTSYNCED 22
]BLE_HS_EAUTHEN 23
^BLE_HS_EAUTHOR 24
_BLE_HS_EENCRYPT 25
`BLE_HS_EENCRYPT_KEY_SZ 26
aBLE_HS_ESTORE_CAP 27
bBLE_HS_ESTORE_FAIL 28
cBLE_HS_EPREEMPTED 29
dBLE_HS_EDISABLED 30
eBLE_HS_ESTALLED 31
hBLE_HS_ERR_ATT_BASE 0x100
kBLE_HS_ATT_ERR(x) ((x) ? BLE_HS_ERR_ATT_BASE + (x) : 0)
nBLE_HS_ERR_HCI_BASE 0x200
qBLE_HS_HCI_ERR(x) ((x) ? BLE_HS_ERR_HCI_BASE + (x) : 0)
tBLE_HS_ERR_L2C_BASE 0x300
wBLE_HS_L2C_ERR(x) ((x) ? BLE_HS_ERR_L2C_BASE + (x) : 0)
zBLE_HS_ERR_SM_US_BASE 0x400
}BLE_HS_SM_US_ERR(x) ((x) ? BLE_HS_ERR_SM_US_BASE + (x) : 0)
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BLE_HS_ERR_SM_PEER_BASE 0x500
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BLE_HS_SM_PEER_ERR(x) ((x) ? BLE_HS_ERR_SM_PEER_BASE + (x) : 0)
†
BLE_HS_ERR_HW_BASE 0x600
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BLE_HS_HW_ERR(x) (BLE_HS_ERR_HW_BASE + (x))
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BLE_HS_IO_DISPLAY_ONLY 0x00
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BLE_HS_IO_DISPLAY_YESNO 0x01
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BLE_HS_IO_KEYBOARD_ONLY 0x02
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BLE_HS_IO_NO_INPUT_OUTPUT 0x03
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BLE_HS_IO_KEYBOARD_DISPLAY 0x04

 




..\..\..\..\host\nimble\nimble\host\include\C:\Keil_v5\ARM\ARMCC\Bin\..\include\..\..\..\..\host\nimble\nimble\include\host/ble_hs.h
inttypes.hnimble/hci_common.hhost/ble_att.h
host/ble_eddystone.h
host/ble_gap.h
host/ble_gatt.h
host/ble_hs_adv.h
host/ble_hs_id.h
host/ble_hs_hci.h
host/ble_hs_log.h
host/ble_hs_mbuf.h
host/ble_hs_stop.h
host/ble_ibeacon.h
host/ble_l2cap.h
host/ble_sm.h
host/ble_store.h
host/ble_uuid.h
nimble/nimble_npl.h


..\..\..\..\host\nimble\nimble\host\include\host/ble_hs.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xintuvoidunsigned intPble_hs_reset_fnü
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)Áble_hs_cfg(gatts_register_cbÁ#gatts_register_argÇ#sm_io_cap:
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!sm_scü#
!sm_keypressü#
sm_our_key_dist:
#
sm_their_key_dist:
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*+,-

H_BLE_GAP_CONN_ 
KBLE_GAP_CONN_MODE_MAX 3
LBLE_GAP_DISC_MODE_MAX 34
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..\..\..\..\host\nimble\nimble\host\src\C:\Keil_v5\ARM\ARMCC\Bin\..\include\..\..\..\..\config\..\..\..\..\host\nimble\porting\nimble\include\..\..\..\..\host\nimble\nimble\host\include\ble_gap_priv.h
inttypes.hnimble_syscfg.hstats/stats.hhost/ble_gap.h

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..\..\..\..\host\nimble\nimble\host\src\ble_gap_priv.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x-hci_le_conn_upd_complete-hci_le_conn_param_req-hci_disconn_complete-hci_encrypt_change-ble_hs_adv-stats_ble_gap_stats)…ble_gap_conn_complete status:
#connection_handleI
#role:
#peer_addr_type:
#Þ:

peer_addrÓ
#conn_itvlI
#conn_latencyI
#supervision_timeoutI
#master_clk_acc:
#Ø:

local_rpaM#ô:

peer_rpai#qble_gap_statsS


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/012

H_BLE_GATT_PRIV_ 
YBLE_GATT_CHR_DECL_SZ_16 5
ZBLE_GATT_CHR_DECL_SZ_128 19
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BLE_GATTS_CLT_CFG_F_NOTIFY 0x0001

BLE_GATTS_CLT_CFG_F_INDICATE 0x0002
Ž
BLE_GATTS_CLT_CFG_F_MODIFIED 0x0080
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BLE_GATTS_CLT_CFG_F_RESERVED 0xfffc
‘
BLE_GATTS_INC_SVC_LEN_NO_UUID 4
’
BLE_GATTS_INC_SVC_LEN_UUID 6
÷
 




..\..\..\..\host\nimble\nimble\host\src\..\..\..\..\config\..\..\..\..\host\nimble\porting\nimble\include\..\..\..\..\host\nimble\nimble\host\include\ble_gatt_priv.h
nimble_syscfg.hstats/stats.hhost/ble_gatt.h

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..\..\..\..\host\nimble\nimble\host\src\ble_gatt_priv.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xint)âble_gatt_resourcessvcsI
#incsI
#chrsI
#dscsI
#cccdsI
#attrsI
#
qble_gattc_statsŽ


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-stats_ble_gattc_stats-stats_ble_gatts_statsPble_gatts_conn_flags:

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#"Ú
6Hb
ble_gattc_statsx
ble_gatts_stats
4567

H_BLE_HS_HCI_PRIV_ 
BLE_HS_HCI_LE_FEAT_ENCRYPTION (0x00000001)
 BLE_HS_HCI_LE_FEAT_CONN_PARAM_REQUEST (0x00000002)
!BLE_HS_HCI_LE_FEAT_EXT_REJECT (0x00000004)
"BLE_HS_HCI_LE_FEAT_SLAVE_FEAT_EXCHANGE (0x00000008)
#BLE_HS_HCI_LE_FEAT_PING (0x00000010)
$BLE_HS_HCI_LE_FEAT_DATA_PACKET_LENGTH_EXT (0x00000020)
%BLE_HS_HCI_LE_FEAT_LL_PRIVACY (0x00000040)
&BLE_HS_HCI_LE_FEAT_EXT_SCANNER_FILTER_POLICIES (0x00000080)
'BLE_HS_HCI_LE_FEAT_2M_PHY (0x00000100)
(BLE_HS_HCI_LE_FEAT_STABLE_MOD_INDEX_TX (0x00000200)
)BLE_HS_HCI_LE_FEAT_STABLE_MOD_INDEX_RX (0x00000400)
*BLE_HS_HCI_LE_FEAT_CODED_PHY (0x00000800)
+BLE_HS_HCI_LE_FEAT_EXT_ADV (0x00001000)
,BLE_HS_HCI_LE_FEAT_PERIODIC_ADV (0x00002000)
-BLE_HS_HCI_LE_FEAT_CSA2 (0x00004000)
.BLE_HS_HCI_LE_FEAT_POWER_CLASS_1 (0x00008000)
/BLE_HS_HCI_LE_FEAT_MIN_NUM_USED_CHAN (0x00010000)œ
 




..\..\..\..\host\nimble\nimble\host\src\..\..\..\..\host\nimble\nimble\include\ble_hs_hci_priv.h
nimble/hci_common.h

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..\..\..\..\host\nimble\nimble\host\src\ble_hs_hci_priv.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xint:
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9:;

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BLE_L2CAP_SIG_HDR_SZ 4
'BLE_L2CAP_SIG_REJECT_MIN_SZ 2
-BLE_L2CAP_SIG_UPDATE_REQ_SZ 8
5BLE_L2CAP_SIG_UPDATE_RSP_SZ 2
:BLE_L2CAP_SIG_UPDATE_RSP_RESULT_ACCEPT 0x0000
;BLE_L2CAP_SIG_UPDATE_RSP_RESULT_REJECT 0x0001„{
 




..\..\..\..\host\nimble\nimble\host\src\..\..\..\..\config\ble_l2cap_sig_priv.h
nimble_syscfg.h


..\..\..\..\host\nimble\nimble\host\src\ble_l2cap_sig_priv.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xintuvoid;ø
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..\..\..\..\host\nimble\nimble\host\src\C:\Keil_v5\ARM\ARMCC\Bin\..\include\..\..\..\..\config\..\..\..\..\host\nimble\porting\nimble\include\..\..\..\..\host\nimble\nimble\host\include\ble_l2cap_coc_priv.h
inttypes.hnimble_syscfg.hos/queue.hos/os_mbuf.hhost/ble_l2cap.hble_l2cap_sig_priv.h


0
..\..\..\..\host\nimble\nimble\host\src\ble_l2cap_coc_priv.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xuvoidint"ò;¯
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7BLE_L2CAP_CID_BLACK_HOLE 0xffff
9BLE_L2CAP_HDR_SZ 4
kBLE_L2CAP_CHAN_F_TXED_MTU 0x01
lBLE_L2CAP_CHAN_F_DISCONNECTING 0x02D
;

 




..\..\..\..\host\nimble\nimble\host\src\..\..\..\..\host\nimble\nimble\host\include\C:\Keil_v5\ARM\ARMCC\Bin\..\include\..\..\..\..\host\nimble\porting\nimble\include\ble_l2cap_priv.h
ble_l2cap_coc_priv.h
host/ble_l2cap.hinttypes.hstats/stats.hos/queue.hos/os_mbuf.h

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..\..\..\..\host\nimble\nimble\host\src\ble_l2cap_priv.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xintN‚î%Á
Pble_l2cap_chan_flags:

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EFG

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&BLE_HS_CONN_F_TERMINATING 0x02
'BLE_HS_CONN_F_TX_FRAG 0x04Ⱦ
 




..\..\..\..\host\nimble\nimble\host\src\C:\Keil_v5\ARM\ARMCC\Bin\..\include\ble_hs_conn_priv.h
inttypes.hble_l2cap_priv.h
ble_gatt_priv.h
ble_att_priv.h



..\..\..\..\host\nimble\nimble\host\src\ble_hs_conn_priv.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xuvoidint"ð)ðble_hs_conn_addrsour_id_addrÌ    #peer_id_addrÌ    #our_ota_addrÌ    #peer_ota_addrÌ    #Nÿö%
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..\..\..\..\host\nimble\nimble\host\src\ble_hs_atomic_priv.h
ble_hs_conn_priv.h


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..\..\..\..\host\nimble\nimble\host\src\ble_hs_atomic_priv.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x
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H_BLE_HS_MBUF_PRIV_ \R
 




..\..\..\..\host\nimble\nimble\host\src\ble_hs_mbuf_priv.h


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..\..\..\..\host\nimble\nimble\host\src\ble_hs_mbuf_priv.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x
QRS

H_BLE_HS_STARTUP_ `U
 




..\..\..\..\host\nimble\nimble\host\src\ble_hs_startup_priv.h


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..\..\..\..\host\nimble\nimble\host\src\ble_hs_startup_priv.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x
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H_BLE_SM_PRIV_ 
$BLE_SM_MTU 65
&BLE_SM_OP_PAIR_REQ 0x01
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(BLE_SM_OP_PAIR_CONFIRM 0x03
)BLE_SM_OP_PAIR_RANDOM 0x04
*BLE_SM_OP_PAIR_FAIL 0x05
+BLE_SM_OP_ENC_INFO 0x06
,BLE_SM_OP_MASTER_ID 0x07
-BLE_SM_OP_IDENTITY_INFO 0x08
.BLE_SM_OP_IDENTITY_ADDR_INFO 0x09
/BLE_SM_OP_SIGN_INFO 0x0a
0BLE_SM_OP_SEC_REQ 0x0b
1BLE_SM_OP_PAIR_PUBLIC_KEY 0x0c
2BLE_SM_OP_PAIR_DHKEY_CHECK 0x0d
3BLE_SM_OP_PAIR_KEYPRESS_NOTIFY 0x0e
Æ
BLE_SM_PROC_STATE_NONE ((uint8_t)-1)
È
BLE_SM_PROC_STATE_PAIR 0
É
BLE_SM_PROC_STATE_CONFIRM 1
Ê
BLE_SM_PROC_STATE_RANDOM 2
Ë
BLE_SM_PROC_STATE_LTK_START 3
Ì
BLE_SM_PROC_STATE_LTK_RESTORE 4
Í
BLE_SM_PROC_STATE_ENC_START 5
Î
BLE_SM_PROC_STATE_ENC_RESTORE 6
Ï
BLE_SM_PROC_STATE_KEY_EXCH 7
Ð
BLE_SM_PROC_STATE_SEC_REQ 8
Ñ
BLE_SM_PROC_STATE_PUBLIC_KEY 9
Ò
BLE_SM_PROC_STATE_DHKEY_CHECK 10
Ó
BLE_SM_PROC_STATE_CNT 11
Õ
BLE_SM_PROC_F_INITIATOR 0x01
Ö
BLE_SM_PROC_F_IO_INJECTED 0x02
×
BLE_SM_PROC_F_ADVANCE_ON_IO 0x04
Ø
BLE_SM_PROC_F_AUTHENTICATED 0x08
Ù
BLE_SM_PROC_F_SC 0x10
Ú
BLE_SM_PROC_F_BONDING 0x20
Ü
BLE_SM_KE_F_ENC_INFO 0x01
Ý
BLE_SM_KE_F_MASTER_ID 0x02
Þ
BLE_SM_KE_F_ID_INFO 0x04
ß
BLE_SM_KE_F_ADDR_INFO 0x08
à
BLE_SM_KE_F_SIGN_INFO 0x10
ìble_sm_sc_io_action(proc,action) (BLE_HS_ENOTSUP)
íble_sm_sc_confirm_exec(proc,res) 
îble_sm_sc_random_exec(proc,res) 
ïble_sm_sc_random_rx(proc,res) 
ðble_sm_sc_public_key_exec(proc,res,arg) 
ñble_sm_sc_public_key_rx(conn_handle,op,om,res) 
òble_sm_sc_dhkey_check_exec(proc,res,arg) 
óble_sm_sc_dhkey_check_rx(conn_handle,op,om,res) 
ôble_sm_sc_init() 0
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..\..\..\..\host\nimble\nimble\host\src\C:\Keil_v5\ARM\ARMCC\Bin\..\include\..\..\..\..\config\..\..\..\..\host\nimble\porting\nimble\include\..\..\..\..\host\nimble\nimble\include\ble_sm_priv.h
inttypes.hnimble_syscfg.hos/queue.hnimble/nimble_opt.h

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..\..\..\..\host\nimble\nimble\host\src\ble_sm_priv.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xunsigned intintuvoid*¢""
stqe_next
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opcode:
#÷:
datam#
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#oob_data_flag:
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authreq:
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#)Êble_sm_pair_confirm¼:

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H_BLE_HS_ADV_PRIV_ \Q
 




..\..\..\..\host\nimble\nimble\host\src\ble_hs_adv_priv.h


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..\..\..\..\host\nimble\nimble\host\src\ble_hs_adv_priv.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x
]^_

H_BLE_HS_FLOW_PRIV_ …
 




..\..\..\..\host\nimble\nimble\host\src\C:\Keil_v5\ARM\ARMCC\Bin\..\include\ble_hs_flow_priv.h
inttypes.h

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..\..\..\..\host\nimble\nimble\host\src\ble_hs_flow_priv.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x
abcd

H_BLE_HS_PVCY_PRIV_ …
 




..\..\..\..\host\nimble\nimble\host\src\C:\Keil_v5\ARM\ARMCC\Bin\..\include\ble_hs_pvcy_priv.h
inttypes.h



..\..\..\..\host\nimble\nimble\host\src\ble_hs_pvcy_priv.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x:
ÿ
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qble_hs_pvcy_default_irkö

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ÿble_hs_pvcy_default_irk
fgh

H_BLE_HS_ID_PRIV_ Œƒ
 




..\..\..\..\host\nimble\nimble\host\src\C:\Keil_v5\ARM\ARMCC\Bin\..\include\ble_hs_id_priv.h
inttypes.h

ì
..\..\..\..\host\nimble\nimble\host\src\ble_hs_id_priv.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x
jkl

H_BLE_HS_PERIODIC_SYNC_ ØÌ
 




..\..\..\..\host\nimble\nimble\host\src\C:\Keil_v5\ARM\ARMCC\Bin\..\include\..\..\..\..\host\nimble\porting\nimble\include\ble_hs_periodic_sync_priv.h
inttypes.hos/queue.h

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..\..\..\..\host\nimble\nimble\host\src\ble_hs_periodic_sync_priv.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xuvoid"ù*œ"
sle_next
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#sync_handleI
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H_BLE_UUID_PRIV_ ˜
 




..\..\..\..\host\nimble\nimble\host\src\..\..\..\..\host\nimble\nimble\host\include\ble_uuid_priv.h
host/ble_uuid.h

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..\..\..\..\host\nimble\nimble\host\src\ble_uuid_priv.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x
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?BLE_HS_ENABLED_STATE_ON 2
BBLE_HS_MAX_CONNECTIONS MYNEWT_VAL(BLE_MAX_CONNECTIONS)
JBLE_HS_ATT_SVR_QUEUED_WRITE_TMO MYNEWT_VAL(BLE_ATT_SVR_QUEUED_WRITE_TMO)
–
BLE_HS_DBG_ASSERT(x) 
—
BLE_HS_DBG_ASSERT_EVAL(x) ((void)(x))ðå
 




..\..\..\..\host\nimble\nimble\host\src\C:\Keil_v5\ARM\ARMCC\Bin\..\include\..\..\..\..\host\nimble\nimble\host\include\..\..\..\..\host\nimble\nimble\include\..\..\..\..\host\nimble\porting\nimble\include\ble_hs_priv.h
assert.hinttypes.hble_att_cmd_priv.h
ble_att_priv.h
ble_gap_priv.h
ble_gatt_priv.h
ble_hs_hci_priv.h
ble_hs_atomic_priv.h
ble_hs_conn_priv.h
ble_hs_mbuf_priv.h
ble_hs_startup_priv.h
ble_l2cap_priv.h
ble_l2cap_sig_priv.h
ble_l2cap_coc_priv.h
ble_sm_priv.h
ble_hs_adv_priv.h
ble_hs_flow_priv.h
ble_hs_pvcy_priv.h
ble_hs_id_priv.h
ble_hs_periodic_sync_priv.h
ble_uuid_priv.h
host/ble_hs.hnimble/nimble_opt.hstats/stats.h

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..\..\..\..\host\nimble\nimble\host\src\ble_hs_priv.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x-os_event-stats_ble_hs_stats*µstqh_first—#stqh_last›#)Ýble_mqueuehead    
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string.herrno.hnimble_syscfg.h
os/os.hhost/ble_l2cap.hnimble/ble.hnimble/hci_common.hble_hs_priv.hble_l2cap_coc_priv.h..\..\..\..\host\nimble\nimble\host\src\ble_l2cap.cble_l2cap.c

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%Component: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed]armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=9931,9931,6642 --cpu=Cortex-M0 --fpu=SoftVFP --output=.\objects\ble_l2cap.o --vfemode=force
Input Comments:p10f38-3Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M0 --fpu=SoftVFP --apcs=/interwork/interwork --no_divide ble_l2cap.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]ArmCC --c99 --split_sections --debug -c --gnu -o.\objects\ble_l2cap.o --depend=.\objects\ble_l2cap.d --cpu=Cortex-M0 --apcs=interwork -O3 -Otime --diag_suppress=9931 --preinclude=soc_config.h -I..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include -I..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc -I..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include -I..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\radio\prf_lib\include -I..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\SEGGER_RTT\RTT -I..\..\..\..\os\freertos\include -I..\..\..\..\os\freertos\portable\RVDS\ARM_CM0 -I..\..\..\..\host\nimble\ext\tinycrypt\include -I..\..\..\..\host\nimble\nimble\include -I..\..\..\..\host\nimble\nimble\host\include -I..\..\..\..\host\nimble\nimble\host\util\include -I..\..\..\..\host\nimble\nimble\transport\include -I..\..\..\..\host\nimble\porting\nimble\include -I..\..\..\..\host\nimble\porting\npl\freertos\include -I..\..\..\..\host\nimble\nimble\host\services\gap\include -I..\..\..\..\host\nimble\nimble\host\services\gatt\include -I..\..\..\..\host\nimble\nimble\host\services\ans\include -I..\..\..\..\host\nimble\nimble\host\store\config\include -I..\..\..\..\host\nimble\ext\base64\include -I..\..\..\..\controller\pan107x_spark\include\utils -I..\..\..\..\controller\pan107x_spark\include -I..\..\..\..\host\kv_store -I.\configuration -I..\src -I..\..\..\..\config -I..\..\..\..\component\app_log -I..\..\..\..\soc -I..\..\..\..\utilities -I..\..\..\..\host -I..\..\..\..\component\kv_store -I..\..\..\..\component\ble_dev_filter -I..\..\..\..\host\smp_bt -I..\..\..\..\host\smp_bt\tinycbor\include -I..\..\..\..\host\smp_bt\mcumgr\cborattr\include -I..\..\..\..\host\smp_bt\mcumgr\img_mgmt\include -I..\..\..\..\host\smp_bt\mcumgr\util\include -I..\..\..\..\host -I..\..\..\..\host\smp_bt\mcumgr\mgmt\include -I..\..\..\..\host\smp_bt\mcumgr\smp\include -I.\RTE\_ble_central_periph -IC:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.0\Device\ARM\ARMCM0\Include -IC:\Keil_v5\ARM\CMSIS\Include -D__MICROLIB -D__UVISION_VERSION=530 -DARMCM0 -D_RTE_ -DIP_107x -DCONFIG_FLASH_LINE_MODE=FLASH_X4_MODE -DBLE_EN=1 -D__ORDER_LITTLE_ENDIAN__=2 -D__BYTE_ORDER__=2 --omf_browse=.\objects\ble_l2cap.crf ..\..\..\..\host\nimble\nimble\host\src\ble_l2cap.c^Š
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