/**************************************************************************//**
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* @file pan_i2c.h
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* @version V1.00
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* $Revision: 2 $
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* $Date: 2023/11/08 $
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* @brief Panchip series I2C driver header file
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*
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* @note
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* Copyright (C) 2023 Panchip Technology Corp. All rights reserved.
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*****************************************************************************/
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#ifndef __PAN_I2C_H__
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#define __PAN_I2C_H__
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/**
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* @brief I2c Interface
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* @defgroup i2c_interface I2c Interface
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* @{
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*/
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/**
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* @brief Structure with i2c init feature.
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*
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* @param I2C_ClockSpeed Specifies the clock frequency.
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* @param I2C_Mode Specifies the I2C mode.This parameter can be a value of
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* \ref PAN_I2C_MODE_MASTER,\ref PAN_I2C_MODE_SLAVE
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* @param I2C_DutyCycle Specifies the I2C fast mode duty cycle.This parameter
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* can be a value of \ref I2C_DutyCycle_16_9, \ref I2C_DutyCycle_2
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* @param I2C_OwnAddress1 Specifies the first device own address,
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* This parameter can be a 7-bit or 10-bit address.
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* @param I2C_AcknowledgedAddress Specifies if 7-bit or 10-bit address is acknowledged.
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* This parameter can be a value of
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* \ref I2C_AcknowledgedAddress_7bit, \ref I2C_AcknowledgedAddress_10bit
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*/
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typedef struct
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{
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uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency.
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This parameter must be set to a value lower than 400kHz */
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uint16_t I2C_Mode; /*!< Specifies the I2C mode.
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This parameter can be a value of @ref I2C_mode */
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uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
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This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
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uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address.
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This parameter can be a 7-bit or 10-bit address. */
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uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
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This parameter can be a value of @ref I2C_acknowledged_address */
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}I2C_InitTypeDef;
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/* Exported constants --------------------------------------------------------*/
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#define I2C_DYNAMIC_TAR_UPDATE 0
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/** @defgroup I2C_mode
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* @brief I2C operational modes
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* @{
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*/
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#define I2C_MODE_MASTER ((uint16_t)0x0021) /*!< I2C Master Mode */
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#define I2C_MODE_SLAVE ((uint16_t)0x0000) /*!< I2C Slave Mode */
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/**
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* @brief Check if the I2C mode is valid.
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* @param MODE: I2C mode to check.
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* @retval true if the mode is valid, false otherwise.
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*/
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#define IS_I2C_MODE(MODE) (((MODE) == I2C_MODE_MASTER) || ((MODE) == I2C_MODE_SLAVE))
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/** @} */
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/** @defgroup I2C_speed_mode
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* @brief I2C communication speed modes
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* @{
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*/
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#define I2C_SPEED_STANDARD_MODE (uint16_t)(0x0002) /*!< Standard Mode (up to 100 Kbps) */
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#define I2C_SPEED_FAST_MODE (uint16_t)(0x0004) /*!< Fast Mode (up to 400 Kbps) */
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#define I2C_SPEED_HIGH_MODE (uint16_t)(0x0006) /*!< High-Speed Mode (up to 3.4 Mbps) */
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/** @} */
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/** @defgroup I2C_duty_cycle
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* @brief I2C fast mode duty cycle options
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* @{
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*/
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#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
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#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
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#define I2C_DutyCycle_1_1 ((uint16_t)0x0800)
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#define I2C_DutyCycle_1_2 ((uint16_t)0x0400)
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/* @brief I2C fast mode duty cycle validation */
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#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
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((CYCLE) == I2C_DutyCycle_2))
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/** @} */
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/** @defgroup I2C_transfer_direction
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* @{
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*/
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#define I2C_Direction_Transmitter ((uint16_t)0x0000)
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#define I2C_Direction_Receiver ((uint16_t)0x0100)
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#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
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((DIRECTION) == I2C_Direction_Receiver))
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/** @} */
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/** @defgroup I2C_acknowledged_address
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* @{
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*/
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#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
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#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
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#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
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((ADDRESS) == I2C_AcknowledgedAddress_10bit))
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/** @} */
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/** @defgroup I2C_Cmd
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* @{
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*/
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#define I2C_CMD_WR ((uint8_t)0x00)
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#define I2C_CMD_RD ((uint8_t)0x01)
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#define I2C_CMD_STOP ((uint8_t)0x02)
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#define I2C_CMD_RESTART ((uint8_t)0x04)
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/** @} */
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/** @defgroup I2C_Receive_FIFO_Threshold_Value
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* @{
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*/
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#define I2C_RX_TL_0 ((uint8_t)0x00)
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#define I2C_RX_TL_1 ((uint8_t)0x01)
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#define I2C_RX_TL_2 ((uint8_t)0x02)
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#define I2C_RX_TL_3 ((uint8_t)0x03)
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#define I2C_RX_TL_4 ((uint8_t)0x04)
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#define I2C_RX_TL_5 ((uint8_t)0x05)
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#define I2C_RX_TL_6 ((uint8_t)0x06)
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#define I2C_RX_TL_7 ((uint8_t)0x07)
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#define I2C_RX_TL_8 ((uint8_t)0x08)
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/** @} */
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/** @defgroup I2C_Transmit_FIFO_Threshold_Value
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* @{
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*/
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#define I2C_TX_TL_0 ((uint8_t)0x00)
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#define I2C_TX_TL_1 ((uint8_t)0x01)
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#define I2C_TX_TL_2 ((uint8_t)0x02)
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#define I2C_TX_TL_3 ((uint8_t)0x03)
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#define I2C_TX_TL_4 ((uint8_t)0x04)
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#define I2C_TX_TL_5 ((uint8_t)0x05)
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#define I2C_TX_TL_6 ((uint8_t)0x06)
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#define I2C_TX_TL_7 ((uint8_t)0x07)
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#define I2C_TX_TL_8 ((uint8_t)0x08)
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/** @} */
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/** @defgroup I2C_interrupts_definition
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* @{
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*/
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#define I2C_IT_RX_UNDER ((uint16_t)0x0001)
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#define I2C_IT_RX_OVER ((uint16_t)0x0002)
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#define I2C_IT_RX_FULL ((uint16_t)0x0004)
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#define I2C_IT_TX_OVER ((uint16_t)0x0008)
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#define I2C_IT_TX_EMPTY ((uint16_t)0x0010)
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#define I2C_IT_RD_REQ ((uint16_t)0x0020)
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#define I2C_IT_TX_ABORT ((uint16_t)0x0040)
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#define I2C_IT_RX_DONE ((uint16_t)0x0080)
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#define I2C_IT_ACTIVITY ((uint16_t)0x0100)
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#define I2C_IT_STOP_DET ((uint16_t)0x0200)
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#define I2C_IT_START_DET ((uint16_t)0x0400)
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#define I2C_IT_GEN_CALL ((uint16_t)0x0800)
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#define I2C_IT_MST_ON_HOLD ((uint16_t)0x2000)
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#define I2C_IT_ALL ((uint16_t)0x2FFF)
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#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x0FFF) == 0x00) && ((IT) != (uint16_t)0x00))
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#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_RX_UNDER) || ((IT) == I2C_IT_RX_OVER) || \
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((IT) == I2C_IT_RX_FULL) || ((IT) == I2C_IT_TX_OVER) || \
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((IT) == I2C_IT_TX_EMPTY) || ((IT) == I2C_IT_RD_REQ) || \
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((IT) == I2C_IT_TX_ABORT) || ((IT) == I2C_IT_RX_DONE) || \
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((IT) == I2C_IT_ACTIVITY) || ((IT) == I2C_IT_STOP_DET) || \
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((IT) == I2C_IT_START_DET)|| ((IT) == I2C_IT_GEN_CALL))
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/** @} */
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/** @defgroup I2C_flags_definition
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* @{
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*/
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#define I2C_FLAG_SLV_ACTIVITY ((uint32_t)0x00000040)
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#define I2C_FLAG_MST_ACTIVITY ((uint32_t)0x00000020)
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#define I2C_FLAG_RFF ((uint32_t)0x00000010)
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#define I2C_FLAG_RFNE ((uint32_t)0x00000008)
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#define I2C_FLAG_TFE ((uint32_t)0x00000004)
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#define I2C_FLAG_TFNF ((uint32_t)0x00000002)
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#define I2C_FLAG_ACTIVITY ((uint32_t)0x00000001)
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#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x007F) == 0x00) && ((FLAG) != (uint16_t)0x00))
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#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_ACTIVITY) || ((FLAG) == I2C_FLAG_TFNF) || \
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((FLAG) == I2C_FLAG_TFE) || ((FLAG) == I2C_FLAG_RFNE) || \
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((FLAG) == I2C_FLAG_RFF) || ((FLAG) == I2C_FLAG_MST_ACTIVITY) || \
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((FLAG) == I2C_FLAG_SLV_ACTIVITY))
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/** @} */
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/** @defgroup I2C_Mask_Definitions
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* @brief I2C mask definitions for various flags and interrupt enables.
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* @{
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*/
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#define FLAG_MASK ((uint32_t)0x007F0FFF) /*!< I2C FLAG mask */
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#define ITEN_MASK ((uint16_t)0x2FFF) /*!< I2C Interrupt Enable mask */
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#define IT_FLAG_MASK ((uint16_t)0x2FFF) /*!< I2C FLAG mask */
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/** @} */
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/**
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* @brief Set I2C mode .
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* @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
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* @param Mode: role of the I2Cx peripheral.
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* This parameter can be: I2C_MODE_MASTER or I2C_MODE_SLAVE.
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* @note This function should be called before enabling
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the I2C Peripheral.
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* @retval None
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*/
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__STATIC_INLINE void I2C_SetMode(I2C_T* I2Cx, uint16_t Mode)
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{
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(Mode == I2C_MODE_MASTER)?(I2Cx->CON |= (I2C_CON_IC_SLAVE_DISABLE | I2C_CON_MASTER_MODE)):(I2Cx->CON &= ~(I2C_CON_IC_SLAVE_DISABLE | I2C_CON_MASTER_MODE));
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}
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/**
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* @brief Set I2C Tx fifo threshold value .
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* @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
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* @param ThresholdValue:Transmit FIFO Threshold Level
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* This parameter can be @I2C_Transmit_FIFO_Threshold_Value.
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* @note Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in
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* IC_RAW_INTR_STAT register). The valid range is 0-8, with the additional
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* restriction that it may not be set to value larger than the depth of the buffer. If an
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* attempt is made to do that, the actual value set will be the maximum depth of the
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* buffer.A value of 0 sets the threshold for 0 entries, and a value of 8 sets the threshold for
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* 8 entries.
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* @retval None
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*/
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__STATIC_INLINE void I2C_SetTxTirggerLevel(I2C_T* I2Cx, uint8_t ThresholdValue)
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{
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I2Cx->TX_TL = (I2Cx->TX_TL & ~I2C_TX_TL) | (ThresholdValue & 0xF);
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}
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/**
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* @brief Set I2C Rx fifo threshold value .
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* @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
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* @param ThresholdValue:Receive FIFO Threshold Level
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* This parameter can be @I2C_Receive_FIFO_Threshold_Value.
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* @note Controls the level of entries (or below) that trigger the RX_FULL interrupt (bit 2 in
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* IC_RAW_INTR_STAT register). The valid range is 0-8, with the additional
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* restriction that it may not be set to value larger than the depth of the buffer. If an
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* attempt is made to do that, the actual value set will be the maximum depth of the
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* buffer.A value of 0 sets the threshold for 0 entries, and a value of 8 sets the threshold for
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* 8 entries.
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* @retval None
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*/
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__STATIC_INLINE void I2C_SetRxTirggerLevel(I2C_T* I2Cx, uint8_t ThresholdValue)
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{
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I2Cx->RX_TL = (I2Cx->RX_TL & ~I2C_RX_TL) | (ThresholdValue & 0xF);
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}
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/**
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* @brief Enables or disables the specified I2C peripheral.
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* @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
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* @param NewState: new state of the I2Cx peripheral.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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__STATIC_INLINE void I2C_Cmd(I2C_T* I2Cx, FunctionalState NewState)
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{
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(NewState != DISABLE)?(I2Cx->IC_ENABLE |= I2C_ENABLE_ENABLE):(I2Cx->IC_ENABLE &= (uint32_t)~((uint32_t)I2C_ENABLE_ENABLE));
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}
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/**
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* @brief Enables or disables the specified I2C general call feature.
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* @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
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* @param NewState: new state of the I2C General call.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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__STATIC_INLINE void I2C_GeneralCallCmd(I2C_T* I2Cx, FunctionalState NewState)
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{
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(NewState != DISABLE)?(I2Cx->TAR = (I2Cx->TAR | I2C_TAR_SPECIAL) & (~I2C_TAR_GC_OR_START)):(I2Cx->TAR = I2Cx->TAR);
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}
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/**
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* @brief Sends a data byte through the I2Cx peripheral.
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* @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
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* @param Data: Byte to be transmitted..
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Cmd : I2C_CMD_RD/I2C_CMD_WR, I2C_CMD_RESTART, or I2C_CMD_STOP
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* @retval None
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*/
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__STATIC_INLINE void I2C_SendDataCmd(I2C_T* I2Cx, uint8_t Data, uint8_t Cmd)
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{
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I2Cx->DATACMD = ((Cmd << 8 ) | (Data & 0xFF));
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}
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/**
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* @brief Sends a data byte through the I2Cx peripheral.
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* @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
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* @param Cmd: I2C_CMD_RD/I2C_CMD_WR,I2C_CMD_RESTART, or I2C_CMD_STOP
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* @retval None
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*/
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__STATIC_INLINE void I2C_SendCmd(I2C_T* I2Cx, uint8_t Cmd)
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{
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I2Cx->DATACMD |= (Cmd << 8);
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}
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/**
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* @brief Returns the most recent received data by the I2Cx peripheral.
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* @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
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* @retval The value of the received data.
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*/
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__STATIC_INLINE uint8_t I2C_ReceiveData(I2C_T* I2Cx)
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{
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return (uint8_t)I2Cx->DATACMD;
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}
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/**
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* @brief Aborting I2C Transfers.
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* @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
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* @retval None
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*/
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__STATIC_INLINE void I2C_AbortTransfer(I2C_T* I2Cx)
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{
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I2Cx->IC_ENABLE |= I2C_ENABLE_ABORT;
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}
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/**
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* @brief Enables or disables the specified I2C DMA requests.
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* @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
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* @param NewState: new state of the I2C DMA transfer.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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__STATIC_INLINE void I2C_DMACmd(I2C_T* I2Cx, FunctionalState NewState)
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{
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(NewState != DISABLE)?(I2Cx->DMA_CR |= (I2C_DMA_CR_RDMAE | I2C_DMA_CR_TDMAE)):(I2Cx->DMA_CR &= (uint32_t)~((uint32_t)(I2C_DMA_CR_RDMAE | I2C_DMA_CR_TDMAE)));
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}
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/**
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* @brief DMA Transmit Data Level Register.
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* @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
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* @param Level: This parameter controls the level at which a DMA request is made by the transmit logic
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* @retval None
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*/
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__STATIC_INLINE void I2C_DMATransferDataLevel(I2C_T* I2Cx, uint8_t Level)
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{
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I2Cx->DMA_TDLR |= (Level & 0x07);
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}
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/**
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* @brief DMA Receive Data Level Register.
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* @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
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* @param Level: This parameter controls the level at which a DMA request is made by the receive logic.
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* @retval None
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*/
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__STATIC_INLINE void I2C_DMAReceiveDataLevel(I2C_T* I2Cx, uint8_t Level)
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{
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I2Cx->DMA_RDLR |= (Level & 0x07);
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}
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/**
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* @brief Checks whether the specified I2C interrupt has occurred or not.
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* @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
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* @param I2C_IT: specifies the interrupt source to check.
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* This parameter can be one of the following values:
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* @arg I2C_IT_RX_UNDER
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* @arg I2C_IT_RX_OVER
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* @arg I2C_IT_RX_FULL
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* @arg I2C_IT_TX_OVER
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* @arg I2C_IT_TX_EMPTY
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* @arg I2C_IT_RD_REQ
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* @arg I2C_IT_TX_ABRT
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* @arg I2C_IT_RX_DONE
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* @arg I2C_IT_ACTIVITY
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* @arg I2C_IT_STOP_DET
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* @arg I2C_IT_START_DET
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* @arg I2C_IT_GEN_CALL
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* @arg I2C_IT_MST_ON_HOLD
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* @retval The new state of I2C_IT (SET or RESET).
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*/
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__STATIC_INLINE ITStatus I2C_GetITStatus(I2C_T* I2Cx, uint16_t I2C_IT)
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{
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return ((I2Cx->INTR_STAT & (I2C_IT & IT_FLAG_MASK)) != (uint32_t)RESET)?(SET):(RESET);
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}
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/**
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* @brief Checks whether the specified I2C interrupt has occurred or not.
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* @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
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* @param I2C_IT: specifies the interrupt source to check.
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* This parameter can be one of the following values:
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* @arg I2C_IT_RX_UNDER
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* @arg I2C_IT_RX_OVER
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* @arg I2C_IT_RX_FULL
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* @arg I2C_IT_TX_OVER
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* @arg I2C_IT_TX_EMPTY
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* @arg I2C_IT_RD_REQ
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* @arg I2C_IT_TX_ABRT
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* @arg I2C_IT_RX_DONE
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* @arg I2C_IT_ACTIVITY
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* @arg I2C_IT_STOP_DET
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* @arg I2C_IT_START_DET
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* @arg I2C_IT_GEN_CALL
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* @arg I2C_IT_MST_ON_HOLD
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* @retval The new state of I2C_IT (SET or RESET).
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*/
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__STATIC_INLINE ITStatus I2C_GetRawITStatus(I2C_T* I2Cx, uint16_t I2C_IT)
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{
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return ((I2Cx->RAW_INTR_STAT & (I2C_IT & IT_FLAG_MASK)) != (uint32_t)RESET)?(SET):(RESET);
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}
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/**
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* @brief Enables or disables the specified I2C interrupts.
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* @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
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* @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled.
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* This parameter can be any combination of the following values:
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* @arg I2C_IT_RX_UNDER
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* @arg I2C_IT_RX_OVER
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* @arg I2C_IT_RX_FULL
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* @arg I2C_IT_TX_OVER
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* @arg I2C_IT_TX_EMPTY
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* @arg I2C_IT_RD_REQ
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* @arg I2C_IT_TX_ABRT
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* @arg I2C_IT_RX_DONE
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* @arg I2C_IT_ACTIVITY
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* @arg I2C_IT_STOP_DET
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* @arg I2C_IT_START_DET
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* @arg I2C_IT_GEN_CALL
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* @param NewState: new state of the specified I2C interrupts.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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__STATIC_INLINE void I2C_ITConfig(I2C_T* I2Cx, uint16_t I2C_IT, FunctionalState NewState)
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{
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(NewState != DISABLE)?(I2Cx->INTR_MASK |= I2C_IT):(I2Cx->INTR_MASK &= (uint16_t)~I2C_IT);
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}
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/**
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* @brief Enables or disables all the specified I2C interrupts.
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* @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
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* @retval None
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*/
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__STATIC_INLINE void I2C_DisableAllIT(I2C_T* I2Cx)
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{
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I2Cx->INTR_MASK = 0x0;
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}
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/**
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* @brief Clears all the I2Cx's interrupt pending bits.
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* @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
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* @retval None
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*/
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__STATIC_INLINE void I2C_ClearAllITPendingBit(I2C_T* I2Cx)
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{
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(void)(I2Cx->CLR_INTR);
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}
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/**
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* @brief get the source of tx_abort.
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* @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
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* @retval true or false
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*/
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__STATIC_INLINE bool I2C_AbortSrcCheck(I2C_T* I2Cx,uint32_t IC_MSK)
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{
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return (I2Cx->TX_ABRT_SRC & IC_MSK)?(true):(false);
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}
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|
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/**
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* @brief set slave address.
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* @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
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* @param addr: slave address.
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* @retval true or false
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*/
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__STATIC_INLINE void I2C_SetSlaveAddr(I2C_T* I2Cx,uint32_t addr)
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{
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I2Cx->SAR = (I2Cx->SAR & ~I2C_TAR_TAR) | addr;
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}
|
|
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/**
|
* @brief Initializes the I2Cx peripheral according to the specified
|
* parameters in the I2C_InitStruct.
|
*
|
* @note To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency
|
* (I2C peripheral input clock) must be a multiple of 10 MHz.
|
*
|
* @param I2Cx: where I2Cx is a i2c peripheral base address.
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* @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that contains
|
* the configuration information for the specified I2C peripheral.
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* @note This function should be called before enabling
|
the I2C Peripheral.
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* @retval false init fail
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* @retval true init succeed
|
*
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* @code:
|
* I2C_InitTypeDef I2C_InitStructure;
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*
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* I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2;
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* I2C_InitStructure.I2C_OwnAddress1 = I2C_SLAVE_OWN_ADDRESS7;
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* I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
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* I2C_InitStructure.I2C_ClockSpeed = I2C_SPEED_100K;
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* I2C_Cmd(I2Cx, DISABLE);
|
* bool ret = I2C_Init(I2Cx, &I2C_InitStructure);
|
*
|
* @endcode
|
*/
|
bool I2C_Init(I2C_T* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
|
/**
|
* @brief Configure the target address for any master transaction.
|
* @param I2Cx: where I2Cx is a i2c peripheral base address.
|
* @param Address: specifies the slave 7-bit address which will be transmitted
|
* @return None.
|
*/
|
void I2C_Set7bitAddress(I2C_T* I2Cx, uint8_t Address);
|
/**
|
* @brief Configure the target address for any master transaction.
|
* @param I2Cx: where I2Cx is a i2c peripheral base address.
|
* @param Address: specifies the slave 10-bit address which will be transmitted
|
* @return None.
|
*/
|
void I2C_Set10bitAddress(I2C_T* I2Cx, uint16_t Address);
|
|
/**
|
* @brief Checks whether the specified I2C flag is set or not.
|
* @param I2Cx: where I2Cx is a i2c peripheral base address.
|
* @param I2C_FLAG: specifies the flag to check.
|
* This parameter can be one of the following values:
|
* @arg I2C_FLAG_SLV_ACTIVITY
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* @arg I2C_FLAG_MST_ACTIVITY
|
* @arg I2C_FLAG_RFF
|
* @arg I2C_FLAG_TFE
|
* @arg I2C_FLAG_TFNF
|
* @arg I2C_FLAG_ACTIVITY
|
* @arg I2C_FLAG_MST_ACTIVITY
|
* @return The new state of I2C_FLAG (SET or RESET).
|
*/
|
FlagStatus I2C_GetFlagStatus(I2C_T* I2Cx, uint32_t I2C_FLAG);
|
/**
|
* @brief Clears the I2Cx's interrupt pending bits.
|
* @param I2Cx: where I2Cx is a i2c peripheral base address.
|
* @param I2C_IT: specifies the interrupt pending bit to clear.
|
* @arg I2C_IT_RX_UNDER
|
* @arg I2C_IT_RX_OVER
|
* @arg I2C_IT_RX_FULL
|
* @arg I2C_IT_TX_OVER
|
* @arg I2C_IT_TX_EMPTY
|
* @arg I2C_IT_RD_REQ
|
* @arg I2C_IT_TX_ABRT
|
* @arg I2C_IT_RX_DONE
|
* @arg I2C_IT_ACTIVITY
|
* @arg I2C_IT_STOP_DET
|
* @arg I2C_IT_START_DET
|
* @arg I2C_IT_GEN_CALL
|
* @arg I2C_IT_MST_ON_HOLD
|
* @return None
|
*/
|
void I2C_ClearITPendingBit(I2C_T* I2Cx, uint16_t I2C_IT);
|
|
/**
|
* @brief read data from the I2Cx peripheral.
|
* @param I2Cx: where I2Cx is a i2c peripheral base address.
|
* @param WriteBuf: cache of stored readings.
|
* @param Size: number of data read from I2C peripheral.
|
* @return none.
|
*/
|
void I2C_Write(I2C_T* I2Cx,uint8_t *WriteBuf,uint32_t Size);
|
|
/**
|
* @brief write data to the I2Cx peripheral.
|
* @param I2Cx: where I2Cx is a i2c peripheral base address.
|
* @param ReadBuf: cache of stored writings.
|
* @param Size: number of data read from I2C peripheral.
|
* @return None.
|
*/
|
void I2C_Read(I2C_T* I2Cx,uint8_t *ReadBuf,uint32_t Size);
|
|
/**@} */
|
|
#ifdef __cplusplus
|
}
|
#endif
|
|
#endif //__PAN_I2C_H__
|
|
/*** (C) COPYRIGHT 2016 Panchip Technology Corp. ***/
|
