/**************************************************************************//**
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* @file pan_hal.c
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* @version V0.0.0
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* $Revision: 1 $
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* $Date: 23/09/10 $
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* @brief Panchip HAL common source file.
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* @note
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* Copyright (C) 2023-2024 Panchip Technology Corp. All rights reserved.
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*****************************************************************************/
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#include "pan_hal.h"
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void HAL_DelayMs(uint32_t ms)
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{
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uint32_t timeout_tick = HAL_TimeConvMsToTick(ms);
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uint32_t uptime_ref = HAL_TimeGetCurrTick();
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while (HAL_TimeGetCurrTick() - uptime_ref < timeout_tick)
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{
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// Busy wait
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}
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}
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__WEAK uint32_t HAL_TimeConvMsToTick(uint32_t ms)
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{
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uint64_t timeout_tick = (uint64_t)ms * (CLK->CLK_TOP_CTRL_3V & CLK_TOPCTL_32K_CLK_SEL_Msk_3v ? 32768 : 32000) / 1000ull;
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if (timeout_tick > UINT32_MAX)
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{
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timeout_tick = HAL_TIME_FOREVER;
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}
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return (uint32_t)timeout_tick;
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}
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__WEAK uint32_t HAL_TimeGetCurrTick(void)
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{
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#if 0
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return (*(volatile uint32_t *)(0x50020014)); // current 32K counter in llctlr
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#else
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return LP_GetSlptmrCurrCount(ANA);
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#endif
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}
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#if CONFIG_IO_TIMING_TRACK
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void HAL_IoTimingTrackInit(void)
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{
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PAN_IO_TIMING_TRACK_INIT_PIN(CONFIG_TRACK_PIN_DMA_IRQ, 0);
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PAN_IO_TIMING_TRACK_INIT_PIN(CONFIG_TRACK_PIN_GPIO0_IRQ, 0);
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PAN_IO_TIMING_TRACK_INIT_PIN(CONFIG_TRACK_PIN_GPIO1_IRQ, 0);
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PAN_IO_TIMING_TRACK_INIT_PIN(CONFIG_TRACK_PIN_GPIO2_IRQ, 0);
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PAN_IO_TIMING_TRACK_INIT_PIN(CONFIG_TRACK_PIN_GPIO3_IRQ, 0);
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PAN_IO_TIMING_TRACK_INIT_PIN(CONFIG_TRACK_PIN_I2C_IRQ, 0);
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PAN_IO_TIMING_TRACK_INIT_PIN(CONFIG_TRACK_PIN_SPI0_IRQ, 0);
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PAN_IO_TIMING_TRACK_INIT_PIN(CONFIG_TRACK_PIN_SPI1_IRQ, 0);
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PAN_IO_TIMING_TRACK_INIT_PIN(CONFIG_TRACK_PIN_TMR0_IRQ, 0);
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PAN_IO_TIMING_TRACK_INIT_PIN(CONFIG_TRACK_PIN_TMR1_IRQ, 0);
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PAN_IO_TIMING_TRACK_INIT_PIN(CONFIG_TRACK_PIN_TMR2_IRQ, 0);
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PAN_IO_TIMING_TRACK_INIT_PIN(CONFIG_TRACK_PIN_UART0_IRQ, 0);
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PAN_IO_TIMING_TRACK_INIT_PIN(CONFIG_TRACK_PIN_UART1_IRQ, 0);
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PAN_IO_TIMING_TRACK_INIT_PIN(CONFIG_TRACK_PIN_WDT_IRQ, 0);
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PAN_IO_TIMING_TRACK_INIT_PIN(CONFIG_TRACK_PIN_WWDT_IRQ, 0);
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}
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#endif // CONFIG_IO_TIMING_TRACK
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void HAL_DriverInit(void)
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{
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// Init 32K timer counter
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ANA->LP_FL_CTRL_3V |= ANAC_FL_SLEEP_CNT_EN_Msk; // slptmr counter en
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#if 0
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CLK_AHBPeriphClockCmd(CLK_AHBPeriph_BLE_32M | CLK_AHBPeriph_BLE_32K, ENABLE);
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(*(volatile uint32_t *)0x5002000C) |= BIT1; // current 32K counter en in llctlr
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#endif
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}
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