/**************************************************************************//**
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* @file pan_hal_uart.c
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* @version V0.0.0
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* $Revision: 1 $
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* $Date: 23/09/10 $
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* @brief Panchip series UART (Universal Asynchronous Receiver-Transmitter) HAL source file.
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* @note
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* Copyright (C) 2023 Panchip Technology Corp. All rights reserved.
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*****************************************************************************/
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#include "pan_hal.h"
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#if (BLE_EN == 1)
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#define PAN_HAL_BLE_IRQ_SPLIT_CALLBACK 1
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#endif
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HAL_UART_HandleTypeDef UART_Handle_Array[PAN_HAL_UART_INST_COUNT] =
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{
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{
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.pUartx = UART0,
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.initObj = {0},
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.interruptObj =
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{
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.txTrigLevel = HAL_UART_TX_FIFO_HALF_FULL,
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.rxTrigLevel = HAL_UART_RX_FIFO_HALF_FULL,
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.IrqPriority = 2,
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.IRQn = UART0_IRQn,
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},
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.pTxBuffPtr = NULL,
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.txXferSize = 0,
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.txXferCount = 0,
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.pRxBuffPtr = NULL,
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.rxXferSize = 0,
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.rxXferCount = 0,
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.isTxBusy = false,
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.isRxBusy = false,
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.dmaSrc = DMAC_Peripheral_UART0_Rx,
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.dmaDst = DMAC_Peripheral_UART0_Tx,
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},
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{
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.pUartx = UART1,
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.initObj = {0},
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.interruptObj =
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{
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.txTrigLevel = HAL_UART_TX_FIFO_HALF_FULL,
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.rxTrigLevel = HAL_UART_RX_FIFO_HALF_FULL,
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.IrqPriority = 2,
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.IRQn = UART1_IRQn,
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},
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.pTxBuffPtr = NULL,
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.txXferSize = 0,
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.txXferCount = 0,
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.pRxBuffPtr = NULL,
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.rxXferSize = 0,
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.rxXferCount = 0,
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.isTxBusy = false,
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.isRxBusy = false,
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.dmaSrc = DMAC_Peripheral_UART1_Rx,
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.dmaDst = DMAC_Peripheral_UART1_Tx,
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}
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};
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HAL_Status HAL_UART_Init(HAL_UART_HandleTypeDef *pUart)
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{
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if (pUart == NULL)
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{
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return HAL_ERROR;
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}
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uint32_t tmpreg = 0x00;
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uint32_t integerdivider = 0x00;
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uint32_t fractionaldivider = 0x00;
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uint64_t apbclock = 0x00;
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if(pUart->pUartx == UART0)
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{
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CLK_APB1PeriphClockCmd(CLK_APB1Periph_UART0, ENABLE);
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}
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else if(pUart->pUartx == UART1)
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{
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CLK_APB2PeriphClockCmd(CLK_APB2Periph_UART1, ENABLE);
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}
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/*---------------------------- UART BRR Configuration -----------------------*/
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/* Configure the UART Baud Rate */
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apbclock = CLK_GetPeripheralFreq((void *)pUart->pUartx);
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/* Unlock to enable write & read divisor register */
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pUart->pUartx->LCR |= UART_LCR_DLAB_Msk;
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/* Determine the integer part baud_rate_divisor = PCLK*100 / (16*required_baud_rate) */
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integerdivider = ((25 * apbclock) / (4 * (pUart->initObj.baudRate)));
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// Too high baudrate (too small divider) would cause DLL/DLH be all 0 which means UART disabled,
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// thus return false if this happens.
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if (integerdivider < 100)
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return HAL_ERROR;
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tmpreg = (integerdivider / 100);
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pUart->pUartx->RBR_THR_DLL = tmpreg & 0xFF;
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pUart->pUartx->IER_DLH = (tmpreg & 0xFF00) >> 8;
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/* Determine the fractional part */
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fractionaldivider = integerdivider - (100 * tmpreg);
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/* Implement the fractional part in the register */
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pUart->pUartx->DLF = ((((fractionaldivider * 16) + 50) / 100));
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pUart->pUartx->LCR &= ~UART_LCR_DLAB_Msk;
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/*---------------------------- UART Line Configuration -----------------------*/
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tmpreg = pUart->pUartx->LCR;
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tmpreg &= ~(UART_LCR_SP_Msk | UART_LCR_EPS_Msk | UART_LCR_PEN_Msk | UART_LCR_STOP_Msk | UART_LCR_DLS_Msk);
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tmpreg |= (pUart->initObj.format);
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pUart->pUartx->LCR = tmpreg;
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/*-------------------------------enable fifo----------------------------------*/
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UART_EnableFifo(pUart->pUartx);
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return HAL_OK;
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}
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HAL_Status HAL_UART_SendData(HAL_UART_HandleTypeDef *pUart, uint8_t *pBuf, uint16_t size, uint32_t timeout)
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{
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if (pUart->isTxBusy)
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{
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return HAL_BUSY;
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}
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if ((pUart == NULL) || (pBuf == NULL) || (size == 0U))
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{
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return HAL_ERROR;
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}
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uint32_t timeout_tick = HAL_TimeConvMsToTick(timeout);
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uint32_t uptime_ref = HAL_TimeGetCurrTick();
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pUart->isTxBusy = true;
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pUart->pTxBuffPtr = pBuf;
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pUart->txXferSize = size;
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pUart->txXferCount = 0;
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while (pUart->txXferCount < pUart->txXferSize)
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{
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// Wait until Transmitter Shift Register and Tx FIFO are both empty
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while (!(UART_GetLineStatus(pUart->pUartx) & UART_LSR_TEMT_Msk))
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{
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if (timeout_tick != HAL_TIME_FOREVER)
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{
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if (HAL_TimeGetCurrTick() - uptime_ref >= timeout_tick)
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{
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pUart->isTxBusy = false;
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return HAL_TIMEOUT;
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}
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}
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}
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// Put a byte to Tx FIFO
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UART_SendData(pUart->pUartx, pUart->pTxBuffPtr[pUart->txXferCount++]);
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}
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pUart->isTxBusy = false;
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return HAL_OK;
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}
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HAL_Status HAL_UART_ReceiveData(HAL_UART_HandleTypeDef *pUart, uint8_t *pBuf, uint16_t size, uint32_t timeout)
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{
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if (pUart->isRxBusy)
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{
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return HAL_BUSY;
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}
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if ((pUart == NULL) || (pBuf == NULL) || (size == 0U))
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{
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return HAL_ERROR;
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}
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uint32_t timeout_tick = HAL_TimeConvMsToTick(timeout);
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uint32_t uptime_ref = HAL_TimeGetCurrTick();
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pUart->isRxBusy = true;
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pUart->pRxBuffPtr = pBuf;
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pUart->rxXferSize = size;
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pUart->rxXferCount = 0;
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while (pUart->rxXferCount < pUart->rxXferSize)
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{
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// Check if there is at least one byte in Rx Data Register or Rx FIFO
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if (UART_GetLineStatus(pUart->pUartx) & UART_LSR_DR_Msk)
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{
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// Get a byte from Rx FIFO
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pUart->pRxBuffPtr[pUart->rxXferCount++] = UART_ReceiveData(pUart->pUartx);
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}
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if (timeout_tick != HAL_TIME_FOREVER)
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{
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if (HAL_TimeGetCurrTick() - uptime_ref >= timeout_tick)
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{
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pUart->isRxBusy = false;
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return HAL_TIMEOUT;
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}
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}
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}
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pUart->isRxBusy = false;
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return HAL_OK;
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}
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#if PAN_HAL_BLE_IRQ_SPLIT_CALLBACK
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#include "pan_ble_stack.h"
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void ble_irq_split_callback(void)
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{
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HAL_UART_HandleTypeDef *pUart;
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for (size_t i = 0; i < PAN_HAL_UART_INST_COUNT; i++)
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{
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pUart = &UART_Handle_Array[i];
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if (pUart->isRxBusy)
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{
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__disable_irq(); // To avoid swiching to the possible higher priority UART ISR
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if (pUart->interruptObj.continuousRxMode)
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{
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while (UART_GetRxFifoLevel(pUart->pUartx) > 1)
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{
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if (pUart->rxXferCount < pUart->rxXferSize)
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{
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pUart->pRxBuffPtr[pUart->rxXferCount++] = UART_ReceiveData(pUart->pUartx);
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}
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else
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{
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// Set UART pending irq manually to trigger uart rx continuous buff full error callback
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NVIC_SetPendingIRQ(pUart->interruptObj.IRQn);
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break;
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}
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}
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}
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else
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{
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while (!UART_IsRxFifoEmpty(pUart->pUartx))
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{
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if (pUart->rxXferCount < pUart->rxXferSize)
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{
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pUart->pRxBuffPtr[pUart->rxXferCount++] = UART_ReceiveData(pUart->pUartx);
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}
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else
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{
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break;
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}
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}
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if (pUart->rxXferCount == pUart->rxXferSize)
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{
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// Set UART pending irq manually to trigger uart rx finish callback
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NVIC_SetPendingIRQ(pUart->interruptObj.IRQn);
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}
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}
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__enable_irq();
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}
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}
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}
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#endif // PAN_HAL_BLE_IRQ_SPLIT_CALLBACK
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HAL_Status HAL_UART_Init_INT(HAL_UART_HandleTypeDef *pUart)
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{
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if (pUart == NULL)
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{
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return HAL_ERROR;
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}
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#if PAN_HAL_BLE_IRQ_SPLIT_CALLBACK
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pan_misc_register_app_irq_handler_cb(ble_irq_split_callback);
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#endif // PAN_HAL_BLE_IRQ_SPLIT_CALLBACK
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// Flush UART FIFOs
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UART_ResetTxFifo(pUart->pUartx);
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UART_ResetRxFifo(pUart->pUartx);
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// Set UART IRQ trigger level
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UART_SetTxTrigger(pUart->pUartx, (UART_TxTriggerDef)pUart->interruptObj.txTrigLevel);
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UART_SetRxTrigger(pUart->pUartx, (UART_RxTriggerDef)pUart->interruptObj.rxTrigLevel);
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// Enable THRE Interrupt Mode
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UART_EnablePtime(pUart->pUartx);
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// Set UART IRQ Priority and enable UART IRQ
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NVIC_SetPriority(pUart->interruptObj.IRQn, pUart->interruptObj.IrqPriority);
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NVIC_EnableIRQ(pUart->interruptObj.IRQn);
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return HAL_OK;
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}
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HAL_Status HAL_UART_SendData_INT(HAL_UART_HandleTypeDef *pUart, uint8_t *pBuf, uint16_t size)
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{
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if (pUart->isTxBusy)
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{
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return HAL_BUSY;
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}
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if ((pUart == NULL) || (pBuf == NULL) || (size == 0U))
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{
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return HAL_ERROR;
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}
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pUart->isTxBusy = true;
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pUart->pTxBuffPtr = pBuf;
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pUart->txXferSize = size;
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pUart->txXferCount = 0;
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// Enable Transmit Trigger interupt to start sending
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UART_EnableIrq(pUart->pUartx, UART_IRQ_THR_EMPTY);
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return HAL_OK;
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}
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HAL_Status HAL_UART_ReceiveData_INT(HAL_UART_HandleTypeDef *pUart, uint8_t *pBuf, uint16_t size)
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{
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if (pUart->isRxBusy)
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{
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return HAL_BUSY;
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}
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if ((pUart == NULL) || (pBuf == NULL) || (size == 0U))
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{
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return HAL_ERROR;
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}
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pUart->isRxBusy = true;
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pUart->pRxBuffPtr = pBuf;
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pUart->rxXferSize = size;
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pUart->rxXferCount = 0;
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// Enable Data Available and Rx Line Status interrupt to start receiving
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UART_EnableIrq(pUart->pUartx, UART_IRQ_RECV_DATA_AVL);
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UART_EnableIrq(pUart->pUartx, UART_IRQ_LINE_STATUS);
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return HAL_OK;
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}
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HAL_Status HAL_UART_ReceiveDataContinuously_INT(HAL_UART_HandleTypeDef *pUart, uint8_t *pBuf, uint16_t bufSize)
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{
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if (pUart->isRxBusy)
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{
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return HAL_BUSY;
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}
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if ((pUart == NULL) || (pBuf == NULL) || (bufSize == 0U))
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{
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return HAL_ERROR;
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}
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// The continuous Rx mode does not support Rx FIFO trigger level set to 1 char
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if ((UART_RxTriggerDef)pUart->interruptObj.rxTrigLevel == UART_RX_FIFO_ONE_CHAR)
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{
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return HAL_ERROR;
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}
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pUart->interruptObj.continuousRxMode = true;
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pUart->isRxBusy = true;
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pUart->pRxBuffPtr = pBuf;
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pUart->rxXferSize = bufSize;
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pUart->rxXferCount = 0;
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// Enable Data Available and Rx Line Status interrupt to start receiving
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UART_EnableIrq(pUart->pUartx, UART_IRQ_RECV_DATA_AVL);
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UART_EnableIrq(pUart->pUartx, UART_IRQ_LINE_STATUS);
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return HAL_OK;
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}
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HAL_Status HAL_UART_SendDataAbort_INT(HAL_UART_HandleTypeDef *pUart)
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{
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if (pUart == NULL)
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{
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return HAL_ERROR;
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}
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// Disable Transmit Trigger interupt to abort sending
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UART_DisableIrq(pUart->pUartx, UART_IRQ_THR_EMPTY);
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// Flush Tx FIFO
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UART_ResetTxFifo(pUart->pUartx);
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pUart->isTxBusy = false;
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return HAL_OK;
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}
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HAL_Status HAL_UART_ReceiveDataAbort_INT(HAL_UART_HandleTypeDef *pUart)
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{
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if (pUart == NULL)
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{
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return HAL_ERROR;
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}
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// Disable Data Available and Rx Line Status interrupt to abort receiving
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UART_DisableIrq(pUart->pUartx, UART_IRQ_RECV_DATA_AVL);
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UART_DisableIrq(pUart->pUartx, UART_IRQ_LINE_STATUS);
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// Flush Rx FIFO
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UART_ResetRxFifo(pUart->pUartx);
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pUart->isRxBusy = false;
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pUart->interruptObj.continuousRxMode = false;
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return HAL_OK;
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}
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HAL_Status HAL_UART_Init_DMA(HAL_UART_HandleTypeDef *pUart, HAL_UART_DmaDirOpt dmaDir, UART_CallbackFunc callback)
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{
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uint32_t dmaCh;
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if ((pUart == NULL) || (callback == NULL))
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{
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return HAL_ERROR;
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}
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if (dmaDir == HAL_UART_DMA_TX)
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{
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// Configure UART Tx FIFO
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UART_ResetTxFifo(pUart->pUartx);
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UART_SetTxTrigger(pUart->pUartx, UART_TX_FIFO_HALF_FULL);
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UART_EnablePtime(pUart->pUartx); //Enable Programmable THRE Interrupt Mode
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/* Get free DMA channel */
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dmaCh = DMAC_AcquireChannel(DMA);
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if (dmaCh == DMA_INVLID_CHANNEL)
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{
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return HAL_ERROR;
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}
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pUart->txDmaCh = dmaCh;
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DMAC_Channel_Array[dmaCh].ConfigTmp = dma_mem2uart_config;
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DMAC_Channel_Array[dmaCh].ConfigTmp.PeripheralDst = pUart->dmaDst;
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}
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else if (dmaDir == HAL_UART_DMA_RX)
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{
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// Configure UART Rx FIFO
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UART_ResetRxFifo(pUart->pUartx);
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UART_SetRxTrigger(pUart->pUartx, UART_RX_FIFO_HALF_FULL);
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/* Get free DMA channel */
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dmaCh = DMAC_AcquireChannel(DMA);
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if (dmaCh == DMA_INVLID_CHANNEL)
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{
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return HAL_ERROR;
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}
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pUart->rxDmaCh = dmaCh;
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DMAC_Channel_Array[dmaCh].ConfigTmp = dma_uart2mem_config;
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DMAC_Channel_Array[dmaCh].ConfigTmp.PeripheralSrc = pUart->dmaSrc;
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}
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/* Enable DMA transfer interrupt */
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DMAC_ClrIntFlagMsk(DMA, dmaCh, DMAC_FLAG_INDEX_TFR);
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// DMAC_ClrIntFlagMsk(DMA, dmaCh, DMAC_FLAG_INDEX_ERR);
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DMAC_Channel_Array[dmaCh].periph = pUart;
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DMAC_Channel_Array[dmaCh].CallbackUart = callback;
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DMAC_Channel_Array[dmaCh].PeriMode = DMAC_Peri_UART;
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DMAC_SetChannelConfig(DMA, dmaCh, &DMAC_Channel_Array[dmaCh].ConfigTmp);
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return HAL_OK;
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}
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HAL_Status HAL_UART_SendData_DMA(HAL_UART_HandleTypeDef *pUart, uint8_t *pBuf, uint16_t size)
|
{
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if (pUart->isTxBusy)
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{
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return HAL_BUSY;
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}
|
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if ((pUart == NULL) || (pBuf == NULL) || (size == 0U))
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{
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return HAL_ERROR;
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}
|
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pUart->isTxBusy = true;
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DMAC_Channel_Array[pUart->txDmaCh].pBuffPtr = (uint32_t*)pBuf;
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DMAC_Channel_Array[pUart->txDmaCh].XferSize = size;
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DMAC_Channel_Array[pUart->txDmaCh].XferCount = 0;
|
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if (size < 1024)
|
{
|
DMAC_StartChannel(DMA, pUart->txDmaCh, pBuf, (void *)&(pUart->pUartx->RBR_THR_DLL), size);
|
}
|
else
|
{
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DMAC_StartChannel(DMA, pUart->txDmaCh, pBuf, (void *)&(pUart->pUartx->RBR_THR_DLL), 1023);
|
}
|
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return HAL_OK;
|
}
|
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HAL_Status HAL_UART_ReceiveData_DMA(HAL_UART_HandleTypeDef *pUart, uint8_t *pBuf, uint16_t size)
|
{
|
if (pUart->isRxBusy)
|
{
|
return HAL_BUSY;
|
}
|
|
if ((pUart == NULL) || (pBuf == NULL) || (size == 0U))
|
{
|
return HAL_ERROR;
|
}
|
|
pUart->isRxBusy = true;
|
DMAC_Channel_Array[pUart->rxDmaCh].pBuffPtr = (uint32_t*)pBuf;
|
DMAC_Channel_Array[pUart->rxDmaCh].XferSize = size;
|
DMAC_Channel_Array[pUart->rxDmaCh].XferCount = 0;
|
|
if (size < 1024)
|
{
|
DMAC_StartChannel(DMA, pUart->rxDmaCh, (void*)&(pUart->pUartx->RBR_THR_DLL), pBuf, size);
|
}
|
else
|
{
|
DMAC_StartChannel(DMA, pUart->rxDmaCh, (void*)&(pUart->pUartx->RBR_THR_DLL), pBuf, 1023);
|
}
|
|
return HAL_OK;
|
}
|
|
HAL_Status HAL_UART_SendDataAbort_DMA(HAL_UART_HandleTypeDef *pUart)
|
{
|
if (pUart == NULL)
|
{
|
return HAL_ERROR;
|
}
|
|
// Stop current DMA channel
|
DMAC_StopChannel(DMA, pUart->txDmaCh);
|
|
// Flush Tx FIFO
|
UART_ResetTxFifo(pUart->pUartx);
|
|
pUart->isTxBusy = false;
|
|
return HAL_OK;
|
}
|
|
HAL_Status HAL_UART_ReceiveDataAbort_DMA(HAL_UART_HandleTypeDef *pUart)
|
{
|
if (pUart == NULL)
|
{
|
return HAL_ERROR;
|
}
|
|
// Stop current DMA channel
|
DMAC_StopChannel(DMA, pUart->rxDmaCh);
|
|
// Flush Rx FIFO
|
UART_ResetRxFifo(pUart->pUartx);
|
|
pUart->isRxBusy = false;
|
|
return HAL_OK;
|
}
|
|
static void UART_HandleLineStatus(HAL_UART_HandleTypeDef *pUart)
|
{
|
uint32_t lineStatus = UART_GetLineStatus(pUart->pUartx);
|
|
if (pUart->isRxBusy)
|
{
|
// Report Rx error event
|
if (pUart->interruptObj.callbackFunc != NULL)
|
{
|
if (lineStatus & UART_LINE_PARITY_ERR)
|
{
|
pUart->interruptObj.callbackFunc(pUart, HAL_UART_EVT_RX_ERR_PARITY, pUart->pRxBuffPtr, pUart->rxXferCount);
|
}
|
if (lineStatus & UART_LINE_FRAME_ERR)
|
{
|
pUart->interruptObj.callbackFunc(pUart, HAL_UART_EVT_RX_ERR_FRAME, pUart->pRxBuffPtr, pUart->rxXferCount);
|
}
|
if (lineStatus & UART_LINE_OVERRUN_ERR)
|
{
|
pUart->interruptObj.callbackFunc(pUart, HAL_UART_EVT_RX_ERR_OVERRUN, pUart->pRxBuffPtr, pUart->rxXferCount);
|
}
|
}
|
}
|
}
|
|
static void UART_HandleReceivedData(HAL_UART_HandleTypeDef *pUart, UART_EventDef flag)
|
{
|
if (pUart->isRxBusy)
|
{
|
if (pUart->interruptObj.continuousRxMode)
|
{
|
if (flag != UART_EVENT_TIMEOUT)
|
{
|
#if PAN_HAL_BLE_IRQ_SPLIT_CALLBACK
|
__disable_irq(); // To avoid swiching to higher priority LL IRQ
|
#endif
|
// Read data from UART Rx FIFO and remains 1 byte in it
|
while (UART_GetRxFifoLevel(pUart->pUartx) > 1)
|
{
|
if (pUart->rxXferCount < pUart->rxXferSize)
|
{
|
pUart->pRxBuffPtr[pUart->rxXferCount++] = UART_ReceiveData(pUart->pUartx);
|
}
|
else
|
{
|
break;
|
}
|
}
|
#if PAN_HAL_BLE_IRQ_SPLIT_CALLBACK
|
__enable_irq();
|
#endif
|
}
|
else
|
{
|
#if PAN_HAL_BLE_IRQ_SPLIT_CALLBACK
|
__disable_irq(); // To avoid swiching to higher priority LL IRQ
|
#endif
|
// Read all data from UART Rx FIFO due to timeout occurred
|
while (!UART_IsRxFifoEmpty(pUart->pUartx))
|
{
|
if (pUart->rxXferCount < pUart->rxXferSize)
|
{
|
pUart->pRxBuffPtr[pUart->rxXferCount++] = UART_ReceiveData(pUart->pUartx);
|
}
|
else
|
{
|
break;
|
}
|
}
|
#if PAN_HAL_BLE_IRQ_SPLIT_CALLBACK
|
__enable_irq();
|
#endif
|
// End current rx flow and trigger Continuous Rx Timeout callback if Rx FIFO is already empty
|
if (UART_IsRxFifoEmpty(pUart->pUartx))
|
{
|
// Disable Data Available and Rx Line Status interrupt to abort receiving
|
UART_DisableIrq(pUart->pUartx, UART_IRQ_RECV_DATA_AVL);
|
UART_DisableIrq(pUart->pUartx, UART_IRQ_LINE_STATUS);
|
#if PAN_HAL_BLE_IRQ_SPLIT_CALLBACK
|
__disable_irq(); // To avoid swiching to higher priority LL IRQ
|
#endif
|
pUart->isRxBusy = false;
|
pUart->interruptObj.continuousRxMode = false;
|
#if PAN_HAL_BLE_IRQ_SPLIT_CALLBACK
|
__enable_irq();
|
#endif
|
// Trigger Continuous Rx Timeout callback
|
if (pUart->interruptObj.callbackFunc != NULL)
|
{
|
pUart->interruptObj.callbackFunc(pUart, HAL_UART_EVT_CONTI_RX_TIMEOUT, pUart->pRxBuffPtr, pUart->rxXferCount);
|
}
|
}
|
}
|
if (pUart->rxXferCount >= pUart->rxXferSize)
|
{
|
// Trigger Rx Buffer Full callback
|
if (pUart->interruptObj.callbackFunc != NULL)
|
{
|
pUart->interruptObj.callbackFunc(pUart, HAL_UART_EVT_CONTI_RX_BUFF_FULL, pUart->pRxBuffPtr, pUart->rxXferCount);
|
}
|
}
|
}
|
else // Normal Rx Mode (Not Continuous Rx Mode)
|
{
|
#if PAN_HAL_BLE_IRQ_SPLIT_CALLBACK
|
__disable_irq(); // To avoid swiching to higher priority LL IRQ
|
#endif
|
while (!UART_IsRxFifoEmpty(pUart->pUartx))
|
{
|
if (pUart->rxXferCount < pUart->rxXferSize)
|
{
|
pUart->pRxBuffPtr[pUart->rxXferCount++] = UART_ReceiveData(pUart->pUartx);
|
}
|
else
|
{
|
break;
|
}
|
}
|
#if PAN_HAL_BLE_IRQ_SPLIT_CALLBACK
|
__enable_irq();
|
#endif
|
if (pUart->rxXferCount == pUart->rxXferSize)
|
{
|
// Disable Data Available and Rx Line Status interrupt to abort receiving
|
UART_DisableIrq(pUart->pUartx, UART_IRQ_RECV_DATA_AVL);
|
UART_DisableIrq(pUart->pUartx, UART_IRQ_LINE_STATUS);
|
#if PAN_HAL_BLE_IRQ_SPLIT_CALLBACK
|
__disable_irq(); // To avoid swiching to higher priority LL IRQ
|
#endif
|
pUart->isRxBusy = false;
|
#if PAN_HAL_BLE_IRQ_SPLIT_CALLBACK
|
__enable_irq();
|
#endif
|
// Report Rx finish event
|
if (pUart->interruptObj.callbackFunc != NULL)
|
{
|
pUart->interruptObj.callbackFunc(pUart, HAL_UART_EVT_RX_FINISH, pUart->pRxBuffPtr, pUart->rxXferCount);
|
}
|
}
|
}
|
}
|
}
|
|
static void UART_HandleTransmittingData(HAL_UART_HandleTypeDef *pUart)
|
{
|
if (pUart->isTxBusy)
|
{
|
while (!UART_IsTxFifoFull(pUart->pUartx))
|
{
|
if (pUart->txXferCount < pUart->txXferSize)
|
{
|
UART_SendData(pUart->pUartx, pUart->pTxBuffPtr[pUart->txXferCount++]);
|
}
|
else
|
{
|
break;
|
}
|
}
|
|
if (pUart->txXferCount == pUart->txXferSize)
|
{
|
// Disable Transmit Trigger interupt after transmitting done
|
UART_DisableIrq(pUart->pUartx, UART_IRQ_THR_EMPTY);
|
pUart->isTxBusy = false;
|
// Report Tx finish event
|
if (pUart->interruptObj.callbackFunc != NULL)
|
{
|
pUart->interruptObj.callbackFunc(pUart, HAL_UART_EVT_TX_FINISH, pUart->pTxBuffPtr, pUart->txXferCount);
|
}
|
}
|
}
|
}
|
|
static void UART_HandleProc(HAL_UART_HandleTypeDef *pUart)
|
{
|
UART_EventDef event = UART_GetActiveEvent(pUart->pUartx);
|
|
switch (event)
|
{
|
case UART_EVENT_LINE:
|
UART_HandleLineStatus(pUart);
|
break;
|
case UART_EVENT_DATA:
|
UART_HandleReceivedData(pUart, UART_EVENT_DATA);
|
break;
|
case UART_EVENT_TIMEOUT:
|
UART_HandleReceivedData(pUart, UART_EVENT_TIMEOUT);
|
break;
|
case UART_EVENT_THR_EMPTY:
|
UART_HandleTransmittingData(pUart);
|
break;
|
case UART_EVENT_NONE:
|
#if PAN_HAL_BLE_IRQ_SPLIT_CALLBACK
|
UART_HandleReceivedData(pUart, UART_EVENT_NONE);
|
#endif // PAN_HAL_BLE_IRQ_SPLIT_CALLBACK
|
break;
|
default:
|
break;
|
}
|
}
|
|
__WEAK void UART0_IRQHandlerOverlay(void)
|
{
|
UART_HandleProc(&UART_Handle_Array[0]);
|
}
|
|
__WEAK void UART1_IRQHandlerOverlay(void)
|
{
|
UART_HandleProc(&UART_Handle_Array[1]);
|
}
|
|
void UART0_IRQHandler(void)
|
{
|
PAN_IO_TIMING_TRACK_LEVEL(CONFIG_TRACK_PIN_UART0_IRQ, 1);
|
|
UART0_IRQHandlerOverlay();
|
|
PAN_IO_TIMING_TRACK_LEVEL(CONFIG_TRACK_PIN_UART0_IRQ, 0);
|
}
|
|
void UART1_IRQHandler(void)
|
{
|
PAN_IO_TIMING_TRACK_LEVEL(CONFIG_TRACK_PIN_UART1_IRQ, 1);
|
|
UART1_IRQHandlerOverlay();
|
|
PAN_IO_TIMING_TRACK_LEVEL(CONFIG_TRACK_PIN_UART1_IRQ, 0);
|
}
|
