/*
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* Copyright (c) 2021 Shanghai Panchip Microelectronics Co.,Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef COMM_PRF_H
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#define COMM_PRF_H
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#include "pan_pri_rf.h"
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#include "pan_phy.h"
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#ifndef __ramfunc
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#define __ramfunc __attribute__((section(".ramfunc")))
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#endif
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#define PRF_LL_IRQ_PRIORITY 0
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#define PRF_DATA_MAX_SIZE 255
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#define TX_WINDOW (5)
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#define RX_WINDOW (1)
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#define RX_LEGENCY_1M (11)
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#define RX_LEGENCY_2M (5)
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typedef enum {
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PRF_CHIP_MODE_SEL_BLE = 1,
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PRF_CHIP_MODE_SEL_XN297 = 2,
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PRF_CHIP_MODE_SEL_NRF = 3,
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}prf_chip_mode_sel_t;
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typedef enum PRF_ADDR_LENGTH_SEL {
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PRF_ADDR_LENGTH_SEL_3 = 3,
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PRF_ADDR_LENGTH_SEL_4 = 4,
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PRF_ADDR_LENGTH_SEL_5 = 5,
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}prf_addr_length_sel_t;
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typedef enum PRF_CRC_SEL {
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PRF_CRC_SEL_NOCRC = 0,
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PRF_CRC_SEL_CRC8 = 1,
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PRF_CRC_SEL_CRC16 = 2,
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PRF_CRC_SEL_CRC24 = 3,
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}prf_crc_sel_t;
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typedef enum PRF_SCRAMBLE_SEL {
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PRF_SRC_SEL_NOSRC = 0,
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PRF_SRC_SEL_EN = 1,
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}prf_scramble_sel_t;
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typedef enum PRF_MODE {
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PRF_MODE_NORMAL = 0,
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PRF_MODE_ENHANCE = 1,
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PRF_MODE_NORMAL_M1 = 2,
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}prf_mode_t;
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typedef enum PRF_PHY {
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PRF_PHY_1M = 1,
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PRF_PHY_2M = 2,
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PRF_PHY_CODED_S8 = 3,
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PRF_PHY_CODED = 4,
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PRF_PHY_250K = 5,
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}prf_phy_t;
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typedef enum PRF_TRX_MODE {
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PRF_TX_MODE = 0,
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PRF_RX_MODE = 1,
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}prf_trx_mode_t;
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typedef enum PRF_MODE_CONF_SEL {
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PRF_BLE_CONF = 1,
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PRF_NRF_CONF = 2,
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PRF_G_250k_CONF = 3,
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PRF_B_250K_CONF = 4,
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}prf_mode_conf_sel_t;
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typedef enum PRF_PIPE {
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PRF_PIPE0 = (0x1<<0),
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PRF_PIPE1 = (0x1<<1),
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PRF_PIPE2 = (0x1<<2),
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PRF_PIPE3 = (0x1<<3),
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PRF_PIPE4 = (0x1<<4),
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PRF_PIPE5 = (0x1<<5),
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PRF_PIPE6 = (0x1<<6),
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PRF_PIPE7 = (0x1<<7),
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}prf_pipe_t;
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typedef enum PRF_TRANSFER_TYPE {
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PRF_TRF_NORMAL = (0),
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PRF_TRF_NRF52 = (1),
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PRF_TRF_B250K = (2),
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}prf_trf_t;
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typedef enum PRF_ENDIAN {
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PRF_BIG_ENDIAN = 0,
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PRF_LITTLE_ENDIAN = 1,
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}prf_endian_t;
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typedef enum PRF_ENC_DEC_MODE {
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PRF_ENCRYPT_MODE = 0,
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PRF_DECRYPT_MODE = 1,
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}prf_enc_dec_mode_t;
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typedef enum PRF_SPEED_SEL {
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PRF_TRANSFER_SPEED_LOW = 0,
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PRF_TRANSFER_SPEED_4K = 1,
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PRF_TRANSFER_SPEED_8K = 2,
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} prf_speed_sel_t;
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typedef struct {
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uint32_t data_length;
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uint8_t data[PRF_DATA_MAX_SIZE];
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}panchip_prf_payload_t;
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typedef struct
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{
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prf_mode_t work_mode;
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prf_chip_mode_sel_t chip_mode;
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prf_trx_mode_t trx_mode;
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prf_phy_t phy;
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prf_crc_sel_t crc;
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prf_scramble_sel_t src;
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prf_mode_conf_sel_t mode_conf;
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uint16_t rx_timeout;
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uint16_t rf_channel;
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uint8_t tx_no_ack;
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prf_trf_t trf_type;
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uint8_t rx_length;
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uint8_t sync_length;
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uint8_t sync[5];
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int8_t tx_power;
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uint8_t pid_manual_flag;
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uint8_t crc_include_sync;
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uint8_t src_include_sync;
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prf_pipe_t pipe;
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} pan_prf_config_t;
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typedef void (*RRF_CallbackFunc)(void);
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typedef struct
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{
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RRF_CallbackFunc tx_cb;
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RRF_CallbackFunc rx_timeout_cb;
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RRF_CallbackFunc rx_cb;
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RRF_CallbackFunc rx_crc_err_cb;
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RRF_CallbackFunc rx_len_err_cb;
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RRF_CallbackFunc rx_acc_adr_err_cb;
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RRF_CallbackFunc rx_pid_err_cb;
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} pan_prf_callback_t;
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typedef struct {
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uint32_t major;
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uint32_t minor;
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uint32_t patch;
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uint32_t commit_id;
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} pan_prf_version_t;
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#define SLPTMR1_SLPTMR_CMPR_BUS_ENA (3 << 2)
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#define SLPTMR1_SLPTMR_CMPR_BUS_ENA_MSK 0x40 /* 1'b0: disable - 1'b1: Enable */
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#define SLPTMR1_SLPTMR_CMPR_BUS_ENA_SHFT 6
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#define SLPTMR2_SLPTMR_CMPR_STRT_EVENT_DIN (4<<2)
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#define SLPTMR4_SLPTMR_CMPR_BUS_DIN (6<<2)
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#define CTRL_PM_PWR_STATE (2<<2)
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#define CTRL_PM_PWR_STATE_MSK 0x3f0
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#define CTRL_PM_PWR_STATE_SHFT 4
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#define CTRL_PWR_MOD (2<<2)
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#define CTRL_PWR_MOD_MSK 0x7
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#define CTRL_PWR_MOD_SHFT 0
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#define CTRL_MEM_SOFT_RST_N (2<<2)
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#define CTRL_MEM_SOFT_RST_N_MSK 0x8
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#define CTRL_MEM_SOFT_RST_N_SHFT 3
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#define SLPTMR1_SLPTMR_REST_N (3<<2)
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#define SLPTMR1_SLPTMR_REST_N_MSK 0x4 /* active low sleep timer reset signal */
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#define SLPTMR1_SLPTMR_REST_N_SHFT 2
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#define SLPTMR1_SLPTMR_ENA (3<<2)
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#define SLPTMR1_SLPTMR_ENA_MSK 0x2 /* This field specifies the enable for sleep timer */
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#define SLPTMR1_SLPTMR_ENA_SHFT 1
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#define DSLP1_LL_PHY_DRIVER_NRST (7<<2)
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#define DSLP1_LL_PHY_DRIVER_NRST_MSK 0x2
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#define DSLP1_LL_PHY_DRIVER_NRST_SHFT 1
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#define SLPTMR1_SLPTMR_CMPR_STRT_EVENT_ENA (3<<2)
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#define SLPTMR1_SLPTMR_CMPR_STRT_EVENT_ENA_MSK 0x1 /* This field specifies the control compare units status function. - 1'b0: disable - 1'b1: Enable */
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#define SLPTMR1_SLPTMR_CMPR_STRT_EVENT_ENA_SHFT 0
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#define SLPTMR2_SLPTMR_CMPR_STRT_EVENT_DIN (4<<2)
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#define SLPTMR2_SLPTMR_CMPR_STRT_EVENT_DIN_MSK 0xffffffff /* This field specifies the compare unit inputs (compare values). */
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#define SLPTMR2_SLPTMR_CMPR_STRT_EVENT_DIN_SHFT 0
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#define SLPTMR3_SLPTMR_CURRENT (5<<2)
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#define SLPTMR3_SLPTMR_CURRENT_MSK 0xffffffff /* This field specifies the sleep timer current value. */
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#define SLPTMR3_SLPTMR_CURRENT_SHFT 0
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#define LLHWC_WRITE_MASK32_REG(base_addr, reg_ofst, mask, shift, data) \
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LLHWC_WRITE32_REG(base_addr, reg_ofst, \
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((LLHWC_READ32_REG((base_addr), (reg_ofst)) & ~(mask)) | \
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((mask) & ((data) << (shift)))))
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#define LLHWC_READ_MASK32_REG(base_addr, reg_ofst, mask, shift) \
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((LLHWC_READ32_REG((base_addr), (reg_ofst)) & (mask)) >> (shift))
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#define LLHWC_READ_MASK32_REG_EXT(base_addr, reg) LLHWC_READ_MASK32_REG(base_addr, reg, reg##_MSK, reg##_SHFT)
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extern uint8_t panchip_prf_data_rec(panchip_prf_payload_t *p_payload);
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extern void panchip_prf_set_data(panchip_prf_payload_t *p_payload);
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extern void panchip_prf_set_ack_data(panchip_prf_payload_t *p_payload);
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extern void panchip_prf_init(pan_prf_config_t *p_config);
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extern void panchip_prf_trx_start(void);
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extern void panchip_prf_module_init(void);
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extern void panchip_prf_ble_resume(void);
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extern void panchip_switch_prf(pan_prf_config_t *p_config);
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extern void panchip_prf_set_chn(uint16_t rf_channel);
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extern void panchip_prf_trx_trans_time(pan_prf_config_t *p_config);
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extern uint8_t panchip_prf_isr_resume_ble_cb(void);
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extern void panchip_prf_dual_mode_start(pan_prf_config_t *prf_config);
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extern uint8_t panchip_prf_ble_handler(void);
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extern void panchip_prf_isr_proc(void);
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extern void panchip_prf_irq_enable(void);
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extern void panchip_prf_set_tx_pwr(int8_t tx_pwr);
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extern void panchip_prf_module_enable(pan_prf_config_t *p_config);
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extern pan_prf_version_t *panchip_prf_get_version(void);
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extern void panchip_prf_mode_conf_set(prf_mode_conf_sel_t conf);
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extern void panchip_prf_set_phy(prf_phy_t phy);
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extern void panchip_prf_rx_length_irq_cfg(uint8_t value);
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extern void panchip_prf_set_trx_mode(prf_trx_mode_t trx_mode);
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extern void panchip_prf_set_work_mode(prf_mode_t work_mode);
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extern void panchip_prf_set_addr(uint8_t *addr, uint8_t len, prf_pipe_t pipe, uint8_t trx_addr);
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extern void panchip_prf_set_tx_noack(bool flag);
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extern void panchip_prf_rx_timeout(uint16_t time);
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extern void panchip_prf_rx_stop(void);
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extern void panchip_prf_reset(void);
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extern void panchip_prf_pid_cfg(pan_prf_config_t *prf_config, uint8_t pid);
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extern void panchip_white_init_value(uint8_t value);
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extern void panchip_prf_carrier_start(uint16_t tx_channel);
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extern void panchip_prf_carrier_stop(void);
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extern int16_t panchip_prf_read_rssi(void);
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extern void panchip_prf_enable_carrier_rssi(void);
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extern void panchip_prf_disable_carrier_rssi(void);
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extern int16_t panchip_prf_read_carrier_rssi(void);
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extern void panchip_prf_b250k_init(void);
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extern void panchip_prf_isr_init(void);
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extern void panchip_prf_b250k_set_channel(uint8_t idx);
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extern uint32_t panchip_prf_encrypt_decrypt(uint8_t *plain_text,
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uint16_t plain_text_len,
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uint8_t *key,
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uint8_t *iv,
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uint8_t *encry_data,
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prf_enc_dec_mode_t enc_mode);
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extern void panchip_prf_rx_patch_handler(void);
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extern void panchip_prf_get_current_stamp(void);
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extern uint8_t panchip_prf_get_pipe(void);
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extern void panchip_prf_set_crc(prf_crc_sel_t crc, uint8_t crc_include_sync);
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extern void panchip_prf_set_whitening(prf_scramble_sel_t src, uint8_t src_include_sync);
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extern void panchip_prf_set_endian(prf_endian_t endian);
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extern void panchip_prf_reduce_trx_pre_post_delay_time(pan_prf_config_t *p_config, bool restore);
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extern int16_t panchip_prf_set_trx_trans_time(pan_prf_config_t *p_config,
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prf_speed_sel_t speed,
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uint16_t transfer_time);
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extern uint32_t data_addr_tx;
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extern uint32_t data_addr_rx;
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extern int8_t prf_rssi;
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extern pan_prf_config_t rf_config;
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extern pan_prf_callback_t isr_cb;
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extern volatile bool wake_from_lp_mode;
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#endif
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#ifdef __cplusplus
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}
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#endif
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