/*
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* JLink Script (Hook Functions) for PAN107X SoC downloading/debugging
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*/
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/*
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* PAN107X RCC Registers Map:
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*
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* #define CLK_BASE (0x40040000UL)
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*
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* #define CLK_RSTSTS (0x40040000UL)
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* #define CLK_IPRST0 (0x40040004UL)
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* #define CLK_IPRST1 (0x40040008UL)
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* #define CLK_BODCTL_3V (0x4004000CUL)
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* #define CLK_BLDBCTL_3V (0x40040010UL)
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* #define CLK_CLK_TOP_CTRL_3V (0x40040014UL)
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* #define CLK_RCL_CTRL_3V (0x40040018UL)
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* #define CLK_RCH_CTRL (0x4004001CUL)
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* #define CLK_XTL_CTRL_3V (0x40040020UL)
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* #define CLK_XTH_CTRL (0x40040024UL)
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* #define CLK_DPLL_CTRL (0x40040028UL)
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* #define CLK_AHB_CLK_CTRL (0x4004002CUL)
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* #define CLK_APB1_CLK_CTRL (0x40040030UL)
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* #define CLK_APB2_CLK_CTRL (0x40040034UL)
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* #define CLK_MEAS_CLK_CTRL (0x40040038UL)
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*/
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/*
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* PAN107X ANA Registers Map:
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*
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* #define ANA_BASE (0x40070000UL)
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*
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* #define ANA_LP_REG_SYNC (0x40070000UL)
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* #define ANA_LP_FL_CTRL_3V (0x40070004UL)
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* #define ANA_CPU_ADDR_REMAP_CTRL (0x4007005CUL)
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*/
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/*********************************************************************
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*
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* Constants, fixed
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*
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**********************************************************************
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*/
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//
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// Registers (PAN107X)
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//
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__constant U32 ANA_CPU_ADDR_REMAP_CTRL_REG_ADDR = 0x4007005C; // SoC CPU Remap Ctrl Register
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__constant U32 ANA_LP_FL_CTRL_3V_REG_ADDR = 0x40070004; // SoC Low Power Ctrl Register
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//
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// Registers (ARM)
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//
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__constant U32 _AIRCR_ADDR = 0xE000ED0C; // Application Interrupt and Reset Control Register
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__constant U32 _DHCSR_ADDR = 0xE000EDF0; // Debug Halting Control and Status Register
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__constant U32 _DEMCR_ADDR = 0xE000EDFC; // Debug Exception and Monitor Control Register
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//
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// Bits & Shifts (ARM)
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//
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__constant U32 _DP_CTRL_STAT_BIT_STICKYERR = (1 << 5);
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__constant U32 _DHCSR_DBGKEY = (0xA05F << 16);
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__constant U32 _DHCSR_C_DEBUGEN = (1 << 0);
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__constant U32 _DHCSR_C_HALT = (1 << 1);
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__constant U32 _DHCSR_S_HALT = (1 << 17);
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__constant U32 _DHCSR_S_RESET_ST = (1 << 25);
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__constant U32 _DEMCR_VC_CORERESET = (1 << 0);
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__constant U32 _DEMCR_TRCENA = (1 << 24);
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__constant U32 _AIRCR_VECTKEY = (0x05FA << 16);
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__constant U32 _AIRCR_SYSRESETREQ = (1 << 2);
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/*********************************************************************
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*
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* Constants, configurable
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*
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**********************************************************************
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*/
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__constant U32 _DEF_POST_RESET_DELAY = 50;
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/*********************************************************************
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*
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* Global functions
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*
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**********************************************************************
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*/
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/*
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* Do Panchip customized Cortex-M system reset flow
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* NOTE: __probe attribute specifies that this function is executed in the J-Link firmware
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* rather than on the PC side, so changes to global variables may only be temporarily
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* valid inside this function (not guaranteed to be valid later)
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*/
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__probe int DoSysReset(void)
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{
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int r;
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U32 v;
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int t;
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JLINK_SYS_Report("Reset: Halt core after reset via DEMCR.VC_CORERESET.");
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// Halt the CPU
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JLINK_MEM_WriteU32(_DHCSR_ADDR, (_DHCSR_DBGKEY | _DHCSR_C_HALT | _DHCSR_C_DEBUGEN));
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// Set vector catch on reset (to halt the CPU immediately after reset)
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JLINK_MEM_WriteU32(_DEMCR_ADDR, (_DEMCR_VC_CORERESET | _DEMCR_TRCENA));
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// Make sure that no sticky error bits are set on the DP
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JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_ABORT, 0x1E);
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JLINK_SYS_Report("Reset: Clear CPU Remap Ctrl Register.");
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// Clear CPU Remap ctrl reg before reset triggering
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JLINK_MEM_WriteU32(ANA_CPU_ADDR_REMAP_CTRL_REG_ADDR, 0x0);
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// Reset SoC Low Power ctrl reg (Clear BIT6 to indicate SysReset)
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JLINK_MEM_WriteU32(ANA_LP_FL_CTRL_3V_REG_ADDR, 0x00000008);
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// Make sure that no sticky error bits are set on the DP
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JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_ABORT, 0x1E);
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JLINK_SYS_Report("Reset: Reset device via AIRCR.SYSRESETREQ.");
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// Issue reset request via AIRCR.SYSRESETREQ
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JLINK_MEM_WriteU32(_AIRCR_ADDR, (_AIRCR_VECTKEY | _AIRCR_SYSRESETREQ));
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// The spec does not guarantee that the reset takes place immediately, so we give the target some time.
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JLINK_SYS_Sleep(_DEF_POST_RESET_DELAY);
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// Now the SoC is expected to be reset successfully and CPU core is expected to be halted
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// at the 1st instruction to be executed (in Reset_Handler).
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// NOTE:
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// For PAN107X SoC, sys_reset would cause swd connection lost, and here we re-init DAP module
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// before exiting this ResetTarget() hook function.
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//
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// Output DAP init sequence
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//
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r = JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_ABORT, 0x1E); // Make sure that no sticky error flags are set
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r |= JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_CTRL_STAT, (1 << 30) | (1 << 28)); // Set DBGPWRUPREQ and SYSPWRUPREQ to power up the complete DAP. Usually, no need to wait for the DAP to power up.
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r |= JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 24) | (0 << 4)); // Select AP[0] (AHB-AP), bank 0
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if (r < 0) {
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JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_ABORT, 0x1E); // Make sure that no sticky error flags are set
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JLINK_SYS_Report("Reset: SWD sticky error occurred.");
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return 1;
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}
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//
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// Here we should clear the vector catch we have set before
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//
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JLINK_MEM_WriteU32(_DEMCR_ADDR, (0x0 | _DEMCR_TRCENA));
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return 0;
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}
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/*********************************************************************
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*
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* ResetTarget()
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*
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* Function description
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* Replaces reset strategies of DLL. No matter what reset type is selected in the DLL, if this function is present,
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* it will be called instead of the DLL internal reset.
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*
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* Notes
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* (1) DLL expects target CPU to be halted / in debug mode, when leaving this function
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* (2) May use MEM_ API functions
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*/
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int ResetTarget(void)
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{
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int r;
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// Do Cortex-M sys reset
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if (DoSysReset()) {
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return 1;
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}
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return 0;
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}
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