/*
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* FreeRTOS Kernel V10.5.1
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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/*-----------------------------------------------------------
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* Implementation of functions defined in portable.h for the ARM CM0 port.
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*----------------------------------------------------------*/
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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/* Constants required to manipulate the NVIC. */
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#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
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#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
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#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
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#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
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#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
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#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
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#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
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#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
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#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
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#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
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#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
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#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
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#define portMIN_INTERRUPT_PRIORITY ( 255UL )
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#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )
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#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )
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#if ( configUSE_TICKLESS_IDLE == 1 )
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uint32_t ulTimerCountsForOneTick = 0; /*Used to calculate fast*/
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#endif
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/* Constants required to set up the initial stack. */
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#define portINITIAL_XPSR ( 0x01000000 )
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/* The systick is a 24-bit counter. */
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#define portMAX_24_BIT_NUMBER ( 0xffffffUL )
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/* A fiddle factor to estimate the number of SysTick counts that would have
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* occurred while the SysTick counter is stopped during tickless idle
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* calculations. */
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#ifndef portMISSED_COUNTS_FACTOR
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#define portMISSED_COUNTS_FACTOR ( 94UL )
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#endif
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/* Constants used with memory barrier intrinsics. */
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#define portSY_FULL_READ_WRITE ( 15 )
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/* Let the user override the default SysTick clock rate. If defined by the
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* user, this symbol must equal the SysTick clock rate when the CLK bit is 0 in the
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* configuration register. */
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#ifndef configSYSTICK_CLOCK_HZ
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#define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
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/* Ensure the SysTick is clocked at the same frequency as the core. */
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#define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT )
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#else
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/* Select the option to clock SysTick not at the same frequency as the core. */
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#define portNVIC_SYSTICK_CLK_BIT_CONFIG ( 0 )
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#endif
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/* Legacy macro for backward compatibility only. This macro used to be used to
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* replace the function that configures the clock used to generate the tick
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* interrupt (prvSetupTimerInterrupt()), but now the function is declared weak so
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* the application writer can override it by simply defining a function of the
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* same name (vApplicationSetupTickInterrupt()). */
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#ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION
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#define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 0
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#endif
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/* Each task maintains its own interrupt status in the critical nesting
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* variable. */
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static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
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/* The number of SysTick increments that make up one tick period. */
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#if ( configUSE_TICKLESS_IDLE == 1 )
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// static uint32_t ulTimerCountsForOneTick = 0;
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volatile TickType_t ulLPTmrLastCount = 0;
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#endif /* configUSE_TICKLESS_IDLE */
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/* The maximum number of tick periods that can be suppressed is limited by the
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* 24 bit resolution of the SysTick timer. */
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#if ( configUSE_TICKLESS_IDLE == 1 )
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// static uint32_t xMaximumPossibleSuppressedTicks = 0;
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#endif /* configUSE_TICKLESS_IDLE */
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/* Compensate for the CPU cycles that pass while the SysTick is stopped (low
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* power functionality only.
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*/
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#if ( configUSE_TICKLESS_IDLE == 1 )
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// static uint32_t ulStoppedTimerCompensation = 0;
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#endif /* configUSE_TICKLESS_IDLE */
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/*
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* Setup the timer to generate the tick interrupts. The implementation in this
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* file is weak to allow application writers to change the timer used to
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* generate the tick interrupt.
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*/
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void vPortSetupTimerInterrupt( void );
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/*
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* Exception handlers.
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*/
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void xPortPendSVHandler( void );
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void xPortSysTickHandler( void );
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void vPortSVCHandler( void );
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/*
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* Start first task is a separate function so it can be tested in isolation.
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*/
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static void prvPortStartFirstTask( void );
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/*
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* Used to catch tasks that attempt to return from their implementing function.
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*/
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static void prvTaskExitError( void );
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/*-----------------------------------------------------------*/
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/*
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* See header file for description.
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*/
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StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
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TaskFunction_t pxCode,
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void * pvParameters )
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{
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/* Simulate the stack frame as it would be created by a context switch
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* interrupt. */
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pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
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*pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) pxCode; /* PC */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */
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pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
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*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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pxTopOfStack -= 8; /* R11..R4. */
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return pxTopOfStack;
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}
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/*-----------------------------------------------------------*/
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static void prvTaskExitError( void )
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{
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/* A function that implements a task must not exit or attempt to return to
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* its caller as there is nothing to return to. If a task wants to exit it
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* should instead call vTaskDelete( NULL ).
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*
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* Artificially force an assert() to be triggered if configASSERT() is
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* defined, then stop here so application writers can catch the error. */
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configASSERT( uxCriticalNesting == ~0UL );
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portDISABLE_INTERRUPTS();
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for( ; ; )
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{
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}
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}
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/*-----------------------------------------------------------*/
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void vPortSVCHandler( void )
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{
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/* This function is no longer used, but retained for backward
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* compatibility. */
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}
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/*-----------------------------------------------------------*/
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__asm void prvPortStartFirstTask( void )
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{
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extern pxCurrentTCB;
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PRESERVE8
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/* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector
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* table offset register that can be used to locate the initial stack value.
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* Not all M0 parts have the application vector table at address 0. */
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/* *INDENT-OFF* */
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ldr r3, = pxCurrentTCB /* Obtain location of pxCurrentTCB. */
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ldr r1, [ r3 ]
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ldr r0, [ r1 ] /* The first item in pxCurrentTCB is the task top of stack. */
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adds r0, # 32 /* Discard everything up to r0. */
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msr psp, r0 /* This is now the new top of stack to use in the task. */
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movs r0, # 2 /* Switch to the psp stack. */
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msr CONTROL, r0
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isb
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pop { r0 - r5 } /* Pop the registers that are saved automatically. */
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mov lr, r5 /* lr is now in r5. */
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pop { r3 } /* The return address is now in r3. */
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pop { r2 } /* Pop and discard the XPSR. */
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cpsie i /* The first task has its context and interrupts can be enabled. */
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bx r3 /* Finally, jump to the user defined task code. */
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ALIGN
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/* *INDENT-ON* */
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}
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/*-----------------------------------------------------------*/
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/*
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* See header file for description.
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*/
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BaseType_t xPortStartScheduler( void )
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{
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#if ( configUSE_TICKLESS_IDLE == 1 )
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vTaskTickSet(lp_get_curr_tmr_cnt());
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ulTimerCountsForOneTick = configSYSTICK_CLOCK_HZ / configTICK_ON_WAKING_RATE_HZ;
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#endif
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/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
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portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
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portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
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/* Start the timer that generates the tick ISR. Interrupts are disabled
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* here already. */
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vPortSetupTimerInterrupt();
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/* Initialise the critical nesting count ready for the first task. */
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uxCriticalNesting = 0;
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/* Start the first task. */
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prvPortStartFirstTask();
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/* Should not get here! */
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return 0;
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}
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/*-----------------------------------------------------------*/
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void vPortEndScheduler( void )
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{
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/* Not implemented in ports where there is nothing to return to.
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* Artificially force an assert. */
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configASSERT( uxCriticalNesting == 1000UL );
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}
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/*-----------------------------------------------------------*/
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void vPortYield( void )
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{
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/* Set a PendSV to request a context switch. */
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portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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/* Barriers are normally not required but do ensure the code is completely
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* within the specified behaviour for the architecture. */
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__dsb( portSY_FULL_READ_WRITE );
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__isb( portSY_FULL_READ_WRITE );
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}
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/*-----------------------------------------------------------*/
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CONFIG_RAM_CODE void vPortEnterCritical( void )
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{
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portDISABLE_INTERRUPTS();
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uxCriticalNesting++;
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__dsb( portSY_FULL_READ_WRITE );
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__isb( portSY_FULL_READ_WRITE );
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}
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/*-----------------------------------------------------------*/
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void vPortExitCritical( void )
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{
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configASSERT( uxCriticalNesting );
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uxCriticalNesting--;
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if( uxCriticalNesting == 0 )
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{
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portENABLE_INTERRUPTS();
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}
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}
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/*-----------------------------------------------------------*/
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__asm uint32_t ulSetInterruptMaskFromISR( void )
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{
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/* *INDENT-OFF* */
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mrs r0, PRIMASK
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cpsid i
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bx lr
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/* *INDENT-ON* */
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}
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/*-----------------------------------------------------------*/
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__asm void vClearInterruptMaskFromISR( uint32_t ulMask )
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{
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/* *INDENT-OFF* */
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msr PRIMASK, r0
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bx lr
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/* *INDENT-ON* */
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}
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/*-----------------------------------------------------------*/
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CONFIG_RAM_CODE __asm void xPortPendSVHandler( void )
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{
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extern vTaskSwitchContext
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extern pxCurrentTCB
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/* *INDENT-OFF* */
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PRESERVE8
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mrs r0, psp
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ldr r3, = pxCurrentTCB /* Get the location of the current TCB. */
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ldr r2, [ r3 ]
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subs r0, # 32 /* Make space for the remaining low registers. */
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str r0, [ r2 ] /* Save the new top of stack. */
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stmia r0 !, { r4 - r7 } /* Store the low registers that are not saved automatically. */
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mov r4, r8 /* Store the high registers. */
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mov r5, r9
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mov r6, r10
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mov r7, r11
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stmia r0 !, { r4 - r7 }
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push { r3, r14 }
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cpsid i
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bl vTaskSwitchContext
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cpsie i
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pop { r2, r3 } /* lr goes in r3. r2 now holds tcb pointer. */
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ldr r1, [ r2 ]
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ldr r0, [ r1 ] /* The first item in pxCurrentTCB is the task top of stack. */
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adds r0, # 16 /* Move to the high registers. */
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ldmia r0 !, { r4 - r7 } /* Pop the high registers. */
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mov r8, r4
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mov r9, r5
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mov r10, r6
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mov r11, r7
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msr psp, r0 /* Remember the new top of stack for the task. */
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subs r0, # 32 /* Go back for the low registers that are not automatically restored. */
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ldmia r0 !, { r4 - r7 } /* Pop low registers. */
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bx r3
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ALIGN
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/* *INDENT-ON* */
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}
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/*-----------------------------------------------------------*/
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#if ( configUSE_TICKLESS_IDLE == 1 )
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CONFIG_RAM_CODE void UpdateTickAndSch(void)
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{
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uint32_t ulPreviousMask;
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ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
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{
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vTaskTickSet(lp_get_curr_tmr_cnt());
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/* Increment the RTOS tick. */
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if( xTaskIncrementTick() != pdFALSE )
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{
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/* Pend a context switch. */
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portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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}
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}
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portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
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}
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#endif
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CONFIG_RAM_CODE void xPortSysTickHandler( void )
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{
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PAN_IO_TIMING_TRACK_LEVEL(CONFIG_TRACK_PIN_OS_TICK_IRQ, 1);
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#if ( configUSE_TICKLESS_IDLE == 1 )
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UpdateTickAndSch();
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if(portNVIC_SYSTICK_LOAD_REG != (ulTimerCountsForOneTick - 1UL))
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{
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portNVIC_SYSTICK_CTRL_REG = 0UL;
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portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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/* Configure SysTick to interrupt at the requested rate. */
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portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
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portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
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}
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#else
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uint32_t ulPreviousMask;
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ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
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{
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/* Increment the RTOS tick. */
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if( xTaskIncrementTick() != pdFALSE )
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{
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/* Pend a context switch. */
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portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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}
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}
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portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
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#endif
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PAN_IO_TIMING_TRACK_LEVEL(CONFIG_TRACK_PIN_OS_TICK_IRQ, 0);
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}
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/*-----------------------------------------------------------*/
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/*
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* Setup the systick timer to generate the tick interrupts at the required
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* frequency.
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*/
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#if ( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 )
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__weak void vPortSetupTimerInterrupt( void )
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{
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/* Stop and clear the SysTick. */
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portNVIC_SYSTICK_CTRL_REG = 0UL;
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portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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/* Configure SysTick to interrupt at the requested rate. */
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#if ( configUSE_TICKLESS_IDLE == 1 )
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portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
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portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
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#else
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portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
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portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
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#endif
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}
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#endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */
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/*-----------------------------------------------------------*/
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CONFIG_RAM_CODE void vPortSysTickRestart(uint32_t tick)
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{
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/* restart systick, use configTICK_ON_WAKING_RATE_HZ */
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portNVIC_SYSTICK_CTRL_REG = 0UL;
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portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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/* Configure SysTick to interrupt at the requested rate. */
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portNVIC_SYSTICK_LOAD_REG = tick - 1; //ulTimerCountsForOneTick - 1UL;
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portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
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}
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