BLE_PAN1070.git

改为中断来低电平触发发送当前扫描数据，3s内扫描不到的会退出，串口来55 AA 75 70 64 61 74 65，进入升级模式
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2025-04-24 ae079c1fc5d990ba55714d4b3a51b19f96edaec4
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¹qpÙ, ..\..\..\..\config\soc_config.hÿ¼Ù).\configuration\sdk_config.hß¸¼÷Ù9-C:\Keil_v5\ARM\ARMCC\Bin\..\include\stddef.hÜ Íò@Ù9-C:\Keil_v5\ARM\ARMCC\Bin\..\include\string.hÜ Íò#ÙH<..\..\..\..\host\nimble\nimble\host\include\host/ble_gatt.hÿ¼øÙ;/C:\Keil_v5\ARM\ARMCC\Bin\..\include\inttypes.hÜ Íò6Ù9-C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.hÜ Íò$ÙG;..\..\..\..\host\nimble\nimble\host\include\host/ble_att.hÿ¼aÙF:..\..\..\..\host\nimble\porting\nimble\include\os/queue.hÿ¼°ÙH<..\..\..\..\host\nimble\nimble\host\include\host/ble_uuid.hÿ¼ñÙSG..\..\..\..\host\nimble\porting\npl\freertos\include\console/console.hÿ¼Ù8,C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.hÜ ÍòÙ@4..\..\..\..\host\nimble\nimble\include\nimble/ble.hÿ¼xÙ/#..\..\..\..\config\nimble_syscfg.hÿ¼<ÙC7..\..\..\..\host\nimble\porting\nimble\include\os/os.hÿ¼ùÙ9-C:\Keil_v5\ARM\ARMCC\Bin\..\include\assert.hÚ Íò*ÙG;..\..\..\..\host\nimble\nimble\include\nimble/nimble_npl.hÿ¼}Ù:.C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdbool.hÜ ÍòÁÙXL..\..\..\..\host\nimble\porting\npl\freertos\include\nimble/nimble_npl_os.hÿ¼"Ù9-C:\Keil_v5\ARM\ARMCC\Bin\..\include\assert.hÚ Íò*Ù7+..\..\..\..\os\freertos\include\FreeRTOS.hÿ¼UÙ0$..\..\..\..\config\FreeRTOSConfig.hÿ¼Ù^R..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\PanSeries.hÿ¼rÙ9-C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdlib.hÜ Íò8Ù\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\core_cm0.hÿ¼)ÙaU..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\cmsis_version.hÿ¼£ÙbV..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\cmsis_compiler.hÿ¼LÙ_S..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\cmsis_armcc.hÿ¼§ÙeY..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\system_PanSeries.hÿ¼`Ù`T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_sys_log.hÿ¼ZÙ\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_sys.hÿ¼Ù\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_clk.hÿ¼(Ù\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_adc.hÿ¼Ù\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_fmc.hÿ¼úÙ]Q..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_dmac.hÿ¼Ù]Q..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_gpio.hÿ¼Ù\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_spi.hÿ¼äÙ]Q..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_uart.hÿ¼rÙ\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_i2c.hÿ¼2Ù^R..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_timer.hÿ¼Ù\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_pwm.hÿ¼ÜÙ\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_wdt.hÿ¼áÙ]Q..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_wwdt.hÿ¼hÙ[O..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_lp.hÿ¼Ù^R..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_efuse.hÿ¼FÙfZ..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\radio\prf_lib\include\pan_pri_rf.hÿ¼ÓÙ^R..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\PanSeries.hÿ¼rÙ`T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_clktrim.hÿ¼dÙ^R..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_power.hÿ¼1Ù\P..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal.hÿ¼ûÙaU..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_gpio.hÿ¼ãÙ`T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_def.hÿ¼eÙaU..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_uart.hÿ¼ÖÙaU..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_dmac.hÿ¼ýÙ`T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_spi.hÿ¼HÙ`T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_i2c.hÿ¼Ù`T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_wdt.hÿ¼EÙaU..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_wwdt.hÿ¼ÌÙ`T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_pwm.hÿ¼@ÙbV..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_timer.hÿ¼oÙ`T..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_adc.hÿ¼lÙ7+..\..\..\..\os\freertos\include\projdefs.hÿ¼ÂÙ7+..\..\..\..\os\freertos\include\portable.hÿ¼ÆÙE9..\..\..\..\os\freertos\include\deprecated_definitions.hÿ¼÷ÙF:..\..\..\..\os\freertos\portable\RVDS\ARM_CM0\portmacro.hÿ¼¿Ù;/..\..\..\..\os\freertos\include\mpu_wrappers.hÿ¼òÙ4(..\..\..\..\os\freertos\include\queue.hÿ¼Ù3'..\..\..\..\os\freertos\include\task.hÿ¼tÙ3'..\..\..\..\os\freertos\include\list.hÿ¼kÙ5).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<unnamed>QÚ 
"ÔISRõÚ 
"Ô_reserved0æÚ "ÓbtÚ 
"ÓwqÚ
IPSR_Type°ÚP IPSR_ISR_PosÚP IPSR_ISR_MskÚ8
<unnamed>SÚ8
<unnamed>QÚ 
"ÝISRìÚ 
"Ý_reserved0ÝÚ 
"ÝTÚ 
"Ý_reserved1ÜÚ 
"ÝVÚ 
"ÝCÚ 
"ÝZÚ 
"ÝNÚ "ÜbkÚ 
"ÜwhÚ
xPSR_TypeÚPxPSR_N_PosÚPxPSR_N_MskÚPxPSR_Z_PosÚPxPSR_Z_MskÚPxPSR_C_PosÚPxPSR_C_MskÚPxPSR_V_PosÚPxPSR_V_MskÚPxPSR_T_PosÚPxPSR_T_Msk ÚP xPSR_ISR_PoshÚP xPSR_ISR_MskoÚ8
<unnamed>SÚ8
<unnamed>QÚ 
"ö_reserved0ÄÚ 
"öSPSEL6Ú 
"ö_reserved1ÃÚ "õbRÚ 
"õwOÚ CONTROL_TypeÇÚPCONTROL_SPSEL_PosÚPCONTROL_SPSEL_MskÚ8
<unnamed>QÚ <"ÿISERQÚ <"|ÿ
RESERVED0rÚ <"ÿICERaÚ <"|ÿ
RESERVED1qÚ <"ÿISPRFÚ <"|ÿ
RESERVED2pÚ <"ÿICPRVÚ <"|ÿ
RESERVED3oÚ <"ÿ
RESERVED4gÚ  <" ÿIPÓÚ
NVIC_Type¾Ú8
<unnamed>QÚ 
" CPUID²Ú 
" ICSRøÚ 
" 
RESERVED0Ú 
" AIRCR¶Ú 
" SCRCÚ 
" CCRSÚ 
" 
RESERVED1Ú <" SHP
Ú 
" SHCSR¤Ú    SCB_TypeÚ"PSCB_CPUID_IMPLEMENTER_Pos»Ú"PSCB_CPUID_IMPLEMENTER_MskÂÚPSCB_CPUID_VARIANT_PosðÚPSCB_CPUID_VARIANT_Msk÷Ú#PSCB_CPUID_ARCHITECTURE_PosxÚ#PSCB_CPUID_ARCHITECTURE_MskÚPSCB_CPUID_PARTNO_Pos3ÚPSCB_CPUID_PARTNO_Msk:ÚPSCB_CPUID_REVISION_PosÚPSCB_CPUID_REVISION_MskÚ PSCB_ICSR_NMIPENDSET_PosNÚ PSCB_ICSR_NMIPENDSET_MskUÚPSCB_ICSR_PENDSVSET_PosÚPSCB_ICSR_PENDSVSET_MskÚPSCB_ICSR_PENDSVCLR_PosÚPSCB_ICSR_PENDSVCLR_MskÚPSCB_ICSR_PENDSTSET_PosÚPSCB_ICSR_PENDSTSET_MskÚPSCB_ICSR_PENDSTCLR_PosÚPSCB_ICSR_PENDSTCLR_MskÚ PSCB_ICSR_ISRPREEMPT_Pos:Ú PSCB_ICSR_ISRPREEMPT_MskAÚ PSCB_ICSR_ISRPENDING_PosRÚ PSCB_ICSR_ISRPENDING_MskYÚ!PSCB_ICSR_VECTPENDING_PosÚ!PSCB_ICSR_VECTPENDING_MskÚ PSCB_ICSR_VECTACTIVE_PosWÚ PSCB_ICSR_VECTACTIVE_Msk^ÚPSCB_AIRCR_VECTKEY_PosîÚPSCB_AIRCR_VECTKEY_MskõÚ"PSCB_AIRCR_VECTKEYSTAT_PosªÚ"PSCB_AIRCR_VECTKEYSTAT_Msk±Ú PSCB_AIRCR_ENDIANESS_PoskÚ PSCB_AIRCR_ENDIANESS_MskrÚ"PSCB_AIRCR_SYSRESETREQ_PosÚ"PSCB_AIRCR_SYSRESETREQ_MskÚ$PSCB_AIRCR_VECTCLRACTIVE_Pos.Ú$PSCB_AIRCR_VECTCLRACTIVE_Msk5ÚPSCB_SCR_SEVONPEND_PosàÚPSCB_SCR_SEVONPEND_MskçÚPSCB_SCR_SLEEPDEEP_PosûÚPSCB_SCR_SLEEPDEEP_MskÚ PSCB_SCR_SLEEPONEXIT_Pos>Ú PSCB_SCR_SLEEPONEXIT_MskEÚPSCB_CCR_STKALIGN_PosGÚPSCB_CCR_STKALIGN_MskNÚ PSCB_CCR_UNALIGN_TRP_Pos;Ú PSCB_CCR_UNALIGN_TRP_MskBÚ#PSCB_SHCSR_SVCALLPENDED_PosxÚ#PSCB_SHCSR_SVCALLPENDED_MskÚ8
<unnamed>QÚ 
"È CTRL·Ú 
"È LOADÌÚ 
"È VALÚ 
"È CALIBÚ SysTick_TypeÚ#PSysTick_CTRL_COUNTFLAG_Pos¦Ú#PSysTick_CTRL_COUNTFLAG_MskÚ#PSysTick_CTRL_CLKSOURCE_PosÚ#PSysTick_CTRL_CLKSOURCE_Msk¥Ú!PSysTick_CTRL_TICKINT_Pos7Ú!PSysTick_CTRL_TICKINT_Msk>Ú PSysTick_CTRL_ENABLE_Pos¨Ú PSysTick_CTRL_ENABLE_Msk¯Ú PSysTick_LOAD_RELOAD_PosÚ PSysTick_LOAD_RELOAD_Msk´Ú PSysTick_VAL_CURRENT_Pos~Ú PSysTick_VAL_CURRENT_MskÚ PSysTick_CALIB_NOREF_Pos¯Ú PSysTick_CALIB_NOREF_Msk¶ÚPSysTick_CALIB_SKEW_PosñÚPSysTick_CALIB_SKEW_MskøÚ PSysTick_CALIB_TENMS_Pos¢Ú PSysTick_CALIB_TENMS_Msk©ÚP    _VAL2FLDqÚP    _FLD2VALqÚP    SCS_BASEXÚP SysTick_BASEoÚP
NVIC_BASEÚP    SCB_BASEiÚPSCBíÚPSysTickóÚ PNVICÚPCMSIS_NVIC_VIRTUALÚ!PNVIC_SetPriorityGrouping3Ú!PNVIC_GetPriorityGrouping?ÚPNVIC_EnableIRQíÚPNVIC_GetEnableIRQÇÚPNVIC_DisableIRQ~ÚPNVIC_GetPendingIRQGÚPNVIC_SetPendingIRQ;ÚPNVIC_ClearPendingIRQ|ÚPNVIC_SetPriorityÚPNVIC_GetPriorityÚPNVIC_SystemResetÚPCMSIS_VECTAB_VIRTUALÚPNVIC_SetVectorÚPNVIC_GetVectorÚPNVIC_USER_IRQ_OFFSETdÚPEXC_RETURN_HANDLER+ÚPEXC_RETURN_THREAD_MSPÚPEXC_RETURN_THREAD_PSPÚP_BIT_SHIFTÚP    _SHP_IDX-ÚP_IP_IDXÚ#P__NVIC_SetPriorityGroupingqÚ#P__NVIC_GetPriorityGrouping}Ú__NVIC_EnableIRQTÚ,""IRQn·Ú__memory_changedHÚ__NVIC_GetEnableIRQ.Ú,""IRQn´Ú__NVIC_DisableIRQåÚ,""IRQn²Ú__schedule_barriersÚ__dsbçÚ__isbâÚ__NVIC_GetPendingIRQ®Ú,""IRQnÚ__NVIC_SetPendingIRQ¢Ú,""IRQn«Ú__NVIC_ClearPendingIRQãÚ,""IRQn©Ú__NVIC_SetPriorityõÚ,""IRQn§Ú,
"    priorityÚ__NVIC_GetPriorityÚ,""IRQn¤ÚNVIC_EncodePriorityÚ,
"PriorityGroupÚ,
"PreemptPriority¼Ú,
"SubPrioritywÚ
"PriorityGroupTmp}Ú
"PreemptPriorityBitsFÚ
"SubPriorityBitsÚNVIC_DecodePriorityÚ,
"    Priority Ú,
"PriorityGroupÚ,"pPreemptPriority5Ú," pSubPriorityðÚ
"PriorityGroupTmpvÚ
"PreemptPriorityBits?Ú
"SubPriorityBitsúÚ__NVIC_SetVectorèÚ,""¥IRQnÚ,
"¥vectorkÚ
"¥vectorsÚ__NVIC_GetVectorôÚ,""©IRQnÚ
"©vectorsÚ__NVIC_SystemResetûÚ__nopÓÚSCB_GetFPUTypeôÚSysTick_ConfigYÚ,
"¯ticksØÚP__SYSTEM_PANSERIES_H__ÚP__PAN_STRINGIFYòÚPPAN_STRINGIFY´ÚP __PAN_CONCATÿÚPPAN_CONCATÁÚP__PAN_COND_CODE_1ÚP__PAN_COND_CODE_0ÚP_AAAAA1èÚP_BBBBB0äÚP__PAN_COND_CODEÚ!P__PAN_GET_ARG2_DEBRACKETpÚP__PAN_DEBRACKET,ÚPPAN_COND_CODE_1AÚPPAN_COND_CODE_0BÚ8_adc_vbg_kb^Ú "¿
adc_vbg_kXÚ "¿
adc_vbg_bcÚ ADC_VBG_KB_TDÚ8_otp_structûÚ <"Ãd8§Ú8
<unnamed>QÚ <"Årsvd0±Ú "Å pmu_vbg_trimÚÚ "Årsvd1Ú "Åpmu_vbg_volt_lÚ "Åpmu_vbg_volt_hÚ "Åhp_ldo_trimVÚ "Åhp_ldo_volt_l~Ú "Åhp_ldo_volt_hÚ "Å lph_ldo_trimèÚ "Ålph_ldo_volt_lÚ "Ålph_ldo_volt_hÚ "Å lpl_ldo_trimäÚ "Ålpl_ldo_volt_lÚ "Ålpl_ldo_volt_hÚ "Åflash_ldo_trimÚ "Årsvd2Ú "Åflash_ldo_volt_lBÚ "Åflash_ldo_volt_hFÚ "Å ana_ldo_trimüÚ "Årffe_ldo_trimÚ "Åfsyn_ldo_trimjÚ "Å adc_ldo_trimÚ "Å vco_ldo_trimäÚ "Åipoly_trim¡Ú "Årsvd3Ú "Åbod_vref_trimÚ "Årsvd4Ú "Åbod_vref_volt_l©Ú "Åbod_vref_volt_hÚ "Åadc_vbg_1v17_trimÚ "Årsvd5ÿÚ "Åadc_vbg_1v17_voltzÚ "Åadc_vbg_1v20_trimÚ "Årsvd6þÚ "Åadc_vbg_1v20_voltÚ "Å    rch_trimÚ 
"Å    rch_freqÚ "Årcl_coarse_trim§Ú "Årsvd7ýÚ "Årcl_fine_trimÚ "Å    rcl_freqÚ "Åxth_xocap_aHÚ "Åxth_xocap_m<Ú "Åxth_xocap_n;Ú "Åxtl_xocap_aDÚ "Åxtl_xocap_m8Ú "Åxtl_xocap_n7Ú "Åbuck_imax_cal_trim|Ú "Årsvd8üÚ "Åbuck_zero_cal_trimkÚ "Årsvd9ûÚ "Åbuck_out_trimlÚ "Årsvd10ÑÚ "Åbuck_vout_voltâÚ "Å
adc_vdd_kSÚ "Å
adc_vdd_bgÚ "Å
adc_vbg_kRÚ "Å
adc_vbg_b]Ú "Åadc_temp_voltyÚ "Åcurrent_temp_value>Ú "Å battery_trimÏÚ# "Åpa_power_calib_trim_6dbm3Ú# "Åpa_power_calib_trim_0dbm9Ú <"Å    mac_addrÚ <"    ÅuidwÚ "Å
chip_info<Ú "Åcp_version±Ú "Åft_versionªÚ "Å cp_pass_flagÚ "Å ft_pass_flagüÚ "Åcp_checksumbÚ "Åft_checksum[Ú <"Å user_rw_data¬Ú  "ÃmùÚ8
<unnamed>QÚ <"rsvd0åÚ " pmu_vbg_trimÚ "rsvd17Ú "pmu_vbg_volt_l6Ú "pmu_vbg_volt_h:Ú "hp_ldo_trimÚ "hp_ldo_volt_l²Ú "hp_ldo_volt_h¶Ú " lph_ldo_trimÚ "lph_ldo_volt_lDÚ "lph_ldo_volt_hHÚ " lpl_ldo_trimÚ "lpl_ldo_volt_l@Ú "lpl_ldo_volt_hDÚ "flash_ldo_trimNÚ "rsvd26Ú "flash_ldo_volt_lvÚ "flash_ldo_volt_hzÚ " ana_ldo_trim0Ú "rffe_ldo_trim»Ú "fsyn_ldo_trimÚ " adc_ldo_trim8Ú " vco_ldo_trimÚ "ipoly_trimÕÚ "rsvd35Ú "bod_vref_trimµÚ "rsvd44Ú "bod_vref_volt_lÝÚ "bod_vref_volt_háÚ "rsvd53Ú "    xtl_coreÁÚ "
xth_icoreZÚ "    rch_biasæÚ "dpll_vco_freq_trimÚ "dpll_kvco_ctrlCÚ "dpll_icp_ctrl¼Ú "dpll_icp_biasÒÚ "rsvd62Ú "adc_vbg_1v20_trimÆÚ "ptat_temp_trim,Ú "adc_vbg_1v20_volt´Ú "    rch_trimÉÚ 
"    rch_freqÐÚ "rcl_coarse_trimÛÚ "lph_ldo_vref_trimÚ "rsvd71Ú "rcl_fine_trimºÚ "    rcl_freqÊÚ "analog_temp_volt]Ú <"

rsvd_0x3eÚ "analog_0p6v_voltÇÚ <"
rsvd8ñÚ "buck_imax_cal_trim°Ú "rsvd9/Ú "buck_zero_cal_trimÚ "rsvd10Ú "buck_out_trim Ú "rsvd11Ú "buck_vout_voltÚ "
adc_vdd_kÚ "
adc_vdd_bÚ "
adc_vbg_kÚ "
adc_vbg_bÚ "adc_temp_voltÚ "current_temp_valuerÚ " battery_trimÚ <"rsvd12ÇÚ <"    uid«Ú "
chip_infopÚ "cp_versionåÚ "ft_versionÞÚ " cp_pass_flag7Ú " ft_pass_flag0Ú "cp_checksumÚ "ft_checksumÚ <" user_rw_dataàÚ <"    mac_addr»Ú "xth_xocap_a|Ú "xth_xocap_mpÚ "xth_xocap_noÚ "xth_xocap_trim,Ú "xtl_xocap_axÚ "xtl_xocap_mlÚ "xtl_xocap_nkÚ "xtl_xocap_trim(Ú <"adc_vbg_kbÚÚ "adc_vbat_kÚ "adc_vbat_b!Ú "adc_vbat_dtemp_kÚ "adc_vbat_dtemp_bÚ "adc_temp_kÚ 
"
adc_ctrl2ªÚ 
"adc_extsmptxÚ "xth_fix_code1òÚ "xth_fix_code2ñÚ "xtl_fix_code1îÚ "xtl_fix_code2íÚ <"+rsvd13¢Ú " ft_checksum2[Ú "Ãm_v2ëÚ OTP_STRUCT_TÿÚisFtDataValidèÚSystemCoreClockUpdateaÚSystemInit»Ú,otpxÚSystemHwParamLoader6ÚRESETpÚSETÚFlagStatusïÚ    ITStatusÐÚDISABLEûÚENABLEJÚFunctionalStateÏÚPIS_FUNCTIONAL_STATE×Ú8
<unnamed>QÚ 
"CTLMÚ 
"CMPPÚ 
"INTSTSEÚ 
"CNTKÚ 
"CAP\Ú 
"EXTCTLVÚ 
"EINTSTSþÚ 
"CMP1Ú 
"CMP2ÚTIMER_T¿ÚPTIMER_CTL_PSC_PosÚPTIMER_CTL_PSC_MskÚPTIMER_CTL_CAPSRC_Pos4ÚPTIMER_CTL_CAPSRC_Msk;ÚPTIMER_CTL_WKEN_Pos¿ÚPTIMER_CTL_WKEN_MskÆÚPTIMER_CTL_EXTCNTEN_PosÚPTIMER_CTL_EXTCNTEN_MskÚPTIMER_CTL_ACTSTS_PosÚPTIMER_CTL_ACTSTS_Msk%ÚPTIMER_CTL_RSTCNT_PosÚPTIMER_CTL_RSTCNT_MskÚPTIMER_CTL_OPMODE_Pos,ÚPTIMER_CTL_OPMODE_Msk3ÚPTIMER_CTL_INTEN_PostÚPTIMER_CTL_INTEN_Msk{ÚPTIMER_CTL_CNTEN_PoszÚPTIMER_CTL_CNTEN_MskÚPTIMER_CTL_ICEDEBUG_Pos´ÚPTIMER_CTL_ICEDEBUG_Msk»ÚPTIMER_CMP_CMPDAT_Pos:ÚPTIMER_CMP_CMPDAT_MskAÚPTIMER_INTSTS_TIF_PosÚPTIMER_INTSTS_TIF_MskÚPTIMER_INTSTS_TWKF0_Pos~ÚPTIMER_INTSTS_TWKF0_MskÚPTIMER_INTSTS_TWKF1_Pos}ÚPTIMER_INTSTS_TWKF1_MskÚPTIMER_INTSTS_TWKF2_Pos|ÚPTIMER_INTSTS_TWKF2_MskÚPTIMER_INTSTS_TF0_Pos$ÚPTIMER_INTSTS_TF0_Msk+ÚPTIMER_INTSTS_TF1_Pos#ÚPTIMER_INTSTS_TF1_Msk*ÚPTIMER_INTSTS_TF2_Pos"ÚPTIMER_INTSTS_TF2_Msk)ÚPTIMER_CNT_CNT_PosÚPTIMER_CNT_CNT_MskÚPTIMER_CAP_CAPDAT_PosRÚPTIMER_CAP_CAPDAT_MskYÚ"PTIMER_EXTCTL_CNTPHASE_PosÚ"PTIMER_EXTCTL_CNTPHASE_Msk¦Ú!PTIMER_EXTCTL_CAPEDGE_PosÚ!PTIMER_EXTCTL_CAPEDGE_MskÚPTIMER_EXTCTL_CAPEN_PosÚPTIMER_EXTCTL_CAPEN_MskÚ"PTIMER_EXTCTL_CAPFUNCS_Pos¢Ú"PTIMER_EXTCTL_CAPFUNCS_Msk©Ú PTIMER_EXTCTL_CAPIEN_PosIÚ PTIMER_EXTCTL_CAPIEN_MskPÚ!PTIMER_EXTCTL_CAPDBEN_Pos
Ú!PTIMER_EXTCTL_CAPDBEN_MskÚ!PTIMER_EXTCTL_CNTDBEN_PosùÚ!PTIMER_EXTCTL_CNTDBEN_MskÚ PTIMER_EXTCTL_CAPSEL_PosAÚ PTIMER_EXTCTL_CAPSEL_MskHÚ"PTIMER_EXTCTL_ACMPSSEL_PosÚ"PTIMER_EXTCTL_ACMPSSEL_Msk¤Ú PTIMER_EINTSTS_CAPIF_Pos@Ú PTIMER_EINTSTS_CAPIF_MskGÚPTIMER_EINTSTS_CAPF_PosÚPTIMER_EINTSTS_CAPF_MskÚ8
<unnamed>QÚ 
"ÌTRIM_EN±Ú 
"Ì
TRIM_CODE%Ú 
"Ì
TRIM_CTRLÚ 
"Ì    TRIM_INTWÚ 
"Ì TRIM_CAL_CNT&Ú 
"ÌTRIM_IDEAL_CNTÚ 
"ÌTRIM_REAL_CNTÐÚTRIM_TÚ#PTRIM_MEASURE_TUNING_EN_Pos3Ú#PTRIM_MEASURE_TUNING_EN_Msk:Ú"PTRIM_COARSE_TUNING_EN_PosÚ"PTRIM_COARSE_TUNING_EN_MskÚ PTRIM_FINE_TUNING_EN_Pos)Ú PTRIM_FINE_TUNING_EN_Msk0ÚPTRIM_COARSE_CODE_Pos@ÚPTRIM_COARSE_CODE_MskGÚPTRIM_FINE_CODE_PosßÚPTRIM_FINE_CODE_MskæÚPTRIM_BIT_WIDTH_Pos½ÚPTRIM_BIT_WIDTH_MskÄÚPTRIM_CLRL_RELATION_PosÚPTRIM_CLRL_RELATION_MskÚ$PTRIM_CLRL_EARLY_TERM_EN_Pos×Ú$PTRIM_CLRL_EARLY_TERM_EN_MskÞÚ%PTRIM_CLRL_FAIL_CLAC_FLAG_PosÔÚ%PTRIM_CLRL_FAIL_CLAC_FLAG_MskÛÚ PTRIM_CLRL_CODE_STEP_Pos/Ú PTRIM_CLRL_CODE_STEP_Msk6Ú PTRIM_CLRL_ERR_RANGE_Pos0Ú PTRIM_CLRL_ERR_RANGE_Msk7ÚPTRIM_INT_EN_Pos¤ÚPTRIM_INT_EN_Msk«Ú"PTRIM_INT_MEASURE_STOP_PoslÚ"PTRIM_INT_MEASURE_STOP_MsksÚ#PTRIM_FLAG_MEASURE_STOP_Pos;Ú#PTRIM_FLAG_MEASURE_STOP_MskBÚ PTRIM_INT_CTUNE_STOP_PosÚ PTRIM_INT_CTUNE_STOP_Msk
Ú!PTRIM_FLAG_CTUNE_STOP_PosÒÚ!PTRIM_FLAG_CTUNE_STOP_MskÙÚ PTRIM_INT_FTUNE_STOP_PosÚ PTRIM_INT_FTUNE_STOP_MskÚ!PTRIM_FLAG_FTUNE_STOP_PosÏÚ!PTRIM_FLAG_FTUNE_STOP_MskÖÚPTRIM_INT_OVERFLOW_Pos·ÚPTRIM_INT_OVERFLOW_Msk¾ÚPTRIM_FLAG_OVERFLOW_PosÚPTRIM_FLAG_OVERFLOW_MskÚPTRIM_CALC_CNT_Pos&ÚPTRIM_CALC_CNT_Msk-ÚPTRIM_CALC_WATI_CNT_PosÚPTRIM_CALC_WATI_CNT_MskÚ8
<unnamed>QÚ 
"MODE
Ú 
"DINOFFuÚ 
"DOUTóÚ 
"DATMSKgÚ 
"PINJÚ 
"DBENÚ 
"INTTYPEüÚ 
"INTEN¯Ú 
"INTSRCXÚGPIO_TÚ8
<unnamed>QÚ 
"DBCTL¹Ú
GPIO_DB_T(ÚPGP_MODE_MODE0_PosIÚPGP_MODE_MODE0_MskPÚPGP_MODE_MODE1_PosHÚPGP_MODE_MODE1_MskOÚPGP_MODE_MODE2_PosGÚPGP_MODE_MODE2_MskNÚPGP_MODE_MODE3_PosFÚPGP_MODE_MODE3_MskMÚPGP_MODE_MODE4_PosEÚPGP_MODE_MODE4_MskLÚPGP_MODE_MODE5_PosDÚPGP_MODE_MODE5_MskKÚPGP_DINOFF_DINOFF0_PosÚPGP_DINOFF_DINOFF0_Msk&ÚPGP_DINOFF_DINOFF1_PosÚPGP_DINOFF_DINOFF1_Msk%ÚPGP_DINOFF_DINOFF2_PosÚPGP_DINOFF_DINOFF2_Msk$ÚPGP_DINOFF_DINOFF3_PosÚPGP_DINOFF_DINOFF3_Msk#ÚPGP_DINOFF_DINOFF4_PosÚPGP_DINOFF_DINOFF4_Msk"ÚPGP_DINOFF_DINOFF5_PosÚPGP_DINOFF_DINOFF5_Msk!ÚPGP_DINOFF_DINOFF6_PosÚPGP_DINOFF_DINOFF6_Msk ÚPGP_DINOFF_DINOFF7_PosÚPGP_DINOFF_DINOFF7_MskÚPGP_DOUT_DOUT0_PosÚPGP_DOUT_DOUT0_Msk"ÚPGP_DOUT_DOUT1_PosÚPGP_DOUT_DOUT1_Msk!ÚPGP_DOUT_DOUT2_PosÚPGP_DOUT_DOUT2_Msk ÚPGP_DOUT_DOUT3_PosÚPGP_DOUT_DOUT3_MskÚPGP_DOUT_DOUT4_PosÚPGP_DOUT_DOUT4_MskÚPGP_DOUT_DOUT5_PosÚPGP_DOUT_DOUT5_MskÚPGP_DOUT_DOUT6_PosÚPGP_DOUT_DOUT6_MskÚPGP_DOUT_DOUT7_PosÚPGP_DOUT_DOUT7_MskÚPGP_DATMSK_DATMSK0_PosÚPGP_DATMSK_DATMSK0_Msk
ÚPGP_DATMSK_DATMSK1_PosÚPGP_DATMSK_DATMSK1_Msk    ÚPGP_DATMSK_DATMSK2_PosÚPGP_DATMSK_DATMSK2_MskÚPGP_DATMSK_DATMSK3_PosÚPGP_DATMSK_DATMSK3_MskÚPGP_DATMSK_DATMSK4_PosÿÚPGP_DATMSK_DATMSK4_MskÚPGP_DATMSK_DATMSK5_PosþÚPGP_DATMSK_DATMSK5_MskÚPGP_DATMSK_DATMSK6_PosýÚPGP_DATMSK_DATMSK6_MskÚPGP_DATMSK_DATMSK7_PosüÚPGP_DATMSK_DATMSK7_MskÚPGP_PIN_PIN0_PosÉÚPGP_PIN_PIN0_MskÐÚPGP_PIN_PIN1_PosÈÚPGP_PIN_PIN1_MskÏÚPGP_PIN_PIN2_PosÇÚPGP_PIN_PIN2_MskÎÚPGP_PIN_PIN3_PosÆÚPGP_PIN_PIN3_MskÍÚPGP_PIN_PIN4_PosÅÚPGP_PIN_PIN4_MskÌÚPGP_PIN_PIN5_PosÄÚPGP_PIN_PIN5_MskËÚPGP_PIN_PIN6_PosÃÚPGP_PIN_PIN6_MskÊÚPGP_PIN_PIN7_PosÂÚPGP_PIN_PIN7_MskÉÚPGP_DBEN_DBEN0_PosaÚPGP_DBEN_DBEN0_MskhÚPGP_DBEN_DBEN1_Pos`ÚPGP_DBEN_DBEN1_MskgÚPGP_DBEN_DBEN2_Pos_ÚPGP_DBEN_DBEN2_MskfÚPGP_DBEN_DBEN3_Pos^ÚPGP_DBEN_DBEN3_MskeÚPGP_DBEN_DBEN4_Pos]ÚPGP_DBEN_DBEN4_MskdÚPGP_DBEN_DBEN5_Pos\ÚPGP_DBEN_DBEN5_MskcÚPGP_DBEN_DBEN6_Pos[ÚPGP_DBEN_DBEN6_MskbÚPGP_DBEN_DBEN7_PosZÚPGP_DBEN_DBEN7_MskaÚPGP_INTTYPE_TYPE0_PosÚPGP_INTTYPE_TYPE0_Msk%ÚPGP_INTTYPE_TYPE1_PosÚPGP_INTTYPE_TYPE1_Msk$ÚPGP_INTTYPE_TYPE2_PosÚPGP_INTTYPE_TYPE2_Msk#ÚPGP_INTTYPE_TYPE3_PosÚPGP_INTTYPE_TYPE3_Msk"ÚPGP_INTTYPE_TYPE4_PosÚPGP_INTTYPE_TYPE4_Msk!ÚPGP_INTTYPE_TYPE5_PosÚPGP_INTTYPE_TYPE5_Msk ÚPGP_INTTYPE_TYPE6_PosÚPGP_INTTYPE_TYPE6_MskÚPGP_INTTYPE_TYPE7_PosÚPGP_INTTYPE_TYPE7_MskÚPGP_INTEN_FLIEN0_Pos£ÚPGP_INTEN_FLIEN0_MskªÚPGP_INTEN_FLIEN1_Pos¢ÚPGP_INTEN_FLIEN1_Msk©ÚPGP_INTEN_FLIEN2_Pos¡ÚPGP_INTEN_FLIEN2_Msk¨ÚPGP_INTEN_FLIEN3_Pos ÚPGP_INTEN_FLIEN3_Msk§ÚPGP_INTEN_FLIEN4_PosÚPGP_INTEN_FLIEN4_Msk¦ÚPGP_INTEN_FLIEN5_PosÚPGP_INTEN_FLIEN5_Msk¥ÚPGP_INTEN_FLIEN6_PosÚPGP_INTEN_FLIEN6_Msk¤ÚPGP_INTEN_FLIEN7_PosÚPGP_INTEN_FLIEN7_Msk£ÚPGP_INTEN_RHIEN0_PosÚPGP_INTEN_RHIEN0_Msk¢ÚPGP_INTEN_RHIEN1_PosÚPGP_INTEN_RHIEN1_Msk¡ÚPGP_INTEN_RHIEN2_PosÚPGP_INTEN_RHIEN2_Msk ÚPGP_INTEN_RHIEN3_PosÚPGP_INTEN_RHIEN3_MskÚPGP_INTEN_RHIEN4_PosÚPGP_INTEN_RHIEN4_MskÚPGP_INTEN_RHIEN5_PosÚPGP_INTEN_RHIEN5_MskÚPGP_INTEN_RHIEN6_PosÚPGP_INTEN_RHIEN6_MskÚPGP_INTEN_RHIEN7_PosÚPGP_INTEN_RHIEN7_MskÚPGP_INTSRC_INTSRC0_PosåÚPGP_INTSRC_INTSRC0_MskìÚPGP_INTSRC_INTSRC1_PosäÚPGP_INTSRC_INTSRC1_MskëÚPGP_INTSRC_INTSRC2_PosãÚPGP_INTSRC_INTSRC2_MskêÚPGP_INTSRC_INTSRC3_PosâÚPGP_INTSRC_INTSRC3_MskéÚPGP_INTSRC_INTSRC4_PosáÚPGP_INTSRC_INTSRC4_MskèÚPGP_INTSRC_INTSRC5_PosàÚPGP_INTSRC_INTSRC5_MskçÚPGP_INTSRC_INTSRC6_PosßÚPGP_INTSRC_INTSRC6_MskæÚPGP_INTSRC_INTSRC7_PosÞÚPGP_INTSRC_INTSRC7_MskåÚPGP_INTSRC_INTSRC8_PosÝÚPGP_INTSRC_INTSRC8_MskäÚPGP_INTSRC_INTSRC9_PosÜÚPGP_INTSRC_INTSRC9_MskãÚPGP_INTSRC_INTSRC10_Pos²ÚPGP_INTSRC_INTSRC10_Msk¹ÚPGP_INTSRC_INTSRC11_Pos±ÚPGP_INTSRC_INTSRC11_Msk¸ÚPGP_INTSRC_INTSRC12_Pos°ÚPGP_INTSRC_INTSRC12_Msk·ÚPGP_INTSRC_INTSRC13_Pos¯ÚPGP_INTSRC_INTSRC13_Msk¶ÚPGP_INTSRC_INTSRC14_Pos®ÚPGP_INTSRC_INTSRC14_MskµÚPGP_INTSRC_INTSRC15_PosÚPGP_INTSRC_INTSRC15_Msk´ÚPGP_DBCTL_DBCLKSEL_PosÚPGP_DBCTL_DBCLKSEL_MskÚPGP_DBCTL_DBCLKSRC_Pos
ÚPGP_DBCTL_DBCLKSRC_MskÚPGP_DBCTL_ICLKON_PosÚPGP_DBCTL_ICLKON_MskÚ8
<unnamed>QÚ 
"ÁDATÚ <"Á
RESERVED0
Ú 
"ÁCTL Ú 
"ÁCHENÐÚ 
"ÁCMP0ÞÚ 
"ÁCMP1ÝÚ 
"ÁSTATUSÚ <"Á
RESERVED1Ú 
"ÁTRGDLYÚ 
"ÁEXTSMPT³Ú 
"ÁSEQCTLÚ 
"ÁSEQDAT1õÚ 
"ÁSEQDAT2ôÚ 
"ÁCTL2ÙÚ <"Á
RESERVED2Ú 
"ÁBV_CTLÚADC_T|ÚPADC_DAT_RESULT_PosØÚPADC_DAT_RESULT_MskßÚPADC_DAT_OV_PosÚPADC_DAT_OV_Msk!ÚPADC_DAT_VALID_PosIÚPADC_DAT_VALID_MskPÚPADC_CTL_ADCEN_PosTÚPADC_CTL_ADCEN_Msk[ÚPADC_CTL_ADCIEN_Pos    ÚPADC_CTL_ADCIEN_MskÚPADC_CTL_HWTRGSEL_Pos9ÚPADC_CTL_HWTRGSEL_Msk@ÚPADC_CTL_HWTRGCOND_Pos÷ÚPADC_CTL_HWTRGCOND_MskþÚPADC_CTL_HWTRGEN_PosÚPADC_CTL_HWTRGEN_MskÚPADC_CTL_FIFO_EN_PosÚPADC_CTL_FIFO_EN_MskÚ$PADC_CTL_FIFO_THRE_STATE_PosÚ$PADC_CTL_FIFO_THRE_STATE_MskÚPADC_CTL_SWTRG_PosÚPADC_CTL_SWTRG_MskÚ"PADC_CTL_LEFT_SHIFT_EN_Pos¥Ú"PADC_CTL_LEFT_SHIFT_EN_Msk¬Ú PADC_CTL_SUB_BIAS_EN_PosIÚ PADC_CTL_SUB_BIAS_EN_MskPÚPADC_CTL_BIAS_VALUE_PosªÚPADC_CTL_BIAS_VALUE_Msk±ÚPADC_CHEN_CHEN0_Pos$ÚPADC_CHEN_CHEN0_Msk+ÚPADC_CHEN_CHEN1_Pos#ÚPADC_CHEN_CHEN1_Msk*ÚPADC_CHEN_CHEN2_Pos"ÚPADC_CHEN_CHEN2_Msk)ÚPADC_CHEN_CHEN3_Pos!ÚPADC_CHEN_CHEN3_Msk(ÚPADC_CHEN_CHEN4_Pos ÚPADC_CHEN_CHEN4_Msk'ÚPADC_CHEN_CHEN5_PosÚPADC_CHEN_CHEN5_Msk&ÚPADC_CHEN_CHEN6_PosÚPADC_CHEN_CHEN6_Msk%ÚPADC_CHEN_CHEN7_PosÚPADC_CHEN_CHEN7_Msk$ÚPADC_CHEN_CHEN8_VBG_PosÖÚPADC_CHEN_CHEN8_VBG_MskÝÚPADC_CHEN_CH9_TMP_PosZÚPADC_CHEN_CH9_TMP_MskaÚ PADC_CHEN_CH10_VDD_4_Pos¬Ú PADC_CHEN_CH10_VDD_4_Msk³Ú PADC_CHEN_CH11_VBG_2_Pos¬Ú PADC_CHEN_CH11_VBG_2_Msk³ÚPADC_CHEN_ALL_Msk¤ÚPADC_CMP0_ADCMPEN_PosÚPADC_CMP0_ADCMPEN_MskÚPADC_CMP0_ADCMPIE_PosÚPADC_CMP0_ADCMPIE_MskÚPADC_CMP0_CMPCOND_PosxÚPADC_CMP0_CMPCOND_MskÚPADC_CMP0_CMPCH_PosÚPADC_CMP0_CMPCH_MskÚPADC_CMP0_CMPMCNT_PosjÚPADC_CMP0_CMPMCNT_MskqÚPADC_CMP0_CMPDAT_PosÅÚPADC_CMP0_CMPDAT_MskÌÚPADC_CMP1_ADCMPEN_PosÚPADC_CMP1_ADCMPEN_MskÚPADC_CMP1_ADCMPIE_PosÚPADC_CMP1_ADCMPIE_MskÚPADC_CMP1_CMPCOND_PoswÚPADC_CMP1_CMPCOND_Msk~ÚPADC_CMP1_CMPCH_PosÚPADC_CMP1_CMPCH_MskÚPADC_CMP1_CMPMCNT_PosiÚPADC_CMP1_CMPMCNT_MskpÚPADC_CMP1_CMPDAT_PosÄÚPADC_CMP1_CMPDAT_MskËÚPADC_STATUS_ADIF_PosÚPADC_STATUS_ADIF_MskÚ PADC_STATUS_ADCMPIF0_Pos~Ú PADC_STATUS_ADCMPIF0_MskÚ PADC_STATUS_ADCMPIF1_Pos}Ú PADC_STATUS_ADCMPIF1_MskÚPADC_STATUS_BUSY_PosgÚPADC_STATUS_BUSY_MsknÚPADC_STATUS_CHANNEL_Pos«ÚPADC_STATUS_CHANNEL_Msk²ÚPADC_STATUS_VALID_Pos8ÚPADC_STATUS_VALID_Msk?Ú#PADC_STATUS_INTMSK_FULL_Pos4Ú#PADC_STATUS_INTMSK_FULL_Msk;Ú$PADC_STATUS_INTMSK_EMPTY_PosÖÚ$PADC_STATUS_INTMSK_EMPTY_MskÝÚ#PADC_STATUS_INTMSK_OVER_Pos+Ú#PADC_STATUS_INTMSK_OVER_Msk2Ú#PADC_STATUS_INTMSK_HALF_PosLÚ#PADC_STATUS_INTMSK_HALF_MskSÚ!PADC_STATUS_INTMSK_AD_PosæÚ!PADC_STATUS_INTMSK_AD_MskíÚ#PADC_STATUS_INTMSK_CMP0_PosWÚ#PADC_STATUS_INTMSK_CMP0_Msk^Ú#PADC_STATUS_INTMSK_CMP1_PosVÚ#PADC_STATUS_INTMSK_CMP1_Msk]ÚPADC_STATUS_OV_Pos    ÚPADC_STATUS_OV_MskÚ&PADC_STATUS_ONE_CH_CLR_SEL_PosGÚ&PADC_STATUS_ONE_CH_CLR_SEL_MskNÚ#PADC_STATUS_ONE_CH_FLAG_PosWÚ#PADC_STATUS_ONE_CH_FLAG_Msk^Ú#PADC_STATUS_INTFLG_FULL_PosFÚ#PADC_STATUS_INTFLG_FULL_MskMÚ$PADC_STATUS_INTFLG_EMPTY_PosèÚ$PADC_STATUS_INTFLG_EMPTY_MskïÚ#PADC_STATUS_INTFLG_OVER_Pos=Ú#PADC_STATUS_INTFLG_OVER_MskDÚ#PADC_STATUS_INTFLG_HALF_Pos^Ú#PADC_STATUS_INTFLG_HALF_MskeÚPADC_STATUS_ADCF_PosÚPADC_STATUS_ADCF_Msk£ÚPADC_STATUS_ADCMPF0_PosÉÚPADC_STATUS_ADCMPF0_MskÐÚPADC_STATUS_ADCMPF1_PosÈÚPADC_STATUS_ADCMPF1_MskÏÚ!PADC_STATUS_FLAG_FULL_PosôÚ!PADC_STATUS_FLAG_FULL_MskûÚ"PADC_STATUS_FLAG_EMPTY_PosÚ"PADC_STATUS_FLAG_EMPTY_MskÚ!PADC_STATUS_FLAG_OVER_PosëÚ!PADC_STATUS_FLAG_OVER_MskòÚ!PADC_STATUS_FLAG_HALF_PosÚ!PADC_STATUS_FLAG_HALF_MskÚPADC_TRGDLY_DELAY_PosGÚPADC_TRGDLY_DELAY_MskNÚ PADC_EXTSMPT_EXTSMPT_PosÚ PADC_EXTSMPT_EXTSMPT_Msk#ÚPADC_SEQCTL_SEQEN_PosDÚPADC_SEQCTL_SEQEN_MskKÚPADC_SEQCTL_SEQTYPE_PosÚPADC_SEQCTL_SEQTYPE_MskÚPADC_SEQCTL_MODESEL_Pos³ÚPADC_SEQCTL_MODESEL_MskºÚ PADC_SEQCTL_DELAY_EN_PosYÚ PADC_SEQCTL_DELAY_EN_Msk`ÚPADC_SEQCTL_TRG_SEL_PosÚPADC_SEQCTL_TRG_SEL_MskÚ!PADC_SEQCTL_ONE_CH_EN_PosúÚ!PADC_SEQCTL_ONE_CH_EN_MskÚPADC_SEQCTL_TRG1CTL_Pos»ÚPADC_SEQCTL_TRG1CTL_MskÂÚPADC_SEQCTL_TRG2CTL_PosºÚPADC_SEQCTL_TRG2CTL_MskÁÚPADC_SEQDAT1_RESULT_Pos¶ÚPADC_SEQDAT1_RESULT_Msk½ÚPADC_SEQDAT1_OV_PosøÚPADC_SEQDAT1_OV_MskÿÚPADC_SEQDAT1_VALID_Pos'ÚPADC_SEQDAT1_VALID_Msk.ÚPADC_SEQDAT2_RESULT_PosµÚPADC_SEQDAT2_RESULT_Msk¼ÚPADC_SEQDAT2_OV_Pos÷ÚPADC_SEQDAT2_OV_MskþÚPADC_SEQDAT2_VALID_Pos&ÚPADC_SEQDAT2_VALID_Msk-ÚPADC_CTL2_TESTMODE_PosÚPADC_CTL2_TESTMODE_MskÚPADC_CTL2_SHSEL_PosüÚPADC_CTL2_SHSEL_MskÚPADC_CTL2_DMA_EN_PosµÚPADC_CTL2_DMA_EN_Msk¼ÚPADC_CTL2_CLKDIV_Pos¼ÚPADC_CTL2_CLKDIV_MskÃÚPADC_SEL_VREF_Pos}ÚPADC_SEL_VREF_MskÚPADC_CTL2_CMPCTL_Pos¶ÚPADC_CTL2_CMPCTL_Msk½ÚPADC_CTL2_DRVCTL_PosªÚPADC_CTL2_DRVCTL_Msk±Ú8
<unnamed>QÚ 
"P0_MFPcÚ 
"P1_MFPbÚ 
"P2_MFPaÚ 
"P3_MFP`Ú <"0RESVÚ 
"REGLCTLÚ 
"STATUSAÚ 
"CTRL0ÂÚ 
"CTRL1ÁÚSYS_TEÚPSYS_P0_MFP_MFP_Pos´ÚPSYS_P0_MFP_MFP_Msk»ÚPSYS_P0_MFP_ALT0_PosÚPSYS_P0_MFP_ALT0_MskÚPSYS_P0_MFP_ALT1_PosÚPSYS_P0_MFP_ALT1_MskÚPSYS_P0_MFP_ALT2_PosÚPSYS_P0_MFP_ALT2_MskÚPSYS_P0_MFP_ALT3_PosÚPSYS_P0_MFP_ALT3_MskÚPSYS_P0_MFP_ALT4_PosÚPSYS_P0_MFP_ALT4_MskÚPSYS_P0_MFP_ALT5_PosÚPSYS_P0_MFP_ALT5_MskÚPSYS_P0_MFP_ALT6_Pos~ÚPSYS_P0_MFP_ALT6_MskÚPSYS_P0_MFP_ALT7_Pos}ÚPSYS_P0_MFP_ALT7_MskÚPSYS_P1_MFP_MFP_Pos³ÚPSYS_P1_MFP_MFP_MskºÚPSYS_P1_MFP_ALT0_PosÚPSYS_P1_MFP_ALT0_MskÚPSYS_P1_MFP_ALT1_PosÚPSYS_P1_MFP_ALT1_MskÚPSYS_P1_MFP_ALT2_PosÚPSYS_P1_MFP_ALT2_MskÚPSYS_P1_MFP_ALT3_PosÚPSYS_P1_MFP_ALT3_MskÚPSYS_P1_MFP_ALT4_PosÚPSYS_P1_MFP_ALT4_MskÚPSYS_P1_MFP_ALT5_Pos~ÚPSYS_P1_MFP_ALT5_MskÚPSYS_P1_MFP_ALT6_Pos}ÚPSYS_P1_MFP_ALT6_MskÚPSYS_P1_MFP_ALT7_Pos|ÚPSYS_P1_MFP_ALT7_MskÚPSYS_P1_MFP_TYPE_PosRÚPSYS_P1_MFP_TYPE_MskYÚPSYS_P1_MFP_P12EXT_PosìÚPSYS_P1_MFP_P12EXT_MskóÚPSYS_P1_MFP_P13EXT_PosëÚPSYS_P1_MFP_P13EXT_MskòÚPSYS_P1_MFP_P14EXT_PosêÚPSYS_P1_MFP_P14EXT_MskñÚPSYS_P2_MFP_ALT0_PosÚPSYS_P2_MFP_ALT0_MskÚPSYS_P2_MFP_ALT1_PosÚPSYS_P2_MFP_ALT1_MskÚPSYS_P2_MFP_ALT2_PosÚPSYS_P2_MFP_ALT2_MskÚPSYS_P2_MFP_ALT3_PosÚPSYS_P2_MFP_ALT3_MskÚPSYS_P2_MFP_ALT4_Pos~ÚPSYS_P2_MFP_ALT4_MskÚPSYS_P2_MFP_ALT5_Pos}ÚPSYS_P2_MFP_ALT5_MskÚPSYS_P2_MFP_ALT6_Pos|ÚPSYS_P2_MFP_ALT6_MskÚPSYS_P2_MFP_ALT7_Pos{ÚPSYS_P2_MFP_ALT7_MskÚPSYS_P3_MFP_MFP_Pos±ÚPSYS_P3_MFP_MFP_Msk¸ÚPSYS_P3_MFP_ALT0_PosÚPSYS_P3_MFP_ALT0_MskÚPSYS_P3_MFP_ALT1_PosÚPSYS_P3_MFP_ALT1_MskÚPSYS_P3_MFP_ALT2_PosÚPSYS_P3_MFP_ALT2_MskÚPSYS_P3_MFP_ALT4_Pos}ÚPSYS_P3_MFP_ALT4_MskÚPSYS_P3_MFP_ALT5_Pos|ÚPSYS_P3_MFP_ALT5_MskÚPSYS_P3_MFP_ALT6_Pos{ÚPSYS_P3_MFP_ALT6_MskÚPSYS_P3_MFP_P32EXT_PosèÚPSYS_P3_MFP_P32EXT_MskïÚPSYS_P4_MFP_MFP_Pos°ÚPSYS_P4_MFP_MFP_Msk·ÚPSYS_P4_MFP_ALT6_PoszÚPSYS_P4_MFP_ALT6_MskÚPSYS_P4_MFP_ALT7_PosyÚPSYS_P4_MFP_ALT7_MskÚPSYS_P5_MFP_MFP_Pos¯ÚPSYS_P5_MFP_MFP_Msk¶ÚPSYS_P5_MFP_ALT0_PosÚPSYS_P5_MFP_ALT0_MskÚPSYS_P5_MFP_ALT1_Pos~ÚPSYS_P5_MFP_ALT1_MskÚPSYS_P5_MFP_ALT2_Pos}ÚPSYS_P5_MFP_ALT2_MskÚPSYS_P5_MFP_ALT3_Pos|ÚPSYS_P5_MFP_ALT3_MskÚPSYS_P5_MFP_ALT4_Pos{ÚPSYS_P5_MFP_ALT4_MskÚPSYS_P5_MFP_ALT5_PoszÚPSYS_P5_MFP_ALT5_MskÚPSYS_P5_MFP_ALT6_PosyÚPSYS_P5_MFP_ALT6_MskÚPSYS_P5_MFP_ALT7_PosxÚPSYS_P5_MFP_ALT7_MskÚPSYS_P5_MFP_P50EXT_PosæÚPSYS_P5_MFP_P50EXT_MskíÚPSYS_P5_MFP_P51EXT_PosåÚPSYS_P5_MFP_P51EXT_MskìÚ PSYS_REGLCTL_REGLCTL_Pos5Ú PSYS_REGLCTL_REGLCTL_Msk<Ú8
<unnamed>QÚ 
"ùRSTSTS½Ú 
"ùIPRST0îÚ 
"ùIPRST1íÚ 
"ù
BODCTL_3V
Ú 
"ùBLDBCTL_3VÉÚ 
"ùCLK_TOP_CTRL_3VöÚ 
"ùRCL_CTRL_3VIÚ 
"ù    RCH_CTRL;Ú 
"ùXTL_CTRL_3V2Ú 
"ù    XTH_CTRL$Ú 
"ù
DPLL_CTRLêÚ 
"ù AHB_CLK_CTRLÚ 
"ùAPB1_CLK_CTRLÑÚ 
"ùAPB2_CLK_CTRLÐÚ 
"ùMEAS_CLK_CTRL¯ÚCLK_TjÚPCLK_RSTSTS_CHIPRF_PosÉÚPCLK_RSTSTS_CHIPRF_MskÐÚPCLK_RSTSTS_PINRF_PosÚPCLK_RSTSTS_PINRF_MskÚPCLK_RSTSTS_WDTRF_PosÚPCLK_RSTSTS_WDTRF_MskÚPCLK_RSTSTS_LVRRF_PosûÚPCLK_RSTSTS_LVRRF_MskÚPCLK_RSTSTS_BODRF_PosÚPCLK_RSTSTS_BODRF_Msk!ÚPCLK_RSTSTS_SYSRF_PosðÚPCLK_RSTSTS_SYSRF_Msk÷ÚPCLK_RSTSTS_PORRF_PosþÚPCLK_RSTSTS_PORRF_MskÚPCLK_RSTSTS_CPURF_PosÚPCLK_RSTSTS_CPURF_MskÚPCLK_IPRST0_CHIPRST_PosÚPCLK_IPRST0_CHIPRST_MskÚPCLK_IPRST0_CPURST_PosÕÚPCLK_IPRST0_CPURST_MskÜÚPCLK_IPRST0_DMARST_PosëÚPCLK_IPRST0_DMARST_MskòÚPCLK_IPRST0_RFRST_Pos'ÚPCLK_IPRST0_RFRST_Msk.Ú PCLK_IPRST0_EFUSERST_PosAÚ PCLK_IPRST0_EFUSERST_MskHÚPCLK_IPRST0_USBRST_PosÓÚPCLK_IPRST0_USBRST_MskÚÚ#PCLK_IPRST0_MDMSTDBYRST_PosOÚ#PCLK_IPRST0_MDMSTDBYRST_MskVÚPCLK_IPRST0_MDMRST_PosßÚPCLK_IPRST0_MDMRST_MskæÚ#PCLK_IPRST0_CHIPSCOPEEN_Pos{Ú#PCLK_IPRST0_CHIPSCOPEEN_MskÚPCLK_IPRST0_FTORRST_PosÚPCLK_IPRST0_FTORRST_MskÚPCLK_IPRST1_I2C0RST_PosÌÚPCLK_IPRST1_I2C0RST_MskÓÚPCLK_IPRST1_SPI0RST_PosÚPCLK_IPRST1_SPI0RST_Msk¥ÚPCLK_IPRST1_SPI1RST_PosÚPCLK_IPRST1_SPI1RST_Msk¤Ú PCLK_IPRST1_UART0RST_PosLÚ PCLK_IPRST1_UART0RST_MskSÚ PCLK_IPRST1_UART1RST_PosKÚ PCLK_IPRST1_UART1RST_MskRÚPCLK_IPRST1_PWM0RST_PosÚPCLK_IPRST1_PWM0RST_MskÚPCLK_IPRST1_ADCRST_PosôÚPCLK_IPRST1_ADCRST_MskûÚPCLK_IPRST1_WDTRST_PosÍÚPCLK_IPRST1_WDTRST_MskÔÚPCLK_IPRST1_WWDTRST_PostÚPCLK_IPRST1_WWDTRST_Msk{ÚPCLK_IPRST1_TMR0RST_PosÚPCLK_IPRST1_TMR0RST_MskÚPCLK_IPRST1_TMR1RST_PosÚPCLK_IPRST1_TMR1RST_MskÚPCLK_IPRST1_TMR2RST_PosÚPCLK_IPRST1_TMR2RST_MskÚPCLK_IPRST1_GPIORST_PosÚPCLK_IPRST1_GPIORST_MskÚPCLK_IPRST1_TRIMRST_Pos~ÚPCLK_IPRST1_TRIMRST_MskÚ#PCLK_BODCTL_BODRSTEN_Pos_3vMÚ#PCLK_BODCTL_BODRSTEN_Msk_3vTÚPCLK_BODCTL_BODIF_Pos^ÚPCLK_BODCTL_BODIF_MskeÚPCLK_BODCTL_BODOUT_PosóÚPCLK_BODCTL_BODOUT_MskúÚ PCLK_BODCTL_LVREN_Pos_3v-Ú PCLK_BODCTL_LVREN_Msk_3v4Ú PCLK_BODCTL_BODEN_Pos_3vLÚ PCLK_BODCTL_BODEN_Msk_3vSÚ!PCLK_BODCTL_BODSEL_Pos_3vùÚ!PCLK_BODCTL_BODSEL_Msk_3vÚ#PCLK_BODCTL_LVR_TEST_Pos_3vÚ#PCLK_BODCTL_LVR_TEST_Msk_3v"Ú#PCLK_BODCTL_BOD_TEST_Pos_3v:Ú#PCLK_BODCTL_BOD_TEST_Msk_3vAÚ%PCLK_BLDBCTL_LVRDB_SEL_Pos_3v®Ú%PCLK_BLDBCTL_LVRDB_SEL_Msk_3vµÚ%PCLK_BLDBCTL_BODDB_SEL_Pos_3vÍÚ%PCLK_BLDBCTL_BODDB_SEL_Msk_3vÔÚ'PCLK_TOPCTL_RSICV_SYSCNT_EN_PosÔÚ'PCLK_TOPCTL_RSICV_SYSCNT_EN_MskÛÚ#PCLK_TOPCTL_SYS_CLK_SEL_PosÚ#PCLK_TOPCTL_SYS_CLK_SEL_Msk$Ú&PCLK_TOPCTL_32K_CLK_SEL_Pos_3v^Ú&PCLK_TOPCTL_32K_CLK_SEL_Msk_3veÚPCLK_TOPCTL_AHB_DIV_PosÚPCLK_TOPCTL_AHB_DIV_MskÚ PCLK_TOPCTL_APB1_DIV_PosXÚ PCLK_TOPCTL_APB1_DIV_Msk_Ú PCLK_TOPCTL_APB2_DIV_PosWÚ PCLK_TOPCTL_APB2_DIV_Msk^Ú#PCLK_RCLCTL_RC32K_EN_Pos_3vkÚ#PCLK_RCLCTL_RC32K_EN_Msk_3vrÚ$PCLK_RCLCTL_RC32K_TST_EN_PosÚ$PCLK_RCLCTL_RC32K_TST_EN_MskÚ"PCLK_RCLCTL_CLK_SEL_Pos_3vÚ"PCLK_RCLCTL_CLK_SEL_Msk_3vÚ'PCLK_RCLCTL_RC32K_COARSE_Pos_3v9Ú'PCLK_RCLCTL_RC32K_COARSE_Msk_3v@Ú%PCLK_RCLCTL_RC32K_FINE_Pos_3vØÚ%PCLK_RCLCTL_RC32K_FINE_Msk_3vßÚ&PCLK_RCLCTL_RC32K_DELAY_Pos_3vÚ&PCLK_RCLCTL_RC32K_DELAY_Msk_3vÚPCLK_RCLCTL_STABLE_PosùÚPCLK_RCLCTL_STABLE_MskÚPCLK_RCHCTL_RCH_EN_PoséÚPCLK_RCHCTL_RCH_EN_MskðÚ"PCLK_RCHCTL_RCH_TST_EN_PosÚ"PCLK_RCHCTL_RCH_TST_EN_MskÚPCLK_RCHCTL_CLK_SEL_PosÚPCLK_RCHCTL_CLK_SEL_Msk ÚPCLK_RCHCTL_BIAS_PosÚPCLK_RCHCTL_BIAS_Msk¤Ú PCLK_RCHCTL_RCH_FREQ_PosJÚ PCLK_RCHCTL_RCH_FREQ_MskQÚPCLK_RCHCTL_DELAY_PosKÚPCLK_RCHCTL_DELAY_MskRÚPCLK_RCHCTL_STABLE_PosýÚPCLK_RCHCTL_STABLE_MskÚ!PCLK_XTLCTL_XTL_EN_Pos_3v¥Ú!PCLK_XTLCTL_XTL_EN_Msk_3v¬Ú"PCLK_XTLCTL_XTL_TST_EN_PosQÚ"PCLK_XTLCTL_XTL_TST_EN_MskXÚ$PCLK_XTLCTL_CORE_BIAS_Pos_3vâÚ$PCLK_XTLCTL_CORE_BIAS_Msk_3véÚ#PCLK_XTLCTL_XTL_TRIM_Pos_3vøÚ#PCLK_XTLCTL_XTL_TRIM_Msk_3vÿÚ%PCLK_XTLCTL_XTL_CAP_EN_Pos_3vjÚ%PCLK_XTLCTL_XTL_CAP_EN_Msk_3vqÚ PCLK_XTLCTL_DELAY_Pos_3v"Ú PCLK_XTLCTL_DELAY_Msk_3v)ÚPCLK_XTLCTL_STABLE_PosâÚPCLK_XTLCTL_STABLE_MskéÚPCLK_XTHCTL_XTH_EN_Pos»ÚPCLK_XTHCTL_XTH_EN_MskÂÚ"PCLK_XTHCTL_XTH_TST_EN_PosYÚ"PCLK_XTHCTL_XTH_TST_EN_Msk`Ú"PCLK_XTHCTL_START_FAST_Pos~Ú"PCLK_XTHCTL_START_FAST_MskÚ#PCLK_XTHCTL_DEGLITCH_EN_PosaÚ#PCLK_XTHCTL_DEGLITCH_EN_MskhÚ"PCLK_XTHCTL_XO_CAP_SEL_Pos|Ú"PCLK_XTHCTL_XO_CAP_SEL_MskÚPCLK_XTHCTL_DELAY_Pos4ÚPCLK_XTHCTL_DELAY_Msk;ÚPCLK_XTHCTL_STABLE_PosæÚPCLK_XTHCTL_STABLE_MskíÚ PCLK_DPLLCTL_DPLL_EN_PosGÚ PCLK_DPLLCTL_DPLL_EN_MskNÚ$PCLK_DPLLCTL_DPLL_TST_EN_PosåÚ$PCLK_DPLLCTL_DPLL_TST_EN_MskìÚ!PCLK_DPLLCTL_FREQ_OUT_PosÞÚ!PCLK_DPLLCTL_FREQ_OUT_MskåÚ!PCLK_DPLLCTL_RCLK_SEL_PosôÚ!PCLK_DPLLCTL_RCLK_SEL_MskûÚ!PCLK_DPLLCTL_ICP_BIAS_Pos    Ú!PCLK_DPLLCTL_ICP_BIAS_MskÚ!PCLK_DPLLCTL_ICP_CTRL_PosóÚ!PCLK_DPLLCTL_ICP_CTRL_MskúÚ"PCLK_DPLLCTL_KVCO_CTRL_PosÚ"PCLK_DPLLCTL_KVCO_CTRL_Msk¡Ú&PCLK_DPLLCTL_VCO_FREQ_TRIM_PosIÚ&PCLK_DPLLCTL_VCO_FREQ_TRIM_MskPÚ PCLK_DPLLCTL_DIV_SEL_Pos?Ú PCLK_DPLLCTL_DIV_SEL_MskFÚPCLK_DPLLCTL_DELAY_PosúÚPCLK_DPLLCTL_DELAY_MskÚPCLK_DPLLCTL_STABLE_Pos¬ÚPCLK_DPLLCTL_STABLE_Msk³ÚPCLK_AHBCLK_DMAEN_PospÚPCLK_AHBCLK_DMAEN_MskwÚPCLK_AHBCLK_GPIOEN_PosÚPCLK_AHBCLK_GPIOEN_MskÚ"PCLK_AHBCLK_SYSTICK_EN_Pos¯Ú"PCLK_AHBCLK_SYSTICK_EN_Msk¶ÚPCLK_AHBCLK_APB1EN_Pos<ÚPCLK_AHBCLK_APB1EN_MskCÚPCLK_AHBCLK_APB2EN_Pos;ÚPCLK_AHBCLK_APB2EN_MskBÚPCLK_AHBCLK_AHBEN_PoswÚPCLK_AHBCLK_AHBEN_Msk~Ú!PCLK_AHBCLK_BLE32M_EN_PosVÚ!PCLK_AHBCLK_BLE32M_EN_Msk]Ú!PCLK_AHBCLK_BLE32K_EN_PosXÚ!PCLK_AHBCLK_BLE32K_EN_Msk_Ú"PCLK_AHBCLK_BLE32M_SEL_PosÚ"PCLK_AHBCLK_BLE32M_SEL_Msk
Ú"PCLK_AHBCLK_ROM_CLK_EN_Pos²Ú"PCLK_AHBCLK_ROM_CLK_EN_Msk¹Ú$PCLK_AHBCLK_EFUSE_CLK_EN_Pos$Ú$PCLK_AHBCLK_EFUSE_CLK_EN_Msk+Ú&PCLK_AHBCLK_USB_AHB_CLK_EN_PosÚ&PCLK_AHBCLK_USB_AHB_CLK_EN_MskÚ&PCLK_AHBCLK_USB_48M_CLK_EN_PosÚ&PCLK_AHBCLK_USB_48M_CLK_EN_MskÚ%PCLK_AHBCLK_SPI_FLASH_DIV_PosÊÚ%PCLK_AHBCLK_SPI_FLASH_DIV_MskÑÚ)P!CLK_AHBCLK_SPI_FLASH_CLK_SEL_PosÚ)P!CLK_AHBCLK_SPI_FLASH_CLK_SEL_MskÚ'PCLK_AHBCLK_DPLL_CLK_TST_EN_PosÚ'PCLK_AHBCLK_DPLL_CLK_TST_EN_MskÚ(P CLK_AHBCLK_SPI_CLK_SEL_FPGA_PosÚÚ(P CLK_AHBCLK_SPI_CLK_SEL_FPGA_MskáÚ#PCLK_APB1CLK_WDTSRC_SEL_PosvÚ#PCLK_APB1CLK_WDTSRC_SEL_Msk}Ú$PCLK_APB1CLK_WWDTSRC_SEL_PosÚ$PCLK_APB1CLK_WWDTSRC_SEL_Msk$Ú$PCLK_APB1CLK_TMR0SRC_SEL_Pos@Ú$PCLK_APB1CLK_TMR0SRC_SEL_MskGÚ&PCLK_APB1CLK_PWM01_CLK_SEL_Pos¹Ú&PCLK_APB1CLK_PWM01_CLK_SEL_MskÀÚ&PCLK_APB1CLK_PWM23_CLK_SEL_PosµÚ&PCLK_APB1CLK_PWM23_CLK_SEL_Msk¼Ú&PCLK_APB1CLK_PWM45_CLK_SEL_Pos±Ú&PCLK_APB1CLK_PWM45_CLK_SEL_Msk¸Ú&PCLK_APB1CLK_PWM67_CLK_SEL_PosÚ&PCLK_APB1CLK_PWM67_CLK_SEL_Msk´Ú$PCLK_APB1CLK_ADC_CLK_SEL_PosJÚ$PCLK_APB1CLK_ADC_CLK_SEL_MskQÚ$PCLK_APB2CLK_TMR1SRC_SEL_Pos>Ú$PCLK_APB2CLK_TMR1SRC_SEL_MskEÚ$PCLK_APB2CLK_TMR2SRC_SEL_Pos=Ú$PCLK_APB2CLK_TMR2SRC_SEL_MskDÚ$PCLK_MEASCLK_TRIM_CLK_EN_PosÚ$PCLK_MEASCLK_TRIM_CLK_EN_MskÚ%PCLK_MEASCLK_TRIM_CLK_SEL_Pos²Ú%PCLK_MEASCLK_TRIM_CLK_SEL_Msk¹Ú%PCLK_MEASCLK_TRIM_CLK_DIV_Pos³Ú%PCLK_MEASCLK_TRIM_CLK_DIV_MskºÚ%PCLK_MEASCLK_XTL_QUICK_EN_Pos¤Ú%PCLK_MEASCLK_XTL_QUICK_EN_Msk«Ú PCLK_MEASCLK_XTH_DIV_Pos>Ú PCLK_MEASCLK_XTH_DIV_MskEÚ8
<unnamed>QÚ 
"øCTLÒÚ 
"øALTCTLëÚWDT_TUÚPWDT_CTL_RSTCNT_Pos¨ÚPWDT_CTL_RSTCNT_Msk¯ÚPWDT_CTL_RSTEN_PosüÚPWDT_CTL_RSTEN_MskÚPWDT_CTL_RSTF_PosKÚPWDT_CTL_RSTF_MskRÚPWDT_CTL_IF_PosÿÚPWDT_CTL_IF_MskÚPWDT_CTL_WKEN_PosUÚPWDT_CTL_WKEN_Msk\ÚPWDT_CTL_WKF_Pos¤ÚPWDT_CTL_WKF_Msk«ÚPWDT_CTL_INTEN_Pos
ÚPWDT_CTL_INTEN_MskÚPWDT_CTL_WDTEN_PosÚPWDT_CTL_WDTEN_Msk ÚPWDT_CTL_TOUTSEL_PosTÚPWDT_CTL_TOUTSEL_Msk[Ú#PWDT_CTL_RST_REGION_SEL_PosÚ#PWDT_CTL_RST_REGION_SEL_MskÚPWDT_CTL_TOF_Pos£ÚPWDT_CTL_TOF_MskªÚPWDT_CTL_ICEDEBUG_PosJÚPWDT_CTL_ICEDEBUG_MskQÚPWDT_ALTCTL_RSTDSEL_Pos|ÚPWDT_ALTCTL_RSTDSEL_MskÚ8
<unnamed>QÚ 
"RLDCNTIÚ 
"CTL3Ú 
"STATUS,Ú 
"CNT1ÚWWDT_TüÚPWWDT_RLDCNT_RLDCNT_Pos|ÚPWWDT_RLDCNT_RLDCNT_MskÚPWWDT_CTL_WWDTEN_PosTÚPWWDT_CTL_WWDTEN_Msk[ÚPWWDT_CTL_INTEN_Pos±ÚPWWDT_CTL_INTEN_Msk¸ÚPWWDT_CTL_PSCSEL_PoscÚPWWDT_CTL_PSCSEL_MskjÚPWWDT_CTL_CMPDAT_PostÚPWWDT_CTL_CMPDAT_Msk{ÚPWWDT_CTL_ICEDEBUG_PosñÚPWWDT_CTL_ICEDEBUG_MskøÚPWWDT_STATUS_WWDTIF_PosQÚPWWDT_STATUS_WWDTIF_MskXÚPWWDT_STATUS_WWDTRF_PosHÚPWWDT_STATUS_WWDTRF_MskOÚPWWDT_STATUS_WWDTF_PosÚPWWDT_STATUS_WWDTF_Msk£ÚPWWDT_CNT_CNTDAT_PosmÚPWWDT_CNT_CNTDAT_MsktÚ8
<unnamed>QÚ 
"°CLKPSC6Ú 
"°CLKDIV9Ú 
"°CTLÚ 
"°PERIOD0Ú 
"°PERIOD1Ú 
"°PERIOD2ÿÚ 
"°PERIOD3þÚ 
"°PERIOD4ýÚ 
"°PERIOD5üÚ 
"°PERIOD6ûÚ 
"°PERIOD7úÚ 
"°CMPDAT0Ú 
"°CMPDAT1
Ú 
"°CMPDAT2    Ú 
"°CMPDAT3Ú 
"°CMPDAT4Ú 
"°CMPDAT5Ú 
"°CMPDAT6Ú 
"°CMPDAT7Ú 
"°CTL2åÚ 
"°FLAGàÚ 
"°INTENzÚ 
"°INTSTSÚ 
"°POENÈÚ <"°
RESERVED0.Ú 
"°DTCTL}Ú 
"°    ADCTCTL0ÃÚ 
"°    ADCTCTL1ÂÚ 
"°    ADCTSTS0¬Ú 
"°    ADCTSTS1«Ú <"°
RESERVED1!Ú 
"°PCACTL?ÚPWM_TPÚ PPWM_CLKPSC_CLKPSC01_PosyÚ PPWM_CLKPSC_CLKPSC01_MskÚ PPWM_CLKPSC_CLKPSC23_PosuÚ PPWM_CLKPSC_CLKPSC23_Msk|Ú PPWM_CLKPSC_CLKPSC45_PosqÚ PPWM_CLKPSC_CLKPSC45_MskxÚ PPWM_CLKPSC_CLKPSC67_PosmÚ PPWM_CLKPSC_CLKPSC67_MsktÚPPWM_CLKDIV_CLKDIV0_Pos²ÚPPWM_CLKDIV_CLKDIV0_Msk¹ÚPPWM_CLKDIV_CLKDIV1_Pos±ÚPPWM_CLKDIV_CLKDIV1_Msk¸ÚPPWM_CLKDIV_CLKDIV2_Pos°ÚPPWM_CLKDIV_CLKDIV2_Msk·ÚPPWM_CLKDIV_CLKDIV3_Pos¯ÚPPWM_CLKDIV_CLKDIV3_Msk¶ÚPPWM_CLKDIV_CLKDIV4_Pos®ÚPPWM_CLKDIV_CLKDIV4_MskµÚPPWM_CLKDIV_CLKDIV5_PosÚPPWM_CLKDIV_CLKDIV5_Msk´ÚPPWM_CLKDIV_CLKDIV6_Pos¬ÚPPWM_CLKDIV_CLKDIV6_Msk³ÚPPWM_CLKDIV_CLKDIV7_Pos«ÚPPWM_CLKDIV_CLKDIV7_Msk²ÚPPWM_CTL_CNTEN0_PosÙÚPPWM_CTL_CNTEN0_MskàÚPPWM_CTL_PINV0_PosÚPPWM_CTL_PINV0_MskÚPPWM_CTL_CNTMODE0_PosCÚPPWM_CTL_CNTMODE0_MskJÚPPWM_CTL_CNTEN1_PosØÚPPWM_CTL_CNTEN1_MskßÚPPWM_CTL_HCUPDT_Pos¹ÚPPWM_CTL_HCUPDT_MskÀÚPPWM_CTL_PINV1_PosÚPPWM_CTL_PINV1_MskÚPPWM_CTL_CNTMODE1_PosBÚPPWM_CTL_CNTMODE1_MskIÚPPWM_CTL_CNTEN2_Pos×ÚPPWM_CTL_CNTEN2_MskÞÚPPWM_CTL_PINV2_PosÚPPWM_CTL_PINV2_MskÚPPWM_CTL_CNTMODE2_PosAÚPPWM_CTL_CNTMODE2_MskHÚPPWM_CTL_CNTEN3_PosÖÚPPWM_CTL_CNTEN3_MskÝÚPPWM_CTL_PINV3_PosÚPPWM_CTL_PINV3_MskÚPPWM_CTL_CNTMODE3_Pos@ÚPPWM_CTL_CNTMODE3_MskGÚPPWM_CTL_CNTEN4_PosÕÚPPWM_CTL_CNTEN4_MskÜÚPPWM_CTL_PINV4_PosÚPPWM_CTL_PINV4_MskÚPPWM_CTL_CNTMODE4_Pos?ÚPPWM_CTL_CNTMODE4_MskFÚPPWM_CTL_CNTEN5_PosÔÚPPWM_CTL_CNTEN5_MskÛÚPPWM_CTL_ASYMEN_Pos´ÚPPWM_CTL_ASYMEN_Msk»ÚPPWM_CTL_PINV5_PosÚPPWM_CTL_PINV5_MskÚPPWM_CTL_CNTMODE5_Pos>ÚPPWM_CTL_CNTMODE5_MskEÚPPWM_CTL_CNTEN6_PosÓÚPPWM_CTL_CNTEN6_MskÚÚPPWM_CTL_PINV6_PosÚPPWM_CTL_PINV6_MskÚPPWM_CTL_CNTMODE6_Pos=ÚPPWM_CTL_CNTMODE6_MskDÚPPWM_CTL_CNTEN7_PosÒÚPPWM_CTL_CNTEN7_MskÙÚPPWM_CTL_PINV7_PosÚPPWM_CTL_PINV7_MskÚPPWM_CTL_CNTMODE7_Pos<ÚPPWM_CTL_CNTMODE7_MskCÚ PPWM_PERIOD0_PERIOD0_PostÚ PPWM_PERIOD0_PERIOD0_Msk{Ú PPWM_PERIOD0_PERIOD1_PossÚ PPWM_PERIOD0_PERIOD1_MskzÚ PPWM_PERIOD0_PERIOD2_PosrÚ PPWM_PERIOD0_PERIOD2_MskyÚ PPWM_PERIOD0_PERIOD3_PosqÚ PPWM_PERIOD0_PERIOD3_MskxÚ PPWM_PERIOD0_PERIOD4_PospÚ PPWM_PERIOD0_PERIOD4_MskwÚ PPWM_PERIOD0_PERIOD5_PosoÚ PPWM_PERIOD0_PERIOD5_MskvÚ PPWM_PERIOD0_PERIOD6_PosnÚ PPWM_PERIOD0_PERIOD6_MskuÚ PPWM_PERIOD0_PERIOD7_PosmÚ PPWM_PERIOD0_PERIOD7_MsktÚ PPWM_PERIOD1_PERIOD0_PossÚ PPWM_PERIOD1_PERIOD0_MskzÚ PPWM_PERIOD1_PERIOD1_PosrÚ PPWM_PERIOD1_PERIOD1_MskyÚ PPWM_PERIOD1_PERIOD2_PosqÚ PPWM_PERIOD1_PERIOD2_MskxÚ PPWM_PERIOD1_PERIOD3_PospÚ PPWM_PERIOD1_PERIOD3_MskwÚ PPWM_PERIOD1_PERIOD4_PosoÚ PPWM_PERIOD1_PERIOD4_MskvÚ PPWM_PERIOD1_PERIOD5_PosnÚ PPWM_PERIOD1_PERIOD5_MskuÚ PPWM_PERIOD1_PERIOD6_PosmÚ PPWM_PERIOD1_PERIOD6_MsktÚ PPWM_PERIOD1_PERIOD7_PoslÚ PPWM_PERIOD1_PERIOD7_MsksÚ PPWM_PERIOD2_PERIOD0_PosrÚ PPWM_PERIOD2_PERIOD0_MskyÚ PPWM_PERIOD2_PERIOD1_PosqÚ PPWM_PERIOD2_PERIOD1_MskxÚ PPWM_PERIOD2_PERIOD2_PospÚ PPWM_PERIOD2_PERIOD2_MskwÚ PPWM_PERIOD2_PERIOD3_PosoÚ PPWM_PERIOD2_PERIOD3_MskvÚ PPWM_PERIOD2_PERIOD4_PosnÚ PPWM_PERIOD2_PERIOD4_MskuÚ PPWM_PERIOD2_PERIOD5_PosmÚ PPWM_PERIOD2_PERIOD5_MsktÚ PPWM_PERIOD2_PERIOD6_PoslÚ PPWM_PERIOD2_PERIOD6_MsksÚ PPWM_PERIOD2_PERIOD7_PoskÚ PPWM_PERIOD2_PERIOD7_MskrÚ PPWM_PERIOD3_PERIOD0_PosqÚ PPWM_PERIOD3_PERIOD0_MskxÚ PPWM_PERIOD3_PERIOD1_PospÚ PPWM_PERIOD3_PERIOD1_MskwÚ PPWM_PERIOD3_PERIOD2_PosoÚ PPWM_PERIOD3_PERIOD2_MskvÚ PPWM_PERIOD3_PERIOD3_PosnÚ PPWM_PERIOD3_PERIOD3_MskuÚ PPWM_PERIOD3_PERIOD4_PosmÚ PPWM_PERIOD3_PERIOD4_MsktÚ PPWM_PERIOD3_PERIOD5_PoslÚ PPWM_PERIOD3_PERIOD5_MsksÚ PPWM_PERIOD3_PERIOD6_PoskÚ PPWM_PERIOD3_PERIOD6_MskrÚ PPWM_PERIOD3_PERIOD7_PosjÚ PPWM_PERIOD3_PERIOD7_MskqÚ PPWM_PERIOD4_PERIOD0_PospÚ PPWM_PERIOD4_PERIOD0_MskwÚ PPWM_PERIOD4_PERIOD1_PosoÚ PPWM_PERIOD4_PERIOD1_MskvÚ PPWM_PERIOD4_PERIOD2_PosnÚ PPWM_PERIOD4_PERIOD2_MskuÚ PPWM_PERIOD4_PERIOD3_PosmÚ PPWM_PERIOD4_PERIOD3_MsktÚ PPWM_PERIOD4_PERIOD4_PoslÚ PPWM_PERIOD4_PERIOD4_MsksÚ PPWM_PERIOD4_PERIOD5_PoskÚ PPWM_PERIOD4_PERIOD5_MskrÚ PPWM_PERIOD4_PERIOD6_PosjÚ PPWM_PERIOD4_PERIOD6_MskqÚ PPWM_PERIOD4_PERIOD7_PosiÚ PPWM_PERIOD4_PERIOD7_MskpÚ PPWM_PERIOD5_PERIOD0_PosoÚ PPWM_PERIOD5_PERIOD0_MskvÚ PPWM_PERIOD5_PERIOD1_PosnÚ PPWM_PERIOD5_PERIOD1_MskuÚ PPWM_PERIOD5_PERIOD2_PosmÚ PPWM_PERIOD5_PERIOD2_MsktÚ PPWM_PERIOD5_PERIOD3_PoslÚ PPWM_PERIOD5_PERIOD3_MsksÚ PPWM_PERIOD5_PERIOD4_PoskÚ PPWM_PERIOD5_PERIOD4_MskrÚ PPWM_PERIOD5_PERIOD5_PosjÚ PPWM_PERIOD5_PERIOD5_MskqÚ PPWM_PERIOD5_PERIOD6_PosiÚ PPWM_PERIOD5_PERIOD6_MskpÚ PPWM_PERIOD5_PERIOD7_PoshÚ PPWM_PERIOD5_PERIOD7_MskoÚ PPWM_PERIOD6_PERIOD0_PosnÚ PPWM_PERIOD6_PERIOD0_MskuÚ PPWM_PERIOD6_PERIOD1_PosmÚ PPWM_PERIOD6_PERIOD1_MsktÚ PPWM_PERIOD6_PERIOD2_PoslÚ PPWM_PERIOD6_PERIOD2_MsksÚ PPWM_PERIOD6_PERIOD3_PoskÚ PPWM_PERIOD6_PERIOD3_MskrÚ PPWM_PERIOD6_PERIOD4_PosjÚ PPWM_PERIOD6_PERIOD4_MskqÚ PPWM_PERIOD6_PERIOD5_PosiÚ PPWM_PERIOD6_PERIOD5_MskpÚ PPWM_PERIOD6_PERIOD6_PoshÚ PPWM_PERIOD6_PERIOD6_MskoÚ PPWM_PERIOD6_PERIOD7_PosgÚ PPWM_PERIOD6_PERIOD7_MsknÚ PPWM_PERIOD7_PERIOD0_PosmÚ PPWM_PERIOD7_PERIOD0_MsktÚ PPWM_PERIOD7_PERIOD1_PoslÚ PPWM_PERIOD7_PERIOD1_MsksÚ PPWM_PERIOD7_PERIOD2_PoskÚ PPWM_PERIOD7_PERIOD2_MskrÚ PPWM_PERIOD7_PERIOD3_PosjÚ PPWM_PERIOD7_PERIOD3_MskqÚ PPWM_PERIOD7_PERIOD4_PosiÚ PPWM_PERIOD7_PERIOD4_MskpÚ PPWM_PERIOD7_PERIOD5_PoshÚ PPWM_PERIOD7_PERIOD5_MskoÚ PPWM_PERIOD7_PERIOD6_PosgÚ PPWM_PERIOD7_PERIOD6_MsknÚ PPWM_PERIOD7_PERIOD7_PosfÚ PPWM_PERIOD7_PERIOD7_MskmÚPPWM_CMPDAT0_CMP0_PosgÚPPWM_CMPDAT0_CMP0_MsknÚPPWM_CMPDAT0_CMP1_PosfÚPPWM_CMPDAT0_CMP1_MskmÚPPWM_CMPDAT0_CMP2_PoseÚPPWM_CMPDAT0_CMP2_MsklÚPPWM_CMPDAT0_CMP3_PosdÚPPWM_CMPDAT0_CMP3_MskkÚPPWM_CMPDAT0_CMP4_PoscÚPPWM_CMPDAT0_CMP4_MskjÚPPWM_CMPDAT0_CMP5_PosbÚPPWM_CMPDAT0_CMP5_MskiÚPPWM_CMPDAT0_CMP6_PosaÚPPWM_CMPDAT0_CMP6_MskhÚPPWM_CMPDAT0_CMP7_Pos`ÚPPWM_CMPDAT0_CMP7_MskgÚPPWM_CMPDAT0_CMPD0_Pos!ÚPPWM_CMPDAT0_CMPD0_Msk(ÚPPWM_CMPDAT0_CMPD1_Pos ÚPPWM_CMPDAT0_CMPD1_Msk'ÚPPWM_CMPDAT0_CMPD2_PosÚPPWM_CMPDAT0_CMPD2_Msk&ÚPPWM_CMPDAT0_CMPD3_PosÚPPWM_CMPDAT0_CMPD3_Msk%ÚPPWM_CMPDAT0_CMPD4_PosÚPPWM_CMPDAT0_CMPD4_Msk$ÚPPWM_CMPDAT0_CMPD5_PosÚPPWM_CMPDAT0_CMPD5_Msk#ÚPPWM_CMPDAT0_CMPD6_PosÚPPWM_CMPDAT0_CMPD6_Msk"ÚPPWM_CMPDAT0_CMPD7_PosÚPPWM_CMPDAT0_CMPD7_Msk!ÚPPWM_CMPDAT1_CMP0_PosfÚPPWM_CMPDAT1_CMP0_MskmÚPPWM_CMPDAT1_CMP1_PoseÚPPWM_CMPDAT1_CMP1_MsklÚPPWM_CMPDAT1_CMP2_PosdÚPPWM_CMPDAT1_CMP2_MskkÚPPWM_CMPDAT1_CMP3_PoscÚPPWM_CMPDAT1_CMP3_MskjÚPPWM_CMPDAT1_CMP4_PosbÚPPWM_CMPDAT1_CMP4_MskiÚPPWM_CMPDAT1_CMP5_PosaÚPPWM_CMPDAT1_CMP5_MskhÚPPWM_CMPDAT1_CMP6_Pos`ÚPPWM_CMPDAT1_CMP6_MskgÚPPWM_CMPDAT1_CMP7_Pos_ÚPPWM_CMPDAT1_CMP7_MskfÚPPWM_CMPDAT1_CMPD0_Pos ÚPPWM_CMPDAT1_CMPD0_Msk'ÚPPWM_CMPDAT1_CMPD1_PosÚPPWM_CMPDAT1_CMPD1_Msk&ÚPPWM_CMPDAT1_CMPD2_PosÚPPWM_CMPDAT1_CMPD2_Msk%ÚPPWM_CMPDAT1_CMPD3_PosÚPPWM_CMPDAT1_CMPD3_Msk$ÚPPWM_CMPDAT1_CMPD4_PosÚPPWM_CMPDAT1_CMPD4_Msk#ÚPPWM_CMPDAT1_CMPD5_PosÚPPWM_CMPDAT1_CMPD5_Msk"ÚPPWM_CMPDAT1_CMPD6_PosÚPPWM_CMPDAT1_CMPD6_Msk!ÚPPWM_CMPDAT1_CMPD7_PosÚPPWM_CMPDAT1_CMPD7_Msk ÚPPWM_CMPDAT2_CMP0_PoseÚPPWM_CMPDAT2_CMP0_MsklÚPPWM_CMPDAT2_CMP1_PosdÚPPWM_CMPDAT2_CMP1_MskkÚPPWM_CMPDAT2_CMP2_PoscÚPPWM_CMPDAT2_CMP2_MskjÚPPWM_CMPDAT2_CMP3_PosbÚPPWM_CMPDAT2_CMP3_MskiÚPPWM_CMPDAT2_CMP4_PosaÚPPWM_CMPDAT2_CMP4_MskhÚPPWM_CMPDAT2_CMP5_Pos`ÚPPWM_CMPDAT2_CMP5_MskgÚPPWM_CMPDAT2_CMP6_Pos_ÚPPWM_CMPDAT2_CMP6_MskfÚPPWM_CMPDAT2_CMP7_Pos^ÚPPWM_CMPDAT2_CMP7_MskeÚPPWM_CMPDAT2_CMPD0_PosÚPPWM_CMPDAT2_CMPD0_Msk&ÚPPWM_CMPDAT2_CMPD1_PosÚPPWM_CMPDAT2_CMPD1_Msk%ÚPPWM_CMPDAT2_CMPD2_PosÚPPWM_CMPDAT2_CMPD2_Msk$ÚPPWM_CMPDAT2_CMPD3_PosÚPPWM_CMPDAT2_CMPD3_Msk#ÚPPWM_CMPDAT2_CMPD4_PosÚPPWM_CMPDAT2_CMPD4_Msk"ÚPPWM_CMPDAT2_CMPD5_PosÚPPWM_CMPDAT2_CMPD5_Msk!ÚPPWM_CMPDAT2_CMPD6_PosÚPPWM_CMPDAT2_CMPD6_Msk ÚPPWM_CMPDAT2_CMPD7_PosÚPPWM_CMPDAT2_CMPD7_MskÚPPWM_CMPDAT3_CMP0_PosdÚPPWM_CMPDAT3_CMP0_MskkÚPPWM_CMPDAT3_CMP1_PoscÚPPWM_CMPDAT3_CMP1_MskjÚPPWM_CMPDAT3_CMP2_PosbÚPPWM_CMPDAT3_CMP2_MskiÚPPWM_CMPDAT3_CMP3_PosaÚPPWM_CMPDAT3_CMP3_MskhÚPPWM_CMPDAT3_CMP4_Pos`ÚPPWM_CMPDAT3_CMP4_MskgÚPPWM_CMPDAT3_CMP5_Pos_ÚPPWM_CMPDAT3_CMP5_MskfÚPPWM_CMPDAT3_CMP6_Pos^ÚPPWM_CMPDAT3_CMP6_MskeÚPPWM_CMPDAT3_CMP7_Pos]ÚPPWM_CMPDAT3_CMP7_MskdÚPPWM_CMPDAT3_CMPD0_PosÚPPWM_CMPDAT3_CMPD0_Msk%ÚPPWM_CMPDAT3_CMPD1_PosÚPPWM_CMPDAT3_CMPD1_Msk$ÚPPWM_CMPDAT3_CMPD2_PosÚPPWM_CMPDAT3_CMPD2_Msk#ÚPPWM_CMPDAT3_CMPD3_PosÚPPWM_CMPDAT3_CMPD3_Msk"ÚPPWM_CMPDAT3_CMPD4_PosÚPPWM_CMPDAT3_CMPD4_Msk!ÚPPWM_CMPDAT3_CMPD5_PosÚPPWM_CMPDAT3_CMPD5_Msk ÚPPWM_CMPDAT3_CMPD6_PosÚPPWM_CMPDAT3_CMPD6_MskÚPPWM_CMPDAT3_CMPD7_PosÚPPWM_CMPDAT3_CMPD7_MskÚPPWM_CMPDAT4_CMP0_PoscÚPPWM_CMPDAT4_CMP0_MskjÚPPWM_CMPDAT4_CMP1_PosbÚPPWM_CMPDAT4_CMP1_MskiÚPPWM_CMPDAT4_CMP2_PosaÚPPWM_CMPDAT4_CMP2_MskhÚPPWM_CMPDAT4_CMP3_Pos`ÚPPWM_CMPDAT4_CMP3_MskgÚPPWM_CMPDAT4_CMP4_Pos_ÚPPWM_CMPDAT4_CMP4_MskfÚPPWM_CMPDAT4_CMP5_Pos^ÚPPWM_CMPDAT4_CMP5_MskeÚPPWM_CMPDAT4_CMP6_Pos]ÚPPWM_CMPDAT4_CMP6_MskdÚPPWM_CMPDAT4_CMP7_Pos\ÚPPWM_CMPDAT4_CMP7_MskcÚPPWM_CMPDAT4_CMPD0_PosÚPPWM_CMPDAT4_CMPD0_Msk$ÚPPWM_CMPDAT4_CMPD1_PosÚPPWM_CMPDAT4_CMPD1_Msk#ÚPPWM_CMPDAT4_CMPD2_PosÚPPWM_CMPDAT4_CMPD2_Msk"ÚPPWM_CMPDAT4_CMPD3_PosÚPPWM_CMPDAT4_CMPD3_Msk!ÚPPWM_CMPDAT4_CMPD4_PosÚPPWM_CMPDAT4_CMPD4_Msk ÚPPWM_CMPDAT4_CMPD5_PosÚPPWM_CMPDAT4_CMPD5_MskÚPPWM_CMPDAT4_CMPD6_PosÚPPWM_CMPDAT4_CMPD6_MskÚPPWM_CMPDAT4_CMPD7_PosÚPPWM_CMPDAT4_CMPD7_MskÚPPWM_CMPDAT5_CMP0_PosbÚPPWM_CMPDAT5_CMP0_MskiÚPPWM_CMPDAT5_CMP1_PosaÚPPWM_CMPDAT5_CMP1_MskhÚPPWM_CMPDAT5_CMP2_Pos`ÚPPWM_CMPDAT5_CMP2_MskgÚPPWM_CMPDAT5_CMP3_Pos_ÚPPWM_CMPDAT5_CMP3_MskfÚPPWM_CMPDAT5_CMP4_Pos^ÚPPWM_CMPDAT5_CMP4_MskeÚPPWM_CMPDAT5_CMP5_Pos]ÚPPWM_CMPDAT5_CMP5_MskdÚPPWM_CMPDAT5_CMP6_Pos\ÚPPWM_CMPDAT5_CMP6_MskcÚPPWM_CMPDAT5_CMP7_Pos[ÚPPWM_CMPDAT5_CMP7_MskbÚPPWM_CMPDAT5_CMPD0_PosÚPPWM_CMPDAT5_CMPD0_Msk#ÚPPWM_CMPDAT5_CMPD1_PosÚPPWM_CMPDAT5_CMPD1_Msk"ÚPPWM_CMPDAT5_CMPD2_PosÚPPWM_CMPDAT5_CMPD2_Msk!ÚPPWM_CMPDAT5_CMPD3_PosÚPPWM_CMPDAT5_CMPD3_Msk ÚPPWM_CMPDAT5_CMPD4_PosÚPPWM_CMPDAT5_CMPD4_MskÚPPWM_CMPDAT5_CMPD5_PosÚPPWM_CMPDAT5_CMPD5_MskÚPPWM_CMPDAT5_CMPD6_PosÚPPWM_CMPDAT5_CMPD6_MskÚPPWM_CMPDAT5_CMPD7_PosÚPPWM_CMPDAT5_CMPD7_MskÚPPWM_CMPDAT6_CMP0_PosaÚPPWM_CMPDAT6_CMP0_MskhÚPPWM_CMPDAT6_CMP1_Pos`ÚPPWM_CMPDAT6_CMP1_MskgÚPPWM_CMPDAT6_CMP2_Pos_ÚPPWM_CMPDAT6_CMP2_MskfÚPPWM_CMPDAT6_CMP3_Pos^ÚPPWM_CMPDAT6_CMP3_MskeÚPPWM_CMPDAT6_CMP4_Pos]ÚPPWM_CMPDAT6_CMP4_MskdÚPPWM_CMPDAT6_CMP5_Pos\ÚPPWM_CMPDAT6_CMP5_MskcÚPPWM_CMPDAT6_CMP6_Pos[ÚPPWM_CMPDAT6_CMP6_MskbÚPPWM_CMPDAT6_CMP7_PosZÚPPWM_CMPDAT6_CMP7_M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<unnamed>QÚ 
"²    X_FL_CTL^Ú "²
X_FL_TRIGÚ "²X_FL_CONFIGÚ <"²X_FL_WDtÚ 
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"²X_FL_REMAP_ADDRDÚ 
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"² X_FL_IRQ_CTLÚ 
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<unnamed>QÚ <"ÁX_FL_BUFFERÁÚFLCTL_W_BUFF_TÚ"PFLCTL_CTL_BYTES_NUM_R_PoskÚ"PFLCTL_CTL_BYTES_NUM_R_MskrÚ"PFLCTL_CTL_BYTES_NUM_W_PosfÚ"PFLCTL_CTL_BYTES_NUM_W_MskmÚPFLCTL_TRIG_TRG_PosÀÚPFLCTL_TRIG_TRG_MskÇÚ#PFLCTL_CONFIG_FLASH_CAP_Pos|Ú#PFLCTL_CONFIG_FLASH_CAP_MskÚ'PFLCTL_CONFIG_TX_ADDR_TRANS_PosÚ'PFLCTL_CONFIG_TX_ADDR_TRANS_MskÚ!PFLCTL_CONFIG_INFO_EN_PosÚ!PFLCTL_CONFIG_INFO_EN_Msk
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<unnamed>QÚ 
"X_CACHE_ENÚ 
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<unnamed>QÚ 
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"DRÚ  
"SRzÚ 
"CPSRãÚ 
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"MIS4Ú 
"ICR?Ú 
"DMACR²ÚSPI_TXÚPSPI_CR0_SCR_PosÅÚPSPI_CR0_SCR_MskÌÚPSPI_CR0_SPH_PosÂÚPSPI_CR0_SPH_MskÉÚPSPI_CR0_SPO_Pos»ÚPSPI_CR0_SPO_MskÂÚPSPI_CR0_FRF_PosÏÚPSPI_CR0_FRF_MskÖÚPSPI_CR0_DSS_PosÃÚPSPI_CR0_DSS_MskÊÚ!PSPI_CR1_SPI_MODE_SEL_PosçÚ!PSPI_CR1_SPI_MODE_SEL_MskîÚPSPI_CR1_CMD_DAT_EN_Pos ÚPSPI_CR1_CMD_DAT_EN_Msk§Ú!PSPI_CR1_CMD_DAT_CTRL_PosúÚ!PSPI_CR1_CMD_DAT_CTRL_MskÚPSPI_CR1_WR_CTRL_PosgÚPSPI_CR1_WR_CTRL_MsknÚPSPI_CR1_RX_LSB_EN_PosÄÚPSPI_CR1_RX_LSB_EN_MskËÚPSPI_CR1_TX_LSB_EN_PosÂÚPSPI_CR1_TX_LSB_EN_MskÉÚPSPI_CR1_SOD_PosÆÚPSPI_CR1_SOD_MskÍÚPSPI_CR1_MS_PosÚPSPI_CR1_MS_MskÚPSPI_CR1_SSE_PosÁÚPSPI_CR1_SSE_MskÈÚPSPI_CR1_LBM_PosÑÚPSPI_CR1_LBM_MskØÚPSPI_DR_PosEÚPSPI_DR_MskLÚPSPI_SR_BUSY_PosÚPSPI_SR_BUSY_MskÚPSPI_SR_RFF_PosñÚPSPI_SR_RFF_MskøÚPSPI_SR_RFNE_Pos¢ÚPSPI_SR_RFNE_Msk©ÚPSPI_SR_TFNF_PosÚPSPI_SR_TFNF_Msk¦ÚPSPI_SR_TFE_PosðÚPSPI_SR_TFE_Msk÷ÚPSPI_CPSR_DIV_PosUÚPSPI_CPSR_DIV_Msk\ÚPSPI_IMSC_TXIM_PosÚPSPI_IMSC_TXIM_MskÚPSPI_IMSC_RXIM_PosÚPSPI_IMSC_RXIM_Msk    ÚPSPI_IMSC_RTIM_PosÚPSPI_IMSC_RTIM_Msk ÚPSPI_RIS_TXIS_Pos:ÚPSPI_RIS_TXIS_MskAÚPSPI_RIS_RXIS_Pos<ÚPSPI_RIS_RXIS_MskCÚPSPI_RIS_RTIS_Pos@ÚPSPI_RIS_RTIS_MskGÚPSPI_RIS_RORIS_PosñÚPSPI_RIS_RORIS_MskøÚPSPI_MIS_TXMIS_PosðÚPSPI_MIS_TXMIS_Msk÷ÚPSPI_MIS_RXMIS_PosòÚPSPI_MIS_RXMIS_MskùÚPSPI_MIS_RTMIS_PosöÚPSPI_MIS_RTMIS_MskýÚPSPI_MIS_RORMIS_Pos§ÚPSPI_MIS_RORMIS_Msk®ÚPSPI_ICR_RTICR_PosÚPSPI_ICR_RTICR_MskÚPSPI_ICR_RORICR_Pos½ÚPSPI_ICR_RORICR_MskÄÚPSPI_DMACR_TDMAE_PosÚPSPI_DMACR_TDMAE_MskÚPSPI_DMACR_RDMAE_PosÚPSPI_DMACR_RDMAE_Msk¡Ú8
<unnamed>QÚ 
"ÝRBR_THR_DLLIÚ 
"ÝIER_DLH¨Ú 
"ÝIIR_FCR¡Ú 
"ÝLCRæÚ 
"ÝMCRåÚ 
"ÝLSRÖÚ 
"ÝMSRÕÚ 
"ÝSCRßÚ 
"ÝLPDLLKÚ 
"ÝLPDLHOÚ <"TÝ
RESERVED0©Ú 
"ÝUSRÍÚ 
"ÝTFLáÚ 
"ÝRFLãÚ <"Ý
RESERVED1àÚ 
"ÝHTXÓÚ 
"ÝDMASA]Ú <"Ý
RESERVED2çÚ 
"ÝDLFñÚ 
"ÝRARâÚ 
"ÝTARàÚ 
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<unnamed>QÚ8
<unnamed>QÚ 
"Þ!SAR_L/Ú 
"Þ!SAR_H3Ú 
"Þ!DAR_L>Ú 
"Þ!DAR_HBÚ <"Þ!
RESERVED0òÚ 
"Þ!CTL_L2Ú 
"Þ!CTL_H6Ú <" Þ!
RESERVED1ÙÚ 
"Þ!CFG_LEÚ 
"Þ!CFG_HIÚ 
"Þ!SGR_L)Ú 
"Þ!SGR_H-Ú 
"Þ!DSR_L,Ú 
"Þ!DSR_H0Ú <"ÀÝ!CHHÚ 
"Ý!
RAW_TFR_LÙÚ 
"Ý!
RAW_TFR_HÝÚ 
"Ý!RAW_BLOCK_LVÚ 
"Ý!RAW_BLOCK_HZÚ 
"Ý!RAW_SRCTRAN_L Ú 
"Ý!RAW_SRCTRAN_H¤Ú 
"Ý!RAW_DSTTRAN_LÚ 
"Ý!RAW_DSTTRAN_H¡Ú 
"Ý!
RAW_ERR_LÜÚ 
"Ý!
RAW_ERR_HàÚ 
"Ý! STATUS_TFR_LÙÚ 
"Ý! STATUS_TFR_HÝÚ 
"Ý!STATUS_BLOCK_LVÚ 
"Ý!STATUS_BLOCK_HZÚ 
"Ý!STATUS_SRCTRAN_L Ú 
"Ý!STATUS_SRCTRAN_H¤Ú 
"Ý!STATUS_DSTTRAN_LÚ 
"Ý!STATUS_DSTTRAN_H¡Ú 
"Ý! STATUS_ERR_LÜÚ 
"Ý! STATUS_ERR_HàÚ 
"Ý!
MSK_TFR_LØÚ 
"Ý!
MSK_TFR_HÜÚ 
"Ý!MSK_BLOCK_LUÚ 
"Ý!MSK_BLOCK_HYÚ 
"Ý!MSK_SRCTRAN_LÚ 
"Ý!MSK_SRCTRAN_H£Ú 
"Ý!MSK_DSTTRAN_LÚ 
"Ý!MSK_DSTTRAN_H Ú 
"Ý!
MSK_ERR_LÛÚ 
"Ý!
MSK_ERR_HßÚ 
"Ý!CLEAR_TFR_LXÚ 
"Ý!CLEAR_TFR_H\Ú 
"Ý!CLEAR_BLOCK_LÕÚ 
"Ý!CLEAR_BLOCK_HÙÚ 
"Ý!CLEAR_SRCTRAN_LÚ 
"Ý!CLEAR_SRCTRAN_H#Ú 
"Ý!CLEAR_DSTTRAN_LÚ 
"Ý!CLEAR_DSTTRAN_H Ú 
"Ý!CLEAR_ERR_L[Ú 
"Ý!CLEAR_ERR_H_Ú 
"Ý! STATUS_INT_LÚÚ 
"Ý! STATUS_INT_HÞÚ <"0Ý!
RESERVED3ÈÚ 
"Ý!DMA_CFG_REG_LÈÚ 
"Ý!DMA_CFG_REG_HÌÚ 
"Ý!CH_EN_REG_LPÚ 
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<unnamed>QÚ 
"î"CONÓÚ 
"î"TARÌÚ 
"î"SARÍÚ 
"î"    HS_MADDRGÚ 
"î"DATACMD½Ú 
"î"SS_SCL_HCNT0Ú 
"î"SS_SCL_LCNT,Ú 
"î"FS_SCL_HCNT=Ú 
"î"FS_SCL_LCNT9Ú 
"î"HS_SCL_HCNT;Ú 
"î"HS_SCL_LCNT7Ú 
"î"
INTR_STATÏÚ 
"î"
INTR_MASKßÚ 
"î"RAW_INTR_STAT~Ú 
"î"RX_TLÚ 
"î"TX_TLÚ 
"î"    CLR_INTR,Ú 
"î"CLR_RX_UNDuÚ 
"î"CLR_RX_OVReÚ 
"î"CLR_TX_OVRcÚ 
"î"CLR_RD_REQÚ 
"î"CLR_TX_ABRT/Ú 
"î"CLR_RX_DONE4Ú 
"î" CLR_ACTIVITYôÚ 
"î" CLR_STOP_DETßÚ 
"î"CLR_START_DETÚ 
"î" CLR_GEN_CALLÚ 
"î"
IC_ENABLEÚ 
"î"STATUSÉÚ 
"î"TXFLRÚ 
"î"RXFLR!Ú 
"î"    SDA_HOLDKÚ 
"î"TX_ABRT_SRC(Ú 
"î"SLV_DATA_NACKµÚ 
"î"DMA_CRçÚ 
"î"    DMA_TDLRBÚ 
"î"    DMA_RDLRDÚ 
"î"
SDA_SETUPßÚ 
"î"ACK_GENERAL_CALLòÚ 
"î"ENABLE_STATUSµÚ 
"î"
FS_SPKLENâÚ 
"î"
HS_SPKLENàÚ 
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I2C_RX_TLóÚP
I2C_TX_TLñÚP I2C_CLR_INTRÚPI2C_CLR_RX_UNDERÇÚPI2C_CLR_TX_OVER    ÚPI2C_CLR_RD_REQuÚPI2C_CLR_TX_ABORTËÚPI2C_CLR_RX_DONE!ÚPI2C_CLR_ACTIVITYáÚPI2C_CLR_STOP_DETÌÚPI2C_CLR_START_DETÚPI2C_CLR_GEN_CALLùÚPI2C_CLR_RESTART_DETçÚPI2C_CLR_MST_ON_HOLDÒÚPI2C_ENABLE_ENABLEßÚPI2C_ENABLE_ABORTÚPI2C_STATUS_ACTIVITYØÚPI2C_STATUS_TFNFÚPI2C_STATUS_TFEpÚPI2C_STATUS_RFNE"ÚPI2C_STATUS_RFErÚ PI2C_STATUS_MST_ACTIVITY}Ú PI2C_STATUS_SLV_ACTIVITY|ÚP
I2C_TXFLRÚP
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<unnamed>QÚ 
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"«$LP_FL_CTRL_3V×Ú 
"«$LP_SPACING_TIME0Ú 
"«$LP_SPACING_TIME1Ú 
"«$LP_SPACING_TIME2Ú 
"«$
LP_SLPTMRÚ 
"«$LP_INT_CTRLjÚ 
"«$LP_DLY_CTRL_3V~Ú 
"«$ LP_PTAT_POLYÚ 
"«$
LP_HP_LDOÚ 
"«$ LP_LP_LDO_3V%Ú 
"«$LP_ANA_LDOÝÚ 
"«$LP_FSYN_LDOkÚ 
"«$LP_SWKÚ 
"«$LP_BUCK_3VÞÚ 
"«$ANA_ADC_LDO¯Ú 
"«$ ANA_RFFE_LDORÚ 
"«$ANA_VCO_LDOÚ 
"«$ANA_DFTßÚ 
"«$ANA_MISC_3V¡Ú 
"«$ANA_RESERVED_3VeÚ 
"«$ ACT_32K_CTRLgÚ 
"«$ACT_32K_BASECORRCÚ 
"«$CPU_ADDR_REMAP_CTRL
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ÚPANAC_CPU_POWER_CTL_PosÚPANAC_CPU_POWER_CTL_MskÚPANAC_PHY_POWER_CTL_Pos}ÚPANAC_PHY_POWER_CTL_MskÚ#PANAC_LL_SRAM_POWER_CTL_Pos<Ú#PANAC_LL_SRAM_POWER_CTL_MskCÚ!PANAC_FLASH_POWER_CTL_PosüÚ!PANAC_FLASH_POWER_CTL_MskÚPANAC_LDO_POWER_CTL_PosÚPANAC_LDO_POWER_CTL_MskÚ PANAC_LDOL_POWER_CTL_PosAÚ PANAC_LDOL_POWER_CTL_MskHÚPANAC_INT_LP_INT_EN_PoszÚPANAC_INT_LP_INT_EN_MskÚPANAC_INT_DP_FLAG_PosIÚPANAC_INT_DP_FLAG_MskPÚ%PANAC_INT_STANDBY_M1_FLAG_PosÛÚ%PANAC_INT_STANDBY_M1_FLAG_MskâÚ%PANAC_INT_STANDBY_M0_FLAG_PosÜÚ%PANAC_INT_STANDBY_M0_FLAG_MskãÚ#PANAC_INT_SRAM_RET_FLAG_PosTÚ#PANAC_INT_SRAM_RET_FLAG_Msk[Ú&PANAC_INT_SLEEP_TMR_INT_EN_Pos=Ú&PANAC_INT_SLEEP_TMR_INT_EN_MskDÚ PANAC_INT_SLEEP_TMR0_PosUÚ PANAC_INT_SLEEP_TMR0_Msk\Ú PANAC_INT_SLEEP_TMR1_PosTÚ PANAC_INT_SLEEP_TMR1_Msk[Ú PANAC_INT_SLEEP_TMR2_PosSÚ PANAC_INT_SLEEP_TMR2_MskZÚ%PANAC_INT_SLEEP_TMR_WK_EN_PosÚ%PANAC_INT_SLEEP_TMR_WK_EN_MskÚ!PANAC_32KCLK_DLY_TIME_Pos8Ú!PANAC_32KCLK_DLY_TIME_Msk?ÚPANAC_32KCLK_DLY_EN_PosØÚPANAC_32KCLK_DLY_EN_MskßÚ"PANAC_HPLDO_RDY_BYPASS_Pos Ú"PANAC_HPLDO_RDY_BYPASS_Msk§Ú$PANAC_LPLDOH_DLY_TIME_Pos_3vñÚ$PANAC_LPLDOH_DLY_TIME_Msk_3vøÚPANAC_PTAT_CORE_EN_PosëÚPANAC_PTAT_CORE_EN_MskòÚPANAC_PTAT_TMP_TRIM_PosxÚPANAC_PTAT_TMP_TRIM_MskÚPANAC_PTAT_TRIM_PosÐÚPANAC_PTAT_TRIM_Msk×Ú#PANAC_PTAT_FLT_SHIFT_EN_PosGÚ#PANAC_PTAT_FLT_SHIFT_EN_MskNÚ!PANAC_PTAT_FLT_ACT_EN_PosñÚ!PANAC_PTAT_FLT_ACT_EN_MskøÚPANAC_POLY_EN_PosrÚPANAC_POLY_EN_MskyÚPANAC_IPOLY_TRIM_PoszÚPANAC_IPOLY_TRIM_MskÚPANAC_HPLDO_EN_Pos=ÚPANAC_HPLDO_EN_MskDÚPANAC_HPLDO_BYPASS_PosöÚPANAC_HPLDO_BYPASS_MskýÚPANAC_HPLDO_TRIM_PosÚPANAC_HPLDO_TRIM_MskÚPANAC_HPLDO_SEL_PosêÚPANAC_HPLDO_SEL_MskñÚ&PANAC_HPLDO_FLASHLDO_BP_Pos_3vrÚ&PANAC_HPLDO_FLASHLDO_BP_Msk_3vyÚ&PANAC_HPLDO_FLASHLDO_EN_Pos_3vqÚ&PANAC_HPLDO_FLASHLDO_EN_Msk_3vxÚ&PANAC_HPLDO_FLASHLDO_LP_EN_Pos~Ú&PANAC_HPLDO_FLASHLDO_LP_EN_MskÚ(P ANAC_HPLDO_FLASHLDO_CAP_SEL_PosñÚ(P ANAC_HPLDO_FLASHLDO_CAP_SEL_MskøÚ%PANAC_HPLDO_FLASHLDO_TRIM_PosÒÚ%PANAC_HPLDO_FLASHLDO_TRIM_MskÙÚPANAC_LPLDO_L_EN_PosÚPANAC_LPLDO_L_EN_MskÚ"PANAC_LPLDO_L_DVDD_SEL_Pos¬Ú"PANAC_LPLDO_L_DVDD_SEL_Msk³ÚPANAC_LPLDO_H_EN_Pos_3vÚPANAC_LPLDO_H_EN_Msk_3vÚ%PANAC_LPLDO_H_DVDD_SEL_Pos_3v¢Ú%PANAC_LPLDO_H_DVDD_SEL_Msk_3v©Ú%PANAC_LPLDO_H_REF_TRIM_Pos_3vÚ%PANAC_LPLDO_H_REF_TRIM_Msk_3vÚ%PANAC_LPLDO_H_MODE_SEL_Pos_3vÚ%PANAC_LPLDO_H_MODE_SEL_Msk_3v¦ÚPANAC_ANA_LDO_EN_Pos¢ÚPANAC_ANA_LDO_EN_Msk©ÚPANAC_ANA_LDO_TRIM_PosõÚPANAC_ANA_LDO_TRIM_MsküÚPANAC_FSYN_LDO_EN_Pos0ÚPANAC_FSYN_LDO_EN_Msk7ÚPANAC_FSYN_LDO_TRIM_PosÚPANAC_FSYN_LDO_TRIM_MskÚPANAC_HP_DVDD_PD_PosÚPANAC_HP_DVDD_PD_MskÚPANAC_HP_DVDD_EN_PosÚPANAC_HP_DVDD_EN_MskÚPANAC_DVDD_SRAM0_EN_PosÆÚPANAC_DVDD_SRAM0_EN_MskÍÚPANAC_DVDD_SRAM1_EN_PosÅÚPANAC_DVDD_SRAM1_EN_MskÌÚPANAC_DVDD_LPLDO_EN_Pos®ÚPANAC_DVDD_LPLDO_EN_MskµÚPANAC_VDD_FLASH_EN_PosÚPANAC_VDD_FLASH_EN_MskÚPANAC_DVDD_DLL_EN_PosQÚPANAC_DVDD_DLL_EN_MskXÚPANAC_DVDD_PHY_EN_Pos<ÚPANAC_DVDD_PHY_EN_MskCÚPANAC_DVDD_CPU_EN_PosEÚPANAC_DVDD_CPU_EN_MskLÚ#PANAC_BUCK_BYPASS_EN_Pos_3vDÚ#PANAC_BUCK_BYPASS_EN_Msk_3vKÚPANAC_BUCK_EN_Pos_3vÚPANAC_BUCK_EN_Msk_3vÚPANAC_BUCK_VOUT_Pos_3vÄÚPANAC_BUCK_VOUT_Msk_3vËÚPANAC_BUCK_IMAX_Pos_3vãÚPANAC_BUCK_IMAX_Msk_3vêÚ"PANAC_BUCK_IMAX_CAL_Pos_3v¬Ú"PANAC_BUCK_IMAX_CAL_Msk_3v³Ú"PANAC_BUCK_ZERO_CAL_Pos_3vÚ"PANAC_BUCK_ZERO_CAL_Msk_3v¢Ú%PANAC_BUCK_DLY_MODE_EN_Pos_3v¥Ú%PANAC_BUCK_DLY_MODE_EN_Msk_3v¬ÚPANAC_BUCK_TEST_EN_PosèÚPANAC_BUCK_TEST_EN_MskïÚ%PANAC_BUCK_DEBOUNCE_EN_Pos_3vÍÚ%PANAC_BUCK_DEBOUNCE_EN_Msk_3vÔÚ PANAC_BUCK_CAL_EN_Pos_3vLÚ PANAC_BUCK_CAL_EN_Msk_3vSÚPANAC_BUCK_CAL_OUT_PosóÚPANAC_BUCK_CAL_OUT_MskúÚ&PANAC_BUCK_VOL_LIMIT_EN_Pos_3vAÚ&PANAC_BUCK_VOL_LIMIT_EN_Msk_3vHÚPANAC_ADC_LDO_EN_PosªÚPANAC_ADC_LDO_EN_Msk±ÚPANAC_ADC_LDO_TRIM_PosýÚPANAC_ADC_LDO_TRIM_MskÚPANAC_RFFE_LDO_EN_PosMÚPANAC_RFFE_LDO_EN_MskTÚPANAC_RFFE_LDO_TRIM_Pos ÚPANAC_RFFE_LDO_TRIM_Msk§ÚPANAC_VCO_LDO_EN_PosÚPANAC_VCO_LDO_EN_MskÚPANAC_VCO_LDO_TRIM_PosÝÚPANAC_VCO_LDO_TRIM_MskäÚ PANAC_DFT_BUF_BYPASS_PosOÚ PANAC_DFT_BUF_BYPASS_MskVÚPANAC_DFT_FLAG_SEL_PosÚPANAC_DFT_FLAG_SEL_MskÚPANAC_DFT_CLK_SEL_PosFÚPANAC_DFT_CLK_SEL_MskMÚPANAC_DFT_I_SEL_PosÛÚPANAC_DFT_I_SEL_MskâÚPANAC_DFT_V_SEL_PosÎÚPANAC_DFT_V_SEL_MskÕÚ$PANAC_DFT_FLAG_OUTPUT_EN_PosùÚ$PANAC_DFT_FLAG_OUTPUT_EN_MskÚ#PANAC_DFT_CLK_OUTPUT_EN_Pos;Ú#PANAC_DFT_CLK_OUTPUT_EN_MskBÚ!PANAC_DFT_I_OUTPUT_EN_PosÐÚ!PANAC_DFT_I_OUTPUT_EN_Msk×Ú!PANAC_DFT_V_OUTPUT_EN_PosÃÚ!PANAC_DFT_V_OUTPUT_EN_MskÊÚ"PANAC_DFT_PAD_TEST_SEL_Pos¢Ú"PANAC_DFT_PAD_TEST_SEL_Msk©Ú%PANAC_DFT_BATTERY_TEST_EN_Pos§Ú%PANAC_DFT_BATTERY_TEST_EN_Msk®Ú&PANAC_DFT_BATTERY_TEST_SEL_PosTÚ&PANAC_DFT_BATTERY_TEST_SEL_Msk[Ú'PANAC_DFT_BATTERY_TEST_TRIM_PosúÚ'PANAC_DFT_BATTERY_TEST_TRIM_MskÚ'PANAC_MISC_RST_VREF_TRIM_Pos_3vÓÚ'PANAC_MISC_RST_VREF_TRIM_Msk_3vÚÚ"PANAC_MISC_PMU_LDO_TST_PosÚ"PANAC_MISC_PMU_LDO_TST_MskÚ%PANAC_MISC_PMU_VBG_BUF_EN_Pos§Ú%PANAC_MISC_PMU_VBG_BUF_EN_Msk®Ú.P&ANAC_MISC_LPLDO_LEVEL_SHIFT_EN_Pos_3vÊÚ.P&ANAC_MISC_LPLDO_LEVEL_SHIFT_EN_Msk_3vÑÚ+P#ANAC_MISC_HPLDO_LEVEL_SHIFT_EN_PosÜÚ+P#ANAC_MISC_HPLDO_LEVEL_SHIFT_EN_MskãÚ%PANAC_MISC_FLASH_PAD_PUEN_PosÌÚ%PANAC_MISC_FLASH_PAD_PUEN_MskÓÚ%PANAC_MISC_FLASH_PAD_PDEN_PosÝÚ%PANAC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<unnamed>QÚ 
"Æ&EF_CTLÚ 
"Æ&EF_ADDRÊÚ 
"Æ&EF_DATÚ 
"Æ&EF_RSV0ºÚ 
"Æ&EF_VDD    Ú 
"Æ&EF_RSV1¹Ú 
"Æ&EF_CMDÚ 
"Æ&EF_TRGúÚ 
"Æ&EF_PROG_TIMING1EÚ 
"Æ&EF_PROG_TIMING2DÚ 
"Æ&EF_PROG_TIMING3CÚ 
"Æ&EF_READ_TIMING4^Ú 
"Æ&EF_READ_TIMING5]Ú <"0Æ&EF_RSV2ZÚ 
"Æ&EF_OP_ERRORUÚ 
"Æ&EF_VERIFY_DEBUG1Ú 
"Æ&EF_VERIFY_DEBUG2Ú 
"Æ&EF_VERIFY_DEBUG3Ú 
"Æ&EF_VERIFY_DEBUG4Ú 
"Æ&EF_FLASH_PERMISSION÷ÚEFUSE_TÈÚPEFUSE_CTL_EFUSE_EN_PosÚPEFUSE_CTL_EFUSE_EN_MskÚPEFUSE_CTL_THR_DVDD_PosÚPEFUSE_CTL_THR_DVDD_MskÚ"PEFUSE_CTL_TAEN_RD_CTL_PosÚ"PEFUSE_CTL_TAEN_RD_CTL_MskÚ!PEFUSE_CTL_THR_RD_CTL_PosÌÚ!PEFUSE_CTL_THR_RD_CTL_MskÓÚPEFUSE_CTL_TRD_CTL_PosËÚPEFUSE_CTL_TRD_CTL_MskÒÚ!PEFUSE_CTL_TSR_RD_CTL_PosÁÚ!PEFUSE_CTL_TSR_RD_CTL_MskÈÚ#PEFUSE_CTL_TSR_DVDD_CTL_Pos1Ú#PEFUSE_CTL_TSR_DVDD_CTL_Msk8Ú!PEFUSE_CTL_THP_RD_CTL_PosÎÚ!PEFUSE_CTL_THP_RD_CTL_MskÕÚ&PEFUSE_CTL_THP_PG_AVDD_CTL_PosEÚ&PEFUSE_CTL_THP_PG_AVDD_CTL_MskLÚ#PEFUSE_CTL_TAEN_PGM_CTL_Pos@Ú#PEFUSE_CTL_TAEN_PGM_CTL_MskGÚ"PEFUSE_CTL_THP_PGM_CTL_Pos~Ú"PEFUSE_CTL_THP_PGM_CTL_MskÚPEFUSE_CTL_TPGM_CTL_Pos{ÚPEFUSE_CTL_TPGM_CTL_MskÚ"PEFUSE_CTL_TSP_PGM_CTL_PossÚ"PEFUSE_CTL_TSP_PGM_CTL_MskzÚ&PEFUSE_CTL_TSP_PG_AVDD_CTL_Pos:Ú&PEFUSE_CTL_TSP_PG_AVDD_CTL_MskAÚ!PEFUSE_CTL_TSP_RD_CTL_PosÃÚ%PEFUSE_CTL_TSP_TSP_RD_CTL_MsklÚ%PEFUSE_ADDR_EFUSEADDR_ADR_PosèÚ%PEFUSE_ADDR_EFUSEADDR_ADR_MskïÚ#PEFUSE_DAT_EFUSEDAT_DAT_PosnÚ#PEFUSE_DAT_EFUSEDAT_DAT_MskuÚ+P#EFUSE_DAT_EFUSEDAT_DAT_CONFIRM_PosñÚ+P#EFUSE_DAT_EFUSEDAT_DAT_CONFIRM_MskøÚPEFUSE_VDD_DVDD_REG_PosÚPEFUSE_VDD_DVDD_REG_Msk¢ÚPEFUSE_VDD_AVDD_REG_PosÚPEFUSE_VDD_AVDD_REG_Msk¥Ú#PEFUSE_CMD_EFUSECMD_CMD_Pos}Ú#PEFUSE_CMD_EFUSECMD_CMD_MskÚ"PEFUSE_TRG_EFUSETRG_GO_PosÚ"PEFUSE_TRG_EFUSETRG_GO_MskÚ*P"EFUSE_PROG_TIMING1_TSP_RD_SET_PosûÚ*P"EFUSE_PROG_TIMING1_TSP_RD_SET_MskÚ/P'EFUSE_PROG_TIMING1_TSP_PG_AVDD_SET_PosrÚ/P'EFUSE_PROG_TIMING1_TSP_PG_AVDD_SET_MskyÚ+P#EFUSE_PROG_TIMING1_TSP_PGM_SET_Pos«Ú+P#EFUSE_PROG_TIMING1_TSP_PGM_SET_Msk²Ú(P EFUSE_PROG_TIMING2_TPGM_SET_Pos²Ú(P EFUSE_PROG_TIMING2_TPGM_SET_Msk¹Ú+P#EFUSE_PROG_TIMING2_THP_PGM_SET_PosµÚ+P#EFUSE_PROG_TIMING2_THP_PGM_SET_Msk¼Ú,P$EFUSE_PROG_TIMING2_TAEN_PGM_SET_PoswÚ,P$EFUSE_PROG_TIMING2_TAEN_PGM_SET_Msk~Ú/P'EFUSE_PROG_TIMING3_THP_PG_AVDD_SET_Pos{Ú/P'EFUSE_PROG_TIMING3_THP_PG_AVDD_SET_MskÚ*P"EFUSE_PROG_TIMING3_THP_RD_SET_PosÚ*P"EFUSE_PROG_TIMING3_THP_RD_SET_MskÚ,P$EFUSE_READ_TIMING4_TSR_DVDD_SET_PosÚ,P$EFUSE_READ_TIMING4_TSR_DVDD_SET_MskÚ*P"EFUSE_READ_TIMING4_TSR_RD_SET_PosÚ*P"EFUSE_READ_TIMING4_TSR_RD_SET_MskÚ'PEFUSE_READ_TIMING4_TRD_SET_PosÚ'PEFUSE_READ_TIMING4_TRD_SET_Msk#Ú*P"EFUSE_READ_TIMING5_THR_RD_SET_PosÚ*P"EFUSE_READ_TIMING5_THR_RD_SET_Msk#Ú+P#EFUSE_READ_TIMING5_TAEN_RD_SET_PosàÚ+P#EFUSE_READ_TIMING5_TAEN_RD_SET_MskçÚ,P$EFUSE_READ_TIMING5_THR_DVDD_SET_PosÚ,P$EFUSE_READ_TIMING5_THR_DVDD_SET_MskÚ$PEFUSE_OP_ERROR_OP_ERROR_Pos¾Ú$PEFUSE_OP_ERROR_OP_ERROR_MskÅÚ0P(EFUSE_VERIFY_DEBUG1_VERIFY_DBG_KEY1_PospÚ0P(EFUSE_VERIFY_DEBUG1_VERIFY_DBG_KEY1_MskwÚ0P(EFUSE_VERIFY_DEBUG2_VERIFY_DBG_KEY2_PosnÚ0P(EFUSE_VERIFY_DEBUG2_VERIFY_DBG_KEY2_MskuÚ0P(EFUSE_VERIFY_DEBUG3_VERIFY_DBG_KEY3_PoslÚ0P(EFUSE_VERIFY_DEBUG3_VERIFY_DBG_KEY3_MsksÚ0P(EFUSE_VERIFY_DEBUG4_VERIFY_DBG_KEY4_PosjÚ0P(EFUSE_VERIFY_DEBUG4_VERIFY_DBG_KEY4_MskqÚ(P EFUSE_FLASH_PERMISSION_CTRL_Pos»Ú(P EFUSE_FLASH_PERMISSION_CTRL_MskÂÚ8
<unnamed>QÚ "°'FADDRÚ "°'POWERbÚ "°'INT_IN1ÙÚ "°'INT_IN2ØÚ "°'    INT_OUT1vÚ "°'    INT_OUT2uÚ "°'INT_USB·Ú "°'    INT_IN1EÚ "°'    INT_IN2EÚ "°'
INT_OUT1E/Ú "°'
INT_OUT2E.Ú "°'    INT_USBEpÚ "°'FRAME1QÚ "°'FRAME2PÚ "°'INDEXwÚ "°'REVÚ "°'MAX_PKT_IN»Ú "°'CSR0_INCSR1¼Ú "°'IN_CSR2ÛÚ "°'MAX_PKT_OUTXÚ "°'    OUT_CSR1yÚ "°'    OUT_CSR2xÚ "°'OUT_COUNT1ÔÚ "°'OUT_COUNT2ÓÚ <"°'REV0Ú "°'    FIFO_EP0¡Ú <"°'REV1Ú "°'    FIFO_EP1 Ú <"°'REV2Ú "°'    FIFO_EP2Ú <"°'REV3Ú "°'    FIFO_EP3ÚUSB_TZÚ8
<unnamed>QÚ 
"Ò'    DMA_INTRRÚ 
"Ò'CNTL1dÚ 
"Ò'ADDR1zÚ 
"Ò'COUNT1
Ú    USBDMA_TÚPUSB_DMA_REQUEST_PosqÚPUSB_DMA_REQUEST_MskxÚPUSB_DMA_DIRECTION_PosõÚPUSB_DMA_DIRECTION_MsküÚPUSB_DMA_MODE_SEL_Pos0ÚPUSB_DMA_MODE_SEL_Msk7ÚPUSB_DMA_EP_NUM_Pos¸ÚPUSB_DMA_EP_NUM_Msk¿Ú8
<unnamed>QÚ 
"à'revs0ÈÚ 
"à'FSM5Ú 
"à'FSM6Ú 
"à'FSM13nÚ 
"à'FSM14mÚ 
"à'FSM15lÚ 
"à'FSM16kÚ 
"à'FSM17jÚ 
"à'FSM18iÚ 
"à'FSM19hÚ 
"à'PHY1Ú 
"à'PHY2Ú 
"à'PHY3Ú 
"à'PHY4Ú 
"à'PHY5Ú <"à'revs1Ú 
"à'INTR1JÚ 
"à'INTCLRêÚ 
"à'INTMSKàÚ 
"à'INTR4GÚ 
"à'revs2ÆÚ 
"à'ACTTMR1¸Ú 
"à'ACTTMR2·Ú 
"à'ACTTMR6³Ú 
"à'ACTTMR7²Ú 
"à'revs3ÅÚ 
"à'SECURE1¼Ú 
"à'SECURE2»Ú 
"à'SECURE3ºÚ 
"à'SECURE4¹Ú 
"à'SECURE5¸Ú 
"à'SECURE6·Ú 
"à'SECURE7¶Ú 
"à'SECURE8µÚ 
"à'SECURE9´Ú 
"à'    SECURE10Ú 
"à'revs4ÄÚ 
"à'TEST_MUX00µÚ 
"à'RNG1¢Ú 
"à'RNG2¡Ú 
"à'revs5ÃÚ 
"à'LL_MAC_CTRLPÚ 
"à'TEST_MUX01´Ú 
"à'TEST_MUX02³Ú 
"à'TEST_MUX03²Ú <"à'revs6Ú 
"à'R00_CTLÀÚ 
"à'R01_INT·Ú 
"à'R02_TMR_CTLdÚ 
"à'R03_RX_ADDR_LÅÚ 
"à'R04_RX_CTLÚ 
"à'R05_TX_ADDR_LÁÚ 
"à'R06_TX_CTL©Ú 
"à' R07_SRAM_CTLÚ 
"à'R08_RX_ADDR1_LÚ 
"à'R09_RX_ADDR2_LÚ 
"à'R0A_RX_ADDR3_LÚ 
"à'R0B_RX_ADDR4_LÚ 
"à'R0C_RX_ADDR5_L~Ú 
"à'R0D_RX_ADDR6_L|Ú 
"à'R0E_RX_ADDR7_LzÚ 
"à'R0F_RX_ADDR_H¶Ú 
"à'R10_RX_ADDR_EN~Ú 
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ÚSYS_AssertErrorðÚP__PAN_SYS_H__QÚPSYS_MFP_TYPE_Msk?ÚPSYS_MFP_ALT_Msk¢ÚPSYS_MFP_MFP_Msk ÚP SYS_MFP_GPIOäÚPSYS_MFP_P00_GPIOÍÚPSYS_MFP_P00_SWD_CLKÏÚPSYS_MFP_P00_UART1_RX~ÚPSYS_MFP_P00_I2C0_SCLÅÚPSYS_MFP_P00_SPI0_CLKÚPSYS_MFP_P00_LL_DBG_14jÚPSYS_MFP_P00_MDM_DBG_11%ÚPSYS_MFP_P00_RESERVEDÚPSYS_MFP_P00_MskÓÚPSYS_MFP_P01_GPIOÌÚPSYS_MFP_P01_SWD_DATÏÚPSYS_MFP_P01_UART1_TX{ÚPSYS_MFP_P01_I2C0_SDAÎÚPSYS_MFP_P01_SPI0_CSäÚPSYS_MFP_P01_LL_DBG_15hÚPSYS_MFP_P01_MDM_DBG_12#ÚPSYS_MFP_P01_RESERVEDÚPSYS_MFP_P01_MskÒÚPSYS_MFP_P02_GPIOËÚPSYS_MFP_P02_UART0_CTS;ÚPSYS_MFP_P02_SPI1_MISO<ÚPSYS_MFP_P02_PWM_CH3ãÚPSYS_MFP_P02_UART1_CTS:ÚPSYS_MFP_P02_LL_DBG_8ÚPSYS_MFP_P02_MDM_DBG_19ÚPSYS_MFP_P02_RESERVEDÚPSYS_MFP_P02_MskÑÚPSYS_MFP_P03_GPIOÊÚPSYS_MFP_P03_UART0_CTS:ÚPSYS_MFP_P03_SPI0_CSâÚPSYS_MFP_P03_PWM_CH2ãÚ#PSYS_MFP_P03_TIMER0_CNT_OUTÚPSYS_MFP_P03_LL_DBG_8ÚPSYS_MFP_P03_MDM_DBG_5QÚPSYS_MFP_P03_RESERVEDÚPSYS_MFP_P03_MskÐÚPSYS_MFP_P04_GPIOÉÚPSYS_MFP_P04_UART0_RTS*ÚPSYS_MFP_P04_SPI0_CLKÚPSYS_MFP_P04_PWM_CH3áÚPSYS_MFP_P04_TIMER0_EXTëÚPSYS_MFP_P04_LL_DBG_9ÚPSYS_MFP_P04_MDM_DBG_6OÚPSYS_MFP_P04_RESERVEDÚPSYS_MFP_P04_MskÏÚPSYS_MFP_P05_GPIOÈÚPSYS_MFP_P05_UART0_TXxÚPSYS_MFP_P05_SPI0_MISO:ÚPSYS_MFP_P05_PWM_CH4ßÚPSYS_MFP_P05_EXT_STADC.ÚPSYS_MFP_P05_LL_DBG_12gÚPSYS_MFP_P05_MDM_DBG_9KÚPSYS_MFP_P05_RESERVEDÚPSYS_MFP_P05_MskÎÚPSYS_MFP_P06_GPIOÇÚPSYS_MFP_P06_UART0_RXyÚPSYS_MFP_P06_SPI0_MISO9ÚPSYS_MFP_P06_PWM_CH5ÝÚPSYS_MFP_P06_TIMER1_EXTèÚPSYS_MFP_P06_LL_DBG_13eÚPSYS_MFP_P06_MDM_DBG_3PÚPSYS_MFP_P06_AHB_CLKìÚPSYS_MFP_P06_MskÍÚPSYS_MFP_P07_GPIOÆÚPSYS_MFP_P07_UART1_RXwÚPSYS_MFP_P07_I2C0_SCL¾ÚPSYS_MFP_P07_SPI0_MOSI8ÚPSYS_MFP_P07_PWM_CH0áÚPSYS_MFP_P07_LL_DBG_10gÚPSYS_MFP_P07_MDM_DBG_7KÚPSYS_MFP_P07_RESERVEDÚPSYS_MFP_P07_MskÌÚPSYS_MFP_P10_GPIOÌÚPSYS_MFP_P10_UART1_TX{ÚPSYS_MFP_P10_I2C0_SDAÎÚPSYS_MFP_P10_SPI0_MISO>ÚPSYS_MFP_P10_PWM_CH5âÚPSYS_MFP_P10_LL_DBG_11lÚPSYS_MFP_P10_MDM_DBG_8PÚPSYS_MFP_P10_RESERVEDÚPSYS_MFP_P10_MskÒÚPSYS_MFP_P11_GPIOËÚPSYS_MFP_P11_UART1_RTS+ÚPSYS_MFP_P11_SPI0_MOSI=ÚPSYS_MFP_P11_PWM_CH7ßÚPSYS_MFP_P11_CLK_32KÚPSYS_MFP_P11_LL_DBG_9ÚPSYS_MFP_P11_MDM_DBG_0WÚPSYS_MFP_P11_UART0_TX{ÚPSYS_MFP_P11_MskÑÚPSYS_MFP_P12_GPIOÊÚPSYS_MFP_P12_UART0_RX|ÚPSYS_MFP_P12_PWM_CH4áÚ#PSYS_MFP_P12_TIMER0_CNT_OUTÚPSYS_MFP_P12_UART1_TXyÚPSYS_MFP_P12_LL_DBG_4ÚPSYS_MFP_P12_MDM_DBG_17ÚPSYS_MFP_P12_SPI0_MISO<ÚPSYS_MFP_P12_MskÐÚPSYS_MFP_P13_GPIOÉÚPSYS_MFP_P13_UART0_RTS*ÚPSYS_MFP_P13_I2C0_SDAËÚPSYS_MFP_P13_PWM_CH3áÚPSYS_MFP_P13_LL_DBG_3ÚPSYS_MFP_P13_MDM_DBG_16ÚPSYS_MFP_P13_SPI1_CSàÚPSYS_MFP_P13_SPI0_CSáÚPSYS_MFP_P13_MskÏÚPSYS_MFP_P14_GPIOÈÚPSYS_MFP_P14_UART0_CTS8ÚPSYS_MFP_P14_I2C0_SCLÀÚPSYS_MFP_P14_PWM_CH2áÚPSYS_MFP_P14_LL_DEBUG_2üÚPSYS_MFP_P14_MDM_DBG_15ÚPSYS_MFP_P14_SPI0_CLKÚPSYS_MFP_P14_RESERVEDÚPSYS_MFP_P14_MskÎÚPSYS_MFP_P15_GPIOÇÚPSYS_MFP_P15_SPI0_CSßÚPSYS_MFP_P15_PWM_CH5ÝÚPSYS_MFP_P15_TIMER0_EXTéÚPSYS_MFP_P15_UART0_RXyÚPSYS_MFP_P15_LL_DBG_5ÚPSYS_MFP_P15_MDM_DBG_18ÚPSYS_MFP_P15_RESERVEDÚPSYS_MFP_P15_MskÍÚPSYS_MFP_P16_GPIOÆÚPSYS_MFP_P16_UART0_TXvÚ#PSYS_MFP_P16_TIMER2_CNT_OUTÚPSYS_MFP_P16_PWM_CH0áÚPSYS_MFP_P16_LL_DBG_0ÚPSYS_MFP_P16_MDM_DBG_13ÚPSYS_MFP_P16_SPI1_CLKÚPSYS_MFP_P16_I2C0_SCL¾ÚPSYS_MFP_P16_MskÌÚPSYS_MFP_P17_GPIOÅÚPSYS_MFP_P17_UART0_RXwÚPSYS_MFP_P17_TIMER2_EXTåÚPSYS_MFP_P17_PWM_CH1ßÚPSYS_MFP_P17_LL_DBG_1ÚPSYS_MFP_P17_MDM_DBG_14ÚPSYS_MFP_P17_RCHÚPSYS_MFP_P17_RESERVEDÚPSYS_MFP_P17_MskËÚPSYS_MFP_P20_GPIOËÚPSYS_MFP_P20_SPI1_MISO<ÚPSYS_MFP_P20_PWM_CH6àÚPSYS_MFP_P20_TADC_CLKÚPSYS_MFP_P20_LL_DBG_6ÚPSYS_MFP_P20_MDM_DBG_2UÚPSYS_MFP_P20_XTL_C1_CLKêÚPSYS_MFP_P20_RESERVEDÚPSYS_MFP_P20_MskÑÚPSYS_MFP_P21_GPIOÊÚPSYS_MFP_P21_SPI1_MOSI;ÚPSYS_MFP_P21_PWM_CH7ÞÚPSYS_MFP_P21_TADC_VLDÚPSYS_MFP_P21_LL_DBG_7ÚPSYS_MFP_P21_MDM_DBG_1UÚPSYS_MFP_P21_XTL_C2_CLKèÚPSYS_MFP_P21_RESERVEDÚPSYS_MFP_P21_MskÐÚPSYS_MFP_P22_GPIOÉÚPSYS_MFP_P22_SPI1_CLKÚPSYS_MFP_P22_PWM_CH0äÚPSYS_MFP_P22_RESERVEDÚPSYS_MFP_P22_TADC_DATl.ÚPSYS_MFP_P22_MDM_DBG_0UÚPSYS_MFP_P22_SPI0_MOSI;ÚPSYS_MFP_P22_RESERVED1]ÚPSYS_MFP_P22_MskÏÚPSYS_MFP_P23_GPIOÈÚPSYS_MFP_P23_SPI1_CSßÚPSYS_MFP_P23_PWM_CH1âÚPSYS_MFP_P23_DPLL_DIV8GÚPSYS_MFP_P23_TADC_DATHQÚPSYS_MFP_P23_MDM_DBG_10!ÚPSYS_MFP_P23_I2C0_SCLÀÚPSYS_MFP_P23_RESERVEDÚPSYS_MFP_P23_MskÎÚPSYS_MFP_P24_GPIOÇÚPSYS_MFP_P24_SPI1_MISO8ÚPSYS_MFP_P24_UART1_RXxÚPSYS_MFP_P24_PWM_CH2àÚ#PSYS_MFP_P24_TIMER1_CNT_OUTÚPSYS_MFP_P24_MDM_DBG_4OÚPSYS_MFP_P24_RESERVEDÚPSYS_MFP_P24_RESERVED1[ÚPSYS_MFP_P24_MskÍÚPSYS_MFP_P25_GPIOÆÚPSYS_MFP_P25_SPI1_MOSI7ÚPSYS_MFP_P25_UART1_TXuÚPSYS_MFP_P25_PWM_CH3ÞÚPSYS_MFP_P25_MDM_DBG_5MÚPSYS_MFP_P25_RESERVEDÚPSYS_MFP_P25_I2C0_SDAÈÚPSYS_MFP_P25_RESERVED1ZÚPSYS_MFP_P25_MskÌÚPSYS_MFP_P26_GPIOÅÚPSYS_MFP_P26_UART1_RTS%ÚPSYS_MFP_P26_PWM_CH4ÜÚPSYS_MFP_P26_SPI1_CSÜÚPSYS_MFP_P26_MDM_DBG_4MÚPSYS_MFP_P26_MDM_DBG_10ÚPSYS_MFP_P26_RESERVEDÚPSYS_MFP_P26_RESERVED1YÚPSYS_MFP_P26_MskËÚPSYS_MFP_P27_GPIOÄÚPSYS_MFP_P27_UART1_CTS3ÚPSYS_MFP_P27_PWM_CH5ÚÚPSYS_MFP_P27_SPI1_CLKÚPSYS_MFP_P27_RESERVEDÚPSYS_MFP_P27_MDM_DBG_20ÚPSYS_MFP_P27_XTHÚPSYS_MFP_P27_RESERVED1XÚPSYS_MFP_P27_MskÊÚPSYS_MFP_P30_GPIOÊÚPSYS_MFP_P30_UART1_RX{ÚPSYS_MFP_P30_PWM_CH6ßÚPSYS_MFP_P30_SPI1_MISO;ÚPSYS_MFP_P30_MDM_DBG_10#ÚPSYS_MFP_P30_RESERVEDÚPSYS_MFP_P30_RESERVED1^ÚPSYS_MFP_P30_RESERVED2]ÚPSYS_MFP_P30_MskÐÚPSYS_MFP_P31_GPIOÉÚPSYS_MFP_P31_UART1_TXxÚPSYS_MFP_P31_PWM_CH7ÝÚPSYS_MFP_P31_SPI1_MOSI:ÚPSYS_MFP_P31_RESERVEDÚPSYS_MFP_P31_RESERVED1]ÚPSYS_MFP_P31_RESERVED2\ÚPSYS_MFP_P31_RESERVED3[ÚPSYS_MFP_P31_MskÏÚPSYS_SET_MFP)ÚSYS_UnlockRegòÚSYS_LockRegÙÚSYS_IsRegLocked@Ú,
 
u32NopCnt¡ÚSYS_delay_10nopPÚP__PAN_CLK_H__vÚ$PCLK_APB1_WDTSEL_MILLI_PULSEhÚPCLK_APB1_WDTSEL_RCL32K@Ú%PCLK_APB1_WWDTSEL_MILLI_PULSEÚ PCLK_APB1_WWDTSEL_RCL32KçÚ!PCLK_APB1_TMR0SEL_APB1CLK»Ú PCLK_APB1_TMR0SEL_RCL32K
ÚPCLK_APB1_TMR0SEL_TM0ÐÚ!PCLK_APB2_TMR1SEL_APB2CLK¸Ú PCLK_APB2_TMR1SEL_RCL32KÚPCLK_APB2_TMR1SEL_TM1ÍÚ!PCLK_APB2_TMR2SEL_APB2CLK·Ú PCLK_APB2_TMR2SEL_RCL32KÚPCLK_APB2_TMR2SEL_TM2ËÚ"PCLK_APB1_PWM_CH01_SEL_APBIÚ%PCLK_APB1_PWM_CH01_SEL_CLK32KÚ"PCLK_APB1_PWM_CH23_SEL_APBEÚ%PCLK_APB1_PWM_CH23_SEL_CLK32KÚ"PCLK_APB1_PWM_CH45_SEL_APBAÚ%PCLK_APB1_PWM_CH45_SEL_CLK32KÚ"PCLK_APB1_PWM_CH67_SEL_APB=Ú%PCLK_APB1_PWM_CH67_SEL_CLK32KÚP
FREQ_1MHZÚP
FREQ_8MHZÚPFREQ_16MHZÔÚPFREQ_25MHZÔÚPFREQ_32MHZÖÚPFREQ_48MHZÏÚPFREQ_64MHZÑÚPFREQ_96MHZÌÚPFREQ_50MHZÖÚPFREQ_72MHZÒÚPFREQ_100MHZ¨ÚPCLK_SYS_SRCSEL_RCHÚPCLK_SYS_SRCSEL_XTHñÚPCLK_SYS_SRCSEL_DPLL·Ú PCLK_DPLL_REF_CLKSEL_RCH£Ú PCLK_DPLL_REF_CLKSEL_XTHÚPCLK_DPLL_OUT_48M×ÚPCLK_DPLL_OUT_64MÙÚPCLK_APB1Periph_I2C0³ÚPCLK_APB1Periph_SPI0ÚPCLK_APB1Periph_UART03Ú!PCLK_APB1Periph_PWM0_CH01(Ú!PCLK_APB1Periph_PWM0_CH23$Ú!PCLK_APB1Periph_PWM0_CH45 Ú!PCLK_APB1Periph_PWM0_CH67ÚPCLK_APB1Periph_PWM0_ENÚPCLK_APB1Periph_ADCÛÚPCLK_APB1Periph_WDT´ÚPCLK_APB1Periph_WWDT[ÚPCLK_APB1Periph_TMR0~Ú PCLK_APB1Periph_MILI_CLK5ÚPCLK_APB1Periph_AllÚPCLK_APB2Periph_SPI1ÚPCLK_APB2Periph_UART11ÚPCLK_APB2Periph_TMR1|ÚPCLK_APB2Periph_TMR2{ÚPCLK_APB2Periph_AllÚPCLK_AHBPeriph_DMACÇÚPCLK_AHBPeriph_GPIOÚPCLK_AHBPeriph_SYSTICK¬ÚPCLK_AHBPeriph_APB1ØÚPCLK_AHBPeriph_APB2×ÚPCLK_AHBPeriph_AHBÚPCLK_AHBPeriph_BLE_32MòÚPCLK_AHBPeriph_BLE_32KôÚPCLK_AHBPeriph_ROMðÚPCLK_AHBPeriph_EFUSEbÚPCLK_AHBPeriph_USB_AHBÂÚPCLK_AHBPeriph_USB_48MÔÚPCLK_AHBPeriph_AllÅÚPCLK_DivideSource_Ahb:ÚPCLK_DivideSource_Apb1ÿÚPCLK_DivideSource_Apb2þÚPCLK_RCL_SELECTvÚPCLK_RCH_SELECTzÚPCLK_XTL_SELECT_ÚPCLK_XTH_SELECTcÚPCLK_DPLL_SELECT)ÚPCLK_STABLE_STATUS_PosÙÚPCLK_STABLE_STATUS_MskàÚ!PCLKTRIM_CALC_CLK_SEL_32KÚ!PCLKTRIM_CALC_CLK_SEL_32MÚ!PCLKTRIM_QDEC_CLK_SEL_APB[Ú!PCLKTRIM_QDEC_CLK_SEL_32K~Ú"PCLKTRIM_KSCAN_CLK_SEL_APBÚ"PCLKTRIM_KSCAN_CLK_SEL_32K)ÚPDMA_RSTÚPLL_RSTÏÚP
EFUSE_RSTéÚPUSB_RST{ÚPMDMSTB_RSTÚPMDM_RSTÚP    I2C0_RSTuÚP    SPI0_RSTGÚP    SPI1_RSTFÚP
UART0_RSTõÚP
UART1_RSTôÚP    PWM0_RST?ÚPADC_RSTÚPWDT_RSTvÚP    WWDT_RSTÚP    TMR0_RST@ÚP    TMR1_RST?ÚP    TMR2_RST>ÚP    GPIO_RST4ÚPCLKTRIM_RSTGÚPCLK_BODCTL_BOD_INT_EN@ÚPCLK_BODCTL_BOD_RST_EN2Ú PCLK_BODCTL_BODSEL_1_75VãÚ PCLK_BODCTL_BODSEL_1_95VáÚ PCLK_BODCTL_BODSEL_2_15VèÚ PCLK_BODCTL_BODSEL_2_35VæÚ PCLK_BODCTL_BODSEL_2_55VäÚ PCLK_BODCTL_BODSEL_2_75VâÚ PCLK_BODCTL_BODSEL_2_95VàÚ#PCLK_BLDBCTL_BODDBSEL_2POW0Ú#PCLK_BLDBCTL_BODDBSEL_2POW1Ú#PCLK_BLDBCTL_BODDBSEL_2POW2Ú#PCLK_BLDBCTL_BODDBSEL_2POW3Ú#PCLK_BLDBCTL_BODDBSEL_2POW4Ú#PCLK_BLDBCTL_BODDBSEL_2POW5 Ú#PCLK_BLDBCTL_LVRDBSEL_2POW0óÚ#PCLK_BLDBCTL_LVRDBSEL_2POW1òÚ#PCLK_BLDBCTL_LVRDBSEL_2POW2ñÚ#PCLK_BLDBCTL_LVRDBSEL_2POW3ðÚ#PCLK_BLDBCTL_LVRDBSEL_2POW4ïÚ#PCLK_BLDBCTL_LVRDBSEL_2POW5îÚCLK_XthStartupConfigÚCLK_HCLKConfig'Ú,
"Á/
u32ClkDiv¤ÚCLK_PCLK1ConfigìÚ,
"Ã/
u32ClkDiv¢ÚCLK_PCLK2ConfigëÚ,
"Å/
u32ClkDiv ÚCLK_SetDpllOutputFreqºÚ,
"Ç/freqÚCLK_EnableClkTrimÚ,""É/    NewStateuÚCLK_SelectClkTrimSrcUÚ,
"Ë/srcuÚ CLK_SetClkTrimCalClkDiv^Ú,"Í/divvÚ
"Í/reg¡ÚCLK_FLASH_CLKDIV_1ÚCLK_FLASH_CLKDIV_2ÚCLK_FLASH_CLKDIV_4ÚCLK_FLASH_CLKDIV_8ÚCLK_FLASH_CLKDIV_16NÚCLK_FLASH_CLKDIV_30RÚCLK_SetFlashClkDiv@Ú,"Ö/divvÚ
"Ö/regÚCLK_GetHCLKFreqÁÚCLK_GetCPUFreqýÚCLK_GetPCLK1FreqÚCLK_GetPCLK2FreqÚ,
 
u32ClkSrc±ÚCLK_RefClkSrcConfigÔÚ,
 
u32ClkSrc±Ú,
    freq_outjÚCLK_SYSCLKConfig`Ú,
 
u32ClkDiv¶Ú,
 
u32ClkDiv¶Ú,
 
u32ClkDiv¶Ú,
CLK_AHBPeriphYÚ,"    NewStateÚCLK_AHBPeriphClockCmdRÚ,
CLK_APB1PeriphÚ,"    NewStateÚCLK_APB1PeriphClockCmdÚ,
CLK_APB2PeriphÚ,"    NewStateÚCLK_APB2PeriphClockCmdÚ,
u32ClkMaskKÚCLK_WaitClockReadyÚCLK_Wait3vSyncReady¹ÚCLK_Set3vSyncAutoÚ,
 
u32clkseluÚCLK_SetWdtClkSrcòÚ,
 
u32clkseluÚCLK_SetWwdtClkSrcyÚ,timer¦Ú,
 
u32clkseluÚCLK_SetTmrClkSrcîÚ,
    u32ChNumÚ,
 
u32clkseluÚCLK_SetPwmClkSrcíÚ,Peripheral±ÚCLK_GetPeripheralFreqËÚCLK_ResetChipÚ!CLK_ResetSystemToRomModeÚ,
u32ModuleIndexÚCLK_ResetModule(Ú,i32ModeÚ,
u32BODLevel"ÚCLK_ConfigureBODÚCLK_EnableBODyÚCLK_DisableBOD
ÚCLK_GetBODStatusÚCLK_GetBODIntFlagóÚCLK_ClearBODIntFlag(Ú,
 u32BodDBTimeÃÚCLK_SetBODDebounceTimeÎÚCLK_EnableLVRZÚCLK_DisableLVRëÚ,
 u32LvrDBTime¤ÚCLK_SetLVRDebounceTime¯ÚP__PAN_ADC_H__ÚPADC_INPUTRANGE_HIGHÚPADC_INPUTRANGE_LOW2ÚPADC_CH8_EXT{ÚPADC_CH8_BGPÚPADC_CMP0_LESS_THANPÚPADC_CMP1_LESS_THANOÚ%PADC_CMP0_GREATER_OR_EQUAL_TOÚ%PADC_CMP1_GREATER_OR_EQUAL_TOÚPADC_TRIGGER_BY_EXT_PINÔÚPADC_TRIGGER_BY_PWMÚ!PADC_FALLING_EDGE_TRIGGERÚ PADC_RISING_EDGE_TRIGGERÃÚP ADC_ADIF_INT.ÚP ADC_CMP0_INT2ÚP ADC_CMP1_INT1ÚPADC_FIFO_FULL_INTÚPADC_FIFO_EMPTY_INT$ÚPADC_FIFO_OVER_INTyÚPADC_FIFO_HALF_INTÚPADC_SAMPLE_CLOCK_0dÚPADC_SAMPLE_CLOCK_1cÚPADC_SAMPLE_CLOCK_2bÚPADC_SAMPLE_CLOCK_4`ÚPADC_SAMPLE_CLOCK_8\ÚPADC_SAMPLE_CLOCK_16+ÚPADC_SAMPLE_CLOCK_32-ÚPADC_SAMPLE_CLOCK_64(ÚPADC_SAMPLE_CLOCK_128õÚPADC_SAMPLE_CLOCK_256óÚPADC_SAMPLE_CLOCK_512øÚPADC_SAMPLE_CLOCK_1024ÇÚ!PADC_SEQMODE_TYPE_23SHUNToÚ PADC_SEQMODE_TYPE_1SHUNT¥Ú$PADC_SEQMODE_MODESELECT_CH01ÑÚ$PADC_SEQMODE_MODESELECT_CH12ÏÚ$PADC_SEQMODE_MODESELECT_CH02ÐÚ#PADC_SEQMODE_MODESELECT_ONEÝÚ PADC_SEQMODE_PWM0_RISINGºÚ PADC_SEQMODE_PWM0_CENTERÅÚ!PADC_SEQMODE_PWM0_FALLINGÚ PADC_SEQMODE_PWM0_PERIODÃÚ PADC_SEQMODE_PWM2_RISING¸Ú PADC_SEQMODE_PWM2_CENTERÃÚ!PADC_SEQMODE_PWM2_FALLINGÚ PADC_SEQMODE_PWM2_PERIODÁÚ PADC_SEQMODE_PWM4_RISING¶Ú PADC_SEQMODE_PWM4_CENTERÁÚ!PADC_SEQMODE_PWM4_FALLINGÚ PADC_SEQMODE_PWM4_PERIOD¿Ú PADC_SEQMODE_PWM6_RISING´Ú PADC_SEQMODE_PWM6_CENTER¿Ú!PADC_SEQMODE_PWM6_FALLINGÚ PADC_SEQMODE_PWM6_PERIOD½ÚPADC_COMPARATOR_0ýÚPADC_COMPARATOR_1üÚ!PADC_FIFO_TRIG_LEVEL_HALFjÚ!PADC_FIFO_TRIG_LEVEL_FULLRÚ8
<unnamed>QÚ "Ê0
chip_infoÚ "Ê0ft_versionÚ "Ê0
adc_vdd_b@Ú "Ê0
adc_vdd_k,Ú "Ê0
adc_vbg_k+Ú "Ê0
adc_vbg_b6Ú "Ê0adc_temp_voltRÚ "Ê0current_temp_valueÚ "Ê0adc_vbg_1v20_trimkÚ "Ê0
rsvd_0x30Ú <"Ê0adc_vbg_kbÚ "Ê0adc_vbat_k»Ú "Ê0adc_vbat_bÆÚ "Ê0adc_vbat_dtemp_k8Ú "Ê0adc_vbat_dtemp_bAÚ "Ê0adc_temp_kªÚ 
"Ê0
adc_ctrl2OÚ 
"Ê0adc_extsmptÚ
ADC_OPT_T"Ú@
m_adc_optõÚ
global_calc_vbat_mv$Ú,optxÚ ADC_SetCalirationParamsýÚADC_GetConversionDataãÚ,"â0ADCxUÚADC_StatusFlag³Ú,"ä0ADCxSÚ,
"ä0IntMaskäÚADC_ClearStatusFlagÂÚ,"ç0ADCxPÚ,
"ç0IntMaskáÚADC_IntMaskÚ,"ê0ADCxMÚ,
"ê0IntMaskÞÚ,""ê0    NewStateSÚADC_IsIntOccuredÚ,"î0ADCxIÚ,
"î0IntMaskÚÚADC_ClearIntFlag!Ú,"ñ0ADCxFÚ,
"ñ0IntMask×ÚADC_IsBusyZÚ,"ô0ADCxCÚADC_IsDataOverrunÚ,"ö0ADCxAÚADC_IsDataValidÚ,"ø0ADCx?ÚADC_PowerDownÚ,"ú0ADCx=ÚADC_PowerOníÚ,"ü0ADCx;Ú"ADC_SequentialModeDisableGÚ,"þ0ADCx9ÚADC_Trigger2SelectCÚ,"1ADCx¶Ú,""1    NewState¼ÚADC_DisableCompare0üÚ,"1ADCx³ÚADC_DisableCompare1ûÚ,"1ADCx±ÚADC_StartConvert¾Ú,"1ADCx¯ÚADC_StopConvert(Ú,"1ADCxÚADC_TestModeEnable=Ú,"1ADCx«ÚADC_TestModeDisableÎÚ,"1ADCx©ÚADC_DmaModeEnableÍÚ,"1ADCx§Ú,""1    NewStateÚADC_SetClockDividerÈÚ,"1ADCx¤Ú,
"1Divider%Ú    ADC_Open+Ú,"1ADCx¡Ú,
"1ChMask´ÚADC_SelInputRangeÚ,"1ADCxÚ,
"1EnableHighÚADC_TriggerDelayêÚ,"1ADCxÚ,
"1DataoÚADC_SetExtraSampleTimeÚ,"1ADCxÚ,
"1SampleTimeéÚADC_IsOneChConvertEnd"Ú,"¡1ADCxÚADC_ClearByHwRÚ,"£1ADCxÚ,""£1    NewStateÚADC_LeftShiftEnsÚ,"¦1ADCxÚ,""¦1    NewStateÚADC_SubtractBiasEn/Ú,"©1ADCxÚ,""©1    NewStateÚADC_SetBiasDataÚ,"¬1ADCxÚ,
"¬1    BiasData×ÚADC_SetFifoTrigLevelgÚ,"¯1ADCxÚ,"¯1LevelâÚADC_SeqModeOneChEn{Ú,"²1ADCxÚ,""²1    NewStateÚ ,ADCxÚ,buf_enkÚ    ADC_InitÚ ,ADCxÚ ADC_PrepareVbgCalibDataPÚ ,ADCxÚ,
    adc_codeÚADC_OutputVoltage<Ú ,ADCxÚ,sample_bufÚ,
sample_cnt¥Ú,
    trim_cntoÚ!ADC_SamplingCodeTrimMean¾Ú ,ADCxÚ"ADC_MeasureSocTemperature
Ú ,ADCxÚ&ADC_MeasureSocTemperatureFasttÚ ,ADCxÚADC_MeasureSocVbatÚ ,ADCxÚADC_Disable÷Ú
ADC_Close¹Ú ,ADCxÚ,
SourcebÚ,
ParamäÚADC_EnableHWTriggeráÚ ,ADCxÚADC_DisableHWTriggerrÚ ,ADCxÚ ,
MaskKÚADC_EnableInt5Ú ,ADCxÚ ,
MaskKÚADC_DisableIntÆÚ ,ADCxÚ,
SeqTYPEfÚ,
ModeSel(ÚADC_SeqModeEnableªÚ ,ADCxÚ,
SeqModeTriSrcÀÚADC_SeqModeTriggerSrcíÚ ,ADCxÚ,
ChNumúÚ,
 CmpConditionÚ,
CmpData7Ú,
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TrigAÚ,LeveläÚ,DmaEnÚ,HwClrENeÚADC_SeqOneChModeConfigÄÚP__PAN_FMC_H__zÚPM32ÚPCMD_ERASE_PAGEÚPCMD_ERASE_SECTORÙÚPCMD_ERASE_32KÿÚPCMD_ERASE_64KúÚPCMD_ERASE_CHIPÚPCMD_READ_STATUS_LlÚPCMD_READ_STATUS_HpÚPCMD_WRITE_STATUSªÚPOPS_WR_STU_REG_NORÇÚPOPS_WR_STU_REG_ALLÝÚPCMD_FAST_READÕÚPCMD_NORM_READÇÚP
CMD_DREAD&ÚP
CMD_2READ8ÚP
CMD_QREADÚP
CMD_4READ6ÚPCMD_BURST_READqÚPBURST_READ_MODE_8ÚPBURST_READ_MODE_16RÚPBURST_READ_MODE_32TÚPBURST_READ_MODE_64OÚP    CMD_TRIGRÚPCMD_WRITE_ENABLEçÚPCMD_WRITE_DISABLEÚPFLASH_X1_MODE×ÚPFLASH_X2_MODEÖÚPFLASH_X4_MODEÔÚPQUAD_ENABLE_PosëÚPQUAD_ENABLE_MskòÚPWrite_Enable_Latch_PosÚPWrite_Enable_Latch_MskÚPWrite_In_Process_Pos³ÚPWrite_In_Process_MskºÚPLong_Time_Op_Pos~ÚP
PAGE_SIZEÚPSECTOR_SIZEKÚ8_flash_ids¥Ú "2manufacturer_id¶Ú8
<unnamed>SÚ <"2dnÚ8
<unnamed>QÚ "2memory_type_idÚ "2memory_density_idÃÚ <"2uidÚFLASH_IDS_TÚ
flash_idsÚ#FMC_EnterDeepPowerDownModeåÚ,"2fmc¦Ú"FMC_ExitDeepPowerDownModeKÚ,"2fmc¤ÚFMC_IsBusyWorking]Ú,"2fmc¢Ú,fmcÚFMC_GetFlashUniqueIdYÚ,fmcÚFMC_GetFlashJedecId÷Ú,fmcÚFMC_SetFlashCapacityCÚ,fmcÚ!FMC_GetFlashCodeAreaSizeæÚ,fmcÚ,adrÚFMC_EraseSector5Ú,fmcÚ ,addr4ÚFMC_EraseBlock32kæÚ,fmcÚ ,addr4ÚFMC_EraseBlock64káÚ,fmcÚ ,
addr<Ú,
lenÚFMC_EraseCodeAreaÚ,fmcÚ ,
mode2ÚInitIcacheÚ,fmcÚ ,
addr<Ú,
count¬Ú,chksum:ÚFMC_GetCrc32SumÃÚ,fmcÚ,adrÚ,szæÚBlankCheckÚ,fmcÚ,adrÚ,szæÚ,bufÚVerifygÚ,fmcÚ,adrÚ,szæÚ,bufÚProgramPage}Ú,fmcÚ,cmd¬ÚFMC_ReadStatusRegsÚ,fmcÚFMC_WriteEnableCÚ,fmcÚFMC_WriteDisableÔÚ,fmcÚ,opsÚ,
bufÚFMC_WriteStatusRegâÚ,fmcÚ ,
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addr<Ú ,dataDÚFMC_WriteByteúÚ,fmcÚ ,
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lenÚFMC_WriteStreamÚ,fmcÚ ,
Addr\Ú,cmd¬Ú,bufÚ,
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lenÚFMC_WriteInfoAreaÚ,fmcÚFMC_EraseInfoAreaÚ,fmcÚ ,
mode2Ú,enhanceÚFMC_SetFlashModeôÚ,fmcÚFMC_ExitEnhanceMode¼Ú,fmcÚ ,
mode2ÚFMC_EnterEnhanceModeVÚ,fmcÚFMC_EnableAutoDpÿÚ,fmcÚFMC_DisableAutoDpÚ,fmcÚ,
cntÚFMC_SetRdpWaitCountÚ,fmcÚ,
cntÚFMC_SetDpWaitCountÚ,fmcÚ ,"IRQnhÚ,"    NewStateÚFMC_SetSuspendIrqWÚ,fmcÚ,
timeoutÊÚFMC_SetSuspendTimeoutÚP__PAN_DMAC_H__9ÚPDMAC_CHANNEL_NUMBERÚPDMA_INVLID_CHANNELXÚ"PDMAC_TransferType_Mem2MemoÚ"PDMAC_TransferType_Mem2PergÚ"PDMAC_TransferType_Per2MemgÚ"PDMAC_TransferType_Per2Per_ÚPDMAC_FlowControl_DMAÚ$PDMAC_FlowControl_Peripheral=ÚPDMAC_BurstLen_1zÚPDMAC_BurstLen_4wÚPDMAC_BurstLen_8sÚPDMAC_BurstLen_16BÚPDMAC_BurstLen_32DÚPDMAC_BurstLen_64?ÚPDMAC_BurstLen_128ÚPDMAC_BurstLen_256
Ú"PDMAC_AddrChange_Increment`Ú"PDMAC_AddrChange_DecrementnÚ!PDMAC_AddrChange_NoChangeÚPDMAC_DataWidth_8&ÚPDMAC_DataWidth_16õÚPDMAC_DataWidth_32÷ÚPDMAC_DataWidth_64òÚPDMAC_DataWidth_128¿ÚPDMAC_DataWidth_256½Ú PDMAC_Peripheral_I2C0_Tx¥Ú PDMAC_Peripheral_I2C0_Rx§Ú PDMAC_Peripheral_SPI0_TxwÚ PDMAC_Peripheral_SPI0_RxyÚ!PDMAC_Peripheral_UART0_Tx%Ú!PDMAC_Peripheral_UART0_Rx'Ú PDMAC_Peripheral_SPI1_TxvÚ PDMAC_Peripheral_SPI1_RxxÚ!PDMAC_Peripheral_UART1_Tx$Ú!PDMAC_Peripheral_UART1_Rx&ÚPDMAC_Peripheral_ADCþÚPDMAC_Peripheral_USB_RxÚPDMAC_Peripheral_USB_Tx«Ú#PDMAC_HandshakePolarity_Low·Ú$PDMAC_HandshakePolarity_HighgÚPDMAC_Handshake_DefaultÚ PDMAC_Handshake_SoftwareøÚ PDMAC_Handshake_HardwareÚ$PDMAC_LockLevel_Tfr_Complete}Ú&PDMAC_LockLevel_Block_CompleteºÚ,P$DMAC_LockLevel_Transaction_CompleteÚPDMAC_ChannelPriority_0ÚPDMAC_ChannelPriority_1ÚPDMAC_ChannelPriority_2ÚPDMAC_ChannelPriority_3~ÚPDMAC_ChannelPriority_4}ÚPDMAC_ChannelPriority_5|ÚPDMAC_ChannelPriority_6{ÚPDMAC_ChannelPriority_7zÚPDMAC_CHANNELALL_MASKÒÚPDMAC_FLAG_INDEX_TFRõÚPDMAC_FLAG_INDEX_BLKÚPDMAC_FLAG_INDEX_SRCTFRÚPDMAC_FLAG_INDEX_DSTTFRÚPDMAC_FLAG_INDEX_ERRøÚPDMAC_FLAG_MASK_TFRCÚPDMAC_FLAG_MASK_BLKVÚPDMAC_FLAG_MASK_SRCTFRUÚPDMAC_FLAG_MASK_DSTTFRRÚPDMAC_FLAG_MASK_ERRFÚPDMAC_FLAG_MASK_ALLVÚ$8__DMAC_ChannelConfigTypeDefÚ 
"à3CTL_LÚ 
"à3CTL_H"Ú 
"à3CFG_L1Ú 
"à3CFG_H5Ú$__DMAC_ChannelConfigTypeDefÙÚ"8DMAC_ChannelConfigTypeDef_Ú 
"æ3
IntEnable,Ú 
"æ3 DataWidthDstóÚ 
"æ3 DataWidthSrcöÚ 
"æ3AddrChangeDstªÚ 
"æ3AddrChangeSrcÚ 
"æ3BurstLenDst@Ú 
"æ3BurstLenSrcCÚ 
"æ3GatherEnSrcdÚ 
"æ3 ScatterEnDstäÚ 
"æ3__Rev0Ú 
"æ3 TransferType±Ú 
"æ3FlowControl!Ú 
"æ3__Rev1Ú 
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BlockSizeÚ 
"æ3Done"Ú 
"æ3__Rev3Ú 
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FifoEmptyÚ 
"æ3 HandshakeDstæÚ 
"æ3 HandshakeSrcéÚ 
"æ3LockBusïÚ 
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"æ3 LockBusLevelíÚ 
"æ3LockChannelLevelVÚ 
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"æ3__Rev6Ú 
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"æ3AutoReloadDst{Ú 
"æ3FlowControlModeÚ 
"æ3    FifoModeÚ 
"æ3ProtectControlÒÚ 
"æ3__Rev7Ú 
"æ3PeripheralSrcbÚ 
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"æ3__Rev8Ú"DMAC_ChannelConfigTypeDefÚDMAC_IsChannelValidõÚ,"4dmaµÚ,
"4ChIdx!ÚPDMAC_ChannelMaskòÚDMAC_CombinedIntStatusÚ,"4dma±Ú,
"4FlgMsk§ÚDMAC_StatusFlagdÚ,"4dma®Ú,
"4ChIdxÚ,
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"4ChIdxÚ,
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"¡4ChIdxÚ,
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DMAC_InitÎÚ,dmaÚDMAC_DeInit!Ú,dmaÚ,
ChIdxÚ,
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ChIdxÚ,
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ChIdxÚ,ConfigoÚDMAC_SetChannelConfigÚ,dmaÚ,
ChIdxÚ,ConfigoÚDMAC_GetChannelConfigÚ,dmaÚ,
ChIdxÚ,Src£Ú,Dst Ú,
LenºÚDMAC_StartChannelÚ,dmaÚ,
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ChIdxÚDMAC_StopChannelõÚ,dmaÚ,
ChIdxÚ"DMAC_GetXferredBlockCount^Ú,dmaÚDMAC_AcquireChannelËÚ,dmaÚ,
ChIdxÚDMAC_ReleaseChannelÔÚ,dmaÚ"DMAC_IsAllChannelReleasedÚP__PAN_GPIO_H__ÚP GPIO_PIN_MAXùÚ8"_GPIO_ModeDef$Ú"Ò4GPIO_MODE_INPUTÚ"Ò4GPIO_MODE_OUTPUT²Ú"Ò4GPIO_MODE_OPEN_DRAINÚ"Ò4GPIO_MODE_QUASI"Ú GPIO_ModeDefÇÚ8"_GPIO_IntAttrDefÝÚ"Ø4GPIO_INT_RISING Ú"Ø4GPIO_INT_FALLINGÚÚ"Ø4GPIO_INT_BOTH_EDGE2Ú"Ø4GPIO_INT_HIGH½Ú"Ø4 GPIO_INT_LOWíÚGPIO_IntAttrDefÚ8"_GPIO_ClkSrcDefcÚ""ß4GPIO_DBCTL_DBCLKSRC_RCL¼Ú#"ß4GPIO_DBCTL_DBCLKSRC_HCLKyÚGPIO_ClkSrcDefÚ8"_GPIO_ClkSelDefgÚ "ã4GPIO_DBCTL_DBCLKSEL_1pÚ "ã4GPIO_DBCTL_DBCLKSEL_2oÚ "ã4GPIO_DBCTL_DBCLKSEL_4mÚ "ã4GPIO_DBCTL_DBCLKSEL_8iÚ!"ã4GPIO_DBCTL_DBCLKSEL_168Ú!"ã4GPIO_DBCTL_DBCLKSEL_32:Ú!"ã4GPIO_DBCTL_DBCLKSEL_645Ú""ã4GPIO_DBCTL_DBCLKSEL_128Ú""ã4GPIO_DBCTL_DBCLKSEL_256Ú""ã4GPIO_DBCTL_DBCLKSEL_512Ú#"ã4GPIO_DBCTL_DBCLKSEL_1024ÔÚ#"ã4GPIO_DBCTL_DBCLKSEL_2048ÍÚ#"ã4GPIO_DBCTL_DBCLKSEL_4096ÈÚ#"ã4GPIO_DBCTL_DBCLKSEL_8192ÇÚ$"ã4GPIO_DBCTL_DBCLKSEL_16384Ú$"ã4GPIO_DBCTL_DBCLKSEL_32768ÚGPIO_ClkSelDef
ÚPGPIO_PIN_ADDRÂÚPP00ÚPP01ÚPP02ÚPP03ÚPP04ÚPP05ÚPP06ÚPP07ÚPP10ÚPP11ÚPP12ÚPP13ÚPP14ÚPP15ÚPP16ÚPP17 ÚPP20ÚPP21ÚPP22ÚPP23ÚPP24ÚPP25ÚPP26 ÚPP27ÚPP30ÚPP31ÚGPIO_ClrIntFlagÚ,"5gpio3Ú,
"5u32PinMaskWÚGPIO_ClrAllIntFlagcÚ,"5gpio0ÚGPIO_DisableDebounceeÚ,"5gpio.Ú,
"5u32PinMaskRÚGPIO_EnableDebounceÔÚ,"5gpio+Ú,
"5u32PinMaskOÚ GPIO_DisableDigitalPath9Ú,"5gpio(Ú,
"5u32PinMaskLÚGPIO_EnableDigitalPath¨Ú,"5gpio%Ú,
"5u32PinMaskIÚGPIO_DisablePullupPathwÚ,"¡5gpio"Ú,
"¡5u32PinMaskFÚGPIO_EnablePullupPathæÚ,"¤5gpioÚ,
"¤5u32PinMaskCÚ!GPIO_DisablePulldownPath Ú,"§5gpioÚ,
"§5u32PinMask@Ú GPIO_EnablePulldownPathÚ,"ª5gpioÚ,
"ª5u32PinMask=ÚGPIO_DisableDoutMaskbÚ,"5gpioÚ,
"5u32PinMask:ÚGPIO_EnableDoutMaskÑÚ,"°5gpioÚ,
"°5u32PinMask7ÚGPIO_GetIntFlagÚ,"³5gpioÚ,
"³5u32PinMask4ÚGPIO_SetDebounceTime^Ú,""¶5clksrc/Ú,""¶5clksel3ÚGPIO_GetInDataùÚ,"¹5gpio
ÚGPIO_SetOutDatajÚ,"»5gpioÚ,
"»5data+ÚGPIO_GetOutDatavÚ,"¾5gpioÚGPIO_ToggleîÚ,"À5gpioÚ,
"À5u32PinMask'ÚGPIO_EnableIntØÚ,"Ã5gpioÚ,
"Ã5u32Pin¸Ú,""Ã5IntAttribsÚGPIO_DisableIntiÚ,"Ç5gpioüÚ,
"Ç5u32Pin´ÚPGPIO_EnableEINT0vÚPGPIO_DisableEINT0ÚPGPIO_EnableEINT1uÚPGPIO_DisableEINT1Ú ,gpioÚ,
PinMaskÚ ,"Mode=Ú GPIO_SetModeÚP__PAN_SPI_H__dÚ8"SPI_Irq:Ú "Ó5SPI_IRQ_TX_HALF_EMPTYÿÚ"Ó5SPI_IRQ_RX_HALF_FULL_Ú"Ó5SPI_IRQ_RX_TIMEOUTéÚ"Ó5SPI_IRQ_RX_OVERRUNßÚ"Ó5SPI_IRQ_ALLNÚSPI_IrqDefgÚ8"    SPI_RoleÒÚ"Ú5SPI_RoleMastergÚ"Ú5SPI_RoleSlaveÚÚSPI_RoleDefÿÚ8"SPI_DataFrameSizeRÚ"Þ5SPI_DataFrame_4bÚ"Þ5SPI_DataFrame_5bÚ"Þ5SPI_DataFrame_6bÚ"Þ5SPI_DataFrame_7bÚ"Þ5SPI_DataFrame_8bÿÚ"Þ5SPI_DataFrame_9bþÚ"Þ5SPI_DataFrame_10bÔÚ"Þ5SPI_DataFrame_11bÓÚ"Þ5SPI_DataFrame_12bÒÚ"Þ5SPI_DataFrame_13bÑÚ"Þ5SPI_DataFrame_14bÐÚ"Þ5SPI_DataFrame_15bÏÚ"Þ5SPI_DataFrame_16bÎÚSPI_DataFrameSizeDefÚ8"SPI_BaudRateDiv+Ú"í5SPI_BaudRateDiv_2Ú"í5SPI_BaudRateDiv_4Ú"í5SPI_BaudRateDiv_6Ú"í5SPI_BaudRateDiv_8Ú"í5SPI_BaudRateDiv_16YÚ"í5SPI_BaudRateDiv_32[Ú"í5SPI_BaudRateDiv_48TÚ"í5SPI_BaudRateDiv_64VÚ"í5SPI_BaudRateDiv_96QÚ"í5SPI_BaudRateDiv_128#Ú"í5SPI_BaudRateDiv_160'Ú"í5SPI_BaudRateDiv_192"Ú"í5SPI_BaudRateDiv_224&Ú"í5SPI_BaudRateDiv_240(Ú"í5SPI_BaudRateDiv_250'ÚSPI_BaudRateDivDefXÚPSPI_BAUD_RATE_DIVuÚ8" SPI_ClockPolEÚ"ÿ5SPI_ClockPolarityLowÂÚ "ÿ5SPI_ClockPolarityHighrÚSPI_ClockPolDefrÚ8"SPI_ClockPhase{Ú""6SPI_ClockPhaseFirstEdgeOÚ#"6SPI_ClockPhaseSecondEdgeùÚSPI_ClockPhaseDef¨Ú8"SPI_FrameFormatÚ"6SPI_FormatMotorolaùÚ"6 SPI_FormatTiÚ"6SPI_FormatMicrowireÚSPI_FrameFormatDef/Ú8"SPI_WireNumÚ"6SPI_WireNumThreeïÚ"6SPI_WireNumFourMÚSPI_WireNumDefÄÚ8"SPI_CmdDat3Ú"6SPI_CommandSelectÚ"6SPI_DataSelectÔÚSPI_CmdDatDef`Ú8"SPI_WriteReadSel©Ú"6SPI_3WireReadfÚ"6SPI_3WireWriteÕÚSPI_WriteReadSelDefÖÚ8
<unnamed>QÚ ""6    SPI_roleÙÚ ""6SPI_dataFrameSizeYÚ ""6    SPI_CPOL]Ú ""6    SPI_CPHAoÚ "6SPI_baudRateDivEÚ ""6SPI_formatþÚSPI_InitTypeDefSÚSPI_EnableSpiÚ," 6SPIxmÚ
" 6tmpregpÚSPI_DisableSpiÚ,"£6SPIxjÚ
"£6tmpregmÚSPI_IsSpiEnabledöÚ,"¦6SPIxgÚ
"¦6tmpregjÚSPI_EnableDmaTxfÚ,"©6SPIxdÚ
"©6tmpreggÚSPI_DisableDmaTx÷Ú,"¬6SPIxaÚ
"¬6tmpregdÚSPI_IsDmaTxEnabled@Ú,"¯6SPIx^Ú
"¯6tmpregaÚSPI_EnableDmaRxhÚ,"²6SPIx[Ú
"²6tmpreg^ÚSPI_DisableDmaRxùÚ,"µ6SPIxXÚ
"µ6tmpreg[ÚSPI_IsDmaRxEnabledBÚ,"¸6SPIxUÚ
"¸6tmpregXÚ SPI_SendDataÚ,"»6SPIxRÚ,
"»6DataJÚSPI_ReceiveDataNÚ,"¾6SPIxOÚSPI_EnableIrqÚ,"À6SPIxMÚ,""À6irq`Ú
"À6tmpregPÚSPI_DisableIrqÚ,"Ä6SPIxIÚ,""Ä6irq\Ú
"Ä6tmpregLÚSPI_IsIrqEnabledöÚ,"È6SPIxEÚ,""È6irqXÚ
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"Ì6tmpregDÚSPI_IsIrqActiveGÚ,"Ï6SPIx>Ú,""Ï6irqQÚ
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"Ó6tmpreg=Ú SPI_ClearIrq~Ú,"×6SPIx6Ú,""×6irqIÚ
"×6tmpreg9ÚSPI_GetRawActiveIrq±Ú,"Û6SPIx2Ú
"Û6tmpreg5ÚSPI_IsTxFifoEmptylÚ,"Þ6SPIx/Ú
"Þ6tmpreg2ÚSPI_IsTxFifoFullêÚ,"á6SPIx,Ú
"á6tmpreg/ÚSPI_IsRxFifoEmptynÚ,"ä6SPIx)Ú
"ä6tmpreg,ÚSPI_IsRxFifoFullìÚ,"ç6SPIx&Ú
"ç6tmpreg)ÚSPI_IsBusy6Ú,"ê6SPIx#Ú
"ê6tmpreg&ÚSPI_TxLsbEnableWÚ,"í6SPIx Ú,"í6enable.ÚSPI_RxLsbEnableYÚ,"ð6SPIxÚ,"ð6enable+ÚSPI_SetWireNumÚ,"ó6SPIxÚ,""ó6num)ÚSPI_DataCmdLineEnable"Ú,"ö6SPIxÚ,""ö6    NewStateAÚSPI_DataCmdSelCmdDat¢Ú,"ù6SPIxÚ,""ù6cmdDat ÚSPI_WriteReadCtrlkÚ,"ü6SPIxÚ ,""ü6wrÚ ,SPIxeÚ,SPI_InitStructQÚ    SPI_InitùÚP__PAN_UART_H__Ú8"UART_TxTriggerhÚ"7UART_TX_FIFO_EMPTYEÚ!"7UART_TX_FIFO_TWO_CHARSÚ$"7UART_TX_FIFO_QUARTER_FULLÚ!"7UART_TX_FIFO_HALF_FULLÚUART_TxTriggerDefÚ8"UART_RxTriggerjÚ "7UART_RX_FIFO_ONE_CHARkÚ$"7UART_RX_FIFO_QUARTER_FULLÚ!"7UART_RX_FIFO_HALF_FULLÚ*"7 UART_RX_FIFO_TWO_LESS_THAN_FULL
ÚUART_RxTriggerDefÚ8"UART_LineCtrlíÚ"7Uart_Line_5n1EÚ"7Uart_Line_5n1_5Ú"7Uart_Line_5e1NÚ"7Uart_Line_5e1_5¶Ú"7Uart_Line_5o1DÚ"7Uart_Line_5o1_5¬Ú"7Uart_Line_5s1@Ú"7Uart_Line_5s1_5¨Ú"7Uart_Line_5m1FÚ"7Uart_Line_5m1_5®Ú"7Uart_Line_6n1DÚ"7Uart_Line_6n2CÚ"7Uart_Line_6e1MÚ"7Uart_Line_6e2LÚ"7Uart_Line_6o1CÚ"7Uart_Line_6o2BÚ"7Uart_Line_6s1?Ú"7Uart_Line_6s2>Ú"7Uart_Line_6m1EÚ"7Uart_Line_6m2DÚ"7Uart_Line_7n1CÚ"7Uart_Line_7n2BÚ"7Uart_Line_7e1LÚ"7Uart_Line_7e2KÚ"7Uart_Line_7o1BÚ"7Uart_Line_7o2AÚ"7Uart_Line_7s1>Ú"7Uart_Line_7s2=Ú"7Uart_Line_7m1DÚ"7Uart_Line_7m2CÚ"7Uart_Line_8n1BÚ"7Uart_Line_8n2AÚ"7Uart_Line_8e1KÚ"7Uart_Line_8e2JÚ"7Uart_Line_8o1AÚ"7Uart_Line_8o2@Ú"7Uart_Line_8s1=Ú"7Uart_Line_8s2<Ú"7Uart_Line_8m1CÚ"7Uart_Line_8m2BÚUART_LineCtrlDefÚ8"    UART_IrqèÚ!"¹7UART_IRQ_RECV_DATA_AVLîÚ"¹7UART_IRQ_THR_EMPTYÚ"¹7UART_IRQ_LINE_STATUSrÚ "¹7UART_IRQ_MODEM_STATUS&Ú"¹7 UART_IRQ_ALLÚUART_IrqDefÚ8"UART_EventÚ"À7UART_EVENT_MODEMÖÚ"À7UART_EVENT_NONEÚ"À7UART_EVENT_THR_EMPTYdÚ"À7UART_EVENT_DATA0Ú"À7UART_EVENT_LINE"Ú"À7UART_EVENT_TIMEOUTÚUART_EventDef;Ú8"UART_LineStatusúÚ"È7UART_LINE_DATA_RDY.Ú "È7UART_LINE_OVERRUN_ERRÚ"È7UART_LINE_PARITY_ERRqÚ"È7UART_LINE_FRAME_ERRáÚ"È7UART_LINE_BREAK_INTåÚ"È7UART_LINE_THREkÚ"È7UART_LINE_TXSR_EMPTYSÚ "È7UART_LINE_RX_FIFO_ERRÚ"È7UART_LINE_ADDR_RCVDëÚUART_LineStatusDef'Ú8"UART_ModemStatusÚ"Ó7UART_MODEM_DCTSÚ"Ó7UART_MODEM_DDSRÚ"Ó7UART_MODEM_TERIÚ"Ó7UART_MODEM_DDCD8Ú"Ó7UART_MODEM_CTS_Ú"Ó7UART_MODEM_DSR`Ú"Ó7UART_MODEM_RI°Ú"Ó7UART_MODEM_DCD~ÚUART_ModemStatusDef»Ú8
<unnamed>QÚ 
"Ý7UART_BaudRateøÚ ""Ý7UART_LineCtrlÎÚUART_InitTypeDefÚUART_EnableStickParityoÚ,"á7UARTxÙÚ UART_DisableStickParityÚ,"ã7UARTx×ÚUART_GetLineStatus    Ú,"å7UARTxÕÚUART_GetModemStatusÚ,"ç7UARTxÓÚUART_EnableFifopÚ,"é7UARTxÑÚUART_DisableFifoÚ,"ë7UARTxÏÚUART_IsFifoEnabledJÚ,"í7UARTxÍÚUART_ResetRxFifoèÚ,"ï7UARTxËÚ
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"¶8addr,Ú UART_SetTransmitAddressçÚ,"¹8UARTxÚ,
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"Ë9addrÚ ,I2CxÚ,I2C_InitStructÚ    I2C_Init'Ú ,I2CxÚ,AddressÚI2C_Set7bitAddress?Ú ,I2CxÚ,Address    ÚI2C_Set10bitAddressÚ ,I2CxÚ,
    I2C_FLAGÚI2C_GetFlagStatusÚ ,I2CxÚ,I2C_ITÚI2C_ClearITPendingBit9Ú ,I2CxÚ,    WriteBufÚ ,
Size<Ú
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Size<Ú    I2C_Read?ÚP__PAN_TIMER_H__ËÚ8"_TIMER_CntModeDef¥Ú"æ9TIMER_ONESHOT_MODEÚ"æ9TIMER_PERIODIC_MODEãÚ"æ9TIMER_TOGGLE_MODEtÚ "æ9TIMER_CONTINUOUS_MODEÚTIMER_CntModeDefHÚ8"_TIMER_CapModeDef¶Ú+"ì9!TIMER_CAPTURE_FREE_COUNTING_MODE·Ú."ì9$TIMER_CAPTURE_TRIGGER_COUNTING_MODE¿Ú+"ì9!TIMER_CAPTURE_COUNTER_RESET_MODEÚTIMER_CapModeDefYÚ8"_TIMER_CapEdgeDefÆÚ%"ñ9TIMER_CAPTURE_FALLING_EDGE¹Ú$"ñ9TIMER_CAPTURE_RISING_EDGEìÚ""ñ9TIMER_CAPTURE_BOTH_EDGEÚ1"ñ9'TIMER_CAPTURE_FALLING_THEN_RISING_EDGEèÚ1"ñ9'TIMER_CAPTURE_RISING_THEN_FALLING_EDGEèÚTIMER_CapEdgeDefiÚ8"_TIMER_EvtCntEdgeDefÚ%"ø9TIMER_COUNTER_FALLING_EDGE¦Ú$"ø9TIMER_COUNTER_RISING_EDGEÙÚTIMER_EvtCntEdgeDef#Ú8"_TIMER_CapSrcDefÚ'"ü9TIMER_CAPTURE_SOURCE_EXT_PIN´Ú*"ü9 TIMER_CAPTURE_SOURCE_32K_OUTPUTåÚTIMER_CapSrcDef¸Ú8"_TIMER0_CmpSelDefÛÚ"":TMR0_COMPARATOR_SEL_CMP÷Ú#":TMR0_COMPARATOR_SEL_CMP1ÄÚ#":TMR0_COMPARATOR_SEL_CMP2ÃÚTIMER0_CmpSelDef~ÚPFIXED_DEVIATION;ÚTIMER_EnableCaptureÓÚ,":timerÄÚ,"":capMode Ú,"":capEdge1ÚTIMER_DisableCapturedÚ,":timerÀÚ!TIMER_EnableEventCounter»Ú,":timer¾Ú,"":evtCntEdgeåÚ"TIMER_DisableEventCounterLÚ,":timer»ÚTIMER_SetPrescaleValueÚ,":timer¹Ú,
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"¹:timer_flagÚTIMER_GetWakeupFlagçÚ,"¼:timerÚTIMER_ClearWakeupFlagÚ,"¾:timerÚ,
"¾:
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"Ð:u32CntModeÚ,timer¦Ú,"cntModeïÚ,
u32FreqiÚTIMER_OpenbÚ,timer¦ÚTIMER_CloseüÚ,timer¦Ú,
u32UsecgÚTIMER_DelayÚ,timer¦Ú,"cmp_seqÔÚ,
    u32ValueøÚTIMER_SetCmpValueÚP__PAN_PWM_H__\ÚPPWM_CHANNEL_NUMÚPPWM_CH0¯ÚPPWM_CH1®ÚPPWM_CH2ÚPPWM_CH3¬ÚPPWM_CH4«ÚPPWM_CH5ªÚPPWM_CH6©ÚPPWM_CH7¨Ú8"_PWM_ClkSrcSelDefvÚ"ê:PWM_CLK_SRC_APBóÚ"ê:PWM_CLK_SRC_RCLåÚ"ê:PWM_CLK_SRC_XTLÎÚPWM_ClkSrcSelDefÚ8"_PWM_ClkDivDef¥Ú"ï:PWM_CLK_DIV_1Ú"ï:PWM_CLK_DIV_2Ú"ï:PWM_CLK_DIV_4Ú"ï:PWM_CLK_DIV_8Ú"ï:PWM_CLK_DIV_16aÚ"ï:PWM_CLK_DIRECTOÚPWM_ClkDivDefHÚ8"_PWM_AlignedTypeDefÚ"÷:PWM_EDGE_ALIGNEDÏÚ"÷:PWM_CENTER_ALIGNEDÚPWM_AlignedTypeDef%Ú8"_PWM_IntPeriodTypeDef¤Ú#"û:PWM_PERIOD_INT_UNDERFLOWÚ#"û:PWM_PERIOD_INT_MATCH_CNRÚPWM_IntPeriodTypeDefGÚ8"_PWM_OperateTypeDeffÚ!"ÿ:OPERATION_EDGE_ALIGNEDþÚ#"ÿ:OPERATION_CENTER_ALIGNEDNÚ+"ÿ:!OPERATION_PRECISE_CENTER_ALIGNEDÔÚPWM_OperateTypeDef    Ú8"_PWM_CntModeDef6Ú";PWM_CNTMODE_ONE_SHOT¹Ú"";PWM_CNTMODE_AUTO_RELOADãÚPWM_CntModeDefÙÚPWM_EnableOutput©Ú,";pwmÚ,
";u32ChannelMask¿ÚPWM_DisableOutput:Ú,";pwmÚ,
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";u32ChannelNumÚ,
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";u32ChannelNum
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"¤;u32ChannelNumÚPWM_EnablePeriodInt¦Ú,"§;pwmsÚ,
"§;u32ChannelNumþÚPWM_DisablePeriodInt7Ú,"ª;pwmpÚ,
"ª;u32ChannelNumûÚPWM_ClearPeriodIntFlagÚ,";pwmmÚ,
";u32ChannelNumøÚPWM_GetPeriodIntFlagQÚ,"°;pwmjÚ,
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"¶;u32ChannelNumïÚPWM_ClearZeroIntFlagMÚ,"¹;pwmaÚ,
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u32ChannelNumÚ,
 u32Frequency;Ú,
 u32DutyCycleWÚ,"OperateTypeBÚ PWM_ConfigOutputChannelÇÚ,pwmwÚ,
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u32EnableResetÚ,
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u32CmpValueÒÚ,
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    reg_addrÚPHY_SingleRegReadzÚ,
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addr<ÚEFUSE_ReadByteåÚ,efuse¯Ú ,
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"ô>cnt@ÚTRIM_GetIdealCntÚ,"÷>trim¶ÚTRIM_GetRealCntrÚ,"ù>trim´Ú TRIM_IsIntStatusOccuredûÚ,"û>trim²Ú,
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"?codeQÚTRIM_GetCoarseCode=Ú,"?trimÚTRIM_SetFineCodeÚ,"?trimÚ,
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ÚPGPIO_P1_PIN_NUM    ÚPGPIO_P2_PIN_NUMÚPGPIO_P3_PIN_NUMÚPGPIO_INTEN_MASK_BASEÚPGPIO_INTTYPE_MASK_BASEßÚ P0_0æÚ P0_1åÚ P0_2äÚ P0_3ãÚ P0_4âÚ P0_5áÚ P0_6àÚ P0_7ßÚ P1_0åÚ P1_1äÚ P1_2ãÚ P1_3âÚ P1_4áÚ P1_5àÚ P1_6ßÚ P1_7ÞÚ P2_0äÚ P2_1ãÚ P2_2âÚ P2_3áÚ P2_4àÚ P2_5ßÚ P2_6ÞÚ P2_7ÝÚ P3_0ãÚ P3_1âÚHAL_GPIO_PinIdOÚ$HAL_GPIO_MODE_INPUT_DIGITALÚ#HAL_GPIO_MODE_INPUT_ANALOGâÚ&HAL_GPIO_MODE_OUTPUT_PUSHPULL°Ú'HAL_GPIO_MODE_OUTPUT_OPENDRAINÚ*"HAL_GPIO_MODE_QUASI_BIDIRECTIONALÚÚHAL_GPIO_Mode ÚHAL_GPIO_PULL_DISABLEÚHAL_GPIO_PULL_UPÚÚHAL_GPIO_PULL_DOWNCÚHAL_GPIO_PullÚHAL_GPIO_LEVEL_LOWNÚHAL_GPIO_LEVEL_HIGHÚHAL_GPIO_Level+ÚHAL_GPIO_INT_RISINGÿÚHAL_GPIO_INT_FALLINGÌÚHAL_GPIO_INT_BOTH_EDGE$ÚHAL_GPIO_INT_HIGH¯ÚHAL_GPIO_INT_LOWßÚHAL_GPIO_INT_DISABLEÕÚHAL_GPIO_IntModeoÚHAL_GPIO_CallbackFunc|Ú<hHAL_GPIO_CallbackArraykÚ8
<unnamed>QÚ ""@mode.Ú ""@pullÚ ""@level¼ÚHAL_GPIO_InitTypeDefÒÚ8
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pinIDÚ,"    debounceuÚ HAL_GPIO_SetIntDebounce|ÚP__PAN_HAL_UART_H__ÖÚHAL_UART_EVT_TX_FINISHèÚHAL_UART_EVT_RX_FINISHêÚ&HAL_UART_EVT_CONTI_RX_TIMEOUTÚ( HAL_UART_EVT_CONTI_RX_BUFF_FULLÚ#HAL_UART_EVT_RX_ERR_PARITYÚ"HAL_UART_EVT_RX_ERR_FRAMEòÚ$HAL_UART_EVT_RX_ERR_OVERRUN(ÚHAL_UART_EVT_MAXÚÚHAL_UART_EventOptÛÚ#HAL_UART_INT_RECV_DATA_AVLÅÚHAL_UART_INT_THR_EMPTYÜÚ!HAL_UART_INT_LINE_STATUSIÚ"HAL_UART_INT_MODEM_STATUSýÚHAL_UART_INT_ALLëÚHAL_UART_INT_DISABLEÈÚHAL_UART_IntModeOpt)ÚHAL_UART_TX_FIFO_EMPTYåÚ#HAL_UART_TX_FIFO_TWO_CHARS¢Ú&HAL_UART_TX_FIFO_QUARTER_FULL°Ú#HAL_UART_TX_FIFO_HALF_FULL¿ÚHAL_UART_TxTrigOptyÚ"HAL_UART_RX_FIFO_ONE_CHARÚ&HAL_UART_RX_FIFO_QUARTER_FULL²Ú#HAL_UART_RX_FIFO_HALF_FULLÁÚ,$HAL_UART_RX_FIFO_TWO_LESS_THAN_FULL°ÚHAL_UART_RxTrigOpt{ÚHAL_UART_DMA_TX3ÚHAL_UART_DMA_RX5ÚHAL_UART_DmaDirOptªÚHAL_UART_FMT_5_N_1RÚHAL_UART_FMT_5_N_1_5ºÚHAL_UART_FMT_5_E_1[ÚHAL_UART_FMT_5_E_1_5ÃÚHAL_UART_FMT_5_O_1QÚHAL_UART_FMT_5_O_1_5¹ÚHAL_UART_FMT_5_S_1MÚHAL_UART_FMT_5_S_1_5µÚHAL_UART_FMT_5_M_1SÚHAL_UART_FMT_5_M_1_5»ÚHAL_UART_FMT_6_N_1QÚHAL_UART_FMT_6_N_2PÚHAL_UART_FMT_6_E_1ZÚHAL_UART_FMT_6_E_2YÚHAL_UART_FMT_6_O_1PÚHAL_UART_FMT_6_O_2OÚHAL_UART_FMT_6_S_1LÚHAL_UART_FMT_6_S_2KÚHAL_UART_FMT_6_M_1RÚHAL_UART_FMT_6_M_2QÚHAL_UART_FMT_7_N_1PÚHAL_UART_FMT_7_N_2OÚHAL_UART_FMT_7_E_1YÚHAL_UART_FMT_7_E_2XÚHAL_UART_FMT_7_O_1OÚHAL_UART_FMT_7_O_2NÚHAL_UART_FMT_7_S_1KÚHAL_UART_FMT_7_S_2JÚHAL_UART_FMT_7_M_1QÚHAL_UART_FMT_7_M_2PÚHAL_UART_FMT_8_N_1OÚHAL_UART_FMT_8_N_2NÚHAL_UART_FMT_8_E_1XÚHAL_UART_FMT_8_E_2WÚHAL_UART_FMT_8_O_1NÚHAL_UART_FMT_8_O_2MÚHAL_UART_FMT_8_S_1JÚHAL_UART_FMT_8_S_2IÚHAL_UART_FMT_8_M_1PÚHAL_UART_FMT_8_M_2OÚHAL_UART_FormatOptrÚ 8_HAL_UART_HandleTypeDeflÚHAL_UART_HandleTypeDef    ÚHAL_UART_CallbackFuncoÚ8
<unnamed>QÚ 
"A    baudRateÎÚ ""Aformat\ÚHAL_UART_InitTypeDefÅÚ8
<unnamed>QÚ ""AtxTrigLevel]Ú ""ArxTrigLevel_Ú ""AIRQnÚ "AIrqPriorityeÚ "AcontinuousRxModeCÚ "A callbackFunc#ÚHAL_UART_IntTypeDef0Ú "ÿ@pUartxìÚ "ÿ@initObjÚ "ÿ@ interruptObjPÚ "ÿ@pTxBuffPtrsÚ "ÿ@txXferSizeXÚ "ÿ@txXferCountèÚ "ÿ@pRxBuffPtruÚ "ÿ@rxXferSizeZÚ "ÿ@rxXferCountêÚ "ÿ@    isTxBusy6Ú "ÿ@    isRxBusy8Ú "ÿ@txDmaChÚÚ "ÿ@rxDmaChÜÚ 
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timeoutÊÚHAL_UART_ReceiveData´Ú,pUart»Ú ,pBuf<Ú ,sizeÚHAL_UART_SendData_INT¡Ú,pUart»Ú ,pBuf<Ú ,sizeÚ!HAL_UART_ReceiveData_INTbÚ,pUart»Ú ,pBuf<Ú,bufSize÷Ú-%HAL_UART_ReceiveDataContinuously_INT.Ú,pUart»Ú#HAL_UART_SendDataAbort_INTÚ,pUart»Ú&HAL_UART_ReceiveDataAbort_INT`Ú,pUart»Ú ,pBuf<Ú ,sizeÚHAL_UART_SendData_DMAºÚ,pUart»Ú ,pBuf<Ú ,sizeÚ!HAL_UART_ReceiveData_DMA{Ú,pUart»Ú#HAL_UART_SendDataAbort_DMA¸Ú,pUart»Ú&HAL_UART_ReceiveDataAbort_DMAyÚP__PAN_HAL_DMAC_H__ýÚDMAC_Peri_UARTBÚDMAC_Peri_I2CÂÚDMAC_Peri_SPIÚDMAC_Peri_ADC¸ÚDMAC_Peri_Mode_OptcÚ8
<unnamed>QÚ "ÕAdmamÚ "ÕAperiphÚ "ÕA
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<unnamed>QÚ ""ôAModeòÚSPI_InterruptOptDefÚBAUDRATE_100K`ÚBAUDRATE_500K\ÚBAUDRATE_1MÂÚBAUDRATE_2MÁÚBAUDRATE_5M¾Ú BAUDRATE_10MÚ SPI_BaudRateÚ8
<unnamed>QÚ ""þArole»Ú ""þA    dataSize0Ú ""þAclkPolarityÑÚ ""þA    clkPhase:Ú ""þAbaudrateDivôÚ ""þAformatàÚSPI_InitOptDefÄÚSPI_STAT_NULLÂÚSPI_STAT_RXWÚSPI_STAT_TXUÚSPI_STAT_RXTX§ÚSPI_XferStatOpt4Ú8
<unnamed>QÚ "BpSpixÐÚ "BinitObjÚ ""B    xferStatÚ "B interruptObjÍÚ "BpTxBuffPtråÚ "BtxXferSizeÊÚ "BtxXferCountZÚ "BpRxBuffPtrçÚ "BrxXferSizeÌÚ "BrxXferCount\Ú ""BIRQnÚ "BrxIntCallback²Ú "BtxIntCallback°Ú 
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errorCodeEÚSPI_HandleTypeDefÚ<hspiHandleArray²ÚP    SPI0_OBJeÚP    SPI1_OBJdÚ ,pSpi-Ú HAL_SPI_Init½Ú ,pSpi-ÚHAL_SPI_DeInitÚ ,pSpi-ÚHAL_SPI_Init_INTkÚ ,pSpi-ÚHAL_SPI_DeInit_INT¾Ú ,pSpi-Ú ,pBuf<Ú ,
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sizeÚ,
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sizeÚ,    callbackÚHAL_SPI_SendData_INTóÚ ,pSpi-Ú ,pBuf<Ú ,
sizeÚ,    callbackÚ HAL_SPI_ReceiveData_INT´Ú ,pSpi-Ú,    pSendBufªÚ,
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<unnamed>QÚ ""óBClockSpeedÚ ""óBRoleåÚ ""óB
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<unnamed>QÚ "CI2Cx¹Ú "CI2C_InitObjÚ "C InterruptObjöÚ "CpTxBuffPtrîÚ "CTxXferSizeóÚ "CTxXferCountÚ "CpRxBuffPtrðÚ "CRxXferSizeõÚ "CRxXferCountÚ ""CIRQnÚ "CRxIntCallbackÛÚ "CTxIntCallbackÙÚ 
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<unnamed>QÚ ""ÝCTimeoutÚ ""ÝCResetDelayÚ 
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<unnamed>QÚ "åC CallbackFuncâÚWDT_Interrupt_Opt2Ú,wdt|Ú HAL_WDT_InitºÚHAL_WDT_DeInit Ú,wdt|Ú HAL_WDT_FeedÚÚ,optxÚHAL_WDT_Init_INThÚHAL_WDT_DeInit_INT»ÚWDT_IRQHandlerÔÚP__PAN_HAL_WWDT_HÚWWDT_CallbackFunc¡Ú8
<unnamed>QÚ ""óC
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<unnamed>QÚ ""EInputRangeÞÚ ""EModebÚADC_InitOptýÚ8
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