国产蓝牙芯片的仓库
blame | 历史 | 原始文档
WXK
2025-04-24 ae079c1fc5d990ba55714d4b3a51b19f96edaec4 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231

ELF(¬Å4(¯¬@ºpGÀºpGpµ FÐ(Ðþçþçÿ÷þÿ h¨C `ÿ÷þÿp½øµ Ð,ÿ÷þÿ h(Ð&F6'àh°BÑþçþç9Fÿ÷þÿ h(ôÑÿ÷þÿ(Fÿ÷þÿø½µÿ÷þÿ½pµFÐ0Ðþçþçÿ÷þÿ%h(F°C `ÿ÷þÿ(Fp½µ ÿ÷þÿР ` ÿ÷þÿ F½µFÿ÷þÿ$hÿ÷þÿ F½øµF!‘Ð8Ðþçþç%F&5ÿ÷þÿ!hðh9C!`¨BÐhFh


        


S#hÔBÑ àFŸC


ÑÒ՚


C’"!hRCÿ÷þÿ0F®BâÑ!h˜C!`ÿ÷þÿ hø½ÿµF°FFÐþç,Ðÿ÷þÿ(Ðàþç/Ðþçÿ÷þÿ(F.h™ÿ÷þÿ˜C F°CÐ/Р!FC:F(ÿ÷þÿÿ÷þÿ(Р   à(h C(`à.hÿ÷þÿàÿ÷þÿÿ÷þÿF€


Ôÿ÷þÿ.h F°CÑ0F C(`ÿ÷þÿ66


0F°ð½ÿµ'°FFF(РÐþçþç,Ðÿ÷þÿ(Ðàþç


˜(Ðþçÿ÷þÿ(h.Ð!FCÐ


à BЙF)РC(`ÿ÷þÿ7à


™)И(Ð'?.Р€C!F9C(


šÿ÷þÿÿ÷þÿ(ÐàFÿ÷þÿàÿ÷þÿÿ÷þÿF€Ôÿ÷þÿ/h.РF¸CÐà'BИ(Ð8F C(`ÿ÷þÿ>6


0F°ð½..\\..\\..\\..\\os\\freertos\\event_groups.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x__asm___14_event_groups_c_5f98c4ce____REV16w ..\\..\\..\\..\\..\\modules\\hal\\panchip\\panplat\\pan1070\\bsp\\cmsis\\include\\cmsis_armcc.hí..\\..\\..\\..\\os\\freertos\\event_groups.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x__asm___14_event_groups_c_5f98c4ce____REVSHw ..\\..\\..\\..\\..\\modules\\hal\\panchip\\panplat\\pan1070\\bsp\\cmsis\\include\\cmsis_armcc.hü0ÿÿÿÿarmcc+|     


0ÿÿÿÿarmcc+|     


(ÿÿÿÿarmcc+| A~„Ž(ÿÿÿÿarmcc+| tAz„…†‡Ž(ÿÿÿÿarmcc+|  šAw„…†‡ŽBvI{(ÿÿÿÿarmcc+|  ÎAw„…†‡ŽBvc{(ÿÿÿÿarmcc+| $A|„…†Ž(ÿÿÿÿarmcc+| A~„Ž(ÿÿÿÿarmcc+| <Az„…†‡Ž(ÿÿÿÿarmcc+| A~„Ž(ÿÿÿÿarmcc+|  A|„…†ŽÜ


..\..\..\..\os\freertos\event_groups.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x4..\..\..\..\os\freertos\event_groups.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x>´”xEventGroupCreateê^__resultêPXpxEventBits³TX..\..\..\..\os\freertos\event_groups.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xtI×éto


Éo«b,Prc<GcM4cZZbhcs‹d‡c!c±mdÁè..\..\..\..\os\freertos\event_groups.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xš>è xEventGroupSyncšixEventGroupêÞiuxBitsToSet·¿iuxBitsToWaitFor·‹ixTicksToWaitBb^__resultP–YuxOriginalBitValue\uxReturnZpxEventBits³9YxAlreadyYielded\xTimeoutOccurred´..\..\..\..\os\freertos\event_groups.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xÎ>µ½ xEventGroupWaitBitsÎixEventGroupêáiuxBitsToWaitFor·­ixClearOnExit½jixWaitForAllBits½+ixTicksToWaitBÿ^__resultPÊZpxEventBits³Ö\uxReturnZuxControlBits¢\xWaitConditionMetYxAlreadyYielded\xTimeoutOccurredÅ4ÊZuxCurrentEventBits·„FüÔ4FØ    o÷qo^n"e6dF4F´Ô¢´³o÷Ko8n"e6dF¢ ..\..\..\..\os\freertos\event_groups.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x$IŸ_$o‚io”@b¦P"c¶"bÆU„..\..\..\..\os\freertos\event_groups.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x>†… xEventGroupGetBitsFromISRixEventGroupêI^__resultPZuxSavedInterruptStatus/#ZpxEventBitsË6XuxReturnT


T..\..\..\..\os\freertos\event_groups.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x<?ÓõvEventGroupDelete<ixEventGroupê]ZpxEventBits³?ZpxTasksWaitingForBitsß!D..\..\..\..\os\freertos\event_groups.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xuvoid"à?Å¥vEventGroupSetBitsCallbackipvEventGroupæ5iulBitsToSetã"„..\..\..\..\os\freertos\event_groups.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x uvoid"à?ƒ®vEventGroupClearBitsCallback ipvEventGroupæ…iulBitsToClearãrF‚_±o‚_o”Ae¦c¶#dÆH= ..\..\..\..\os\freertos\event_groups.cp= ..\..\..\..\os\freertos\event_groups.c”    !     ä= ..\..\..\..\os\freertos\event_groups.c– z     }      +I    <= ..\..\..\..\os\freertos\event_groups.cÅ%z    }%    #    !  %1    q m      z!     h= ..\..\..\..\os\freertos\event_groups.cÁ)~  x        }%    )è    s £}|3R    


 


%     w]( Y-         sö}!     ˆ= ..\..\..\..\os\freertos\event_groups.cÚ     l= ..\..\..\..\os\freertos\event_groups.c…,    ¨= ..\..\..\..\os\freertos\event_groups.cõ  t  {    `= ..\..\..\..\os\freertos\event_groups.c¦Œ= ..\..\..\..\os\freertos\event_groups.c¯ «~Ô²~        Ã}}}–t}<HR<dV<dP<dUT8dT‘h8d‘hQWP}–}$˜}(˜š}


$U>dUlŠUS$W>dWR$T>dTlŠTQ$‘`


P


$U}}$Ì}(ÌÎ}¢´T¢´W4FT4FP8PPX^PWFWXrWˆW


UPUX¾U‘F‘Xˆ‘SVFVXˆV°VR‘dP‘dXˆ‘d¾‘dQTPTX¾TP}––$}


T$TQV$V


P}–––}P


TP}–<} T$<T U$<UP}––}QP}––– }


T TU U


PQ


P__DATE__ "Apr 22 2025"__TIME__ "16:45:38"__STDC__ 1__STDC_VERSION__ 199901L__STDC_HOSTED__ 1__STDC_ISO_10646__ 200607__EDG__ 1__EDG_VERSION__ 407__EDG_SIZE_TYPE__ unsigned int__EDG_PTRDIFF_TYPE__ int__GNUC__ 4__GNUC_STDC_INLINE__ 1__GNUC_MINOR__ 7__GNUC_PATCHLEVEL__ 0__VERSION__ "4.7 (EDG gcc mode)"__CHAR16_TYPE__ unsigned short__CHAR32_TYPE__ unsigned int__USER_LABEL_PREFIX__ __CHAR_UNSIGNED__ 1__WCHAR_UNSIGNED__ 1__SIZE_TYPE__ unsigned int__PTRDIFF_TYPE__ int__WCHAR_TYPE__ unsigned short__WINT_TYPE__ unsigned short__INTMAX_TYPE__ long long__UINTMAX_TYPE__ unsigned long long__sizeof_int 4__sizeof_long 4__sizeof_ptr 4__ARMCC_VERSION 5060750__TARGET_CPU_CORTEX_M0 1__TARGET_FPU_SOFTVFP 1__TARGET_FPU_SOFTVFP 1__MICROLIB 1__UVISION_VERSION 530ARMCM0 1_RTE_ 1IP_107x 1CONFIG_FLASH_LINE_MODE FLASH_X4_MODEBLE_EN 1__ORDER_LITTLE_ENDIAN__ 2__BYTE_ORDER__ 2__CC_ARM 1__arm 1__arm__ 1__TARGET_ARCH_6S_M 1__TARGET_ARCH_ARM 0__TARGET_ARCH_THUMB 3__TARGET_ARCH_A64 0__TARGET_ARCH_AARCH32 1__TARGET_PROFILE_M 1__TARGET_FEATURE_HALFWORD 1__TARGET_FEATURE_THUMB 1__TARGET_FEATURE_DMB 1__TARGET_FEATURE_EXTENSION_REGISTER_COUNT 0__APCS_INTERWORK 1__thumb 1__thumb__ 1__t32__ 1__OPTIMISE_TIME 1__OPTIMIZE__ 1__OPT_SMALL_ASSERT 1__OPTIMISE_LEVEL 3__SOFTFP__ 1$8àxEventGroupCreate"ìàxEventGroupSync&¸àxEventGroupWaitBits,ˆàxEventGroupGetBitsFromISR$XàvEventGroupDelete-HêvEventGroupSetBitsCallback/ˆêvEventGroupClearBitsCallbackA%.CDESDK_CONFIG_H CONFIG_SOC_DCDC_PAN1070 1CONFIG_SYSTEM_CLOCK 48(CONFIG_APB1_CLOCK_DIVISOR 25CONFIG_APB2_CLOCK_DIVISOR 2<CONFIG_LOW_SPEED_CLOCK_SRC 1ACONFIG_FORCE_CALIB_RCL_CLK 0ECONFIG_RAM_FUNCTION 1JCONFIG_FLASH_LDO_EN 1MCONFIG_VECTOR_REMAP_TO_RAM 1QCONFIG_AUTO_OPTIMIZE_POWER_PARAM 0TCONFIG_TEMP_SAMPLE_INTERVAL_S 300WCONFIG_DVDD_VOL_OPTIMIZE_EN 1bCONFIG_PM 0eCONFIG_SYSTEM_WATCH_DOG_ENABLE 0kCONFIG_KEEP_FLASH_POWER_IN_LP_MODE 1pCONFIG_DEEPSLEEP_MODE_2 0}CONFIG_SOC_INCREASE_LPLDOH_CALIB_CODE 0‚CONFIG_PM_STANDBY_M1_WAKEUP_WITHOUT_RESET 0…CONFIG_HCLK_OPTIMIZE_EN 0ŽCONFIG_OS_EN 1‘configMAX_PRIORITIES 8”configTOTAL_HEAP_SIZE 11000—CONFIG_MAIN_TASK_STACK_SIZE 400šCONFIG_MAIN_TASK_PRIO 3CONFIG_BLE_HOST_THREAD_STACK_SIZE 400 CONFIG_BLE_HOST_THREAD_PRIO 6£configUSE_TIMERS 1¦configTIMER_TASK_STACK_DEPTH 128©configTIMER_TASK_PRIORITY 2¬configTIMER_QUEUE_LENGTH 12¯configUSE_IDLE_HOOK 0²configUSE_TICK_HOOK 0µconfigUSE_MALLOC_FAILED_HOOK 1¹configCHECK_FOR_STACK_OVERFLOW 0¼CONFIG_FREERTOS_HEAP_PRINT 0ÆCONFIG_USER_CHIP_MAC_ADDR 1ÓCONFIG_BT_CTLR_TX_POWER_DFT 0ÖCONFIG_BT_MAX_NUM_OF_CENTRAL 1ÙCONFIG_BT_MAX_NUM_OF_PERIPHERAL 1ÜMYNEWT_VAL_BLE_ROLE_BROADCASTER 1ßMYNEWT_VAL_BLE_ROLE_CENTRAL 1âMYNEWT_VAL_BLE_ROLE_OBSERVER 1åMYNEWT_VAL_BLE_ROLE_PERIPHERAL 1èMYNEWT_VAL_BLE_ATT_PREFERRED_MTU 247ëMYNEWT_VAL_BLE_TRANSPORT_ACL_FROM_LL_COUNT 8îMYNEWT_VAL_BLE_TRANSPORT_ACL_SIZE 251ñMYNEWT_VAL_BLE_TRANSPORT_EVT_COUNT 8ôMYNEWT_VAL_BLE_TRANSPORT_EVT_DISCARDABLE_COUNT 6÷MYNEWT_VAL_MSYS_1_BLOCK_COUNT 4úMYNEWT_VAL_MSYS_1_BLOCK_SIZE 120ýCONFIG_BLE_CONTROLLER_RF_RX_BUF_NUM 8€CONFIG_BLE_CONTROLLER_RF_TX_BUF_NUM 4ƒCONFIG_BLE_CONTROLLER_LL_ENC_TIME 300†CONFIG_BLE_CONTROLLER_MORE_DATA_NUM 6‰CONFIG_BLE_CONTROLLER_WIHTELIST_NUM 1ŒCONFIG_BLE_CONTROLLER_RESOLVELIST_NUM 0CONFIG_BLE_CONTROLLER_MASTER_LINK_MARGIN 10“CONFIG_BLE_LL_IRQ_PRIO 0—CONFIG_BLE_EVT_HANDLER_IRQ_PRIO 1¡MYNEWT_VAL_BLE_SM_SC_LVL 2¤MYNEWT_VAL_BLE_SM_LEGACY 1§MYNEWT_VAL_BLE_SM_SC 0¯CONFIG_HS_IO_CAPABILITY 3²MYNEWT_VAL_BLE_SM_BONDING 0µMYNEWT_VAL_BLE_SM_MITM 0¸MYNEWT_VAL_BLE_SM_OOB_DATA_FLAG 0¿MYNEWT_VAL_BLE_SM_OUR_KEY_DIST 1ÆMYNEWT_VAL_BLE_SM_THEIR_KEY_DIST 1ÉMYNEWT_VAL_BLE_STORE_CONFIG_PERSIST 1ÌMYNEWT_VAL_BLE_STORE_MAX_BONDS 2ÏMYNEWT_VAL_BLE_STORE_MAX_CCCDS 8ÒMYNEWT_VAL_HOST_SOFTWARE_RPA 1æCONFIG_FLASH_SIZE 0x7F000íCONFIG_FLASH_PARTITION_BOOTLOADER_ADDR 0x00000òCONFIG_FLASH_PARTITION_BOOTLOADER_SIZE 0x0A000÷CONFIG_FLASH_PARTITION_APP_ADDR 0x0A000üCONFIG_FLASH_PARTITION_APP_SIZE 0x37000CONFIG_FLASH_PARTITION_APP_BACKUP_ADDR 0x41000†CONFIG_FLASH_PARTITION_APP_BACKUP_SIZE 0x37000ŠCONFIG_FLASH_PARTITION_KVSTORE_ADDR 0x78000CONFIG_FLASH_PARTITION_KVSTORE_SIZE 0x04000”CONFIG_FLASH_PARTITION_USER_CUSTOM_ADDR 0x7C000™CONFIG_FLASH_PARTITION_USER_CUSTOM_SIZE 0x03000ÈCONFIG_APP_USE_IMAGE_HEADER 1ËCONFIG_APP_IMG_VER_MAJOR 0ÎCONFIG_APP_IMG_VER_MINOR 0ÑCONFIG_APP_IMG_VER_REVISION 1ÔCONFIG_APP_IMG_VER_BUILD 0áCONFIG_FIRMWARE_ENCRYPTION 0óAPP_LOG_EN 1ûAPP_LOG_LVL 4þAPP_LOG_LVL_OUTPUT_EN 1APP_LOG_TRACE_OUTPUT_EN 0„CONFIG_UART_LOG_ENABLE 1CONFIG_LOG_UART_PIN 2™CONFIG_LOG_UART_BAUDRATE 921600 CONFIG_RTT_LOG_ENABLE 0¤CONFIG_LOG_RTT_UP_BUFFER_SIZE 512ªCONFIG_IO_TIMING_TRACK 0±CONFIG_BT_CTLR_LINK_LAYER_DEBUG 0ÐCONFIG_TRACK_PIN_DEEPSLEEP_MODE 0x22ïCONFIG_TRACK_PIN_SLEEP_MODE 0x23ŽCONFIG_TRACK_PIN_LL_IRQ 0x99®CONFIG_TRACK_PIN_BLE_EVNT_IRQ 0x99ÍCONFIG_TRACK_PIN_OS_TICK_IRQ 0x99ìCONFIG_TRACK_PIN_SLPTMR_IRQ 0x99‹CONFIG_TRACK_PIN_HARDFAULT_IRQ 0x99ªCONFIG_TRACK_PIN_DMA_IRQ 0x99ÉCONFIG_TRACK_PIN_GPIO0_IRQ 0x99èCONFIG_TRACK_PIN_GPIO1_IRQ 0x99‡CONFIG_TRACK_PIN_GPIO2_IRQ 0x99¦CONFIG_TRACK_PIN_GPIO3_IRQ 0x99ÅCONFIG_TRACK_PIN_I2C_IRQ 0x99äCONFIG_TRACK_PIN_SPI0_IRQ 0x99ƒCONFIG_TRACK_PIN_SPI1_IRQ 0x99¢CONFIG_TRACK_PIN_TMR0_IRQ 0x99ÁCONFIG_TRACK_PIN_TMR1_IRQ 0x99àCONFIG_TRACK_PIN_TMR2_IRQ 0x99ÿCONFIG_TRACK_PIN_UART0_IRQ 0x99ž    CONFIG_TRACK_PIN_UART1_IRQ 0x99½    CONFIG_TRACK_PIN_WDT_IRQ 0x99Ü    CONFIG_TRACK_PIN_WWDT_IRQ 0x99û    CONFIG_TRACK_USER_APP_CHN0 0x99š


CONFIG_TRACK_USER_APP_CHN1 0x99¹


CONFIG_TRACK_USER_APP_CHN2 0x99Ø


CONFIG_TRACK_USER_APP_CHN3 0x99÷


CONFIG_TRACK_USER_APP_CHN4 0x99–CONFIG_TRACK_USER_APP_CHN5 0x99µCONFIG_TRACK_USER_APP_CHN6 0x99ÔCONFIG_TRACK_USER_APP_CHN7 0x99ÚCONFIG_STARTUP_LONG_DELAY 0@4 .\configuration\sdk_config.hÐ


.\configuration\sdk_config.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xGHI_SOC_CONFIG_H_ TCONFIG_RAM_CODE __attribute__((section(".ramfunc")))™CONFIG_FLASH_PARTITION_CHIP_INFO_ADDR 0x7F000šCONFIG_FLASH_PARTITION_CHIP_INFO_SIZE 0x1000«IS_BOOTABLE_APP 0ÃENCRYPT_SECTION dX ..\..\..\..\config\.\configuration\soc_config.hsdk_config.hÔ


..\..\..\..\config\soc_config.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xKLM__stdlib_h __ARMCLIB_VERSION 5060037__LONGLONG long long_ARMABI __declspec(__nothrow)_ARMABI_PURE __declspec(__nothrow) __attribute__((const))_ARMABI_NORETURN __declspec(__nothrow) __declspec(__noreturn)_ARMABI_THROW !__STDLIB_DECLS )__USE_C99_STDLIB 1-__CLIBNS4__CLIBNS GNULLHNULL 0mEXIT_FAILURE 1oEXIT_SUCCESS 0RAND_MAX 0x7fffffffˆMB_CUR_MAX ( __aeabi_MB_CUR_MAX() )¥__fpsr_IXE 0x100000¦__fpsr_UFE 0x80000§__fpsr_OFE 0x40000¨__fpsr_DZE 0x20000©__fpsr_IOE 0x10000«__fpsr_IXC 0x10¬__fpsr_UFC 0x8­__fpsr_OFC 0x4®__fpsr_DZC 0x2¯__fpsr_IOC 0x1ý__LONGLONGPD C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdlib.hÀC:\Keil_v5\ARM\ARMCC\Bin\..\include\stdlib.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]unsigned intunsigned shortintlonglong longuvoidcharPsize_tŠ<Pwchar_tšP)•div_tquot¬#rem¬#Pdiv_tó\))Åldiv_tquot³#rem³#Pldiv_t"^/)÷lldiv_tquot»#rem»#Plldiv_tSa2)¬_rand_stateä ¬8__x—#)Ö_ANSI_rand_stateʬ__xÁ#Næ¬%æ%îV"ÈÎ"ê"ÖP__heapprtòò)±__sdiv32by16quot¬#rem¬#P__sdiv32by16ÿ0)ï__udiv32by16quotŠ#remŠ#P__udiv32by16F€9)­__sdiv64by32rem¬#quot¬#P__sdiv64by32„‚0OPQ__stddef_h __ARMCLIB_VERSION 5060037__STDDEF_DECLS __CLIBNS __CLIBNS SNULLTNULL 0[offsetof(t,memb) ((__CLIBNS size_t)__INTADDR__(&(((t *)0)->memb)))\P C:\Keil_v5\ARM\ARMCC\Bin\..\include\stddef.hstdlib.hC:\Keil_v5\ARM\ARMCC\Bin\..\include\stddef.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]intlong doubleunsigned shortunsigned intPptrdiff_tŠ&Pmax_align_t‘_Psize_t²<Pwchar_t PSTU__stdint_h __ARMCLIB_VERSION 5060037__INT64 __int64__INT64_C_SUFFIX__ ll__PASTE2(x,y) x ## y__PASTE(x,y) __PASTE2(x, y)__INT64_C(x) __ESCAPE__(__PASTE(x, __INT64_C_SUFFIX__))__UINT64_C(x) __ESCAPE__(__PASTE(x ## u, __INT64_C_SUFFIX__))__LONGLONG long long#__STDINT_DECLS %__CLIBNS,__CLIBNS sINT8_MIN -128tINT16_MIN -32768uINT32_MIN (~0x7fffffff)vINT64_MIN __INT64_C(~0x7fffffffffffffff)yINT8_MAX 127zINT16_MAX 32767{INT32_MAX 2147483647|INT64_MAX __INT64_C(9223372036854775807)UINT8_MAX 255€UINT16_MAX 65535UINT32_MAX 4294967295u‚UINT64_MAX __UINT64_C(18446744073709551615)‡INT_LEAST8_MIN -128ˆINT_LEAST16_MIN -32768‰INT_LEAST32_MIN (~0x7fffffff)ŠINT_LEAST64_MIN __INT64_C(~0x7fffffffffffffff)INT_LEAST8_MAX 127ŽINT_LEAST16_MAX 32767INT_LEAST32_MAX 2147483647INT_LEAST64_MAX __INT64_C(9223372036854775807)“UINT_LEAST8_MAX 255”UINT_LEAST16_MAX 65535•UINT_LEAST32_MAX 4294967295u–UINT_LEAST64_MAX __UINT64_C(18446744073709551615)›INT_FAST8_MIN (~0x7fffffff)œINT_FAST16_MIN (~0x7fffffff)INT_FAST32_MIN (~0x7fffffff)žINT_FAST64_MIN __INT64_C(~0x7fffffffffffffff)¡INT_FAST8_MAX 2147483647¢INT_FAST16_MAX 2147483647£INT_FAST32_MAX 2147483647¤INT_FAST64_MAX __INT64_C(9223372036854775807)§UINT_FAST8_MAX 4294967295u¨UINT_FAST16_MAX 4294967295u©UINT_FAST32_MAX 4294967295uªUINT_FAST64_MAX __UINT64_C(18446744073709551615)²INTPTR_MIN INT32_MIN¹INTPTR_MAX INT32_MAXÀUINTPTR_MAX UINT32_MAXÆINTMAX_MIN __ESCAPE__(~0x7fffffffffffffffll)ÉINTMAX_MAX __ESCAPE__(9223372036854775807ll)ÌUINTMAX_MAX __ESCAPE__(18446744073709551615ull)ÕPTRDIFF_MIN INT32_MINÖPTRDIFF_MAX INT32_MAXÚSIG_ATOMIC_MIN (~0x7fffffff)ÛSIG_ATOMIC_MAX 2147483647áSIZE_MAX UINT32_MAXçWCHAR_MINèWCHAR_MAXîWCHAR_MIN 0ïWCHAR_MAX 65535óWINT_MIN (~0x7fffffff)ôWINT_MAX 2147483647ûINT8_C(x) (x)üINT16_C(x) (x)ýINT32_C(x) (x)þINT64_C(x) __INT64_C(x)€UINT8_C(x) (x ## u)UINT16_C(x) (x ## u)‚UINT32_C(x) (x ## u)ƒUINT64_C(x) __UINT64_C(x)†INTMAX_C(x) __ESCAPE__(x ## ll)‡UINTMAX_C(x) __ESCAPE__(x ## ull)²__INT64³__LONGLONGPD C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.hC:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]signed charshortintlong longunsigned charunsigned shortunsigned intunsigned long longPint8_tŠ8 Pint16_t™9 Pint32_t¢: Pint64_t©; Puint8_t¶> Puint16_tÇ? Puint32_tÙ@ Puint64_téA Pint_least8_tŠG Pint_least16_t™H Pint_least32_t¢I Pint_least64_t©J Puint_least8_t¶M Puint_least16_tÇN Puint_least32_tÙO Puint_least64_téP Pint_fast8_t¢U Pint_fast16_t¢V Pint_fast32_t¢W Pint_fast64_t©X Puint_fast8_tÙ[ Puint_fast16_tÙ\ Puint_fast32_tÙ] Puint_fast64_té^ Pintptr_t¢e Puintptr_tÙf Pintmax_t©j!Puintmax_ték!WXYZ__stdio_h __ARMCLIB_VERSION 5060037"_ARMABI __declspec(__nothrow)%__STDIO_DECLS '__CLIBNS-__CLIBNS <NULL=NULL 0g_SYS_OPEN 16¥stdin (&__CLIBNS __stdin)§stdout (&__CLIBNS __stdout)©stderr (&__CLIBNS __stderr)¬_IOFBF 0x100­_IOLBF 0x200®_IONBF 0x400±BUFSIZ (512)³FOPEN_MAX _SYS_OPEN¹FILENAME_MAX 256¾L_tmpnam FILENAME_MAXÄTMP_MAX 256ÌEOF (-1)ÒSEEK_SET 0ÓSEEK_CUR 1ÔSEEK_END 2Ú_IOBIN 0x04Ü__STDIN_BUFSIZ (64)Ý__STDOUT_BUFSIZ (64)Þ__STDERR_BUFSIZ (16)¿getchar() getc(stdin)àputchar(c) putc(c, stdout)XO C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.hstdlib.h¸C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]unsigned intunsigned long long)â__fpos_t_struct__pos™#__mbstate“#P__va_listFPfpos_t¯a-__FILEPFILElq__stdinq__stdoutq__stderr"q__aeabi_stdinCq__aeabi_stdoutCq__aeabi_stderrCPsize_t‰<*¸__state1‰#__state2‰#l¼__stdin%__stdout4__stderrG__aeabi_stdin[__aeabi_stdoutp__aeabi_stderr\]^__string_h __ARMCLIB_VERSION 5060037_ARMABI __declspec(__nothrow)__STRING_DECLS __CLIBNS$__CLIBNS 7NULL8NULL 0\P C:\Keil_v5\ARM\ARMCC\Bin\..\include\string.hstdlib.h¨C:\Keil_v5\ARM\ARMCC\Bin\..\include\string.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]unsigned intPsize_tŠ<`ab __CMSIS_VERSION_H #__CM_CMSIS_VERSION_MAIN ( 5U)$__CM_CMSIS_VERSION_SUB ( 3U)%__CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | __CM_CMSIS_VERSION_SUB )xl ..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\cmsis_version.h


..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\cmsis_version.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xdef__CMSIS_ARMCC_H $__ARM_ARCH_6M__ 19__ASM __asm<__INLINE __inline?__STATIC_INLINE static __inlineB__STATIC_FORCEINLINE static __forceinlineE__NO_RETURN __declspec(noreturn)H__USED __attribute__((used))K__WEAK __attribute__((weak))N__PACKED __attribute__((packed))Q__PACKED_STRUCT __packed structT__PACKED_UNION __packed unionW__UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))Z__UNALIGNED_UINT16_WRITE(addr,val) ((*((__packed uint16_t *)(addr))) = (val))]__UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))`__UNALIGNED_UINT32_WRITE(addr,val) ((*((__packed uint32_t *)(addr))) = (val))c__UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))f__ALIGNED(x) __attribute__((aligned(x)))i__RESTRICT __restrictl__COMPILER_BARRIER() __memory_changed()r__PROGRAM_START __mainv__INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limitz__STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base~__VECTOR_TABLE __Vectors‚__VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) __NOP __nop§__WFI __wfi¯__WFE __wfe¶__SEV __sev¿__ISB() do { __schedule_barrier(); __isb(0xF); __schedule_barrier(); } while (0U)Ê__DSB() do { __schedule_barrier(); __dsb(0xF); __schedule_barrier(); } while (0U)Õ__DMB() do { __schedule_barrier(); __dmb(0xF); __schedule_barrier(); } while (0U)â__REV __revŠ__ROR __ror”__BKPT(value) __breakpoint(value)¹__CLZ __clztj ..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\cmsis_armcc.hü


..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\cmsis_armcc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x;ÉŸ__get_CONTROLYa__resultYY__regControlYP<ƒ«__set_CONTROL$YcontrolY__regControlYP;¾·__get_IPSRYa__resultYY__regIPSRYP;ùÃ__get_APSRYa__resultYY__regAPSRYP;´Ï__get_xPSRYa__resultYY__regXPSRYP;ýÛ__get_PSPYa__resultYY__regProcessStackPointerYP<Æç__set_PSP$YtopOfProcStackY__regProcessStackPointerYP;Œó__get_MSPYa__resultYY__regMainStackPointerYP<Òÿ__set_MSP$YtopOfMainStackY__regMainStackPointerYP;“‹__get_PRIMASKYa__resultYY__regPriMaskYP<Í—__set_PRIMASK$YpriMaskY__regPriMaskYP;÷ö__get_FPSCRYa__resultY<˜‡__set_FPSCR$Yfpscr;Þ¡9__RBITY$Yvaluea__resultY\resultY\sY;«    ý8__SSAT$val$Ysata__resultª    \max«\min«;ö    –9__USATY$val$Ysata__resultYõ    \maxöYhij__CMSIS_COMPILER_H "¸¯ ..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\C:\Keil_v5\ARM\ARMCC\Bin\..\include\cmsis_compiler.hstdint.hcmsis_armcc.h


..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\cmsis_compiler.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xlmn __CORE_CM0_H_GENERIC "?B__CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)C__CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB)D__CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | __CM0_CMSIS_VERSION_SUB )G__CORTEX_M (0U)L__FPU_USED 0Us__CORE_CM0_H_DEPENDANT ¢__I volatile const¤__O volatile¥__IO volatile¨__IM volatile const©__OM volatileª__IOM volatileÕAPSR_N_Pos 31UÖAPSR_N_Msk (1UL << APSR_N_Pos)ØAPSR_Z_Pos 30UÙAPSR_Z_Msk (1UL << APSR_Z_Pos)ÛAPSR_C_Pos 29UÜAPSR_C_Msk (1UL << APSR_C_Pos)ÞAPSR_V_Pos 28UßAPSR_V_Msk (1UL << APSR_V_Pos)ðIPSR_ISR_Pos 0UñIPSR_ISR_Msk (0x1FFUL )ˆxPSR_N_Pos 31U‰xPSR_N_Msk (1UL << xPSR_N_Pos)‹xPSR_Z_Pos 30UŒxPSR_Z_Msk (1UL << xPSR_Z_Pos)ŽxPSR_C_Pos 29UxPSR_C_Msk (1UL << xPSR_C_Pos)‘xPSR_V_Pos 28U’xPSR_V_Msk (1UL << xPSR_V_Pos)”xPSR_T_Pos 24U•xPSR_T_Msk (1UL << xPSR_T_Pos)—xPSR_ISR_Pos 0U˜xPSR_ISR_Msk (0x1FFUL )ªCONTROL_SPSEL_Pos 1U«CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)ãSCB_CPUID_IMPLEMENTER_Pos 24UäSCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)æSCB_CPUID_VARIANT_Pos 20UçSCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)éSCB_CPUID_ARCHITECTURE_Pos 16UêSCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)ìSCB_CPUID_PARTNO_Pos 4UíSCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)ïSCB_CPUID_REVISION_Pos 0UðSCB_CPUID_REVISION_Msk (0xFUL )óSCB_ICSR_NMIPENDSET_Pos 31UôSCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)öSCB_ICSR_PENDSVSET_Pos 28U÷SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)ùSCB_ICSR_PENDSVCLR_Pos 27UúSCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)üSCB_ICSR_PENDSTSET_Pos 26UýSCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)ÿSCB_ICSR_PENDSTCLR_Pos 25U€SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)‚SCB_ICSR_ISRPREEMPT_Pos 23UƒSCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)…SCB_ICSR_ISRPENDING_Pos 22U†SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)ˆSCB_ICSR_VECTPENDING_Pos 12U‰SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)‹SCB_ICSR_VECTACTIVE_Pos 0UŒSCB_ICSR_VECTACTIVE_Msk (0x1FFUL )SCB_AIRCR_VECTKEY_Pos 16USCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)’SCB_AIRCR_VECTKEYSTAT_Pos 16U“SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)•SCB_AIRCR_ENDIANESS_Pos 15U–SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)˜SCB_AIRCR_SYSRESETREQ_Pos 2U™SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)›SCB_AIRCR_VECTCLRACTIVE_Pos 1UœSCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)ŸSCB_SCR_SEVONPEND_Pos 4U SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)¢SCB_SCR_SLEEPDEEP_Pos 2U£SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)¥SCB_SCR_SLEEPONEXIT_Pos 1U¦SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)©SCB_CCR_STKALIGN_Pos 9UªSCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)¬SCB_CCR_UNALIGN_TRP_Pos 3U­SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)°SCB_SHCSR_SVCALLPENDED_Pos 15U±SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)ÉSysTick_CTRL_COUNTFLAG_Pos 16UÊSysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)ÌSysTick_CTRL_CLKSOURCE_Pos 2UÍSysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)ÏSysTick_CTRL_TICKINT_Pos 1UÐSysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)ÒSysTick_CTRL_ENABLE_Pos 0UÓSysTick_CTRL_ENABLE_Msk (1UL )ÖSysTick_LOAD_RELOAD_Pos 0U×SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL )ÚSysTick_VAL_CURRENT_Pos 0UÛSysTick_VAL_CURRENT_Msk (0xFFFFFFUL )ÞSysTick_CALIB_NOREF_Pos 31UßSysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)áSysTick_CALIB_SKEW_Pos 30UâSysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)äSysTick_CALIB_TENMS_Pos 0UåSysTick_CALIB_TENMS_Msk (0xFFFFFFUL )_VAL2FLD(field,value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)‰_FLD2VAL(field,value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)–SCS_BASE (0xE000E000UL)—SysTick_BASE (SCS_BASE + 0x0010UL)˜NVIC_BASE (SCS_BASE + 0x0100UL)™SCB_BASE (SCS_BASE + 0x0D00UL)›SCB ((SCB_Type *) SCB_BASE )œSysTick ((SysTick_Type *) SysTick_BASE )NVIC ((NVIC_Type *) NVIC_BASE )¿NVIC_SetPriorityGrouping __NVIC_SetPriorityGroupingÀNVIC_GetPriorityGrouping __NVIC_GetPriorityGroupingÁNVIC_EnableIRQ __NVIC_EnableIRQÂNVIC_GetEnableIRQ __NVIC_GetEnableIRQÃNVIC_DisableIRQ __NVIC_DisableIRQÄNVIC_GetPendingIRQ __NVIC_GetPendingIRQÅNVIC_SetPendingIRQ __NVIC_SetPendingIRQÆNVIC_ClearPendingIRQ __NVIC_ClearPendingIRQÈNVIC_SetPriority __NVIC_SetPriorityÉNVIC_GetPriority __NVIC_GetPriorityÊNVIC_SystemReset __NVIC_SystemResetÓNVIC_SetVector __NVIC_SetVectorÔNVIC_GetVector __NVIC_GetVector×NVIC_USER_IRQ_OFFSET 16ÛEXC_RETURN_HANDLER (0xFFFFFFF1UL)ÜEXC_RETURN_THREAD_MSP (0xFFFFFFF9UL)ÝEXC_RETURN_THREAD_PSP (0xFFFFFFFDUL)â_BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)ã_SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )ä_IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )æ__NVIC_SetPriorityGrouping(X) (void)(X)ç__NVIC_GetPriorityGrouping() (0U)È¿ ..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\C:\Keil_v5\ARM\ARMCC\Bin\..\include\core_cm0.hstdint.hcmsis_version.hcmsis_compiler.hð


..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\core_cm0.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x*Ù!_reserved0Y#!VY#!CY#!ZY#!NY#SìbwYPAPSR_TypeYÒ*ª!ISRY#    !_reserved0Y#S½b~wYPIPSR_Typeªí*Ø!ISRY#    !_reserved0Y#!TY#!_reserved1Y#!VY#!CY#!ZY#!NY#SëbÏwYPxPSR_TypeX…*Â!_reserved0Y#!SPSELY#!_reserved1Y#SÕb}wYPCONTROL_Type§*ë øëISERï#YRESERVED0#©ëICER #€ÁYRESERVED16#„ÜëISPRS#€ôYRESERVED2i#„ëICPR†#€§YRESERVED3œ#„ÄY?RESERVED4¹#€ßëIPÖ#€tYPNVIC_TypeêÆ*‹    (CPUID‘#ICSRë#RESERVED0Y#AIRCRë#SCRë#CCRë#RESERVED1Y#òëSHPi#SHCSRë#$Yt‹PSCB_Typeà*Û    CTRLë#LOADë#VALë#CALIB‘#PSysTick_Type¦Æ<•


ï__NVIC_EnableIRQ$ƒIRQn;Ò


‚__NVIC_GetEnableIRQY$ƒIRQna__resultY<ø


•__NVIC_DisableIRQ$ƒIRQn;¶¨__NVIC_GetPendingIRQY$ƒIRQna__resultY<ß»__NVIC_SetPendingIRQ$ƒIRQn<ŠÊ__NVIC_ClearPendingIRQ$ƒIRQn<ÀÜ__NVIC_SetPriority$ƒIRQn$Ypriority;üô__NVIC_GetPriorityY$ƒIRQna__resultY;±NVIC_EncodePriorityY$YPriorityGroup$YPreemptPriority$YSubPrioritya__resultY\PriorityGroupTmpY\PreemptPriorityBitsY\SubPriorityBitsY<Þ¨NVIC_DecodePriority$YPriority$YPriorityGroup$äpPreemptPriority$äpSubPriority\PriorityGroupTmpY\PreemptPriorityBitsY\SubPriorityBitsY"YÞ<¨À__NVIC_SetVector$ƒIRQn$Yvector\vectorsY;ðÐ__NVIC_GetVectorY$ƒIRQna__resultY\vectorsY<ŒÛ"__NVIC_SystemReset;¹üSCB_GetFPUTypeYa__resultY;ò›SysTick_ConfigY$Yticksa__resultYpqr__bool_true_false_are_defined 1__ARMCLIB_VERSION 5060037bool _Booltrue 1false 0PE C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdbool.hŒC:\Keil_v5\ARM\ARMCC\Bin\..\include\stdbool.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]tuvw__SYSTEM_PANSERIES_H__ __PAN_STRINGIFY(x) #xPAN_STRINGIFY(s) __PAN_STRINGIFY(s)__PAN_CONCAT(x,y) x ## yPAN_CONCAT(x,y) __PAN_CONCAT(x, y)#__PAN_COND_CODE_1(_flag,_if_1_code,_else_code) __PAN_COND_CODE(_AAAAA ## _flag, _if_1_code, _else_code)%__PAN_COND_CODE_0(_flag,_if_0_code,_else_code) __PAN_COND_CODE(_BBBBB ## _flag, _if_0_code, _else_code)'_AAAAA1 _ZZZZZ,(_BBBBB0 _ZZZZZ,)__PAN_COND_CODE(one_or_two_args,_if_code,_else_code) __PAN_GET_ARG2_DEBRACKET(one_or_two_args _if_code, _else_code)-__PAN_GET_ARG2_DEBRACKET(ignore_this,val,__VA_ARGS__...) __PAN_DEBRACKET val/__PAN_DEBRACKET(__VA_ARGS__...) __VA_ARGS__@PAN_COND_CODE_1(_flag,_if_1_code,_else_code) __PAN_COND_CODE_1(_flag, _if_1_code, _else_code)PPAN_COND_CODE_0(_flag,_if_0_code,_else_code) __PAN_COND_CODE_0(_flag, _if_0_code, _else_code)¸® ..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\C:\Keil_v5\ARM\ARMCC\Bin\..\include\system_PanSeries.hstdint.hstdbool.h”


..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\system_PanSeries.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xfloat_Bool*º€°:rsvd0%#!pmu_vbg_trim:#!rsvd1:#!pmu_vbg_volt_l:#pmu_vbg_volt_h:#!hp_ldo_trim:# !hp_ldo_volt_l:# hp_ldo_volt_h:#!!lph_ldo_trim:#"!lph_ldo_volt_l:#"lph_ldo_volt_h:##!lpl_ldo_trim:#$!lpl_ldo_volt_l:#$lpl_ldo_volt_h:#%!flash_ldo_trim:#&!rsvd2:#&!flash_ldo_volt_l:#&flash_ldo_volt_h:#'!ana_ldo_trim:#(!rffe_ldo_trim:#(!fsyn_ldo_trim:#)!adc_ldo_trim:#)!vco_ldo_trim:#*!ipoly_trim:#*!rsvd3:#*!bod_vref_trim:#+!rsvd4:#+!bod_vref_volt_l:#+bod_vref_volt_h:#,rsvd5:#-!xtl_core:#.!xth_icore:#.!rch_bias:#.!dpll_vco_freq_trim:#.!dpll_kvco_ctrl:#/!dpll_icp_ctrl:#/!dpll_icp_bias:#/!rsvd6:#/!adc_vbg_1v20_trim:#0!ptat_temp_trim:#0adc_vbg_1v20_voltI#1rch_trim:#3rch_freqY#4!rcl_coarse_trim:#8!lph_ldo_vref_trim:#8!rsvd7:#8rcl_fine_trim:#9rcl_freqI#:analog_temp_voltI#<Ê:    rsvd_0x3e¿#>analog_0p6v_voltI#H€:    rsvd8õ#J!buck_imax_cal_trim:#T!rsvd9:#T!buck_zero_cal_trim:#U!rsvd10:#U!buck_out_trim:#V!rsvd11:#Vbuck_vout_voltI#Wadc_vdd_kI#Yadc_vdd_bÿ#[adc_vbg_kI#\adc_vbg_b #^adc_temp_voltI#`current_temp_value #bbattery_trim:#dÕ:rsvd12J#eî:uidc#lchip_info:#ucp_version:#vft_version:#wcp_pass_flag:#xft_pass_flag:#ycp_checksum:#zft_checksum:#{•:user_rw_data


#|´:mac_addr)#€xth_xocap_a#†xth_xocap_m#Šxth_xocap_n#Žxth_xocap_trim:#’xtl_xocap_a#“xtl_xocap_m#—xtl_xocap_n#›xtl_xocap_trim:#Ÿøn


adc_vbg_kbï# adc_vbat_kI#¼adc_vbat_b #¾adc_vbat_dtemp_k #Àadc_vbat_dtemp_b #Âadc_temp_k#Äadc_ctrl2Y#Èadc_extsmptY#Ìxth_fix_code1:#Ðxth_fix_code2:#Ñxtl_fix_code1:#Òxtl_fix_code2:#Ó“:*rsvd13


#Ôft_checksum2:#ÿRî_otp_struct€×:ÿd8K


mâ


m_v2 PADC_VBG_KB_T«


XPOTP_STRUCT_T:


qisFtDataValid)â_adc_vbg_kbadc_vbg_kI#adc_vbg_b #*–#€ò:rsvd0ç


#!pmu_vbg_trim:#!rsvd1:#!pmu_vbg_volt_l:#pmu_vbg_volt_h:#!hp_ldo_trim:# !hp_ldo_volt_l:# hp_ldo_volt_h:#!!lph_ldo_trim:#"!lph_ldo_volt_l:#"lph_ldo_volt_h:##!lpl_ldo_trim:#$!lpl_ldo_volt_l:#$lpl_ldo_volt_h:#%!flash_ldo_trim:#&!rsvd2:#&!flash_ldo_volt_l:#&flash_ldo_volt_h:#'!ana_ldo_trim:#(!rffe_ldo_trim:#(!fsyn_ldo_trim:#)!adc_ldo_trim:#)!vco_ldo_trim:#*!ipoly_trim:#*!rsvd3:#*!bod_vref_trim:#+!rsvd4:#+!bod_vref_volt_l:#+bod_vref_volt_h:#,!adc_vbg_1v17_trim:#-!rsvd5:#-adc_vbg_1v17_voltI#.!adc_vbg_1v20_trim:#0!rsvd6:#0adc_vbg_1v20_voltI#1rch_trim:#3rch_freqY#4!rcl_coarse_trim:#8!rsvd7:#8rcl_fine_trim:#9rcl_freqI#:xth_xocap_a#<xth_xocap_m#@xth_xocap_n#Dxtl_xocap_a#Hxtl_xocap_m#Lxtl_xocap_n#P!buck_imax_cal_trim:#T!rsvd8:#T!buck_zero_cal_trim:#U!rsvd9:#U!buck_out_trim:#V!rsvd10:#Vbuck_vout_voltI#Wadc_vdd_kI#Yadc_vdd_bÿ#[adc_vbg_kI#\adc_vbg_b #^adc_temp_voltI#`current_temp_value #bbattery_trim:#d!pa_power_calib_trim_6dbm:#e!pa_power_calib_trim_0dbm:#e¿!:mac_addr´#fÚ!:uidÏ#lchip_info:#ucp_version:#vft_version:#wcp_pass_flag:#xft_pass_flag:#ycp_checksum:#zft_checksum:#{#:user_rw_datav#| ˜—


isFtDataValidyz{__PAN_SYS_LOG_H__ DBG_ON 0INFO_ON 1WARN_ON 1ERR_ON 1TEST_ON 1ASSERT_ON 1SYS_ABORT() do { } while (1)!LOG(flags,__VA_ARGS__...) do { if (flags) printf(__VA_ARGS__); } while (0)'SYS_DBG(fmt,__VA_ARGS__...) LOG(DBG_ON, "[SYS DBG] %s:%s():%d, " fmt, __FILE__, __FUNCTION__, __LINE__, ## __VA_ARGS__)(SYS_INFO(fmt,__VA_ARGS__...) LOG(INFO_ON, "[SYS INFO] %s:%s():%d, " fmt, __FILE__, __FUNCTION__, __LINE__, ## __VA_ARGS__))SYS_WARN(fmt,__VA_ARGS__...) LOG(WARN_ON, "[SYS WARN] %s:%s():%d, " fmt, __FILE__, __FUNCTION__, __LINE__, ## __VA_ARGS__)*SYS_TEST(__VA_ARGS__...) LOG(TEST_ON, __VA_ARGS__),SYS_ERR(fmt,__VA_ARGS__...) do { LOG(ERR_ON, "[SYS ERR] %s:%s():%d, "fmt, __FILE__, __FUNCTION__, __LINE__, ## __VA_ARGS__); if (ERR_ON) SYS_ABORT(); } while (0)5SYS_ASSERT(expr) ((expr) ? (void)0u : SYS_AssertError((uint8_t*)__FILE__, __LINE__, (uint8_t*)(#expr)))°§ ..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\C:\Keil_v5\ARM\ARMCC\Bin\..\include\pan_sys_log.hstdio.hstdint.h


..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_sys_log.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x}~ __PAN_SYS_H__  SYS_MFP_TYPE_Msk(bit) (1UL << ((bit) +16))!SYS_MFP_ALT_Msk(bit) (1UL << ((bit) + 8))"SYS_MFP_MFP_Msk(bit) (1UL << ((bit) ))$SYS_MFP_GPIO 0x00000000UL'SYS_MFP_P00_GPIO 0x00000000UL(SYS_MFP_P00_SWD_CLK 0x00000001UL)SYS_MFP_P00_UART1_RX 0x00000100UL*SYS_MFP_P00_I2C0_SCL 0x00000101UL+SYS_MFP_P00_SPI0_CLK 0x00010000UL,SYS_MFP_P00_LL_DBG_14 0x00010001UL-SYS_MFP_P00_MDM_DBG_11 0x00010100UL.SYS_MFP_P00_RESERVED 0x00010101UL/SYS_MFP_P00_Msk 0x00010101UL1SYS_MFP_P01_GPIO 0x00000000UL2SYS_MFP_P01_SWD_DAT 0x00000002UL3SYS_MFP_P01_UART1_TX 0x00000200UL4SYS_MFP_P01_I2C0_SDA 0x00000202UL5SYS_MFP_P01_SPI0_CS 0x00020000UL6SYS_MFP_P01_LL_DBG_15 0x00020002UL7SYS_MFP_P01_MDM_DBG_12 0x00020200UL8SYS_MFP_P01_RESERVED 0x00020202UL9SYS_MFP_P01_Msk 0x00020202UL;SYS_MFP_P02_GPIO 0x00000000UL<SYS_MFP_P02_UART0_CTS 0x00000004UL=SYS_MFP_P02_SPI1_MISO 0x00000400UL>SYS_MFP_P02_PWM_CH3 0x00000404UL?SYS_MFP_P02_UART1_CTS 0x00040000UL@SYS_MFP_P02_LL_DBG_8 0x00040004ULASYS_MFP_P02_MDM_DBG_19 0x00040400ULBSYS_MFP_P02_RESERVED 0x00040404ULCSYS_MFP_P02_Msk 0x00040404ULESYS_MFP_P03_GPIO 0x00000000ULFSYS_MFP_P03_UART0_CTS 0x00000008ULGSYS_MFP_P03_SPI0_CS 0x00000800ULHSYS_MFP_P03_PWM_CH2 0x00000808ULISYS_MFP_P03_TIMER0_CNT_OUT 0x00080000ULJSYS_MFP_P03_LL_DBG_8 0x00080008ULKSYS_MFP_P03_MDM_DBG_5 0x00080800ULLSYS_MFP_P03_RESERVED 0x00080808ULMSYS_MFP_P03_Msk 0x00080808ULOSYS_MFP_P04_GPIO 0x00000000ULPSYS_MFP_P04_UART0_RTS 0x00000010ULQSYS_MFP_P04_SPI0_CLK 0x00001000ULRSYS_MFP_P04_PWM_CH3 0x00001010ULSSYS_MFP_P04_TIMER0_EXT 0x00100000ULTSYS_MFP_P04_LL_DBG_9 0x00100010ULUSYS_MFP_P04_MDM_DBG_6 0x00101000ULVSYS_MFP_P04_RESERVED 0x00101010ULWSYS_MFP_P04_Msk 0x00101010ULYSYS_MFP_P05_GPIO 0x00000000ULZSYS_MFP_P05_UART0_TX 0x00000020UL[SYS_MFP_P05_SPI0_MISO 0x00002000UL\SYS_MFP_P05_PWM_CH4 0x00002020UL]SYS_MFP_P05_EXT_STADC 0x00200000UL^SYS_MFP_P05_LL_DBG_12 0x00200020UL_SYS_MFP_P05_MDM_DBG_9 0x00202000UL`SYS_MFP_P05_RESERVED 0x00202020ULaSYS_MFP_P05_Msk 0x00202020ULcSYS_MFP_P06_GPIO 0x00000000ULdSYS_MFP_P06_UART0_RX 0x00000040ULeSYS_MFP_P06_SPI0_MISO 0x00004000ULfSYS_MFP_P06_PWM_CH5 0x00004040ULgSYS_MFP_P06_TIMER1_EXT 0x00400000ULhSYS_MFP_P06_LL_DBG_13 0x00400040ULiSYS_MFP_P06_MDM_DBG_3 0x00404000ULjSYS_MFP_P06_AHB_CLK 0x00404040ULkSYS_MFP_P06_Msk 0x00404040ULmSYS_MFP_P07_GPIO 0x00000000ULnSYS_MFP_P07_UART1_RX 0x00000080ULoSYS_MFP_P07_I2C0_SCL 0x00008000ULpSYS_MFP_P07_SPI0_MOSI 0x00008080ULqSYS_MFP_P07_PWM_CH0 0x00800000ULrSYS_MFP_P07_LL_DBG_10 0x00800080ULsSYS_MFP_P07_MDM_DBG_7 0x00808000ULtSYS_MFP_P07_RESERVED 0x00808080ULuSYS_MFP_P07_Msk 0x00808080ULxSYS_MFP_P10_GPIO 0x00000000ULySYS_MFP_P10_UART1_TX 0x00000001ULzSYS_MFP_P10_I2C0_SDA 0x00000100UL{SYS_MFP_P10_SPI0_MISO 0x00000101UL|SYS_MFP_P10_PWM_CH5 0x00010000UL}SYS_MFP_P10_LL_DBG_11 0x00010001UL~SYS_MFP_P10_MDM_DBG_8 0x00010100ULSYS_MFP_P10_RESERVED 0x00010101UL€SYS_MFP_P10_Msk 0x00010101UL‚SYS_MFP_P11_GPIO 0x00000000ULƒSYS_MFP_P11_UART1_RTS 0x00000002UL„SYS_MFP_P11_SPI0_MOSI 0x00000200UL…SYS_MFP_P11_PWM_CH7 0x00000202UL†SYS_MFP_P11_CLK_32K 0x00020000UL‡SYS_MFP_P11_LL_DBG_9 0x00020002ULˆSYS_MFP_P11_MDM_DBG_0 0x00020200UL‰SYS_MFP_P11_UART0_TX 0x00020202ULŠSYS_MFP_P11_Msk 0x00020202ULŒSYS_MFP_P12_GPIO 0x00000000ULSYS_MFP_P12_UART0_RX 0x00000004ULŽSYS_MFP_P12_PWM_CH4 0x00000400ULSYS_MFP_P12_TIMER0_CNT_OUT 0x00000404ULSYS_MFP_P12_UART1_TX 0x00040000UL‘SYS_MFP_P12_LL_DBG_4 0x00040004UL’SYS_MFP_P12_MDM_DBG_17 0X00040400UL“SYS_MFP_P12_SPI0_MISO 0x00040404UL”SYS_MFP_P12_Msk 0x00040404UL–SYS_MFP_P13_GPIO 0x00000000UL—SYS_MFP_P13_UART0_RTS 0x00000008UL˜SYS_MFP_P13_I2C0_SDA 0x00000800UL™SYS_MFP_P13_PWM_CH3 0x00000808ULšSYS_MFP_P13_LL_DBG_3 0x00080000UL›SYS_MFP_P13_MDM_DBG_16 0x00080008ULœSYS_MFP_P13_SPI1_CS 0x00080800ULSYS_MFP_P13_SPI0_CS 0x00080808ULžSYS_MFP_P13_Msk 0x00080808UL SYS_MFP_P14_GPIO 0x00000000UL¡SYS_MFP_P14_UART0_CTS 0x00000010UL¢SYS_MFP_P14_I2C0_SCL 0x00001000UL£SYS_MFP_P14_PWM_CH2 0x00001010UL¤SYS_MFP_P14_LL_DEBUG_2 0x00100000UL¥SYS_MFP_P14_MDM_DBG_15 0x00100010UL¦SYS_MFP_P14_SPI0_CLK 0x00101000UL§SYS_MFP_P14_RESERVED 0x00101010UL¨SYS_MFP_P14_Msk 0x00101010ULªSYS_MFP_P15_GPIO 0x00000000UL«SYS_MFP_P15_SPI0_CS 0x00000020UL¬SYS_MFP_P15_PWM_CH5 0x00002000UL­SYS_MFP_P15_TIMER0_EXT 0x00002020UL®SYS_MFP_P15_UART0_RX 0x00200000UL¯SYS_MFP_P15_LL_DBG_5 0x00200020UL°SYS_MFP_P15_MDM_DBG_18 0x00202000UL±SYS_MFP_P15_RESERVED 0x00202020UL²SYS_MFP_P15_Msk 0x00202020UL´SYS_MFP_P16_GPIO 0x00000000ULµSYS_MFP_P16_UART0_TX 0x00000040UL¶SYS_MFP_P16_TIMER2_CNT_OUT 0x00004000UL·SYS_MFP_P16_PWM_CH0 0x00004040UL¸SYS_MFP_P16_LL_DBG_0 0x00400000UL¹SYS_MFP_P16_MDM_DBG_13 0x00400040ULºSYS_MFP_P16_SPI1_CLK 0x00404000UL»SYS_MFP_P16_I2C0_SCL 0x00404040UL¼SYS_MFP_P16_Msk 0x00404040UL¾SYS_MFP_P17_GPIO 0x00000000UL¿SYS_MFP_P17_UART0_RX 0x00000080ULÀSYS_MFP_P17_TIMER2_EXT 0x00008000ULÁSYS_MFP_P17_PWM_CH1 0x00008080ULÂSYS_MFP_P17_LL_DBG_1 0x00800000ULÃSYS_MFP_P17_MDM_DBG_14 0x00800080ULÄSYS_MFP_P17_RCH 0x00808000ULÅSYS_MFP_P17_RESERVED 0x00808080ULÆSYS_MFP_P17_Msk 0x00808080ULÉSYS_MFP_P20_GPIO 0x00000000ULÊSYS_MFP_P20_SPI1_MISO 0x00000001ULËSYS_MFP_P20_PWM_CH6 0x00000100ULÌSYS_MFP_P20_TADC_CLK 0x00000101ULÍSYS_MFP_P20_LL_DBG_6 0x00010000ULÎSYS_MFP_P20_MDM_DBG_2 0x00010001ULÏSYS_MFP_P20_XTL_C1_CLK 0x00010100ULÐSYS_MFP_P20_RESERVED 0x00010101ULÑSYS_MFP_P20_Msk 0x00010101ULÓSYS_MFP_P21_GPIO 0x00000000ULÔSYS_MFP_P21_SPI1_MOSI 0x00000002ULÕSYS_MFP_P21_PWM_CH7 0x00000200ULÖSYS_MFP_P21_TADC_VLD 0x00000202UL×SYS_MFP_P21_LL_DBG_7 0x00020000ULØSYS_MFP_P21_MDM_DBG_1 0x00020002ULÙSYS_MFP_P21_XTL_C2_CLK 0x00020200ULÚSYS_MFP_P21_RESERVED 0x00020202ULÛSYS_MFP_P21_Msk 0x00020202ULÝSYS_MFP_P22_GPIO 0x00000000ULÞSYS_MFP_P22_SPI1_CLK 0x00000004ULßSYS_MFP_P22_PWM_CH0 0x00000400ULàSYS_MFP_P22_RESERVED 0x00000404ULáSYS_MFP_P22_TADC_DATl 0x00040000ULâSYS_MFP_P22_MDM_DBG_0 0x00040004ULãSYS_MFP_P22_SPI0_MOSI 0x00040400ULäSYS_MFP_P22_RESERVED1 0x00040404ULåSYS_MFP_P22_Msk 0x00040404ULçSYS_MFP_P23_GPIO 0x00000000ULèSYS_MFP_P23_SPI1_CS 0x00000008ULéSYS_MFP_P23_PWM_CH1 0x00000800ULêSYS_MFP_P23_DPLL_DIV8 0x00000808ULëSYS_MFP_P23_TADC_DATH 0x00080000ULìSYS_MFP_P23_MDM_DBG_10 0x00080008ULíSYS_MFP_P23_I2C0_SCL 0x00080800ULîSYS_MFP_P23_RESERVED 0x00080808ULïSYS_MFP_P23_Msk 0x00080808ULñSYS_MFP_P24_GPIO 0x00000000ULòSYS_MFP_P24_SPI1_MISO 0x00000010ULóSYS_MFP_P24_UART1_RX 0x00001000ULôSYS_MFP_P24_PWM_CH2 0x00001010ULõSYS_MFP_P24_TIMER1_CNT_OUT 0x00100000ULöSYS_MFP_P24_MDM_DBG_4 0x00100010UL÷SYS_MFP_P24_RESERVED 0x00101000ULøSYS_MFP_P24_RESERVED1 0x00101010ULùSYS_MFP_P24_Msk 0x00101010ULûSYS_MFP_P25_GPIO 0x00000000ULüSYS_MFP_P25_SPI1_MOSI 0x00000020ULýSYS_MFP_P25_UART1_TX 0x00002000ULþSYS_MFP_P25_PWM_CH3 0x00002020ULÿSYS_MFP_P25_MDM_DBG_5 0x00200000UL€SYS_MFP_P25_RESERVED 0x00200020ULSYS_MFP_P25_I2C0_SDA 0x00202000UL‚SYS_MFP_P25_RESERVED1 0x00202020ULƒSYS_MFP_P25_Msk 0x00202020UL…SYS_MFP_P26_GPIO 0x00000000UL†SYS_MFP_P26_UART1_RTS 0x00000040UL‡SYS_MFP_P26_PWM_CH4 0x00004000ULˆSYS_MFP_P26_SPI1_CS 0x00004040UL‰SYS_MFP_P26_MDM_DBG_4 0x00400000ULŠSYS_MFP_P26_MDM_DBG_10 0x00400040UL‹SYS_MFP_P26_RESERVED 0x00404000ULŒSYS_MFP_P26_RESERVED1 0x00404040ULSYS_MFP_P26_Msk 0x00404040ULSYS_MFP_P27_GPIO 0x00000000ULSYS_MFP_P27_UART1_CTS 0x00000080UL‘SYS_MFP_P27_PWM_CH5 0x00008000UL’SYS_MFP_P27_SPI1_CLK 0x00008080UL“SYS_MFP_P27_RESERVED 0x00800000UL”SYS_MFP_P27_MDM_DBG_20 0x00800080UL•SYS_MFP_P27_XTH 0x00808000UL–SYS_MFP_P27_RESERVED1 0x00808080UL—SYS_MFP_P27_Msk 0x00808080ULšSYS_MFP_P30_GPIO 0x00000000UL›SYS_MFP_P30_UART1_RX 0x00000001ULœSYS_MFP_P30_PWM_CH6 0x00000100ULSYS_MFP_P30_SPI1_MISO 0x00000101ULžSYS_MFP_P30_MDM_DBG_10 0x00010000ULŸSYS_MFP_P30_RESERVED 0x00010001UL SYS_MFP_P30_RESERVED1 0x00010100UL¡SYS_MFP_P30_RESERVED2 0x00010101UL¢SYS_MFP_P30_Msk 0x00010101UL¤SYS_MFP_P31_GPIO 0x00000000UL¥SYS_MFP_P31_UART1_TX 0x00000002UL¦SYS_MFP_P31_PWM_CH7 0x00000200UL§SYS_MFP_P31_SPI1_MOSI 0x00000202UL¨SYS_MFP_P31_RESERVED 0x00020000UL©SYS_MFP_P31_RESERVED1 0x00020002ULªSYS_MFP_P31_RESERVED2 0x00020200UL«SYS_MFP_P31_RESERVED3 0x00020202UL¬SYS_MFP_P31_Msk 0x00020202UL¶SYS_SET_MFP(Port,Bit,Func) (SYS->Port ## _MFP = (SYS->Port ## _MFP & ~SYS_MFP_ ## Port ## Bit ## _Msk) | SYS_MFP_ ## Port ## Bit ## _ ## Func)pg ..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_sys.h0


..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_sys.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x<œÃSYS_UnlockReg<±ÔSYS_LockReg‚ƒ__PAN_CLK_H__ CLK_APB1_WDTSEL_MILLI_PULSE (0x00010000UL)CLK_APB1_WDTSEL_RCL32K (0x00000000UL)CLK_APB1_WWDTSEL_MILLI_PULSE (0x00000000UL) CLK_APB1_WWDTSEL_RCL32K (0x00020000UL)"CLK_APB1_TMR0SEL_APB1CLK (0x00000000UL)#CLK_APB1_TMR0SEL_RCL32K (0x00040000UL)$CLK_APB1_TMR0SEL_TM0 (0x00080000UL)&CLK_APB2_TMR1SEL_APB2CLK (0x00000000UL)'CLK_APB2_TMR1SEL_RCL32K (0x00000100UL)(CLK_APB2_TMR1SEL_TM1 (0x00000200UL)*CLK_APB2_TMR2SEL_APB2CLK (0x00000000UL)+CLK_APB2_TMR2SEL_RCL32K (0x00000400UL),CLK_APB2_TMR2SEL_TM2 (0x00000800UL).CLK_APB1_PWM_CH01_SEL_APB (0x00000000UL)/CLK_APB1_PWM_CH01_SEL_CLK32K (0x00100000UL)0CLK_APB1_PWM_CH23_SEL_APB (0x00000000UL)1CLK_APB1_PWM_CH23_SEL_CLK32K (0x00200000UL)2CLK_APB1_PWM_CH45_SEL_APB (0x00000000UL)3CLK_APB1_PWM_CH45_SEL_CLK32K (0x00400000UL)4CLK_APB1_PWM_CH67_SEL_APB (0x00000000UL)5CLK_APB1_PWM_CH67_SEL_CLK32K (0x00800000UL);FREQ_1MHZ (1000000)<FREQ_8MHZ (8000000)=FREQ_16MHZ (16000000)>FREQ_25MHZ (25000000)?FREQ_32MHZ (32000000)@FREQ_48MHZ (48000000)AFREQ_64MHZ (64000000)BFREQ_96MHZ (96000000)CFREQ_50MHZ (50000000)DFREQ_72MHZ (72000000)EFREQ_100MHZ (100000000)LCLK_SYS_SRCSEL_RCH ((uint32_t)0x00000000)MCLK_SYS_SRCSEL_XTH ((uint32_t)0x00000100)NCLK_SYS_SRCSEL_DPLL ((uint32_t)0x00000200)UCLK_DPLL_REF_CLKSEL_RCH ((uint32_t)0x00000000)VCLK_DPLL_REF_CLKSEL_XTH ((uint32_t)0x00000008)WCLK_DPLL_OUT_48M ((uint32_t)0x00000000)XCLK_DPLL_OUT_64M ((uint32_t)0x00000004)`CLK_APB1Periph_I2C0 ((uint32_t)0x00000001)aCLK_APB1Periph_SPI0 ((uint32_t)0x00000002)bCLK_APB1Periph_UART0 ((uint32_t)0x00000008)cCLK_APB1Periph_PWM0_CH01 ((uint32_t)0x00000010)dCLK_APB1Periph_PWM0_CH23 ((uint32_t)0x00000020)eCLK_APB1Periph_PWM0_CH45 ((uint32_t)0x00000040)fCLK_APB1Periph_PWM0_CH67 ((uint32_t)0x00000080)gCLK_APB1Periph_PWM0_EN ((uint32_t)0x00000100)hCLK_APB1Periph_ADC ((uint32_t)0x00000200)iCLK_APB1Periph_WDT ((uint32_t)0x00000400)jCLK_APB1Periph_WWDT ((uint32_t)0x00000800)kCLK_APB1Periph_TMR0 ((uint32_t)0x00001000)lCLK_APB1Periph_MILI_CLK ((uint32_t)0x00002000)mCLK_APB1Periph_All ((uint32_t)0x00003ffb)uCLK_APB2Periph_SPI1 ((uint32_t)0x00000002)vCLK_APB2Periph_UART1 ((uint32_t)0x00000008)wCLK_APB2Periph_TMR1 ((uint32_t)0x00000010)xCLK_APB2Periph_TMR2 ((uint32_t)0x00000020)yCLK_APB2Periph_All ((uint32_t)0x0000003a)€CLK_AHBPeriph_DMAC ((uint32_t)0x00000001)CLK_AHBPeriph_GPIO ((uint32_t)0x00000002)‚CLK_AHBPeriph_SYSTICK ((uint32_t)0x00000004)ƒCLK_AHBPeriph_APB1 ((uint32_t)0x00000008)„CLK_AHBPeriph_APB2 ((uint32_t)0x00000010)…CLK_AHBPeriph_AHB ((uint32_t)0x00000020)†CLK_AHBPeriph_BLE_32M ((uint32_t)0x00000040)‡CLK_AHBPeriph_BLE_32K ((uint32_t)0x00000080)‰CLK_AHBPeriph_ROM ((uint32_t)0x00000400)ŠCLK_AHBPeriph_EFUSE ((uint32_t)0x00000800)‹CLK_AHBPeriph_USB_AHB ((uint32_t)0x00002000)ŒCLK_AHBPeriph_USB_48M ((uint32_t)0x00004000)CLK_AHBPeriph_All ((uint32_t)0x00006CFF)“CLK_DivideSource_Ahb (1)”CLK_DivideSource_Apb1 (2)•CLK_DivideSource_Apb2 (4)›CLK_RCL_SELECT (0)œCLK_RCH_SELECT (1)CLK_XTL_SELECT (2)žCLK_XTH_SELECT (3)ŸCLK_DPLL_SELECT (4)¢CLK_STABLE_STATUS_Pos (24)£CLK_STABLE_STATUS_Msk (0x1ul << CLK_STABLE_STATUS_Pos)¥CLKTRIM_CALC_CLK_SEL_32K (0)¦CLKTRIM_CALC_CLK_SEL_32M (1)¨CLKTRIM_QDEC_CLK_SEL_APB (0)©CLKTRIM_QDEC_CLK_SEL_32K (1)«CLKTRIM_KSCAN_CLK_SEL_APB (0)¬CLKTRIM_KSCAN_CLK_SEL_32K (1)³DMA_RST ((0x0<<24) | CLK_IPRST0_DMARST_Pos )´LL_RST ((0x0<<24) | CLK_IPRST0_RFRST_Pos )µEFUSE_RST ((0x0<<24) | CLK_IPRST0_EFUSERST_Pos )¶USB_RST ((0x0<<24) | CLK_IPRST0_USBRST_Pos )·MDMSTB_RST ((0x0<<24) | CLK_IPRST0_MDMSTDBYRST_Pos )¸MDM_RST ((0x0<<24) | CLK_IPRST0_MDMRST_Pos )¹I2C0_RST ((0x4<<24) | CLK_IPRST1_I2C0RST_Pos )ºSPI0_RST ((0x4<<24) | CLK_IPRST1_SPI0RST_Pos )»SPI1_RST ((0x4<<24) | CLK_IPRST1_SPI1RST_Pos )¼UART0_RST ((0x4<<24) | CLK_IPRST1_UART0RST_Pos )½UART1_RST ((0x4<<24) | CLK_IPRST1_UART1RST_Pos )¾PWM0_RST ((0x4<<24) | CLK_IPRST1_PWM0RST_Pos )¿ADC_RST ((0x4<<24) | CLK_IPRST1_ADCRST_Pos )ÀWDT_RST ((0x4<<24) | CLK_IPRST1_WDTRST_Pos )ÁWWDT_RST ((0x4<<24) | CLK_IPRST1_WWDTRST_Pos )ÂTMR0_RST ((0x4<<24) | CLK_IPRST1_TMR0RST_Pos )ÃTMR1_RST ((0x4<<24) | CLK_IPRST1_TMR1RST_Pos )ÄTMR2_RST ((0x4<<24) | CLK_IPRST1_TMR2RST_Pos )ÅGPIO_RST ((0x4<<24) | CLK_IPRST1_GPIORST_Pos )ÆCLKTRIM_RST ((0x4<<24) | CLK_IPRST1_TRIMRST_Pos )ÎCLK_BODCTL_BOD_INT_EN (0UL<<CLK_BODCTL_BODRSTEN_Pos_3v)ÏCLK_BODCTL_BOD_RST_EN (1UL<<CLK_BODCTL_BODRSTEN_Pos_3v)ÐCLK_BODCTL_BODSEL_1_75V (0UL<<CLK_BODCTL_BODSEL_Pos_3v)ÑCLK_BODCTL_BODSEL_1_95V (1UL<<CLK_BODCTL_BODSEL_Pos_3v)ÒCLK_BODCTL_BODSEL_2_15V (2UL<<CLK_BODCTL_BODSEL_Pos_3v)ÓCLK_BODCTL_BODSEL_2_35V (3UL<<CLK_BODCTL_BODSEL_Pos_3v)ÔCLK_BODCTL_BODSEL_2_55V (4UL<<CLK_BODCTL_BODSEL_Pos_3v)ÕCLK_BODCTL_BODSEL_2_75V (5UL<<CLK_BODCTL_BODSEL_Pos_3v)ÖCLK_BODCTL_BODSEL_2_95V (6UL<<CLK_BODCTL_BODSEL_Pos_3v)ßCLK_BLDBCTL_BODDBSEL_2POW0 0x00000001ULàCLK_BLDBCTL_BODDBSEL_2POW1 0x00000002ULáCLK_BLDBCTL_BODDBSEL_2POW2 0x00000004ULâCLK_BLDBCTL_BODDBSEL_2POW3 0x00000008ULãCLK_BLDBCTL_BODDBSEL_2POW4 0x00000010ULäCLK_BLDBCTL_BODDBSEL_2POW5 0x00000020ULìCLK_BLDBCTL_LVRDBSEL_2POW0 0x00000100ULíCLK_BLDBCTL_LVRDBSEL_2POW1 0x00000200ULîCLK_BLDBCTL_LVRDBSEL_2POW2 0x00000400ULïCLK_BLDBCTL_LVRDBSEL_2POW3 0x00000800ULðCLK_BLDBCTL_LVRDBSEL_2POW4 0x00001000ULñCLK_BLDBCTL_LVRDBSEL_2POW5 0x00002000ULpg ..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_clk.h


..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_clk.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xCLK_FLASH_CLKDIV_1CLK_FLASH_CLKDIV_2CLK_FLASH_CLKDIV_4CLK_FLASH_CLKDIV_8CLK_FLASH_CLKDIV_16CLK_FLASH_CLKDIV_30<®øCLK_XthStartupConfig<Ö„CLK_HCLKConfig$Yu32ClkDiv<ÿCLK_PCLK1Config$Yu32ClkDiv<¨œCLK_PCLK2Config$Yu32ClkDiv<Ò¾CLK_SetDpllOutputFreq$Yfreq<üáCLK_EnableClkTrim$åNewState<¤ïCLK_SelectClkTrimSrc$Ysrc<ÙûCLK_SetClkTrimCalClkDiv$Idiv\regY<‰•CLK_SetFlashClkDiv$:div\regY…†‡ˆ __PAN_ADC_H__ ADC_INPUTRANGE_HIGH (1UL)ADC_INPUTRANGE_LOW (0UL)ADC_CH8_EXT (0UL)ADC_CH8_BGP (ADC_CHEN_CH8SEL_Msk) ADC_CMP0_LESS_THAN (0UL << ADC_CMP0_CMPCOND_Pos)!ADC_CMP1_LESS_THAN (0UL << ADC_CMP1_CMPCOND_Pos)"ADC_CMP0_GREATER_OR_EQUAL_TO (1ul << ADC_CMP0_CMPCOND_Pos)#ADC_CMP1_GREATER_OR_EQUAL_TO (1ul << ADC_CMP1_CMPCOND_Pos)$ADC_TRIGGER_BY_EXT_PIN (0UL << ADC_CTL_HWTRGSEL_Pos)%ADC_TRIGGER_BY_PWM (ADC_CTL_HWTRGSEL_Msk)&ADC_FALLING_EDGE_TRIGGER (0UL << ADC_CTL_HWTRGCOND_Pos)'ADC_RISING_EDGE_TRIGGER (ADC_CTL_HWTRGCOND_Msk),ADC_ADIF_INT (ADC_STATUS_ADIF_Msk)-ADC_CMP0_INT (ADC_STATUS_ADCMPIF0_Msk).ADC_CMP1_INT (ADC_STATUS_ADCMPIF1_Msk)/ADC_FIFO_FULL_INT (ADC_STATUS_INTFLG_FULL_Msk)0ADC_FIFO_EMPTY_INT (ADC_STATUS_INTFLG_EMPTY_Msk)1ADC_FIFO_OVER_INT (ADC_STATUS_INTFLG_OVER_Msk)2ADC_FIFO_HALF_INT (ADC_STATUS_INTFLG_HALF_Msk)8ADC_SAMPLE_CLOCK_0 (0UL)9ADC_SAMPLE_CLOCK_1 (1UL):ADC_SAMPLE_CLOCK_2 (2UL);ADC_SAMPLE_CLOCK_4 (3UL)<ADC_SAMPLE_CLOCK_8 (4UL)=ADC_SAMPLE_CLOCK_16 (5UL)>ADC_SAMPLE_CLOCK_32 (6UL)?ADC_SAMPLE_CLOCK_64 (7UL)@ADC_SAMPLE_CLOCK_128 (8UL)AADC_SAMPLE_CLOCK_256 (9UL)BADC_SAMPLE_CLOCK_512 (10UL)CADC_SAMPLE_CLOCK_1024 (11UL)DADC_SEQMODE_TYPE_23SHUNT (0UL)EADC_SEQMODE_TYPE_1SHUNT (1UL)FADC_SEQMODE_MODESELECT_CH01 (0UL)GADC_SEQMODE_MODESELECT_CH12 (1UL)HADC_SEQMODE_MODESELECT_CH02 (2UL)IADC_SEQMODE_MODESELECT_ONE (3UL)JADC_SEQMODE_PWM0_RISING (0UL)KADC_SEQMODE_PWM0_CENTER (1UL)LADC_SEQMODE_PWM0_FALLING (2UL)MADC_SEQMODE_PWM0_PERIOD (3UL)NADC_SEQMODE_PWM2_RISING (4UL)OADC_SEQMODE_PWM2_CENTER (5UL)PADC_SEQMODE_PWM2_FALLING (6UL)QADC_SEQMODE_PWM2_PERIOD (7UL)RADC_SEQMODE_PWM4_RISING (8UL)SADC_SEQMODE_PWM4_CENTER (9UL)TADC_SEQMODE_PWM4_FALLING (10UL)UADC_SEQMODE_PWM4_PERIOD (11UL)VADC_SEQMODE_PWM6_RISING (12UL)WADC_SEQMODE_PWM6_CENTER (13UL)XADC_SEQMODE_PWM6_FALLING (14UL)YADC_SEQMODE_PWM6_PERIOD (15UL)\ADC_COMPARATOR_0 (0)]ADC_COMPARATOR_1 (1)_ADC_FIFO_TRIG_LEVEL_HALF (0)`ADC_FIFO_TRIG_LEVEL_FULL (1)pg ..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_adc.hì


..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_adc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xfloat_BoolPADC_OPT_TZvqm_adc_optqglobal_calc_vbat_mvY;‘‚ADC_GetConversionDataY$‘ADCxa__resultY"Ï;×”ADC_StatusFlag$‘ADCx$YIntMaska__result<‹¦ADC_ClearStatusFlag$‘ADCx$YIntMask<ƹADC_IntMask$‘ADCx$YIntMask$åNewState;ˆÌADC_IsIntOccured$‘ADCx$YIntMaska__result<¹ßADC_ClearIntFlag$‘ADCx$YIntMask;çëADC_IsBusy$‘ADCxa__result;œ÷ADC_IsDataOverrun$‘ADCxa__result;σADC_IsDataValid$‘ADCxa__result<ïADC_PowerDown$‘ADCx<—ADC_PowerOn$‘ADCx<¹¡ADC_SequentialModeDisable$‘ADCx<í¬ADC_Trigger2Select$‘ADCx$åNewState<“¶ADC_DisableCompare0$‘ADCx<¹ÀADC_DisableCompare1$‘ADCx<ÜÊADC_StartConvert$‘ADCx<þÓADC_StopConvert$‘ADCx<£    ÞADC_TestModeEnable$‘ADCx<É    èADC_TestModeDisable$‘ADCx<ü    óADC_DmaModeEnable$‘ADCx$åNewState<°


ÿADC_SetClockDivider$‘ADCx$YDivider<Ø


ADC_Open$‘ADCx$YChMask<˜ADC_SelInputRange$‘ADCx$YEnableHigh<»¢ADC_TriggerDelay$‘ADCx$YData<õ¸ADC_SetExtraSampleTime$‘ADCx$YSampleTime;®ÃADC_IsOneChConvertEnd$‘ADCxa__result<ÝÏADC_ClearByHw$‘ADCx$åNewState<Ž ÛADC_LeftShiftEn$‘ADCx$åNewState< çADC_SubtractBiasEn$‘ADCx$åNewState<ó óADC_SetBiasData$‘ADCx$YBiasData<¦‚ADC_SetFifoTrigLevel$‘ADCx$:Level<ڏADC_SeqModeOneChEn$‘ADCx$åNewState*ì@chip_info:#ft_version:#adc_vdd_bÿ#adc_vdd_kI#adc_vbg_kI#adc_vbg_b #adc_temp_voltI#


current_temp_value #!adc_vbg_1v20_trim:#!rsvd_0x30:#Ãn


adc_vbg_kb8#adc_vbat_kI#,adc_vbat_b #.adc_vbat_dtemp_k #0adc_vbat_dtemp_b #2adc_temp_k#4adc_ctrl2Y#8adc_extsmptY#<4ð(m_adc_opt8global_calc_vbat_mvŠ‹Œ __PAN_FMC_H__ M32(adr) (*((vu32 *) (adr)))CMD_ERASE_PAGE (0X81)CMD_ERASE_SECTOR (0X20) CMD_ERASE_32K (0X52)!CMD_ERASE_64K (0Xd8)"CMD_ERASE_CHIP (0xc7)(CMD_READ_STATUS_L (0x05))CMD_READ_STATUS_H (0x35)*CMD_WRITE_STATUS (0x01)0OPS_WR_STU_REG_NOR (0x00)1OPS_WR_STU_REG_ALL (0x01)7CMD_FAST_READ (0x0b)8CMD_NORM_READ (0x03)9CMD_DREAD (0x3B):CMD_2READ (0xBB);CMD_QREAD (0x6B)<CMD_4READ (0xEB)BCMD_BURST_READ (0x77)CBURST_READ_MODE_8 (0x00)DBURST_READ_MODE_16 (0x01)EBURST_READ_MODE_32 (0x02)FBURST_READ_MODE_64 (0x03)JCMD_TRIG (0x01)KCMD_WRITE_ENABLE (0x06)LCMD_WRITE_DISABLE (0x04)QFLASH_X1_MODE 0RFLASH_X2_MODE 1SFLASH_X4_MODE 2VQUAD_ENABLE_Pos (9)WQUAD_ENABLE_Msk (0x1ul << QUAD_ENABLE_Pos)XWrite_Enable_Latch_Pos (1)YWrite_Enable_Latch_Msk (0x1ul << Write_Enable_Latch_Pos)ZWrite_In_Process_Pos (0)[Write_In_Process_Msk (0x1ul << Write_In_Process_Pos)\Long_Time_Op_Pos (17)^PAGE_SIZE (256)_SECTOR_SIZE (4096)pg ..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_fmc.h\


..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_fmc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x_Bool; FMC_IsBusyWorking$*fmca__result*úmemory_type_id:#memory_density_id:#S•‰:d~B)Ü_flash_idsmanufacturer_id:#z#Ð:uidÅ#PFLASH_IDS_T•tqflash_idsÜ<ªFMC_EnterDeepPowerDownMode$*fmc"<ېFMC_ExitDeepPowerDownMode$*fmc`ïflash_ids‘__PAN_DMAC_H__ DMAC_CHANNEL_NUMBER 2DMA_INVLID_CHANNEL (~0ul)$DMAC_TransferType_Mem2Mem (0)%DMAC_TransferType_Mem2Per (1)&DMAC_TransferType_Per2Mem (2)'DMAC_TransferType_Per2Per (3)+DMAC_FlowControl_DMA (0),DMAC_FlowControl_Peripheral (1)2DMAC_BurstLen_1 (0)3DMAC_BurstLen_4 (1)4DMAC_BurstLen_8 (2)5DMAC_BurstLen_16 (3)6DMAC_BurstLen_32 (4)7DMAC_BurstLen_64 (5)8DMAC_BurstLen_128 (6)9DMAC_BurstLen_256 (7)@DMAC_AddrChange_Increment (0)ADMAC_AddrChange_Decrement (1)BDMAC_AddrChange_NoChange (2)IDMAC_DataWidth_8 (0)JDMAC_DataWidth_16 (1)KDMAC_DataWidth_32 (2)LDMAC_DataWidth_64 (3)MDMAC_DataWidth_128 (4)NDMAC_DataWidth_256 (5)UDMAC_Peripheral_I2C0_Tx 0VDMAC_Peripheral_I2C0_Rx 1WDMAC_Peripheral_SPI0_Tx 2XDMAC_Peripheral_SPI0_Rx 3YDMAC_Peripheral_UART0_Tx 4ZDMAC_Peripheral_UART0_Rx 5]DMAC_Peripheral_SPI1_Tx 8^DMAC_Peripheral_SPI1_Rx 9_DMAC_Peripheral_UART1_Tx 10`DMAC_Peripheral_UART1_Rx 11aDMAC_Peripheral_ADC 12bDMAC_Peripheral_USB_Rx 15cDMAC_Peripheral_USB_Tx 14hDMAC_HandshakePolarity_Low (1)iDMAC_HandshakePolarity_High (0)pDMAC_Handshake_Default (1)qDMAC_Handshake_Software (1)rDMAC_Handshake_Hardware (0)uDMAC_LockLevel_Tfr_Complete (0)vDMAC_LockLevel_Block_Complete (1)wDMAC_LockLevel_Transaction_Complete (2)|DMAC_ChannelPriority_0 (0)}DMAC_ChannelPriority_1 (1)~DMAC_ChannelPriority_2 (2)DMAC_ChannelPriority_3 (3)€DMAC_ChannelPriority_4 (4)DMAC_ChannelPriority_5 (5)‚DMAC_ChannelPriority_6 (6)ƒDMAC_ChannelPriority_7 (7)‡DMAC_CHANNELALL_MASK (~((~0ul)<<DMAC_CHANNEL_NUMBER))ŒDMAC_FLAG_INDEX_TFR (0<<1)DMAC_FLAG_INDEX_BLK (1<<1)ŽDMAC_FLAG_INDEX_SRCTFR (2<<1)DMAC_FLAG_INDEX_DSTTFR (3<<1)DMAC_FLAG_INDEX_ERR (4<<1)˜DMAC_FLAG_MASK_TFR (1ul<<(DMAC_FLAG_INDEX_TFR >>1))™DMAC_FLAG_MASK_BLK (1ul<<(DMAC_FLAG_INDEX_BLK >>1))šDMAC_FLAG_MASK_SRCTFR (1ul<<(DMAC_FLAG_INDEX_SRCTFR>>1))›DMAC_FLAG_MASK_DSTTFR (1ul<<(DMAC_FLAG_INDEX_DSTTFR>>1))œDMAC_FLAG_MASK_ERR (1ul<<(DMAC_FLAG_INDEX_ERR >>1))DMAC_FLAG_MASK_ALL (0x1Ful)ŸDMAC_ChannelMask(idx) (1ul<<(idx))th ..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_dmac.h


..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_dmac.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x)ã__DMAC_ChannelConfigTypeDefCTL_LY#CTL_HY#CFG_LY#CFG_HY#P__DMAC_ChannelConfigTypeDef¯)·


DMAC_ChannelConfigTypeDef!IntEnableY#!DataWidthDstY#!DataWidthSrcY#!AddrChangeDstY#!AddrChangeSrcY#!BurstLenDstY#!BurstLenSrcY#!GatherEnSrcY#!ScatterEnDstY# !__Rev0Y#!TransferTypeY#


!FlowControlY#    !__Rev1Y#    !BlockSizeY#!DoneY#!__Rev3Y#!__Rev4Y#!ChannelPriorityY#!ChannelSuspendY#!FifoEmptyY#!HandshakeDstY#!HandshakeSrcY#!LockBusY#!LockChannelY#!LockBusLevelY#!LockChannelLevelY#!HandshakePolarityDstY# !HandshakePolaritySrcY#!__Rev6Y#


!AutoReloadSrcY#!AutoReloadDstY#!FlowControlModeY#!FifoModeY#!ProtectControlY#!__Rev7Y#!PeripheralSrcY#!PeripheralDstY#!__Rev8Y#PDMAC_ChannelConfigTypeDef‡;Ÿ–DMAC_IsChannelValidY$Ÿdma$YChIdxa__resultY"S;ï­DMAC_CombinedIntStatusY$Ÿdma$YFlgMska__resultY;¾¾DMAC_StatusFlagY$Ÿdma$YChIdx$YFlgIdxa__resultY;Š ÊDMAC_IntFlagY$Ÿdma$YChIdx$YFlgIdxa__resultY;Ù ÏDMAC_IntFlagMskY$Ÿdma$YChIdx$YFlgIdxa__resultY<“ÛDMAC_ClrIntFlag$Ÿdma$YChIdx$YFlgIdx“”• __PAN_GPIO_H__ GPIO_PIN_MAX 8xGPIO_PIN_ADDR(port,pin) (*((volatile uint32_t *)((GPIOBIT0_BASE+(0x20*(port))) + ((pin)<<2))))yP00 GPIO_PIN_ADDR(0, 0)zP01 GPIO_PIN_ADDR(0, 1){P02 GPIO_PIN_ADDR(0, 2)|P03 GPIO_PIN_ADDR(0, 3)}P04 GPIO_PIN_ADDR(0, 4)~P05 GPIO_PIN_ADDR(0, 5)P06 GPIO_PIN_ADDR(0, 6)€P07 GPIO_PIN_ADDR(0, 7)P10 GPIO_PIN_ADDR(1, 0)‚P11 GPIO_PIN_ADDR(1, 1)ƒP12 GPIO_PIN_ADDR(1, 2)„P13 GPIO_PIN_ADDR(1, 3)…P14 GPIO_PIN_ADDR(1, 4)†P15 GPIO_PIN_ADDR(1, 5)‡P16 GPIO_PIN_ADDR(1, 6)ˆP17 GPIO_PIN_ADDR(1, 7)‰P20 GPIO_PIN_ADDR(2, 0)ŠP21 GPIO_PIN_ADDR(2, 1)‹P22 GPIO_PIN_ADDR(2, 2)ŒP23 GPIO_PIN_ADDR(2, 3)P24 GPIO_PIN_ADDR(2, 4)ŽP25 GPIO_PIN_ADDR(2, 5)P26 GPIO_PIN_ADDR(2, 6)P27 GPIO_PIN_ADDR(2, 7)‘P30 GPIO_PIN_ADDR(3, 0)’P31 GPIO_PIN_ADDR(3, 1)óGPIO_EnableEINT0 GPIO_EnableInt€GPIO_DisableEINT0 GPIO_DisableIntGPIO_EnableEINT1 GPIO_EnableIntœGPIO_DisableEINT1 GPIO_DisableInt¤™ ..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\C:\Keil_v5\ARM\ARMCC\Bin\..\include\pan_gpio.hstdint.h 


..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_gpio.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x_Bool;ÓëGPIO_GetIntFlag$9gpio$Yu32PinMaska__result<‡‚GPIO_SetDebounceTime$clksrc$ðclksel;½GPIO_GetInDataY$9gpioa__resultY<êŸGPIO_SetOutData$9gpio$Ydata;¡­GPIO_GetOutDataY$9gpioa__resultY<мGPIO_Toggle$9gpio$Yu32PinMask<ÑGPIO_EnableInt$9gpio$Yu32Pin$µIntAttribs<¼áGPIO_DisableInt$9gpio$Yu32Pin¡_GPIO_ModeDefGPIO_MODE_INPUTGPIO_MODE_OUTPUTGPIO_MODE_OPEN_DRAINGPIO_MODE_QUASIPGPIO_ModeDef¼)µ_GPIO_IntAttrDefGPIO_INT_RISINGGPIO_INT_FALLINGGPIO_INT_BOTH_EDGEGPIO_INT_HIGHGPIO_INT_LOWPGPIO_IntAttrDef57˜_GPIO_ClkSrcDefGPIO_DBCTL_DBCLKSRC_RCLGPIO_DBCTL_DBCLKSRC_HCLKPGPIO_ClkSrcDefÌCð_GPIO_ClkSelDefGPIO_DBCTL_DBCLKSEL_1GPIO_DBCTL_DBCLKSEL_2GPIO_DBCTL_DBCLKSEL_4GPIO_DBCTL_DBCLKSEL_8GPIO_DBCTL_DBCLKSEL_16GPIO_DBCTL_DBCLKSEL_32GPIO_DBCTL_DBCLKSEL_64GPIO_DBCTL_DBCLKSEL_128GPIO_DBCTL_DBCLKSEL_256GPIO_DBCTL_DBCLKSEL_512    GPIO_DBCTL_DBCLKSEL_1024


GPIO_DBCTL_DBCLKSEL_2048GPIO_DBCTL_DBCLKSEL_4096GPIO_DBCTL_DBCLKSEL_8192 GPIO_DBCTL_DBCLKSEL_16384GPIO_DBCTL_DBCLKSEL_32768PGPIO_ClkSelDef.]<¹¢GPIO_ClrIntFlag$9gpio$Yu32PinMask"ž<ä»GPIO_ClrAllIntFlag$9gpio<œ ÔGPIO_DisableDebounce$9gpio$Yu32PinMask<Ó ãGPIO_EnableDebounce$9gpio$Yu32PinMask<ŽòGPIO_DisableDigitalPath$9gpio$Yu32PinMask<ȁGPIO_EnableDigitalPath$9gpio$Yu32PinMask<‚GPIO_DisablePullupPath$9gpio$Yu32PinMask<»ŸGPIO_EnablePullupPath$9gpio$Yu32PinMask<÷®GPIO_DisablePulldownPath$9gpio$Yu32PinMask<²½GPIO_EnablePulldownPath$9gpio$Yu32PinMask<êÌGPIO_DisableDoutMask$9gpio$Yu32PinMask<¡ÛGPIO_EnableDoutMask$9gpio$Yu32PinMask—˜™ __PAN_SPI_H__ jSPI_BAUD_RATE_DIV(x) ((x)?(x):(256))pg ..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_spi.hè 


..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_spi.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x_Bool;ÏäSPI_IsSpiEnabled$³ SPIxa__result\tmpregY<þõSPI_EnableDmaTx$³ SPIx\tmpregY<®„SPI_DisableDmaTx$³ SPIx\tmpregY;ñ“SPI_IsDmaTxEnabled$³ SPIxa__result\tmpregY< ¤SPI_EnableDmaRx$³ SPIx\tmpregY<гSPI_DisableDmaRx$³ SPIx\tmpregY;“ÂSPI_IsDmaRxEnabled$³ SPIxa__result\tmpregY<½ÓSPI_SendData$³ SPIx$YData;ôÞSPI_ReceiveDataY$³ SPIxa__resultY<©ïSPI_EnableIrq$³ SPIx$Êirq\tmpregY<ß„SPI_DisableIrq$³ SPIx$Êirq\tmpregY;¨™SPI_IsIrqEnabled$³ SPIx$Êirqa__result\tmpregY;î¯SPI_GetMskedActiveIrqÊ$³ SPIxa__resultÊ\tmpregY;¶ÅSPI_IsIrqActive$³ SPIx$Êirqa__result\tmpregY;    ÜSPI_IsRawIrqActive$³ SPIx$Êirqa__result\tmpregY<µ    ðSPI_ClearIrq$³ SPIx$Êirq\tmpregY;ù    ƒSPI_GetRawActiveIrqÊ$³ SPIxa__resultÊ\tmpregY;»


“SPI_IsTxFifoEmpty$³ SPIxa__result\tmpregY;ü


£SPI_IsTxFifoFull$³ SPIxa__result\tmpregY;¾´SPI_IsRxFifoEmpty$³ SPIxa__result\tmpregY;ÿÆSPI_IsRxFifoFull$³ SPIxa__result\tmpregY;ºØSPI_IsBusy$³ SPIxa__result\tmpregY<çéSPI_TxLsbEnable$³ SPIx$enable<” ôSPI_RxLsbEnable$³ SPIx$enable<½ ‚SPI_SetWireNum$³ SPIx$<num<ô SPI_DataCmdLineEnable$³ SPIx$åNewState<¦ŸSPI_DataCmdSelCmdDat$³ SPIx$ŠcmdDat<Ñ­SPI_WriteReadCtrl$³ SPIx$ÙwrÊSPI_IrqSPI_IRQ_TX_HALF_EMPTYSPI_IRQ_RX_HALF_FULLSPI_IRQ_RX_TIMEOUTSPI_IRQ_RX_OVERRUNSPI_IRQ_ALLPSPI_IrqDefQ$SPI_RoleSPI_RoleMasterSPI_RoleSlavePSPI_RoleDefÜ.ÂSPI_DataFrameSizeSPI_DataFrame_4bSPI_DataFrame_5bSPI_DataFrame_6bSPI_DataFrame_7bSPI_DataFrame_8bSPI_DataFrame_9bSPI_DataFrame_10b    SPI_DataFrame_11b


SPI_DataFrame_12bSPI_DataFrame_13bSPI_DataFrame_14b SPI_DataFrame_15bSPI_DataFrame_16bPSPI_DataFrameSizeDef P¿SPI_BaudRateDivSPI_BaudRateDiv_2SPI_BaudRateDiv_4SPI_BaudRateDiv_6SPI_BaudRateDiv_8SPI_BaudRateDiv_16SPI_BaudRateDiv_32 SPI_BaudRateDiv_480SPI_BaudRateDiv_64@SPI_BaudRateDiv_96`SPI_BaudRateDiv_128€SPI_BaudRateDiv_160 SPI_BaudRateDiv_192ÀSPI_BaudRateDiv_224àSPI_BaudRateDiv_240ðSPI_BaudRateDiv_250úPSPI_BaudRateDivDef^    gœSPI_ClockPolSPI_ClockPolarityLowSPI_ClockPolarityHighPSPI_ClockPolDefÙ


uþSPI_ClockPhaseSPI_ClockPhaseFirstEdgeSPI_ClockPhaseSecondEdgePSPI_ClockPhaseDef3éSPI_FrameFormatSPI_FormatMotorolaSPI_FormatTiSPI_FormatMicrowirePSPI_FrameFormatDef—Š¼SPI_WireNumSPI_WireNumThreeSPI_WireNumFourPSPI_WireNumDef”ŠSPI_CmdDatSPI_CommandSelectSPI_DataSelectPSPI_CmdDatDefSÙSPI_WriteReadSelSPI_3WireReadSPI_3WireWritePSPI_WriteReadSelDef §*îSPI_role #SPI_dataFrameSizeB    #SPI_CPOL#SPI_CPHA~#SPI_baudRateDivI#SPI_formaté#PSPI_InitTypeDefõ½<³ÆSPI_EnableSpi$³ SPIx\tmpregY"<çÕSPI_DisableSpi$³ SPIx\tmpregY›œ __PAN_UART_H__ th ..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_uart.hØ


..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_uart.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x_Bool;Æ”UART_IsFifoEnabled$óUARTxa__result<òŸUART_ResetRxFifo$óUARTx\valrtY<œ²UART_ResetTxFifo$óUARTx<ËÂUART_SetTxTrigger$óUARTx$ñlevel<úÓUART_SetRxTrigger$óUARTx$‘level;¶âUART_GetTxFifoLevel:$óUARTxa__result:;òíUART_GetRxFifoLevel:$óUARTxa__result:<”øUART_EnableAfc$óUARTx<·ƒUART_DisableAfc$óUARTx;íŽUART_IsAfcEnabled$óUARTxa__result<™šUART_SendData$óUARTx$:Data;Ò¥UART_ReceiveData:$óUARTxa__result:<ö°UART_EnablePtime$óUARTx<›»UART_DisablePtime$óUARTx;ÓÆUART_IsPtimeEnabled$óUARTxa__result<ýÒUART_EnableIrq$óUARTx$irq<¨ÞUART_DisableIrq$óUARTx$irq;æêUART_IsIrqEnabled$óUARTx$irqa__result;     õUART_GetIrqMasked:$óUARTxa__result:;Ø    €UART_GetActiveEvent¤$óUARTxa__result¤;


‹UART_IsTxFifoEmpty$óUARTxa__result;Å


–UART_IsTxFifoFull$óUARTxa__result;ü


¡UART_IsRxFifoEmpty$óUARTxa__result;²¬UART_IsRxFifoFull$óUARTxa__result<×·UART_EnableHaltTX$óUARTx<ýÂUART_DisableHaltTX$óUARTx<ŸÍUART_EnableRts$óUARTx<ÂØUART_DisableRts$óUARTx<éãUART_Enable9BitData$óUARTx<‘ îUART_Disable9BitData$óUARTx<½ ùUART_EnableAddrMatchMode$óUARTx<ê „UART_DisableAddrMatchMode$óUARTx<‹UART_SendAddr$óUARTx<ÀœUART_SetReceiveAddress$óUARTx$Yaddr<ö¨UART_SetTransmitAddress$óUARTx$YaddrñUART_TxTriggerUART_TX_FIFO_EMPTYUART_TX_FIFO_TWO_CHARSUART_TX_FIFO_QUARTER_FULLUART_TX_FIFO_HALF_FULLPUART_TxTriggerDefv$‘UART_RxTriggerUART_RX_FIFO_ONE_CHARUART_RX_FIFO_QUARTER_FULLUART_RX_FIFO_HALF_FULLUART_RX_FIFO_TWO_LESS_THAN_FULLPUART_RxTriggerDef


0ïUART_LineCtrlUart_Line_5n1Uart_Line_5n1_5Uart_Line_5e1Uart_Line_5e1_5Uart_Line_5o1Uart_Line_5o1_5Uart_Line_5s18Uart_Line_5s1_5<Uart_Line_5m1(Uart_Line_5m1_5,Uart_Line_6n1Uart_Line_6n2Uart_Line_6e1Uart_Line_6e2Uart_Line_6o1    Uart_Line_6o2 Uart_Line_6s19Uart_Line_6s2=Uart_Line_6m1)Uart_Line_6m2-Uart_Line_7n1Uart_Line_7n2Uart_Line_7e1Uart_Line_7e2Uart_Line_7o1


Uart_Line_7o2Uart_Line_7s1:Uart_Line_7s2>Uart_Line_7m1*Uart_Line_7m2.Uart_Line_8n1Uart_Line_8n2Uart_Line_8e1Uart_Line_8e2Uart_Line_8o1Uart_Line_8o2Uart_Line_8s1;Uart_Line_8s2?Uart_Line_8m1+Uart_Line_8m2/PUART_LineCtrlDefªb†UART_IrqUART_IRQ_RECV_DATA_AVLUART_IRQ_THR_EMPTYUART_IRQ_LINE_STATUSUART_IRQ_MODEM_STATUSUART_IRQ_ALLPUART_IrqDef‡s¤UART_EventUART_EVENT_MODEMUART_EVENT_NONEUART_EVENT_THR_EMPTYUART_EVENT_DATAUART_EVENT_LINEUART_EVENT_TIMEOUTPUART_EventDef“ŸUART_LineStatusUART_LINE_DATA_RDYUART_LINE_OVERRUN_ERRUART_LINE_PARITY_ERRUART_LINE_FRAME_ERRUART_LINE_BREAK_INTUART_LINE_THRE UART_LINE_TXSR_EMPTY@UART_LINE_RX_FIFO_ERR€UART_LINE_ADDR_RCVDPUART_LineStatusDefº§ãUART_ModemStatusUART_MODEM_DCTSUART_MODEM_DDSRUART_MODEM_TERIUART_MODEM_DDCDUART_MODEM_CTSUART_MODEM_DSR UART_MODEM_RI@UART_MODEM_DCD€PUART_ModemStatusDefº ·*°UART_BaudRateY#UART_LineCtrlo#PUART_InitTypeDefÅ<óÐUART_EnableStickParity$óUARTx"k <¤ÛUART_DisableStickParity$óUARTx;Ûæ$UART_GetLineStatusŸ $óUARTxa__resultŸ ;“ë%UART_GetModemStatusc$óUARTxa__resultc<¶÷UART_EnableFifo$óUARTx<Ú†UART_DisableFifo$óUARTxŸ ¡__PAN_I2C_H__ =I2C_DYNAMIC_TAR_UPDATE 0DI2C_MODE_MASTER ((uint16_t)0x0021)EI2C_MODE_SLAVE ((uint16_t)0x0000)LIS_I2C_MODE(MODE) (((MODE) == I2C_MODE_MASTER) || ((MODE) == I2C_MODE_SLAVE))TI2C_SPEED_STANDARD_MODE (uint16_t)(0x0002)UI2C_SPEED_FAST_MODE (uint16_t)(0x0004)VI2C_SPEED_HIGH_MODE (uint16_t)(0x0006)^I2C_DutyCycle_16_9 ((uint16_t)0x4000)_I2C_DutyCycle_2 ((uint16_t)0xBFFF)`I2C_DutyCycle_1_1 ((uint16_t)0x0800)aI2C_DutyCycle_1_2 ((uint16_t)0x0400)fIS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || ((CYCLE) == I2C_DutyCycle_2))mI2C_Direction_Transmitter ((uint16_t)0x0000)nI2C_Direction_Receiver ((uint16_t)0x0100)oIS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || ((DIRECTION) == I2C_Direction_Receiver))vI2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)wI2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)xIS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || ((ADDRESS) == I2C_AcknowledgedAddress_10bit))I2C_CMD_WR ((uint8_t)0x00)€I2C_CMD_RD ((uint8_t)0x01)I2C_CMD_STOP ((uint8_t)0x02)‚I2C_CMD_RESTART ((uint8_t)0x04)ˆI2C_RX_TL_0 ((uint8_t)0x00)‰I2C_RX_TL_1 ((uint8_t)0x01)ŠI2C_RX_TL_2 ((uint8_t)0x02)‹I2C_RX_TL_3 ((uint8_t)0x03)ŒI2C_RX_TL_4 ((uint8_t)0x04)I2C_RX_TL_5 ((uint8_t)0x05)ŽI2C_RX_TL_6 ((uint8_t)0x06)I2C_RX_TL_7 ((uint8_t)0x07)I2C_RX_TL_8 ((uint8_t)0x08)–I2C_TX_TL_0 ((uint8_t)0x00)—I2C_TX_TL_1 ((uint8_t)0x01)˜I2C_TX_TL_2 ((uint8_t)0x02)™I2C_TX_TL_3 ((uint8_t)0x03)šI2C_TX_TL_4 ((uint8_t)0x04)›I2C_TX_TL_5 ((uint8_t)0x05)œI2C_TX_TL_6 ((uint8_t)0x06)I2C_TX_TL_7 ((uint8_t)0x07)žI2C_TX_TL_8 ((uint8_t)0x08)¥I2C_IT_RX_UNDER ((uint16_t)0x0001)¦I2C_IT_RX_OVER ((uint16_t)0x0002)§I2C_IT_RX_FULL ((uint16_t)0x0004)¨I2C_IT_TX_OVER ((uint16_t)0x0008)©I2C_IT_TX_EMPTY ((uint16_t)0x0010)ªI2C_IT_RD_REQ ((uint16_t)0x0020)«I2C_IT_TX_ABORT ((uint16_t)0x0040)¬I2C_IT_RX_DONE ((uint16_t)0x0080)­I2C_IT_ACTIVITY ((uint16_t)0x0100)®I2C_IT_STOP_DET ((uint16_t)0x0200)¯I2C_IT_START_DET ((uint16_t)0x0400)°I2C_IT_GEN_CALL ((uint16_t)0x0800)±I2C_IT_MST_ON_HOLD ((uint16_t)0x2000)²I2C_IT_ALL ((uint16_t)0x2FFF)´IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x0FFF) == 0x00) && ((IT) != (uint16_t)0x00))¶IS_I2C_GET_IT(IT) (((IT) == I2C_IT_RX_UNDER) || ((IT) == I2C_IT_RX_OVER) || ((IT) == I2C_IT_RX_FULL) || ((IT) == I2C_IT_TX_OVER) || ((IT) == I2C_IT_TX_EMPTY) || ((IT) == I2C_IT_RD_REQ) || ((IT) == I2C_IT_TX_ABORT) || ((IT) == I2C_IT_RX_DONE) || ((IT) == I2C_IT_ACTIVITY) || ((IT) == I2C_IT_STOP_DET) || ((IT) == I2C_IT_START_DET)|| ((IT) == I2C_IT_GEN_CALL))ÁI2C_FLAG_SLV_ACTIVITY ((uint32_t)0x00000040)ÂI2C_FLAG_MST_ACTIVITY ((uint32_t)0x00000020)ÃI2C_FLAG_RFF ((uint32_t)0x00000010)ÄI2C_FLAG_RFNE ((uint32_t)0x00000008)ÅI2C_FLAG_TFE ((uint32_t)0x00000004)ÆI2C_FLAG_TFNF ((uint32_t)0x00000002)ÇI2C_FLAG_ACTIVITY ((uint32_t)0x00000001)ÈIS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x007F) == 0x00) && ((FLAG) != (uint16_t)0x00))ÉIS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_ACTIVITY) || ((FLAG) == I2C_FLAG_TFNF) || ((FLAG) == I2C_FLAG_TFE) || ((FLAG) == I2C_FLAG_RFNE) || ((FLAG) == I2C_FLAG_RFF) || ((FLAG) == I2C_FLAG_MST_ACTIVITY) || ((FLAG) == I2C_FLAG_SLV_ACTIVITY))ÓFLAG_MASK ((uint32_t)0x007F0FFF)ÔITEN_MASK ((uint16_t)0x2FFF)ÕIT_FLAG_MASK ((uint16_t)0x2FFF)pg ..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_i2c.h€


..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_i2c.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x_Bool;ÐÇI2C_AbortSrcCheck$>I2Cx$YIC_MSKa__result<þÓI2C_SetSlaveAddr$>I2Cx$Yaddr*þI2C_ClockSpeedY#I2C_ModeI#I2C_DutyCycleI#I2C_OwnAddress1I#I2C_AcknowledgedAddressI#


PI2C_InitTypeDef~8<¾áI2C_SetMode$>I2Cx$IMode"Z<òI2C_SetTxTirggerLevel$>I2Cx$:ThresholdValue<¾„I2C_SetRxTirggerLevel$>I2Cx$:ThresholdValue<çI2C_Cmd$>I2Cx$åNewState<›šI2C_GeneralCallCmd$>I2Cx$åNewState<Ò¦I2C_SendDataCmd$>I2Cx$:Data$:Cmd<ú°I2C_SendCmd$>I2Cx$:Cmd;±¹I2C_ReceiveData:$>I2Cxa__result:<ÕÂI2C_AbortTransfer$>I2Cx<ÍI2C_DMACmd$>I2Cx$åNewState<¸×I2C_DMATransferDataLevel$>I2Cx$:Level<îáI2C_DMAReceiveDataLevel$>I2Cx$:Level;²    ùI2C_GetITStatus»$>I2Cx$II2C_ITa__result»;ù    ‘I2C_GetRawITStatus»$>I2Cx$II2C_ITa__result»<´


ªI2C_ITConfig$>I2Cx$II2C_IT$åNewState<×


´I2C_DisableAllIT$>I2Cx<‚½I2C_ClearAllITPendingBit$>I2Cx£¤¥__PAN_TIMER_H__ aFIXED_DEVIATION (12)ti ..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_timer.h


..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_timer.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x_Bool;ÃÄTIMER_IsActive$û    timera__result<âÏTIMER_Start$û    timer<€ÙTIMER_Stop$û    timer<ŸãTIMER_Reset$û    timer<ÅîTIMER_EnableWakeup$û    timer<ìøTIMER_DisableWakeup$û    timer<›ƒTIMER_EnableCaptureDebounce$û    timer<ˍTIMER_DisableCaptureDebounce$û    timer<ÿ˜TIMER_EnableEventCounterDebounce$û    timer<´¢TIMER_DisableEventCounterDebounce$û    timer<׬TIMER_EnableInt$û    timer<û¶TIMER_DisableInt$û    timer<¥ÀTIMER_EnableCaptureInt$û    timer<ÐÊTIMER_DisableCaptureInt$û    timer;‰ÖTIMER_GetIntFlagY$û    timera__resultY<¯àTIMER_ClearIntFlag$û    timer;çìTIMER_GetTFFlagY$û    timera__resultY<ûTIMER_ClearTFFlag$û    timer$Ytimer_flag;Ù‡TIMER_GetWakeupFlagY$û    timera__resultY<’    –TIMER_ClearWakeupFlag$û    timer$Ywake_flag;Ò    ¢TIMER_GetCaptureIntFlagY$û    timera__resultY<ÿ    ¬TIMER_ClearCaptureIntFlag$û    timer;¼


¸TIMER_GetCaptureFlagY$û    timera__resultY<æ


ÂTIMER_ClearCaptureFlag$û    timer<›ÐTIMER_SetCaptureSource$û    timer$$    capSrc;ØÚTIMER_GetCaptureDataY$û    timera__resultY;‘äTIMER_GetCounterY$û    timera__resultY<ÍïTIMER_SetTmrCounterMode$û    timer$Yu32CntModeÈ _TIMER_CntModeDefTIMER_ONESHOT_MODETIMER_PERIODIC_MODETIMER_TOGGLE_MODETIMER_CONTINUOUS_MODEPTIMER_CntModeDefM%ç_TIMER_CapModeDefTIMER_CAPTURE_FREE_COUNTING_MODETIMER_CAPTURE_TRIGGER_COUNTING_MODETIMER_CAPTURE_COUNTER_RESET_MODEPTIMER_CapModeDefà0À_TIMER_CapEdgeDefTIMER_CAPTURE_FALLING_EDGETIMER_CAPTURE_RISING_EDGETIMER_CAPTURE_BOTH_EDGETIMER_CAPTURE_FALLING_THEN_RISING_EDGETIMER_CAPTURE_RISING_THEN_FALLING_EDGEPTIMER_CapEdgeDef=­_TIMER_EvtCntEdgeDefTIMER_COUNTER_FALLING_EDGETIMER_COUNTER_RISING_EDGEPTIMER_EvtCntEdgeDefXG¤_TIMER_CapSrcDefTIMER_CAPTURE_SOURCE_EXT_PINTIMER_CAPTURE_SOURCE_32K_OUTPUTPTIMER_CapSrcDefÈS¥_TIMER0_CmpSelDefTMR0_COMPARATOR_SEL_CMPTMR0_COMPARATOR_SEL_CMP1TMR0_COMPARATOR_SEL_CMP2PTIMER0_CmpSelDef;    ^<ûtTIMER_EnableCapture$û    timer$gcapMode$@capEdge"€<©‚TIMER_DisableCapture$û    timer<äTIMER_EnableEventCounter$û    timer$­evtCntEdge<‘›TIMER_DisableEventCounter$û    timer<ʨTIMER_SetPrescaleValue$û    timer$Yu32Value<ÿ·TIMER_SetCountingMode$û    timer$ÈcntMode§¨© __PAN_PWM_H__ PWM_CHANNEL_NUM (8) PWM_CH0 0x0!PWM_CH1 0x1"PWM_CH2 0x2#PWM_CH3 0x3$PWM_CH4 0x4%PWM_CH5 0x5&PWM_CH6 0x6'PWM_CH7 0x7pg ..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_pwm.hx 


..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_pwm.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xÕ_PWM_ClkSrcSelDefPWM_CLK_SRC_APBPWM_CLK_SRC_RCLPWM_CLK_SRC_XTLPPWM_ClkSrcSelDef6é_PWM_ClkDivDefPWM_CLK_DIV_1PWM_CLK_DIV_2PWM_CLK_DIV_4PWM_CLK_DIV_8PWM_CLK_DIV_16PWM_CLK_DIRECTPPWM_ClkDivDefmCÁ_PWM_AlignedTypeDefPWM_EDGE_ALIGNEDPWM_CENTER_ALIGNEDPPWM_AlignedTypeDefþM®_PWM_IntPeriodTypeDefPWM_PERIOD_INT_UNDERFLOWPWM_PERIOD_INT_MATCH_CNRPPWM_IntPeriodTypeDef[W½_PWM_OperateTypeDefOPERATION_EDGE_ALIGNEDOPERATION_CENTER_ALIGNEDOPERATION_PRECISE_CENTER_ALIGNEDPPWM_OperateTypeDefÊbŸ_PWM_CntModeDefPWM_CNTMODE_ONE_SHOTPWM_CNTMODE_AUTO_RELOADPPWM_CntModeDefWl<ëvPWM_EnableOutput$ëpwm$Yu32ChannelMask"ó    <©‚PWM_DisableOutput$ëpwm$Yu32ChannelMask<ߍPWM_StartChannel$ëpwm$Yu32ChannelNum<”    ˜PWM_StopChannel$ëpwm$Yu32ChannelNum<Þ    ¥PWM_EnableDeadZone$ëpwm$Yu32ChannelNum$Yu32Duration<—


µPWM_DisableDeadZone$ëpwm$Yu32ChannelNum<Î


ÃPWM_EnableCMPDInt$ëpwm$Yu32ChannelNum<†ÎPWM_DisableCMPDInt$ëpwm$Yu32ChannelNum<ÀÙPWM_ClearCMPDIntFlag$ëpwm$Yu32ChannelNum;æPWM_GetCMPDIntFlagY$ëpwm$Yu32ChannelNuma__resultY<ÆñPWM_EnablePeriodInt$ëpwm$Yu32ChannelNum<€ üPWM_DisablePeriodInt$ëpwm$Yu32ChannelNum<¼ ‡PWM_ClearPeriodIntFlag$ëpwm$Yu32ChannelNum;‹”PWM_GetPeriodIntFlagY$ëpwm$Yu32ChannelNuma__resultY<¡PWM_EnableZeroInt$ëpwm$Yu32ChannelNum<ú¬PWM_DisableZeroInt$ëpwm$Yu32ChannelNum<´·PWM_ClearZeroIntFlag$ëpwm$Yu32ChannelNum;ÄPWM_GetZeroIntFlagY$ëpwm$Yu32ChannelNuma__resultY<¸ÏPWM_EnableCMPUInt$ëpwm$Yu32ChannelNum<ðÚPWM_DisableCMPUInt$ëpwm$Yu32ChannelNum<ªåPWM_ClearCMPUIntFlag$ëpwm$Yu32ChannelNum;÷òPWM_GetCMPUIntFlagY$ëpwm$Yu32ChannelNuma__resultY<PWM_EnableCenterInt$ëpwm$Yu32ChannelNum$®IntPeriodType<üŽPWM_DisableCenterInt$ëpwm$Yu32ChannelNum<¸™PWM_ClearCenterIntFlag$ëpwm$Yu32ChannelNum;‡¦PWM_GetCenterIntFlagY$ëpwm$Yu32ChannelNuma__resultY<²°PWM_EnableIndependentMode$ëpwm<ß¹PWM_EnableComplementaryMode$ëpwm<ÃPWM_DisableComplementaryMode$ëpwm<²ÍPWM_EnableGroupMode$ëpwm<Ø×PWM_DisableGroupMode$ëpwm<üáPWM_EnableSyncMode$ëpwm<¡ëPWM_DisableSyncMode$ëpwm<êùPWM_SetPrescaler$ëpwm$Yu32ChannelNum$Yu32Prescaler<¢†PWM_ResetPrescaler$ëpwm$Yu32ChannelNum<â˜PWM_SetDivider$ëpwm$Yu32ChannelNum$éDivider<Ÿ¥PWM_SetCMR$ëpwm$Yu32ChannelNum$Yu32CMR<ܲPWM_SetCNR$ëpwm$Yu32ChannelNum$Yu32CNR<›¿PWM_SetCMRD$ëpwm$Yu32ChannelNum$Yu32CMRD<äÍPWM_SetAlignedType$ëpwm$Yu32ChannelMask$AAlignedType<Ž×PWM_EnableAsymmetricMode$ëpwm<¹áPWM_DisableAsymmetricMode$ëpwm<ØëPWM_EnablePCA$ëpwm<øõPWM_DisablePCA$ëpwm«¬­ __PAN_WDT_H__ pg ..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_wdt.h„


..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_wdt.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x_Bool;¸hWDT_GetResetFlaga__result;ätWDT_GetTimeoutFlaga__result;”€WDT_GetTimeoutIntFlaga__result;ÇŒWDT_GetTimeoutWakeupFlaga__result<á—WDT_ResetCounterß_WDT_TimeoutWDT_TIMEOUT_2POW4WDT_TIMEOUT_2POW6WDT_TIMEOUT_2POW8WDT_TIMEOUT_2POW10WDT_TIMEOUT_2POW12WDT_TIMEOUT_2POW14WDT_TIMEOUT_2POW15WDT_TIMEOUT_2POW16WDT_TIMEOUT_2POW17WDT_TIMEOUT_2POW18    WDT_TIMEOUT_2POW19


WDT_TIMEOUT_2POW20WDT_TIMEOUT_2POW21WDT_TIMEOUT_2POW22 WDT_TIMEOUT_2POW23WDT_TIMEOUT_2POW24PWDT_TimeoutDefá.ð_WDT_ResetDelayWDT_RESET_DELAY_2CLKWDT_RESET_DELAY_17CLKWDT_RESET_DELAY_129CLKWDT_RESET_DELAY_1025CLKPWDT_ResetDelayDefu:<¤AWDT_ClearResetFlag<ÁJWDT_ClearTimeoutFlag<áSWDT_ClearTimeoutIntFlag<„    \WDT_ClearTimeoutWakeupFlag¯°± __PAN_WWDT_H__ 3WWDT_RELOAD_WORD (0x00005AA5)th ..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_wwdt.hð


..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_wwdt.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x_Bool;º^WWDT_GetResetFlaga__result;ãjWWDT_GetIntFlaga__result;ŽvWWDT_GetWWDTFFlaga__result;¼WWDT_GetCounterYa__resultY;ïŒWWDT_GetCompareValueYa__resultY<‹šWWDT_ReloadCounter†_WWDT_PrescaleWWDT_PRESCALER_1WWDT_PRESCALER_2WWDT_PRESCALER_4WWDT_PRESCALER_8WWDT_PRESCALER_16WWDT_PRESCALER_32WWDT_PRESCALER_64WWDT_PRESCALER_128WWDT_PRESCALER_192WWDT_PRESCALER_256    WWDT_PRESCALER_384


WWDT_PRESCALER_512WWDT_PRESCALER_768WWDT_PRESCALER_1024 WWDT_PRESCALER_1536WWDT_PRESCALER_2048PWWDT_PrescaleDef0<º<WWDT_ClearResetFlag<ÔGWWDT_ClearIntFlag<ðRWWDT_ClearWWDTFFlag³´µ__PAN_LP_H__ LP_EXT_P56_WK_EN (1)LP_EXT_P56_WK_DISABLE (0)LP_EXT_P56_WK_EDGE_LOW (0) LP_EXT_P56_WK_EDGE_HIGH (1)#LP_SLPTMR_CH0 (0)$LP_SLPTMR_CH1 (1)%LP_SLPTMR_CH2 (2)'LP_MODE_SEL_SLEEP_MODE (0)(LP_MODE_SEL_DEEPSLEEP_MODE (1))LP_MODE_SEL_STANDBY_M1_MODE (2)*LP_MODE_SEL_STANDBY_M0_MODE (3),LP_DEEPSLEEP_MODE1 (1)-LP_DEEPSLEEP_MODE2 (2).LP_DEEPSLEEP_MODE3 (3)0LP_STANDBY_M1_MODE_SEL LP_STANDBY_M1_MODE11LP_STANDBY_M1_MODE1 (1)2LP_STANDBY_M1_MODE2 (2)3LP_STANDBY_M1_MODE3 (3)5LP_STBM1_WAKEUP_SRC_GPIO BIT06LP_STBM1_WAKEUP_SRC_SLPTMR BIT18LP_RETENTION_SRAM_NONE (0)9LP_RETENTION_SRAM_BLOCK0 BIT0:LP_RETENTION_SRAM_BLOCK1 BIT1;LP_RETENTION_SRAM_DECRYPT BIT2<LP_RETENTION_SRAM_PHY_REGS BIT3=LP_RETENTION_SRAM_LL BIT4>LP_RETENTION_SRAM_ALL (BIT0 | BIT1 | BIT2 | BIT3 | BIT4)pf ..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_lp.hÈ


..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_lp.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x<°GLP_EnableInt$0ana$åNewState"e<åRLP_ClearWakeFlag$0ana$Yu32Mask<˜]LP_HpldoRdyBypassEn$0ana$åNewState<ÉhLP_FastClkDelayEn$0ana$åNewState·¸¹ __PAN_EFUSE_H__ EFUSE_CMD_READ (0X0)EFUSE_CMD_PROGRAM (0X1)EFUSE_CMD_INACTIVE (0X2)%EFUSE_STATUS_OK (0x0)&EFUSE_STATUS_FAIL (0x1)ti ..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_efuse.h¬


..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_efuse.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x<¤1EFUSE_Init$$efuse"<É?EFUSE_UnInit$$efuse;…LEFUSE_GetErrorStatusY$$efusea__resultY<¬WEFUSE_ClrErrorStatus$$efuse»¼½ __PANSERIES_H__ J__CM0_REV 0x0000K__MPU_PRESENT 0L__NVIC_PRIO_BITS 2M__Vendor_SysTickConfig 0N__FPU_PRESENT 0PQUZIS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))¹TIMER_CTL_PSC_Pos (0)ºTIMER_CTL_PSC_Msk (0xfful << TIMER_CTL_PSC_Pos)¼TIMER_CTL_CAPSRC_Pos (19)½TIMER_CTL_CAPSRC_Msk (0x1ul << TIMER_CTL_CAPSRC_Pos)¿TIMER_CTL_WKEN_Pos (23)ÀTIMER_CTL_WKEN_Msk (0x1ul << TIMER_CTL_WKEN_Pos)ÂTIMER_CTL_EXTCNTEN_Pos (24)ÃTIMER_CTL_EXTCNTEN_Msk (0x1ul << TIMER_CTL_EXTCNTEN_Pos)ÅTIMER_CTL_ACTSTS_Pos (25)ÆTIMER_CTL_ACTSTS_Msk (0x1ul << TIMER_CTL_ACTSTS_Pos)ÈTIMER_CTL_RSTCNT_Pos (26)ÉTIMER_CTL_RSTCNT_Msk (0x1ul << TIMER_CTL_RSTCNT_Pos)ËTIMER_CTL_OPMODE_Pos (27)ÌTIMER_CTL_OPMODE_Msk (0x3ul << TIMER_CTL_OPMODE_Pos)ÎTIMER_CTL_INTEN_Pos (29)ÏTIMER_CTL_INTEN_Msk (0x1ul << TIMER_CTL_INTEN_Pos)ÑTIMER_CTL_CNTEN_Pos (30)ÒTIMER_CTL_CNTEN_Msk (0x1ul << TIMER_CTL_CNTEN_Pos)ÔTIMER_CTL_ICEDEBUG_Pos (31)ÕTIMER_CTL_ICEDEBUG_Msk (0x1ul << TIMER_CTL_ICEDEBUG_Pos)×TIMER_CMP_CMPDAT_Pos (0)ØTIMER_CMP_CMPDAT_Msk (0xFFfffffful << TIMER_CMP_CMPDAT_Pos)ÚTIMER_INTSTS_TIF_Pos (0)ÛTIMER_INTSTS_TIF_Msk (0x1ul << TIMER_INTSTS_TIF_Pos)ÝTIMER_INTSTS_TWKF0_Pos (1)ÞTIMER_INTSTS_TWKF0_Msk (0x1ul << TIMER_INTSTS_TWKF0_Pos)àTIMER_INTSTS_TWKF1_Pos (2)áTIMER_INTSTS_TWKF1_Msk (0x1ul << TIMER_INTSTS_TWKF1_Pos)ãTIMER_INTSTS_TWKF2_Pos (3)äTIMER_INTSTS_TWKF2_Msk (0x1ul << TIMER_INTSTS_TWKF2_Pos)æTIMER_INTSTS_TF0_Pos (4)çTIMER_INTSTS_TF0_Msk (0x1ul << TIMER_INTSTS_TF0_Pos)éTIMER_INTSTS_TF1_Pos (5)êTIMER_INTSTS_TF1_Msk (0x1ul << TIMER_INTSTS_TF1_Pos)ìTIMER_INTSTS_TF2_Pos (6)íTIMER_INTSTS_TF2_Msk (0x1ul << TIMER_INTSTS_TF2_Pos)ïTIMER_CNT_CNT_Pos (0)ðTIMER_CNT_CNT_Msk (0xFFfffffful << TIMER_CNT_CNT_Pos)òTIMER_CAP_CAPDAT_Pos (0)óTIMER_CAP_CAPDAT_Msk (0xFFfffffful << TIMER_CAP_CAPDAT_Pos)õTIMER_EXTCTL_CNTPHASE_Pos (0)öTIMER_EXTCTL_CNTPHASE_Msk (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos)øTIMER_EXTCTL_CAPEDGE_Pos (1)ùTIMER_EXTCTL_CAPEDGE_Msk (0x3ul << TIMER_EXTCTL_CAPEDGE_Pos)ûTIMER_EXTCTL_CAPEN_Pos (3)üTIMER_EXTCTL_CAPEN_Msk (0x1ul << TIMER_EXTCTL_CAPEN_Pos)þTIMER_EXTCTL_CAPFUNCS_Pos (4)ÿTIMER_EXTCTL_CAPFUNCS_Msk (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos)TIMER_EXTCTL_CAPIEN_Pos (5)‚TIMER_EXTCTL_CAPIEN_Msk (0x1ul << TIMER_EXTCTL_CAPIEN_Pos)„TIMER_EXTCTL_CAPDBEN_Pos (6)…TIMER_EXTCTL_CAPDBEN_Msk (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos)‡TIMER_EXTCTL_CNTDBEN_Pos (7)ˆTIMER_EXTCTL_CNTDBEN_Msk (0x1ul << TIMER_EXTCTL_CNTDBEN_Pos)ŠTIMER_EXTCTL_CAPSEL_Pos (8)‹TIMER_EXTCTL_CAPSEL_Msk (0x1ul << TIMER_EXTCTL_CAPSEL_Pos)TIMER_EXTCTL_ACMPSSEL_Pos (9)ŽTIMER_EXTCTL_ACMPSSEL_Msk (0x1ul << TIMER_EXTCTL_ACMPSSEL_Pos)TIMER_EINTSTS_CAPIF_Pos (0)‘TIMER_EINTSTS_CAPIF_Msk (0x1ul << TIMER_EINTSTS_CAPIF_Pos)“TIMER_EINTSTS_CAPF_Pos (1)”TIMER_EINTSTS_CAPF_Msk (0x1ul << TIMER_EINTSTS_CAPF_Pos)§TRIM_MEASURE_TUNING_EN_Pos (0)¨TRIM_MEASURE_TUNING_EN_Msk (0x1ul << TRIM_MEASURE_TUNING_EN_Pos)©TRIM_COARSE_TUNING_EN_Pos (1)ªTRIM_COARSE_TUNING_EN_Msk (0x1ul << TRIM_COARSE_TUNING_EN_Pos)«TRIM_FINE_TUNING_EN_Pos (2)¬TRIM_FINE_TUNING_EN_Msk (0x1ul << TRIM_FINE_TUNING_EN_Pos)¯TRIM_COARSE_CODE_Pos (0)°TRIM_COARSE_CODE_Msk (0xful << TRIM_COARSE_CODE_Pos)±TRIM_FINE_CODE_Pos (8)²TRIM_FINE_CODE_Msk (0xfful << TRIM_FINE_CODE_Pos)³TRIM_BIT_WIDTH_Pos (16)´TRIM_BIT_WIDTH_Msk (0x7ul << TRIM_BIT_WIDTH_Pos)·TRIM_CLRL_RELATION_Pos (0)¸TRIM_CLRL_RELATION_Msk (0x1ul << TRIM_CLRL_RELATION_Pos)¹TRIM_CLRL_EARLY_TERM_EN_Pos (1)ºTRIM_CLRL_EARLY_TERM_EN_Msk (0x1ul << TRIM_CLRL_EARLY_TERM_EN_Pos)»TRIM_CLRL_FAIL_CLAC_FLAG_Pos (2)¼TRIM_CLRL_FAIL_CLAC_FLAG_Msk (0x1ul << TRIM_CLRL_FAIL_CLAC_FLAG_Pos)½TRIM_CLRL_CODE_STEP_Pos (8)¾TRIM_CLRL_CODE_STEP_Msk (0xfful << TRIM_CLRL_CODE_STEP_Pos)¿TRIM_CLRL_ERR_RANGE_Pos (16)ÀTRIM_CLRL_ERR_RANGE_Msk (0xfffful << TRIM_CLRL_ERR_RANGE_Pos)ÃTRIM_INT_EN_Pos (0)ÄTRIM_INT_EN_Msk (0x1ul << TRIM_INT_EN_Pos)ÅTRIM_INT_MEASURE_STOP_Pos (1)ÆTRIM_INT_MEASURE_STOP_Msk (0x1ul << TRIM_INT_MEASURE_STOP_Pos)ÇTRIM_FLAG_MEASURE_STOP_Pos (2)ÈTRIM_FLAG_MEASURE_STOP_Msk (0x1ul << TRIM_FLAG_MEASURE_STOP_Pos)ÉTRIM_INT_CTUNE_STOP_Pos (3)ÊTRIM_INT_CTUNE_STOP_Msk (0x1ul << TRIM_INT_CTUNE_STOP_Pos)ËTRIM_FLAG_CTUNE_STOP_Pos (4)ÌTRIM_FLAG_CTUNE_STOP_Msk (0x1ul << TRIM_FLAG_CTUNE_STOP_Pos)ÍTRIM_INT_FTUNE_STOP_Pos (5)ÎTRIM_INT_FTUNE_STOP_Msk (0x1ul << TRIM_INT_FTUNE_STOP_Pos)ÏTRIM_FLAG_FTUNE_STOP_Pos (6)ÐTRIM_FLAG_FTUNE_STOP_Msk (0x1ul << TRIM_FLAG_FTUNE_STOP_Pos)ÑTRIM_INT_OVERFLOW_Pos (9)ÒTRIM_INT_OVERFLOW_Msk (0x1ul << TRIM_INT_OVERFLOW_Pos)ÓTRIM_FLAG_OVERFLOW_Pos (10)ÔTRIM_FLAG_OVERFLOW_Msk (0x1ul << TRIM_FLAG_OVERFLOW_Pos)ÚTRIM_CALC_CNT_Pos (0)ÛTRIM_CALC_CNT_Msk (0xFFFFFFul << TRIM_INT_EN_Pos)ÜTRIM_CALC_WATI_CNT_Pos (24)ÝTRIM_CALC_WATI_CNT_Msk (0xFFul << TRIM_CALC_WATI_CNT_Pos)·GP_MODE_MODE0_Pos (0)¸GP_MODE_MODE0_Msk (0x3ul << GP_MODE_MODE0_Pos)ºGP_MODE_MODE1_Pos (2)»GP_MODE_MODE1_Msk (0x3ul << GP_MODE_MODE1_Pos)½GP_MODE_MODE2_Pos (4)¾GP_MODE_MODE2_Msk (0x3ul << GP_MODE_MODE2_Pos)ÀGP_MODE_MODE3_Pos (6)ÁGP_MODE_MODE3_Msk (0x3ul << GP_MODE_MODE3_Pos)ÃGP_MODE_MODE4_Pos (8)ÄGP_MODE_MODE4_Msk (0x3ul << GP_MODE_MODE4_Pos)ÆGP_MODE_MODE5_Pos (10)ÇGP_MODE_MODE5_Msk (0x3ul << GP_MODE_MODE5_Pos)ÉGP_DINOFF_DINOFF0_Pos (16)ÊGP_DINOFF_DINOFF0_Msk (0x1ul << GP_DINOFF_DINOFF0_Pos)ÌGP_DINOFF_DINOFF1_Pos (17)ÍGP_DINOFF_DINOFF1_Msk (0x1ul << GP_DINOFF_DINOFF1_Pos)ÏGP_DINOFF_DINOFF2_Pos (18)ÐGP_DINOFF_DINOFF2_Msk (0x1ul << GP_DINOFF_DINOFF2_Pos)ÒGP_DINOFF_DINOFF3_Pos (19)ÓGP_DINOFF_DINOFF3_Msk (0x1ul << GP_DINOFF_DINOFF3_Pos)ÕGP_DINOFF_DINOFF4_Pos (20)ÖGP_DINOFF_DINOFF4_Msk (0x1ul << GP_DINOFF_DINOFF4_Pos)ØGP_DINOFF_DINOFF5_Pos (21)ÙGP_DINOFF_DINOFF5_Msk (0x1ul << GP_DINOFF_DINOFF5_Pos)ÛGP_DINOFF_DINOFF6_Pos (22)ÜGP_DINOFF_DINOFF6_Msk (0x1ul << GP_DINOFF_DINOFF6_Pos)ÞGP_DINOFF_DINOFF7_Pos (23)ßGP_DINOFF_DINOFF7_Msk (0x1ul << GP_DINOFF_DINOFF7_Pos)áGP_DOUT_DOUT0_Pos (0)âGP_DOUT_DOUT0_Msk (0x1ul << GP_DOUT_DOUT0_Pos)äGP_DOUT_DOUT1_Pos (1)åGP_DOUT_DOUT1_Msk (0x1ul << GP_DOUT_DOUT1_Pos)çGP_DOUT_DOUT2_Pos (2)èGP_DOUT_DOUT2_Msk (0x1ul << GP_DOUT_DOUT2_Pos)êGP_DOUT_DOUT3_Pos (3)ëGP_DOUT_DOUT3_Msk (0x1ul << GP_DOUT_DOUT3_Pos)íGP_DOUT_DOUT4_Pos (4)îGP_DOUT_DOUT4_Msk (0x1ul << GP_DOUT_DOUT4_Pos)ðGP_DOUT_DOUT5_Pos (5)ñGP_DOUT_DOUT5_Msk (0x1ul << GP_DOUT_DOUT5_Pos)óGP_DOUT_DOUT6_Pos (6)ôGP_DOUT_DOUT6_Msk (0x1ul << GP_DOUT_DOUT6_Pos)öGP_DOUT_DOUT7_Pos (7)÷GP_DOUT_DOUT7_Msk (0x1ul << GP_DOUT_DOUT7_Pos)ùGP_DATMSK_DATMSK0_Pos (0)úGP_DATMSK_DATMSK0_Msk (0x1ul << GP_DATMSK_DATMSK0_Pos)üGP_DATMSK_DATMSK1_Pos (1)ýGP_DATMSK_DATMSK1_Msk (0x1ul << GP_DATMSK_DATMSK1_Pos)ÿGP_DATMSK_DATMSK2_Pos (2)€GP_DATMSK_DATMSK2_Msk (0x1ul << GP_DATMSK_DATMSK2_Pos)‚GP_DATMSK_DATMSK3_Pos (3)ƒGP_DATMSK_DATMSK3_Msk (0x1ul << GP_DATMSK_DATMSK3_Pos)…GP_DATMSK_DATMSK4_Pos (4)†GP_DATMSK_DATMSK4_Msk (0x1ul << GP_DATMSK_DATMSK4_Pos)ˆGP_DATMSK_DATMSK5_Pos (5)‰GP_DATMSK_DATMSK5_Msk (0x1ul << GP_DATMSK_DATMSK5_Pos)‹GP_DATMSK_DATMSK6_Pos (6)ŒGP_DATMSK_DATMSK6_Msk (0x1ul << GP_DATMSK_DATMSK6_Pos)ŽGP_DATMSK_DATMSK7_Pos (7)GP_DATMSK_DATMSK7_Msk (0x1ul << GP_DATMSK_DATMSK7_Pos)‘GP_PIN_PIN0_Pos (0)’GP_PIN_PIN0_Msk (0x1ul << GP_PIN_PIN0_Pos)”GP_PIN_PIN1_Pos (1)•GP_PIN_PIN1_Msk (0x1ul << GP_PIN_PIN1_Pos)—GP_PIN_PIN2_Pos (2)˜GP_PIN_PIN2_Msk (0x1ul << GP_PIN_PIN2_Pos)šGP_PIN_PIN3_Pos (3)›GP_PIN_PIN3_Msk (0x1ul << GP_PIN_PIN3_Pos)GP_PIN_PIN4_Pos (4)žGP_PIN_PIN4_Msk (0x1ul << GP_PIN_PIN4_Pos) GP_PIN_PIN5_Pos (5)¡GP_PIN_PIN5_Msk (0x1ul << GP_PIN_PIN5_Pos)£GP_PIN_PIN6_Pos (6)¤GP_PIN_PIN6_Msk (0x1ul << GP_PIN_PIN6_Pos)¦GP_PIN_PIN7_Pos (7)§GP_PIN_PIN7_Msk (0x1ul << GP_PIN_PIN7_Pos)©GP_DBEN_DBEN0_Pos (0)ªGP_DBEN_DBEN0_Msk (0x1ul << GP_DBEN_DBEN0_Pos)¬GP_DBEN_DBEN1_Pos (1)­GP_DBEN_DBEN1_Msk (0x1ul << GP_DBEN_DBEN1_Pos)¯GP_DBEN_DBEN2_Pos (2)°GP_DBEN_DBEN2_Msk (0x1ul << GP_DBEN_DBEN2_Pos)²GP_DBEN_DBEN3_Pos (3)³GP_DBEN_DBEN3_Msk (0x1ul << GP_DBEN_DBEN3_Pos)µGP_DBEN_DBEN4_Pos (4)¶GP_DBEN_DBEN4_Msk (0x1ul << GP_DBEN_DBEN4_Pos)¸GP_DBEN_DBEN5_Pos (5)¹GP_DBEN_DBEN5_Msk (0x1ul << GP_DBEN_DBEN5_Pos)»GP_DBEN_DBEN6_Pos (6)¼GP_DBEN_DBEN6_Msk (0x1ul << GP_DBEN_DBEN6_Pos)¾GP_DBEN_DBEN7_Pos (7)¿GP_DBEN_DBEN7_Msk (0x1ul << GP_DBEN_DBEN7_Pos)ÁGP_INTTYPE_TYPE0_Pos (0)ÂGP_INTTYPE_TYPE0_Msk (0x1ul << GP_INTTYPE_TYPE0_Pos)ÄGP_INTTYPE_TYPE1_Pos (1)ÅGP_INTTYPE_TYPE1_Msk (0x1ul << GP_INTTYPE_TYPE1_Pos)ÇGP_INTTYPE_TYPE2_Pos (2)ÈGP_INTTYPE_TYPE2_Msk (0x1ul << GP_INTTYPE_TYPE2_Pos)ÊGP_INTTYPE_TYPE3_Pos (3)ËGP_INTTYPE_TYPE3_Msk (0x1ul << GP_INTTYPE_TYPE3_Pos)ÍGP_INTTYPE_TYPE4_Pos (4)ÎGP_INTTYPE_TYPE4_Msk (0x1ul << GP_INTTYPE_TYPE4_Pos)ÐGP_INTTYPE_TYPE5_Pos (5)ÑGP_INTTYPE_TYPE5_Msk (0x1ul << GP_INTTYPE_TYPE5_Pos)ÓGP_INTTYPE_TYPE6_Pos (6)ÔGP_INTTYPE_TYPE6_Msk (0x1ul << GP_INTTYPE_TYPE6_Pos)ÖGP_INTTYPE_TYPE7_Pos (7)×GP_INTTYPE_TYPE7_Msk (0x1ul << GP_INTTYPE_TYPE7_Pos)ÙGP_INTEN_FLIEN0_Pos (0)ÚGP_INTEN_FLIEN0_Msk (0x1ul << GP_INTEN_FLIEN0_Pos)ÜGP_INTEN_FLIEN1_Pos (1)ÝGP_INTEN_FLIEN1_Msk (0x1ul << GP_INTEN_FLIEN1_Pos)ßGP_INTEN_FLIEN2_Pos (2)àGP_INTEN_FLIEN2_Msk (0x1ul << GP_INTEN_FLIEN2_Pos)âGP_INTEN_FLIEN3_Pos (3)ãGP_INTEN_FLIEN3_Msk (0x1ul << GP_INTEN_FLIEN3_Pos)åGP_INTEN_FLIEN4_Pos (4)æGP_INTEN_FLIEN4_Msk (0x1ul << GP_INTEN_FLIEN4_Pos)èGP_INTEN_FLIEN5_Pos (5)éGP_INTEN_FLIEN5_Msk (0x1ul << GP_INTEN_FLIEN5_Pos)ëGP_INTEN_FLIEN6_Pos (6)ìGP_INTEN_FLIEN6_Msk (0x1ul << GP_INTEN_FLIEN6_Pos)îGP_INTEN_FLIEN7_Pos (7)ïGP_INTEN_FLIEN7_Msk (0x1ul << GP_INTEN_FLIEN7_Pos)ñGP_INTEN_RHIEN0_Pos (16)òGP_INTEN_RHIEN0_Msk (0x1ul << GP_INTEN_RHIEN0_Pos)ôGP_INTEN_RHIEN1_Pos (17)õGP_INTEN_RHIEN1_Msk (0x1ul << GP_INTEN_RHIEN1_Pos)÷GP_INTEN_RHIEN2_Pos (18)øGP_INTEN_RHIEN2_Msk (0x1ul << GP_INTEN_RHIEN2_Pos)úGP_INTEN_RHIEN3_Pos (19)ûGP_INTEN_RHIEN3_Msk (0x1ul << GP_INTEN_RHIEN3_Pos)ýGP_INTEN_RHIEN4_Pos (20)þGP_INTEN_RHIEN4_Msk (0x1ul << GP_INTEN_RHIEN4_Pos)€GP_INTEN_RHIEN5_Pos (21)GP_INTEN_RHIEN5_Msk (0x1ul << GP_INTEN_RHIEN5_Pos)ƒGP_INTEN_RHIEN6_Pos (22)„GP_INTEN_RHIEN6_Msk (0x1ul << GP_INTEN_RHIEN6_Pos)†GP_INTEN_RHIEN7_Pos (23)‡GP_INTEN_RHIEN7_Msk (0x1ul << GP_INTEN_RHIEN7_Pos)‰GP_INTSRC_INTSRC0_Pos (0)ŠGP_INTSRC_INTSRC0_Msk (0x1ul << GP_INTSRC_INTSRC0_Pos)ŒGP_INTSRC_INTSRC1_Pos (1)GP_INTSRC_INTSRC1_Msk (0x1ul << GP_INTSRC_INTSRC1_Pos)GP_INTSRC_INTSRC2_Pos (2)GP_INTSRC_INTSRC2_Msk (0x1ul << GP_INTSRC_INTSRC2_Pos)’GP_INTSRC_INTSRC3_Pos (3)“GP_INTSRC_INTSRC3_Msk (0x1ul << GP_INTSRC_INTSRC3_Pos)•GP_INTSRC_INTSRC4_Pos (4)–GP_INTSRC_INTSRC4_Msk (0x1ul << GP_INTSRC_INTSRC4_Pos)˜GP_INTSRC_INTSRC5_Pos (5)™GP_INTSRC_INTSRC5_Msk (0x1ul << GP_INTSRC_INTSRC5_Pos)›GP_INTSRC_INTSRC6_Pos (6)œGP_INTSRC_INTSRC6_Msk (0x1ul << GP_INTSRC_INTSRC6_Pos)žGP_INTSRC_INTSRC7_Pos (7)ŸGP_INTSRC_INTSRC7_Msk (0x1ul << GP_INTSRC_INTSRC7_Pos)¡GP_INTSRC_INTSRC8_Pos (8)¢GP_INTSRC_INTSRC8_Msk (0x1ul << GP_INTSRC_INTSRC8_Pos)¤GP_INTSRC_INTSRC9_Pos (9)¥GP_INTSRC_INTSRC9_Msk (0x1ul << GP_INTSRC_INTSRC9_Pos)§GP_INTSRC_INTSRC10_Pos (10)¨GP_INTSRC_INTSRC10_Msk (0x1ul << GP_INTSRC_INTSRC10_Pos)ªGP_INTSRC_INTSRC11_Pos (11)«GP_INTSRC_INTSRC11_Msk (0x1ul << GP_INTSRC_INTSRC11_Pos)­GP_INTSRC_INTSRC12_Pos (12)®GP_INTSRC_INTSRC12_Msk (0x1ul << GP_INTSRC_INTSRC12_Pos)°GP_INTSRC_INTSRC13_Pos (13)±GP_INTSRC_INTSRC13_Msk (0x1ul << GP_INTSRC_INTSRC13_Pos)³GP_INTSRC_INTSRC14_Pos (14)´GP_INTSRC_INTSRC14_Msk (0x1ul << GP_INTSRC_INTSRC14_Pos)¶GP_INTSRC_INTSRC15_Pos (15)·GP_INTSRC_INTSRC15_Msk (0x1ul << GP_INTSRC_INTSRC15_Pos)¹GP_MODE_MODE0_Pos (0)ºGP_MODE_MODE0_Msk (0x3ul << GP_MODE_MODE0_Pos)¼GP_MODE_MODE1_Pos (2)½GP_MODE_MODE1_Msk (0x3ul << GP_MODE_MODE1_Pos)¿GP_MODE_MODE2_Pos (4)ÀGP_MODE_MODE2_Msk (0x3ul << GP_MODE_MODE2_Pos)ÂGP_MODE_MODE3_Pos (6)ÃGP_MODE_MODE3_Msk (0x3ul << GP_MODE_MODE3_Pos)ÅGP_MODE_MODE4_Pos (8)ÆGP_MODE_MODE4_Msk (0x3ul << GP_MODE_MODE4_Pos)ÈGP_MODE_MODE5_Pos (10)ÉGP_MODE_MODE5_Msk (0x3ul << GP_MODE_MODE5_Pos)ËGP_DINOFF_DINOFF0_Pos (16)ÌGP_DINOFF_DINOFF0_Msk (0x1ul << GP_DINOFF_DINOFF0_Pos)ÎGP_DINOFF_DINOFF1_Pos (17)ÏGP_DINOFF_DINOFF1_Msk (0x1ul << GP_DINOFF_DINOFF1_Pos)ÑGP_DINOFF_DINOFF2_Pos (18)ÒGP_DINOFF_DINOFF2_Msk (0x1ul << GP_DINOFF_DINOFF2_Pos)ÔGP_DINOFF_DINOFF3_Pos (19)ÕGP_DINOFF_DINOFF3_Msk (0x1ul << GP_DINOFF_DINOFF3_Pos)×GP_DINOFF_DINOFF4_Pos (20)ØGP_DINOFF_DINOFF4_Msk (0x1ul << GP_DINOFF_DINOFF4_Pos)ÚGP_DINOFF_DINOFF5_Pos (21)ÛGP_DINOFF_DINOFF5_Msk (0x1ul << GP_DINOFF_DINOFF5_Pos)ÝGP_DINOFF_DINOFF6_Pos (22)ÞGP_DINOFF_DINOFF6_Msk (0x1ul << GP_DINOFF_DINOFF6_Pos)àGP_DINOFF_DINOFF7_Pos (23)áGP_DINOFF_DINOFF7_Msk (0x1ul << GP_DINOFF_DINOFF7_Pos)ãGP_DOUT_DOUT0_Pos (0)äGP_DOUT_DOUT0_Msk (0x1ul << GP_DOUT_DOUT0_Pos)æGP_DOUT_DOUT1_Pos (1)çGP_DOUT_DOUT1_Msk (0x1ul << GP_DOUT_DOUT1_Pos)éGP_DOUT_DOUT2_Pos (2)êGP_DOUT_DOUT2_Msk (0x1ul << GP_DOUT_DOUT2_Pos)ìGP_DOUT_DOUT3_Pos (3)íGP_DOUT_DOUT3_Msk (0x1ul << GP_DOUT_DOUT3_Pos)ïGP_DOUT_DOUT4_Pos (4)ðGP_DOUT_DOUT4_Msk (0x1ul << GP_DOUT_DOUT4_Pos)òGP_DOUT_DOUT5_Pos (5)óGP_DOUT_DOUT5_Msk (0x1ul << GP_DOUT_DOUT5_Pos)õGP_DOUT_DOUT6_Pos (6)öGP_DOUT_DOUT6_Msk (0x1ul << GP_DOUT_DOUT6_Pos)øGP_DOUT_DOUT7_Pos (7)ùGP_DOUT_DOUT7_Msk (0x1ul << GP_DOUT_DOUT7_Pos)ûGP_DATMSK_DATMSK0_Pos (0)üGP_DATMSK_DATMSK0_Msk (0x1ul << GP_DATMSK_DATMSK0_Pos)þGP_DATMSK_DATMSK1_Pos (1)ÿGP_DATMSK_DATMSK1_Msk (0x1ul << GP_DATMSK_DATMSK1_Pos)GP_DATMSK_DATMSK2_Pos (2)‚GP_DATMSK_DATMSK2_Msk (0x1ul << GP_DATMSK_DATMSK2_Pos)„GP_DATMSK_DATMSK3_Pos (3)…GP_DATMSK_DATMSK3_Msk (0x1ul << GP_DATMSK_DATMSK3_Pos)‡GP_DATMSK_DATMSK4_Pos (4)ˆGP_DATMSK_DATMSK4_Msk (0x1ul << GP_DATMSK_DATMSK4_Pos)ŠGP_DATMSK_DATMSK5_Pos (5)‹GP_DATMSK_DATMSK5_Msk (0x1ul << GP_DATMSK_DATMSK5_Pos)GP_DATMSK_DATMSK6_Pos (6)ŽGP_DATMSK_DATMSK6_Msk (0x1ul << GP_DATMSK_DATMSK6_Pos)GP_DATMSK_DATMSK7_Pos (7)‘GP_DATMSK_DATMSK7_Msk (0x1ul << GP_DATMSK_DATMSK7_Pos)“GP_PIN_PIN0_Pos (0)”GP_PIN_PIN0_Msk (0x1ul << GP_PIN_PIN0_Pos)–GP_PIN_PIN1_Pos (1)—GP_PIN_PIN1_Msk (0x1ul << GP_PIN_PIN1_Pos)™GP_PIN_PIN2_Pos (2)šGP_PIN_PIN2_Msk (0x1ul << GP_PIN_PIN2_Pos)œGP_PIN_PIN3_Pos (3)GP_PIN_PIN3_Msk (0x1ul << GP_PIN_PIN3_Pos)ŸGP_PIN_PIN4_Pos (4) GP_PIN_PIN4_Msk (0x1ul << GP_PIN_PIN4_Pos)¢GP_PIN_PIN5_Pos (5)£GP_PIN_PIN5_Msk (0x1ul << GP_PIN_PIN5_Pos)¥GP_PIN_PIN6_Pos (6)¦GP_PIN_PIN6_Msk (0x1ul << GP_PIN_PIN6_Pos)¨GP_PIN_PIN7_Pos (7)©GP_PIN_PIN7_Msk (0x1ul << GP_PIN_PIN7_Pos)«GP_DBEN_DBEN0_Pos (0)¬GP_DBEN_DBEN0_Msk (0x1ul << GP_DBEN_DBEN0_Pos)®GP_DBEN_DBEN1_Pos (1)¯GP_DBEN_DBEN1_Msk (0x1ul << GP_DBEN_DBEN1_Pos)±GP_DBEN_DBEN2_Pos (2)²GP_DBEN_DBEN2_Msk (0x1ul << GP_DBEN_DBEN2_Pos)´GP_DBEN_DBEN3_Pos (3)µGP_DBEN_DBEN3_Msk (0x1ul << GP_DBEN_DBEN3_Pos)·GP_DBEN_DBEN4_Pos (4)¸GP_DBEN_DBEN4_Msk (0x1ul << GP_DBEN_DBEN4_Pos)ºGP_DBEN_DBEN5_Pos (5)»GP_DBEN_DBEN5_Msk (0x1ul << GP_DBEN_DBEN5_Pos)½GP_DBEN_DBEN6_Pos (6)¾GP_DBEN_DBEN6_Msk (0x1ul << GP_DBEN_DBEN6_Pos)ÀGP_DBEN_DBEN7_Pos (7)ÁGP_DBEN_DBEN7_Msk (0x1ul << GP_DBEN_DBEN7_Pos)ÃGP_INTTYPE_TYPE0_Pos (0)ÄGP_INTTYPE_TYPE0_Msk (0x1ul << GP_INTTYPE_TYPE0_Pos)ÆGP_INTTYPE_TYPE1_Pos (1)ÇGP_INTTYPE_TYPE1_Msk (0x1ul << GP_INTTYPE_TYPE1_Pos)ÉGP_INTTYPE_TYPE2_Pos (2)ÊGP_INTTYPE_TYPE2_Msk (0x1ul << GP_INTTYPE_TYPE2_Pos)ÌGP_INTTYPE_TYPE3_Pos (3)ÍGP_INTTYPE_TYPE3_Msk (0x1ul << GP_INTTYPE_TYPE3_Pos)ÏGP_INTTYPE_TYPE4_Pos (4)ÐGP_INTTYPE_TYPE4_Msk (0x1ul << GP_INTTYPE_TYPE4_Pos)ÒGP_INTTYPE_TYPE5_Pos (5)ÓGP_INTTYPE_TYPE5_Msk (0x1ul << GP_INTTYPE_TYPE5_Pos)ÕGP_INTTYPE_TYPE6_Pos (6)ÖGP_INTTYPE_TYPE6_Msk (0x1ul << GP_INTTYPE_TYPE6_Pos)ØGP_INTTYPE_TYPE7_Pos (7)ÙGP_INTTYPE_TYPE7_Msk (0x1ul << GP_INTTYPE_TYPE7_Pos)ÛGP_INTEN_FLIEN0_Pos (0)ÜGP_INTEN_FLIEN0_Msk (0x1ul << GP_INTEN_FLIEN0_Pos)ÞGP_INTEN_FLIEN1_Pos (1)ßGP_INTEN_FLIEN1_Msk (0x1ul << GP_INTEN_FLIEN1_Pos)áGP_INTEN_FLIEN2_Pos (2)âGP_INTEN_FLIEN2_Msk (0x1ul << GP_INTEN_FLIEN2_Pos)äGP_INTEN_FLIEN3_Pos (3)åGP_INTEN_FLIEN3_Msk (0x1ul << GP_INTEN_FLIEN3_Pos)çGP_INTEN_FLIEN4_Pos (4)èGP_INTEN_FLIEN4_Msk (0x1ul << GP_INTEN_FLIEN4_Pos)êGP_INTEN_FLIEN5_Pos (5)ëGP_INTEN_FLIEN5_Msk (0x1ul << GP_INTEN_FLIEN5_Pos)íGP_INTEN_FLIEN6_Pos (6)îGP_INTEN_FLIEN6_Msk (0x1ul << GP_INTEN_FLIEN6_Pos)ðGP_INTEN_FLIEN7_Pos (7)ñGP_INTEN_FLIEN7_Msk (0x1ul << GP_INTEN_FLIEN7_Pos)óGP_INTEN_RHIEN0_Pos (16)ôGP_INTEN_RHIEN0_Msk (0x1ul << GP_INTEN_RHIEN0_Pos)öGP_INTEN_RHIEN1_Pos (17)÷GP_INTEN_RHIEN1_Msk (0x1ul << GP_INTEN_RHIEN1_Pos)ùGP_INTEN_RHIEN2_Pos (18)úGP_INTEN_RHIEN2_Msk (0x1ul << GP_INTEN_RHIEN2_Pos)üGP_INTEN_RHIEN3_Pos (19)ýGP_INTEN_RHIEN3_Msk (0x1ul << GP_INTEN_RHIEN3_Pos)ÿGP_INTEN_RHIEN4_Pos (20)€GP_INTEN_RHIEN4_Msk (0x1ul << GP_INTEN_RHIEN4_Pos)‚GP_INTEN_RHIEN5_Pos (21)ƒGP_INTEN_RHIEN5_Msk (0x1ul << GP_INTEN_RHIEN5_Pos)…GP_INTEN_RHIEN6_Pos (22)†GP_INTEN_RHIEN6_Msk (0x1ul << GP_INTEN_RHIEN6_Pos)ˆGP_INTEN_RHIEN7_Pos (23)‰GP_INTEN_RHIEN7_Msk (0x1ul << GP_INTEN_RHIEN7_Pos)‹GP_INTSRC_INTSRC0_Pos (0)ŒGP_INTSRC_INTSRC0_Msk (0x1ul << GP_INTSRC_INTSRC0_Pos)ŽGP_INTSRC_INTSRC1_Pos (1)GP_INTSRC_INTSRC1_Msk (0x1ul << GP_INTSRC_INTSRC1_Pos)‘GP_INTSRC_INTSRC2_Pos (2)’GP_INTSRC_INTSRC2_Msk (0x1ul << GP_INTSRC_INTSRC2_Pos)”GP_INTSRC_INTSRC3_Pos (3)•GP_INTSRC_INTSRC3_Msk (0x1ul << GP_INTSRC_INTSRC3_Pos)—GP_INTSRC_INTSRC4_Pos (4)˜GP_INTSRC_INTSRC4_Msk (0x1ul << GP_INTSRC_INTSRC4_Pos)šGP_INTSRC_INTSRC5_Pos (5)›GP_INTSRC_INTSRC5_Msk (0x1ul << GP_INTSRC_INTSRC5_Pos)GP_INTSRC_INTSRC6_Pos (6)žGP_INTSRC_INTSRC6_Msk (0x1ul << GP_INTSRC_INTSRC6_Pos) GP_INTSRC_INTSRC7_Pos (7)¡GP_INTSRC_INTSRC7_Msk (0x1ul << GP_INTSRC_INTSRC7_Pos)£GP_INTSRC_INTSRC8_Pos (8)¤GP_INTSRC_INTSRC8_Msk (0x1ul << GP_INTSRC_INTSRC8_Pos)¦GP_INTSRC_INTSRC9_Pos (9)§GP_INTSRC_INTSRC9_Msk (0x1ul << GP_INTSRC_INTSRC9_Pos)©GP_INTSRC_INTSRC10_Pos (10)ªGP_INTSRC_INTSRC10_Msk (0x1ul << GP_INTSRC_INTSRC10_Pos)¬GP_INTSRC_INTSRC11_Pos (11)­GP_INTSRC_INTSRC11_Msk (0x1ul << GP_INTSRC_INTSRC11_Pos)¯GP_INTSRC_INTSRC12_Pos (12)°GP_INTSRC_INTSRC12_Msk (0x1ul << GP_INTSRC_INTSRC12_Pos)²GP_INTSRC_INTSRC13_Pos (13)³GP_INTSRC_INTSRC13_Msk (0x1ul << GP_INTSRC_INTSRC13_Pos)µGP_INTSRC_INTSRC14_Pos (14)¶GP_INTSRC_INTSRC14_Msk (0x1ul << GP_INTSRC_INTSRC14_Pos)¸GP_INTSRC_INTSRC15_Pos (15)¹GP_INTSRC_INTSRC15_Msk (0x1ul << GP_INTSRC_INTSRC15_Pos)»GP_MODE_MODE0_Pos (0)¼GP_MODE_MODE0_Msk (0x3ul << GP_MODE_MODE0_Pos)¾GP_MODE_MODE1_Pos (2)¿GP_MODE_MODE1_Msk (0x3ul << GP_MODE_MODE1_Pos)ÁGP_MODE_MODE2_Pos (4)ÂGP_MODE_MODE2_Msk (0x3ul << GP_MODE_MODE2_Pos)ÄGP_MODE_MODE3_Pos (6)ÅGP_MODE_MODE3_Msk (0x3ul << GP_MODE_MODE3_Pos)ÇGP_MODE_MODE4_Pos (8)ÈGP_MODE_MODE4_Msk (0x3ul << GP_MODE_MODE4_Pos)ÊGP_MODE_MODE5_Pos (10)ËGP_MODE_MODE5_Msk (0x3ul << GP_MODE_MODE5_Pos)ÍGP_DINOFF_DINOFF0_Pos (16)ÎGP_DINOFF_DINOFF0_Msk (0x1ul << GP_DINOFF_DINOFF0_Pos)ÐGP_DINOFF_DINOFF1_Pos (17)ÑGP_DINOFF_DINOFF1_Msk (0x1ul << GP_DINOFF_DINOFF1_Pos)ÓGP_DINOFF_DINOFF2_Pos (18)ÔGP_DINOFF_DINOFF2_Msk (0x1ul << GP_DINOFF_DINOFF2_Pos)ÖGP_DINOFF_DINOFF3_Pos (19)×GP_DINOFF_DINOFF3_Msk (0x1ul << GP_DINOFF_DINOFF3_Pos)ÙGP_DINOFF_DINOFF4_Pos (20)ÚGP_DINOFF_DINOFF4_Msk (0x1ul << GP_DINOFF_DINOFF4_Pos)ÜGP_DINOFF_DINOFF5_Pos (21)ÝGP_DINOFF_DINOFF5_Msk (0x1ul << GP_DINOFF_DINOFF5_Pos)ßGP_DINOFF_DINOFF6_Pos (22)àGP_DINOFF_DINOFF6_Msk (0x1ul << GP_DINOFF_DINOFF6_Pos)âGP_DINOFF_DINOFF7_Pos (23)ãGP_DINOFF_DINOFF7_Msk (0x1ul << GP_DINOFF_DINOFF7_Pos)åGP_DOUT_DOUT0_Pos (0)æGP_DOUT_DOUT0_Msk (0x1ul << GP_DOUT_DOUT0_Pos)èGP_DOUT_DOUT1_Pos (1)éGP_DOUT_DOUT1_Msk (0x1ul << GP_DOUT_DOUT1_Pos)ëGP_DOUT_DOUT2_Pos (2)ìGP_DOUT_DOUT2_Msk (0x1ul << GP_DOUT_DOUT2_Pos)îGP_DOUT_DOUT3_Pos (3)ïGP_DOUT_DOUT3_Msk (0x1ul << GP_DOUT_DOUT3_Pos)ñGP_DOUT_DOUT4_Pos (4)òGP_DOUT_DOUT4_Msk (0x1ul << GP_DOUT_DOUT4_Pos)ôGP_DOUT_DOUT5_Pos (5)õGP_DOUT_DOUT5_Msk (0x1ul << GP_DOUT_DOUT5_Pos)÷GP_DOUT_DOUT6_Pos (6)øGP_DOUT_DOUT6_Msk (0x1ul << GP_DOUT_DOUT6_Pos)úGP_DOUT_DOUT7_Pos (7)ûGP_DOUT_DOUT7_Msk (0x1ul << GP_DOUT_DOUT7_Pos)ýGP_DATMSK_DATMSK0_Pos (0)þGP_DATMSK_DATMSK0_Msk (0x1ul << GP_DATMSK_DATMSK0_Pos)€GP_DATMSK_DATMSK1_Pos (1)GP_DATMSK_DATMSK1_Msk (0x1ul << GP_DATMSK_DATMSK1_Pos)ƒGP_DATMSK_DATMSK2_Pos (2)„GP_DATMSK_DATMSK2_Msk (0x1ul << GP_DATMSK_DATMSK2_Pos)†GP_DATMSK_DATMSK3_Pos (3)‡GP_DATMSK_DATMSK3_Msk (0x1ul << GP_DATMSK_DATMSK3_Pos)‰GP_DATMSK_DATMSK4_Pos (4)ŠGP_DATMSK_DATMSK4_Msk (0x1ul << GP_DATMSK_DATMSK4_Pos)ŒGP_DATMSK_DATMSK5_Pos (5)GP_DATMSK_DATMSK5_Msk (0x1ul << GP_DATMSK_DATMSK5_Pos)GP_DATMSK_DATMSK6_Pos (6)GP_DATMSK_DATMSK6_Msk (0x1ul << GP_DATMSK_DATMSK6_Pos)’GP_DATMSK_DATMSK7_Pos (7)“GP_DATMSK_DATMSK7_Msk (0x1ul << GP_DATMSK_DATMSK7_Pos)•GP_PIN_PIN0_Pos (0)–GP_PIN_PIN0_Msk (0x1ul << GP_PIN_PIN0_Pos)˜GP_PIN_PIN1_Pos (1)™GP_PIN_PIN1_Msk (0x1ul << GP_PIN_PIN1_Pos)›GP_PIN_PIN2_Pos (2)œGP_PIN_PIN2_Msk (0x1ul << GP_PIN_PIN2_Pos)žGP_PIN_PIN3_Pos (3)ŸGP_PIN_PIN3_Msk (0x1ul << GP_PIN_PIN3_Pos)¡GP_PIN_PIN4_Pos (4)¢GP_PIN_PIN4_Msk (0x1ul << GP_PIN_PIN4_Pos)¤GP_PIN_PIN5_Pos (5)¥GP_PIN_PIN5_Msk (0x1ul << GP_PIN_PIN5_Pos)§GP_PIN_PIN6_Pos (6)¨GP_PIN_PIN6_Msk (0x1ul << GP_PIN_PIN6_Pos)ªGP_PIN_PIN7_Pos (7)«GP_PIN_PIN7_Msk (0x1ul << GP_PIN_PIN7_Pos)­GP_DBEN_DBEN0_Pos (0)®GP_DBEN_DBEN0_Msk (0x1ul << GP_DBEN_DBEN0_Pos)°GP_DBEN_DBEN1_Pos (1)±GP_DBEN_DBEN1_Msk (0x1ul << GP_DBEN_DBEN1_Pos)³GP_DBEN_DBEN2_Pos (2)´GP_DBEN_DBEN2_Msk (0x1ul << GP_DBEN_DBEN2_Pos)¶GP_DBEN_DBEN3_Pos (3)·GP_DBEN_DBEN3_Msk (0x1ul << GP_DBEN_DBEN3_Pos)¹GP_DBEN_DBEN4_Pos (4)ºGP_DBEN_DBEN4_Msk (0x1ul << GP_DBEN_DBEN4_Pos)¼GP_DBEN_DBEN5_Pos (5)½GP_DBEN_DBEN5_Msk (0x1ul << GP_DBEN_DBEN5_Pos)¿GP_DBEN_DBEN6_Pos (6)ÀGP_DBEN_DBEN6_Msk (0x1ul << GP_DBEN_DBEN6_Pos)ÂGP_DBEN_DBEN7_Pos (7)ÃGP_DBEN_DBEN7_Msk (0x1ul << GP_DBEN_DBEN7_Pos)ÅGP_INTTYPE_TYPE0_Pos (0)ÆGP_INTTYPE_TYPE0_Msk (0x1ul << GP_INTTYPE_TYPE0_Pos)ÈGP_INTTYPE_TYPE1_Pos (1)ÉGP_INTTYPE_TYPE1_Msk (0x1ul << GP_INTTYPE_TYPE1_Pos)ËGP_INTTYPE_TYPE2_Pos (2)ÌGP_INTTYPE_TYPE2_Msk (0x1ul << GP_INTTYPE_TYPE2_Pos)ÎGP_INTTYPE_TYPE3_Pos (3)ÏGP_INTTYPE_TYPE3_Msk (0x1ul << GP_INTTYPE_TYPE3_Pos)ÑGP_INTTYPE_TYPE4_Pos (4)ÒGP_INTTYPE_TYPE4_Msk (0x1ul << GP_INTTYPE_TYPE4_Pos)ÔGP_INTTYPE_TYPE5_Pos (5)ÕGP_INTTYPE_TYPE5_Msk (0x1ul << GP_INTTYPE_TYPE5_Pos)×GP_INTTYPE_TYPE6_Pos (6)ØGP_INTTYPE_TYPE6_Msk (0x1ul << GP_INTTYPE_TYPE6_Pos)ÚGP_INTTYPE_TYPE7_Pos (7)ÛGP_INTTYPE_TYPE7_Msk (0x1ul << GP_INTTYPE_TYPE7_Pos)ÝGP_INTEN_FLIEN0_Pos (0)ÞGP_INTEN_FLIEN0_Msk (0x1ul << GP_INTEN_FLIEN0_Pos)àGP_INTEN_FLIEN1_Pos (1)áGP_INTEN_FLIEN1_Msk (0x1ul << GP_INTEN_FLIEN1_Pos)ãGP_INTEN_FLIEN2_Pos (2)äGP_INTEN_FLIEN2_Msk (0x1ul << GP_INTEN_FLIEN2_Pos)æGP_INTEN_FLIEN3_Pos (3)çGP_INTEN_FLIEN3_Msk (0x1ul << GP_INTEN_FLIEN3_Pos)éGP_INTEN_FLIEN4_Pos (4)êGP_INTEN_FLIEN4_Msk (0x1ul << GP_INTEN_FLIEN4_Pos)ìGP_INTEN_FLIEN5_Pos (5)íGP_INTEN_FLIEN5_Msk (0x1ul << GP_INTEN_FLIEN5_Pos)ïGP_INTEN_FLIEN6_Pos (6)ðGP_INTEN_FLIEN6_Msk (0x1ul << GP_INTEN_FLIEN6_Pos)òGP_INTEN_FLIEN7_Pos (7)óGP_INTEN_FLIEN7_Msk (0x1ul << GP_INTEN_FLIEN7_Pos)õGP_INTEN_RHIEN0_Pos (16)öGP_INTEN_RHIEN0_Msk (0x1ul << GP_INTEN_RHIEN0_Pos)øGP_INTEN_RHIEN1_Pos (17)ùGP_INTEN_RHIEN1_Msk (0x1ul << GP_INTEN_RHIEN1_Pos)ûGP_INTEN_RHIEN2_Pos (18)üGP_INTEN_RHIEN2_Msk (0x1ul << GP_INTEN_RHIEN2_Pos)þGP_INTEN_RHIEN3_Pos (19)ÿGP_INTEN_RHIEN3_Msk (0x1ul << GP_INTEN_RHIEN3_Pos)GP_INTEN_RHIEN4_Pos (20)‚GP_INTEN_RHIEN4_Msk (0x1ul << GP_INTEN_RHIEN4_Pos)„GP_INTEN_RHIEN5_Pos (21)…GP_INTEN_RHIEN5_Msk (0x1ul << GP_INTEN_RHIEN5_Pos)‡GP_INTEN_RHIEN6_Pos (22)ˆGP_INTEN_RHIEN6_Msk (0x1ul << GP_INTEN_RHIEN6_Pos)ŠGP_INTEN_RHIEN7_Pos (23)‹GP_INTEN_RHIEN7_Msk (0x1ul << GP_INTEN_RHIEN7_Pos)GP_INTSRC_INTSRC0_Pos (0)ŽGP_INTSRC_INTSRC0_Msk (0x1ul << GP_INTSRC_INTSRC0_Pos)GP_INTSRC_INTSRC1_Pos (1)‘GP_INTSRC_INTSRC1_Msk (0x1ul << GP_INTSRC_INTSRC1_Pos)“GP_INTSRC_INTSRC2_Pos (2)”GP_INTSRC_INTSRC2_Msk (0x1ul << GP_INTSRC_INTSRC2_Pos)–GP_INTSRC_INTSRC3_Pos (3)—GP_INTSRC_INTSRC3_Msk (0x1ul << GP_INTSRC_INTSRC3_Pos)™GP_INTSRC_INTSRC4_Pos (4)šGP_INTSRC_INTSRC4_Msk (0x1ul << GP_INTSRC_INTSRC4_Pos)œGP_INTSRC_INTSRC5_Pos (5)GP_INTSRC_INTSRC5_Msk (0x1ul << GP_INTSRC_INTSRC5_Pos)ŸGP_INTSRC_INTSRC6_Pos (6) GP_INTSRC_INTSRC6_Msk (0x1ul << GP_INTSRC_INTSRC6_Pos)¢GP_INTSRC_INTSRC7_Pos (7)£GP_INTSRC_INTSRC7_Msk (0x1ul << GP_INTSRC_INTSRC7_Pos)¥GP_INTSRC_INTSRC8_Pos (8)¦GP_INTSRC_INTSRC8_Msk (0x1ul << GP_INTSRC_INTSRC8_Pos)¨GP_INTSRC_INTSRC9_Pos (9)©GP_INTSRC_INTSRC9_Msk (0x1ul << GP_INTSRC_INTSRC9_Pos)«GP_INTSRC_INTSRC10_Pos (10)¬GP_INTSRC_INTSRC10_Msk (0x1ul << GP_INTSRC_INTSRC10_Pos)®GP_INTSRC_INTSRC11_Pos (11)¯GP_INTSRC_INTSRC11_Msk (0x1ul << GP_INTSRC_INTSRC11_Pos)±GP_INTSRC_INTSRC12_Pos (12)²GP_INTSRC_INTSRC12_Msk (0x1ul << GP_INTSRC_INTSRC12_Pos)´GP_INTSRC_INTSRC13_Pos (13)µGP_INTSRC_INTSRC13_Msk (0x1ul << GP_INTSRC_INTSRC13_Pos)·GP_INTSRC_INTSRC14_Pos (14)¸GP_INTSRC_INTSRC14_Msk (0x1ul << GP_INTSRC_INTSRC14_Pos)ºGP_INTSRC_INTSRC15_Pos (15)»GP_INTSRC_INTSRC15_Msk (0x1ul << GP_INTSRC_INTSRC15_Pos)½GP_MODE_MODE0_Pos (0)¾GP_MODE_MODE0_Msk (0x3ul << GP_MODE_MODE0_Pos)ÀGP_MODE_MODE1_Pos (2)ÁGP_MODE_MODE1_Msk (0x3ul << GP_MODE_MODE1_Pos)ÃGP_MODE_MODE2_Pos (4)ÄGP_MODE_MODE2_Msk (0x3ul << GP_MODE_MODE2_Pos)ÆGP_MODE_MODE3_Pos (6)ÇGP_MODE_MODE3_Msk (0x3ul << GP_MODE_MODE3_Pos)ÉGP_MODE_MODE4_Pos (8)ÊGP_MODE_MODE4_Msk (0x3ul << GP_MODE_MODE4_Pos)ÌGP_MODE_MODE5_Pos (10)ÍGP_MODE_MODE5_Msk (0x3ul << GP_MODE_MODE5_Pos)ÏGP_DINOFF_DINOFF0_Pos (16)ÐGP_DINOFF_DINOFF0_Msk (0x1ul << GP_DINOFF_DINOFF0_Pos)ÒGP_DINOFF_DINOFF1_Pos (17)ÓGP_DINOFF_DINOFF1_Msk (0x1ul << GP_DINOFF_DINOFF1_Pos)ÕGP_DINOFF_DINOFF2_Pos (18)ÖGP_DINOFF_DINOFF2_Msk (0x1ul << GP_DINOFF_DINOFF2_Pos)ØGP_DINOFF_DINOFF3_Pos (19)ÙGP_DINOFF_DINOFF3_Msk (0x1ul << GP_DINOFF_DINOFF3_Pos)ÛGP_DINOFF_DINOFF4_Pos (20)ÜGP_DINOFF_DINOFF4_Msk (0x1ul << GP_DINOFF_DINOFF4_Pos)ÞGP_DINOFF_DINOFF5_Pos (21)ßGP_DINOFF_DINOFF5_Msk (0x1ul << GP_DINOFF_DINOFF5_Pos)áGP_DINOFF_DINOFF6_Pos (22)âGP_DINOFF_DINOFF6_Msk (0x1ul << GP_DINOFF_DINOFF6_Pos)äGP_DINOFF_DINOFF7_Pos (23)åGP_DINOFF_DINOFF7_Msk (0x1ul << GP_DINOFF_DINOFF7_Pos)çGP_DOUT_DOUT0_Pos (0)èGP_DOUT_DOUT0_Msk (0x1ul << GP_DOUT_DOUT0_Pos)êGP_DOUT_DOUT1_Pos (1)ëGP_DOUT_DOUT1_Msk (0x1ul << GP_DOUT_DOUT1_Pos)íGP_DOUT_DOUT2_Pos (2)îGP_DOUT_DOUT2_Msk (0x1ul << GP_DOUT_DOUT2_Pos)ðGP_DOUT_DOUT3_Pos (3)ñGP_DOUT_DOUT3_Msk (0x1ul << GP_DOUT_DOUT3_Pos)óGP_DOUT_DOUT4_Pos (4)ôGP_DOUT_DOUT4_Msk (0x1ul << GP_DOUT_DOUT4_Pos)öGP_DOUT_DOUT5_Pos (5)÷GP_DOUT_DOUT5_Msk (0x1ul << GP_DOUT_DOUT5_Pos)ùGP_DOUT_DOUT6_Pos (6)úGP_DOUT_DOUT6_Msk (0x1ul << GP_DOUT_DOUT6_Pos)üGP_DOUT_DOUT7_Pos (7)ýGP_DOUT_DOUT7_Msk (0x1ul << GP_DOUT_DOUT7_Pos)ÿGP_DATMSK_DATMSK0_Pos (0)€GP_DATMSK_DATMSK0_Msk (0x1ul << GP_DATMSK_DATMSK0_Pos)‚GP_DATMSK_DATMSK1_Pos (1)ƒGP_DATMSK_DATMSK1_Msk (0x1ul << GP_DATMSK_DATMSK1_Pos)…GP_DATMSK_DATMSK2_Pos (2)†GP_DATMSK_DATMSK2_Msk (0x1ul << GP_DATMSK_DATMSK2_Pos)ˆGP_DATMSK_DATMSK3_Pos (3)‰GP_DATMSK_DATMSK3_Msk (0x1ul << GP_DATMSK_DATMSK3_Pos)‹GP_DATMSK_DATMSK4_Pos (4)ŒGP_DATMSK_DATMSK4_Msk (0x1ul << GP_DATMSK_DATMSK4_Pos)ŽGP_DATMSK_DATMSK5_Pos (5)GP_DATMSK_DATMSK5_Msk (0x1ul << GP_DATMSK_DATMSK5_Pos)‘GP_DATMSK_DATMSK6_Pos (6)’GP_DATMSK_DATMSK6_Msk (0x1ul << GP_DATMSK_DATMSK6_Pos)”GP_DATMSK_DATMSK7_Pos (7)•GP_DATMSK_DATMSK7_Msk (0x1ul << GP_DATMSK_DATMSK7_Pos)—GP_PIN_PIN0_Pos (0)˜GP_PIN_PIN0_Msk (0x1ul << GP_PIN_PIN0_Pos)šGP_PIN_PIN1_Pos (1)›GP_PIN_PIN1_Msk (0x1ul << GP_PIN_PIN1_Pos)GP_PIN_PIN2_Pos (2)žGP_PIN_PIN2_Msk (0x1ul << GP_PIN_PIN2_Pos) GP_PIN_PIN3_Pos (3)¡GP_PIN_PIN3_Msk (0x1ul << GP_PIN_PIN3_Pos)£GP_PIN_PIN4_Pos (4)¤GP_PIN_PIN4_Msk (0x1ul << GP_PIN_PIN4_Pos)¦GP_PIN_PIN5_Pos (5)§GP_PIN_PIN5_Msk (0x1ul << GP_PIN_PIN5_Pos)©GP_PIN_PIN6_Pos (6)ªGP_PIN_PIN6_Msk (0x1ul << GP_PIN_PIN6_Pos)¬GP_PIN_PIN7_Pos (7)­GP_PIN_PIN7_Msk (0x1ul << GP_PIN_PIN7_Pos)¯GP_DBEN_DBEN0_Pos (0)°GP_DBEN_DBEN0_Msk (0x1ul << GP_DBEN_DBEN0_Pos)²GP_DBEN_DBEN1_Pos (1)³GP_DBEN_DBEN1_Msk (0x1ul << GP_DBEN_DBEN1_Pos)µGP_DBEN_DBEN2_Pos (2)¶GP_DBEN_DBEN2_Msk (0x1ul << GP_DBEN_DBEN2_Pos)¸GP_DBEN_DBEN3_Pos (3)¹GP_DBEN_DBEN3_Msk (0x1ul << GP_DBEN_DBEN3_Pos)»GP_DBEN_DBEN4_Pos (4)¼GP_DBEN_DBEN4_Msk (0x1ul << GP_DBEN_DBEN4_Pos)¾GP_DBEN_DBEN5_Pos (5)¿GP_DBEN_DBEN5_Msk (0x1ul << GP_DBEN_DBEN5_Pos)ÁGP_DBEN_DBEN6_Pos (6)ÂGP_DBEN_DBEN6_Msk (0x1ul << GP_DBEN_DBEN6_Pos)ÄGP_DBEN_DBEN7_Pos (7)ÅGP_DBEN_DBEN7_Msk (0x1ul << GP_DBEN_DBEN7_Pos)ÇGP_INTTYPE_TYPE0_Pos (0)ÈGP_INTTYPE_TYPE0_Msk (0x1ul << GP_INTTYPE_TYPE0_Pos)ÊGP_INTTYPE_TYPE1_Pos (1)ËGP_INTTYPE_TYPE1_Msk (0x1ul << GP_INTTYPE_TYPE1_Pos)ÍGP_INTTYPE_TYPE2_Pos (2)ÎGP_INTTYPE_TYPE2_Msk (0x1ul << GP_INTTYPE_TYPE2_Pos)ÐGP_INTTYPE_TYPE3_Pos (3)ÑGP_INTTYPE_TYPE3_Msk (0x1ul << GP_INTTYPE_TYPE3_Pos)ÓGP_INTTYPE_TYPE4_Pos (4)ÔGP_INTTYPE_TYPE4_Msk (0x1ul << GP_INTTYPE_TYPE4_Pos)ÖGP_INTTYPE_TYPE5_Pos (5)×GP_INTTYPE_TYPE5_Msk (0x1ul << GP_INTTYPE_TYPE5_Pos)ÙGP_INTTYPE_TYPE6_Pos (6)ÚGP_INTTYPE_TYPE6_Msk (0x1ul << GP_INTTYPE_TYPE6_Pos)ÜGP_INTTYPE_TYPE7_Pos (7)ÝGP_INTTYPE_TYPE7_Msk (0x1ul << GP_INTTYPE_TYPE7_Pos)ßGP_INTEN_FLIEN0_Pos (0)àGP_INTEN_FLIEN0_Msk (0x1ul << GP_INTEN_FLIEN0_Pos)âGP_INTEN_FLIEN1_Pos (1)ãGP_INTEN_FLIEN1_Msk (0x1ul << GP_INTEN_FLIEN1_Pos)åGP_INTEN_FLIEN2_Pos (2)æGP_INTEN_FLIEN2_Msk (0x1ul << GP_INTEN_FLIEN2_Pos)èGP_INTEN_FLIEN3_Pos (3)éGP_INTEN_FLIEN3_Msk (0x1ul << GP_INTEN_FLIEN3_Pos)ëGP_INTEN_FLIEN4_Pos (4)ìGP_INTEN_FLIEN4_Msk (0x1ul << GP_INTEN_FLIEN4_Pos)îGP_INTEN_FLIEN5_Pos (5)ïGP_INTEN_FLIEN5_Msk (0x1ul << GP_INTEN_FLIEN5_Pos)ñGP_INTEN_FLIEN6_Pos (6)òGP_INTEN_FLIEN6_Msk (0x1ul << GP_INTEN_FLIEN6_Pos)ôGP_INTEN_FLIEN7_Pos (7)õGP_INTEN_FLIEN7_Msk (0x1ul << GP_INTEN_FLIEN7_Pos)÷GP_INTEN_RHIEN0_Pos (16)øGP_INTEN_RHIEN0_Msk (0x1ul << GP_INTEN_RHIEN0_Pos)úGP_INTEN_RHIEN1_Pos (17)ûGP_INTEN_RHIEN1_Msk (0x1ul << GP_INTEN_RHIEN1_Pos)ýGP_INTEN_RHIEN2_Pos (18)þGP_INTEN_RHIEN2_Msk (0x1ul << GP_INTEN_RHIEN2_Pos)€GP_INTEN_RHIEN3_Pos (19)GP_INTEN_RHIEN3_Msk (0x1ul << GP_INTEN_RHIEN3_Pos)ƒGP_INTEN_RHIEN4_Pos (20)„GP_INTEN_RHIEN4_Msk (0x1ul << GP_INTEN_RHIEN4_Pos)†GP_INTEN_RHIEN5_Pos (21)‡GP_INTEN_RHIEN5_Msk (0x1ul << GP_INTEN_RHIEN5_Pos)‰GP_INTEN_RHIEN6_Pos (22)ŠGP_INTEN_RHIEN6_Msk (0x1ul << GP_INTEN_RHIEN6_Pos)ŒGP_INTEN_RHIEN7_Pos (23)GP_INTEN_RHIEN7_Msk (0x1ul << GP_INTEN_RHIEN7_Pos)GP_INTSRC_INTSRC0_Pos (0)GP_INTSRC_INTSRC0_Msk (0x1ul << GP_INTSRC_INTSRC0_Pos)’GP_INTSRC_INTSRC1_Pos (1)“GP_INTSRC_INTSRC1_Msk (0x1ul << GP_INTSRC_INTSRC1_Pos)•GP_INTSRC_INTSRC2_Pos (2)–GP_INTSRC_INTSRC2_Msk (0x1ul << GP_INTSRC_INTSRC2_Pos)˜GP_INTSRC_INTSRC3_Pos (3)™GP_INTSRC_INTSRC3_Msk (0x1ul << GP_INTSRC_INTSRC3_Pos)›GP_INTSRC_INTSRC4_Pos (4)œGP_INTSRC_INTSRC4_Msk (0x1ul << GP_INTSRC_INTSRC4_Pos)žGP_INTSRC_INTSRC5_Pos (5)ŸGP_INTSRC_INTSRC5_Msk (0x1ul << GP_INTSRC_INTSRC5_Pos)¡GP_INTSRC_INTSRC6_Pos (6)¢GP_INTSRC_INTSRC6_Msk (0x1ul << GP_INTSRC_INTSRC6_Pos)¤GP_INTSRC_INTSRC7_Pos (7)¥GP_INTSRC_INTSRC7_Msk (0x1ul << GP_INTSRC_INTSRC7_Pos)§GP_INTSRC_INTSRC8_Pos (8)¨GP_INTSRC_INTSRC8_Msk (0x1ul << GP_INTSRC_INTSRC8_Pos)ªGP_INTSRC_INTSRC9_Pos (9)«GP_INTSRC_INTSRC9_Msk (0x1ul << GP_INTSRC_INTSRC9_Pos)­GP_INTSRC_INTSRC10_Pos (10)®GP_INTSRC_INTSRC10_Msk (0x1ul << GP_INTSRC_INTSRC10_Pos)°GP_INTSRC_INTSRC11_Pos (11)±GP_INTSRC_INTSRC11_Msk (0x1ul << GP_INTSRC_INTSRC11_Pos)³GP_INTSRC_INTSRC12_Pos (12)´GP_INTSRC_INTSRC12_Msk (0x1ul << GP_INTSRC_INTSRC12_Pos)¶GP_INTSRC_INTSRC13_Pos (13)·GP_INTSRC_INTSRC13_Msk (0x1ul << GP_INTSRC_INTSRC13_Pos)¹GP_INTSRC_INTSRC14_Pos (14)ºGP_INTSRC_INTSRC14_Msk (0x1ul << GP_INTSRC_INTSRC14_Pos)¼GP_INTSRC_INTSRC15_Pos (15)½GP_INTSRC_INTSRC15_Msk (0x1ul << GP_INTSRC_INTSRC15_Pos)¿GP_MODE_MODE0_Pos (0)ÀGP_MODE_MODE0_Msk (0x3ul << GP_MODE_MODE0_Pos)ÂGP_MODE_MODE1_Pos (2)ÃGP_MODE_MODE1_Msk (0x3ul << GP_MODE_MODE1_Pos)ÅGP_MODE_MODE2_Pos (4)ÆGP_MODE_MODE2_Msk (0x3ul << GP_MODE_MODE2_Pos)ÈGP_MODE_MODE3_Pos (6)ÉGP_MODE_MODE3_Msk (0x3ul << GP_MODE_MODE3_Pos)ËGP_MODE_MODE4_Pos (8)ÌGP_MODE_MODE4_Msk (0x3ul << GP_MODE_MODE4_Pos)ÎGP_MODE_MODE5_Pos (10)ÏGP_MODE_MODE5_Msk (0x3ul << GP_MODE_MODE5_Pos)ÑGP_DINOFF_DINOFF0_Pos (16)ÒGP_DINOFF_DINOFF0_Msk (0x1ul << GP_DINOFF_DINOFF0_Pos)ÔGP_DINOFF_DINOFF1_Pos (17)ÕGP_DINOFF_DINOFF1_Msk (0x1ul << GP_DINOFF_DINOFF1_Pos)×GP_DINOFF_DINOFF2_Pos (18)ØGP_DINOFF_DINOFF2_Msk (0x1ul << GP_DINOFF_DINOFF2_Pos)ÚGP_DINOFF_DINOFF3_Pos (19)ÛGP_DINOFF_DINOFF3_Msk (0x1ul << GP_DINOFF_DINOFF3_Pos)ÝGP_DINOFF_DINOFF4_Pos (20)ÞGP_DINOFF_DINOFF4_Msk (0x1ul << GP_DINOFF_DINOFF4_Pos)àGP_DINOFF_DINOFF5_Pos (21)áGP_DINOFF_DINOFF5_Msk (0x1ul << GP_DINOFF_DINOFF5_Pos)ãGP_DINOFF_DINOFF6_Pos (22)äGP_DINOFF_DINOFF6_Msk (0x1ul << GP_DINOFF_DINOFF6_Pos)æGP_DINOFF_DINOFF7_Pos (23)çGP_DINOFF_DINOFF7_Msk (0x1ul << GP_DINOFF_DINOFF7_Pos)éGP_DOUT_DOUT0_Pos (0)êGP_DOUT_DOUT0_Msk (0x1ul << GP_DOUT_DOUT0_Pos)ìGP_DOUT_DOUT1_Pos (1)íGP_DOUT_DOUT1_Msk (0x1ul << GP_DOUT_DOUT1_Pos)ïGP_DOUT_DOUT2_Pos (2)ðGP_DOUT_DOUT2_Msk (0x1ul << GP_DOUT_DOUT2_Pos)òGP_DOUT_DOUT3_Pos (3)óGP_DOUT_DOUT3_Msk (0x1ul << GP_DOUT_DOUT3_Pos)õGP_DOUT_DOUT4_Pos (4)öGP_DOUT_DOUT4_Msk (0x1ul << GP_DOUT_DOUT4_Pos)øGP_DOUT_DOUT5_Pos (5)ùGP_DOUT_DOUT5_Msk (0x1ul << GP_DOUT_DOUT5_Pos)ûGP_DOUT_DOUT6_Pos (6)üGP_DOUT_DOUT6_Msk (0x1ul << GP_DOUT_DOUT6_Pos)þGP_DOUT_DOUT7_Pos (7)ÿGP_DOUT_DOUT7_Msk (0x1ul << GP_DOUT_DOUT7_Pos)GP_DATMSK_DATMSK0_Pos (0)‚GP_DATMSK_DATMSK0_Msk (0x1ul << GP_DATMSK_DATMSK0_Pos)„GP_DATMSK_DATMSK1_Pos (1)…GP_DATMSK_DATMSK1_Msk (0x1ul << GP_DATMSK_DATMSK1_Pos)‡GP_DATMSK_DATMSK2_Pos (2)ˆGP_DATMSK_DATMSK2_Msk (0x1ul << GP_DATMSK_DATMSK2_Pos)ŠGP_DATMSK_DATMSK3_Pos (3)‹GP_DATMSK_DATMSK3_Msk (0x1ul << GP_DATMSK_DATMSK3_Pos)GP_DATMSK_DATMSK4_Pos (4)ŽGP_DATMSK_DATMSK4_Msk (0x1ul << GP_DATMSK_DATMSK4_Pos)GP_DATMSK_DATMSK5_Pos (5)‘GP_DATMSK_DATMSK5_Msk (0x1ul << GP_DATMSK_DATMSK5_Pos)“GP_DATMSK_DATMSK6_Pos (6)”GP_DATMSK_DATMSK6_Msk (0x1ul << GP_DATMSK_DATMSK6_Pos)–GP_DATMSK_DATMSK7_Pos (7)—GP_DATMSK_DATMSK7_Msk (0x1ul << GP_DATMSK_DATMSK7_Pos)™GP_PIN_PIN0_Pos (0)šGP_PIN_PIN0_Msk (0x1ul << GP_PIN_PIN0_Pos)œGP_PIN_PIN1_Pos (1)GP_PIN_PIN1_Msk (0x1ul << GP_PIN_PIN1_Pos)ŸGP_PIN_PIN2_Pos (2) GP_PIN_PIN2_Msk (0x1ul << GP_PIN_PIN2_Pos)¢GP_PIN_PIN3_Pos (3)£GP_PIN_PIN3_Msk (0x1ul << GP_PIN_PIN3_Pos)¥GP_PIN_PIN4_Pos (4)¦GP_PIN_PIN4_Msk (0x1ul << GP_PIN_PIN4_Pos)¨GP_PIN_PIN5_Pos (5)©GP_PIN_PIN5_Msk (0x1ul << GP_PIN_PIN5_Pos)«GP_PIN_PIN6_Pos (6)¬GP_PIN_PIN6_Msk (0x1ul << GP_PIN_PIN6_Pos)®GP_PIN_PIN7_Pos (7)¯GP_PIN_PIN7_Msk (0x1ul << GP_PIN_PIN7_Pos)±GP_DBEN_DBEN0_Pos (0)²GP_DBEN_DBEN0_Msk (0x1ul << GP_DBEN_DBEN0_Pos)´GP_DBEN_DBEN1_Pos (1)µGP_DBEN_DBEN1_Msk (0x1ul << GP_DBEN_DBEN1_Pos)·GP_DBEN_DBEN2_Pos (2)¸GP_DBEN_DBEN2_Msk (0x1ul << GP_DBEN_DBEN2_Pos)ºGP_DBEN_DBEN3_Pos (3)»GP_DBEN_DBEN3_Msk (0x1ul << GP_DBEN_DBEN3_Pos)½GP_DBEN_DBEN4_Pos (4)¾GP_DBEN_DBEN4_Msk (0x1ul << GP_DBEN_DBEN4_Pos)ÀGP_DBEN_DBEN5_Pos (5)ÁGP_DBEN_DBEN5_Msk (0x1ul << GP_DBEN_DBEN5_Pos)ÃGP_DBEN_DBEN6_Pos (6)ÄGP_DBEN_DBEN6_Msk (0x1ul << GP_DBEN_DBEN6_Pos)ÆGP_DBEN_DBEN7_Pos (7)ÇGP_DBEN_DBEN7_Msk (0x1ul << GP_DBEN_DBEN7_Pos)ÉGP_INTTYPE_TYPE0_Pos (0)ÊGP_INTTYPE_TYPE0_Msk (0x1ul << GP_INTTYPE_TYPE0_Pos)ÌGP_INTTYPE_TYPE1_Pos (1)ÍGP_INTTYPE_TYPE1_Msk (0x1ul << GP_INTTYPE_TYPE1_Pos)ÏGP_INTTYPE_TYPE2_Pos (2)ÐGP_INTTYPE_TYPE2_Msk (0x1ul << GP_INTTYPE_TYPE2_Pos)ÒGP_INTTYPE_TYPE3_Pos (3)ÓGP_INTTYPE_TYPE3_Msk (0x1ul << GP_INTTYPE_TYPE3_Pos)ÕGP_INTTYPE_TYPE4_Pos (4)ÖGP_INTTYPE_TYPE4_Msk (0x1ul << GP_INTTYPE_TYPE4_Pos)ØGP_INTTYPE_TYPE5_Pos (5)ÙGP_INTTYPE_TYPE5_Msk (0x1ul << GP_INTTYPE_TYPE5_Pos)ÛGP_INTTYPE_TYPE6_Pos (6)ÜGP_INTTYPE_TYPE6_Msk (0x1ul << GP_INTTYPE_TYPE6_Pos)ÞGP_INTTYPE_TYPE7_Pos (7)ßGP_INTTYPE_TYPE7_Msk (0x1ul << GP_INTTYPE_TYPE7_Pos)áGP_INTEN_FLIEN0_Pos (0)âGP_INTEN_FLIEN0_Msk (0x1ul << GP_INTEN_FLIEN0_Pos)äGP_INTEN_FLIEN1_Pos (1)åGP_INTEN_FLIEN1_Msk (0x1ul << GP_INTEN_FLIEN1_Pos)çGP_INTEN_FLIEN2_Pos (2)èGP_INTEN_FLIEN2_Msk (0x1ul << GP_INTEN_FLIEN2_Pos)êGP_INTEN_FLIEN3_Pos (3)ëGP_INTEN_FLIEN3_Msk (0x1ul << GP_INTEN_FLIEN3_Pos)íGP_INTEN_FLIEN4_Pos (4)îGP_INTEN_FLIEN4_Msk (0x1ul << GP_INTEN_FLIEN4_Pos)ðGP_INTEN_FLIEN5_Pos (5)ñGP_INTEN_FLIEN5_Msk (0x1ul << GP_INTEN_FLIEN5_Pos)óGP_INTEN_FLIEN6_Pos (6)ôGP_INTEN_FLIEN6_Msk (0x1ul << GP_INTEN_FLIEN6_Pos)öGP_INTEN_FLIEN7_Pos (7)÷GP_INTEN_FLIEN7_Msk (0x1ul << GP_INTEN_FLIEN7_Pos)ùGP_INTEN_RHIEN0_Pos (16)úGP_INTEN_RHIEN0_Msk (0x1ul << GP_INTEN_RHIEN0_Pos)üGP_INTEN_RHIEN1_Pos (17)ýGP_INTEN_RHIEN1_Msk (0x1ul << GP_INTEN_RHIEN1_Pos)ÿGP_INTEN_RHIEN2_Pos (18)€GP_INTEN_RHIEN2_Msk (0x1ul << GP_INTEN_RHIEN2_Pos)‚GP_INTEN_RHIEN3_Pos (19)ƒGP_INTEN_RHIEN3_Msk (0x1ul << GP_INTEN_RHIEN3_Pos)…GP_INTEN_RHIEN4_Pos (20)†GP_INTEN_RHIEN4_Msk (0x1ul << GP_INTEN_RHIEN4_Pos)ˆGP_INTEN_RHIEN5_Pos (21)‰GP_INTEN_RHIEN5_Msk (0x1ul << GP_INTEN_RHIEN5_Pos)‹GP_INTEN_RHIEN6_Pos (22)ŒGP_INTEN_RHIEN6_Msk (0x1ul << GP_INTEN_RHIEN6_Pos)ŽGP_INTEN_RHIEN7_Pos (23)GP_INTEN_RHIEN7_Msk (0x1ul << GP_INTEN_RHIEN7_Pos)‘GP_INTSRC_INTSRC0_Pos (0)’GP_INTSRC_INTSRC0_Msk (0x1ul << GP_INTSRC_INTSRC0_Pos)”GP_INTSRC_INTSRC1_Pos (1)•GP_INTSRC_INTSRC1_Msk (0x1ul << GP_INTSRC_INTSRC1_Pos)—GP_INTSRC_INTSRC2_Pos (2)˜GP_INTSRC_INTSRC2_Msk (0x1ul << GP_INTSRC_INTSRC2_Pos)šGP_INTSRC_INTSRC3_Pos (3)›GP_INTSRC_INTSRC3_Msk (0x1ul << GP_INTSRC_INTSRC3_Pos)GP_INTSRC_INTSRC4_Pos (4)žGP_INTSRC_INTSRC4_Msk (0x1ul << GP_INTSRC_INTSRC4_Pos) GP_INTSRC_INTSRC5_Pos (5)¡GP_INTSRC_INTSRC5_Msk (0x1ul << GP_INTSRC_INTSRC5_Pos)£GP_INTSRC_INTSRC6_Pos (6)¤GP_INTSRC_INTSRC6_Msk (0x1ul << GP_INTSRC_INTSRC6_Pos)¦GP_INTSRC_INTSRC7_Pos (7)§GP_INTSRC_INTSRC7_Msk (0x1ul << GP_INTSRC_INTSRC7_Pos)©GP_INTSRC_INTSRC8_Pos (8)ªGP_INTSRC_INTSRC8_Msk (0x1ul << GP_INTSRC_INTSRC8_Pos)¬GP_INTSRC_INTSRC9_Pos (9)­GP_INTSRC_INTSRC9_Msk (0x1ul << GP_INTSRC_INTSRC9_Pos)¯GP_INTSRC_INTSRC10_Pos (10)°GP_INTSRC_INTSRC10_Msk (0x1ul << GP_INTSRC_INTSRC10_Pos)²GP_INTSRC_INTSRC11_Pos (11)³GP_INTSRC_INTSRC11_Msk (0x1ul << GP_INTSRC_INTSRC11_Pos)µGP_INTSRC_INTSRC12_Pos (12)¶GP_INTSRC_INTSRC12_Msk (0x1ul << GP_INTSRC_INTSRC12_Pos)¸GP_INTSRC_INTSRC13_Pos (13)¹GP_INTSRC_INTSRC13_Msk (0x1ul << GP_INTSRC_INTSRC13_Pos)»GP_INTSRC_INTSRC14_Pos (14)¼GP_INTSRC_INTSRC14_Msk (0x1ul << GP_INTSRC_INTSRC14_Pos)¾GP_INTSRC_INTSRC15_Pos (15)¿GP_INTSRC_INTSRC15_Msk (0x1ul << GP_INTSRC_INTSRC15_Pos)ÁGP_MODE_MODE0_Pos (0)ÂGP_MODE_MODE0_Msk (0x3ul << GP_MODE_MODE0_Pos)ÄGP_MODE_MODE1_Pos (2)ÅGP_MODE_MODE1_Msk (0x3ul << GP_MODE_MODE1_Pos)ÇGP_MODE_MODE2_Pos (4)ÈGP_MODE_MODE2_Msk (0x3ul << GP_MODE_MODE2_Pos)ÊGP_MODE_MODE3_Pos (6)ËGP_MODE_MODE3_Msk (0x3ul << GP_MODE_MODE3_Pos)ÍGP_MODE_MODE4_Pos (8)ÎGP_MODE_MODE4_Msk (0x3ul << GP_MODE_MODE4_Pos)ÐGP_MODE_MODE5_Pos (10)ÑGP_MODE_MODE5_Msk (0x3ul << GP_MODE_MODE5_Pos)ÓGP_DINOFF_DINOFF0_Pos (16)ÔGP_DINOFF_DINOFF0_Msk (0x1ul << GP_DINOFF_DINOFF0_Pos)ÖGP_DINOFF_DINOFF1_Pos (17)×GP_DINOFF_DINOFF1_Msk (0x1ul << GP_DINOFF_DINOFF1_Pos)ÙGP_DINOFF_DINOFF2_Pos (18)ÚGP_DINOFF_DINOFF2_Msk (0x1ul << GP_DINOFF_DINOFF2_Pos)ÜGP_DINOFF_DINOFF3_Pos (19)ÝGP_DINOFF_DINOFF3_Msk (0x1ul << GP_DINOFF_DINOFF3_Pos)ßGP_DINOFF_DINOFF4_Pos (20)àGP_DINOFF_DINOFF4_Msk (0x1ul << GP_DINOFF_DINOFF4_Pos)âGP_DINOFF_DINOFF5_Pos (21)ãGP_DINOFF_DINOFF5_Msk (0x1ul << GP_DINOFF_DINOFF5_Pos)åGP_DINOFF_DINOFF6_Pos (22)æGP_DINOFF_DINOFF6_Msk (0x1ul << GP_DINOFF_DINOFF6_Pos)èGP_DINOFF_DINOFF7_Pos (23)éGP_DINOFF_DINOFF7_Msk (0x1ul << GP_DINOFF_DINOFF7_Pos)ëGP_DOUT_DOUT0_Pos (0)ìGP_DOUT_DOUT0_Msk (0x1ul << GP_DOUT_DOUT0_Pos)îGP_DOUT_DOUT1_Pos (1)ïGP_DOUT_DOUT1_Msk (0x1ul << GP_DOUT_DOUT1_Pos)ñGP_DOUT_DOUT2_Pos (2)òGP_DOUT_DOUT2_Msk (0x1ul << GP_DOUT_DOUT2_Pos)ôGP_DOUT_DOUT3_Pos (3)õGP_DOUT_DOUT3_Msk (0x1ul << GP_DOUT_DOUT3_Pos)÷GP_DOUT_DOUT4_Pos (4)øGP_DOUT_DOUT4_Msk (0x1ul << GP_DOUT_DOUT4_Pos)úGP_DOUT_DOUT5_Pos (5)ûGP_DOUT_DOUT5_Msk (0x1ul << GP_DOUT_DOUT5_Pos)ýGP_DOUT_DOUT6_Pos (6)þGP_DOUT_DOUT6_Msk (0x1ul << GP_DOUT_DOUT6_Pos)€GP_DOUT_DOUT7_Pos (7)GP_DOUT_DOUT7_Msk (0x1ul << GP_DOUT_DOUT7_Pos)ƒGP_DATMSK_DATMSK0_Pos (0)„GP_DATMSK_DATMSK0_Msk (0x1ul << GP_DATMSK_DATMSK0_Pos)†GP_DATMSK_DATMSK1_Pos (1)‡GP_DATMSK_DATMSK1_Msk (0x1ul << GP_DATMSK_DATMSK1_Pos)‰GP_DATMSK_DATMSK2_Pos (2)ŠGP_DATMSK_DATMSK2_Msk (0x1ul << GP_DATMSK_DATMSK2_Pos)ŒGP_DATMSK_DATMSK3_Pos (3)GP_DATMSK_DATMSK3_Msk (0x1ul << GP_DATMSK_DATMSK3_Pos)GP_DATMSK_DATMSK4_Pos (4)GP_DATMSK_DATMSK4_Msk (0x1ul << GP_DATMSK_DATMSK4_Pos)’GP_DATMSK_DATMSK5_Pos (5)“GP_DATMSK_DATMSK5_Msk (0x1ul << GP_DATMSK_DATMSK5_Pos)•GP_DATMSK_DATMSK6_Pos (6)–GP_DATMSK_DATMSK6_Msk (0x1ul << GP_DATMSK_DATMSK6_Pos)˜GP_DATMSK_DATMSK7_Pos (7)™GP_DATMSK_DATMSK7_Msk (0x1ul << GP_DATMSK_DATMSK7_Pos)›GP_PIN_PIN0_Pos (0)œGP_PIN_PIN0_Msk (0x1ul << GP_PIN_PIN0_Pos)žGP_PIN_PIN1_Pos (1)ŸGP_PIN_PIN1_Msk (0x1ul << GP_PIN_PIN1_Pos)¡GP_PIN_PIN2_Pos (2)¢GP_PIN_PIN2_Msk (0x1ul << GP_PIN_PIN2_Pos)¤GP_PIN_PIN3_Pos (3)¥GP_PIN_PIN3_Msk (0x1ul << GP_PIN_PIN3_Pos)§GP_PIN_PIN4_Pos (4)¨GP_PIN_PIN4_Msk (0x1ul << GP_PIN_PIN4_Pos)ªGP_PIN_PIN5_Pos (5)«GP_PIN_PIN5_Msk (0x1ul << GP_PIN_PIN5_Pos)­GP_PIN_PIN6_Pos (6)®GP_PIN_PIN6_Msk (0x1ul << GP_PIN_PIN6_Pos)°GP_PIN_PIN7_Pos (7)±GP_PIN_PIN7_Msk (0x1ul << GP_PIN_PIN7_Pos)³GP_DBEN_DBEN0_Pos (0)´GP_DBEN_DBEN0_Msk (0x1ul << GP_DBEN_DBEN0_Pos)¶GP_DBEN_DBEN1_Pos (1)·GP_DBEN_DBEN1_Msk (0x1ul << GP_DBEN_DBEN1_Pos)¹GP_DBEN_DBEN2_Pos (2)ºGP_DBEN_DBEN2_Msk (0x1ul << GP_DBEN_DBEN2_Pos)¼GP_DBEN_DBEN3_Pos (3)½GP_DBEN_DBEN3_Msk (0x1ul << GP_DBEN_DBEN3_Pos)¿GP_DBEN_DBEN4_Pos (4)ÀGP_DBEN_DBEN4_Msk (0x1ul << GP_DBEN_DBEN4_Pos)ÂGP_DBEN_DBEN5_Pos (5)ÃGP_DBEN_DBEN5_Msk (0x1ul << GP_DBEN_DBEN5_Pos)ÅGP_DBEN_DBEN6_Pos (6)ÆGP_DBEN_DBEN6_Msk (0x1ul << GP_DBEN_DBEN6_Pos)ÈGP_DBEN_DBEN7_Pos (7)ÉGP_DBEN_DBEN7_Msk (0x1ul << GP_DBEN_DBEN7_Pos)ËGP_INTTYPE_TYPE0_Pos (0)ÌGP_INTTYPE_TYPE0_Msk (0x1ul << GP_INTTYPE_TYPE0_Pos)ÎGP_INTTYPE_TYPE1_Pos (1)ÏGP_INTTYPE_TYPE1_Msk (0x1ul << GP_INTTYPE_TYPE1_Pos)ÑGP_INTTYPE_TYPE2_Pos (2)ÒGP_INTTYPE_TYPE2_Msk (0x1ul << GP_INTTYPE_TYPE2_Pos)ÔGP_INTTYPE_TYPE3_Pos (3)ÕGP_INTTYPE_TYPE3_Msk (0x1ul << GP_INTTYPE_TYPE3_Pos)×GP_INTTYPE_TYPE4_Pos (4)ØGP_INTTYPE_TYPE4_Msk (0x1ul << GP_INTTYPE_TYPE4_Pos)ÚGP_INTTYPE_TYPE5_Pos (5)ÛGP_INTTYPE_TYPE5_Msk (0x1ul << GP_INTTYPE_TYPE5_Pos)ÝGP_INTTYPE_TYPE6_Pos (6)ÞGP_INTTYPE_TYPE6_Msk (0x1ul << GP_INTTYPE_TYPE6_Pos)àGP_INTTYPE_TYPE7_Pos (7)áGP_INTTYPE_TYPE7_Msk (0x1ul << GP_INTTYPE_TYPE7_Pos)ãGP_INTEN_FLIEN0_Pos (0)äGP_INTEN_FLIEN0_Msk (0x1ul << GP_INTEN_FLIEN0_Pos)æGP_INTEN_FLIEN1_Pos (1)çGP_INTEN_FLIEN1_Msk (0x1ul << GP_INTEN_FLIEN1_Pos)éGP_INTEN_FLIEN2_Pos (2)êGP_INTEN_FLIEN2_Msk (0x1ul << GP_INTEN_FLIEN2_Pos)ìGP_INTEN_FLIEN3_Pos (3)íGP_INTEN_FLIEN3_Msk (0x1ul << GP_INTEN_FLIEN3_Pos)ïGP_INTEN_FLIEN4_Pos (4)ðGP_INTEN_FLIEN4_Msk (0x1ul << GP_INTEN_FLIEN4_Pos)òGP_INTEN_FLIEN5_Pos (5)óGP_INTEN_FLIEN5_Msk (0x1ul << GP_INTEN_FLIEN5_Pos)õGP_INTEN_FLIEN6_Pos (6)öGP_INTEN_FLIEN6_Msk (0x1ul << GP_INTEN_FLIEN6_Pos)øGP_INTEN_FLIEN7_Pos (7)ùGP_INTEN_FLIEN7_Msk (0x1ul << GP_INTEN_FLIEN7_Pos)ûGP_INTEN_RHIEN0_Pos (16)üGP_INTEN_RHIEN0_Msk (0x1ul << GP_INTEN_RHIEN0_Pos)þGP_INTEN_RHIEN1_Pos (17)ÿGP_INTEN_RHIEN1_Msk (0x1ul << GP_INTEN_RHIEN1_Pos)GP_INTEN_RHIEN2_Pos (18)‚GP_INTEN_RHIEN2_Msk (0x1ul << GP_INTEN_RHIEN2_Pos)„GP_INTEN_RHIEN3_Pos (19)…GP_INTEN_RHIEN3_Msk (0x1ul << GP_INTEN_RHIEN3_Pos)‡GP_INTEN_RHIEN4_Pos (20)ˆGP_INTEN_RHIEN4_Msk (0x1ul << GP_INTEN_RHIEN4_Pos)ŠGP_INTEN_RHIEN5_Pos (21)‹GP_INTEN_RHIEN5_Msk (0x1ul << GP_INTEN_RHIEN5_Pos)GP_INTEN_RHIEN6_Pos (22)ŽGP_INTEN_RHIEN6_Msk (0x1ul << GP_INTEN_RHIEN6_Pos)GP_INTEN_RHIEN7_Pos (23)‘GP_INTEN_RHIEN7_Msk (0x1ul << GP_INTEN_RHIEN7_Pos)“GP_INTSRC_INTSRC0_Pos (0)”GP_INTSRC_INTSRC0_Msk (0x1ul << GP_INTSRC_INTSRC0_Pos)–GP_INTSRC_INTSRC1_Pos (1)—GP_INTSRC_INTSRC1_Msk (0x1ul << GP_INTSRC_INTSRC1_Pos)™GP_INTSRC_INTSRC2_Pos (2)šGP_INTSRC_INTSRC2_Msk (0x1ul << GP_INTSRC_INTSRC2_Pos)œGP_INTSRC_INTSRC3_Pos (3)GP_INTSRC_INTSRC3_Msk (0x1ul << GP_INTSRC_INTSRC3_Pos)ŸGP_INTSRC_INTSRC4_Pos (4) GP_INTSRC_INTSRC4_Msk (0x1ul << GP_INTSRC_INTSRC4_Pos)¢GP_INTSRC_INTSRC5_Pos (5)£GP_INTSRC_INTSRC5_Msk (0x1ul << GP_INTSRC_INTSRC5_Pos)¥GP_INTSRC_INTSRC6_Pos (6)¦GP_INTSRC_INTSRC6_Msk (0x1ul << GP_INTSRC_INTSRC6_Pos)¨GP_INTSRC_INTSRC7_Pos (7)©GP_INTSRC_INTSRC7_Msk (0x1ul << GP_INTSRC_INTSRC7_Pos)«GP_INTSRC_INTSRC8_Pos (8)¬GP_INTSRC_INTSRC8_Msk (0x1ul << GP_INTSRC_INTSRC8_Pos)®GP_INTSRC_INTSRC9_Pos (9)¯GP_INTSRC_INTSRC9_Msk (0x1ul << GP_INTSRC_INTSRC9_Pos)±GP_INTSRC_INTSRC10_Pos (10)²GP_INTSRC_INTSRC10_Msk (0x1ul << GP_INTSRC_INTSRC10_Pos)´GP_INTSRC_INTSRC11_Pos (11)µGP_INTSRC_INTSRC11_Msk (0x1ul << GP_INTSRC_INTSRC11_Pos)·GP_INTSRC_INTSRC12_Pos (12)¸GP_INTSRC_INTSRC12_Msk (0x1ul << GP_INTSRC_INTSRC12_Pos)ºGP_INTSRC_INTSRC13_Pos (13)»GP_INTSRC_INTSRC13_Msk (0x1ul << GP_INTSRC_INTSRC13_Pos)½GP_INTSRC_INTSRC14_Pos (14)¾GP_INTSRC_INTSRC14_Msk (0x1ul << GP_INTSRC_INTSRC14_Pos)ÀGP_INTSRC_INTSRC15_Pos (15)ÁGP_INTSRC_INTSRC15_Msk (0x1ul << GP_INTSRC_INTSRC15_Pos)ÃGP_DBCTL_DBCLKSEL_Pos (0)ÄGP_DBCTL_DBCLKSEL_Msk (0xful << GP_DBCTL_DBCLKSEL_Pos)ÆGP_DBCTL_DBCLKSRC_Pos (4)ÇGP_DBCTL_DBCLKSRC_Msk (0x1ul << GP_DBCTL_DBCLKSRC_Pos)ÉGP_DBCTL_ICLKON_Pos (5)ÊGP_DBCTL_ICLKON_Msk (0x1ul << GP_DBCTL_ICLKON_Pos)ÇADC_DAT_RESULT_Pos (0)ÈADC_DAT_RESULT_Msk (0xfffful << ADC_DAT_RESULT_Pos)ÉADC_DAT_OV_Pos (16)ÊADC_DAT_OV_Msk (0x1ul << ADC_DAT_OV_Pos)ËADC_DAT_VALID_Pos (17)ÌADC_DAT_VALID_Msk (0x1ul << ADC_DAT_VALID_Pos)ÎADC_CTL_ADCEN_Pos (0)ÏADC_CTL_ADCEN_Msk (0x1ul << ADC_CTL_ADCEN_Pos)ÐADC_CTL_ADCIEN_Pos (1)ÑADC_CTL_ADCIEN_Msk (0x1ul << ADC_CTL_ADCIEN_Pos)ÒADC_CTL_HWTRGSEL_Pos (4)ÓADC_CTL_HWTRGSEL_Msk (0x3ul << ADC_CTL_HWTRGSEL_Pos)ÔADC_CTL_HWTRGCOND_Pos (6)ÕADC_CTL_HWTRGCOND_Msk (0x1ul << ADC_CTL_HWTRGCOND_Pos)ÖADC_CTL_HWTRGEN_Pos (8)×ADC_CTL_HWTRGEN_Msk (0x1ul << ADC_CTL_HWTRGEN_Pos)ØADC_CTL_FIFO_EN_Pos (9)ÙADC_CTL_FIFO_EN_Msk (0x1ul << ADC_CTL_FIFO_EN_Pos)ÚADC_CTL_FIFO_THRE_STATE_Pos (10)ÛADC_CTL_FIFO_THRE_STATE_Msk (0x1ul << ADC_CTL_FIFO_THRE_STATE_Pos)ÜADC_CTL_SWTRG_Pos (11)ÝADC_CTL_SWTRG_Msk (0x1ul << ADC_CTL_SWTRG_Pos)ÞADC_CTL_SWTRG_Pos (11)ßADC_CTL_SWTRG_Msk (0x1ul << ADC_CTL_SWTRG_Pos)àADC_CTL_SWTRG_Pos (11)áADC_CTL_SWTRG_Msk (0x1ul << ADC_CTL_SWTRG_Pos)âADC_CTL_LEFT_SHIFT_EN_Pos (12)ãADC_CTL_LEFT_SHIFT_EN_Msk (0x1ul << ADC_CTL_LEFT_SHIFT_EN_Pos)äADC_CTL_SUB_BIAS_EN_Pos (13)åADC_CTL_SUB_BIAS_EN_Msk (0x1ul << ADC_CTL_SUB_BIAS_EN_Pos)æADC_CTL_BIAS_VALUE_Pos (16)çADC_CTL_BIAS_VALUE_Msk (0xffful << ADC_CTL_BIAS_VALUE_Pos)êADC_CHEN_CHEN0_Pos (0)ëADC_CHEN_CHEN0_Msk (0x1ul << ADC_CHEN_CHEN0_Pos)ìADC_CHEN_CHEN1_Pos (1)íADC_CHEN_CHEN1_Msk (0x1ul << ADC_CHEN_CHEN1_Pos)îADC_CHEN_CHEN2_Pos (2)ïADC_CHEN_CHEN2_Msk (0x1ul << ADC_CHEN_CHEN2_Pos)ðADC_CHEN_CHEN3_Pos (3)ñADC_CHEN_CHEN3_Msk (0x1ul << ADC_CHEN_CHEN3_Pos)òADC_CHEN_CHEN4_Pos (4)óADC_CHEN_CHEN4_Msk (0x1ul << ADC_CHEN_CHEN4_Pos)ôADC_CHEN_CHEN5_Pos (5)õADC_CHEN_CHEN5_Msk (0x1ul << ADC_CHEN_CHEN5_Pos)öADC_CHEN_CHEN6_Pos (6)÷ADC_CHEN_CHEN6_Msk (0x1ul << ADC_CHEN_CHEN6_Pos)øADC_CHEN_CHEN7_Pos (7)ùADC_CHEN_CHEN7_Msk (0x1ul << ADC_CHEN_CHEN7_Pos)úADC_CHEN_CHEN8_VBG_Pos (8)ûADC_CHEN_CHEN8_VBG_Msk (0x1ul << ADC_CHEN_CHEN8_VBG_Pos)üADC_CHEN_CH9_TMP_Pos (9)ýADC_CHEN_CH9_TMP_Msk (0x1ul << ADC_CHEN_CH9_TMP_Pos)þADC_CHEN_CH10_VDD_4_Pos (10)ÿADC_CHEN_CH10_VDD_4_Msk (0x1ul << ADC_CHEN_CH10_VDD_4_Pos)€ADC_CHEN_CH11_VBG_2_Pos (11)ADC_CHEN_CH11_VBG_2_Msk (0x1ul << ADC_CHEN_CH11_VBG_2_Pos)‚ADC_CHEN_ALL_Msk (0xFFFul)„ADC_CMP0_ADCMPEN_Pos (0)…ADC_CMP0_ADCMPEN_Msk (0x1ul << ADC_CMP0_ADCMPEN_Pos)†ADC_CMP0_ADCMPIE_Pos (1)‡ADC_CMP0_ADCMPIE_Msk (0x1ul << ADC_CMP0_ADCMPIE_Pos)ˆADC_CMP0_CMPCOND_Pos (2)‰ADC_CMP0_CMPCOND_Msk (0x1ul << ADC_CMP0_CMPCOND_Pos)ŠADC_CMP0_CMPCH_Pos (3)‹ADC_CMP0_CMPCH_Msk (0x7ul << ADC_CMP0_CMPCH_Pos)ŒADC_CMP0_CMPMCNT_Pos (8)ADC_CMP0_CMPMCNT_Msk (0xful << ADC_CMP0_CMPMCNT_Pos)ŽADC_CMP0_CMPDAT_Pos (16)ADC_CMP0_CMPDAT_Msk (0xffful << ADC_CMP0_CMPDAT_Pos)‘ADC_CMP1_ADCMPEN_Pos (0)’ADC_CMP1_ADCMPEN_Msk (0x1ul << ADC_CMP1_ADCMPEN_Pos)“ADC_CMP1_ADCMPIE_Pos (1)”ADC_CMP1_ADCMPIE_Msk (0x1ul << ADC_CMP1_ADCMPIE_Pos)•ADC_CMP1_CMPCOND_Pos (2)–ADC_CMP1_CMPCOND_Msk (0x1ul << ADC_CMP1_CMPCOND_Pos)—ADC_CMP1_CMPCH_Pos (3)˜ADC_CMP1_CMPCH_Msk (0x7ul << ADC_CMP1_CMPCH_Pos)™ADC_CMP1_CMPMCNT_Pos (8)šADC_CMP1_CMPMCNT_Msk (0xful << ADC_CMP1_CMPMCNT_Pos)›ADC_CMP1_CMPDAT_Pos (16)œADC_CMP1_CMPDAT_Msk (0xffful << ADC_CMP1_CMPDAT_Pos)žADC_STATUS_ADIF_Pos (0)ŸADC_STATUS_ADIF_Msk (0x1ul << ADC_STATUS_ADIF_Pos) ADC_STATUS_ADCMPIF0_Pos (1)¡ADC_STATUS_ADCMPIF0_Msk (0x1ul << ADC_STATUS_ADCMPIF0_Pos)¢ADC_STATUS_ADCMPIF1_Pos (2)£ADC_STATUS_ADCMPIF1_Msk (0x1ul << ADC_STATUS_ADCMPIF1_Pos)¤ADC_STATUS_BUSY_Pos (3)¥ADC_STATUS_BUSY_Msk (0x1ul << ADC_STATUS_BUSY_Pos)¦ADC_STATUS_CHANNEL_Pos (4)§ADC_STATUS_CHANNEL_Msk (0x7ul << ADC_STATUS_CHANNEL_Pos)¨ADC_STATUS_VALID_Pos (8)©ADC_STATUS_VALID_Msk (0x1ul << ADC_STATUS_VALID_Pos)ªADC_STATUS_INTMSK_FULL_Pos (9)«ADC_STATUS_INTMSK_FULL_Msk (0x1ul << ADC_STATUS_INTMSK_FULL_Pos)¬ADC_STATUS_INTMSK_EMPTY_Pos (10)­ADC_STATUS_INTMSK_EMPTY_Msk (0x1ul << ADC_STATUS_INTMSK_EMPTY_Pos)®ADC_STATUS_INTMSK_OVER_Pos (11)¯ADC_STATUS_INTMSK_OVER_Msk (0x1ul << ADC_STATUS_INTMSK_OVER_Pos)°ADC_STATUS_INTMSK_HALF_Pos (12)±ADC_STATUS_INTMSK_HALF_Msk (0x1ul << ADC_STATUS_INTMSK_HALF_Pos)²ADC_STATUS_INTMSK_AD_Pos (13)³ADC_STATUS_INTMSK_AD_Msk (0x1ul << ADC_STATUS_INTMSK_AD_Pos)´ADC_STATUS_INTMSK_CMP0_Pos (14)µADC_STATUS_INTMSK_CMP0_Msk (0x1ul << ADC_STATUS_INTMSK_CMP0_Pos)¶ADC_STATUS_INTMSK_CMP1_Pos (15)·ADC_STATUS_INTMSK_CMP1_Msk (0x1ul << ADC_STATUS_INTMSK_CMP1_Pos)¸ADC_STATUS_OV_Pos (16)¹ADC_STATUS_OV_Msk (0x1ul << ADC_STATUS_OV_Pos)ºADC_STATUS_ONE_CH_CLR_SEL_Pos (17)»ADC_STATUS_ONE_CH_CLR_SEL_Msk (0x1ul << ADC_STATUS_ONE_CH_CLR_SEL_Pos)¼ADC_STATUS_ONE_CH_FLAG_Pos (18)½ADC_STATUS_ONE_CH_FLAG_Msk (0x1ul << ADC_STATUS_ONE_CH_FLAG_Pos)¾ADC_STATUS_INTFLG_FULL_Pos (19)¿ADC_STATUS_INTFLG_FULL_Msk (0x1ul << ADC_STATUS_INTFLG_FULL_Pos)ÀADC_STATUS_INTFLG_EMPTY_Pos (20)ÁADC_STATUS_INTFLG_EMPTY_Msk (0x1ul << ADC_STATUS_INTFLG_EMPTY_Pos)ÂADC_STATUS_INTFLG_OVER_Pos (21)ÃADC_STATUS_INTFLG_OVER_Msk (0x1ul << ADC_STATUS_INTFLG_OVER_Pos)ÄADC_STATUS_INTFLG_HALF_Pos (22)ÅADC_STATUS_INTFLG_HALF_Msk (0x1ul << ADC_STATUS_INTFLG_HALF_Pos)ÆADC_STATUS_ADCF_Pos (24)ÇADC_STATUS_ADCF_Msk (0x1ul << ADC_STATUS_ADCF_Pos)ÈADC_STATUS_ADCMPF0_Pos (25)ÉADC_STATUS_ADCMPF0_Msk (0x1ul << ADC_STATUS_ADCMPF0_Pos)ÊADC_STATUS_ADCMPF1_Pos (26)ËADC_STATUS_ADCMPF1_Msk (0x1ul << ADC_STATUS_ADCMPF1_Pos)ÌADC_STATUS_FLAG_FULL_Pos (27)ÍADC_STATUS_FLAG_FULL_Msk (0x1ul << ADC_STATUS_FLAG_FULL_Pos)ÎADC_STATUS_FLAG_EMPTY_Pos (28)ÏADC_STATUS_FLAG_EMPTY_Msk (0x1ul << ADC_STATUS_FLAG_EMPTY_Pos)ÐADC_STATUS_FLAG_OVER_Pos (29)ÑADC_STATUS_FLAG_OVER_Msk (0x1ul << ADC_STATUS_FLAG_OVER_Pos)ÒADC_STATUS_FLAG_HALF_Pos (30)ÓADC_STATUS_FLAG_HALF_Msk (0x1ul << ADC_STATUS_FLAG_HALF_Pos)ÕADC_TRGDLY_DELAY_Pos (0)ÖADC_TRGDLY_DELAY_Msk (0xfful << ADC_TRGDLY_DELAY_Pos)ØADC_EXTSMPT_EXTSMPT_Pos (0)ÙADC_EXTSMPT_EXTSMPT_Msk (0x3fful << ADC_EXTSMPT_EXTSMPT_Pos)ÛADC_SEQCTL_SEQEN_Pos (0)ÜADC_SEQCTL_SEQEN_Msk (0x1ul << ADC_SEQCTL_SEQEN_Pos)ÝADC_SEQCTL_SEQTYPE_Pos (1)ÞADC_SEQCTL_SEQTYPE_Msk (0x1ul << ADC_SEQCTL_SEQTYPE_Pos)ßADC_SEQCTL_MODESEL_Pos (2)àADC_SEQCTL_MODESEL_Msk (0x3ul << ADC_SEQCTL_MODESEL_Pos)áADC_SEQCTL_DELAY_EN_Pos (4)âADC_SEQCTL_DELAY_EN_Msk (0x1ul << ADC_SEQCTL_DELAY_EN_Pos)ãADC_SEQCTL_TRG_SEL_Pos (5)äADC_SEQCTL_TRG_SEL_Msk (0x1ul << ADC_SEQCTL_TRG_SEL_Pos)åADC_SEQCTL_ONE_CH_EN_Pos (6)æADC_SEQCTL_ONE_CH_EN_Msk (0x1ul << ADC_SEQCTL_ONE_CH_EN_Pos)çADC_SEQCTL_TRG1CTL_Pos (8)èADC_SEQCTL_TRG1CTL_Msk (0xful << ADC_SEQCTL_TRG1CTL_Pos)éADC_SEQCTL_TRG2CTL_Pos (16)êADC_SEQCTL_TRG2CTL_Msk (0xful << ADC_SEQCTL_TRG2CTL_Pos)ìADC_SEQDAT1_RESULT_Pos (0)íADC_SEQDAT1_RESULT_Msk (0x3fful << ADC_SEQDAT1_RESULT_Pos)îADC_SEQDAT1_OV_Pos (16)ïADC_SEQDAT1_OV_Msk (0x1ul << ADC_SEQDAT1_OV_Pos)ðADC_SEQDAT1_VALID_Pos (17)ñADC_SEQDAT1_VALID_Msk (0x1ul << ADC_SEQDAT1_VALID_Pos)óADC_SEQDAT2_RESULT_Pos (0)ôADC_SEQDAT2_RESULT_Msk (0x3fful << ADC_SEQDAT2_RESULT_Pos)õADC_SEQDAT2_OV_Pos (16)öADC_SEQDAT2_OV_Msk (0x1ul << ADC_SEQDAT2_OV_Pos)÷ADC_SEQDAT2_VALID_Pos (17)øADC_SEQDAT2_VALID_Msk (0x1ul << ADC_SEQDAT2_VALID_Pos)úADC_CTL2_TESTMODE_Pos (0)ûADC_CTL2_TESTMODE_Msk (0x1ul << ADC_CTL2_TESTMODE_Pos)üADC_CTL2_SHSEL_Pos (1)ýADC_CTL2_SHSEL_Msk (0x1ul << ADC_CTL2_SHSEL_Pos)þADC_CTL2_DMA_EN_Pos (2)ÿADC_CTL2_DMA_EN_Msk (0x1ul << ADC_CTL2_DMA_EN_Pos)€ADC_CTL2_CLKDIV_Pos (8)ADC_CTL2_CLKDIV_Msk (0x7ul << ADC_CTL2_CLKDIV_Pos)‚ADC_SEL_VREF_Pos (17)ƒADC_SEL_VREF_Msk (0x1ul << ADC_SEL_VREF_Pos)„ADC_CTL2_CMPCTL_Pos (24)…ADC_CTL2_CMPCTL_Msk (0x3ul << ADC_CTL2_CMPCTL_Pos)†ADC_CTL2_DRVCTL_Pos (26)‡ADC_CTL2_DRVCTL_Msk (0x3ul << ADC_CTL2_DRVCTL_Pos)«SYS_P0_MFP_MFP_Pos (0)¬SYS_P0_MFP_MFP_Msk (0xfful << SYS_P0_MFP_MFP_Pos)®SYS_P0_MFP_ALT0_Pos (8)¯SYS_P0_MFP_ALT0_Msk (0x1ul << SYS_P0_MFP_ALT0_Pos)±SYS_P0_MFP_ALT1_Pos (9)²SYS_P0_MFP_ALT1_Msk (0x1ul << SYS_P0_MFP_ALT1_Pos)´SYS_P0_MFP_ALT2_Pos (10)µSYS_P0_MFP_ALT2_Msk (0x1ul << SYS_P0_MFP_ALT2_Pos)·SYS_P0_MFP_ALT3_Pos (11)¸SYS_P0_MFP_ALT3_Msk (0x1ul << SYS_P0_MFP_ALT3_Pos)ºSYS_P0_MFP_ALT4_Pos (12)»SYS_P0_MFP_ALT4_Msk (0x1ul << SYS_P0_MFP_ALT4_Pos)½SYS_P0_MFP_ALT5_Pos (13)¾SYS_P0_MFP_ALT5_Msk (0x1ul << SYS_P0_MFP_ALT5_Pos)ÀSYS_P0_MFP_ALT6_Pos (14)ÁSYS_P0_MFP_ALT6_Msk (0x1ul << SYS_P0_MFP_ALT6_Pos)ÃSYS_P0_MFP_ALT7_Pos (15)ÄSYS_P0_MFP_ALT7_Msk (0x1ul << SYS_P0_MFP_ALT7_Pos)ÆSYS_P1_MFP_MFP_Pos (0)ÇSYS_P1_MFP_MFP_Msk (0xfful << SYS_P1_MFP_MFP_Pos)ÉSYS_P1_MFP_ALT0_Pos (8)ÊSYS_P1_MFP_ALT0_Msk (0x1ul << SYS_P1_MFP_ALT0_Pos)ÌSYS_P1_MFP_ALT1_Pos (9)ÍSYS_P1_MFP_ALT1_Msk (0x1ul << SYS_P1_MFP_ALT1_Pos)ÏSYS_P1_MFP_ALT2_Pos (10)ÐSYS_P1_MFP_ALT2_Msk (0x1ul << SYS_P1_MFP_ALT2_Pos)ÒSYS_P1_MFP_ALT3_Pos (11)ÓSYS_P1_MFP_ALT3_Msk (0x1ul << SYS_P1_MFP_ALT3_Pos)ÕSYS_P1_MFP_ALT4_Pos (12)ÖSYS_P1_MFP_ALT4_Msk (0x1ul << SYS_P1_MFP_ALT4_Pos)ØSYS_P1_MFP_ALT5_Pos (13)ÙSYS_P1_MFP_ALT5_Msk (0x1ul << SYS_P1_MFP_ALT5_Pos)ÛSYS_P1_MFP_ALT6_Pos (14)ÜSYS_P1_MFP_ALT6_Msk (0x1ul << SYS_P1_MFP_ALT6_Pos)ÞSYS_P1_MFP_ALT7_Pos (15)ßSYS_P1_MFP_ALT7_Msk (0x1ul << SYS_P1_MFP_ALT7_Pos)áSYS_P1_MFP_TYPE_Pos (16)âSYS_P1_MFP_TYPE_Msk (0xfful << SYS_P1_MFP_TYPE_Pos)äSYS_P1_MFP_P12EXT_Pos (26)åSYS_P1_MFP_P12EXT_Msk (0x1ul << SYS_P1_MFP_P12EXT_Pos)çSYS_P1_MFP_P13EXT_Pos (27)èSYS_P1_MFP_P13EXT_Msk (0x1ul << SYS_P1_MFP_P13EXT_Pos)êSYS_P1_MFP_P14EXT_Pos (28)ëSYS_P1_MFP_P14EXT_Msk (0x1ul << SYS_P1_MFP_P14EXT_Pos)îSYS_P2_MFP_ALT0_Pos (8)ïSYS_P2_MFP_ALT0_Msk (0x1ul << SYS_P2_MFP_ALT0_Pos)ñSYS_P2_MFP_ALT1_Pos (9)òSYS_P2_MFP_ALT1_Msk (0x1ul << SYS_P2_MFP_ALT1_Pos)õSYS_P2_MFP_ALT2_Pos (10)öSYS_P2_MFP_ALT2_Msk (0x1ul << SYS_P2_MFP_ALT2_Pos)øSYS_P2_MFP_ALT3_Pos (11)ùSYS_P2_MFP_ALT3_Msk (0x1ul << SYS_P2_MFP_ALT3_Pos)ûSYS_P2_MFP_ALT4_Pos (12)üSYS_P2_MFP_ALT4_Msk (0x1ul << SYS_P2_MFP_ALT4_Pos)þSYS_P2_MFP_ALT5_Pos (13)ÿSYS_P2_MFP_ALT5_Msk (0x1ul << SYS_P2_MFP_ALT5_Pos) SYS_P2_MFP_ALT6_Pos (14)‚ SYS_P2_MFP_ALT6_Msk (0x1ul << SYS_P2_MFP_ALT6_Pos)… SYS_P2_MFP_ALT7_Pos (15)† SYS_P2_MFP_ALT7_Msk (0x1ul << SYS_P2_MFP_ALT7_Pos)‰ SYS_P3_MFP_MFP_Pos (0)Š SYS_P3_MFP_MFP_Msk (0xfful << SYS_P3_MFP_MFP_Pos)Œ SYS_P3_MFP_ALT0_Pos (8) SYS_P3_MFP_ALT0_Msk (0x1ul << SYS_P3_MFP_ALT0_Pos) SYS_P3_MFP_ALT1_Pos (9) SYS_P3_MFP_ALT1_Msk (0x1ul << SYS_P3_MFP_ALT1_Pos)’ SYS_P3_MFP_ALT2_Pos (10)“ SYS_P3_MFP_ALT2_Msk (0x1ul << SYS_P3_MFP_ALT2_Pos)• SYS_P3_MFP_ALT4_Pos (12)– SYS_P3_MFP_ALT4_Msk (0x1ul << SYS_P3_MFP_ALT4_Pos)˜ SYS_P3_MFP_ALT5_Pos (13)™ SYS_P3_MFP_ALT5_Msk (0x1ul << SYS_P3_MFP_ALT5_Pos)› SYS_P3_MFP_ALT6_Pos (14)œ SYS_P3_MFP_ALT6_Msk (0x1ul << SYS_P3_MFP_ALT6_Pos)ž SYS_P3_MFP_P32EXT_Pos (26)Ÿ SYS_P3_MFP_P32EXT_Msk (0x1ul << SYS_P3_MFP_P32EXT_Pos)¡ SYS_P4_MFP_MFP_Pos (0)¢ SYS_P4_MFP_MFP_Msk (0xfful << SYS_P4_MFP_MFP_Pos)¤ SYS_P4_MFP_ALT6_Pos (14)¥ SYS_P4_MFP_ALT6_Msk (0x1ul << SYS_P4_MFP_ALT6_Pos)§ SYS_P4_MFP_ALT7_Pos (15)¨ SYS_P4_MFP_ALT7_Msk (0x1ul << SYS_P4_MFP_ALT7_Pos)ª SYS_P5_MFP_MFP_Pos (0)« SYS_P5_MFP_MFP_Msk (0xfful << SYS_P5_MFP_MFP_Pos)­ SYS_P5_MFP_ALT0_Pos (8)® SYS_P5_MFP_ALT0_Msk (0x1ul << SYS_P5_MFP_ALT0_Pos)° SYS_P5_MFP_ALT1_Pos (9)± SYS_P5_MFP_ALT1_Msk (0x1ul << SYS_P5_MFP_ALT1_Pos)³ SYS_P5_MFP_ALT2_Pos (10)´ SYS_P5_MFP_ALT2_Msk (0x1ul << SYS_P5_MFP_ALT2_Pos)¶ SYS_P5_MFP_ALT3_Pos (11)· SYS_P5_MFP_ALT3_Msk (0x1ul << SYS_P5_MFP_ALT3_Pos)¹ SYS_P5_MFP_ALT4_Pos (12)º SYS_P5_MFP_ALT4_Msk (0x1ul << SYS_P5_MFP_ALT4_Pos)¼ SYS_P5_MFP_ALT5_Pos (13)½ SYS_P5_MFP_ALT5_Msk (0x1ul << SYS_P5_MFP_ALT5_Pos)¿ SYS_P5_MFP_ALT6_Pos (14)À SYS_P5_MFP_ALT6_Msk (0x1ul << SYS_P5_MFP_ALT5_Pos) SYS_P5_MFP_ALT7_Pos (15)àSYS_P5_MFP_ALT7_Msk (0x1ul << SYS_P5_MFP_ALT5_Pos)Å SYS_P5_MFP_P50EXT_Pos (24)Æ SYS_P5_MFP_P50EXT_Msk (0x1ul << SYS_P5_MFP_P50EXT_Pos)È SYS_P5_MFP_P51EXT_Pos (25)É SYS_P5_MFP_P51EXT_Msk (0x1ul << SYS_P5_MFP_P51EXT_Pos)Ë SYS_REGLCTL_REGLCTL_Pos (0)Ì SYS_REGLCTL_REGLCTL_Msk (0xfful << SYS_REGLCTL_REGLCTL_Pos)õ CLK_RSTSTS_CHIPRF_Pos (0)ö CLK_RSTSTS_CHIPRF_Msk (0x1ul << CLK_RSTSTS_CHIPRF_Pos)÷ CLK_RSTSTS_PINRF_Pos (1)ø CLK_RSTSTS_PINRF_Msk (0x1ul << CLK_RSTSTS_PINRF_Pos)ù CLK_RSTSTS_WDTRF_Pos (2)ú CLK_RSTSTS_WDTRF_Msk (0x1ul << CLK_RSTSTS_WDTRF_Pos)û CLK_RSTSTS_LVRRF_Pos (3)ü CLK_RSTSTS_LVRRF_Msk (0x1ul << CLK_RSTSTS_LVRRF_Pos)ý CLK_RSTSTS_BODRF_Pos (4)þ CLK_RSTSTS_BODRF_Msk (0x1ul << CLK_RSTSTS_BODRF_Pos)ÿ CLK_RSTSTS_SYSRF_Pos (5)€!CLK_RSTSTS_SYSRF_Msk (0x1ul << CLK_RSTSTS_SYSRF_Pos)!CLK_RSTSTS_PORRF_Pos (6)‚!CLK_RSTSTS_PORRF_Msk (0x1ul << CLK_RSTSTS_PORRF_Pos)ƒ!CLK_RSTSTS_CPURF_Pos (7)„!CLK_RSTSTS_CPURF_Msk (0x1ul << CLK_RSTSTS_CPURF_Pos)‡!CLK_IPRST0_CHIPRST_Pos (0)ˆ!CLK_IPRST0_CHIPRST_Msk (0x1ul << CLK_IPRST0_CHIPRST_Pos)‰!CLK_IPRST0_CPURST_Pos (1)Š!CLK_IPRST0_CPURST_Msk (0x1ul << CLK_IPRST0_CPURST_Pos)‹!CLK_IPRST0_DMARST_Pos (2)Œ!CLK_IPRST0_DMARST_Msk (0x1ul << CLK_IPRST0_DMARST_Pos)!CLK_IPRST0_RFRST_Pos (3)Ž!CLK_IPRST0_RFRST_Msk (0x1ul << CLK_IPRST0_RFRST_Pos)!CLK_IPRST0_EFUSERST_Pos (4)!CLK_IPRST0_EFUSERST_Msk (0x1ul << CLK_IPRST0_EFUSERST_Pos)‘!CLK_IPRST0_USBRST_Pos (6)’!CLK_IPRST0_USBRST_Msk (0x1ul << CLK_IPRST0_USBRST_Pos)“!CLK_IPRST0_MDMSTDBYRST_Pos (7)”!CLK_IPRST0_MDMSTDBYRST_Msk (0x1ul << CLK_IPRST0_MDMSTDBYRST_Pos)•!CLK_IPRST0_MDMRST_Pos (8)–!CLK_IPRST0_MDMRST_Msk (0x1ul << CLK_IPRST0_MDMRST_Pos)—!CLK_IPRST0_CHIPSCOPEEN_Pos (9)˜!CLK_IPRST0_CHIPSCOPEEN_Msk (0x1ul << CLK_IPRST0_CHIPSCOPEEN_Pos)™!CLK_IPRST0_FTORRST_Pos (10)š!CLK_IPRST0_FTORRST_Msk (0x1ul << CLK_IPRST0_FTORRST_Pos)!CLK_IPRST1_I2C0RST_Pos (0)ž!CLK_IPRST1_I2C0RST_Msk (0x1ul << CLK_IPRST1_I2C0RST_Pos)Ÿ!CLK_IPRST1_SPI0RST_Pos (2) !CLK_IPRST1_SPI0RST_Msk (0x1ul << CLK_IPRST1_SPI0RST_Pos)¡!CLK_IPRST1_SPI1RST_Pos (3)¢!CLK_IPRST1_SPI1RST_Msk (0x1ul << CLK_IPRST1_SPI1RST_Pos)£!CLK_IPRST1_UART0RST_Pos (6)¤!CLK_IPRST1_UART0RST_Msk (0x1ul << CLK_IPRST1_UART0RST_Pos)¥!CLK_IPRST1_UART1RST_Pos (7)¦!CLK_IPRST1_UART1RST_Msk (0x1ul << CLK_IPRST1_UART1RST_Pos)§!CLK_IPRST1_PWM0RST_Pos (8)¨!CLK_IPRST1_PWM0RST_Msk (0x1ul << CLK_IPRST1_PWM0RST_Pos)©!CLK_IPRST1_ADCRST_Pos (9)ª!CLK_IPRST1_ADCRST_Msk (0x1ul << CLK_IPRST1_ADCRST_Pos)«!CLK_IPRST1_WDTRST_Pos (10)¬!CLK_IPRST1_WDTRST_Msk (0x1ul << CLK_IPRST1_WDTRST_Pos)­!CLK_IPRST1_WWDTRST_Pos (11)®!CLK_IPRST1_WWDTRST_Msk (0x1ul << CLK_IPRST1_WWDTRST_Pos)¯!CLK_IPRST1_TMR0RST_Pos (12)°!CLK_IPRST1_TMR0RST_Msk (0x1ul << CLK_IPRST1_TMR0RST_Pos)±!CLK_IPRST1_TMR1RST_Pos (13)²!CLK_IPRST1_TMR1RST_Msk (0x1ul << CLK_IPRST1_TMR1RST_Pos)³!CLK_IPRST1_TMR2RST_Pos (14)´!CLK_IPRST1_TMR2RST_Msk (0x1ul << CLK_IPRST1_TMR2RST_Pos)µ!CLK_IPRST1_GPIORST_Pos (15)¶!CLK_IPRST1_GPIORST_Msk (0x1ul << CLK_IPRST1_GPIORST_Pos)·!CLK_IPRST1_TRIMRST_Pos (16)¸!CLK_IPRST1_TRIMRST_Msk (0x1ul << CLK_IPRST1_TRIMRST_Pos)»!CLK_BODCTL_BODRSTEN_Pos_3v (3)¼!CLK_BODCTL_BODRSTEN_Msk_3v (0x1ul << CLK_BODCTL_BODRSTEN_Pos_3v)½!CLK_BODCTL_BODIF_Pos (4)¾!CLK_BODCTL_BODIF_Msk (0x1ul << CLK_BODCTL_BODIF_Pos)¿!CLK_BODCTL_BODOUT_Pos (6)À!CLK_BODCTL_BODOUT_Msk (0x1ul << CLK_BODCTL_BODOUT_Pos)Á!CLK_BODCTL_LVREN_Pos_3v (16)Â!CLK_BODCTL_LVREN_Msk_3v (0x1ul << CLK_BODCTL_LVREN_Pos_3v)Ã!CLK_BODCTL_BODEN_Pos_3v (17)Ä!CLK_BODCTL_BODEN_Msk_3v (0x1ul << CLK_BODCTL_BODEN_Pos_3v)Å!CLK_BODCTL_BODSEL_Pos_3v (18)Æ!CLK_BODCTL_BODSEL_Msk_3v (0x7ul << CLK_BODCTL_BODSEL_Pos_3v)Ç!CLK_BODCTL_LVR_TEST_Pos_3v (21)È!CLK_BODCTL_LVR_TEST_Msk_3v (0x1ul << CLK_BODCTL_LVR_TEST_Pos_3v)É!CLK_BODCTL_BOD_TEST_Pos_3v (22)Ê!CLK_BODCTL_BOD_TEST_Msk_3v (0x1ul << CLK_BODCTL_BOD_TEST_Pos_3v)Í!CLK_BLDBCTL_LVRDB_SEL_Pos_3v (8)Î!CLK_BLDBCTL_LVRDB_SEL_Msk_3v (0x3Ful << CLK_BLDBCTL_LVRDB_SEL_Pos_3v)Ï!CLK_BLDBCTL_BODDB_SEL_Pos_3v (0)Ð!CLK_BLDBCTL_BODDB_SEL_Msk_3v (0x3Ful << CLK_BLDBCTL_BODDB_SEL_Pos_3v)Ó!CLK_TOPCTL_RSICV_SYSCNT_EN_Pos (0)Ô!CLK_TOPCTL_RSICV_SYSCNT_EN_Msk (0x1ul << CLK_TOPCTL_RSICV_SYSCNT_EN_Pos)Õ!CLK_TOPCTL_SYS_CLK_SEL_Pos (8)Ö!CLK_TOPCTL_SYS_CLK_SEL_Msk (0x3ul << CLK_TOPCTL_SYS_CLK_SEL_Pos)×!CLK_TOPCTL_32K_CLK_SEL_Pos_3v (10)Ø!CLK_TOPCTL_32K_CLK_SEL_Msk_3v (0x1ul << CLK_TOPCTL_32K_CLK_SEL_Pos_3v)Ù!CLK_TOPCTL_AHB_DIV_Pos (12)Ú!CLK_TOPCTL_AHB_DIV_Msk (0xFul << CLK_TOPCTL_AHB_DIV_Pos)Û!CLK_TOPCTL_APB1_DIV_Pos (16)Ü!CLK_TOPCTL_APB1_DIV_Msk (0xFul << CLK_TOPCTL_APB1_DIV_Pos)Ý!CLK_TOPCTL_APB2_DIV_Pos (20)Þ!CLK_TOPCTL_APB2_DIV_Msk (0xFul << CLK_TOPCTL_APB2_DIV_Pos)á!CLK_RCLCTL_RC32K_EN_Pos_3v (0)â!CLK_RCLCTL_RC32K_EN_Msk_3v (0x1ul << CLK_RCLCTL_RC32K_EN_Pos_3v)ã!CLK_RCLCTL_RC32K_TST_EN_Pos (1)ä!CLK_RCLCTL_RC32K_TST_EN_Msk (0x1ul << CLK_RCLCTL_RC32K_TST_EN_Pos)å!CLK_RCLCTL_CLK_SEL_Pos_3v (2)æ!CLK_RCLCTL_CLK_SEL_Msk_3v (0x1ul << CLK_RCLCTL_CLK_SEL_Pos_3v)ç!CLK_RCLCTL_RC32K_COARSE_Pos_3v (4)è!CLK_RCLCTL_RC32K_COARSE_Msk_3v (0xFul << CLK_RCLCTL_RC32K_COARSE_Pos_3v)é!CLK_RCLCTL_RC32K_FINE_Pos_3v (8)ê!CLK_RCLCTL_RC32K_FINE_Msk_3v (0xFFul << CLK_RCLCTL_RC32K_FINE_Pos_3v)ë!CLK_RCLCTL_RC32K_DELAY_Pos_3v (16)ì!CLK_RCLCTL_RC32K_DELAY_Msk_3v (0x3ul << CLK_RCLCTL_RC32K_DELAY_Pos_3v)í!CLK_RCLCTL_STABLE_Pos (24)î!CLK_RCLCTL_STABLE_Msk (0x1ul << CLK_RCLCTL_STABLE_Pos)ñ!CLK_RCHCTL_RCH_EN_Pos (0)ò!CLK_RCHCTL_RCH_EN_Msk (0x1ul << CLK_RCHCTL_RCH_EN_Pos)ó!CLK_RCHCTL_RCH_TST_EN_Pos (1)ô!CLK_RCHCTL_RCH_TST_EN_Msk (0x1ul << CLK_RCHCTL_RCH_TST_EN_Pos)õ!CLK_RCHCTL_CLK_SEL_Pos (2)ö!CLK_RCHCTL_CLK_SEL_Msk (0x1ul << CLK_RCHCTL_CLK_SEL_Pos)÷!CLK_RCHCTL_BIAS_Pos (4)ø!CLK_RCHCTL_BIAS_Msk (0x3ul << CLK_RCHCTL_BIAS_Pos)ù!CLK_RCHCTL_RCH_FREQ_Pos (8)ú!CLK_RCHCTL_RCH_FREQ_Msk (0xFFul << CLK_RCHCTL_RCH_FREQ_Pos)û!CLK_RCHCTL_DELAY_Pos (16)ü!CLK_RCHCTL_DELAY_Msk (0x3ul << CLK_RCHCTL_DELAY_Pos)ý!CLK_RCHCTL_STABLE_Pos (24)þ!CLK_RCHCTL_STABLE_Msk (0x1ul << CLK_RCHCTL_STABLE_Pos)"CLK_XTLCTL_XTL_EN_Pos_3v (0)‚"CLK_XTLCTL_XTL_EN_Msk_3v (0x1ul << CLK_XTLCTL_XTL_EN_Pos_3v)ƒ"CLK_XTLCTL_XTL_TST_EN_Pos (1)„"CLK_XTLCTL_XTL_TST_EN_Msk (0x1ul << CLK_XTLCTL_XTL_TST_EN_Pos)…"CLK_XTLCTL_CORE_BIAS_Pos_3v (4)†"CLK_XTLCTL_CORE_BIAS_Msk_3v (0x7ul << CLK_XTLCTL_CORE_BIAS_Pos_3v)‡"CLK_XTLCTL_XTL_TRIM_Pos_3v (7)ˆ"CLK_XTLCTL_XTL_TRIM_Msk_3v (0x3Ful << CLK_XTLCTL_XTL_TRIM_Pos_3v)‰"CLK_XTLCTL_XTL_CAP_EN_Pos_3v (13)Š"CLK_XTLCTL_XTL_CAP_EN_Msk_3v (0x1ul << CLK_XTLCTL_XTL_CAP_EN_Pos_3v)‹"CLK_XTLCTL_DELAY_Pos_3v (16)Œ"CLK_XTLCTL_DELAY_Msk_3v (0x3ul << CLK_XTLCTL_DELAY_Pos_3v)"CLK_XTLCTL_STABLE_Pos (24)Ž"CLK_XTLCTL_STABLE_Msk (0x1ul << CLK_XTLCTL_STABLE_Pos)‘"CLK_XTHCTL_XTH_EN_Pos (0)’"CLK_XTHCTL_XTH_EN_Msk (0x1ul << CLK_XTHCTL_XTH_EN_Pos)“"CLK_XTHCTL_XTH_TST_EN_Pos (1)”"CLK_XTHCTL_XTH_TST_EN_Msk (0x1ul << CLK_XTHCTL_XTH_TST_EN_Pos)•"CLK_XTHCTL_START_FAST_Pos (2)–"CLK_XTHCTL_START_FAST_Msk (0x1ul << CLK_XTHCTL_START_FAST_Pos)—"CLK_XTHCTL_DEGLITCH_EN_Pos (3)˜"CLK_XTHCTL_DEGLITCH_EN_Msk (0x1ul << CLK_XTHCTL_DEGLITCH_EN_Pos)™"CLK_XTHCTL_XO_CAP_SEL_Pos (4)š"CLK_XTHCTL_XO_CAP_SEL_Msk (0x3ful << CLK_XTHCTL_XO_CAP_SEL_Pos)›"CLK_XTHCTL_DELAY_Pos (16)œ"CLK_XTHCTL_DELAY_Msk (0x1ul << CLK_XTHCTL_DELAY_Pos)"CLK_XTHCTL_STABLE_Pos (24)ž"CLK_XTHCTL_STABLE_Msk (0x1ul << CLK_XTHCTL_STABLE_Pos)¡"CLK_DPLLCTL_DPLL_EN_Pos (0)¢"CLK_DPLLCTL_DPLL_EN_Msk (0x1ul << CLK_DPLLCTL_DPLL_EN_Pos)£"CLK_DPLLCTL_DPLL_TST_EN_Pos (1)¤"CLK_DPLLCTL_DPLL_TST_EN_Msk (0x1ul << CLK_DPLLCTL_DPLL_TST_EN_Pos)¥"CLK_DPLLCTL_FREQ_OUT_Pos (2)¦"CLK_DPLLCTL_FREQ_OUT_Msk (0x1ul << CLK_DPLLCTL_FREQ_OUT_Pos)§"CLK_DPLLCTL_RCLK_SEL_Pos (3)¨"CLK_DPLLCTL_RCLK_SEL_Msk (0x1ul << CLK_DPLLCTL_RCLK_SEL_Pos)©"CLK_DPLLCTL_ICP_BIAS_Pos (4)ª"CLK_DPLLCTL_ICP_BIAS_Msk (0x3ul << CLK_DPLLCTL_ICP_BIAS_Pos)«"CLK_DPLLCTL_ICP_CTRL_Pos (6)¬"CLK_DPLLCTL_ICP_CTRL_Msk (0x3ul << CLK_DPLLCTL_ICP_CTRL_Pos)­"CLK_DPLLCTL_KVCO_CTRL_Pos (8)®"CLK_DPLLCTL_KVCO_CTRL_Msk (0x7ul << CLK_DPLLCTL_KVCO_CTRL_Pos)¯"CLK_DPLLCTL_VCO_FREQ_TRIM_Pos (11)°"CLK_DPLLCTL_VCO_FREQ_TRIM_Msk (0x3ul << CLK_DPLLCTL_VCO_FREQ_TRIM_Pos)±"CLK_DPLLCTL_DIV_SEL_Pos (13)²"CLK_DPLLCTL_DIV_SEL_Msk (0x1ul << CLK_DPLLCTL_DIV_SEL_Pos)³"CLK_DPLLCTL_DELAY_Pos (16)´"CLK_DPLLCTL_DELAY_Msk (0x3ul << CLK_DPLLCTL_STARTUP_Pos)µ"CLK_DPLLCTL_STABLE_Pos (24)¶"CLK_DPLLCTL_STABLE_Msk (0x1ul << CLK_DPLLCTL_STABLE_Pos)¹"CLK_AHBCLK_DMAEN_Pos (0)º"CLK_AHBCLK_DMAEN_Msk (0x1ul << CLK_AHBCLK_DMAEN_Pos)»"CLK_AHBCLK_GPIOEN_Pos (1)¼"CLK_AHBCLK_GPIOEN_Msk (0x1ul << CLK_AHBCLK_GPIOEN_Pos)½"CLK_AHBCLK_SYSTICK_EN_Pos (2)¾"CLK_AHBCLK_SYSTICK_EN_Msk (0x1ul << CLK_AHBCLK_SYSTICK_EN_Pos)¿"CLK_AHBCLK_APB1EN_Pos (3)À"CLK_AHBCLK_APB1EN_Msk (0x1ul << CLK_AHBCLK_APB1EN_Pos)Á"CLK_AHBCLK_APB2EN_Pos (4)Â"CLK_AHBCLK_APB2EN_Msk (0x1ul << CLK_AHBCLK_APB2EN_Pos)Ã"CLK_AHBCLK_AHBEN_Pos (5)Ä"CLK_AHBCLK_AHBEN_Msk (0x1ul << CLK_AHBCLK_AHBEN_Pos)Å"CLK_AHBCLK_BLE32M_EN_Pos (6)Æ"CLK_AHBCLK_BLE32M_EN_Msk (0x1ul << CLK_AHBCLK_BLE32M_EN_Pos)Ç"CLK_AHBCLK_BLE32K_EN_Pos (7)È"CLK_AHBCLK_BLE32K_EN_Msk (0x1ul << CLK_AHBCLK_BLE32K_EN_Pos)É"CLK_AHBCLK_BLE32M_SEL_Pos (8)Ê"CLK_AHBCLK_BLE32M_SEL_Msk (0x3ul << CLK_AHBCLK_BLE32M_SEL_Pos)Ë"CLK_AHBCLK_ROM_CLK_EN_Pos (10)Ì"CLK_AHBCLK_ROM_CLK_EN_Msk (0x1ul << CLK_AHBCLK_ROM_CLK_EN_Pos)Í"CLK_AHBCLK_EFUSE_CLK_EN_Pos (11)Î"CLK_AHBCLK_EFUSE_CLK_EN_Msk (0x1ul << CLK_AHBCLK_EFUSE_CLK_EN_Pos)Ï"CLK_AHBCLK_USB_AHB_CLK_EN_Pos (13)Ð"CLK_AHBCLK_USB_AHB_CLK_EN_Msk (0x1ul << CLK_AHBCLK_USB_AHB_CLK_EN_Pos)Ñ"CLK_AHBCLK_USB_48M_CLK_EN_Pos (14)Ò"CLK_AHBCLK_USB_48M_CLK_EN_Msk (0x1ul << CLK_AHBCLK_USB_48M_CLK_EN_Pos)Ó"CLK_AHBCLK_SPI_FLASH_DIV_Pos (16)Ô"CLK_AHBCLK_SPI_FLASH_DIV_Msk (0xFul << CLK_AHBCLK_SPI_FLASH_DIV_Pos)Õ"CLK_AHBCLK_SPI_FLASH_CLK_SEL_Pos (20)Ö"CLK_AHBCLK_SPI_FLASH_CLK_SEL_Msk (0x1ul << CLK_AHBCLK_SPI_FLASH_CLK_SEL_Pos)×"CLK_AHBCLK_DPLL_CLK_TST_EN_Pos (21)Ø"CLK_AHBCLK_DPLL_CLK_TST_EN_Msk (0x1ul << CLK_AHBCLK_DPLL_CLK_TST_EN_Pos)Ù"CLK_AHBCLK_SPI_CLK_SEL_FPGA_Pos (24)Ú"CLK_AHBCLK_SPI_CLK_SEL_FPGA_Msk (0x1ul << CLK_AHBCLK_SPI_CLK_SEL_FPGA_Pos)Ý"CLK_APB1CLK_WDTSRC_SEL_Pos (16)Þ"CLK_APB1CLK_WDTSRC_SEL_Msk (0x1ul << CLK_APB1CLK_WDTSRC_SEL_Pos)ß"CLK_APB1CLK_WWDTSRC_SEL_Pos (17)à"CLK_APB1CLK_WWDTSRC_SEL_Msk (0x1ul << CLK_APB1CLK_WWDTSRC_SEL_Pos)á"CLK_APB1CLK_TMR0SRC_SEL_Pos (18)â"CLK_APB1CLK_TMR0SRC_SEL_Msk (0x3ul << CLK_APB1CLK_TMR0SRC_SEL_Pos)ã"CLK_APB1CLK_PWM01_CLK_SEL_Pos (20)ä"CLK_APB1CLK_PWM01_CLK_SEL_Msk (0x1ul << CLK_APB1CLK_PWM01_CLK_SEL_Pos)å"CLK_APB1CLK_PWM23_CLK_SEL_Pos (21)æ"CLK_APB1CLK_PWM23_CLK_SEL_Msk (0x1ul << CLK_APB1CLK_PWM23_CLK_SEL_Pos)ç"CLK_APB1CLK_PWM45_CLK_SEL_Pos (22)è"CLK_APB1CLK_PWM45_CLK_SEL_Msk (0x1ul << CLK_APB1CLK_PWM45_CLK_SEL_Pos)é"CLK_APB1CLK_PWM67_CLK_SEL_Pos (23)ê"CLK_APB1CLK_PWM67_CLK_SEL_Msk (0x1ul << CLK_APB1CLK_PWM67_CLK_SEL_Pos)ë"CLK_APB1CLK_ADC_CLK_SEL_Pos (24)ì"CLK_APB1CLK_ADC_CLK_SEL_Msk (0x1ul << CLK_APB1CLK_ADC_CLK_SEL_Pos)ï"CLK_APB2CLK_TMR1SRC_SEL_Pos (8)ð"CLK_APB2CLK_TMR1SRC_SEL_Msk (0x3ul << CLK_APB2CLK_TMR1SRC_SEL_Pos)ñ"CLK_APB2CLK_TMR2SRC_SEL_Pos (10)ò"CLK_APB2CLK_TMR2SRC_SEL_Msk (0x3ul << CLK_APB2CLK_TMR2SRC_SEL_Pos)ö"CLK_MEASCLK_TRIM_CLK_EN_Pos (1)÷"CLK_MEASCLK_TRIM_CLK_EN_Msk (0x1ul << CLK_MEASCLK_TRIM_CLK_EN_Pos)ø"CLK_MEASCLK_TRIM_CLK_SEL_Pos (2)ù"CLK_MEASCLK_TRIM_CLK_SEL_Msk (0x1ul << CLK_MEASCLK_TRIM_CLK_SEL_Pos)ú"CLK_MEASCLK_TRIM_CLK_DIV_Pos (4)û"CLK_MEASCLK_TRIM_CLK_DIV_Msk (0x1fful << CLK_MEASCLK_TRIM_CLK_DIV_Pos)ü"CLK_MEASCLK_XTL_QUICK_EN_Pos (14)ý"CLK_MEASCLK_XTL_QUICK_EN_Msk (0x1ul << CLK_MEASCLK_XTL_QUICK_EN_Pos)þ"CLK_MEASCLK_XTH_DIV_Pos (15)ÿ"CLK_MEASCLK_XTH_DIV_Msk (0x1fful << CLK_MEASCLK_XTH_DIV_Pos)ó#WDT_CTL_RSTCNT_Pos (0)ô#WDT_CTL_RSTCNT_Msk (0x1ul << WDT_CTL_RSTCNT_Pos)ö#WDT_CTL_RSTEN_Pos (1)÷#WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos)ù#WDT_CTL_RSTF_Pos (2)ú#WDT_CTL_RSTF_Msk (0x1ul << WDT_CTL_RSTF_Pos)ü#WDT_CTL_IF_Pos (3)ý#WDT_CTL_IF_Msk (0x1ul << WDT_CTL_IF_Pos)ÿ#WDT_CTL_WKEN_Pos (4)€$WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos)‚$WDT_CTL_WKF_Pos (5)ƒ$WDT_CTL_WKF_Msk (0x1ul << WDT_CTL_WKF_Pos)…$WDT_CTL_INTEN_Pos (6)†$WDT_CTL_INTEN_Msk (0x1ul << WDT_CTL_INTEN_Pos)ˆ$WDT_CTL_WDTEN_Pos (7)‰$WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos)‹$WDT_CTL_TOUTSEL_Pos (8)Œ$WDT_CTL_TOUTSEL_Msk (0xful << WDT_CTL_TOUTSEL_Pos)Ž$WDT_CTL_RST_REGION_SEL_Pos (12)$WDT_CTL_RST_REGION_SEL_Msk (0x1ul << WDT_CTL_RST_REGION_SEL_Pos)‘$WDT_CTL_TOF_Pos (16)’$WDT_CTL_TOF_Msk (0x1ul << WDT_CTL_TOF_Pos)”$WDT_CTL_ICEDEBUG_Pos (31)•$WDT_CTL_ICEDEBUG_Msk (0x1ul << WDT_CTL_ICEDEBUG_Pos)—$WDT_ALTCTL_RSTDSEL_Pos (0)˜$WDT_ALTCTL_RSTDSEL_Msk (0x3ul << WDT_ALTCTL_RSTDSEL_Pos)•%WWDT_RLDCNT_RLDCNT_Pos (0)–%WWDT_RLDCNT_RLDCNT_Msk (0xfffffffful << WWDT_RLDCNT_RLDCNT_Pos)˜%WWDT_CTL_WWDTEN_Pos (0)™%WWDT_CTL_WWDTEN_Msk (0x1ul << WWDT_CTL_WWDTEN_Pos)›%WWDT_CTL_INTEN_Pos (1)œ%WWDT_CTL_INTEN_Msk (0x1ul << WWDT_CTL_INTEN_Pos)ž%WWDT_CTL_PSCSEL_Pos (8)Ÿ%WWDT_CTL_PSCSEL_Msk (0xful << WWDT_CTL_PSCSEL_Pos)¡%WWDT_CTL_CMPDAT_Pos (16)¢%WWDT_CTL_CMPDAT_Msk (0x3ful << WWDT_CTL_CMPDAT_Pos)¤%WWDT_CTL_ICEDEBUG_Pos (31)¥%WWDT_CTL_ICEDEBUG_Msk (0x1ul << WWDT_CTL_ICEDEBUG_Pos)§%WWDT_STATUS_WWDTIF_Pos (0)¨%WWDT_STATUS_WWDTIF_Msk (0x1ul << WWDT_STATUS_WWDTIF_Pos)ª%WWDT_STATUS_WWDTRF_Pos (1)«%WWDT_STATUS_WWDTRF_Msk (0x1ul << WWDT_STATUS_WWDTRF_Pos)­%WWDT_STATUS_WWDTF_Pos (2)®%WWDT_STATUS_WWDTF_Msk (0x1ul << WWDT_STATUS_WWDTF_Pos)°%WWDT_CNT_CNTDAT_Pos (0)±%WWDT_CNT_CNTDAT_Msk (0x3ful << WWDT_CNT_CNTDAT_Pos)¹.PWM_CLKPSC_CLKPSC01_Pos (0)º.PWM_CLKPSC_CLKPSC01_Msk (0xfful << PWM_CLKPSC_CLKPSC01_Pos)¼.PWM_CLKPSC_CLKPSC23_Pos (8)½.PWM_CLKPSC_CLKPSC23_Msk (0xfful << PWM_CLKPSC_CLKPSC23_Pos)¿.PWM_CLKPSC_CLKPSC45_Pos (16)À.PWM_CLKPSC_CLKPSC45_Msk (0xfful << PWM_CLKPSC_CLKPSC45_Pos)Â.PWM_CLKPSC_CLKPSC67_Pos (24)Ã.PWM_CLKPSC_CLKPSC67_Msk (0xfful << PWM_CLKPSC_CLKPSC67_Pos)Å.PWM_CLKDIV_CLKDIV0_Pos (0)Æ.PWM_CLKDIV_CLKDIV0_Msk (0x7ul << PWM_CLKDIV_CLKDIV0_Pos)È.PWM_CLKDIV_CLKDIV1_Pos (4)É.PWM_CLKDIV_CLKDIV1_Msk (0x7ul << PWM_CLKDIV_CLKDIV1_Pos)Ë.PWM_CLKDIV_CLKDIV2_Pos (8)Ì.PWM_CLKDIV_CLKDIV2_Msk (0x7ul << PWM_CLKDIV_CLKDIV2_Pos)Î.PWM_CLKDIV_CLKDIV3_Pos (12)Ï.PWM_CLKDIV_CLKDIV3_Msk (0x7ul << PWM_CLKDIV_CLKDIV3_Pos)Ñ.PWM_CLKDIV_CLKDIV4_Pos (16)Ò.PWM_CLKDIV_CLKDIV4_Msk (0x7ul << PWM_CLKDIV_CLKDIV4_Pos)Ô.PWM_CLKDIV_CLKDIV5_Pos (20)Õ.PWM_CLKDIV_CLKDIV5_Msk (0x7ul << PWM_CLKDIV_CLKDIV5_Pos)Ø.PWM_CLKDIV_CLKDIV6_Pos (24)Ù.PWM_CLKDIV_CLKDIV6_Msk (0x7ul << PWM_CLKDIV_CLKDIV6_Pos)Û.PWM_CLKDIV_CLKDIV7_Pos (28)Ü.PWM_CLKDIV_CLKDIV7_Msk (0x7ul << PWM_CLKDIV_CLKDIV7_Pos)Þ.PWM_CTL_CNTEN0_Pos (0)ß.PWM_CTL_CNTEN0_Msk (0x1ul << PWM_CTL_CNTEN0_Pos)á.PWM_CTL_PINV0_Pos (2)â.PWM_CTL_PINV0_Msk (0x1ul << PWM_CTL_PINV0_Pos)ä.PWM_CTL_CNTMODE0_Pos (3)å.PWM_CTL_CNTMODE0_Msk (0x1ul << PWM_CTL_CNTMODE0_Pos)ç.PWM_CTL_CNTEN1_Pos (4)è.PWM_CTL_CNTEN1_Msk (0x1ul << PWM_CTL_CNTEN1_Pos)ê.PWM_CTL_HCUPDT_Pos (5)ë.PWM_CTL_HCUPDT_Msk (0x1ul << PWM_CTL_HCUPDT_Pos)í.PWM_CTL_PINV1_Pos (6)î.PWM_CTL_PINV1_Msk (0x1ul << PWM_CTL_PINV1_Pos)ð.PWM_CTL_CNTMODE1_Pos (7)ñ.PWM_CTL_CNTMODE1_Msk (0x1ul << PWM_CTL_CNTMODE1_Pos)ó.PWM_CTL_CNTEN2_Pos (8)ô.PWM_CTL_CNTEN2_Msk (0x1ul << PWM_CTL_CNTEN2_Pos)ö.PWM_CTL_PINV2_Pos (10)÷.PWM_CTL_PINV2_Msk (0x1ul << PWM_CTL_PINV2_Pos)ù.PWM_CTL_CNTMODE2_Pos (11)ú.PWM_CTL_CNTMODE2_Msk (0x1ul << PWM_CTL_CNTMODE2_Pos)ü.PWM_CTL_CNTEN3_Pos (12)ý.PWM_CTL_CNTEN3_Msk (0x1ul << PWM_CTL_CNTEN3_Pos)ÿ.PWM_CTL_PINV3_Pos (14)€/PWM_CTL_PINV3_Msk (0x1ul << PWM_CTL_PINV3_Pos)‚/PWM_CTL_CNTMODE3_Pos (15)ƒ/PWM_CTL_CNTMODE3_Msk (0x1ul << PWM_CTL_CNTMODE3_Pos)…/PWM_CTL_CNTEN4_Pos (16)†/PWM_CTL_CNTEN4_Msk (0x1ul << PWM_CTL_CNTEN4_Pos)ˆ/PWM_CTL_PINV4_Pos (18)‰/PWM_CTL_PINV4_Msk (0x1ul << PWM_CTL_PINV4_Pos)‹/PWM_CTL_CNTMODE4_Pos (19)Œ/PWM_CTL_CNTMODE4_Msk (0x1ul << PWM_CTL_CNTMODE4_Pos)Ž/PWM_CTL_CNTEN5_Pos (20)/PWM_CTL_CNTEN5_Msk (0x1ul << PWM_CTL_CNTEN5_Pos)‘/PWM_CTL_ASYMEN_Pos (21)’/PWM_CTL_ASYMEN_Msk (0x1ul << PWM_CTL_ASYMEN_Pos)”/PWM_CTL_PINV5_Pos (22)•/PWM_CTL_PINV5_Msk (0x1ul << PWM_CTL_PINV5_Pos)—/PWM_CTL_CNTMODE5_Pos (23)˜/PWM_CTL_CNTMODE5_Msk (0x1ul << PWM_CTL_CNTMODE5_Pos)š/PWM_CTL_CNTEN6_Pos (24)›/PWM_CTL_CNTEN6_Msk (0x1ul << PWM_CTL_CNTEN6_Pos)/PWM_CTL_PINV6_Pos (26)ž/PWM_CTL_PINV6_Msk (0x1ul << PWM_CTL_PINV6_Pos) /PWM_CTL_CNTMODE6_Pos (27)¡/PWM_CTL_CNTMODE6_Msk (0x1ul << PWM_CTL_CNTMODE6_Pos)£/PWM_CTL_CNTEN7_Pos (28)¤/PWM_CTL_CNTEN7_Msk (0x1ul << PWM_CTL_CNTEN7_Pos)¦/PWM_CTL_PINV7_Pos (30)§/PWM_CTL_PINV7_Msk (0x1ul << PWM_CTL_PINV7_Pos)©/PWM_CTL_CNTMODE7_Pos (31)ª/PWM_CTL_CNTMODE7_Msk (0x1ul << PWM_CTL_CNTMODE7_Pos)¬/PWM_PERIOD0_PERIOD0_Pos (0)­/PWM_PERIOD0_PERIOD0_Msk (0xfffful << PWM_PERIOD0_PERIOD0_Pos)¯/PWM_PERIOD0_PERIOD1_Pos (0)°/PWM_PERIOD0_PERIOD1_Msk (0xfffful << PWM_PERIOD0_PERIOD1_Pos)²/PWM_PERIOD0_PERIOD2_Pos (0)³/PWM_PERIOD0_PERIOD2_Msk (0xfffful << PWM_PERIOD0_PERIOD2_Pos)µ/PWM_PERIOD0_PERIOD3_Pos (0)¶/PWM_PERIOD0_PERIOD3_Msk (0xfffful << PWM_PERIOD0_PERIOD3_Pos)¸/PWM_PERIOD0_PERIOD4_Pos (0)¹/PWM_PERIOD0_PERIOD4_Msk (0xfffful << PWM_PERIOD0_PERIOD4_Pos)»/PWM_PERIOD0_PERIOD5_Pos (0)¼/PWM_PERIOD0_PERIOD5_Msk (0xfffful << PWM_PERIOD0_PERIOD5_Pos)¾/PWM_PERIOD0_PERIOD6_Pos (0)¿/PWM_PERIOD0_PERIOD6_Msk (0xfffful << PWM_PERIOD0_PERIOD6_Pos)Á/PWM_PERIOD0_PERIOD7_Pos (0)Â/PWM_PERIOD0_PERIOD7_Msk (0xfffful << PWM_PERIOD0_PERIOD7_Pos)Ä/PWM_PERIOD1_PERIOD0_Pos (0)Å/PWM_PERIOD1_PERIOD0_Msk (0xfffful << PWM_PERIOD1_PERIOD0_Pos)Ç/PWM_PERIOD1_PERIOD1_Pos (0)È/PWM_PERIOD1_PERIOD1_Msk (0xfffful << PWM_PERIOD1_PERIOD1_Pos)Ê/PWM_PERIOD1_PERIOD2_Pos (0)Ë/PWM_PERIOD1_PERIOD2_Msk (0xfffful << PWM_PERIOD1_PERIOD2_Pos)Í/PWM_PERIOD1_PERIOD3_Pos (0)Î/PWM_PERIOD1_PERIOD3_Msk (0xfffful << PWM_PERIOD1_PERIOD3_Pos)Ð/PWM_PERIOD1_PERIOD4_Pos (0)Ñ/PWM_PERIOD1_PERIOD4_Msk (0xfffful << PWM_PERIOD1_PERIOD4_Pos)Ó/PWM_PERIOD1_PERIOD5_Pos (0)Ô/PWM_PERIOD1_PERIOD5_Msk (0xfffful << PWM_PERIOD1_PERIOD5_Pos)Ö/PWM_PERIOD1_PERIOD6_Pos (0)×/PWM_PERIOD1_PERIOD6_Msk (0xfffful << PWM_PERIOD1_PERIOD6_Pos)Ù/PWM_PERIOD1_PERIOD7_Pos (0)Ú/PWM_PERIOD1_PERIOD7_Msk (0xfffful << PWM_PERIOD1_PERIOD7_Pos)Ü/PWM_PERIOD2_PERIOD0_Pos (0)Ý/PWM_PERIOD2_PERIOD0_Msk (0xfffful << PWM_PERIOD2_PERIOD0_Pos)ß/PWM_PERIOD2_PERIOD1_Pos (0)à/PWM_PERIOD2_PERIOD1_Msk (0xfffful << PWM_PERIOD2_PERIOD1_Pos)â/PWM_PERIOD2_PERIOD2_Pos (0)ã/PWM_PERIOD2_PERIOD2_Msk (0xfffful << PWM_PERIOD2_PERIOD2_Pos)å/PWM_PERIOD2_PERIOD3_Pos (0)æ/PWM_PERIOD2_PERIOD3_Msk (0xfffful << PWM_PERIOD2_PERIOD3_Pos)è/PWM_PERIOD2_PERIOD4_Pos (0)é/PWM_PERIOD2_PERIOD4_Msk (0xfffful << PWM_PERIOD2_PERIOD4_Pos)ë/PWM_PERIOD2_PERIOD5_Pos (0)ì/PWM_PERIOD2_PERIOD5_Msk (0xfffful << PWM_PERIOD2_PERIOD5_Pos)î/PWM_PERIOD2_PERIOD6_Pos (0)ï/PWM_PERIOD2_PERIOD6_Msk (0xfffful << PWM_PERIOD2_PERIOD6_Pos)ñ/PWM_PERIOD2_PERIOD7_Pos (0)ò/PWM_PERIOD2_PERIOD7_Msk (0xfffful << PWM_PERIOD2_PERIOD7_Pos)ô/PWM_PERIOD3_PERIOD0_Pos (0)õ/PWM_PERIOD3_PERIOD0_Msk (0xfffful << PWM_PERIOD3_PERIOD0_Pos)÷/PWM_PERIOD3_PERIOD1_Pos (0)ø/PWM_PERIOD3_PERIOD1_Msk (0xfffful << PWM_PERIOD3_PERIOD1_Pos)ú/PWM_PERIOD3_PERIOD2_Pos (0)û/PWM_PERIOD3_PERIOD2_Msk (0xfffful << PWM_PERIOD3_PERIOD2_Pos)ý/PWM_PERIOD3_PERIOD3_Pos (0)þ/PWM_PERIOD3_PERIOD3_Msk (0xfffful << PWM_PERIOD3_PERIOD3_Pos)€0PWM_PERIOD3_PERIOD4_Pos (0)0PWM_PERIOD3_PERIOD4_Msk (0xfffful << PWM_PERIOD3_PERIOD4_Pos)ƒ0PWM_PERIOD3_PERIOD5_Pos (0)„0PWM_PERIOD3_PERIOD5_Msk (0xfffful << PWM_PERIOD3_PERIOD5_Pos)†0PWM_PERIOD3_PERIOD6_Pos (0)‡0PWM_PERIOD3_PERIOD6_Msk (0xfffful << PWM_PERIOD3_PERIOD6_Pos)‰0PWM_PERIOD3_PERIOD7_Pos (0)Š0PWM_PERIOD3_PERIOD7_Msk (0xfffful << PWM_PERIOD3_PERIOD7_Pos)Œ0PWM_PERIOD4_PERIOD0_Pos (0)0PWM_PERIOD4_PERIOD0_Msk (0xfffful << PWM_PERIOD4_PERIOD0_Pos)0PWM_PERIOD4_PERIOD1_Pos (0)0PWM_PERIOD4_PERIOD1_Msk (0xfffful << PWM_PERIOD4_PERIOD1_Pos)’0PWM_PERIOD4_PERIOD2_Pos (0)“0PWM_PERIOD4_PERIOD2_Msk (0xfffful << PWM_PERIOD4_PERIOD2_Pos)•0PWM_PERIOD4_PERIOD3_Pos (0)–0PWM_PERIOD4_PERIOD3_Msk (0xfffful << PWM_PERIOD4_PERIOD3_Pos)˜0PWM_PERIOD4_PERIOD4_Pos (0)™0PWM_PERIOD4_PERIOD4_Msk (0xfffful << PWM_PERIOD4_PERIOD4_Pos)›0PWM_PERIOD4_PERIOD5_Pos (0)œ0PWM_PERIOD4_PERIOD5_Msk (0xfffful << PWM_PERIOD4_PERIOD5_Pos)ž0PWM_PERIOD4_PERIOD6_Pos (0)Ÿ0PWM_PERIOD4_PERIOD6_Msk (0xfffful << PWM_PERIOD4_PERIOD6_Pos)¡0PWM_PERIOD4_PERIOD7_Pos (0)¢0PWM_PERIOD4_PERIOD7_Msk (0xfffful << PWM_PERIOD4_PERIOD7_Pos)¤0PWM_PERIOD5_PERIOD0_Pos (0)¥0PWM_PERIOD5_PERIOD0_Msk (0xfffful << PWM_PERIOD5_PERIOD0_Pos)§0PWM_PERIOD5_PERIOD1_Pos (0)¨0PWM_PERIOD5_PERIOD1_Msk (0xfffful << PWM_PERIOD5_PERIOD1_Pos)ª0PWM_PERIOD5_PERIOD2_Pos (0)«0PWM_PERIOD5_PERIOD2_Msk (0xfffful << PWM_PERIOD5_PERIOD2_Pos)­0PWM_PERIOD5_PERIOD3_Pos (0)®0PWM_PERIOD5_PERIOD3_Msk (0xfffful << PWM_PERIOD5_PERIOD3_Pos)°0PWM_PERIOD5_PERIOD4_Pos (0)±0PWM_PERIOD5_PERIOD4_Msk (0xfffful << PWM_PERIOD5_PERIOD4_Pos)³0PWM_PERIOD5_PERIOD5_Pos (0)´0PWM_PERIOD5_PERIOD5_Msk (0xfffful << PWM_PERIOD5_PERIOD5_Pos)¶0PWM_PERIOD5_PERIOD6_Pos (0)·0PWM_PERIOD5_PERIOD6_Msk (0xfffful << PWM_PERIOD6_PERIOD6_Pos)¹0PWM_PERIOD5_PERIOD7_Pos (0)º0PWM_PERIOD5_PERIOD7_Msk (0xfffful << PWM_PERIOD6_PERIOD7_Pos)¼0PWM_PERIOD6_PERIOD0_Pos (0)½0PWM_PERIOD6_PERIOD0_Msk (0xfffful << PWM_PERIOD6_PERIOD0_Pos)¿0PWM_PERIOD6_PERIOD1_Pos (0)À0PWM_PERIOD6_PERIOD1_Msk (0xfffful << PWM_PERIOD6_PERIOD1_Pos)Â0PWM_PERIOD6_PERIOD2_Pos (0)Ã0PWM_PERIOD6_PERIOD2_Msk (0xfffful << PWM_PERIOD6_PERIOD2_Pos)Å0PWM_PERIOD6_PERIOD3_Pos (0)Æ0PWM_PERIOD6_PERIOD3_Msk (0xfffful << PWM_PERIOD6_PERIOD3_Pos)È0PWM_PERIOD6_PERIOD4_Pos (0)É0PWM_PERIOD6_PERIOD4_Msk (0xfffful << PWM_PERIOD6_PERIOD4_Pos)Ë0PWM_PERIOD6_PERIOD5_Pos (0)Ì0PWM_PERIOD6_PERIOD5_Msk (0xfffful << PWM_PERIOD6_PERIOD5_Pos)Î0PWM_PERIOD6_PERIOD6_Pos (0)Ï0PWM_PERIOD6_PERIOD6_Msk (0xfffful << PWM_PERIOD6_PERIOD6_Pos)Ñ0PWM_PERIOD6_PERIOD7_Pos (0)Ò0PWM_PERIOD6_PERIOD7_Msk (0xfffful << PWM_PERIOD6_PERIOD7_Pos)Ô0PWM_PERIOD7_PERIOD0_Pos (0)Õ0PWM_PERIOD7_PERIOD0_Msk (0xfffful << PWM_PERIOD7_PERIOD0_Pos)×0PWM_PERIOD7_PERIOD1_Pos (0)Ø0PWM_PERIOD7_PERIOD1_Msk (0xfffful << PWM_PERIOD7_PERIOD1_Pos)Ú0PWM_PERIOD7_PERIOD2_Pos (0)Û0PWM_PERIOD7_PERIOD2_Msk (0xfffful << PWM_PERIOD7_PERIOD2_Pos)Ý0PWM_PERIOD7_PERIOD3_Pos (0)Þ0PWM_PERIOD7_PERIOD3_Msk (0xfffful << PWM_PERIOD7_PERIOD3_Pos)à0PWM_PERIOD7_PERIOD4_Pos (0)á0PWM_PERIOD7_PERIOD4_Msk (0xfffful << PWM_PERIOD7_PERIOD4_Pos)ã0PWM_PERIOD7_PERIOD5_Pos (0)ä0PWM_PERIOD7_PERIOD5_Msk (0xfffful << PWM_PERIOD7_PERIOD5_Pos)æ0PWM_PERIOD7_PERIOD6_Pos (0)ç0PWM_PERIOD7_PERIOD6_Msk (0xfffful << PWM_PERIOD7_PERIOD6_Pos)é0PWM_PERIOD7_PERIOD7_Pos (0)ê0PWM_PERIOD7_PERIOD7_Msk (0xfffful << PWM_PERIOD7_PERIOD7_Pos)ì0PWM_CMPDAT0_CMP0_Pos (0)í0PWM_CMPDAT0_CMP0_Msk (0xfffful << PWM_CMPDAT0_CMP0_Pos)ï0PWM_CMPDAT0_CMP1_Pos (0)ð0PWM_CMPDAT0_CMP1_Msk (0xfffful << PWM_CMPDAT0_CMP1_Pos)ò0PWM_CMPDAT0_CMP2_Pos (0)ó0PWM_CMPDAT0_CMP2_Msk (0xfffful << PWM_CMPDAT0_CMP2_Pos)õ0PWM_CMPDAT0_CMP3_Pos (0)ö0PWM_CMPDAT0_CMP3_Msk (0xfffful << PWM_CMPDAT0_CMP3_Pos)ø0PWM_CMPDAT0_CMP4_Pos (0)ù0PWM_CMPDAT0_CMP4_Msk (0xfffful << PWM_CMPDAT0_CMP4_Pos)û0PWM_CMPDAT0_CMP5_Pos (0)ü0PWM_CMPDAT0_CMP5_Msk (0xfffful << PWM_CMPDAT0_CMP5_Pos)þ0PWM_CMPDAT0_CMP6_Pos (0)ÿ0PWM_CMPDAT0_CMP6_Msk (0xfffful << PWM_CMPDAT0_CMP6_Pos)1PWM_CMPDAT0_CMP7_Pos (0)‚1PWM_CMPDAT0_CMP7_Msk (0xfffful << PWM_CMPDAT0_CMP7_Pos)„1PWM_CMPDAT0_CMPD0_Pos (16)…1PWM_CMPDAT0_CMPD0_Msk (0xfffful << PWM_CMPDAT0_CMPD0_Pos)‡1PWM_CMPDAT0_CMPD1_Pos (16)ˆ1PWM_CMPDAT0_CMPD1_Msk (0xfffful << PWM_CMPDAT0_CMPD1_Pos)Š1PWM_CMPDAT0_CMPD2_Pos (16)‹1PWM_CMPDAT0_CMPD2_Msk (0xfffful << PWM_CMPDAT0_CMPD2_Pos)1PWM_CMPDAT0_CMPD3_Pos (16)Ž1PWM_CMPDAT0_CMPD3_Msk (0xfffful << PWM_CMPDAT0_CMPD3_Pos)1PWM_CMPDAT0_CMPD4_Pos (16)‘1PWM_CMPDAT0_CMPD4_Msk (0xfffful << PWM_CMPDAT0_CMPD4_Pos)“1PWM_CMPDAT0_CMPD5_Pos (16)”1PWM_CMPDAT0_CMPD5_Msk (0xfffful << PWM_CMPDAT0_CMPD5_Pos)–1PWM_CMPDAT0_CMPD6_Pos (16)—1PWM_CMPDAT0_CMPD6_Msk (0xfffful << PWM_CMPDAT0_CMPD6_Pos)™1PWM_CMPDAT0_CMPD7_Pos (16)š1PWM_CMPDAT0_CMPD7_Msk (0xfffful << PWM_CMPDAT0_CMPD7_Pos)œ1PWM_CMPDAT1_CMP0_Pos (0)1PWM_CMPDAT1_CMP0_Msk (0xfffful << PWM_CMPDAT1_CMP0_Pos)Ÿ1PWM_CMPDAT1_CMP1_Pos (0) 1PWM_CMPDAT1_CMP1_Msk (0xfffful << PWM_CMPDAT1_CMP1_Pos)¢1PWM_CMPDAT1_CMP2_Pos (0)£1PWM_CMPDAT1_CMP2_Msk (0xfffful << PWM_CMPDAT1_CMP2_Pos)¥1PWM_CMPDAT1_CMP3_Pos (0)¦1PWM_CMPDAT1_CMP3_Msk (0xfffful << PWM_CMPDAT1_CMP3_Pos)¨1PWM_CMPDAT1_CMP4_Pos (0)©1PWM_CMPDAT1_CMP4_Msk (0xfffful << PWM_CMPDAT1_CMP4_Pos)«1PWM_CMPDAT1_CMP5_Pos (0)¬1PWM_CMPDAT1_CMP5_Msk (0xfffful << PWM_CMPDAT1_CMP5_Pos)®1PWM_CMPDAT1_CMP6_Pos (0)¯1PWM_CMPDAT1_CMP6_Msk (0xfffful << PWM_CMPDAT1_CMP6_Pos)±1PWM_CMPDAT1_CMP7_Pos (0)²1PWM_CMPDAT1_CMP7_Msk (0xfffful << PWM_CMPDAT1_CMP7_Pos)´1PWM_CMPDAT1_CMPD0_Pos (16)µ1PWM_CMPDAT1_CMPD0_Msk (0xfffful << PWM_CMPDAT1_CMPD0_Pos)·1PWM_CMPDAT1_CMPD1_Pos (16)¸1PWM_CMPDAT1_CMPD1_Msk (0xfffful << PWM_CMPDAT1_CMPD1_Pos)º1PWM_CMPDAT1_CMPD2_Pos (16)»1PWM_CMPDAT1_CMPD2_Msk (0xfffful << PWM_CMPDAT1_CMPD2_Pos)½1PWM_CMPDAT1_CMPD3_Pos (16)¾1PWM_CMPDAT1_CMPD3_Msk (0xfffful << PWM_CMPDAT1_CMPD3_Pos)À1PWM_CMPDAT1_CMPD4_Pos (16)Á1PWM_CMPDAT1_CMPD4_Msk (0xfffful << PWM_CMPDAT1_CMPD4_Pos)Ã1PWM_CMPDAT1_CMPD5_Pos (16)Ä1PWM_CMPDAT1_CMPD5_Msk (0xfffful << PWM_CMPDAT1_CMPD5_Pos)Æ1PWM_CMPDAT1_CMPD6_Pos (16)Ç1PWM_CMPDAT1_CMPD6_Msk (0xfffful << PWM_CMPDAT1_CMPD6_Pos)É1PWM_CMPDAT1_CMPD7_Pos (16)Ê1PWM_CMPDAT1_CMPD7_Msk (0xfffful << PWM_CMPDAT1_CMPD7_Pos)Ì1PWM_CMPDAT2_CMP0_Pos (0)Í1PWM_CMPDAT2_CMP0_Msk (0xfffful << PWM_CMPDAT2_CMP0_Pos)Ï1PWM_CMPDAT2_CMP1_Pos (0)Ð1PWM_CMPDAT2_CMP1_Msk (0xfffful << PWM_CMPDAT2_CMP1_Pos)Ò1PWM_CMPDAT2_CMP2_Pos (0)Ó1PWM_CMPDAT2_CMP2_Msk (0xfffful << PWM_CMPDAT2_CMP2_Pos)Õ1PWM_CMPDAT2_CMP3_Pos (0)Ö1PWM_CMPDAT2_CMP3_Msk (0xfffful << PWM_CMPDAT2_CMP3_Pos)Ø1PWM_CMPDAT2_CMP4_Pos (0)Ù1PWM_CMPDAT2_CMP4_Msk (0xfffful << PWM_CMPDAT2_CMP4_Pos)Û1PWM_CMPDAT2_CMP5_Pos (0)Ü1PWM_CMPDAT2_CMP5_Msk (0xfffful << PWM_CMPDAT2_CMP5_Pos)Þ1PWM_CMPDAT2_CMP6_Pos (0)ß1PWM_CMPDAT2_CMP6_Msk (0xfffful << PWM_CMPDAT2_CMP6_Pos)á1PWM_CMPDAT2_CMP7_Pos (0)â1PWM_CMPDAT2_CMP7_Msk (0xfffful << PWM_CMPDAT2_CMP7_Pos)ä1PWM_CMPDAT2_CMPD0_Pos (16)å1PWM_CMPDAT2_CMPD0_Msk (0xfffful << PWM_CMPDAT2_CMPD0_Pos)ç1PWM_CMPDAT2_CMPD1_Pos (16)è1PWM_CMPDAT2_CMPD1_Msk (0xfffful << PWM_CMPDAT2_CMPD1_Pos)ê1PWM_CMPDAT2_CMPD2_Pos (16)ë1PWM_CMPDAT2_CMPD2_Msk (0xfffful << PWM_CMPDAT2_CMPD2_Pos)í1PWM_CMPDAT2_CMPD3_Pos (16)î1PWM_CMPDAT2_CMPD3_Msk (0xfffful << PWM_CMPDAT2_CMPD3_Pos)ð1PWM_CMPDAT2_CMPD4_Pos (16)ñ1PWM_CMPDAT2_CMPD4_Msk (0xfffful << PWM_CMPDAT2_CMPD4_Pos)ó1PWM_CMPDAT2_CMPD5_Pos (16)ô1PWM_CMPDAT2_CMPD5_Msk (0xfffful << PWM_CMPDAT2_CMPD5_Pos)ö1PWM_CMPDAT2_CMPD6_Pos (16)÷1PWM_CMPDAT2_CMPD6_Msk (0xfffful << PWM_CMPDAT2_CMPD6_Pos)ù1PWM_CMPDAT2_CMPD7_Pos (16)ú1PWM_CMPDAT2_CMPD7_Msk (0xfffful << PWM_CMPDAT2_CMPD7_Pos)ü1PWM_CMPDAT3_CMP0_Pos (0)ý1PWM_CMPDAT3_CMP0_Msk (0xfffful << PWM_CMPDAT3_CMP0_Pos)ÿ1PWM_CMPDAT3_CMP1_Pos (0)€2PWM_CMPDAT3_CMP1_Msk (0xfffful << PWM_CMPDAT3_CMP1_Pos)‚2PWM_CMPDAT3_CMP2_Pos (0)ƒ2PWM_CMPDAT3_CMP2_Msk (0xfffful << PWM_CMPDAT3_CMP2_Pos)…2PWM_CMPDAT3_CMP3_Pos (0)†2PWM_CMPDAT3_CMP3_Msk (0xfffful << PWM_CMPDAT3_CMP3_Pos)ˆ2PWM_CMPDAT3_CMP4_Pos (0)‰2PWM_CMPDAT3_CMP4_Msk (0xfffful << PWM_CMPDAT3_CMP4_Pos)‹2PWM_CMPDAT3_CMP5_Pos (0)Œ2PWM_CMPDAT3_CMP5_Msk (0xfffful << PWM_CMPDAT3_CMP5_Pos)Ž2PWM_CMPDAT3_CMP6_Pos (0)2PWM_CMPDAT3_CMP6_Msk (0xfffful << PWM_CMPDAT3_CMP6_Pos)‘2PWM_CMPDAT3_CMP7_Pos (0)’2PWM_CMPDAT3_CMP7_Msk (0xfffful << PWM_CMPDAT3_CMP7_Pos)”2PWM_CMPDAT3_CMPD0_Pos (16)•2PWM_CMPDAT3_CMPD0_Msk (0xfffful << PWM_CMPDAT3_CMPD0_Pos)—2PWM_CMPDAT3_CMPD1_Pos (16)˜2PWM_CMPDAT3_CMPD1_Msk (0xfffful << PWM_CMPDAT3_CMPD1_Pos)š2PWM_CMPDAT3_CMPD2_Pos (16)›2PWM_CMPDAT3_CMPD2_Msk (0xfffful << PWM_CMPDAT3_CMPD2_Pos)2PWM_CMPDAT3_CMPD3_Pos (16)ž2PWM_CMPDAT3_CMPD3_Msk (0xfffful << PWM_CMPDAT3_CMPD3_Pos) 2PWM_CMPDAT3_CMPD4_Pos (16)¡2PWM_CMPDAT3_CMPD4_Msk (0xfffful << PWM_CMPDAT3_CMPD4_Pos)£2PWM_CMPDAT3_CMPD5_Pos (16)¤2PWM_CMPDAT3_CMPD5_Msk (0xfffful << PWM_CMPDAT3_CMPD5_Pos)¦2PWM_CMPDAT3_CMPD6_Pos (16)§2PWM_CMPDAT3_CMPD6_Msk (0xfffful << PWM_CMPDAT3_CMPD4_Pos)©2PWM_CMPDAT3_CMPD7_Pos (16)ª2PWM_CMPDAT3_CMPD7_Msk (0xfffful << PWM_CMPDAT3_CMPD7_Pos)¬2PWM_CMPDAT4_CMP0_Pos (0)­2PWM_CMPDAT4_CMP0_Msk (0xfffful << PWM_CMPDAT4_CMP0_Pos)¯2PWM_CMPDAT4_CMP1_Pos (0)°2PWM_CMPDAT4_CMP1_Msk (0xfffful << PWM_CMPDAT4_CMP1_Pos)²2PWM_CMPDAT4_CMP2_Pos (0)³2PWM_CMPDAT4_CMP2_Msk (0xfffful << PWM_CMPDAT4_CMP2_Pos)µ2PWM_CMPDAT4_CMP3_Pos (0)¶2PWM_CMPDAT4_CMP3_Msk (0xfffful << PWM_CMPDAT4_CMP3_Pos)¸2PWM_CMPDAT4_CMP4_Pos (0)¹2PWM_CMPDAT4_CMP4_Msk (0xfffful << PWM_CMPDAT4_CMP4_Pos)»2PWM_CMPDAT4_CMP5_Pos (0)¼2PWM_CMPDAT4_CMP5_Msk (0xfffful << PWM_CMPDAT4_CMP5_Pos)¾2PWM_CMPDAT4_CMP6_Pos (0)¿2PWM_CMPDAT4_CMP6_Msk (0xfffful << PWM_CMPDAT4_CMP6_Pos)Á2PWM_CMPDAT4_CMP7_Pos (0)Â2PWM_CMPDAT4_CMP7_Msk (0xfffful << PWM_CMPDAT4_CMP7_Pos)Ä2PWM_CMPDAT4_CMPD0_Pos (16)Å2PWM_CMPDAT4_CMPD0_Msk (0xfffful << PWM_CMPDAT4_CMPD0_Pos)Ç2PWM_CMPDAT4_CMPD1_Pos (16)È2PWM_CMPDAT4_CMPD1_Msk (0xfffful << PWM_CMPDAT4_CMPD1_Pos)Ê2PWM_CMPDAT4_CMPD2_Pos (16)Ë2PWM_CMPDAT4_CMPD2_Msk (0xfffful << PWM_CMPDAT4_CMPD2_Pos)Í2PWM_CMPDAT4_CMPD3_Pos (16)Î2PWM_CMPDAT4_CMPD3_Msk (0xfffful << PWM_CMPDAT4_CMPD3_Pos)Ð2PWM_CMPDAT4_CMPD4_Pos (16)Ñ2PWM_CMPDAT4_CMPD4_Msk (0xfffful << PWM_CMPDAT4_CMPD4_Pos)Ó2PWM_CMPDAT4_CMPD5_Pos (16)Ô2PWM_CMPDAT4_CMPD5_Msk (0xfffful << PWM_CMPDAT4_CMPD5_Pos)Ö2PWM_CMPDAT4_CMPD6_Pos (16)×2PWM_CMPDAT4_CMPD6_Msk (0xfffful << PWM_CMPDAT4_CMPD6_Pos)Ù2PWM_CMPDAT4_CMPD7_Pos (16)Ú2PWM_CMPDAT4_CMPD7_Msk (0xfffful << PWM_CMPDAT4_CMPD7_Pos)Ü2PWM_CMPDAT5_CMP0_Pos (0)Ý2PWM_CMPDAT5_CMP0_Msk (0xfffful << PWM_CMPDAT5_CMP0_Pos)ß2PWM_CMPDAT5_CMP1_Pos (0)à2PWM_CMPDAT5_CMP1_Msk (0xfffful << PWM_CMPDAT5_CMP1_Pos)â2PWM_CMPDAT5_CMP2_Pos (0)ã2PWM_CMPDAT5_CMP2_Msk (0xfffful << PWM_CMPDAT5_CMP2_Pos)å2PWM_CMPDAT5_CMP3_Pos (0)æ2PWM_CMPDAT5_CMP3_Msk (0xfffful << PWM_CMPDAT5_CMP3_Pos)è2PWM_CMPDAT5_CMP4_Pos (0)é2PWM_CMPDAT5_CMP4_Msk (0xfffful << PWM_CMPDAT5_CMP4_Pos)ë2PWM_CMPDAT5_CMP5_Pos (0)ì2PWM_CMPDAT5_CMP5_Msk (0xfffful << PWM_CMPDAT5_CMP5_Pos)î2PWM_CMPDAT5_CMP6_Pos (0)ï2PWM_CMPDAT5_CMP6_Msk (0xfffful << PWM_CMPDAT5_CMP6_Pos)ñ2PWM_CMPDAT5_CMP7_Pos (0)ò2PWM_CMPDAT5_CMP7_Msk (0xfffful << PWM_CMPDAT5_CMP7_Pos)ô2PWM_CMPDAT5_CMPD0_Pos (16)õ2PWM_CMPDAT5_CMPD0_Msk (0xfffful << PWM_CMPDAT5_CMPD0_Pos)÷2PWM_CMPDAT5_CMPD1_Pos (16)ø2PWM_CMPDAT5_CMPD1_Msk (0xfffful << PWM_CMPDAT5_CMPD1_Pos)ú2PWM_CMPDAT5_CMPD2_Pos (16)û2PWM_CMPDAT5_CMPD2_Msk (0xfffful << PWM_CMPDAT5_CMPD2_Pos)ý2PWM_CMPDAT5_CMPD3_Pos (16)þ2PWM_CMPDAT5_CMPD3_Msk (0xfffful << PWM_CMPDAT5_CMPD3_Pos)€3PWM_CMPDAT5_CMPD4_Pos (16)3PWM_CMPDAT5_CMPD4_Msk (0xfffful << PWM_CMPDAT5_CMPD4_Pos)ƒ3PWM_CMPDAT5_CMPD5_Pos (16)„3PWM_CMPDAT5_CMPD5_Msk (0xfffful << PWM_CMPDAT5_CMPD5_Pos)†3PWM_CMPDAT5_CMPD6_Pos (16)‡3PWM_CMPDAT5_CMPD6_Msk (0xfffful << PWM_CMPDAT5_CMPD6_Pos)‰3PWM_CMPDAT5_CMPD7_Pos (16)Š3PWM_CMPDAT5_CMPD7_Msk (0xfffful << PWM_CMPDAT5_CMPD7_Pos)Œ3PWM_CMPDAT6_CMP0_Pos (0)3PWM_CMPDAT6_CMP0_Msk (0xfffful << PWM_CMPDAT6_CMP0_Pos)3PWM_CMPDAT6_CMP1_Pos (0)3PWM_CMPDAT6_CMP1_Msk (0xfffful << PWM_CMPDAT6_CMP1_Pos)’3PWM_CMPDAT6_CMP2_Pos (0)“3PWM_CMPDAT6_CMP2_Msk (0xfffful << PWM_CMPDAT6_CMP2_Pos)•3PWM_CMPDAT6_CMP3_Pos (0)–3PWM_CMPDAT6_CMP3_Msk (0xfffful << PWM_CMPDAT6_CMP3_Pos)˜3PWM_CMPDAT6_CMP4_Pos (0)™3PWM_CMPDAT6_CMP4_Msk (0xfffful << PWM_CMPDAT6_CMP4_Pos)›3PWM_CMPDAT6_CMP5_Pos (0)œ3PWM_CMPDAT6_CMP5_Msk (0xfffful << PWM_CMPDAT6_CMP5_Pos)ž3PWM_CMPDAT6_CMP6_Pos (0)Ÿ3PWM_CMPDAT6_CMP6_Msk (0xfffful << PWM_CMPDAT6_CMP6_Pos)¡3PWM_CMPDAT6_CMP7_Pos (0)¢3PWM_CMPDAT6_CMP7_Msk (0xfffful << PWM_CMPDAT6_CMP7_Pos)¤3PWM_CMPDAT6_CMPD0_Pos (16)¥3PWM_CMPDAT6_CMPD0_Msk (0xfffful << PWM_CMPDAT6_CMPD0_Pos)§3PWM_CMPDAT6_CMPD1_Pos (16)¨3PWM_CMPDAT6_CMPD1_Msk (0xfffful << PWM_CMPDAT6_CMPD1_Pos)ª3PWM_CMPDAT6_CMPD2_Pos (16)«3PWM_CMPDAT6_CMPD2_Msk (0xfffful << PWM_CMPDAT6_CMPD2_Pos)­3PWM_CMPDAT6_CMPD3_Pos (16)®3PWM_CMPDAT6_CMPD3_Msk (0xfffful << PWM_CMPDAT6_CMPD3_Pos)°3PWM_CMPDAT6_CMPD4_Pos (16)±3PWM_CMPDAT6_CMPD4_Msk (0xfffful << PWM_CMPDAT6_CMPD4_Pos)³3PWM_CMPDAT6_CMPD5_Pos (16)´3PWM_CMPDAT6_CMPD5_Msk (0xfffful << PWM_CMPDAT6_CMPD5_Pos)¶3PWM_CMPDAT6_CMPD6_Pos (16)·3PWM_CMPDAT6_CMPD6_Msk (0xfffful << PWM_CMPDAT6_CMPD6_Pos)¹3PWM_CMPDAT6_CMPD7_Pos (16)º3PWM_CMPDAT6_CMPD7_Msk (0xfffful << PWM_CMPDAT6_CMPD7_Pos)¼3PWM_CMPDAT7_CMP0_Pos (0)½3PWM_CMPDAT7_CMP0_Msk (0xfffful << PWM_CMPDAT7_CMP0_Pos)¿3PWM_CMPDAT7_CMP1_Pos (0)À3PWM_CMPDAT7_CMP1_Msk (0xfffful << PWM_CMPDAT7_CMP1_Pos)Â3PWM_CMPDAT7_CMP2_Pos (0)Ã3PWM_CMPDAT7_CMP2_Msk (0xfffful << PWM_CMPDAT7_CMP2_Pos)Å3PWM_CMPDAT7_CMP3_Pos (0)Æ3PWM_CMPDAT7_CMP3_Msk (0xfffful << PWM_CMPDAT7_CMP3_Pos)È3PWM_CMPDAT7_CMP4_Pos (0)É3PWM_CMPDAT7_CMP4_Msk (0xfffful << PWM_CMPDAT7_CMP4_Pos)Ë3PWM_CMPDAT7_CMP5_Pos (0)Ì3PWM_CMPDAT7_CMP5_Msk (0xfffful << PWM_CMPDAT7_CMP5_Pos)Î3PWM_CMPDAT7_CMP6_Pos (0)Ï3PWM_CMPDAT7_CMP6_Msk (0xfffful << PWM_CMPDAT7_CMP6_Pos)Ñ3PWM_CMPDAT7_CMP7_Pos (0)Ò3PWM_CMPDAT7_CMP7_Msk (0xfffful << PWM_CMPDAT7_CMP7_Pos)Ô3PWM_CMPDAT7_CMPD0_Pos (16)Õ3PWM_CMPDAT7_CMPD0_Msk (0xfffful << PWM_CMPDAT7_CMPD0_Pos)×3PWM_CMPDAT7_CMPD1_Pos (16)Ø3PWM_CMPDAT7_CMPD1_Msk (0xfffful << PWM_CMPDAT7_CMPD1_Pos)Ú3PWM_CMPDAT7_CMPD2_Pos (16)Û3PWM_CMPDAT7_CMPD2_Msk (0xfffful << PWM_CMPDAT7_CMPD2_Pos)Ý3PWM_CMPDAT7_CMPD3_Pos (16)Þ3PWM_CMPDAT7_CMPD3_Msk (0xfffful << PWM_CMPDAT7_CMPD3_Pos)à3PWM_CMPDAT7_CMPD4_Pos (16)á3PWM_CMPDAT7_CMPD4_Msk (0xfffful << PWM_CMPDAT7_CMPD4_Pos)ã3PWM_CMPDAT7_CMPD5_Pos (16)ä3PWM_CMPDAT7_CMPD5_Msk (0xfffful << PWM_CMPDAT7_CMPD5_Pos)æ3PWM_CMPDAT7_CMPD6_Pos (16)ç3PWM_CMPDAT7_CMPD6_Msk (0xfffful << PWM_CMPDAT7_CMPD6_Pos)é3PWM_CMPDAT7_CMPD7_Pos (16)ê3PWM_CMPDAT7_CMPD7_Msk (0xfffful << PWM_CMPDAT7_CMPD7_Pos)ì3PWM_CTL2_BRKIEN_Pos (16)í3PWM_CTL2_BRKIEN_Msk (0x1ul << PWM_CTL2_BRKIEN_Pos)ï3PWM_CTL2_PINTTYPE_Pos (17)ð3PWM_CTL2_PINTTYPE_Msk (0x1ul << PWM_CTL2_PINTTYPE_Pos)ò3PWM_CTL2_DTCNT01_Pos (24)ó3PWM_CTL2_DTCNT01_Msk (0x1ul << PWM_CTL2_DTCNT01_Pos)õ3PWM_CTL2_DTCNT23_Pos (25)ö3PWM_CTL2_DTCNT23_Msk (0x1ul << PWM_CTL2_DTCNT23_Pos)ø3PWM_CTL2_DTCNT45_Pos (26)ù3PWM_CTL2_DTCNT45_Msk (0x1ul << PWM_CTL2_DTCNT45_Pos)û3PWM_CTL2_DTCNT67_Pos (27)ü3PWM_CTL2_DTCNT67_Msk (0x1ul << PWM_CTL2_DTCNT67_Pos)þ3PWM_CTL2_CNTCLR_Pos (27)ÿ3PWM_CTL2_CNTCLR_Msk (0x1ul << PWM_CTL2_CNTCLR_Pos)4PWM_CTL2_MODE_Pos (28)‚4PWM_CTL2_MODE_Msk (0x3ul << PWM_CTL2_MODE_Pos)„4PWM_CTL2_GROUPEN_Pos (30)…4PWM_CTL2_GROUPEN_Msk (0x1ul << PWM_CTL2_GROUPEN_Pos)‡4PWM_CTL2_CNTTYPE_Pos (31)ˆ4PWM_CTL2_CNTTYPE_Msk (0x1ul << PWM_CTL2_CNTTYPE_Pos)Š4PWM_FLAG_ZF0_Pos (0)‹4PWM_FLAG_ZF0_Msk (0x1ul << PWM_FLAG_ZF0_Pos)4PWM_FLAG_ZF1_Pos (1)Ž4PWM_FLAG_ZF1_Msk (0x1ul << PWM_FLAG_ZF1_Pos)4PWM_FLAG_ZF2_Pos (2)‘4PWM_FLAG_ZF2_Msk (0x1ul << PWM_FLAG_ZF2_Pos)“4PWM_FLAG_ZF3_Pos (3)”4PWM_FLAG_ZF3_Msk (0x1ul << PWM_FLAG_ZF3_Pos)–4PWM_FLAG_ZF4_Pos (4)—4PWM_FLAG_ZF4_Msk (0x1ul << PWM_FLAG_ZF4_Pos)™4PWM_FLAG_ZF5_Pos (5)š4PWM_FLAG_ZF5_Msk (0x1ul << PWM_FLAG_ZF5_Pos)œ4PWM_FLAG_ZF6_Pos (6)4PWM_FLAG_ZF6_Msk (0x1ul << PWM_FLAG_ZF6_Pos)Ÿ4PWM_FLAG_ZF7_Pos (7) 4PWM_FLAG_ZF7_Msk (0x1ul << PWM_FLAG_ZF7_Pos)¢4PWM_FLAG_CMPDF0_Pos (8)£4PWM_FLAG_CMPDF0_Msk (0x1ul << PWM_FLAG_CMPDF0_Pos)¥4PWM_FLAG_CMPDF1_Pos (9)¦4PWM_FLAG_CMPDF1_Msk (0x1ul << PWM_FLAG_CMPDF1_Pos)¨4PWM_FLAG_CMPDF2_Pos (10)©4PWM_FLAG_CMPDF2_Msk (0x1ul << PWM_FLAG_CMPDF2_Pos)«4PWM_FLAG_CMPDF3_Pos (11)¬4PWM_FLAG_CMPDF3_Msk (0x1ul << PWM_FLAG_CMPDF3_Pos)®4PWM_FLAG_CMPDF4_Pos (12)¯4PWM_FLAG_CMPDF4_Msk (0x1ul << PWM_FLAG_CMPDF4_Pos)±4PWM_FLAG_CMPDF5_Pos (13)²4PWM_FLAG_CMPDF5_Msk (0x1ul << PWM_FLAG_CMPDF5_Pos)´4PWM_FLAG_CMPDF6_Pos (14)µ4PWM_FLAG_CMPDF6_Msk (0x1ul << PWM_FLAG_CMPDF6_Pos)·4PWM_FLAG_CMPDF7_Pos (15)¸4PWM_FLAG_CMPDF7_Msk (0x1ul << PWM_FLAG_CMPDF7_Pos)º4PWM_FLAG_PF0_Pos (16)»4PWM_FLAG_PF0_Msk (0x1ul << PWM_FLAG_PF0_Pos)½4PWM_FLAG_PF1_Pos (17)¾4PWM_FLAG_PF1_Msk (0x1ul << PWM_FLAG_PF1_Pos)À4PWM_FLAG_PF2_Pos (18)Á4PWM_FLAG_PF2_Msk (0x1ul << PWM_FLAG_PF2_Pos)Ã4PWM_FLAG_PF3_Pos (19)Ä4PWM_FLAG_PF3_Msk (0x1ul << PWM_FLAG_PF3_Pos)Æ4PWM_FLAG_PF4_Pos (20)Ç4PWM_FLAG_PF4_Msk (0x1ul << PWM_FLAG_PF4_Pos)É4PWM_FLAG_PF5_Pos (21)Ê4PWM_FLAG_PF5_Msk (0x1ul << PWM_FLAG_PF5_Pos)Ì4PWM_FLAG_PF6_Pos (22)Í4PWM_FLAG_PF6_Msk (0x1ul << PWM_FLAG_PF6_Pos)Ï4PWM_FLAG_PF7_Pos (23)Ð4PWM_FLAG_PF7_Msk (0x1ul << PWM_FLAG_PF7_Pos)Ò4PWM_FLAG_CMPUF0_Pos (24)Ó4PWM_FLAG_CMPUF0_Msk (0x1ul << PWM_FLAG_CMPUF0_Pos)Õ4PWM_FLAG_CMPUF1_Pos (25)Ö4PWM_FLAG_CMPUF1_Msk (0x1ul << PWM_FLAG_CMPUF1_Pos)Ø4PWM_FLAG_CMPUF2_Pos (26)Ù4PWM_FLAG_CMPUF2_Msk (0x1ul << PWM_FLAG_CMPUF2_Pos)Û4PWM_FLAG_CMPUF3_Pos (27)Ü4PWM_FLAG_CMPUF3_Msk (0x1ul << PWM_FLAG_CMPUF3_Pos)Þ4PWM_FLAG_CMPUF4_Pos (28)ß4PWM_FLAG_CMPUF4_Msk (0x1ul << PWM_FLAG_CMPUF4_Pos)á4PWM_FLAG_CMPUF5_Pos (29)â4PWM_FLAG_CMPUF5_Msk (0x1ul << PWM_FLAG_CMPUF5_Pos)ä4PWM_FLAG_CMPUF6_Pos (30)å4PWM_FLAG_CMPUF6_Msk (0x1ul << PWM_FLAG_CMPUF6_Pos)ç4PWM_FLAG_CMPUF7_Pos (31)è4PWM_FLAG_CMPUF7_Msk (0x1ul << PWM_FLAG_CMPUF7_Pos)ê4PWM_INTEN_ZIEN0_Pos (0)ë4PWM_INTEN_ZIEN0_Msk (0x1ul << PWM_INTEN_ZIEN0_Pos)í4PWM_INTEN_ZIEN1_Pos (1)î4PWM_INTEN_ZIEN1_Msk (0x1ul << PWM_INTEN_ZIEN1_Pos)ð4PWM_INTEN_ZIEN2_Pos (2)ñ4PWM_INTEN_ZIEN2_Msk (0x1ul << PWM_INTEN_ZIEN2_Pos)ó4PWM_INTEN_ZIEN3_Pos (3)ô4PWM_INTEN_ZIEN3_Msk (0x1ul << PWM_INTEN_ZIEN3_Pos)ö4PWM_INTEN_ZIEN4_Pos (4)÷4PWM_INTEN_ZIEN4_Msk (0x1ul << PWM_INTEN_ZIEN4_Pos)ù4PWM_INTEN_ZIEN5_Pos (5)ú4PWM_INTEN_ZIEN5_Msk (0x1ul << PWM_INTEN_ZIEN5_Pos)ý4PWM_INTEN_ZIEN6_Pos (6)þ4PWM_INTEN_ZIEN6_Msk (0x1ul << PWM_INTEN_ZIEN6_Pos)5PWM_INTEN_ZIEN7_Pos (7)‚5PWM_INTEN_ZIEN7_Msk (0x1ul << PWM_INTEN_ZIEN7_Pos)„5PWM_INTEN_CMPDIEN0_Pos (8)…5PWM_INTEN_CMPDIEN0_Msk (0x1ul << PWM_INTEN_CMPDIEN0_Pos)‡5PWM_INTEN_CMPDIEN1_Pos (9)ˆ5PWM_INTEN_CMPDIEN1_Msk (0x1ul << PWM_INTEN_CMPDIEN1_Pos)Š5PWM_INTEN_CMPDIEN2_Pos (10)‹5PWM_INTEN_CMPDIEN2_Msk (0x1ul << PWM_INTEN_CMPDIEN2_Pos)5PWM_INTEN_CMPDIEN3_Pos (11)Ž5PWM_INTEN_CMPDIEN3_Msk (0x1ul << PWM_INTEN_CMPDIEN3_Pos)5PWM_INTEN_CMPDIEN4_Pos (12)‘5PWM_INTEN_CMPDIEN4_Msk (0x1ul << PWM_INTEN_CMPDIEN4_Pos)“5PWM_INTEN_CMPDIEN5_Pos (13)”5PWM_INTEN_CMPDIEN5_Msk (0x1ul << PWM_INTEN_CMPDIEN5_Pos)—5PWM_INTEN_CMPDIEN6_Pos (14)˜5PWM_INTEN_CMPDIEN6_Msk (0x1ul << PWM_INTEN_CMPDIEN6_Pos)š5PWM_INTEN_CMPDIEN7_Pos (15)›5PWM_INTEN_CMPDIEN7_Msk (0x1ul << PWM_INTEN_CMPDIEN7_Pos)5PWM_INTEN_PIEN0_Pos (16)ž5PWM_INTEN_PIEN0_Msk (0x1ul << PWM_INTEN_PIEN0_Pos) 5PWM_INTEN_PIEN1_Pos (17)¡5PWM_INTEN_PIEN1_Msk (0x1ul << PWM_INTEN_PIEN1_Pos)£5PWM_INTEN_PIEN2_Pos (18)¤5PWM_INTEN_PIEN2_Msk (0x1ul << PWM_INTEN_PIEN2_Pos)¦5PWM_INTEN_PIEN3_Pos (19)§5PWM_INTEN_PIEN3_Msk (0x1ul << PWM_INTEN_PIEN3_Pos)©5PWM_INTEN_PIEN4_Pos (20)ª5PWM_INTEN_PIEN4_Msk (0x1ul << PWM_INTEN_PIEN4_Pos)¬5PWM_INTEN_PIEN5_Pos (21)­5PWM_INTEN_PIEN5_Msk (0x1ul << PWM_INTEN_PIEN5_Pos)°5PWM_INTEN_PIEN6_Pos (22)±5PWM_INTEN_PIEN6_Msk (0x1ul << PWM_INTEN_PIEN6_Pos)´5PWM_INTEN_PIEN7_Pos (23)µ5PWM_INTEN_PIEN7_Msk (0x1ul << PWM_INTEN_PIEN7_Pos)·5PWM_INTEN_CMPUIEN0_Pos (24)¸5PWM_INTEN_CMPUIEN0_Msk (0x1ul << PWM_INTEN_CMPUIEN0_Pos)º5PWM_INTEN_CMPUIEN1_Pos (25)»5PWM_INTEN_CMPUIEN1_Msk (0x1ul << PWM_INTEN_CMPUIEN1_Pos)½5PWM_INTEN_CMPUIEN2_Pos (26)¾5PWM_INTEN_CMPUIEN2_Msk (0x1ul << PWM_INTEN_CMPUIEN2_Pos)À5PWM_INTEN_CMPUIEN3_Pos (27)Á5PWM_INTEN_CMPUIEN3_Msk (0x1ul << PWM_INTEN_CMPUIEN3_Pos)Ã5PWM_INTEN_CMPUIEN4_Pos (28)Ä5PWM_INTEN_CMPUIEN4_Msk (0x1ul << PWM_INTEN_CMPUIEN4_Pos)Æ5PWM_INTEN_CMPUIEN5_Pos (29)Ç5PWM_INTEN_CMPUIEN5_Msk (0x1ul << PWM_INTEN_CMPUIEN5_Pos)É5PWM_INTEN_CMPUIEN6_Pos (30)Ê5PWM_INTEN_CMPUIEN6_Msk (0x1ul << PWM_INTEN_CMPUIEN6_Pos)Ì5PWM_INTEN_CMPUIEN7_Pos (31)Í5PWM_INTEN_CMPUIEN7_Msk (0x1ul << PWM_INTEN_CMPUIEN7_Pos)Ï5PWM_INTSTS_ZIF0_Pos (0)Ð5PWM_INTSTS_ZIF0_Msk (0x1ul << PWM_INTSTS_ZIF0_Pos)Ò5PWM_INTSTS_ZIF1_Pos (1)Ó5PWM_INTSTS_ZIF1_Msk (0x1ul << PWM_INTSTS_ZIF1_Pos)Õ5PWM_INTSTS_ZIF2_Pos (2)Ö5PWM_INTSTS_ZIF2_Msk (0x1ul << PWM_INTSTS_ZIF2_Pos)Ø5PWM_INTSTS_ZIF3_Pos (3)Ù5PWM_INTSTS_ZIF3_Msk (0x1ul << PWM_INTSTS_ZIF3_Pos)Û5PWM_INTSTS_ZIF4_Pos (4)Ü5PWM_INTSTS_ZIF4_Msk (0x1ul << PWM_INTSTS_ZIF4_Pos)Þ5PWM_INTSTS_ZIF5_Pos (5)ß5PWM_INTSTS_ZIF5_Msk (0x1ul << PWM_INTSTS_ZIF5_Pos)á5PWM_INTSTS_ZIF6_Pos (6)â5PWM_INTSTS_ZIF6_Msk (0x1ul << PWM_INTSTS_ZIF6_Pos)ä5PWM_INTSTS_ZIF7_Pos (7)å5PWM_INTSTS_ZIF7_Msk (0x1ul << PWM_INTSTS_ZIF7_Pos)ç5PWM_INTSTS_CMPDIF0_Pos (8)è5PWM_INTSTS_CMPDIF0_Msk (0x1ul << PWM_INTSTS_CMPDIF0_Pos)ê5PWM_INTSTS_CMPDIF1_Pos (9)ë5PWM_INTSTS_CMPDIF1_Msk (0x1ul << PWM_INTSTS_CMPDIF1_Pos)í5PWM_INTSTS_CMPDIF2_Pos (10)î5PWM_INTSTS_CMPDIF2_Msk (0x1ul << PWM_INTSTS_CMPDIF2_Pos)ð5PWM_INTSTS_CMPDIF3_Pos (11)ñ5PWM_INTSTS_CMPDIF3_Msk (0x1ul << PWM_INTSTS_CMPDIF3_Pos)ó5PWM_INTSTS_CMPDIF4_Pos (12)ô5PWM_INTSTS_CMPDIF4_Msk (0x1ul << PWM_INTSTS_CMPDIF4_Pos)ö5PWM_INTSTS_CMPDIF5_Pos (13)÷5PWM_INTSTS_CMPDIF5_Msk (0x1ul << PWM_INTSTS_CMPDIF5_Pos)ù5PWM_INTSTS_CMPDIF6_Pos (14)ú5PWM_INTSTS_CMPDIF6_Msk (0x1ul << PWM_INTSTS_CMPDIF6_Pos)ü5PWM_INTSTS_CMPDIF7_Pos (15)ý5PWM_INTSTS_CMPDIF7_Msk (0x1ul << PWM_INTSTS_CMPDIF7_Pos)ÿ5PWM_INTSTS_PIF0_Pos (16)€6PWM_INTSTS_PIF0_Msk (0x1ul << PWM_INTSTS_PIF0_Pos)‚6PWM_INTSTS_PIF1_Pos (17)ƒ6PWM_INTSTS_PIF1_Msk (0x1ul << PWM_INTSTS_PIF1_Pos)…6PWM_INTSTS_PIF2_Pos (18)†6PWM_INTSTS_PIF2_Msk (0x1ul << PWM_INTSTS_PIF2_Pos)ˆ6PWM_INTSTS_PIF3_Pos (19)‰6PWM_INTSTS_PIF3_Msk (0x1ul << PWM_INTSTS_PIF3_Pos)‹6PWM_INTSTS_PIF4_Pos (20)Œ6PWM_INTSTS_PIF4_Msk (0x1ul << PWM_INTSTS_PIF4_Pos)Ž6PWM_INTSTS_PIF5_Pos (21)6PWM_INTSTS_PIF5_Msk (0x1ul << PWM_INTSTS_PIF5_Pos)‘6PWM_INTSTS_PIF6_Pos (22)’6PWM_INTSTS_PIF6_Msk (0x1ul << PWM_INTSTS_PIF6_Pos)”6PWM_INTSTS_PIF7_Pos (23)•6PWM_INTSTS_PIF7_Msk (0x1ul << PWM_INTSTS_PIF7_Pos)—6PWM_INTSTS_CMPUIF0_Pos (24)˜6PWM_INTSTS_CMPUIF0_Msk (0x1ul << PWM_INTSTS_CMPUIF0_Pos)š6PWM_INTSTS_CMPUIF1_Pos (25)›6PWM_INTSTS_CMPUIF1_Msk (0x1ul << PWM_INTSTS_CMPUIF1_Pos)6PWM_INTSTS_CMPUIF2_Pos (26)ž6PWM_INTSTS_CMPUIF2_Msk (0x1ul << PWM_INTSTS_CMPUIF2_Pos) 6PWM_INTSTS_CMPUIF3_Pos (27)¡6PWM_INTSTS_CMPUIF3_Msk (0x1ul << PWM_INTSTS_CMPUIF3_Pos)£6PWM_INTSTS_CMPUIF4_Pos (28)¤6PWM_INTSTS_CMPUIF4_Msk (0x1ul << PWM_INTSTS_CMPUIF4_Pos)¦6PWM_INTSTS_CMPUIF5_Pos (29)§6PWM_INTSTS_CMPUIF5_Msk (0x1ul << PWM_INTSTS_CMPUIF5_Pos)©6PWM_INTSTS_CMPUIF6_Pos (30)ª6PWM_INTSTS_CMPUIF6_Msk (0x1ul << PWM_INTSTS_CMPUIF6_Pos)¬6PWM_INTSTS_CMPUIF7_Pos (31)­6PWM_INTSTS_CMPUIF7_Msk (0x1ul << PWM_INTSTS_CMPUIF7_Pos)¯6PWM_POEN_POEN0_Pos (0)°6PWM_POEN_POEN0_Msk (0x1ul << PWM_POEN_POEN0_Pos)²6PWM_POEN_POEN1_Pos (1)³6PWM_POEN_POEN1_Msk (0x1ul << PWM_POEN_POEN1_Pos)µ6PWM_POEN_POEN2_Pos (2)¶6PWM_POEN_POEN2_Msk (0x1ul << PWM_POEN_POEN2_Pos)¸6PWM_POEN_POEN3_Pos (3)¹6PWM_POEN_POEN3_Msk (0x1ul << PWM_POEN_POEN3_Pos)»6PWM_POEN_POEN4_Pos (4)¼6PWM_POEN_POEN4_Msk (0x1ul << PWM_POEN_POEN4_Pos)¾6PWM_POEN_POEN5_Pos (5)¿6PWM_POEN_POEN5_Msk (0x1ul << PWM_POEN_POEN5_Pos)Á6PWM_POEN_POEN6_Pos (6)Â6PWM_POEN_POEN6_Msk (0x1ul << PWM_POEN_POEN4_Pos)Ä6PWM_POEN_POEN7_Pos (7)Å6PWM_POEN_POEN7_Msk (0x1ul << PWM_POEN_POEN7_Pos)Ç6PWM_BRKCTL_BRK0EN_Pos (0)È6PWM_BRKCTL_BRK0EN_Msk (0x1ul << PWM_BRKCTL_BRK0EN_Pos)Ê6PWM_BRKCTL_BRK1EN_Pos (1)Ë6PWM_BRKCTL_BRK1EN_Msk (0x1ul << PWM_BRKCTL_BRK1EN_Pos)Í6PWM_BRKCTL_BRK0SEL_Pos (2)Î6PWM_BRKCTL_BRK0SEL_Msk (0x1ul << PWM_BRKCTL_BRK0SEL_Pos)Ð6PWM_BRKCTL_BRK1SEL_Pos (3)Ñ6PWM_BRKCTL_BRK1SEL_Msk (0x1ul << PWM_BRKCTL_BRK1SEL_Pos)Ó6PWM_BRKCTL_BRKSTS_Pos (7)Ô6PWM_BRKCTL_BRKSTS_Msk (0x1ul << PWM_BRKCTL_BRKSTS_Pos)Ö6PWM_BRKCTL_BRKACT_Pos (8)×6PWM_BRKCTL_BRKACT_Msk (0x1ul << PWM_BRKCTL_BRKACT_Pos)Ù6PWM_BRKCTL_SWBRK_Pos (9)Ú6PWM_BRKCTL_SWBRK_Msk (0x1ul << PWM_BRKCTL_SWBRK_Pos)Ü6PWM_BRKCTL_BRKIF0_Pos (16)Ý6PWM_BRKCTL_BRKIF0_Msk (0x1ul << PWM_BRKCTL_BRKIF0_Pos)ß6PWM_BRKCTL_BRKIF1_Pos (17)à6PWM_BRKCTL_BRKIF1_Msk (0x1ul << PWM_BRKCTL_BRKIF1_Pos)â6PWM_BRKCTL_BRKF0_Pos (18)ã6PWM_BRKCTL_BRKF0_Msk (0x1ul << PWM_BRKCTL_BRKF0_Pos)å6PWM_BRKCTL_BRKF1_Pos (19)æ6PWM_BRKCTL_BRKF1_Msk (0x1ul << PWM_BRKCTL_BRKF1_Pos)è6PWM_BRKCTL_BKOD0_Pos (24)é6PWM_BRKCTL_BKOD0_Msk (0x1ul << PWM_BRKCTL_BKOD0_Pos)ë6PWM_BRKCTL_BKOD1_Pos (25)ì6PWM_BRKCTL_BKOD1_Msk (0x1ul << PWM_BRKCTL_BKOD1_Pos)î6PWM_BRKCTL_BKOD2_Pos (26)ï6PWM_BRKCTL_BKOD2_Msk (0x1ul << PWM_BRKCTL_BKOD2_Pos)ñ6PWM_BRKCTL_BKOD3_Pos (27)ò6PWM_BRKCTL_BKOD3_Msk (0x1ul << PWM_BRKCTL_BKOD3_Pos)ô6PWM_BRKCTL_BKOD4_Pos (28)õ6PWM_BRKCTL_BKOD4_Msk (0x1ul << PWM_BRKCTL_BKOD4_Pos)÷6PWM_BRKCTL_BKOD5_Pos (29)ø6PWM_BRKCTL_BKOD5_Msk (0x1ul << PWM_BRKCTL_BKOD5_Pos)ú6PWM_BRKCTL_D6BKOD_Pos (30)û6PWM_BRKCTL_D6BKOD_Msk (0x1ul << PWM_BRKCTL_D6BKOD_Pos)ý6PWM_BRKCTL_D7BKOD_Pos (31)þ6PWM_BRKCTL_D7BKOD_Msk (0x1ul << PWM_BRKCTL_D7BKOD_Pos)€7PWM_DTCTL_DTI01_Pos (0)7PWM_DTCTL_DTI01_Msk (0xfful << PWM_DTCTL_DTI01_Pos)ƒ7PWM_DTCTL_DTI23_Pos (8)„7PWM_DTCTL_DTI23_Msk (0xfful << PWM_DTCTL_DTI23_Pos)†7PWM_DTCTL_DTI45_Pos (16)‡7PWM_DTCTL_DTI45_Msk (0xfful << PWM_DTCTL_DTI45_Pos)‰7PWM_DTCTL_DTI67_Pos (24)Š7PWM_DTCTL_DTI67_Msk (0xfful << PWM_DTCTL_DTI67_Pos)Œ7PWM_ADCTCTL0_CUTRGEN0_Pos (0)7PWM_ADCTCTL0_CUTRGEN0_Msk (0x1ul << PWM_ADCTCTL0_CUTRGEN0_Pos)7PWM_ADCTCTL0_CPTRGEN0_Pos (1)7PWM_ADCTCTL0_CPTRGEN0_Msk (0x1ul << PWM_ADCTCTL0_CPTRGEN0_Pos)’7PWM_ADCTCTL0_CDTRGEN0_Pos (2)“7PWM_ADCTCTL0_CDTRGEN0_Msk (0x1ul << PWM_ADCTCTL0_CDTRGEN0_Pos)•7PWM_ADCTCTL0_ZPTRGEN0_Pos (3)–7PWM_ADCTCTL0_ZPTRGEN0_Msk (0x1ul << PWM_ADCTCTL0_ZPTRGEN0_Pos)˜7PWM_ADCTCTL0_CUTRGEN1_Pos (8)™7PWM_ADCTCTL0_CUTRGEN1_Msk (0x1ul << PWM_ADCTCTL0_CUTRGEN1_Pos)›7PWM_ADCTCTL0_CPTRGEN1_Pos (9)œ7PWM_ADCTCTL0_CPTRGEN1_Msk (0x1ul << PWM_ADCTCTL0_CPTRGEN1_Pos)ž7PWM_ADCTCTL0_CDTRGEN1_Pos (10)Ÿ7PWM_ADCTCTL0_CDTRGEN1_Msk (0x1ul << PWM_ADCTCTL0_CDTRGEN1_Pos)¡7PWM_ADCTCTL0_ZPTRGEN1_Pos (11)¢7PWM_ADCTCTL0_ZPTRGEN1_Msk (0x1ul << PWM_ADCTCTL0_ZPTRGEN1_Pos)¤7PWM_ADCTCTL0_CUTRGEN2_Pos (16)¥7PWM_ADCTCTL0_CUTRGEN2_Msk (0x1ul << PWM_ADCTCTL0_CUTRGEN2_Pos)§7PWM_ADCTCTL0_CPTRGEN2_Pos (17)¨7PWM_ADCTCTL0_CPTRGEN2_Msk (0x1ul << PWM_ADCTCTL0_CPTRGEN2_Pos)ª7PWM_ADCTCTL0_CDTRGEN2_Pos (18)«7PWM_ADCTCTL0_CDTRGEN2_Msk (0x1ul << PWM_ADCTCTL0_CDTRGEN2_Pos)­7PWM_ADCTCTL0_ZPTRGEN2_Pos (19)®7PWM_ADCTCTL0_ZPTRGEN2_Msk (0x1ul << PWM_ADCTCTL0_ZPTRGEN2_Pos)°7PWM_ADCTCTL0_CUTRGEN3_Pos (24)±7PWM_ADCTCTL0_CUTRGEN3_Msk (0x1ul << PWM_ADCTCTL0_CUTRGEN3_Pos)³7PWM_ADCTCTL0_CPTRGEN3_Pos (25)´7PWM_ADCTCTL0_CPTRGEN3_Msk (0x1ul << PWM_ADCTCTL0_CPTRGEN3_Pos)¶7PWM_ADCTCTL0_CDTRGEN3_Pos (26)·7PWM_ADCTCTL0_CDTRGEN3_Msk (0x1ul << PWM_ADCTCTL0_CDTRGEN3_Pos)¹7PWM_ADCTCTL0_ZPTRGEN3_Pos (27)º7PWM_ADCTCTL0_ZPTRGEN3_Msk (0x1ul << PWM_ADCTCTL0_ZPTRGEN3_Pos)¼7PWM_ADCTCTL1_CUTRGEN4_Pos (0)½7PWM_ADCTCTL1_CUTRGEN4_Msk (0x1ul << PWM_ADCTCTL1_CUTRGEN4_Pos)¿7PWM_ADCTCTL1_CPTRGEN4_Pos (1)À7PWM_ADCTCTL1_CPTRGEN4_Msk (0x1ul << PWM_ADCTCTL1_CPTRGEN4_Pos)Â7PWM_ADCTCTL1_CDTRGEN4_Pos (2)Ã7PWM_ADCTCTL1_CDTRGEN4_Msk (0x1ul << PWM_ADCTCTL1_CDTRGEN4_Pos)Å7PWM_ADCTCTL1_ZPTRGEN4_Pos (3)Æ7PWM_ADCTCTL1_ZPTRGEN4_Msk (0x1ul << PWM_ADCTCTL1_ZPTRGEN4_Pos)È7PWM_ADCTCTL1_CUTRGEN5_Pos (8)É7PWM_ADCTCTL1_CUTRGEN5_Msk (0x1ul << PWM_ADCTCTL1_CUTRGEN5_Pos)Ë7PWM_ADCTCTL1_CPTRGEN5_Pos (9)Ì7PWM_ADCTCTL1_CPTRGEN5_Msk (0x1ul << PWM_ADCTCTL1_CPTRGEN5_Pos)Î7PWM_ADCTCTL1_CDTRGEN5_Pos (10)Ï7PWM_ADCTCTL1_CDTRGEN5_Msk (0x1ul << PWM_ADCTCTL1_CDTRGEN5_Pos)Ñ7PWM_ADCTCTL1_ZPTRGEN5_Pos (11)Ò7PWM_ADCTCTL1_ZPTRGEN5_Msk (0x1ul << PWM_ADCTCTL1_ZPTRGEN5_Pos)Ô7PWM_ADCTCTL1_CUTRGEN6_Pos (16)Õ7PWM_ADCTCTL1_CUTRGEN6_Msk (0x1ul << PWM_ADCTCTL1_CUTRGEN2_Pos)×7PWM_ADCTCTL1_CPTRGEN6_Pos (17)Ø7PWM_ADCTCTL1_CPTRGEN6_Msk (0x1ul << PWM_ADCTCTL1_CPTRGEN2_Pos)Ú7PWM_ADCTCTL1_CDTRGEN6_Pos (18)Û7PWM_ADCTCTL1_CDTRGEN6_Msk (0x1ul << PWM_ADCTCTL1_CDTRGEN2_Pos)Ý7PWM_ADCTCTL1_ZPTRGEN6_Pos (19)Þ7PWM_ADCTCTL1_ZPTRGEN6_Msk (0x1ul << PWM_ADCTCTL1_ZPTRGEN2_Pos)à7PWM_ADCTCTL1_CUTRGEN7_Pos (24)á7PWM_ADCTCTL1_CUTRGEN7_Msk (0x1ul << PWM_ADCTCTL1_CUTRGEN7_Pos)ã7PWM_ADCTCTL1_CPTRGEN7_Pos (25)ä7PWM_ADCTCTL1_CPTRGEN7_Msk (0x1ul << PWM_ADCTCTL1_CPTRGEN7_Pos)æ7PWM_ADCTCTL1_CDTRGEN7_Pos (26)ç7PWM_ADCTCTL1_CDTRGEN7_Msk (0x1ul << PWM_ADCTCTL1_CDTRGEN7_Pos)é7PWM_ADCTCTL1_ZPTRGEN7_Pos (27)ê7PWM_ADCTCTL1_ZPTRGEN7_Msk (0x1ul << PWM_ADCTCTL1_ZPTRGEN7_Pos)ì7PWM_ADCTSTS0_CUTRGF0_Pos (0)í7PWM_ADCTSTS0_CUTRGF0_Msk (0x1ul << PWM_ADCTSTS0_CUTRGF0_Pos)ï7PWM_ADCTSTS0_CPTRGF0_Pos (1)ð7PWM_ADCTSTS0_CPTRGF0_Msk (0x1ul << PWM_ADCTSTS0_CPTRGF0_Pos)ò7PWM_ADCTSTS0_CDTRGF0_Pos (2)ó7PWM_ADCTSTS0_CDTRGF0_Msk (0x1ul << PWM_ADCTSTS0_CDTRGF0_Pos)õ7PWM_ADCTSTS0_ZPTRGF0_Pos (3)ö7PWM_ADCTSTS0_ZPTRGF0_Msk (0x1ul << PWM_ADCTSTS0_ZPTRGF0_Pos)ø7PWM_ADCTSTS0_CUTRGF1_Pos (8)ù7PWM_ADCTSTS0_CUTRGF1_Msk (0x1ul << PWM_ADCTSTS0_CUTRGF1_Pos)û7PWM_ADCTSTS0_CPTRGF1_Pos (9)ü7PWM_ADCTSTS0_CPTRGF1_Msk (0x1ul << PWM_ADCTSTS0_CPTRGF1_Pos)þ7PWM_ADCTSTS0_CDTRGF1_Pos (10)ÿ7PWM_ADCTSTS0_CDTRGF1_Msk (0x1ul << PWM_ADCTSTS0_CDTRGF1_Pos)8PWM_ADCTSTS0_ZPTRGF1_Pos (11)‚8PWM_ADCTSTS0_ZPTRGF1_Msk (0x1ul << PWM_ADCTSTS0_ZPTRGF1_Pos)„8PWM_ADCTSTS0_CUTRGF2_Pos (16)…8PWM_ADCTSTS0_CUTRGF2_Msk (0x1ul << PWM_ADCTSTS0_CUTRGF2_Pos)‡8PWM_ADCTSTS0_CPTRGF2_Pos (17)ˆ8PWM_ADCTSTS0_CPTRGF2_Msk (0x1ul << PWM_ADCTSTS0_CPTRGF2_Pos)Š8PWM_ADCTSTS0_CDTRGF2_Pos (18)‹8PWM_ADCTSTS0_CDTRGF2_Msk (0x1ul << PWM_ADCTSTS0_CDTRGF2_Pos)8PWM_ADCTSTS0_ZPTRGF2_Pos (19)Ž8PWM_ADCTSTS0_ZPTRGF2_Msk (0x1ul << PWM_ADCTSTS0_ZPTRGF2_Pos)8PWM_ADCTSTS0_CUTRGF3_Pos (24)‘8PWM_ADCTSTS0_CUTRGF3_Msk (0x1ul << PWM_ADCTSTS0_CUTRGF3_Pos)“8PWM_ADCTSTS0_CPTRGF3_Pos (25)”8PWM_ADCTSTS0_CPTRGF3_Msk (0x1ul << PWM_ADCTSTS0_CPTRGF3_Pos)–8PWM_ADCTSTS0_CDTRGF3_Pos (26)—8PWM_ADCTSTS0_CDTRGF3_Msk (0x1ul << PWM_ADCTSTS0_CDTRGF3_Pos)™8PWM_ADCTSTS0_ZPTRGF3_Pos (27)š8PWM_ADCTSTS0_ZPTRGF3_Msk (0x1ul << PWM_ADCTSTS0_ZPTRGF3_Pos)œ8PWM_ADCTSTS1_CUTRGF4_Pos (0)8PWM_ADCTSTS1_CUTRGF4_Msk (0x1ul << PWM_ADCTSTS1_CUTRGF4_Pos)Ÿ8PWM_ADCTSTS1_CPTRGF4_Pos (1) 8PWM_ADCTSTS1_CPTRGF4_Msk (0x1ul << PWM_ADCTSTS1_CPTRGF4_Pos)¢8PWM_ADCTSTS1_CDTRGF4_Pos (2)£8PWM_ADCTSTS1_CDTRGF4_Msk (0x1ul << PWM_ADCTSTS1_CDTRGF4_Pos)¥8PWM_ADCTSTS1_ZPTRGF4_Pos (3)¦8PWM_ADCTSTS1_ZPTRGF4_Msk (0x1ul << PWM_ADCTSTS1_ZPTRGF4_Pos)¨8PWM_ADCTSTS1_CUTRGF5_Pos (8)©8PWM_ADCTSTS1_CUTRGF5_Msk (0x1ul << PWM_ADCTSTS1_CUTRGF5_Pos)«8PWM_ADCTSTS1_CPTRGF5_Pos (9)¬8PWM_ADCTSTS1_CPTRGF5_Msk (0x1ul << PWM_ADCTSTS1_CPTRGF5_Pos)®8PWM_ADCTSTS1_CDTRGF5_Pos (10)¯8PWM_ADCTSTS1_CDTRGF5_Msk (0x1ul << PWM_ADCTSTS1_CDTRGF5_Pos)±8PWM_ADCTSTS1_ZPTRGF5_Pos (11)²8PWM_ADCTSTS1_ZPTRGF5_Msk (0x1ul << PWM_ADCTSTS1_ZPTRGF5_Pos)µ8PWM_ADCTSTS1_CUTRGF6_Pos (16)¶8PWM_ADCTSTS1_CUTRGF6_Msk (0x1ul << PWM_ADCTSTS7_CUTRGF6_Pos)¸8PWM_ADCTSTS1_CPTRGF6_Pos (17)¹8PWM_ADCTSTS1_CPTRGF6_Msk (0x1ul << PWM_ADCTSTS7_CPTRGF6_Pos)»8PWM_ADCTSTS1_CDTRGF6_Pos (18)¼8PWM_ADCTSTS1_CDTRGF6_Msk (0x1ul << PWM_ADCTSTS7_CDTRGF6_Pos)¾8PWM_ADCTSTS1_ZPTRGF6_Pos (19)¿8PWM_ADCTSTS1_ZPTRGF6_Msk (0x1ul << PWM_ADCTSTS7_ZPTRGF6_Pos)Á8PWM_ADCTSTS1_CUTRGF7_Pos (24)Â8PWM_ADCTSTS1_CUTRGF7_Msk (0x1ul << PWM_ADCTSTS7_CUTRGF7_Pos)Ä8PWM_ADCTSTS1_CPTRGF7_Pos (25)Å8PWM_ADCTSTS1_CPTRGF7_Msk (0x1ul << PWM_ADCTSTS7_CPTRGF7_Pos)Ç8PWM_ADCTSTS1_CDTRGF7_Pos (26)È8PWM_ADCTSTS1_CDTRGF7_Msk (0x1ul << PWM_ADCTSTS7_CDTRGF7_Pos)Ê8PWM_ADCTSTS1_ZPTRGF7_Pos (27)Ë8PWM_ADCTSTS1_ZPTRGF7_Msk (0x1ul << PWM_ADCTSTS7_ZPTRGF7_Pos)Í8PWM_PCACTL_PCAEN_Pos (0)Î8PWM_PCACTL_PCAEN_Msk (0x1ul << PWM_PCACTL_PCAEN_Pos)÷8FLCTL_CTL_BYTES_NUM_R_Pos (8)ø8FLCTL_CTL_BYTES_NUM_R_Msk (0xFFFFFFul << FLCTL_CTL_BYTES_NUM_R_Pos)ù8FLCTL_CTL_BYTES_NUM_W_Pos (0)ú8FLCTL_CTL_BYTES_NUM_W_Msk (0x7ul << FLCTL_CTL_BYTES_NUM_W_Pos)ý8FLCTL_TRIG_TRG_Pos (0)þ8FLCTL_TRIG_TRG_Msk (0x1ul << FLCTL_TRIG_TRG_Pos)9FLCTL_CONFIG_FLASH_CAP_Pos (3)‚9FLCTL_CONFIG_FLASH_CAP_Msk (0x7ul << FLCTL_CONFIG_FLASH_CAP_Pos)ƒ9FLCTL_CONFIG_TX_ADDR_TRANS_Pos (2)„9FLCTL_CONFIG_TX_ADDR_TRANS_Msk (0x1ul << FLCTL_CONFIG_TX_ADDR_TRANS_Pos)…9FLCTL_CONFIG_INFO_EN_Pos (1)†9FLCTL_CONFIG_INFO_EN_Msk (0x1ul << FLCTL_CONFIG_INFO_EN_Pos)‡9FLCTL_CONFIG_PP_ACTIVE_Pos (0)ˆ9FLCTL_CONFIG_PP_ACTIVE_Msk (0x1ul << FLCTL_CONFIG_PP_ACTIVE_Pos)‹9FLCTL_W_DATA_Pos (0)Œ9FLCTL_W_DATA_Msk (0xFFul << FLCTL_W_DATA_Pos)9FLCTL_X_MODE_TIMEOUT_CNT_Pos (26)9FLCTL_X_MODE_TIMEOUT_CNT_Msk (0x3Ful << FLCTL_X_MODE_TIMEOUT_CNT_Pos)‘9FLCTL_X_MODE_RESUME_EN_Pos (25)’9FLCTL_X_MODE_RESUME_EN_Msk (0x1ul << FLCTL_X_MODE_RESUME_EN_Pos)“9FLCTL_X_MODE_SUS_SUCCESS_Pos (24)”9FLCTL_X_MODE_SUS_SUCCESS_Msk (0x1ul << FLCTL_X_MODE_SUS_SUCCESS_Pos)–9FLCTL_X_MODE_CLK_DLY_Pos (21)—9FLCTL_X_MODE_CLK_DLY_Msk (0x7ul << FLCTL_X_MODE_CLK_DLY_Pos)˜9FLCTL_X_MODE_RX_NEG_Pos (20)™9FLCTL_X_MODE_RX_NEG_Msk (0x1ul << FLCTL_X_MODE_RX_NEG_Pos)š9FLCTL_X_MODE_CRC32_EN_Pos (19)›9FLCTL_X_MODE_CRC32_EN_Msk (0x1ul << FLCTL_X_MODE_CRC32_EN_Pos)œ9FLCTL_X_MODE_ENHANCE_MODE_Pos (18)9FLCTL_X_MODE_ENHANCE_MODE_Msk (0x1ul << FLCTL_X_MODE_ENHANCE_MODE_Pos)ž9FLCTL_X_MODE_LONG_TIME_OP_Pos (17)Ÿ9FLCTL_X_MODE_LONG_TIME_OP_Msk (0x1ul << FLCTL_X_MODE_LONG_TIME_OP_Pos) 9FLCTL_X_MODE_EN_BURST_WRAP_Pos (16)¡9FLCTL_X_MODE_EN_BURST_WRAP_Msk (0x1ul << FLCTL_X_MODE_EN_BURST_WRAP_Pos)¢9FLCTL_X_MODE_CS_IDLE_CYCLE_Pos (8)£9FLCTL_X_MODE_CS_IDLE_CYCLE_Msk (0xFFul << FLCTL_X_MODE_CS_IDLE_CYCLE_Pos)¤9FLCTL_X_MODE_X_MODE_Pos (0)¥9FLCTL_X_MODE_X_MODE_Msk (0x3ul << FLCTL_X_MODE_X_MODE_Pos)¨9FLCTL_X2_CMD_Pos (0)©9FLCTL_X2_CMD_Msk (0xFFul << FLCTL_X2_CMD_Pos)¬9FLCTL_X4_CMD_Pos (0)­9FLCTL_X4_CMD_Msk (0xFFul << FLCTL_X4_CMD_Pos)°9FLCTL_DP_CMD_Pos (0)±9FLCTL_DP_CMD_Msk (0xFFul << FLCTL_DP_CMD_Pos)´9FLCTL_RDP_CMD_Pos (0)µ9FLCTL_RDP_CMD_Msk (0xFFul << FLCTL_RDP_CMD_Pos)¸9FLCTL_REMAP_ADDR_Pos (0)¹9FLCTL_REMAP_ADDR_Msk (0xFFul << FLCTL_REMAP_ADDR_Pos)¼9FLCTL_DP_CTL_RDP_WT_CNT_Pos (16)½9FLCTL_DP_CTL_RDP_WT_CNT_Msk (0xFFFFul << FLCTL_DP_CTL_RDP_WT_CNT_Pos)¾9FLCTL_DP_CTL_DP_WT_CNT_Pos (4)¿9FLCTL_DP_CTL_DP_WT_CNT_Msk (0xFFFul << FLCTL_DP_CTL_DP_WT_CNT_Pos)À9FLCTL_DP_CTL_DP_EN_Pos (0)Á9FLCTL_DP_CTL_DP_EN_Msk (0x1ul << FLCTL_DP_CTL_DP_EN_Pos)Ä9FLCTL_PROGRAM_SUS_CMD_Pos (24)Å9FLCTL_PROGRAM_SUS_CMD_Msk (0xFFul << FLCTL_PROGRAM_SUS_CMD_Pos)Æ9FLCTL_PROGRAM_RESUME_CMD_Pos (16)Ç9FLCTL_PROGRAM_RESUME_CMD_Msk (0xFFul << FLCTL_PROGRAM_RESUME_CMD_Pos)È9FLCTL_ERASE_SUS_CMD_Pos (8)É9FLCTL_ERASE_SUS_CMD_Msk (0xFFul << FLCTL_ERASE_SUS_CMD_Pos)Ê9FLCTL_ERASE_RESUME_CMD_Pos (0)Ë9FLCTL_ERASE_RESUME_CMD_Msk (0xFFul << FLCTL_ERASE_RESUME_CMD_Pos)ò9SPI_CR0_SCR_Pos (8)ó9SPI_CR0_SCR_Msk (0xFFul << SPI_CR0_SCR_Pos)õ9SPI_CR0_SPH_Pos (7)ö9SPI_CR0_SPH_Msk (0x1ul << SPI_CR0_SPH_Pos)ø9SPI_CR0_SPO_Pos (6)ù9SPI_CR0_SPO_Msk (0x1ul << SPI_CR0_SPO_Pos)û9SPI_CR0_FRF_Pos (4)ü9SPI_CR0_FRF_Msk (0x3ul << SPI_CR0_FRF_Pos)þ9SPI_CR0_DSS_Pos (0)ÿ9SPI_CR0_DSS_Msk (0xFul << SPI_CR0_DSS_Pos):SPI_CR1_SPI_MODE_SEL_Pos (10)‚:SPI_CR1_SPI_MODE_SEL_Msk (0x1ul << SPI_CR1_SPI_MODE_SEL_Pos)ƒ:SPI_CR1_CMD_DAT_EN_Pos (9)„:SPI_CR1_CMD_DAT_EN_Msk (0x1ul << SPI_CR1_CMD_DAT_EN_Pos)…:SPI_CR1_CMD_DAT_CTRL_Pos (8)†:SPI_CR1_CMD_DAT_CTRL_Msk (0x1ul << SPI_CR1_CMD_DAT_CTRL_Pos)‡:SPI_CR1_WR_CTRL_Pos (7)ˆ:SPI_CR1_WR_CTRL_Msk (0x1ul << SPI_CR1_WR_CTRL_Pos)Š:SPI_CR1_RX_LSB_EN_Pos (5)‹:SPI_CR1_RX_LSB_EN_Msk (0x1ul << SPI_CR1_RX_LSB_EN_Pos):SPI_CR1_TX_LSB_EN_Pos (4)Ž:SPI_CR1_TX_LSB_EN_Msk (0x1ul << SPI_CR1_TX_LSB_EN_Pos):SPI_CR1_SOD_Pos (3)‘:SPI_CR1_SOD_Msk (0x1ul << SPI_CR1_SOD_Pos)“:SPI_CR1_MS_Pos (2)”:SPI_CR1_MS_Msk (0x1ul << SPI_CR1_MS_Pos)–:SPI_CR1_SSE_Pos (1)—:SPI_CR1_SSE_Msk (0x1ul << SPI_CR1_SSE_Pos)™:SPI_CR1_LBM_Pos (0)š:SPI_CR1_LBM_Msk (0x1ul << SPI_CR1_LBM_Pos)œ:SPI_DR_Pos (0):SPI_DR_Msk (0xFFul << SPI_DR_Pos) :SPI_SR_BUSY_Pos (4)¡:SPI_SR_BUSY_Msk (0x1ul << SPI_SR_BUSY_Pos)£:SPI_SR_RFF_Pos (3)¤:SPI_SR_RFF_Msk (0x1ul << SPI_SR_RFF_Pos)¦:SPI_SR_RFNE_Pos (2)§:SPI_SR_RFNE_Msk (0x1ul << SPI_SR_RFNE_Pos)©:SPI_SR_TFNF_Pos (1)ª:SPI_SR_TFNF_Msk (0x1ul << SPI_SR_TFNF_Pos)¬:SPI_SR_TFE_Pos (0)­:SPI_SR_TFE_Msk (0x1ul << SPI_SR_TFE_Pos)°:SPI_CPSR_DIV_Pos (0)±:SPI_CPSR_DIV_Msk (0xFul << SPI_CPSR_DIV_Pos)´:SPI_IMSC_TXIM_Pos (3)µ:SPI_IMSC_TXIM_Msk (0x1ul << SPI_IMSC_TXIM_Pos)·:SPI_IMSC_RXIM_Pos (2)¸:SPI_IMSC_RXIM_Msk (0x1ul << SPI_IMSC_RXIM_Pos)º:SPI_IMSC_RTIM_Pos (1)»:SPI_IMSC_RTIM_Msk (0x1ul << SPI_IMSC_RTIM_Pos)¾:SPI_RIS_TXIS_Pos (3)¿:SPI_RIS_TXIS_Msk (0x1ul << SPI_RIS_TXIS_Pos)Á:SPI_RIS_RXIS_Pos (2)Â:SPI_RIS_RXIS_Msk (0x1ul << SPI_RIS_RXIS_Pos)Ä:SPI_RIS_RTIS_Pos (1)Å:SPI_RIS_RTIS_Msk (0x1ul << SPI_RIS_RTIS_Pos)Ç:SPI_RIS_RORIS_Pos (0)È:SPI_RIS_RORIS_Msk (0x1ul << SPI_RIS_RORIS_Pos)Ê:SPI_MIS_TXMIS_Pos (3)Ë:SPI_MIS_TXMIS_Msk (0x1ul << SPI_MIS_TXMIS_Pos)Í:SPI_MIS_RXMIS_Pos (2)Î:SPI_MIS_RXMIS_Msk (0x1ul << SPI_MIS_RXMIS_Pos)Ð:SPI_MIS_RTMIS_Pos (1)Ñ:SPI_MIS_RTMIS_Msk (0x1ul << SPI_MIS_RTMIS_Pos)Ó:SPI_MIS_RORMIS_Pos (0)Ô:SPI_MIS_RORMIS_Msk (0x1ul << SPI_MIS_RORMIS_Pos)×:SPI_ICR_RTICR_Pos (1)Ø:SPI_ICR_RTICR_Msk (0x1ul << SPI_ICR_RTICR_Pos)Ú:SPI_ICR_RORICR_Pos (0)Û:SPI_ICR_RORICR_Msk (0x1ul << SPI_ICR_RORICR_Pos)Þ:SPI_DMACR_TDMAE_Pos (1)ß:SPI_DMACR_TDMAE_Msk (0x1ul << SPI_DMACR_TDMAE_Pos)á:SPI_DMACR_RDMAE_Pos (0)â:SPI_DMACR_RDMAE_Msk (0x1ul << SPI_DMACR_RDMAE_Pos)”>UART_RBR_MSB9_Pos (8)•>UART_RBR_MSB9_Msk (0x1ul << UART_RBR_MSB9_Pos)—>UART_RBR_DAT_Pos (0)˜>UART_RBR_DAT_Msk (0xfful << UART_RBR_DAT_Pos)š>UART_THR_MSB9_Pos (8)›>UART_THR_MSB9_Msk (0x1ul << UART_THR_MSB9_Pos)>UART_THR_DAT_Pos (0)ž>UART_THR_DAT_Msk (0xfful << UART_THR_DAT_Pos) >UART_DLH_Pos (0)¡>UART_DLH_Msk (0xfful << UART_DLH_Pos)£>UART_DLL_Pos (0)¤>UART_DLL_Msk (0xfful << UART_DLL_Pos)¦>UART_IER_EPTI_Pos (7)§>UART_IER_EPTI_Msk (0x1ul << UART_IER_EPTI_Pos)©>UART_IER_EMSI_Pos (3)ª>UART_IER_EMSI_Msk (0x1ul << UART_IER_EMSI_Pos)«>UART_IER_ERLSI_Pos (2)¬>UART_IER_ERLSI_Msk (0x1ul << UART_IER_ERLSI_Pos)­>UART_IER_ETHREI_Pos (1)®>UART_IER_ETHREI_Msk (0x1ul << UART_IER_ETHREI_Pos)¯>UART_IER_ERDAI_Pos (0)°>UART_IER_ERDAI_Msk (0x1ul << UART_IER_ERDAI_Pos)²>UART_IER_ALL_IRQ_Pos (0)³>UART_IER_ALL_IRQ_Msk (0xful << UART_IER_ALL_IRQ_Pos)µ>UART_IIR_FIFOSE_Pos (6)¶>UART_IIR_FIFOSE_Msk (0x3ul << UART_IIR_FIFOSE_Pos)¸>UART_IIR_IID_Pos (0)¹>UART_IIR_IID_Msk (0xful << UART_IIR_IID_Pos)¼>UART_FCR_RT_Pos (6)½>UART_FCR_RT_Msk (0x3ul << UART_FCR_RT_Pos)¾>UART_FCR_TET_Pos (4)¿>UART_FCR_TET_Msk (0x3ul << UART_FCR_TET_Pos)À>UART_FCR_DMAM_Pos (3)Á>UART_FCR_DMAM_Msk (0x1ul << UART_FCR_DMAM_Pos)Â>UART_FCR_XFIFOR_Pos (2)Ã>UART_FCR_XFIFOR_Msk (0x1ul << UART_FCR_XFIFOR_Pos)Ä>UART_FCR_RFIFOR_Pos (1)Å>UART_FCR_RFIFOR_Msk (0x1ul << UART_FCR_RFIFOR_Pos)Æ>UART_FCR_FIFOE_Pos (0)Ç>UART_FCR_FIFOE_Msk (0x1ul << UART_FCR_FIFOE_Pos)Ê>UART_LCR_DLAB_Pos (7)Ë>UART_LCR_DLAB_Msk (0x1ul << UART_LCR_DLAB_Pos)Ì>UART_LCR_BC_Pos (6)Í>UART_LCR_BC_Msk (0x1ul << UART_LCR_BC_Pos)Î>UART_LCR_SP_Pos (5)Ï>UART_LCR_SP_Msk (0x1ul << UART_LCR_SP_Pos)Ð>UART_LCR_EPS_Pos (4)Ñ>UART_LCR_EPS_Msk (0x1ul << UART_LCR_EPS_Pos)Ò>UART_LCR_PEN_Pos (3)Ó>UART_LCR_PEN_Msk (0x1ul << UART_LCR_PEN_Pos)Ô>UART_LCR_STOP_Pos (2)Õ>UART_LCR_STOP_Msk (0x1ul << UART_LCR_STOP_Pos)Ö>UART_LCR_DLS_Pos (0)×>UART_LCR_DLS_Msk (0x3ul << UART_LCR_DLS_Pos)Ú>UART_MCR_SIRE_Pos (6)Û>UART_MCR_SIRE_Msk (0x1ul << UART_MCR_SIRE_Pos)Ü>UART_MCR_AFCE_Pos (5)Ý>UART_MCR_AFCE_Msk (0x1ul << UART_MCR_AFCE_Pos)Þ>UART_MCR_LB_Pos (4)ß>UART_MCR_LB_Msk (0x1ul << UART_MCR_LB_Pos)à>UART_MCR_OUT2_Pos (3)á>UART_MCR_OUT2_Msk (0x1ul << UART_MCR_OUT2_Pos)â>UART_MCR_OUT1_Pos (2)ã>UART_MCR_OUT1_Msk (0x1ul << UART_MCR_OUT1_Pos)ä>UART_MCR_RTS_Pos (1)å>UART_MCR_RTS_Msk (0x1ul << UART_MCR_RTS_Pos)æ>UART_MCR_DTR_Pos (0)ç>UART_MCR_DTR_Msk (0x1ul << UART_MCR_DTR_Pos)ê>UART_LSR_ADDR_RCVD_Pos (8)ë>UART_LSR_ADDR_RCVD_Msk (0x1ul << UART_LSR_ADDR_RCVD_Pos)ì>UART_LSR_RFE_Pos (7)í>UART_LSR_RFE_Msk (0x1ul << UART_LSR_RFE_Pos)î>UART_LSR_TEMT_Pos (6)ï>UART_LSR_TEMT_Msk (0x1ul << UART_LSR_TEMT_Pos)ð>UART_LSR_THRE_Pos (5)ñ>UART_LSR_THRE_Msk (0x1ul << UART_LSR_THRE_Pos)ò>UART_LSR_BI_Pos (4)ó>UART_LSR_BI_Msk (0x1ul << UART_LSR_BI_Pos)ô>UART_LSR_FE_Pos (3)õ>UART_LSR_FE_Msk (0x1ul << UART_LSR_FE_Pos)ö>UART_LSR_PE_Pos (2)÷>UART_LSR_PE_Msk (0x1ul << UART_LSR_PE_Pos)ø>UART_LSR_OE_Pos (1)ù>UART_LSR_OE_Msk (0x1ul << UART_LSR_OE_Pos)ú>UART_LSR_DR_Pos (0)û>UART_LSR_DR_Msk (0x1ul << UART_LSR_DR_Pos)ý>UART_LSR_LINE_STATUS_Pos (0)þ>UART_LSR_LINE_STATUS_Msk (0x1FFul << UART_LSR_LINE_STATUS_Pos)?UART_MSR_DCD_Pos (7)‚?UART_MSR_DCD_Msk (0x1ul << UART_MSR_DCD_Pos)ƒ?UART_MSR_RI_Pos (6)„?UART_MSR_RI_Msk (0x1ul << UART_MSR_RI_Pos)…?UART_MSR_DSR_Pos (5)†?UART_MSR_DSR_Msk (0x1ul << UART_MSR_DSR_Pos)‡?UART_MSR_CTS_Pos (4)ˆ?UART_MSR_CTS_Msk (0x1ul << UART_MSR_CTS_Pos)‰?UART_MSR_DDCD_Pos (3)Š?UART_MSR_DDCD_Msk (0x1ul << UART_MSR_DDCD_Pos)‹?UART_MSR_TERI_Pos (2)Œ?UART_MSR_TERI_Msk (0x1ul << UART_MSR_TERI_Pos)?UART_MSR_DDSR_Pos (1)Ž?UART_MSR_DDSR_Msk (0x1ul << UART_MSR_DDSR_Pos)?UART_MSR_DCTS_Pos (0)?UART_MSR_DCTS_Msk (0x1ul << UART_MSR_DCTS_Pos)’?UART_MSR_MODEM_STATUS_Pos (0)“?UART_MSR_MODEM_STATUS_Msk (0xFFul << UART_MSR_MODEM_STATUS_Pos)–?UART_SCR_Pos (0)—?UART_SCR_Msk (0xFFFFFFFFul << UART_SCR_Pos)š?UART_LPDLL_Pos (0)›?UART_LPDLL_Msk (0xFFul << UART_LPDLL_Pos)ž?UART_LPDLH_Pos (0)Ÿ?UART_LPDLH_Msk (0xFFul << UART_LPDLH_Pos)¢?UART_USR_RFF_Pos (4)£?UART_USR_RFF_Msk (0x1ul << UART_USR_RFF_Pos)¤?UART_USR_RFNE_Pos (3)¥?UART_USR_RFNE_Msk (0x1ul << UART_USR_RFNE_Pos)¦?UART_USR_TFE_Pos (2)§?UART_USR_TFE_Msk (0x1ul << UART_USR_TFE_Pos)¨?UART_USR_TFNF_Pos (1)©?UART_USR_TFNF_Msk (0x1ul << UART_USR_TFNF_Pos)¬?UART_TFL_Pos (0)­?UART_TFL_Msk (0x1Ful << UART_TFL_Pos)°?UART_RFL_Pos (0)±?UART_RFL_Msk (0x1Ful << UART_RFL_Pos)´?UART_DMASA_Pos (0)µ?UART_DMASA_Msk (0x1ul << UART_DMASA_Pos)¸?UART_DLF_Pos (0)¹?UART_DLF_Msk (0xFul << UART_DLF_Pos)¼?UART_RAR_Pos (0)½?UART_RAR_Msk (0xFFul << UART_RAR_Pos)À?UART_TAR_Pos (0)Á?UART_TAR_Msk (0xFFul << UART_TAR_Pos)Æ?UART_LCR_EXT_TRANSMIT_MODE_Pos (3)Ç?UART_LCR_EXT_TRANSMIT_MODE_Msk (0x1ul << UART_LCR_EXT_TRANSMIT_MODE_Pos)È?UART_LCR_EXT_SEND_ADDR_Pos (2)É?UART_LCR_EXT_SEND_ADDR_Msk (0x1ul << UART_LCR_EXT_SEND_ADDR_Pos)Ê?UART_LCR_EXT_ADDR_MATCH_Pos (1)Ë?UART_LCR_EXT_ADDR_MATCH_Msk (0x1ul << UART_LCR_EXT_ADDR_MATCH_Pos)Ì?UART_LCR_EXT_DLS_E_Pos (0)Í?UART_LCR_EXT_DLS_E_Msk (0x1ul << UART_LCR_EXT_DLS_E_Pos)Ø?UART_DR_OE ((uint32_t)0x00000800)Ù?UART_DR_BE ((uint32_t)0x00000400)Ú?UART_DR_PE ((uint32_t)0x00000200)Û?UART_DR_FE ((uint32_t)0x00000100)Ü?UART_DR_DATA ((uint32_t)0x000000FF)à?UART_RSCR_OE ((uint32_t)0x00000008)á?UART_RSCR_BE ((uint32_t)0x00000004)â?UART_RSCR_PE ((uint32_t)0x00000002)ã?UART_RSCR_FE ((uint32_t)0x00000001)å?UART_RSCR_CLR_ERR ((uint32_t)0x000000ff)ê?UART_STATUS_RI ((uint32_t)0x00000100)ë?UART_STATUS_TXFE ((uint32_t)0x00000080)ì?UART_STATUS_RXFF ((uint32_t)0x00000040)í?UART_STATUS_TXFF ((uint32_t)0x00000020)î?UART_STATUS_RXFE ((uint32_t)0x00000010)ï?UART_STATUS_BUSY ((uint32_t)0x00000008)ð?UART_STATUS_DCD ((uint32_t)0x00000004)ñ?UART_STATUS_DSR ((uint32_t)0x00000002)ò?UART_STATUS_CTS ((uint32_t)0x00000001)õ?UART_IRDA_LP_DIV ((uint32_t)0x000000FF)ø?UART_BRD_IBRD ((uint32_t)0x0000FFFF)û?UART_BRD_FBRD ((uint32_t)0x0000003F)þ?UART_LC_CLEAR_MSK ((uint32_t)0x000000FF)€@UART_LC_SPS ((uint32_t)0x00000080)@UART_LC_WLEN ((uint32_t)0x00000060)‚@UART_LC_FEN ((uint32_t)0x00000010)ƒ@UART_LC_STP2 ((uint32_t)0x00000008)„@UART_LC_EPS ((uint32_t)0x00000004)…@UART_LC_PEN ((uint32_t)0x00000002)†@UART_LC_BRK ((uint32_t)0x00000001)‰@UART_CR_CLEAR_MSK ((uint32_t)0x0000FF87)‹@UART_CR_CTSEN ((uint32_t)0x00008000)Œ@UART_CR_RTSEN ((uint32_t)0x00004000)@UART_CR_OUT2 ((uint32_t)0x00002000)Ž@UART_CR_OUT1 ((uint32_t)0x00001000)@UART_CR_RTS ((uint32_t)0x00000800)@UART_CR_DTR ((uint32_t)0x00000400)‘@UART_CR_RXE ((uint32_t)0x00000200)’@UART_CR_TXE ((uint32_t)0x00000100)“@UART_CR_LBE ((uint32_t)0x00000080)”@UART_CR_SIRLP ((uint32_t)0x00000004)•@UART_CR_SIREN ((uint32_t)0x00000002)–@UART_CR_UARTEN ((uint32_t)0x00000001)™@UART_INT_FIFO_RXIFLSEL ((uint32_t)0x00000038)š@UART_INT_FIFO_TXIFLSEL ((uint32_t)0x00000007)@UART_INT_MSK_OEIM ((uint32_t)0x00000400)ž@UART_INT_MSK_BEIM ((uint32_t)0x00000200)Ÿ@UART_INT_MSK_PEIM ((uint32_t)0x00000100) @UART_INT_MSK_FEIM ((uint32_t)0x00000080)¡@UART_INT_MSK_RTIM ((uint32_t)0x00000040)¢@UART_INT_MSK_TXIM ((uint32_t)0x00000020)£@UART_INT_MSK_RXIM ((uint32_t)0x00000010)¤@UART_INT_MSK_DSRMIM ((uint32_t)0x00000008)¥@UART_INT_MSK_DCDMIM ((uint32_t)0x00000004)¦@UART_INT_MSK_CTSMIM ((uint32_t)0x00000002)§@UART_INT_MSK_RIMIM ((uint32_t)0x00000001)ª@UART_RAW_INT_MSK_OEIM ((uint32_t)0x00000400)«@UART_RAW_INT_MSK_BEIM ((uint32_t)0x00000200)¬@UART_RAW_INT_MSK_PEIM ((uint32_t)0x00000100)­@UART_RAW_INT_MSK_FEIM ((uint32_t)0x00000080)®@UART_RAW_INT_MSK_RTIM ((uint32_t)0x00000040)¯@UART_RAW_INT_MSK_TXIM ((uint32_t)0x00000020)°@UART_RAW_INT_MSK_RXIM ((uint32_t)0x00000010)±@UART_RAW_INT_MSK_DSRMIM ((uint32_t)0x00000008)²@UART_RAW_INT_MSK_DCDMIM ((uint32_t)0x00000004)³@UART_RAW_INT_MSK_CTSMIM ((uint32_t)0x00000002)´@UART_RAW_INT_MSK_RIMIM ((uint32_t)0x00000001)·@UART_MASKED_INT_STAT_OEIM ((uint32_t)0x00000400)¸@UART_MASKED_INT_STAT_BEIM ((uint32_t)0x00000200)¹@UART_MASKED_INT_STAT_PEIM ((uint32_t)0x00000100)º@UART_MASKED_INT_STAT_FEIM ((uint32_t)0x00000080)»@UART_MASKED_INT_STAT_RTIM ((uint32_t)0x00000040)¼@UART_MASKED_INT_STAT_TXIM ((uint32_t)0x00000020)½@UART_MASKED_INT_STAT_RXIM ((uint32_t)0x00000010)¾@UART_MASKED_INT_STAT_DSRMIM ((uint32_t)0x00000008)¿@UART_MASKED_INT_STAT_DCDMIM ((uint32_t)0x00000004)À@UART_MASKED_INT_STAT_CTSMIM ((uint32_t)0x00000002)Á@UART_MASKED_INT_STAT_RIMIM ((uint32_t)0x00000001)Ä@UART_CLR_INT_OEIM ((uint32_t)0x00000400)Å@UART_CLR_INT_BEIM ((uint32_t)0x00000200)Æ@UART_CLR_INT_PEIM ((uint32_t)0x00000100)Ç@UART_CLR_INT_FEIM ((uint32_t)0x00000080)È@UART_CLR_INT_RTIM ((uint32_t)0x00000040)É@UART_CLR_INT_TXIM ((uint32_t)0x00000020)Ê@UART_CLR_INT_RXIM ((uint32_t)0x00000010)Ë@UART_CLR_INT_DSRMIM ((uint32_t)0x00000008)Ì@UART_CLR_INT_DCDMIM ((uint32_t)0x00000004)Í@UART_CLR_INT_CTSMIM ((uint32_t)0x00000002)Î@UART_CLR_INT_RIMIM ((uint32_t)0x00000001)Ñ@UART_DMA_CR_DMAONERR ((uint32_t)0x00000004)Ò@UART_DMA_CR_TXDMAE ((uint32_t)0x00000002)Ó@UART_DMA_CR_RXDMAE ((uint32_t)0x00000001)ÎADMAC_DMACFGREG_L_DMA_EN_Pos (0)ÏADMAC_DMACFGREG_L_DMA_EN_Msk (0x1ul << DMAC_DMACFGREG_L_DMA_EN_Pos)ÑADMAC_CHENREG_L_CH_EN_Pos(ch) (ch)ÒADMAC_CHENREG_L_CH_EN_Msk(ch) (0x1ul << DMAC_CHENREG_L_CH_EN_Pos(ch))ÔADMAC_CHENREG_L_CH_EN_ALL_Pos (0)ÕADMAC_CHENREG_L_CH_EN_ALL_Msk (0xfful << DMAC_CHENREG_L_CH_EN_ALL_Pos)×ADMAC_CHENREG_L_CH_EN_WE_Pos(ch) ((ch)+8)ØADMAC_CHENREG_L_CH_EN_WE_Msk(ch) (0x1ul << DMAC_CHENREG_L_CH_EN_WE_Pos(ch))ÚADMAC_CHENREG_L_CH_EN_WE_ALL_Pos (8)ÛADMAC_CHENREG_L_CH_EN_WE_ALL_Msk (0xfful << DMAC_CHENREG_L_CH_EN_WE_ALL_Pos)ÝADMAC_SAR_L_SAR_Pos (0)ÞADMAC_SAR_L_SAR_Msk (0xfffffffful << DMAC_SAR_L_SAR_Pos)àADMAC_DAR_L_DAR_Pos (0)áADMAC_DAR_L_DAR_Msk (0xfffffffful << DMAC_DAR_L_DAR_Pos)ãADMAC_CTL_L_INT_EN_Pos (0)äADMAC_CTL_L_INT_EN_Msk (0x1ul << DMAC_CTL_L_INT_EN_Pos)æADMAC_CTL_L_DST_TR_WIDTH_Pos (1)çADMAC_CTL_L_DST_TR_WIDTH_Msk (0x3ul << DMAC_CTL_L_DST_TR_WIDTH_Pos)éADMAC_CTL_L_SRC_TR_WIDTH_Pos (4)êADMAC_CTL_L_SRC_TR_WIDTH_Msk (0x3ul << DMAC_CTL_L_SRC_TR_WIDTH_Pos)ìADMAC_CTL_L_DINC_Pos (7)íADMAC_CTL_L_DINC_Msk (0x3ul << DMAC_CTL_L_DINC_Pos)ïADMAC_CTL_L_SINC_Pos (9)ðADMAC_CTL_L_SINC_Msk (0x3ul << DMAC_CTL_L_SINC_Pos)òADMAC_CTL_L_DEST_MSIZE_Pos (11)óADMAC_CTL_L_DEST_MSIZE_Msk (0x7ul << DMAC_CTL_L_DEST_MSIZE_Pos)õADMAC_CTL_L_SRC_MSIZE_Pos (14)öADMAC_CTL_L_SRC_MSIZE_Msk (0x7ul << DMAC_CTL_L_SRC_MSIZE_Pos)øADMAC_CTL_L_TT_FC_Pos (20)ùADMAC_CTL_L_TT_FC_Msk (0x7ul << DMAC_CTL_L_TT_FC_Pos)ûADMAC_CTL_H_BLOCK_TS_Pos (0)üADMAC_CTL_H_BLOCK_TS_Msk (0xffful << DMAC_CTL_H_BLOCK_TS_Pos)þADMAC_CTL_H_DONE_Pos (12)ÿADMAC_CTL_H_DONE_Msk (0x1ul << DMAC_CTL_H_DONE_Pos)BDMAC_CFG_L_CH_PRIOR_Pos (5)‚BDMAC_CFG_L_CH_PRIOR_Msk (0x7 << DMAC_CFG_L_CH_PRIOR_Pos)„BDMAC_CFG_L_CH_SUSP_Pos (8)…BDMAC_CFG_L_CH_SUSP_Msk (0x1ul << DMAC_CFG_L_CH_SUSP_Pos)‡BDMAC_CFG_L_FIFO_EMPTY_Pos (9)ˆBDMAC_CFG_L_FIFO_EMPTY_Msk (0x1ul << DMAC_CFG_L_FIFO_EMPTY_Pos)ŠBDMAC_CFG_L_HS_SEL_DST_Pos (10)‹BDMAC_CFG_L_HS_SEL_DST_Msk (0x1ul << DMAC_CFG_L_HS_SEL_DST_Pos)BDMAC_CFG_L_HS_SEL_SRC_Pos (11)ŽBDMAC_CFG_L_HS_SEL_SRC_Msk (0x1ul << DMAC_CFG_L_HS_SEL_SRC_Pos)‘BDMAC_CFG_L_DST_HS_POL_Pos (18)’BDMAC_CFG_L_DST_HS_POL_Msk (0x1ul << DMAC_CFG_L_DST_HS_POL_Pos)”BDMAC_CFG_L_SRC_HS_POL_Pos (19)•BDMAC_CFG_L_SRC_HS_POL_Msk (0x1ul << DMAC_CFG_L_SRC_HS_POL_Pos)™BDMAC_CFG_H_FCMODE_Pos (0)šBDMAC_CFG_H_FCMODE_Msk (0x1ul << DMAC_CFG_H_FCMODE_Pos)œBDMAC_CFG_H_FIFO_MODE_Pos (1)BDMAC_CFG_H_FIFO_MODE_Msk (0x1ul << DMAC_CFG_H_FIFO_MODE_Pos)ŸBDMAC_CFG_H_PROTCTL_Pos (2) BDMAC_CFG_H_PROTCTL_Msk (0x7ul << DMAC_CFG_H_PROTCTL_Pos)¢BDMAC_CFG_H_SRC_PER_Pos (7)£BDMAC_CFG_H_SRC_PER_Msk (0xful << DMAC_CFG_H_SRC_PER_Pos)¥BDMAC_CFG_H_DEST_PER_Pos (11)¦BDMAC_CFG_H_DEST_PER_Msk (0xful << DMAC_CFG_H_DEST_PER_Pos)¨BDMAC_INT_RAW_STAT_CLR_Pos(ch) (ch)©BDMAC_INT_RAW_STAT_CLR_Msk(ch) (0x1ul << DMAC_INT_RAW_STAT_CLR_Pos(ch))«BDMAC_INT_RAW_STAT_CLR_ALL_Pos (0)¬BDMAC_INT_RAW_STAT_CLR_ALL_Msk (0xfful << DMAC_INT_RAW_STAT_CLR_ALL_Pos)®BDMAC_INT_MASK_L_Pos(ch) (ch)¯BDMAC_INT_MASK_L_Msk(ch) (0x1ul << DMAC_INT_MASK_L_Pos(ch))±BDMAC_INT_MASK_L_ALL_Pos (0)²BDMAC_INT_MASK_L_ALL_Msk (0xfful << DMAC_INT_MASK_L_ALL_Pos)´BDMAC_INT_MASK_L_WE_Pos(ch) ((ch)+8)µBDMAC_INT_MASK_L_WE_Msk(ch) (0x1ul << DMAC_INT_MASK_L_WE_Pos(ch))·BDMAC_INT_MASK_L_WE_ALL_Pos (8)¸BDMAC_INT_MASK_L_WE_ALL_Msk (0xfful << DMAC_INT_MASK_L_WE_ALL_Pos)ºBDMAC_STATUSINT_L_TFR_Pos (0)»BDMAC_STATUSINT_L_TFR_Msk (0x1ul << DMAC_STATUSINT_L_TFR_Pos)½BDMAC_STATUSINT_L_BLOCK_Pos (1)¾BDMAC_STATUSINT_L_BLOCK_Msk (0x1ul << DMAC_STATUSINT_L_BLOCK_Pos)ÀBDMAC_STATUSINT_L_SRCTRAN_Pos (2)ÁBDMAC_STATUSINT_L_SRCTRAN_Msk (0x1ul << DMAC_STATUSINT_L_SRCTRAN_Pos)ÃBDMAC_STATUSINT_L_DSTTRAN_Pos (3)ÄBDMAC_STATUSINT_L_DSTTRAN_Msk (0x1ul << DMAC_STATUSINT_L_DSTTRAN_Pos)ÆBDMAC_STATUSINT_L_ERR_Pos (4)ÇBDMAC_STATUSINT_L_ERR_Msk (0x1ul << DMAC_STATUSINT_L_ERR_Pos)‰CI2C_CON_MASTER_MODE ((uint16_t)0x0001)‹CI2C_CON_SPEED ((uint16_t)0x0006)ŒCI2C_CON_SPEED_0 ((uint16_t)0x0002)CI2C_CON_SPEED_1 ((uint16_t)0x0004)CI2C_CON_IC_10BITADDR_SLAVE ((uint16_t)0x0008)CI2C_CON_IC_10BITADDR_MASTER ((uint16_t)0x0010)‘CI2C_CON_IC_RESTART_EN ((uint16_t)0x0020)’CI2C_CON_IC_SLAVE_DISABLE ((uint16_t)0x0040)“CI2C_CON_STOP_DET_IFADDRESSED ((uint16_t)0x0080)”CI2C_CON_TX_EMPTY_CTRL ((uint16_t)0x0100)—CI2C_TAR_TAR ((uint16_t)0x03ff)˜CI2C_TAR_IC_TAR_0 ((uint16_t)0x0001)™CI2C_TAR_IC_TAR_1 ((uint16_t)0x0002)šCI2C_TAR_IC_TAR_2 ((uint16_t)0x0004)›CI2C_TAR_IC_TAR_3 ((uint16_t)0x0008)œCI2C_TAR_IC_TAR_4 ((uint16_t)0x0010)CI2C_TAR_IC_TAR_5 ((uint16_t)0x0020)žCI2C_TAR_IC_TAR_6 ((uint16_t)0x0040)ŸCI2C_TAR_IC_TAR_7 ((uint16_t)0x0080) CI2C_TAR_IC_TAR_8 ((uint16_t)0x0100)¡CI2C_TAR_IC_TAR_9 ((uint16_t)0x0200)£CI2C_TAR_GC_OR_START ((uint16_t)0x0400)¤CI2C_TAR_SPECIAL ((uint16_t)0x0800)¥CI2C_TAR_IC_10BITADDR_MASTER ((uint16_t)0x1000)¨CI2C_SAR_IC_SAR ((uint16_t)0x03ff)ªCI2C_HS_MADDR_IC_HS_MAR ((uint16_t)0x0007)¬CI2C_DATA_CMD_DAT ((uint16_t)0x00ff)­CI2C_DATA_CMD_CMD_R ((uint16_t)0x0100)®CI2C_DATA_CMD_STOP ((uint16_t)0x0200)¯CI2C_DATA_CMD_RESTART ((uint16_t)0x0400)²CI2C_SS_SCL_HCNT ((uint16_t)0xffff)µCI2C_SS_SCL_LCNT ((uint16_t)0xffff)¸CI2C_FS_SCL_HCNT ((uint16_t)0xffff)»CI2C_FS_SCL_LCNT ((uint16_t)0xffff)¾CI2C_HS_SCL_HCNT ((uint16_t)0xffff)ÁCI2C_HS_SCL_LCNT ((uint16_t)0xffff)ÄCI2C_INTR_STAT_R_RX_UNDER ((uint16_t)0x0001)ÅCI2C_INTR_STAT_R_RX_OVER ((uint16_t)0x0002)ÆCI2C_INTR_STAT_R_RX_FULL ((uint16_t)0x0004)ÇCI2C_INTR_STAT_R_TX_OVER ((uint16_t)0x0008)ÈCI2C_INTR_STAT_R_TX_EMPTY ((uint16_t)0x0010)ÉCI2C_INTR_STAT_R_RD_REQ ((uint16_t)0x0020)ÊCI2C_INTR_STAT_R_TX_ABRT ((uint16_t)0x0040)ËCI2C_INTR_STAT_R_RX_DONE ((uint16_t)0x0080)ÌCI2C_INTR_STAT_R_ACTIVITY ((uint16_t)0x0100)ÍCI2C_INTR_STAT_R_STOP_DET ((uint16_t)0x0200)ÎCI2C_INTR_STAT_R_START_DET ((uint16_t)0x0400)ÏCI2C_INTR_STAT_R_GEN_CALL ((uint16_t)0x0800)ÐCI2C_INTR_STAT_R_RESTART_DET ((uint16_t)0x1000)ÑCI2C_INTR_STAT_R_MST_ON_HOLD ((uint16_t)0x2000)ÕCI2C_INTR_MASK_M_RX_UNDER ((uint16_t)0x0001)ÖCI2C_INTR_MASK_M_RX_OVER ((uint16_t)0x0002)×CI2C_INTR_MASK_M_RX_FULL ((uint16_t)0x0004)ØCI2C_INTR_MASK_M_TX_OVER ((uint16_t)0x0008)ÙCI2C_INTR_MASK_M_TX_EMPTY ((uint16_t)0x0010)ÚCI2C_INTR_MASK_M_RD_REQ ((uint16_t)0x0020)ÛCI2C_INTR_MASK_M_TX_ABRT ((uint16_t)0x0040)ÜCI2C_INTR_MASK_M_RX_DONE ((uint16_t)0x0080)ÝCI2C_INTR_MASK_M_ACTIVITY ((uint16_t)0x0100)ÞCI2C_INTR_MASK_M_STOP_DET ((uint16_t)0x0200)ßCI2C_INTR_MASK_M_START_DET ((uint16_t)0x0400)àCI2C_INTR_MASK_M_GEN_CALL ((uint16_t)0x0800)áCI2C_INTR_MASK_M_RESTART_DET ((uint16_t)0x1000)âCI2C_INTR_MASK_M_MST_ON_HOLD ((uint16_t)0x2000)åCI2C_RAW_INTR_STAT_RX_UNDER ((uint16_t)0x0001)æCI2C_RAW_INTR_STAT_RX_OVER ((uint16_t)0x0002)çCI2C_RAW_INTR_STAT_RX_FULL ((uint16_t)0x0004)èCI2C_RAW_INTR_STAT_TX_OVER ((uint16_t)0x0008)éCI2C_RAW_INTR_STAT_TX_EMPTY ((uint16_t)0x0010)êCI2C_RAW_INTR_STAT_RD_REQ ((uint16_t)0x0020)ëCI2C_RAW_INTR_STAT_TX_ABRT ((uint16_t)0x0040)ìCI2C_RAW_INTR_STAT_RX_DONE ((uint16_t)0x0080)íCI2C_RAW_INTR_STAT_ACTIVITY ((uint16_t)0x0100)îCI2C_RAW_INTR_STAT_STOP_DET ((uint16_t)0x0200)ïCI2C_RAW_INTR_STAT_START_DET ((uint16_t)0x0400)ðCI2C_RAW_INTR_STAT_GEN_CALL ((uint16_t)0x0800)ñCI2C_RAW_INTR_STAT_RESTART_DET ((uint16_t)0x1000)òCI2C_RAW_INTR_STAT_MST_ON_HOLD ((uint16_t)0x2000)õCI2C_RX_TL ((uint16_t)0x00ff)øCI2C_TX_TL ((uint16_t)0x00ff)ûCI2C_CLR_INTR ((uint16_t)0x0001)þCI2C_CLR_RX_UNDER ((uint16_t)0x0001)DI2C_CLR_RX_UNDER ((uint16_t)0x0001)„DI2C_CLR_TX_OVER ((uint16_t)0x0001)‡DI2C_CLR_RD_REQ ((uint16_t)0x0001)ŠDI2C_CLR_TX_ABORT ((uint16_t)0x0001)DI2C_CLR_RX_DONE ((uint16_t)0x0001)DI2C_CLR_ACTIVITY ((uint16_t)0x0001)“DI2C_CLR_STOP_DET ((uint16_t)0x0001)–DI2C_CLR_START_DET ((uint16_t)0x0001)™DI2C_CLR_GEN_CALL ((uint16_t)0x0001)›DI2C_CLR_RESTART_DET ((uint16_t)0x0001)DI2C_CLR_MST_ON_HOLD ((uint16_t)0x0001)¡DI2C_ENABLE_ENABLE ((uint16_t)0x0001)¢DI2C_ENABLE_ABORT ((uint16_t)0x0002)¤DI2C_STATUS_ACTIVITY ((uint16_t)0x0001)¥DI2C_STATUS_TFNF ((uint16_t)0x0002)¦DI2C_STATUS_TFE ((uint16_t)0x0004)§DI2C_STATUS_RFNE ((uint16_t)0x0008)¨DI2C_STATUS_RFE ((uint16_t)0x0010)©DI2C_STATUS_MST_ACTIVITY ((uint16_t)0x0020)ªDI2C_STATUS_SLV_ACTIVITY ((uint16_t)0x0040)­DI2C_TXFLR ((uint32_t)0x0000000f)°DI2C_RXFLR ((uint32_t)0x0000000f)³DI2C_SDA_HOLD ((uint32_t)0x0000ffff)¶DI2C_TX_ABRT_SOURCE_7B_ADDR_NOACK ((uint32_t)0x00000001)·DI2C_TX_ABRT_SOURCE_10ADDR1_NOACK ((uint32_t)0x00000002)¸DI2C_TX_ABRT_SOURCE_10ADDR2_NOACK ((uint32_t)0x00000004)¹DI2C_TX_ABRT_SOURCE_TXDATA_NOACK ((uint32_t)0x00000008)ºDI2C_TX_ABRT_SOURCE_GCALL_NOACK ((uint32_t)0x00000010)»DI2C_TX_ABRT_SOURCE_GCALL_READ ((uint32_t)0x00000020)¼DI2C_TX_ABRT_SOURCE_HS_ACKDET ((uint32_t)0x00000040)½DI2C_TX_ABRT_SOURCE_SBYTE_ACKDET ((uint32_t)0x00000080)¾DI2C_TX_ABRT_SOURCE_HS_NORSTRT ((uint32_t)0x00000100)¿DI2C_TX_ABRT_SOURCE_SBYTE_NORSTRT ((uint32_t)0x00000200)ÀDI2C_TX_ABRT_SOURCE_10B_RD_NORSTRT ((uint32_t)0x00000400)ÁDI2C_TX_ABRT_SOURCE_MASTER_DIS ((uint32_t)0x00000800)ÂDI2C_TX_ABRT_SOURCE_ARB_LOST ((uint32_t)0x00001000)ÃDI2C_TX_ABRT_SOURCE_SLVFLUSH_TXFIFO ((uint32_t)0x00002000)ÄDI2C_TX_ABRT_SOURCE_SLV_ARBLOST ((uint32_t)0x00004000)ÅDI2C_TX_ABRT_SOURCE_SLVRD_INTX ((uint32_t)0x00008000)ÆDI2C_TX_ABRT_SOURCE_USER_ABRT ((uint32_t)0x00010000)ÈDI2C_TX_ABRT_SOURCE_TX_FLUSH_CNT ((uint32_t)0xff000000)ËDI2C_SLV_DATA_NACK_ONLY ((uint32_t)0x00000001)ÎDI2C_DMA_CR_RDMAE ((uint32_t)0x00000001)ÏDI2C_DMA_CR_TDMAE ((uint32_t)0x00000002)ÒDI2C_DMA_TDLR ((uint32_t)0x00000007)ÕDI2C_DMA_RDLR ((uint32_t)0x00000007)ØDI2C_SDA_SETUP ((uint32_t)0x000000ff)ÛDI2C_ACK_GENERAL_CALL ((uint32_t)0x00000001)ÞDI2C_ENABLE_STATUS_IC_EN ((uint32_t)0x00000001)ßDI2C_ENABLE_STATUS_SLV_RX_ABORTED ((uint32_t)0x00000002)àDI2C_ENABLE_STATUS_SLV_FIFO_FILLED_AND_FLUSHED ((uint32_t)0x00000004)ãDI2C_FS_SPKLEN ((uint32_t)0x0000000ff)æDI2C_HS_SPKLEN ((uint32_t)0x0000000ff)éDI2C_COMP_PARAM1_APB_DATA_WIDTH ((uint32_t)0x000000003)êDI2C_COMP_PARAM1_MAX_SPEED_MODE ((uint32_t)0x000000006)ëDI2C_COMP_PARAM1_HC_COUNT_VALUES ((uint32_t)0x000000010)ìDI2C_COMP_PARAM1_INTR_IO ((uint32_t)0x000000020)íDI2C_COMP_PARAM1_HAS_DMA ((uint32_t)0x000000040)îDI2C_COMP_PARAM1_ADD_ENCODED_PARAMS ((uint32_t)0x000000080)ïDI2C_COMP_PARAM1_RX_BUFFER_DEPTH ((uint32_t)0x00000ff00)ðDI2C_COMP_PARAM1_TX_BUFFER_DEPTH ((uint32_t)0x000ff0000)óDI2C_COMP_VERSION ((uint32_t)0xffffffffff)öDI2C_COMP_TYPE ((uint32_t)0xffffffffff)–EANAC_LP_REG_SYNC_3V_Pos (0)—EANAC_LP_REG_SYNC_3V_Msk (0x1ul << ANAC_LP_REG_SYNC_3V_Pos)˜EANAC_LP_REG_SYNC_3V_TRG_Pos (1)™EANAC_LP_REG_SYNC_3V_TRG_Msk (0x1ul << ANAC_LP_REG_SYNC_3V_TRG_Pos)›EANAC_FL_SLEEP_MODE_SEL_Pos (0)œEANAC_FL_SLEEP_MODE_SEL_Msk (0x3ul << ANAC_FL_SLEEP_MODE_SEL_Pos)EANAC_FL_EXT_WAKEUP_SEL_Pos_3v (2)žEANAC_FL_EXT_WAKEUP_SEL_Msk_3v (0x1ul << ANAC_FL_EXT_WAKEUP_SEL_Pos_3v)ŸEANAC_FL_SLEEP_CNT_EN_Pos (3) EANAC_FL_SLEEP_CNT_EN_Msk (0x1ul << ANAC_FL_SLEEP_CNT_EN_Pos)¡EANAC_FL_CPU_RETENTION_EN_Pos (4)¢EANAC_FL_CPU_RETENTION_EN_Msk (0x1ul << ANAC_FL_CPU_RETENTION_EN_Pos)£EANAC_FL_LDO_ISOLATE_EN_Pos (5)¤EANAC_FL_LDO_ISOLATE_EN_Msk (0x1ul << ANAC_FL_LDO_ISOLATE_EN_Pos)¥EANAC_FL_RCL_GATE_EN_Pos (6)¦EANAC_FL_RCL_GATE_EN_Msk (0x1ul << ANAC_FL_RCL_GATE_EN_Pos)§EANAC_FL_PWR_CTL_EN_Pos (7)¨EANAC_FL_PWR_CTL_EN_Msk (0x1ul << ANAC_FL_PWR_CTL_EN_Pos)©EANAC_FL_FLASH_BP_EN_Pos (12)ªEANAC_FL_FLASH_BP_EN_Msk (0x1ul << ANAC_FL_FLASH_BP_EN_Pos)«EANAC_FL_FLASH_LP_EN_Pos (13)¬EANAC_FL_FLASH_LP_EN_Msk (0x1ul << ANAC_FL_FLASH_LP_EN_Pos)­EANAC_FL_BUCK_BP_EN_Pos (14)®EANAC_FL_BUCK_BP_EN_Msk (0x1ul << ANAC_FL_BUCK_BP_EN_Pos)¯EANAC_FL_BUCK_EN_Pos (15)°EANAC_FL_BUCK_EN_Msk (0x1ul << ANAC_FL_BUCK_EN_Pos)±EANAC_FL_DPLL_EN_Pos (16)²EANAC_FL_DPLL_EN_Msk (0x1ul << ANAC_FL_DPLL_EN_Pos)³EANAC_FL_RCH_EN_Pos (17)´EANAC_FL_RCH_EN_Msk (0x1ul << ANAC_FL_RCH_EN_Pos)µEANAC_FL_XTH_EN_Pos (18)¶EANAC_FL_XTH_EN_Msk (0x1ul << ANAC_FL_XTH_EN_Pos)·EANAC_FL_XTAL32K_EN_Pos_3v (19)¸EANAC_FL_XTAL32K_EN_Msk_3v (0x1ul << ANAC_FL_XTAL32K_EN_Pos_3v)¹EANAC_FL_RC32K_EN_Pos_3v (20)ºEANAC_FL_RC32K_EN_Msk_3v (0x1ul << ANAC_FL_RC32K_EN_Pos_3v)»EANAC_FL_LDO_HP_EN_Pos (22)¼EANAC_FL_LDO_HP_EN_Msk (0x1ul << ANAC_FL_LDO_HP_EN_Pos)½EANAC_FL_PMU_EN_Pos (23)¾EANAC_FL_PMU_EN_Msk (0x1ul << ANAC_FL_PMU_EN_Pos)¿EANAC_SRAM0_POWER_CTL_Pos (24)ÀEANAC_SRAM0_POWER_CTL_Msk (0x1ul << ANAC_SRAM0_POWER_CTL_Pos)ÁEANAC_SRAM1_POWER_CTL_Pos (25)ÂEANAC_SRAM1_POWER_CTL_Msk (0x1ul << ANAC_SRAM1_POWER_CTL_Pos)ÃEANAC_CPU_POWER_CTL_Pos (26)ÄEANAC_CPU_POWER_CTL_Msk (0x1ul << ANAC_CPU_POWER_CTL_Pos)ÅEANAC_PHY_POWER_CTL_Pos (27)ÆEANAC_PHY_POWER_CTL_Msk (0x1ul << ANAC_PHY_POWER_CTL_Pos)ÇEANAC_LL_SRAM_POWER_CTL_Pos (28)ÈEANAC_LL_SRAM_POWER_CTL_Msk (0x1ul << ANAC_LL_SRAM_POWER_CTL_Pos)ÉEANAC_FLASH_POWER_CTL_Pos (29)ÊEANAC_FLASH_POWER_CTL_Msk (0x1ul << ANAC_FLASH_POWER_CTL_Pos)ËEANAC_LDO_POWER_CTL_Pos (30)ÌEANAC_LDO_POWER_CTL_Msk (0x1ul << ANAC_LDO_POWER_CTL_Pos)ÍEANAC_LDOL_POWER_CTL_Pos (31)ÎEANAC_LDOL_POWER_CTL_Msk (0x1ul << ANAC_LDOL_POWER_CTL_Pos)ÒEANAC_INT_LP_INT_EN_Pos (0)ÓEANAC_INT_LP_INT_EN_Msk (0x1ul << ANAC_INT_LP_INT_EN_Pos)ÔEANAC_INT_DP_FLAG_Pos (1)ÕEANAC_INT_DP_FLAG_Msk (0x1ul << ANAC_INT_DP_FLAG_Pos)ÖEANAC_INT_STANDBY_M1_FLAG_Pos (2)×EANAC_INT_STANDBY_M1_FLAG_Msk (0x1ul << ANAC_INT_STANDBY_M1_FLAG_Pos)ØEANAC_INT_STANDBY_M0_FLAG_Pos (3)ÙEANAC_INT_STANDBY_M0_FLAG_Msk (0x1ul << ANAC_INT_STANDBY_M0_FLAG_Pos)ÚEANAC_INT_SRAM_RET_FLAG_Pos (4)ÛEANAC_INT_SRAM_RET_FLAG_Msk (0x1ul << ANAC_INT_SRAM_RET_FLAG_Pos)ÜEANAC_INT_SLEEP_TMR_INT_EN_Pos (16)ÝEANAC_INT_SLEEP_TMR_INT_EN_Msk (0x1ul << ANAC_INT_SLEEP_TMR_INT_EN_Pos)ÞEANAC_INT_SLEEP_TMR0_Pos (17)ßEANAC_INT_SLEEP_TMR0_Msk (0x1ul << ANAC_INT_SLEEP_TMR0_Pos)àEANAC_INT_SLEEP_TMR1_Pos (18)áEANAC_INT_SLEEP_TMR1_Msk (0x1ul << ANAC_INT_SLEEP_TMR1_Pos)âEANAC_INT_SLEEP_TMR2_Pos (19)ãEANAC_INT_SLEEP_TMR2_Msk (0x1ul << ANAC_INT_SLEEP_TMR2_Pos)äEANAC_INT_SLEEP_TMR_WK_EN_Pos (20)åEANAC_INT_SLEEP_TMR_WK_EN_Msk (0x1ul << ANAC_INT_SLEEP_TMR_WK_EN_Pos)èEANAC_32KCLK_DLY_TIME_Pos (0)éEANAC_32KCLK_DLY_TIME_Msk (0x3FFul << ANAC_32KCLK_DLY_TIME_Pos)êEANAC_32KCLK_DLY_EN_Pos (10)ëEANAC_32KCLK_DLY_EN_Msk (0x1ul << ANAC_32KCLK_DLY_EN_Pos)ìEANAC_HPLDO_RDY_BYPASS_Pos (11)íEANAC_HPLDO_RDY_BYPASS_Msk (0x1ul << ANAC_HPLDO_RDY_BYPASS_Pos)îEANAC_LPLDOH_DLY_TIME_Pos_3v (16)ïEANAC_LPLDOH_DLY_TIME_Msk_3v (0x3FFul << ANAC_LPLDOH_DLY_TIME_Pos_3v)òEANAC_PTAT_CORE_EN_Pos (0)óEANAC_PTAT_CORE_EN_Msk (0x1ul << ANAC_PTAT_CORE_EN_Pos)ôEANAC_PTAT_TMP_TRIM_Pos (1)õEANAC_PTAT_TMP_TRIM_Msk (0x3ul << ANAC_PTAT_TMP_TRIM_Pos)öEANAC_PTAT_TRIM_Pos (3)÷EANAC_PTAT_TRIM_Msk (0x7ul << ANAC_PTAT_TRIM_Pos)øEANAC_PTAT_FLT_SHIFT_EN_Pos (6)ùEANAC_PTAT_FLT_SHIFT_EN_Msk (0x1ul << ANAC_PTAT_FLT_SHIFT_EN_Pos)úEANAC_PTAT_FLT_ACT_EN_Pos (7)ûEANAC_PTAT_FLT_ACT_EN_Msk (0x1ul << ANAC_PTAT_FLT_ACT_EN_Pos)üEANAC_POLY_EN_Pos (8)ýEANAC_POLY_EN_Msk (0x1ul << ANAC_POLY_EN_Pos)þEANAC_IPOLY_TRIM_Pos (16)ÿEANAC_IPOLY_TRIM_Msk (0x3ul << ANAC_IPOLY_TRIM_Pos)‚FANAC_HPLDO_EN_Pos (0)ƒFANAC_HPLDO_EN_Msk (0x1ul << ANAC_HPLDO_EN_Pos)„FANAC_HPLDO_BYPASS_Pos (2)…FANAC_HPLDO_BYPASS_Msk (0x1ul << ANAC_HPLDO_BYPASS_Pos)†FANAC_HPLDO_TRIM_Pos (3)‡FANAC_HPLDO_TRIM_Msk (0xFul << ANAC_HPLDO_TRIM_Pos)ˆFANAC_HPLDO_SEL_Pos (9)‰FANAC_HPLDO_SEL_Msk (0x1ul << ANAC_HPLDO_SEL_Pos)ŠFANAC_HPLDO_FLASHLDO_BP_Pos_3v (16)‹FANAC_HPLDO_FLASHLDO_BP_Msk_3v (0x1ul << ANAC_HPLDO_FLASHLDO_BP_Pos_3v)ŒFANAC_HPLDO_FLASHLDO_EN_Pos_3v (17)FANAC_HPLDO_FLASHLDO_EN_Msk_3v (0x1ul << ANAC_HPLDO_FLASHLDO_EN_Pos_3v)ŽFANAC_HPLDO_FLASHLDO_LP_EN_Pos (18)FANAC_HPLDO_FLASHLDO_LP_EN_Msk (0x1ul << ANAC_HPLDO_FLASHLDO_LP_EN_Pos)FANAC_HPLDO_FLASHLDO_CAP_SEL_Pos (19)‘FANAC_HPLDO_FLASHLDO_CAP_SEL_Msk (0x1ul << ANAC_HPLDO_FLASHLDO_CAP_SEL_Pos)’FANAC_HPLDO_FLASHLDO_TRIM_Pos (20)“FANAC_HPLDO_FLASHLDO_TRIM_Msk (0x7ul << ANAC_HPLDO_FLASHLDO_TRIM_Pos)•FANAC_LPLDO_L_EN_Pos (0)–FANAC_LPLDO_L_EN_Msk (0x1ul << ANAC_LPLDO_L_EN_Pos)—FANAC_LPLDO_L_DVDD_SEL_Pos (1)˜FANAC_LPLDO_L_DVDD_SEL_Msk (0xFul << ANAC_LPLDO_L_DVDD_SEL_Pos)™FANAC_LPLDO_H_EN_Pos_3v (16)šFANAC_LPLDO_H_EN_Msk_3v (0x1ul << ANAC_LPLDO_H_EN_Pos_3v)›FANAC_LPLDO_H_DVDD_SEL_Pos_3v (17)œFANAC_LPLDO_H_DVDD_SEL_Msk_3v (0xFul << ANAC_LPLDO_H_DVDD_SEL_Pos_3v)FANAC_LPLDO_H_REF_TRIM_Pos_3v (21)žFANAC_LPLDO_H_REF_TRIM_Msk_3v (0x7ul << ANAC_LPLDO_H_REF_TRIM_Pos_3v)ŸFANAC_LPLDO_H_MODE_SEL_Pos_3v (24) FANAC_LPLDO_H_MODE_SEL_Msk_3v (0x1ul << ANAC_LPLDO_H_MODE_SEL_Pos_3v)£FANAC_ANA_LDO_EN_Pos (0)¤FANAC_ANA_LDO_EN_Msk (0x1ul << ANAC_ANA_LDO_EN_Pos)¥FANAC_ANA_LDO_TRIM_Pos (3)¦FANAC_ANA_LDO_TRIM_Msk (0xFul << ANAC_ANA_LDO_TRIM_Pos)¨FANAC_FSYN_LDO_EN_Pos (0)©FANAC_FSYN_LDO_EN_Msk (0x1ul << ANAC_FSYN_LDO_EN_Pos)ªFANAC_FSYN_LDO_TRIM_Pos (3)«FANAC_FSYN_LDO_TRIM_Msk (0xFul << ANAC_FSYN_LDO_TRIM_Pos)­FANAC_HP_DVDD_PD_Pos (0)®FANAC_HP_DVDD_PD_Msk (0x1ul << ANAC_HP_DVDD_PD_Pos)¯FANAC_HP_DVDD_EN_Pos (1)°FANAC_HP_DVDD_EN_Msk (0x1ul << ANAC_HP_DVDD_EN_Pos)±FANAC_DVDD_SRAM0_EN_Pos (2)²FANAC_DVDD_SRAM0_EN_Msk (0x1ul << ANAC_DVDD_SRAM0_EN_Pos)³FANAC_DVDD_SRAM1_EN_Pos (3)´FANAC_DVDD_SRAM1_EN_Msk (0x1ul << ANAC_DVDD_SRAM1_EN_Pos)µFANAC_DVDD_LPLDO_EN_Pos (4)¶FANAC_DVDD_LPLDO_EN_Msk (0x1ul << ANAC_DVDD_LPLDO_EN_Pos)·FANAC_VDD_FLASH_EN_Pos (5)¸FANAC_VDD_FLASH_EN_Msk (0x1ul << ANAC_VDD_FLASH_EN_Pos)¹FANAC_DVDD_DLL_EN_Pos (6)ºFANAC_DVDD_DLL_EN_Msk (0x1ul << ANAC_DVDD_DLL_EN_Pos)»FANAC_DVDD_PHY_EN_Pos (7)¼FANAC_DVDD_PHY_EN_Msk (0x1ul << ANAC_DVDD_PHY_EN_Pos)½FANAC_DVDD_CPU_EN_Pos (8)¾FANAC_DVDD_CPU_EN_Msk (0x1ul << ANAC_DVDD_CPU_EN_Pos)ÁFANAC_BUCK_BYPASS_EN_Pos_3v (0)ÂFANAC_BUCK_BYPASS_EN_Msk_3v (0x1ul << ANAC_BUCK_BYPASS_EN_Pos_3v)ÃFANAC_BUCK_EN_Pos_3v (1)ÄFANAC_BUCK_EN_Msk_3v (0x1ul << ANAC_BUCK_EN_Pos_3v)ÅFANAC_BUCK_VOUT_Pos_3v (2)ÆFANAC_BUCK_VOUT_Msk_3v (0xful << ANAC_BUCK_VOUT_Pos_3v)ÇFANAC_BUCK_IMAX_Pos_3v (6)ÈFANAC_BUCK_IMAX_Msk_3v (0x7ul << ANAC_BUCK_IMAX_Pos_3v)ÉFANAC_BUCK_IMAX_CAL_Pos_3v (9)ÊFANAC_BUCK_IMAX_CAL_Msk_3v (0x1Ful << ANAC_BUCK_IMAX_CAL_Pos_3v)ËFANAC_BUCK_ZERO_CAL_Pos_3v (14)ÌFANAC_BUCK_ZERO_CAL_Msk_3v (0x1Ful << ANAC_BUCK_ZERO_CAL_Pos_3v)ÍFANAC_BUCK_DLY_MODE_EN_Pos_3v (19)ÎFANAC_BUCK_DLY_MODE_EN_Msk_3v (0x1ul << ANAC_BUCK_DLY_MODE_EN_Pos_3v)ÏFANAC_BUCK_TEST_EN_Pos (20)ÐFANAC_BUCK_TEST_EN_Msk (0x1ul << ANAC_BUCK_TEST_EN_Pos)ÑFANAC_BUCK_DEBOUNCE_EN_Pos_3v (21)ÒFANAC_BUCK_DEBOUNCE_EN_Msk_3v (0x1ul << ANAC_BUCK_DEBOUNCE_EN_Pos_3v)ÓFANAC_BUCK_CAL_EN_Pos_3v (22)ÔFANAC_BUCK_CAL_EN_Msk_3v (0x3ul << ANAC_BUCK_CAL_EN_Pos_3v)ÕFANAC_BUCK_CAL_OUT_Pos (24)ÖFANAC_BUCK_CAL_OUT_Msk (0x1ul << ANAC_BUCK_CAL_OUT_Pos)×FANAC_BUCK_VOL_LIMIT_EN_Pos_3v (25)ØFANAC_BUCK_VOL_LIMIT_EN_Msk_3v (0x1ul << ANAC_BUCK_VOL_LIMIT_EN_Pos_3v)ÛFANAC_ADC_LDO_EN_Pos (0)ÜFANAC_ADC_LDO_EN_Msk (0x1ul << ANAC_ADC_LDO_EN_Pos)ÝFANAC_ADC_LDO_TRIM_Pos (3)ÞFANAC_ADC_LDO_TRIM_Msk (0xFul << ANAC_ADC_LDO_TRIM_Pos)áFANAC_RFFE_LDO_EN_Pos (0)âFANAC_RFFE_LDO_EN_Msk (0x1ul << ANAC_RFFE_LDO_EN_Pos)ãFANAC_RFFE_LDO_TRIM_Pos (3)äFANAC_RFFE_LDO_TRIM_Msk (0xFul << ANAC_RFFE_LDO_TRIM_Pos)æFANAC_VCO_LDO_EN_Pos (0)çFANAC_VCO_LDO_EN_Msk (0x1ul << ANAC_VCO_LDO_EN_Pos)èFANAC_VCO_LDO_TRIM_Pos (3)éFANAC_VCO_LDO_TRIM_Msk (0xFul << ANAC_VCO_LDO_TRIM_Pos)ìFANAC_DFT_BUF_BYPASS_Pos (0)íFANAC_DFT_BUF_BYPASS_Msk (0x1ul << ANAC_DFT_BUF_BYPASS_Pos)îFANAC_DFT_FLAG_SEL_Pos (1)ïFANAC_DFT_FLAG_SEL_Msk (0x3ul << ANAC_DFT_FLAG_SEL_Pos)ðFANAC_DFT_CLK_SEL_Pos (3)ñFANAC_DFT_CLK_SEL_Msk (0x7ul << ANAC_DFT_CLK_SEL_Pos)òFANAC_DFT_I_SEL_Pos (6)óFANAC_DFT_I_SEL_Msk (0x1ul << ANAC_DFT_I_SEL_Pos)ôFANAC_DFT_V_SEL_Pos (7)õFANAC_DFT_V_SEL_Msk (0xFul << ANAC_DFT_V_SEL_Pos)öFANAC_DFT_FLAG_OUTPUT_EN_Pos (11)÷FANAC_DFT_FLAG_OUTPUT_EN_Msk (0x1ul << ANAC_DFT_FLAG_OUTPUT_EN_Pos)øFANAC_DFT_CLK_OUTPUT_EN_Pos (12)ùFANAC_DFT_CLK_OUTPUT_EN_Msk (0x1ul << ANAC_DFT_CLK_OUTPUT_EN_Pos)úFANAC_DFT_I_OUTPUT_EN_Pos (13)ûFANAC_DFT_I_OUTPUT_EN_Msk (0x1ul << ANAC_DFT_I_OUTPUT_EN_Pos)üFANAC_DFT_V_OUTPUT_EN_Pos (14)ýFANAC_DFT_V_OUTPUT_EN_Msk (0x1ul << ANAC_DFT_V_OUTPUT_EN_Pos)þFANAC_DFT_PAD_TEST_SEL_Pos (15)ÿFANAC_DFT_PAD_TEST_SEL_Msk (0x3ul << ANAC_DFT_PAD_TEST_SEL_Pos)€GANAC_DFT_BATTERY_TEST_EN_Pos (22)GANAC_DFT_BATTERY_TEST_EN_Msk (0x1ul << ANAC_DFT_BATTERY_TEST_EN_Pos)‚GANAC_DFT_BATTERY_TEST_SEL_Pos (23)ƒGANAC_DFT_BATTERY_TEST_SEL_Msk (0x1ul << ANAC_DFT_BATTERY_TEST_SEL_Pos)„GANAC_DFT_BATTERY_TEST_TRIM_Pos (24)…GANAC_DFT_BATTERY_TEST_TRIM_Msk (0xfful << ANAC_DFT_BATTERY_TEST_TRIM_Pos)ˆGANAC_MISC_RST_VREF_TRIM_Pos_3v (0)‰GANAC_MISC_RST_VREF_TRIM_Msk_3v (0x7ul << ANAC_MISC_RST_VREF_TRIM_Pos_3v)ŠGANAC_MISC_PMU_LDO_TST_Pos (3)‹GANAC_MISC_PMU_LDO_TST_Msk (0x1ul << ANAC_MISC_PMU_LDO_TST_Pos)ŒGANAC_MISC_PMU_VBG_BUF_EN_Pos (4)GANAC_MISC_PMU_VBG_BUF_EN_Msk (0x1ul << ANAC_MISC_PMU_VBG_BUF_EN_Pos)ŽGANAC_MISC_LPLDO_LEVEL_SHIFT_EN_Pos_3v (6)GANAC_MISC_LPLDO_LEVEL_SHIFT_EN_Msk_3v (0x1ul << ANAC_MISC_LPLDO_LEVEL_SHIFT_EN_Pos_3v)GANAC_MISC_HPLDO_LEVEL_SHIFT_EN_Pos (7)‘GANAC_MISC_HPLDO_LEVEL_SHIFT_EN_Msk (0x1ul << ANAC_MISC_HPLDO_LEVEL_SHIFT_EN_Pos)’GANAC_MISC_FLASH_PAD_PUEN_Pos (14)“GANAC_MISC_FLASH_PAD_PUEN_Msk (0x3Ful << ANAC_MISC_FLASH_PAD_PUEN_Pos)”GANAC_MISC_FLASH_PAD_PDEN_Pos (20)•GANAC_MISC_FLASH_PAD_PDEN_Msk (0x3Ful << ANAC_MISC_FLASH_PAD_PDEN_Pos)–GANAC_MISC_USB_EN_Pos (26)—GANAC_MISC_USB_EN_Msk (0x1ul << ANAC_MISC_USB_EN_Pos)˜GANAC_MISC_USB_DP_PU_Pos (27)™GANAC_MISC_USB_DP_PU_Msk (0x1ul << ANAC_MISC_USB_DP_PU_Pos)šGANAC_MISC_USB_DM_PU_Pos (28)›GANAC_MISC_USB_DM_PU_Msk (0x1ul << ANAC_MISC_USB_DM_PU_Pos)ŸGANAC_ACT_32K_EN_Pos (0) GANAC_ACT_32K_EN_Msk (0x1ul << ANAC_ACT_32K_EN_Pos)¡GANAC_ACT_32K_SEL_Pos (1)¢GANAC_ACT_32K_SEL_Msk (0x1ul << ANAC_ACT_32K_SEL_Pos)£GANAC_ACT_32K_UP_DONE_Pos (3)¤GANAC_ACT_32K_UP_DONE_Msk (0x1ul << ANAC_ACT_32K_UP_DONE_Pos)¥GANAC_ACT_32K_FINE_OFFSET_Pos (12)¦GANAC_ACT_32K_FINE_OFFSET_Msk (0x3FFul << ANAC_ACT_32K_FINE_OFFSET_Pos)§GANAC_ACT_32K_FINE_CORRECT_Pos (22)¨GANAC_ACT_32K_FINE_CORRECT_Msk (0x3FFul << ANAC_ACT_32K_FINE_CORRECT_Pos)«GANAC_CPU_REMAP_ADR_Pos (0)¬GANAC_CPU_REMAP_ADR_Msk (0xFFFFFFul << ANAC_CPU_REMAP_ADR_Pos)­GANAC_CPU_ADR_REMAP_EN_Pos (31)®GANAC_CPU_ADR_REMAP_EN_Msk (0x1ul << ANAC_CPU_ADR_REMAP_EN_Pos)±GANAC_RCL_HW_CAL_TIME_Pos (0)²GANAC_RCL_HW_CAL_TIME_Msk (0xFFul << ANAC_RCL_HW_CAL_TIME_Pos)³GANAC_RCL_HW_CAL_EN_Pos (8)´GANAC_RCL_HW_CAL_EN_Msk (0x1ul << ANAC_RCL_HW_CAL_EN_Pos)µGANAC_RCL_HW_CAL_BUSY_Pos (9)¶GANAC_RCL_HW_CAL_BUSY_Msk (0x1ul << ANAC_RCL_HW_CAL_BUSY_Pos)ÒGEFUSE_CTL_EFUSE_EN_Pos (0)ÓGEFUSE_CTL_EFUSE_EN_Msk (0x1ul << EFUSE_CTL_EFUSE_EN_Pos)ÕGEFUSE_CTL_THR_DVDD_Pos (1)ÖGEFUSE_CTL_THR_DVDD_Msk (0x1ul << EFUSE_CTL_THR_DVDD_Pos)ØGEFUSE_CTL_TAEN_RD_CTL_Pos (2)ÙGEFUSE_CTL_TAEN_RD_CTL_Msk (0x1ul << EFUSE_CTL_TAEN_RD_CTL_Pos)ÛGEFUSE_CTL_THR_RD_CTL_Pos (3)ÜGEFUSE_CTL_THR_RD_CTL_Msk (0x1ul << EFUSE_CTL_THR_RD_CTL_Pos)ÞGEFUSE_CTL_TRD_CTL_Pos (4)ßGEFUSE_CTL_TRD_CTL_Msk (0x1ul << EFUSE_CTL_TRD_CTL_Pos)áGEFUSE_CTL_TSR_RD_CTL_Pos (5)âGEFUSE_CTL_TSR_RD_CTL_Msk (0x1ul << EFUSE_CTL_TSR_RD_CTL_Pos)äGEFUSE_CTL_TSR_DVDD_CTL_Pos (6)åGEFUSE_CTL_TSR_DVDD_CTL_Msk (0x1ul << EFUSE_CTL_TSR_DVDD_CTL_Pos)çGEFUSE_CTL_THP_RD_CTL_Pos (7)èGEFUSE_CTL_THP_RD_CTL_Msk (0x1ul << EFUSE_CTL_THP_RD_CTL_Pos)êGEFUSE_CTL_THP_PG_AVDD_CTL_Pos (8)ëGEFUSE_CTL_THP_PG_AVDD_CTL_Msk (0x1ul << EFUSE_CTL_THP_PG_AVDD_CTL_Pos)íGEFUSE_CTL_TAEN_PGM_CTL_Pos (9)îGEFUSE_CTL_TAEN_PGM_CTL_Msk (0x1ul << EFUSE_CTL_TAEN_PGM_CTL_Pos)ðGEFUSE_CTL_THP_PGM_CTL_Pos (10)ñGEFUSE_CTL_THP_PGM_CTL_Msk (0x1ul << EFUSE_CTL_THP_PGM_CTL_Pos)óGEFUSE_CTL_TPGM_CTL_Pos (11)ôGEFUSE_CTL_TPGM_CTL_Msk (0x1ul << EFUSE_CTL_TPGM_CTL_Pos)öGEFUSE_CTL_TSP_PGM_CTL_Pos (12)÷GEFUSE_CTL_TSP_PGM_CTL_Msk (0x1ul << EFUSE_CTL_TSP_PGM_CTL_Pos)ùGEFUSE_CTL_TSP_PG_AVDD_CTL_Pos (13)úGEFUSE_CTL_TSP_PG_AVDD_CTL_Msk (0x1ul << EFUSE_CTL_TSP_PG_AVDD_CTL_Pos)üGEFUSE_CTL_TSP_RD_CTL_Pos (14)ýGEFUSE_CTL_TSP_TSP_RD_CTL_Msk (0x1ul << EFUSE_CTL_TSP_RD_CTL_Pos)€HEFUSE_ADDR_EFUSEADDR_ADR_Pos (0)HEFUSE_ADDR_EFUSEADDR_ADR_Msk (0xfful << EFUSE_ADDR_EFUSEADDR_ADR_Pos)„HEFUSE_DAT_EFUSEDAT_DAT_Pos (0)…HEFUSE_DAT_EFUSEDAT_DAT_Msk (0xfful << EFUSE_DAT_EFUSEDAT_DAT_Pos)‡HEFUSE_DAT_EFUSEDAT_DAT_CONFIRM_Pos (8)ˆHEFUSE_DAT_EFUSEDAT_DAT_CONFIRM_Msk (0xfful << EFUSE_DAT_EFUSEDAT_DAT_CONFIRM_Pos)‹HEFUSE_VDD_DVDD_REG_Pos (0)ŒHEFUSE_VDD_DVDD_REG_Msk (0x1ul << EFUSE_VDD_DVDD_REG_Pos)ŽHEFUSE_VDD_AVDD_REG_Pos (1)HEFUSE_VDD_AVDD_REG_Msk (0x1ul << EFUSE_VDD_AVDD_REG_Pos)’HEFUSE_CMD_EFUSECMD_CMD_Pos (0)“HEFUSE_CMD_EFUSECMD_CMD_Msk (0x3ul << EFUSE_CMD_EFUSECMD_CMD_Pos)–HEFUSE_TRG_EFUSETRG_GO_Pos (0)—HEFUSE_TRG_EFUSETRG_GO_Msk (0x1ul << EFUSE_TRG_EFUSETRG_GO_Pos)šHEFUSE_PROG_TIMING1_TSP_RD_SET_Pos (0)›HEFUSE_PROG_TIMING1_TSP_RD_SET_Msk (0x1fful << EFUSE_PROG_TIMING1_TSP_RD_SET_Pos)HEFUSE_PROG_TIMING1_TSP_PG_AVDD_SET_Pos (9)žHEFUSE_PROG_TIMING1_TSP_PG_AVDD_SET_Msk (0x1fful << EFUSE_PROG_TIMING1_TSP_PG_AVDD_SET_Pos) HEFUSE_PROG_TIMING1_TSP_PGM_SET_Pos (18)¡HEFUSE_PROG_TIMING1_TSP_PGM_SET_Msk (0x1fful << EFUSE_PROG_TIMING1_TSP_PGM_SET_Pos)¤HEFUSE_PROG_TIMING2_TPGM_SET_Pos (0)¥HEFUSE_PROG_TIMING2_TPGM_SET_Msk (0x1fful << EFUSE_PROG_TIMING2_TPGM_SET_Pos)§HEFUSE_PROG_TIMING2_THP_PGM_SET_Pos (9)¨HEFUSE_PROG_TIMING2_THP_PGM_SET_Msk (0x1fful << EFUSE_PROG_TIMING2_THP_PGM_SET_Pos)ªHEFUSE_PROG_TIMING2_TAEN_PGM_SET_Pos (18)«HEFUSE_PROG_TIMING2_TAEN_PGM_SET_Msk (0x1fful << EFUSE_PROG_TIMING2_TAEN_PGM_SET_Pos)®HEFUSE_PROG_TIMING3_THP_PG_AVDD_SET_Pos (0)¯HEFUSE_PROG_TIMING3_THP_PG_AVDD_SET_Msk (0x1fful << EFUSE_PROG_TIMING3_THP_PG_AVDD_SET_Pos)±HEFUSE_PROG_TIMING3_THP_RD_SET_Pos (9)²HEFUSE_PROG_TIMING3_THP_RD_SET_Msk (0x1fful << EFUSE_PROG_TIMING3_THP_RD_SET_Pos)µHEFUSE_READ_TIMING4_TSR_DVDD_SET_Pos (0)¶HEFUSE_READ_TIMING4_TSR_DVDD_SET_Msk (0x1fful << EFUSE_READ_TIMING4_TSR_DVDD_SET_Pos)¸HEFUSE_READ_TIMING4_TSR_RD_SET_Pos (9)¹HEFUSE_READ_TIMING4_TSR_RD_SET_Msk (0x1fful << EFUSE_READ_TIMING4_TSR_RD_SET_Pos)»HEFUSE_READ_TIMING4_TRD_SET_Pos (18)¼HEFUSE_READ_TIMING4_TRD_SET_Msk (0x1fful << EFUSE_READ_TIMING4_TRD_SET_Pos)¿HEFUSE_READ_TIMING5_THR_RD_SET_Pos (0)ÀHEFUSE_READ_TIMING5_THR_RD_SET_Msk (0x1fful << EFUSE_READ_TIMING5_THR_RD_SET_Pos)ÂHEFUSE_READ_TIMING5_TAEN_RD_SET_Pos (9)ÃHEFUSE_READ_TIMING5_TAEN_RD_SET_Msk (0x1fful << EFUSE_READ_TIMING5_TAEN_RD_SET_Pos)ÅHEFUSE_READ_TIMING5_THR_DVDD_SET_Pos (18)ÆHEFUSE_READ_TIMING5_THR_DVDD_SET_Msk (0x1fful << EFUSE_READ_TIMING5_THR_DVDD_SET_Pos)ÉHEFUSE_OP_ERROR_OP_ERROR_Pos (0)ÊHEFUSE_OP_ERROR_OP_ERROR_Msk (0x1ul << EFUSE_OP_ERROR_OP_ERROR_Pos)ÍHEFUSE_VERIFY_DEBUG1_VERIFY_DBG_KEY1_Pos (0)ÎHEFUSE_VERIFY_DEBUG1_VERIFY_DBG_KEY1_Msk (0xfffffffful << EFUSE_VERIFY_DEBUG1_VERIFY_DBG_KEY1_Pos)ÑHEFUSE_VERIFY_DEBUG2_VERIFY_DBG_KEY2_Pos (0)ÒHEFUSE_VERIFY_DEBUG2_VERIFY_DBG_KEY2_Msk (0xfffffffful << EFUSE_VERIFY_DEBUG2_VERIFY_DBG_KEY2_Pos)ÕHEFUSE_VERIFY_DEBUG3_VERIFY_DBG_KEY3_Pos (0)ÖHEFUSE_VERIFY_DEBUG3_VERIFY_DBG_KEY3_Msk (0xfffffffful << EFUSE_VERIFY_DEBUG3_VERIFY_DBG_KEY3_Pos)ÙHEFUSE_VERIFY_DEBUG4_VERIFY_DBG_KEY4_Pos (0)ÚHEFUSE_VERIFY_DEBUG4_VERIFY_DBG_KEY4_Msk (0xfffffffful << EFUSE_VERIFY_DEBUG4_VERIFY_DBG_KEY4_Pos)ÝHEFUSE_FLASH_PERMISSION_CTRL_Pos (0)ÞHEFUSE_FLASH_PERMISSION_CTRL_Msk (0x1ul << EFUSE_FLASH_PERMISSION_CTRL_Pos)’IUSB_DMA_REQUEST_Pos (0)“IUSB_DMA_REQUEST_Msk (0x1ul << USB_DMA_REQUEST_Pos)”IUSB_DMA_DIRECTION_Pos (1)•IUSB_DMA_DIRECTION_Msk (0x1ul << USB_DMA_DIRECTION_Pos)–IUSB_DMA_MODE_SEL_Pos (2)—IUSB_DMA_MODE_SEL_Msk (0x1ul << USB_DMA_MODE_SEL_Pos)˜IUSB_DMA_EP_NUM_Pos (4)™IUSB_DMA_EP_NUM_Msk (0xful << USB_DMA_EP_NUM_Pos)àIFSM5_SM_STP_Pos 6áIFSM5_SM_STP_Msk (0x1ul<<FSM5_SM_STP_Pos)âIFSM5_SM_TX_LATENCY_Pos 0ãIFSM5_SM_TX_LATENCY_Msk (0x3ful<<FSM5_SM_TX_LATENCY_Pos)åIFSM6_SM_RX_LATENCY_Pos 0æIFSM6_SM_RX_LATENCY_Msk (0xful<<FSM6_SM_RX_LATENCY_Pos)èIFSM13_SM_RX_PACKET_ADDR_1_Pos 16éIFSM13_SM_RX_PACKET_ADDR_1_Msk (0xfffful<<FSM13_SM_RX_PACKET_ADDR_1_Pos)êIFSM13_SM_TX_PACKET_ADDR_1_Pos 0ëIFSM13_SM_TX_PACKET_ADDR_1_Msk (0xfffful<<FSM13_SM_TX_PACKET_ADDR_1_Pos)íIFSM14_SM_RX_PACKET_ADDR_2_Pos 16îIFSM14_SM_RX_PACKET_ADDR_2_Msk (0xfffful<<FSM14_SM_RX_PACKET_ADDR_2_Pos)ïIFSM14_SM_TX_PACKET_ADDR_2_Pos 0ðIFSM14_SM_TX_PACKET_ADDR_2_Msk (0xfffful<<FSM14_SM_TX_PACKET_ADDR_2_Pos)òIFSM15_SM_RX_PACKET_ADDR_3_Pos 16óIFSM15_SM_RX_PACKET_ADDR_3_Msk (0xfffful<<FSM15_SM_RX_PACKET_ADDR_3_Pos)ôIFSM15_SM_TX_PACKET_ADDR_3_Pos 0õIFSM15_SM_TX_PACKET_ADDR_3_Msk (0xfffful<<FSM15_SM_TX_PACKET_ADDR_3_Pos)÷IFSM16_SM_RX_PACKET_ADDR_4_Pos 16øIFSM16_SM_RX_PACKET_ADDR_4_Msk (0xfffful<<FSM16_SM_RX_PACKET_ADDR_4_Pos)ùIFSM16_SM_TX_PACKET_ADDR_4_Pos 0úIFSM16_SM_TX_PACKET_ADDR_4_Msk (0xfffful<<FSM16_SM_TX_PACKET_ADDR_4_Pos)üIFSM17_SM_RX_PACKET_ADDR_5_Pos 16ýIFSM17_SM_RX_PACKET_ADDR_5_Msk (0xfffful<<FSM17_SM_RX_PACKET_ADDR_5_Pos)þIFSM17_SM_TX_PACKET_ADDR_5_Pos 0ÿIFSM17_SM_TX_PACKET_ADDR_5_Msk (0xfffful<<FSM17_SM_TX_PACKET_ADDR_5_Pos)JFSM18_SM_RX_PACKET_ADDR_6_Pos 16‚JFSM18_SM_RX_PACKET_ADDR_6_Msk (0xfffful<<FSM18_SM_RX_PACKET_ADDR_6_Pos)ƒJFSM18_SM_TX_PACKET_ADDR_6_Pos 0„JFSM18_SM_TX_PACKET_ADDR_6_Msk (0xfffful<<FSM18_SM_TX_PACKET_ADDR_6_Pos)†JFSM19_SM_RX_PACKET_ADDR_7_Pos 16‡JFSM19_SM_RX_PACKET_ADDR_7_Msk (0xfffful<<FSM19_SM_RX_PACKET_ADDR_7_Pos)ˆJFSM19_SM_TX_PACKET_ADDR_7_Pos 0‰JFSM19_SM_TX_PACKET_ADDR_7_Msk (0xfffful<<FSM19_SM_TX_PACKET_ADDR_7_Pos)‹JPHY1_PHY_DRV_RSP_BUF_FULL_Pos 22ŒJPHY1_PHY_DRV_RSP_BUF_FULL_Msk (0x1ul<<PHY1_PHY_DRV_RSP_BUF_FULL_Pos)JPHY1_PHY_DRV_RSP_BUF_EMPTY_Pos 21ŽJPHY1_PHY_DRV_RSP_BUF_EMPTY_Msk (0x1ul<<PHY1_PHY_DRV_RSP_BUF_EMPTY_Pos)JPHY1_PHY_DRV_CFG_BUF_ERROR_Pos 20JPHY1_PHY_DRV_CFG_BUF_ERROR_Msk (0x1ul<<PHY1_PHY_DRV_CFG_BUF_ERROR_Pos)‘JPHY1_PHY_DRV_CFG_BUF_FULL_Pos 19’JPHY1_PHY_DRV_CFG_BUF_FULL_Msk (0x1ul<<PHY1_PHY_DRV_CFG_BUF_FULL_Pos)“JPHY1_PHY_DRV_CFG_BUF_EMPTY_Pos 18”JPHY1_PHY_DRV_CFG_BUF_EMPTY_Msk (0x1ul<<PHY1_PHY_DRV_CFG_BUF_EMPTY_Pos)•JPHY1_IF_CLK_PRESCALE_Pos 13–JPHY1_IF_CLK_PRESCALE_Msk (0x1ful<<PHY1_IF_CLK_PRESCALE_Pos)—JPHY1_PHY_DRV_RSSI_REG_ADDR_Pos 5˜JPHY1_PHY_DRV_RSSI_REG_ADDR_Msk (0xfful<<PHY1_PHY_DRV_RSSI_REG_ADDR_Pos)™JPHY1_PHY_DRV_CFG_TRG_Pos 4šJPHY1_PHY_DRV_CFG_TRG_Msk (0x1ul<<PHY1_PHY_DRV_CFG_TRG_Pos)›JPHY1_PHY_DRV_CFG_REG_Pos 2œJPHY1_PHY_DRV_CFG_REG_Msk (0x3ul<<PHY1_PHY_DRV_CFG_REG_Pos)JPHY1_PHY_DRV_RSP_BUF_FLUSH_Pos 1žJPHY1_PHY_DRV_RSP_BUF_FLUSH_Msk (0x1ul<<PHY1_PHY_DRV_RSP_BUF_FLUSH_Pos)ŸJPHY1_PHY_DRV_CFG_BUF_FLUSH_Pos 0 JPHY1_PHY_DRV_CFG_BUF_FLUSH_Msk (0x1ul<<PHY1_PHY_DRV_CFG_BUF_FLUSH_Pos)¢JPHY2_PHY_DRV_RSP_BUF_ERROR_Pos 28£JPHY2_PHY_DRV_RSP_BUF_ERROR_Msk (0x1ul<<PHY2_PHY_DRV_RSP_BUF_ERROR_Pos)¤JPHY2_PHY_DRV_SEQ_RX_END_ADDR_Pos 21¥JPHY2_PHY_DRV_SEQ_RX_END_ADDR_Msk (0x7ful<<PHY2_PHY_DRV_SEQ_RX_END_ADDR_Pos)¦JPHY2_PHY_DRV_SEQ_TX_END_ADDR_Pos 14§JPHY2_PHY_DRV_SEQ_TX_END_ADDR_Msk (0x7ful<<PHY2_PHY_DRV_SEQ_TX_END_ADDR_Pos)¨JPHY2_PHY_DRV_SEQ_RX_STRT_ADDR_Pos 7©JPHY2_PHY_DRV_SEQ_RX_STRT_ADDR_Msk (0x7ful<<PHY2_PHY_DRV_SEQ_RX_STRT_ADDR_Pos)ªJPHY2_PHY_DRV_SEQ_TX_STRT_ADDR_Pos 0«JPHY2_PHY_DRV_SEQ_TX_STRT_ADDR_Msk (0x7ful<<PHY2_PHY_DRV_SEQ_TX_STRT_ADDR_Pos)­JPHY3_PHY_DRV_CFG_BUF_DIN_Pos 0®JPHY3_PHY_DRV_CFG_BUF_DIN_Msk (0xfffffffful<<PHY3_PHY_DRV_CFG_BUF_DIN_Pos)°JPHY4_PHY_DRV_RSP_BUF_DOUT_Pos 0±JPHY4_PHY_DRV_RSP_BUF_DOUT_Msk (0xfffffffful<<PHY4_PHY_DRV_RSP_BUF_DOUT_Pos)³JPHY5_PHY_DRV_SET_CHAN_REG_ADDR_Pos 0´JPHY5_PHY_DRV_SET_CHAN_REG_ADDR_Msk (0xfful<<PHY5_PHY_DRV_SET_CHAN_REG_ADDR_Pos)¶JINTR1_IC_RNG_DONE_Pos 3·JINTR1_IC_RNG_DONE_Msk (0x1ul<<INTR1_IC_RNG_DONE_Pos)¸JINTR1_IC_SEC_DONE_Pos 2¹JINTR1_IC_SEC_DONE_Msk (0x1ul<<INTR1_IC_SEC_DONE_Pos)ºJINTR1_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_Pos 1»JINTR1_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_Msk (0x1ul<<INTR1_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_Pos)¼JINTR1_IC_PHY_DRV_CFG_DONE_Pos 0½JINTR1_IC_PHY_DRV_CFG_DONE_Msk (0x1ul<<INTR1_IC_PHY_DRV_CFG_DONE_Pos)¿JINTCLR_IC_RNG_DONE_CLR_Pos 3ÀJINTCLR_IC_RNG_DONE_CLR_Msk (0x1ul<<INTCLR_IC_RNG_DONE_CLR_Pos)ÁJINTCLR_IC_SEC_DONE_CLR_Pos 2ÂJINTCLR_IC_SEC_DONE_CLR_Msk (0x1ul<<INTCLR_IC_SEC_DONE_CLR_Pos)ÃJINTCLR_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_CLR_Pos 1ÄJINTCLR_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_CLR_Msk (0x1ul<<INTCLR_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_CLR_Pos)ÅJINTCLR_IC_PHY_DRV_CFG_DONE_CLR_Pos 0ÆJINTCLR_IC_PHY_DRV_CFG_DONE_CLR_Msk (0x1ul<<INTCLR_IC_PHY_DRV_CFG_DONE_CLR_Pos)ÈJINTMSK_IC_RNG_DONE_MASK_Pos 3ÉJINTMSK_IC_RNG_DONE_MASK_Msk (0x1ul<<INTMSK_IC_RNG_DONE_MASK_Pos)ÊJINTMSK_IC_SEC_DONE_MASK_Pos 2ËJINTMSK_IC_SEC_DONE_MASK_Msk (0x1ul<<INTMSK_IC_SEC_DONE_MASK_Pos)ÌJINTMSK_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_MASK_Pos 1ÍJINTMSK_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_MASK_Msk (0x1ul<<INTMSK_IC_ACTTMR_CMPR_STRT_EVENT_IRQ_MASK_Pos)ÎJINTMSK_IC_PHY_DRV_CFG_DONE_MASK_Pos 0ÏJINTMSK_IC_PHY_DRV_CFG_DONE_MASK_Msk (0x1ul<<INTMSK_IC_PHY_DRV_CFG_DONE_MASK_Pos)ÑJINTR4_IC_CLR_IRQ_Pos 6ÒJINTR4_IC_CLR_IRQ_Msk (0x1ul<<INTR4_IC_CLR_IRQ_Pos)ÓJINTR4_IC_ONE_PULSE_FLAG_IRQ_Pos 5ÔJINTR4_IC_ONE_PULSE_FLAG_IRQ_Msk (0x1ul<<INTR4_IC_ONE_PULSE_FLAG_IRQ_Pos)ÕJINTR4_IC_MODE_IRQ_Pos 4ÖJINTR4_IC_MODE_IRQ_Msk (0x1ul<<INTR4_IC_MODE_IRQ_Pos)×JINTR4_IC_PULSE_CNT_Pos 0ØJINTR4_IC_PULSE_CNT_Msk (0xful<<INTR4_IC_PULSE_CNT_Pos)ÚJACTTMR1_ACTTMR_CMPR_MAX_EVENT_DIN_Pos 0ÛJACTTMR1_ACTTMR_CMPR_MAX_EVENT_DIN_Msk (0xfffffffful<<ACTTMR1_ACTTMR_CMPR_MAX_EVENT_DIN_Pos)ÝJACTTMR2_ACTTMR_DISABLE_FLG_Pos 2ÞJACTTMR2_ACTTMR_DISABLE_FLG_Msk (0x1ul<<ACTTMR2_ACTTMR_DISABLE_FLG_Pos)ßJACTTMR2_ACT_CLK_ACCUR_FLG_Pos 1àJACTTMR2_ACT_CLK_ACCUR_FLG_Msk (0x1ul<<ACTTMR2_ACT_CLK_ACCUR_FLG_Pos)áJACTTMR2_ACTTMR_CMPR_MAX_EVENT_EN_Pos 0âJACTTMR2_ACTTMR_CMPR_MAX_EVENT_EN_Msk (0x1ul<<ACTTMR2_ACTTMR_CMPR_MAX_EVENT_EN_Pos)äJACTTMR6_ACTTMR_CMPR_STRT_EVENT_DIN_Pos 0åJACTTMR6_ACTTMR_CMPR_STRT_EVENT_DIN_Msk (0xfffffffful<<ACTTMR6_ACTTMR_CMPR_STRT_EVENT_DIN_Pos)çJACTTMR7_ACTTMR_CPTUR_BUS_DOUT_Pos 0èJACTTMR7_ACTTMR_CPTUR_BUS_DOUT_Msk (0xfffffffful<<ACTTMR7_ACTTMR_CPTUR_BUS_DOUT_Pos)êJSECURE1_SEC_DECRYPT_EN_Pos 26ëJSECURE1_SEC_DECRYPT_EN_Msk (0x1ul<<SECURE1_SEC_DECRYPT_EN_Pos)ìJSECURE1_SEC_AD_LEN_Pos 19íJSECURE1_SEC_AD_LEN_Msk (0x7ful<<SECURE1_SEC_AD_LEN_Pos)îJSECURE1_SEC_MIC_LEN_Pos 17ïJSECURE1_SEC_MIC_LEN_Msk (0x3ul<<SECURE1_SEC_MIC_LEN_Pos)ðJSECURE1_SEC_VLD_MAC_Pos 10ñJSECURE1_SEC_VLD_MAC_Msk (0x7ful<<SECURE1_SEC_VLD_MAC_Pos)òJSECURE1_SEC_PKT_ENABLES_Pos 3óJSECURE1_SEC_PKT_ENABLES_Msk (0x7ful<<SECURE1_SEC_PKT_ENABLES_Pos)ôJSECURE1_SEC_MODE_Pos 1õJSECURE1_SEC_MODE_Msk (0x3ul<<SECURE1_SEC_MODE_Pos)öJSECURE1_SEC_ENABLE_Pos 0÷JSECURE1_SEC_ENABLE_Msk (0x1ul<<SECURE1_SEC_ENABLE_Pos)ùJSECURE2_SEC_IV3_Pos 24úJSECURE2_SEC_IV3_Msk (0xfful<<SECURE2_SEC_IV3_Pos)ûJSECURE2_SEC_IV2_Pos 16üJSECURE2_SEC_IV2_Msk (0xfful<<SECURE2_SEC_IV2_Pos)ýJSECURE2_SEC_IV1_Pos 8þJSECURE2_SEC_IV1_Msk (0xfful<<SECURE2_SEC_IV1_Pos)ÿJSECURE2_SEC_IV0_Pos 0€KSECURE2_SEC_IV0_Msk (0xfful<<SECURE2_SEC_IV0_Pos)‚KSECURE3_SEC_IV7_Pos 24ƒKSECURE3_SEC_IV7_Msk (0xfful<<SECURE3_SEC_IV7_Pos)„KSECURE3_SEC_IV6_Pos 16…KSECURE3_SEC_IV6_Msk (0xfful<<SECURE3_SEC_IV6_Pos)†KSECURE3_SEC_IV5_Pos 8‡KSECURE3_SEC_IV5_Msk (0xfful<<SECURE3_SEC_IV5_Pos)ˆKSECURE3_SEC_IV4_Pos 0‰KSECURE3_SEC_IV4_Msk (0xfful<<SECURE3_SEC_IV4_Pos)‹KSECURE4_SEC_KEY2_RX_ADDR_Pos 16ŒKSECURE4_SEC_KEY2_RX_ADDR_Msk (0xfffful<<SECURE4_SEC_KEY2_RX_ADDR_Pos)KSECURE4_SEC_KEY1_RX_ADDR_Pos 0ŽKSECURE4_SEC_KEY1_RX_ADDR_Msk (0xfffful<<SECURE4_SEC_KEY1_RX_ADDR_Pos)KSECURE5_SEC_KEY4_RX_ADDR_Pos 16‘KSECURE5_SEC_KEY4_RX_ADDR_Msk (0xfffful<<SECURE5_SEC_KEY4_RX_ADDR_Pos)’KSECURE5_SEC_KEY3_RX_ADDR_Pos 0“KSECURE5_SEC_KEY3_RX_ADDR_Msk (0xfffful<<SECURE5_SEC_KEY3_RX_ADDR_Pos)•KSECURE6_SEC_KEY6_RX_ADDR_Pos 16–KSECURE6_SEC_KEY6_RX_ADDR_Msk (0xfffful<<SECURE6_SEC_KEY6_RX_ADDR_Pos)—KSECURE6_SEC_KEY5_RX_ADDR_Pos 0˜KSECURE6_SEC_KEY5_RX_ADDR_Msk (0xfffful<<SECURE6_SEC_KEY5_RX_ADDR_Pos)šKSECURE7_SEC_MD_LEN_Pos 24›KSECURE7_SEC_MD_LEN_Msk (0x7ful<<SECURE7_SEC_MD_LEN_Pos)œKSECURE7_SEC_KEY7_RX_ADDR_Pos 8KSECURE7_SEC_KEY7_RX_ADDR_Msk (0xfffful<<SECURE7_SEC_KEY7_RX_ADDR_Pos)žKSECURE7_SEC_PKT_CNT_TX_MSB_Pos 0ŸKSECURE7_SEC_PKT_CNT_TX_MSB_Msk (0xfful<<SECURE7_SEC_PKT_CNT_TX_MSB_Pos)¡KSECURE8_SEC_PKT_CNT_TX_LSB_Pos 0¢KSECURE8_SEC_PKT_CNT_TX_LSB_Msk (0xfffffffful<<SECURE8_SEC_PKT_CNT_TX_LSB_Pos)¤KSECURE9_SEC_PKT_CNT_RX_MSB_Pos 0¥KSECURE9_SEC_PKT_CNT_RX_MSB_Msk (0xfful<<SECURE9_SEC_PKT_CNT_RX_MSB_Pos)§KSECURE10_SEC_PKT_CNT_RX_LSB_Pos 0¨KSECURE10_SEC_PKT_CNT_RX_LSB_Msk (0xfffffffful<<SECURE10_SEC_PKT_CNT_RX_LSB_Pos)ªKTEST_MUX00_TST_MUX_SELECT_03_Pos 18«KTEST_MUX00_TST_MUX_SELECT_03_Msk (0x3ful<<TEST_MUX00_TST_MUX_SELECT_03_Pos)¬KTEST_MUX00_TST_MUX_SELECT_02_Pos 12­KTEST_MUX00_TST_MUX_SELECT_02_Msk (0x3ful<<TEST_MUX00_TST_MUX_SELECT_02_Pos)®KTEST_MUX00_TST_MUX_SELECT_01_Pos 6¯KTEST_MUX00_TST_MUX_SELECT_01_Msk (0x3ful<<TEST_MUX00_TST_MUX_SELECT_01_Pos)°KTEST_MUX00_TST_MUX_SELECT_00_Pos 0±KTEST_MUX00_TST_MUX_SELECT_00_Msk (0x3ful<<TEST_MUX00_TST_MUX_SELECT_00_Pos)³KRNG1_RNG_RING_SCRMB_SEL_Pos 1´KRNG1_RNG_RING_SCRMB_SEL_Msk (0x1ul<<RNG1_RNG_RING_SCRMB_SEL_Pos)µKRNG1_RNG_EN_Pos 0¶KRNG1_RNG_EN_Msk (0x1ul<<RNG1_RNG_EN_Pos)¸KRNG2_RNG_DATA_Pos 0¹KRNG2_RNG_DATA_Msk (0xfffffffful<<RNG2_RNG_DATA_Pos)»KLL_MAC_CTRL_CTRL_LL_EN_Pos 0¼KLL_MAC_CTRL_CTRL_LL_EN_Msk (0x1ul<<LL_MAC_CTRL_CTRL_LL_EN_Pos)¾KTEST_MUX01_TST_MUX_SELECT_07_Pos 18¿KTEST_MUX01_TST_MUX_SELECT_07_Msk (0x3ful<<TEST_MUX01_TST_MUX_SELECT_07_Pos)ÀKTEST_MUX01_TST_MUX_SELECT_06_Pos 12ÁKTEST_MUX01_TST_MUX_SELECT_06_Msk (0x3ful<<TEST_MUX01_TST_MUX_SELECT_06_Pos)ÂKTEST_MUX01_TST_MUX_SELECT_05_Pos 6ÃKTEST_MUX01_TST_MUX_SELECT_05_Msk (0x3ful<<TEST_MUX01_TST_MUX_SELECT_05_Pos)ÄKTEST_MUX01_TST_MUX_SELECT_04_Pos 0ÅKTEST_MUX01_TST_MUX_SELECT_04_Msk (0x3ful<<TEST_MUX01_TST_MUX_SELECT_04_Pos)ÇKTEST_MUX02_TST_MUX_SELECT_11_Pos 18ÈKTEST_MUX02_TST_MUX_SELECT_11_Msk (0x3ful<<TEST_MUX02_TST_MUX_SELECT_11_Pos)ÉKTEST_MUX02_TST_MUX_SELECT_10_Pos 12ÊKTEST_MUX02_TST_MUX_SELECT_10_Msk (0x3ful<<TEST_MUX02_TST_MUX_SELECT_10_Pos)ËKTEST_MUX02_TST_MUX_SELECT_09_Pos 6ÌKTEST_MUX02_TST_MUX_SELECT_09_Msk (0x3ful<<TEST_MUX02_TST_MUX_SELECT_09_Pos)ÍKTEST_MUX02_TST_MUX_SELECT_08_Pos 0ÎKTEST_MUX02_TST_MUX_SELECT_08_Msk (0x3ful<<TEST_MUX02_TST_MUX_SELECT_08_Pos)ÐKTEST_MUX03_TST_MUX_SELECT_15_Pos 18ÑKTEST_MUX03_TST_MUX_SELECT_15_Msk (0x3ful<<TEST_MUX03_TST_MUX_SELECT_15_Pos)ÒKTEST_MUX03_TST_MUX_SELECT_14_Pos 12ÓKTEST_MUX03_TST_MUX_SELECT_14_Msk (0x3ful<<TEST_MUX03_TST_MUX_SELECT_14_Pos)ÔKTEST_MUX03_TST_MUX_SELECT_13_Pos 6ÕKTEST_MUX03_TST_MUX_SELECT_13_Msk (0x3ful<<TEST_MUX03_TST_MUX_SELECT_13_Pos)ÖKTEST_MUX03_TST_MUX_SELECT_12_Pos 0×KTEST_MUX03_TST_MUX_SELECT_12_Msk (0x3ful<<TEST_MUX03_TST_MUX_SELECT_12_Pos)ÚKR00_CTL_TX_PAYLOAD_LEN_Pos 24ÛKR00_CTL_TX_PAYLOAD_LEN_Msk (0xFFul<<R00_CTL_TX_PAYLOAD_LEN_Pos)ÜKR00_CTL_RX_PAYLOAD_LEN_Pos 16ÝKR00_CTL_RX_PAYLOAD_LEN_Msk (0xFFul<<R00_CTL_RX_PAYLOAD_LEN_Pos)ÞKR00_CTL_CRC_ACCESS_ADR_Pos 15ßKR00_CTL_CRC_ACCESS_ADR_Msk (0x1ul<<R00_CTL_CRC_ACCESS_ADR_Pos)àKR00_CTL_CRC24_EN_Pos 14áKR00_CTL_CRC24_EN_Msk (0x1ul<<R00_CTL_CRC24_EN_Pos)âKR00_CTL_ADDR_BYTE_LEN_Pos 12ãKR00_CTL_ADDR_BYTE_LEN_Msk (0x3ul<<R00_CTL_ADDR_BYTE_LEN_Pos)äKR00_CTL_DPY_EN_Pos 11åKR00_CTL_DPY_EN_Msk (0x1ul<<R00_CTL_DPY_EN_Pos)æKR00_CTL_CRC_EN_Pos 10çKR00_CTL_CRC_EN_Msk (0x1ul<<R00_CTL_CRC_EN_Pos)èKR00_CTL_CRC_SEL16_Pos 9éKR00_CTL_CRC_SEL16_Msk (0x1ul<<R00_CTL_CRC_SEL16_Pos)êKR00_CTL_SCR_EN_Pos 8ëKR00_CTL_SCR_EN_Msk (0x1ul<<R00_CTL_SCR_EN_Pos)ìKR00_CTL_NRF_ENHANCE_Pos 7íKR00_CTL_NRF_ENHANCE_Msk (0x1ul<<R00_CTL_NRF_ENHANCE_Pos)îKR00_CTL_ENHANCE_Pos 6ïKR00_CTL_ENHANCE_Msk (0x1ul<<R00_CTL_ENHANCE_Pos)ðKR00_CTL_BW_MODE_Pos 5ñKR00_CTL_BW_MODE_Msk (0x1ul<<R00_CTL_BW_MODE_Pos)òKR00_CTL_CHIP_MODE_Pos 3óKR00_CTL_CHIP_MODE_Msk (0x3ul<<R00_CTL_CHIP_MODE_Pos)ôKR00_CTL_RX_ACK_PAYLOAD_EN_Pos 2õKR00_CTL_RX_ACK_PAYLOAD_EN_Msk (0x1ul<<R00_CTL_RX_ACK_PAYLOAD_EN_Pos)öKR00_CTL_TX_NOACK_EN_Pos 1÷KR00_CTL_TX_NOACK_EN_Msk (0x1ul<<R00_CTL_TX_NOACK_EN_Pos)øKR00_CTL_PRI_RX_Pos 0ùKR00_CTL_PRI_RX_Msk (0x1ul<<R00_CTL_PRI_RX_Pos)ûKR01_INT_PRI_RX_PID_Pos 29üKR01_INT_PRI_RX_PID_Msk (0x3ul<<R01_INT_PRI_RX_PID_Pos)ýKR01_INT_PRI_TX_PID_Pos 27þKR01_INT_PRI_TX_PID_Msk (0x3ul<<R01_INT_PRI_TX_PID_Pos)ÿKR01_INT_RX_LENGTH_ERR_Pos 26€LR01_INT_RX_LENGTH_ERR_Msk (0x1ul<<R01_INT_RX_LENGTH_ERR_Pos)LR01_INT_RX_ACCADDR_ERR_Pos 25‚LR01_INT_RX_ACCADDR_ERR_Msk (0x1ul<<R01_INT_RX_ACCADDR_ERR_Pos)ƒLR01_INT_RX_ACCADDR_ERR_MASK_Pos 23„LR01_INT_RX_ACCADDR_ERR_MASK_Msk (0x1ul<<R01_INT_RX_ACCADDR_ERR_MASK_Pos)…LR01_INT_RX_LENGTH_ERR_MASK_Pos 22†LR01_INT_RX_LENGTH_ERR_MASK_Msk (0x1ul<<R01_INT_RX_LENGTH_ERR_MASK_Pos)‡LR01_INT_PRI_ENDIAN_Pos 21ˆLR01_INT_PRI_ENDIAN_Msk (0x1ul<<R01_INT_PRI_ENDIAN_Pos)‰LR01_INT_PRI_TX_DONE_IRQ_EN_Pos 20ŠLR01_INT_PRI_TX_DONE_IRQ_EN_Msk (0x1ul<<R01_INT_PRI_TX_DONE_IRQ_EN_Pos)‹LR01_INT_PRI_RX_DONE_IRQ_EN_Pos 19ŒLR01_INT_PRI_RX_DONE_IRQ_EN_Msk (0x1ul<<R01_INT_PRI_RX_DONE_IRQ_EN_Pos)LR01_INT_PRI_RX_GOON_Pos 18ŽLR01_INT_PRI_RX_GOON_Msk (0x1ul<<R01_INT_PRI_RX_GOON_Pos)LR01_INT_PRI_RST_Pos 17LR01_INT_PRI_RST_Msk (0x1ul<<R01_INT_PRI_RST_Pos)‘LR01_INT_EXIT_RX_Pos 16’LR01_INT_EXIT_RX_Msk (0x1ul<<R01_INT_EXIT_RX_Pos)“LR01_INT_TX_DONE_IRQ_FLAG_Pos 15”LR01_INT_TX_DONE_IRQ_FLAG_Msk (0x1ul<<R01_INT_TX_DONE_IRQ_FLAG_Pos)•LR01_INT_RX_DONE_IRQ_FLAG_Pos 14–LR01_INT_RX_DONE_IRQ_FLAG_Msk (0x1ul<<R01_INT_RX_DONE_IRQ_FLAG_Pos)—LR01_INT_RX_PID_ERR_IRQ_FLAG_Pos 13˜LR01_INT_RX_PID_ERR_IRQ_FLAG_Msk (0x1ul<<R01_INT_RX_PID_ERR_IRQ_FLAG_Pos)™LR01_INT_RX_CRC_ERR_Pos 12šLR01_INT_RX_CRC_ERR_Msk (0x1ul<<R01_INT_RX_CRC_ERR_Pos)›LR01_INT_TX_TIMEOUT_IRQ_Pos 11œLR01_INT_TX_TIMEOUT_IRQ_Msk (0x1ul<<R01_INT_TX_TIMEOUT_IRQ_Pos)LR01_INT_TX_IRQ_Pos 10žLR01_INT_TX_IRQ_Msk (0x1ul<<R01_INT_TX_IRQ_Pos)ŸLR01_INT_RX_IRQ_Pos 9 LR01_INT_RX_IRQ_Msk (0x1ul<<R01_INT_RX_IRQ_Pos)¡LR01_INT_IRQ_CLR_EN_Pos 8¢LR01_INT_IRQ_CLR_EN_Msk (0x1ul<<R01_INT_IRQ_CLR_EN_Pos)£LR01_INT_RX_CRC_ERR_MASK_Pos 7¤LR01_INT_RX_CRC_ERR_MASK_Msk (0x1ul<<R01_INT_RX_CRC_ERR_MASK_Pos)¥LR01_INT_PID_ERR_MASK_Pos 6¦LR01_INT_PID_ERR_MASK_Msk (0x1ul<<R01_INT_PID_ERR_MASK_Pos)§LR01_INT_TX_TIMEOUT_IRQ_MASK_Pos 5¨LR01_INT_TX_TIMEOUT_IRQ_MASK_Msk (0x1ul<<R01_INT_TX_TIMEOUT_IRQ_MASK_Pos)©LR01_INT_TX_IRQ_MASK_Pos 4ªLR01_INT_TX_IRQ_MASK_Msk (0x1ul<<R01_INT_TX_IRQ_MASK_Pos)«LR01_INT_RX_IRQ_MASK_Pos 3¬LR01_INT_RX_IRQ_MASK_Msk (0x1ul<<R01_INT_RX_IRQ_MASK_Pos)­LR01_INT_MULTI_RX_ACC_ADR_Pos 0®LR01_INT_MULTI_RX_ACC_ADR_Msk (0x7ul<<R01_INT_MULTI_RX_ACC_ADR_Pos)±LR02_TMR_CTL_RX_WAIT_TIME_Pos 16²LR02_TMR_CTL_RX_WAIT_TIME_Msk (0xFFFFul<<R02_TMR_CTL_RX_WAIT_TIME_Pos)³LR02_TMR_CTL_RX_WAIT_TIME_EN_Pos 15´LR02_TMR_CTL_RX_WAIT_TIME_EN_Msk (0X1ul<<R02_TMR_CTL_RX_WAIT_TIME_EN_Pos)µLR02_TMR_CTL_TRX_TRANS_WAIT_TIME_Pos 0¶LR02_TMR_CTL_TRX_TRANS_WAIT_TIME_Msk (0x7FFFul<<R02_TMR_CTL_TRX_TRANS_WAIT_TIME_Pos)¸LR03_RX_ADDR_L_L32B_Pos 0¹LR03_RX_ADDR_L_L32B_Msk (0xFFFFFFFFul<<R03_RX_ADDR_L_L32B_Pos)½LR04_RX_CTL_RX_HEADER1_Pos 24¾LR04_RX_CTL_RX_HEADER1_Msk (0xFFul<<R04_RX_CTL_RX_HEADER1_Pos)¿LR04_RX_CTL_RX_HEADER_Pos 16ÀLR04_RX_CTL_RX_HEADER_Msk (0xFFul<<R04_RX_CTL_RX_HEADER_Pos)ÁLR04_RX_CTL_RX_FEC_Pos 15ÂLR04_RX_CTL_RX_FEC_Msk (0x1ul<<R04_RX_CTL_RX_FEC_Pos)ÃLR04_RX_CTL_TX_FEC_Pos 14ÄLR04_RX_CTL_TX_FEC_Msk (0x1ul<<R04_RX_CTL_TX_FEC_Pos)ÅLR04_RX_CTL_CI_MODE_Pos 12ÆLR04_RX_CTL_CI_MODE_Msk (0x3ul<<R04_RX_CTL_CI_MODE_Pos)ÇLR04_RX_CTL_NORMAL_M1_Pos 11ÈLR04_RX_CTL_NORMAL_M1_Msk (0x1ul<<R04_RX_CTL_NORMAL_M1_Pos)ÉLR04_RX_CTL_HDR_LEN_NUMB_Pos 9ÊLR04_RX_CTL_HDR_LEN_NUMB_Msk (0x3ul<<R04_RX_CTL_HDR_LEN_NUMB_Pos)ËLR04_RX_CTL_HDR_LEN_EXIST_Pos 8ÌLR04_RX_CTL_HDR_LEN_EXIST_Msk (0x1ul<<R04_RX_CTL_HDR_LEN_EXIST_Pos)ÍLR04_RX_CTL_M8B_Pos 0ÎLR04_RX_CTL_M8B_Msk (0xFFul<<R04_RX_CTL_M8B_Pos)ÐLR05_TX_ADDR_L_L32B_Pos 0ÑLR05_TX_ADDR_L_L32B_Msk (0xFFFFFFFFul<<R05_TX_ADDR_L_L32B_Pos)ÓLR06_TX_CTL_RX_HEADER1_Pos 24ÔLR06_TX_CTL_RX_HEADER1_Msk (0xFFul<<R06_TX_CTL_RX_HEADER1_Pos)ÕLR06_TX_CTL_RX_HEADER_Pos 16ÖLR06_TX_CTL_RX_HEADER_Msk (0xFFul<<R06_TX_CTL_RX_HEADER_Pos)×LR06_TX_CTL_MAX_LENGTH_EN_Pos 15ØLR06_TX_CTL_MAX_LENGTH_EN_Msk (0x1ul<<R06_TX_CTL_MAX_LENGTH_EN_Pos)ÙLR06_TX_CTL_WHITENING_INIT_Pos 8ÚLR06_TX_CTL_WHITENING_INIT_Msk (0x7Ful<<R06_TX_CTL_WHITENING_INIT_Pos)ÛLR06_TX_CTL_M8B_Pos 0ÜLR06_TX_CTL_M8B_Msk (0xFFul<<R06_TX_CTL_M8B_Pos)ÞLR07_SRAM_CTL_RX_START_ADDR_Pos 17ßLR07_SRAM_CTL_RX_START_ADDR_Msk (0x7FFul<<R07_SRAM_CTL_RX_START_ADDR_Pos)àLR07_SRAM_CTL_RX_READY_Pos 16áLR07_SRAM_CTL_RX_READY_Msk (0x1ul<<R07_SRAM_CTL_RX_READY_Pos)âLR07_SRAM_CTL_TX_START_ADDR_Pos 1ãLR07_SRAM_CTL_TX_START_ADDR_Msk (0x7FFul<<R07_SRAM_CTL_TX_START_ADDR_Pos)äLR07_SRAM_CTL_TX_READY_Pos 0åLR07_SRAM_CTL_TX_READY_Msk (0x1<<R07_SRAM_CTL_TX_READY_Pos)èLR0F_RX_ADDR4_M8B_Pos 24éLR0F_RX_ADDR4_M8B_Msk (0xFFul<<R0F_RX_ADDR4_M8B_Pos)êLR0F_RX_ADDR3_M8B_Pos 16ëLR0F_RX_ADDR3_M8B_Msk (0xFFul<<R0F_RX_ADDR3_M8B_Pos)ìLR0F_RX_ADDR2_M8B_Pos 8íLR0F_RX_ADDR2_M8B_Msk (0xFFul<<R0F_RX_ADDR2_M8B_Pos)îLR0F_RX_ADDR1_M8B_Pos 0ïLR0F_RX_ADDR1_M8B_Msk (0xFFul<<R0F_RX_ADDR1_M8B_Pos)òLR10_RX_ADDR7_EN_Pos 31óLR10_RX_ADDR7_EN_Msk (0x1ul<<R0F_RX_ADDR7_EN_Pos)ôLR10_RX_ADDR6_EN_Pos 30õLR10_RX_ADDR6_EN_Msk (0x1ul<<R0F_RX_ADDR6_EN_Pos)öLR10_RX_ADDR5_EN_Pos 29÷LR10_RX_ADDR5_EN_Msk (0x1ul<<R0F_RX_ADDR5_EN_Pos)øLR10_RX_ADDR4_EN_Pos 28ùLR10_RX_ADDR4_EN_Msk (0x1ul<<R0F_RX_ADDR4_EN_Pos)úLR10_RX_ADDR3_EN_Pos 27ûLR10_RX_ADDR3_EN_Msk (0x1ul<<R0F_RX_ADDR3_EN_Pos)üLR10_RX_ADDR2_EN_Pos 26ýLR10_RX_ADDR2_EN_Msk (0x1ul<<R0F_RX_ADDR2_EN_Pos)þLR10_RX_ADDR1_EN_Pos 25ÿLR10_RX_ADDR1_EN_Msk (0x1ul<<R0F_RX_ADDR1_EN_Pos)€MR10_RX_ADDR0_EN_Pos 24MR10_RX_ADDR0_EN_Msk (0x1ul<<R0F_RX_ADDR0_EN_Pos)‚MR10_RX_ADDR7_M8B_Pos 16ƒMR10_RX_ADDR7_M8B_Msk (0xFFul<<R0F_RX_ADDR3_M8B_Pos)„MR10_RX_ADDR6_M8B_Pos 8…MR10_RX_ADDR6_M8B_Msk (0xFFul<<R0F_RX_ADDR2_M8B_Pos)†MR10_RX_ADDR5_M8B_Pos 0‡MR10_RX_ADDR5_M8B_Msk (0xFFul<<R0F_RX_ADDR1_M8B_Pos)‹MR11_CFG_NRF_PRE_SEL_Pos 25ŒMR11_CFG_NRF_PRE_SEL_Msk (0x1ul<<R11_CFG_NRF_PRE_SEL_Pos)MR11_CFG_RX_DATA_REV_EN_Pos 24ŽMR11_CFG_RX_DATA_REV_EN_Msk (0x1ul<<R11_CFG_RX_DATA_REV_EN_Pos)MR11_CFG_PRE_SYNC_12B_EN_Pos 23MR11_CFG_PRE_SYNC_12B_EN_Msk (0x1ul<<R11_CFG_PRE_SYNC_12B_EN_Pos)‘MR11_CFG_PRE_SYNC_8B_EN_Pos 22’MR11_CFG_PRE_SYNC_8B_EN_Msk (0x1ul<<R11_CFG_PRE_SYNC_8B_EN_Pos)“MR11_CFG_PRE_SYNC_4B_EN_Pos 21”MR11_CFG_PRE_SYNC_4B_EN_Msk (0x1ul<<R11_CFG_PRE_SYNC_4B_EN_Pos)•MR11_CFG_PRE_SYNC_EN_Pos 20–MR11_CFG_PRE_SYNC_EN_Msk (0x1ul<<R11_CFG_PRE_SYNC_EN_Pos)—MR11_CFG_250K_MODE_EN_Pos 19˜MR11_CFG_250K_MODE_EN_Msk (0x1ul<<R11_CFG_250K_MODE_EN_Pos)™MR11_CFG_B250K_PRE_SEL_Pos 18šMR11_CFG_B250K_PRE_SEL_Msk (0x1ul<<R11_CFG_B250K_PRE_SEL_Pos)›MR11_CFG_LQI_EN_Pos 17œMR11_CFG_LQI_EN_Msk (0x1ul<<R11_CFG_LQI_EN_Pos)MR11_CFG_RX_PID_MANUAL_Pos 15žMR11_CFG_RX_PID_MANUAL_Msk (0x3ul<<R11_CFG_RX_PID_MANUAL_Pos)ŸMR11_CFG_TX_PID_MANUAL_Pos 13 MR11_CFG_TX_PID_MANUAL_Msk (0x3ul<<R11_CFG_TX_PID_MANUAL_Pos)¡MR11_CFG_PREAM_2BYTE_EN_Pos 12¢MR11_CFG_PREAM_2BYTE_EN_Msk (0x1ul<<R11_CFG_PREAM_2BYTE_EN_Pos)£MR11_CFG_B250K_INVERT_EN_Pos 11¤MR11_CFG_B250K_INVERT_EN_Msk (0x1ul<<R11_CFG_B250K_INVERT_EN_Pos)¥MR11_CFG_B250K_SCR_INIT_VALUE_Pos 9¦MR11_CFG_B250K_SCR_INIT_VALUE_Msk (0x3ul<<R11_CFG_B250K_SCR_INIT_VALUE_Pos)§MR11_CFG_B250K_PREAM_Pos 6¨MR11_CFG_B250K_PREAM_Msk (0x7ul<<R11_CFG_B250K_PREAM_Pos)©MR11_CFG_B250K_MODE_Pos 5ªMR11_CFG_B250K_MODE_Msk (0x1ul<<R11_CFG_B250K_MODE_Pos)«MR11_CFG_ADDR_ERR_THR_Pos 2¬MR11_CFG_ADDR_ERR_THR_Msk (0x7ul<<R11_CFG_ADDR_ERR_THR_Pos)­MR11_CFG_PID_MANUAL_EN_Pos 1®MR11_CFG_PID_MANUAL_EN_Msk (0x1ul<<R11_CFG_PID_MANUAL_EN_Pos)¯MR11_CFG_ADDR_SCR_DIS_Pos 0°MR11_CFG_ADDR_SCR_DIS_Msk (0x1ul<<R11_CFG_ADDR_SCR_DIS_Pos)ºMCR_BASE (0x00400000Ul)»MSRAM_BASE (0x20000000UL)½MAHB1_PERIPH_BASE (0x40000000UL)ÀMAPB1_PERIPH_BASE (0x40000000UL)ÁMAPB2_PERIPH_BASE (0x40010000UL)ÃMBLE_PERIPH_BASE (0x50020000UL)ÈMI2C0_BASE (APB1_PERIPH_BASE + 0x00000000UL)ÉMSPI0_BASE (APB1_PERIPH_BASE + 0x00001000UL)ÊMUART0_BASE (APB1_PERIPH_BASE + 0x00003000UL)ËMPWM_BASE (APB1_PERIPH_BASE + 0x00004000UL)ÌMADC_BASE (APB1_PERIPH_BASE + 0x00005000UL)ÍMWDT_BASE (APB1_PERIPH_BASE + 0x00006000UL)ÎMWWDT_BASE (APB1_PERIPH_BASE + 0x00007000UL)ÏMTIMER0_BASE (APB1_PERIPH_BASE + 0x00008000UL)ÓMSPI1_BASE (APB2_PERIPH_BASE + 0x00001000UL)ÔMUART1_BASE (APB2_PERIPH_BASE + 0x00003000UL)ÕMTIMER1_BASE (APB2_PERIPH_BASE + 0x00004000UL)ÖMTIMER2_BASE (APB2_PERIPH_BASE + 0x00005000UL)×MTRIM_BASE (APB2_PERIPH_BASE + 0x00006000UL)ÜMGPIO_BASE (AHB1_PERIPH_BASE + 0x00020000UL)ÝMP0_BASE (GPIO_BASE + 0x00000000UL)ÞMP1_BASE (GPIO_BASE + 0x00000040UL)ßMP2_BASE (GPIO_BASE + 0x00000080UL)àMP3_BASE (GPIO_BASE + 0x000000C0UL)áMGPIO_DBNCECON_BASE (GPIO_BASE + 0x00000180UL)âMGPIOBIT0_BASE (GPIO_BASE + 0x00000200UL)ãMGPIOBIT1_BASE (GPIO_BASE + 0x00000220UL)äMGPIOBIT2_BASE (GPIO_BASE + 0x00000240UL)åMGPIOBIT3_BASE (GPIO_BASE + 0x00000260UL)çMSYS_BASE (AHB1_PERIPH_BASE + 0x00030000UL)èMCLK_BASE (AHB1_PERIPH_BASE + 0x00040000UL)éMFLCTL_BASE (AHB1_PERIPH_BASE + 0x00050000UL)êMFLCTL_BASE1 (AHB1_PERIPH_BASE + 0x00050400UL)ëMDMA_BASE (AHB1_PERIPH_BASE + 0x00060000UL)ìMANA_BASE (AHB1_PERIPH_BASE + 0x00070000UL)íMEFUSE_BASE (AHB1_PERIPH_BASE + 0x00080000UL)îMUSB_BASE (AHB1_PERIPH_BASE + 0x000A0000UL)ïMUSBDMA_BASE (AHB1_PERIPH_BASE + 0x000A0200UL)òMPRI_RF_BASE (BLE_PERIPH_BASE + 0X00000400UL)öMCR ((CR_T *) CR_BASE)ùMI2C0 ((I2C_T *) I2C0_BASE )úMSPI0 ((SPI_T *) SPI0_BASE )ûMUART0 ((UART_T *) UART0_BASE )üMPWM ((PWM_T *) PWM_BASE )ýMADC ((ADC_T *) ADC_BASE )þMWDT ((WDT_T *) WDT_BASE )ÿMWWDT ((WWDT_T *) WWDT_BASE )€NTIMER0 ((TIMER_T *) TIMER0_BASE )„NSPI1 ((SPI_T *) SPI1_BASE )…NUART1 ((UART_T *) UART1_BASE )†NTIMER1 ((TIMER_T *) TIMER1_BASE )‡NTIMER2 ((TIMER_T *) TIMER2_BASE )ˆNTRIM ((TRIM_T *) TRIM_BASE )‹NGPIO ((GPIO_T *) GPIO_BASE )ŒNP0 ((GPIO_T *) P0_BASE )NP1 ((GPIO_T *) P1_BASE )ŽNP2 ((GPIO_T *) P2_BASE )NP3 ((GPIO_T *) P3_BASE )NGPIO_DB ((GPIO_DB_T *) GPIO_DBNCECON_BASE)’NSYS ((SYS_T *) SYS_BASE )“NCLK ((CLK_T *) CLK_BASE )”NFLCTL ((FLCTL_T *) FLCTL_BASE )•NFLCTL_BUFF ((FLCTL_W_BUFF_T *)FLCTL_BASE1 )–NDMA ((DMA_T *) DMA_BASE )—NANA ((ANA_T *) ANA_BASE )˜NEFUSE ((EFUSE_T *) EFUSE_BASE )™NUSB ((USB_T *) USB_BASE )šNUSBDMA ((USBDMA_T *) USBDMA_BASE )NPRI_RF ((PRI_RF_T *) PRI_RF_BASE )¶NTRUE (1)ºNFALSE (0)¾NBIT0 (0x00000001UL)¿NBIT1 (0x00000002UL)ÀNBIT2 (0x00000004UL)ÁNBIT3 (0x00000008UL)ÂNBIT4 (0x00000010UL)ÃNBIT5 (0x00000020UL)ÄNBIT6 (0x00000040UL)ÅNBIT7 (0x00000080UL)ÆNBIT8 (0x00000100UL)ÇNBIT9 (0x00000200UL)ÈNBIT10 (0x00000400UL)ÉNBIT11 (0x00000800UL)ÊNBIT12 (0x00001000UL)ËNBIT13 (0x00002000UL)ÌNBIT14 (0x00004000UL)ÍNBIT15 (0x00008000UL)ÎNBIT16 (0x00010000UL)ÏNBIT17 (0x00020000UL)ÐNBIT18 (0x00040000UL)ÑNBIT19 (0x00080000UL)ÒNBIT20 (0x00100000UL)ÓNBIT21 (0x00200000UL)ÔNBIT22 (0x00400000UL)ÕNBIT23 (0x00800000UL)ÖNBIT24 (0x01000000UL)×NBIT25 (0x02000000UL)ØNBIT26 (0x04000000UL)ÙNBIT27 (0x08000000UL)ÚNBIT28 (0x10000000UL)ÛNBIT29 (0x20000000UL)ÜNBIT30 (0x40000000UL)ÝNBIT31 (0x80000000UL)àNBIT(x) (0x1UL << (x))äNBYTE0_Msk (0x000000FF)åNBYTE1_Msk (0x0000FF00)æNBYTE2_Msk (0x00FF0000)çNBYTE3_Msk (0xFF000000)éNGET_BYTE0(u32Param) ((u32Param & BYTE0_Msk) )êNGET_BYTE1(u32Param) ((u32Param & BYTE1_Msk) >> 8)ëNGET_BYTE2(u32Param) ((u32Param & BYTE2_Msk) >> 16)ìNGET_BYTE3(u32Param) ((u32Param & BYTE3_Msk) >> 24)ïNSET_BIT(REG,BIT) ((REG) |= (BIT))ñNCLEAR_BIT(REG,BIT) ((REG) &= ~(BIT))óNREAD_BIT(REG,BIT) ((REG) & (BIT))õNCLEAR_REG(REG) ((REG) = (0x0))÷NWRITE_REG(REG,VAL) ((REG) = (VAL))ùNREAD_REG(REG) ((REG))ûNMODIFY_REG(REG,CLEARMASK,SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))‰Oassert_param(expr) ((void)0)OFREQ_RCL 32000ŽOFREQ_XTL 32768’ONVIC_SystemReset¤O    ¥O


¦O§O¨O ©OªO«O¬O­O®O¯O°O±O²O³O´OµO¶O·Oìá ..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\C:\Keil_v5\ARM\ARMCC\Bin\..\include\..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include\..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\radio\prf_lib\include\PanSeries.hstdio.hstdlib.hstdint.hstring.hcore_cm0.hsystem_PanSeries.hstdbool.hpan_sys_log.hpan_sys.hpan_clk.hpan_adc.hpan_fmc.hpan_dmac.hpan_gpio.hpan_spi.hpan_uart.hpan_i2c.hpan_timer.hpan_pwm.hpan_wdt.hpan_wwdt.hpan_lp.hpan_efuse.hpan_pri_rf.hpan_clktrim.hpan_power.hpan_hal.hÐ


..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\PanSeries.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xƒIRQnNonMaskableInt_IRQnrHardFault_IRQnsSVCall_IRQn{PendSV_IRQn~SysTick_IRQnI2C0_IRQnSPI0_IRQnUART0_IRQnPWM_IRQnADC_IRQnWDT_IRQnWWDT_IRQnTMR0_IRQnSPI1_IRQn


LL_IRQnUART1_IRQnTMR1_IRQn TMR2_IRQnGPIO0_IRQnGPIO1_IRQnGPIO2_IRQnGPIO3_IRQnUSBDMA_IRQnUSB_IRQnTRIM_IRQnDMA_IRQnBOD_IRQnSLPTMR_IRQnLP_IRQnPIRQn_Type?©RESETSETPFlagStatus”W(PITStatus”W4åDISABLEENABLEPFunctionalStateËY/*ð$CTLp#CMPp#INTSTSp#CNT|#CAP|#EXTCTLp#EINTSTSp#CMP1p#CMP2p# tYYtvPTIMER_Tü±*•TRIM_ENp#TRIM_CODEp#TRIM_CTRLp#TRIM_INTp#TRIM_CAL_CNTp#TRIM_IDEAL_CNTp#TRIM_REAL_CNT|#PTRIM_T¤*ž    $MODEp#DINOFFp#DOUTp#DATMSKp#PINp#DBENp#INTTYPEp#INTENp#INTSRCp# PGPIO_T$*¿    DBCTLp#PGPIO_DB_T­¯*ÏpDAT|#é    |RESERVED0à#CTLp# CHENp#$CMP0p#(CMP1p#,STATUSp#0À


|RESERVED17#4TRGDLYp#DEXTSMPTp#HSEQCTLp#LSEQDAT1|#PSEQDAT2|#TCTL2p#X¯|RESERVED2¦#\BV_CTLp#lPADC_TÑÀ*æPP0_MFPp#P1_MFPp#P2_MFPp#P3_MFPp#¢pRESV#REGLCTLp#@STATUSp#DCTRL0p#HCTRL1p#LPSYS_TÝ£*‡<RSTSTSp#IPRST0p#IPRST1p#BODCTL_3Vp#BLDBCTL_3Vp#CLK_TOP_CTRL_3Vp#RCL_CTRL_3Vp#RCH_CTRLp#XTL_CTRL_3Vp# XTH_CTRLp#$DPLL_CTRLp#(AHB_CLK_CTRLp#,APB1_CLK_CTRLp#0APB2_CLK_CTRLp#4MEAS_CLK_CTRLp#8PCLK_Ttò *³CTLp#ALTCTLp#PWDT_T•ì#*øRLDCNTp#CTLp#STATUSp#CNT|#PWWDT_TÁŽ%*óŒCLKPSCp#CLKDIVp#CTLp#PERIOD0p#PERIOD1p#PERIOD2p#PERIOD3p#PERIOD4p#PERIOD5p# PERIOD6p#$PERIOD7p#(CMPDAT0p#,CMPDAT1p#0CMPDAT2p#4CMPDAT3p#8CMPDAT4p#<CMPDAT5p#@CMPDAT6p#DCMPDAT7p#HCTL2p#LFLAGp#PINTENp#TINTSTSp#XPOENp#\ë|RESERVED0b    #`DTCTLp#dADCTCTL0p#hADCTCTL1p#lADCTSTS0p#pADCTSTS1p#tÒ|RESERVED1É    #xPCACTLp#ˆPPWM_T².*‰$X_FL_CTLp#X_FL_TRIG    #X_FL_CONFIG    #    X_FL_WD9


#X_FL_X_MODEp#X_FL_X2_CMD    #X_FL_X4_CMD    #X_FL_DP_CMD    #X_FL_RDP_CMD    #X_FL_REMAP_ADDRp#X_FL_DP_CTLp#X_FL_IRQ_CTLp#X_FL_SUS_RESU_CMDp# t:PFLCTL_T


ë8*€®    ÿX_FL_BUFFER$#PFLCTL_W_BUFF_Tð8*’X_CACHE_ENp#X_RESVRp#X_CACHE_INIp#PCR_TY×9*”(CR0p#CR1p#DRp#SRp#CPSRp#IMSCp#RISp#MISp#ICRp# DMACRp#$PSPI_TŸë9*ëÐRBR_THR_DLLp#IER_DLHp#IIR_FCRp#LCRp#MCRp#LSRp#MSRp#SCRp#LPDLLp# LPDLHp#$²|RESERVED0©#(USRp#|TFLp#€RFLp#„ï|RESERVED1æ#ˆHTXp#¤DMASAp#¨¤|RESERVED2 #¬DLFp#ÀRARp#ÄTARp#ÈLCR_EXTp#ÌPUART_T">*ÏXSAR_Lp#SAR_Hp#DAR_Lp#DAR_Hp#»pRESERVED0² #CTL_Lp#CTL_Hp#ïpRESERVED1æ # CFG_Lp#@CFG_Hp#DSGR_Lp#HSGR_Hp#LDSR_Lp#PDSR_Hp#T*Ó$¨Ýz CHT#RAW_TFR_Lp#ÀRAW_TFR_Hp#ÄRAW_BLOCK_Lp#ÈRAW_BLOCK_Hp#ÌRAW_SRCTRAN_Lp#ÐRAW_SRCTRAN_Hp#ÔRAW_DSTTRAN_Lp#ØRAW_DSTTRAN_Hp#ÜRAW_ERR_Lp#àRAW_ERR_Hp#äSTATUS_TFR_Lp#èSTATUS_TFR_Hp#ìSTATUS_BLOCK_Lp#ðSTATUS_BLOCK_Hp#ôSTATUS_SRCTRAN_Lp#øSTATUS_SRCTRAN_Hp#üSTATUS_DSTTRAN_Lp#€STATUS_DSTTRAN_Hp#„STATUS_ERR_Lp#ˆSTATUS_ERR_Hp#ŒMSK_TFR_Lp#MSK_TFR_Hp#”MSK_BLOCK_Lp#˜MSK_BLOCK_Hp#œMSK_SRCTRAN_Lp# MSK_SRCTRAN_Hp#¤MSK_DSTTRAN_Lp#¨MSK_DSTTRAN_Hp#¬MSK_ERR_Lp#°MSK_ERR_Hp#´CLEAR_TFR_Lp#¸CLEAR_TFR_Hp#¼CLEAR_BLOCK_Lp#ÀCLEAR_BLOCK_Hp#ÄCLEAR_SRCTRAN_Lp#ÈCLEAR_SRCTRAN_Hp#ÌCLEAR_DSTTRAN_Lp#ÐCLEAR_DSTTRAN_Hp#ÔCLEAR_ERR_Lp#ØCLEAR_ERR_Hp#ÜSTATUS_INT_Lp#àSTATUS_INT_Hp#äì#pRESERVED3ã#èDMA_CFG_REG_Lp#˜DMA_CFG_REG_Hp#œCH_EN_REG_Lp# CH_EN_REG_Hp#¤PDMA_TOËA*Ú*¬CONp#TARp#SARp#HS_MADDRp#DATACMDp#SS_SCL_HCNTp#SS_SCL_LCNTp#FS_SCL_HCNTp#FS_SCL_LCNTp# HS_SCL_HCNTp#$HS_SCL_LCNTp#(INTR_STATp#,INTR_MASKp#0RAW_INTR_STATp#4RX_TLp#8TX_TLp#<CLR_INTRp#@CLR_RX_UNDp#DCLR_RX_OVRp#HCLR_TX_OVRp#LCLR_RD_REQp#PCLR_TX_ABRTp#TCLR_RX_DONEp#XCLR_ACTIVITYp#\CLR_STOP_DETp#`CLR_START_DETp#dCLR_GEN_CALLp#hIC_ENABLEp#lSTATUSp#pTXFLRp#tRXFLRp#xSDA_HOLDp#|TX_ABRT_SRCp#€SLV_DATA_NACKp#„DMA_CRp#ˆDMA_TDLRp#ŒDMA_RDLRp#SDA_SETUPp#”ACK_GENERAL_CALLp#˜ENABLE_STATUSp#œFS_SPKLENp# HS_SPKLENp#¤CLR_RESTART_DETp#¨PI2C_TaC*å.dLP_REG_SYNCp#LP_FL_CTRL_3Vp#LP_SPACING_TIME0p#LP_SPACING_TIME1p#LP_SPACING_TIME2p#LP_SLPTMR|#LP_INT_CTRLp#LP_DLY_CTRL_3Vp#LP_PTAT_POLYp# LP_HP_LDOp#$LP_LP_LDO_3Vp#(LP_ANA_LDOp#,LP_FSYN_LDOp#0LP_SWp#4LP_BUCK_3Vp#8ANA_ADC_LDOp#<ANA_RFFE_LDOp#@ANA_VCO_LDOp#DANA_DFTp#HANA_MISC_3Vp#LANA_RESERVED_3Vp#PACT_32K_CTRLp#TACT_32K_BASECORRp#XCPU_ADDR_REMAP_CTRLp#\RCL_HW_CAL_CTRLp#`PANA_Th“E*„2|EF_CTLp#EF_ADDRp#EF_DATp#EF_RSV0p#EF_VDDp#EF_RSV1p#EF_CMDp#EF_TRGp#EF_PROG_TIMING1p# EF_PROG_TIMING2p#$EF_PROG_TIMING3p#(EF_READ_TIMING4p#,EF_READ_TIMING5p#0æ0pEF_RSV2]#4EF_OP_ERRORp#dEF_VERIFY_DEBUG1p#hEF_VERIFY_DEBUG2p#lEF_VERIFY_DEBUG3p#pEF_VERIFY_DEBUG4p#tEF_FLASH_PERMISSIONp#xPEFUSE_TsÎG*¥6-FADDR    #POWER    #INT_IN1    #INT_IN2    #INT_OUT1    #INT_OUT2    #INT_USB    #INT_IN1E    #INT_IN2E    #INT_OUT1E    #    INT_OUT2E    #


INT_USBE    #FRAME1    #FRAME2    # INDEX    #REV    #MAX_PKT_IN    #CSR0_INCSR1    #IN_CSR2    #MAX_PKT_OUT    #OUT_CSR1    #OUT_CSR2    #OUT_COUNT1    #OUT_COUNT2    #™5    REV0#FIFO_EP0    # ¾5    REV1µ#!FIFO_EP1    #$ã5    REV2Ú#%FIFO_EP2    #(ˆ6    REV3ÿ#)FIFO_EP3    #,PUSB_T„I*ð6DMA_INTRp#CNTL1p#ADDR1p#COUNT1p#PUSBDMA_T3I*§?ˆrevs0p#FSM5p#FSM6p#FSM13p#FSM14p#FSM15p#FSM16p#FSM17p#FSM18p# FSM19p#$PHY1p#(PHY2p#,PHY3p#0PHY4p#4PHY5p#8Ë8prevs1B#<INTR1p#DINTCLRp#HINTMSKp#LINTR4p#Prevs2p#TACTTMR1p#XACTTMR2p#\ACTTMR6p#`ACTTMR7p#drevs3p#hSECURE1p#lSECURE2p#pSECURE3p#tSECURE4p#xSECURE5p#|SECURE6p#€SECURE7p#„SECURE8p#ˆSECURE9p#ŒSECURE10p#revs4p#”TEST_MUX00p#˜RNG1p#œRNG2p# revs5p#¤LL_MAC_CTRLp#¨TEST_MUX01p#¬TEST_MUX02p#°TEST_MUX03p#´Ÿ<prevs6#¸R00_CTLp#ÀR01_INTp#ÄR02_TMR_CTLp#ÈR03_RX_ADDR_Lp#ÌR04_RX_CTLp#ÐR05_TX_ADDR_Lp#ÔR06_TX_CTLp#ØR07_SRAM_CTLp#ÜR08_RX_ADDR1_Lp#àR09_RX_ADDR2_Lp#äR0A_RX_ADDR3_Lp#èR0B_RX_ADDR4_Lp#ìR0C_RX_ADDR5_Lp#ðR0D_RX_ADDR6_Lp#ôR0E_RX_ADDR7_Lp#øR0F_RX_ADDR_Hp#üR10_RX_ADDR_ENp#€R11_CFGp#„PPRI_RF_TÝI<Ò?”O'NVIC_SystemReset¿ÀÁ__PAN_PRI_RF_H__  PRI_RF_MODE_SEL_TX (0)!PRI_RF_MODE_SEL_RX (1)"PRI_RF_MODE_SEL_TRX (2)(PRI_RF_ADDR_BYTE_LEN_2 (0))PRI_RF_ADDR_BYTE_LEN_3 (1)*PRI_RF_ADDR_BYTE_LEN_4 (2)+PRI_RF_ADDR_BYTE_LEN_5 (3)1PRI_RF_CHIP_MODE_INVALID (0)2PRI_RF_CHIP_MODE_BLE (1)3PRI_RF_CHIP_MODE_297 (2)4PRI_RF_CHIP_MODE_NORDIC (3):REG_FILE_OFST 0x0000;SEQ_RAM_OFST 0x1000<LIST_RAM_OFST 0x8000=TX_RX_RAM_OFST 0x8200>CTE_IQ_RAM_OFST 0xB7FCGLLHWC_READ32_REG(base_addr,reg_ofst) (*(volatile uint32_t *)((0x50020000) + (base_addr) + (reg_ofst)))PLLHWC_WRITE32_REG(base_addr,reg_ofst,data) (*(volatile uint32_t *)(((0x50020000) + (base_addr) + (reg_ofst))) = (data))XREAD_4_BYTES(pckt,pos) (((uint32_t) (pckt)[pos]) | (((uint32_t) (pckt)[pos + 1]) << 8) | (((uint32_t) (pckt)[pos + 2]) << 16) | (((uint32_t) (pckt)[pos + 3]) << 24))ePRI_RF_WRITE_REG_VALUE(base,Reg,Func,Value) (base->Reg = (base->Reg & ~(Reg ## _ ## Func ## _Msk)) | ((Value << Reg ## _ ## Func ## _Pos) & Reg ## _ ## Func ## _Msk))nPRI_RF_READ_REG_VALUE(base,Reg,Func) ((base->Reg & (Reg ## _ ## Func ## _Msk)) >> Reg ## _ ## Func ## _Pos)xPRI_RF_SET_FUNC_ENABLE(base,Reg,Func,State) ((State == ENABLE) ? (base->Reg |= Reg ## _ ## Func ## _Msk) : (base->Reg &= ~Reg ## _ ## Func ## _Msk))ÐÇ ..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\radio\prf_lib\include\..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_pri_rf.hPanSeries.hd


..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\radio\prf_lib\include\pan_pri_rf.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x_Bool;ÒÒPRI_RF_IntFlag$·rf$Ymska__result<„ÝPRI_RF_ForceExitRx$·rf$åNewState<ºèPRI_RF_SetTrxTransWaitTime$·rf$Itime<ûõPRI_RF_EnableRxPipeAdr$·rf$Ipipe$åNewState<ªÿPRI_RF_SetRxGoon$·rf$:en_flag<Ý„PRI_RF_SetAddrMatchBit$·rf$:value<’‰PRI_RF_SetPayloadEndian$·rf$:endian<ÈŽPRI_RF_MultiPreamble$·rf$:pre_length<ô”PRI_RF_StopRx$·rf$:en_flag<œ™PRI_RF_RandomNumGenInit$·rf<ÆžPRI_RF_RandomNumGenReinit$·rf;ÿ£PRI_RF_GetRandomNumY$·rfa__resultY<·€PRI_RF_AutoAnlsPayloadEn$·rf$åNewState"§<î‹PRI_RF_CrcCheckEn$·rf$åNewState< –PRI_RF_Crc16Select$·rf$åNewState<РPRI_RF_ScambleEn$·rf$åNewState<†    «PRI_RF_NordicEnhanceEn$·rf$åNewState;    ´PRI_RF_IsNordicEnhance:$·rfa__result:<ò    ¾PRI_RF_EnhanceEn$·rf$åNewState;¨


ÇPRI_RF_IsEnhance:$·rfa__result:<Ý


ÑPRI_RF_BandWidth2mSel$·rf$åNewState<ŽàPRI_RF_ChipModeSel$·rf$:modeSel;ÆéPRI_RF_GetChipMode:$·rfa__result:<ôôPRI_RF_RxAckEn$·rf$åNewState;ªýPRI_RF_IsRxAckEn:$·rfa__result:<ÚˆPRI_RF_TxNoAckEn$·rf$åNewState;’ ‘PRI_RF_IsTxNoAckEn:$·rfa__result:<à PRI_RF_TrxFuncSel$·rf$åNewState;÷ §PRI_RF_IsRxSel:$·rfa__result:<«±PRI_RF_ClearAllIrqEn$·rf$åNewState<ãÂPRI_RF_IntMask$·rf$Ymsk$åNewStateÃÄÅ _PAN_CLKTRIM_H_ tk ..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_clktrim.h4


..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_clktrim.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x_Bool;ÖKTRIM_IsIntStatusOccured    $Àtrim$Ymska__result    <ˆbTRIM_ClearIntStatusMsk$Àtrim$Ymsk<·mTRIM_EnableInt$Àtrim$åNewState<ðxTRIM_SetRelationIncrease$Àtrim$åNewState<«ƒTRIM_SetEarlyTerminatinEn$Àtrim$åNewState<ېTRIM_SetCoarseCode$Àtrim$Ycode;•šTRIM_GetCoarseCodeY$Àtrima__resultY<äTRIM_SetFineCode$Àtrim$Ycode;û­TRIM_GetFineCodeY$Àtrima__resultY<ª¸TRIM_SetBitWidth$Àtrim$Ywidth;â¼TRIM_GetBitWidthY$Àtrima__resultY<”ÊTRIM_StartTuning$Àtrim$Yfunction<ÀTRIM_SetIdealCnt$Àtrim$Ycnt";ý)TRIM_GetIdealCntY$Àtrima__resultY;³3TRIM_GetRealCntY$Àtrima__resultYÇÈÉPAN_POWER__H_ „x ..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_power.hPanSeries.h|


..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_power.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x*ébuck_out_trim:#lph_ldo_vref_trim:#lpl_ldo_trim:#hp_ldo_trim:#Ppower_param_tËÌÍ


__PAN_HAL_DEF_H__  ÿ ..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\C:\Keil_v5\ARM\ARMCC\Bin\..\include\..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\pan_hal_def.hstdbool.hstdint.hPanSeries.hH


..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_def.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xO“%:"    PDMAC_CallbackFunc´UART_CB_FLAG_TX_FINISHUART_CB_FLAG_RX_FINISHUART_CB_FLAG_RX_TIMEOUTUART_CB_FLAG_RX_BUFFFULLUART_CB_FLAG_DMAPUART_Cb_Flag_Opt0øI2C_CB_FLAG_STOPI2C_CB_FLAG_DMA#PI2C_Cb_Flag_OpţADC_CB_FLAG_DMABPADC_Cb_Flag_Opt"éSPI_CB_FLAG_INTSPI_CB_FLAG_DMA#PSPI_CbFlagOpt>'O%´%%I":"~PUART_CallbackFunc–)OÅ%ø%%I"³PI2C_CallbackFuncÅ*Oó%i%ó%I"I"áPSPI_CallbackFuncù+O§%'%'%I"Y"PADC_CallbackFunc-,ÏÐÑÒ


__PAN_HAL_GPIO_H__ GPIO_P0_PIN_NUM 8GPIO_P1_PIN_NUM 8GPIO_P2_PIN_NUM 8GPIO_P3_PIN_NUM 2GPIO_INTEN_MASK_BASE 0x00010001ULGPIO_INTTYPE_MASK_BASE 0x00000001ULˆ} ..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_gpio.hpan_hal_def.hü


..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_gpio.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xßP0_0P0_1P0_2P0_3P0_4P0_5P0_6P0_7P1_0P1_1P1_2P1_3P1_4P1_5P1_6P1_7P2_0 P2_1!P2_2"P2_3#P2_4$P2_5%P2_6&P2_7'P3_00P3_11PHAL_GPIO_PinId


9¢HAL_GPIO_MODE_INPUT_DIGITALHAL_GPIO_MODE_INPUT_ANALOGHAL_GPIO_MODE_OUTPUT_PUSHPULLHAL_GPIO_MODE_OUTPUT_OPENDRAINHAL_GPIO_MODE_QUASI_BIDIRECTIONALPHAL_GPIO_ModeõEÿHAL_GPIO_PULL_DISABLEHAL_GPIO_PULL_UPHAL_GPIO_PULL_DOWNPHAL_GPIO_Pull·OÆHAL_GPIO_LEVEL_LOWHAL_GPIO_LEVEL_HIGHPHAL_GPIO_LevelX÷HAL_GPIO_INT_RISINGHAL_GPIO_INT_FALLINGHAL_GPIO_INT_BOTH_EDGEHAL_GPIO_INT_HIGHHAL_GPIO_INT_LOWHAL_GPIO_INT_DISABLEPHAL_GPIO_IntMode\eO—%÷"PHAL_GPIO_CallbackFuncj*âmode¢#pullÿ#levelF#PHAL_GPIO_InitTypeDef8}*¸    intMode÷#callbackFunc#debounceå#PHAL_GPIO_IntInitTypeDef~ˆá    qHAL_GPIO_CallbackArrayØ)áHAL_GPIO_CallbackArrayÔÕÖ×


__PAN_HAL_UART_H__ ÆPAN_HAL_UART_INST_COUNT 2ÇUART0_OBJ UART_Handle_Array[0]ÈUART1_OBJ UART_Handle_Array[1]ˆ} ..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_uart.hpan_hal_def.ht


 


..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_uart.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x_Boolt


PHAL_UART_EventOptxPHAL_UART_IntModeOptc(PHAL_UART_TxTrigOpt0PHAL_UART_RxTrigOpt8PHAL_UART_DmaDirOpt    >PHAL_UART_FormatOpt4pPHAL_UART_HandleTypeDef)‰(PHAL_UART_CallbackFuncÓ    ‹PHAL_UART_InitTypeDef×    ”PHAL_UART_IntTypeDefü    ¥)Ë_HAL_UART_HandleTypeDef4pUartxK#initObjð#interruptObj #pTxBuffPtrÍ    #txXferSizeI#txXferCountQ#pRxBuffPtrÍ    # rxXferSizeI#$rxXferCountQ#&isTxBusy#(isRxBusy#)txDmaCh:#*rxDmaCh:#+dmaSrcY#,dmaDstY#0"k tIà³qUART_Handle_ArrayWãHAL_UART_EVT_TX_FINISHHAL_UART_EVT_RX_FINISHHAL_UART_EVT_CONTI_RX_TIMEOUTHAL_UART_EVT_CONTI_RX_BUFF_FULLHAL_UART_EVT_RX_ERR_PARITYHAL_UART_EVT_RX_ERR_FRAMEHAL_UART_EVT_RX_ERR_OVERRUNHAL_UART_EVT_MAX…


HAL_UART_INT_RECV_DATA_AVLHAL_UART_INT_THR_EMPTYHAL_UART_INT_LINE_STATUSHAL_UART_INT_MODEM_STATUSHAL_UART_INT_ALLHAL_UART_INT_DISABLEHAL_UART_TX_FIFO_EMPTYHAL_UART_TX_FIFO_TWO_CHARSHAL_UART_TX_FIFO_QUARTER_FULLHAL_UART_TX_FIFO_HALF_FULL‰HAL_UART_RX_FIFO_ONE_CHARHAL_UART_RX_FIFO_QUARTER_FULLHAL_UART_RX_FIFO_HALF_FULLHAL_UART_RX_FIFO_TWO_LESS_THAN_FULL´HAL_UART_DMA_TXHAL_UART_DMA_RX³HAL_UART_FMT_5_N_1HAL_UART_FMT_5_N_1_5HAL_UART_FMT_5_E_1HAL_UART_FMT_5_E_1_5HAL_UART_FMT_5_O_1HAL_UART_FMT_5_O_1_5HAL_UART_FMT_5_S_18HAL_UART_FMT_5_S_1_5<HAL_UART_FMT_5_M_1(HAL_UART_FMT_5_M_1_5,HAL_UART_FMT_6_N_1HAL_UART_FMT_6_N_2HAL_UART_FMT_6_E_1HAL_UART_FMT_6_E_2HAL_UART_FMT_6_O_1    HAL_UART_FMT_6_O_2 HAL_UART_FMT_6_S_19HAL_UART_FMT_6_S_2=HAL_UART_FMT_6_M_1)HAL_UART_FMT_6_M_2-HAL_UART_FMT_7_N_1HAL_UART_FMT_7_N_2HAL_UART_FMT_7_E_1HAL_UART_FMT_7_E_2HAL_UART_FMT_7_O_1


HAL_UART_FMT_7_O_2HAL_UART_FMT_7_S_1:HAL_UART_FMT_7_S_2>HAL_UART_FMT_7_M_1*HAL_UART_FMT_7_M_2.HAL_UART_FMT_8_N_1HAL_UART_FMT_8_N_2HAL_UART_FMT_8_E_1HAL_UART_FMT_8_E_2HAL_UART_FMT_8_O_1HAL_UART_FMT_8_O_2HAL_UART_FMT_8_S_1;HAL_UART_FMT_8_S_2?HAL_UART_FMT_8_M_1+HAL_UART_FMT_8_M_2/OÉ%É    %%Í    %I"³":"³    *übaudRateY#format™#*ötxTrigLevelK#rxTrigLevele#IRQnƒ#IrqPriority:#continuousRxMode#callbackFuncÒ#$x


`UART_Handle_ArrayÙÚÛÜ__PAN_HAL_DMAC_H__ ;DMAC_CHANNEL_NUMS 2=DMAC_Channel_0 DMAC_Channel_Array[0]>DMAC_Channel_1 DMAC_Channel_Array[1]ˆ} ..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_dmac.hpan_hal_def.h|


..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_dmac.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xuvoid"


"YPDMAC_Peri_Mode_OptNPDMAC_HandleTypeDef˜9×4qDMAC_Channel_ArrayNqdma_uart2mem_config7qdma_mem2uart_config7qdma_spi2mem_config7qdma_mem2spi_config7qdma_mem2i2c_config7qdma_i2c2mem_config7qdma_adc2mem_config7qdma_mem2i2c_u16_config7˜DMAC_Peri_UARTDMAC_Peri_I2CDMAC_Peri_SPIDMAC_Peri_ADC*õ8dmau#periph#ConfigTmp7#Callback#CallbackUartš#CallbackI2cÉ# CallbackSpiý#$CallbackAdc1#(PeriMode#,pBuffPtr#0XferSizeI#4XferCountI#6"Sã€WDMAC_Channel_Arraypdma_uart2mem_configŒdma_mem2uart_config¨dma_spi2mem_configÃdma_mem2spi_configÞdma_mem2i2c_configùdma_i2c2mem_configdma_adc2mem_config/dma_mem2i2c_u16_configÞßàá _PAN_HAL_SPI_H_ SPI_RX_BUF_SIZE 256SPI_TX_BUF_SIZE 256oSPI0_OBJ spiHandleArray[0]vSPI1_OBJ spiHandleArray[1]ˆ| ..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_spi.hpan_hal_def.h


..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_spi.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x*œModeÊ#PSPI_InterruptOptDef    !­BAUDRATE_100K †BAUDRATE_500K ¡BAUDRATE_1M@BBAUDRATE_2M€„BAUDRATE_5M@KLBAUDRATE_10M€–˜PSPI_BaudRate7-*²role #dataSizeB    #clkPolarity#clkPhase~#baudrateDiv¿


#formaté#PSPI_InitOptDefÁ;SPI_STAT_NULLSPI_STAT_RXSPI_STAT_TXSPI_STAT_RXTXPSPI_XferStatOptHC*È4pSpixÈ#initObj2#xferStat#


interruptObj#pTxBuffPtrÎ#txXferSizeI#txXferCountÔ#pRxBuffPtrÎ#rxXferSizeI#rxXferCountÔ#IRQnƒ#rxIntCallbacký# txIntCallbacký#$dmaSrcY#(dmaDstY#,errorCodeÚ#0""ItItYPSPI_HandleTypeDef¤a‚àqspiHandleArrayù!spiHandleArrayãäå__PAN_HAL_I2C_H ˆ| ..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_i2c.hpan_hal_def.h


..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_i2c.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x±I2C_ADDR_7BITI2C_ADDR_10BITPI2C_AddressMode_Opt    öI2C_ROLE_MASTER!I2C_ROLE_SLAVEPI2C_Role_OptL'ºI2C_DUTYCYCLE_16_9@I2C_DUTYCYCLE_2ÿ¿PI2C_DutyCycle_OptŠ2õI2C_DIR_TXI2C_DIR_RXPI2C_Direction_OptÓ=ÀI2C_ACK_ADDR_7BIT@I2C_ACK_ADDR_10BITÀPI2C_AckAddr_OptHÖI2C_SPEED_100K †I2C_SPEED_200K@ I2C_SPEED_400K€I2C_SPEED_500K ¡I2C_SPEED_1M@BI2C_SPEED_2M€„PI2C_ClockSpeed_OptWW*ÝClockSpeedÖ#Rolev#DutyCycleº#OwnAddressI#AckAddress@#


AddressMode1#PI2C_Init_Optðo’I2C_Tx_DirI2C_Rx_DirPI2C_Xfer_Dir_Optqt*½pass:#PI2C_Interrupt_Optªy*ð    @I2Cxð#I2C_InitObj]#InterruptObj½#pTxBuffPtrö#TxXferSizeI#TxXferCountü#pRxBuffPtrö# RxXferSizeI#$RxXferCountü#&IRQnƒ#(RxIntCallbackÉ#,TxIntCallbackÉ#0DMA_SRCY#4DMA_DSTY#8StopFlag:#<"Z":tIPI2C_HandleTypeDefÖ™çèé__PAN_HAL_WDT_H ˆ| ..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_wdt.hpan_hal_def.hØ


..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_wdt.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x*óTimeout_#ResetDelayð#ClockSourceY#ResetSwitchY#WakeupSwitchY#PWDT_Init_Opt    !O‹"‡PWDT_CallbackFunc‹&*ÀCallbackFunc#PWDT_Interrupt_Opt§/ëìí __PAN_HAL_WWDT_H ˆ} ..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_wwdt.hpan_hal_def.h°


..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_wwdt.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xOŽ"


PWWDT_CallbackFunc*êPrescaler†#ClockSourceY#CmpValueY#PWWDT_Init_Opt+$*˜CallbackFunc#PWWDT_Interrupt_Opt-ïðñ__PAN_HAL_PWM_H JHAL_PWM_PinConfiguration(port,bit,chId) (SYS->port ## _MFP = (SYS->port ## _MFP & ~SYS_MFP_ ## port ## bit ## _Msk) | SYS_MFP_ ## port ## bit ## _ ## chId)ˆ| ..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_pwm.hpan_hal_def.h|


..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_pwm.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x_BoolPPWM_ChIdH#PPWM_ModeOpt­0PPWM_InitOpt?­PWM0_CH0PWM0_CH1PWM0_CH2PWM0_CH3PWM0_CH4PWM0_CH5PWM0_CH6PWM0_CH7PWM_MODE_INDEPENDENTPWM_MODE_COMPLEMENTARYPWM_MODE_SYNCHRONIZEDPWM_MODE_GROUP*þfrequencyY#dutyCycleY#operateType=#mode"#


inverter    #lowPowerEn    # óôõö__PAN_HAL_TIMER_H _TIMER0_OBJ TIMER_Handle_Array[0]`TIMER1_OBJ TIMER_Handle_Array[1]aTIMER2_OBJ TIMER_Handle_Array[2]ˆ~ ..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_timer.hpan_hal_def.h8


..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_timer.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xÎTIMER_CB_FLAG_CNTTIMER_CB_FLAG_CAPTIMER_CB_FLAG_WKPTIMER_Cb_Flag_Opt!Oï%N"gPTIMER_CallbackFunco(èTIMER_MODE_BASECNTTIMER_MODE_EVENTCNTTIMER_MODE_INCAPTIMER_MODE_WAKEUPPTIMER_Mode_Opt5*‘pass:#PTIMER_Interrupt_Optþ;*Ú$freqY#modeè#cntModeÈ#capModeg#cmpValueY#capEdge@#evtCntEdge­#capSrc$    #prescaleY#tmr0CmpSel¥    # PTIMER_Init_Opt,N*Ä0TIMERxD#initObjÚ#interruptObj#(IRQnƒ#)callbacks#,"€PTIMER_HandleTypeDefð]îJqTIMER_Handle_Arraye;ßeHAL_TIMER_US_TO_CNTY$YtimeUs$ifrequencya__resultY\cnti;·lHAL_TIMER_MS_TO_CNTY$YtimeMs$ifrequencya__resultY\cnti%<nTIMER_Handle_Arrayøùú __PAN_HAL_ADC_H ˆ| ..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_adc.hpan_hal_def.hL


..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal_adc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xðADC_MODE_CONVADC_MODE_EXTRIGADC_MODE_COMPAREADC_MODE_PWMSEQADC_MODE_SGLCONVSEQPADC_ModeOpt    #ßADC_CONV_MODE_BASEADC_CONV_MODE_TEMPADC_CONV_MODE_VBGADC_CONV_MODE_VDD4PADC_ConvertModeOptƒ0ƒADC_CH0ADC_CH1ADC_CH2ADC_CH3ADC_CH4ADC_CH5ADC_CH6ADC_CH7ADC_CH_TEMP    ADC_CH_BATTERY


ADC_IDLEÿPADC_ChIdùEÇADC_INPUT_RANGE_LOWADC_INPUT_RANGE_HIGHPADC_InputRangeOpt“R*ƒInputRangeÇ#Modep#PADC_InitOptà`*´initOpt#idƒ#PADC_HandleTypeDeflüýþ__PAN_HAL_H__ HAL_TIME_FOREVER 0xFFFFFFFFUHAL_ASSERT SYS_ASSERT!"#$%'(    )


*+PAN_IO_TIMING_TRACK_INIT_PIN(__VA_ARGS__...) ŽPAN_IO_TIMING_TRACK_LEVEL(__VA_ARGS__...) PAN_IO_TIMING_TRACK_TOGGLE(__VA_ARGS__...) TH ..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\C:\Keil_v5\ARM\ARMCC\Bin\..\include\pan_hal.hstdint.hpan_hal_gpio.hpan_hal_uart.hpan_hal_dmac.hpan_hal_spi.hpan_hal_i2c.hpan_hal_wdt.hpan_hal_wwdt.hpan_hal_pwm.hpan_hal_timer.hpan_hal_adc.hä


..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc\pan_hal.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x‰HAL_SUCCESSHAL_INVALID_PARAMSHAL_IO_ERRORHAL_DEVICE_BUSYHAL_NO_MEMHAL_NO_HARDWARE_SOURCEHAL_UNKNOWNPHAL_ErrorÑHAL_OKHAL_ERRORHAL_BUSYHAL_TIMEOUTPHAL_StatusšFREERTOS_CONFIG_H -346configUSE_TICKLESS_IDLE CONFIG_PM9configCPU_CLOCK_HZ (SystemCoreClock)EconfigTICK_RATE_HZ ((TickType_t)1000)MconfigMINIMAL_STACK_SIZE ((uint16_t)64)OconfigSUPPORT_DYNAMIC_ALLOCATION 1PconfigSUPPORT_STATIC_ALLOCATION 0WconfigUSE_PREEMPTION 1XconfigUSE_TIME_SLICING 1YconfigIDLE_SHOULD_YIELD 1ZconfigMAX_TASK_NAME_LEN (16)[configUSE_16_BIT_TICKS 0qconfigUSE_MUTEXES 1rconfigUSE_RECURSIVE_MUTEXES 1sconfigUSE_COUNTING_SEMAPHORES 1tconfigUSE_QUEUE_SETS 1uconfigUSE_TASK_NOTIFICATIONS 1wconfigEXPECTED_IDLE_TIME_BEFORE_SLEEP 3xconfigUSE_APPLICATION_TASK_TAG 0yconfigUSE_NEWLIB_REENTRANT 0zconfigUSE_CO_ROUTINES 0~configQUEUE_REGISTRY_SIZE 10configASSERT(x) {if((x) == 0) {while(1){};}}configUSE_DAEMON_TASK_STARTUP_HOOK 0–configENABLE_MPU 0—configENABLE_FPU 0˜configENABLE_TRUSTZONE 1™configMINIMAL_SECURE_STACK_SIZE ((uint32_t)1024)šconfigRUN_FREERTOS_SECURE_ONLY 0configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES 0¢configPRIO_BITS __NVIC_PRIO_BITS©configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x03¯configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 0³configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))·configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))½INCLUDE_vTaskPrioritySet 1¾INCLUDE_uxTaskPriorityGet 1¿INCLUDE_vTaskDelete 1ÀINCLUDE_vTaskSuspend 1ÁINCLUDE_vTaskDelayUntil 1ÂINCLUDE_vTaskDelay 1ÃINCLUDE_xTaskGetIdleTaskHandle 1ÄINCLUDE_xTaskAbortDelay 1ÅINCLUDE_xQueueGetMutexHolder 1ÆINCLUDE_xSemaphoreGetMutexHolder 1ÇINCLUDE_xTaskGetHandle 1ÈINCLUDE_uxTaskGetStackHighWaterMark 1ÉINCLUDE_uxTaskGetStackHighWaterMark2 1ÊINCLUDE_eTaskGetState 1ËINCLUDE_xTaskResumeFromISR 1ÌINCLUDE_xTimerPendFunctionCall 1ÍINCLUDE_xTaskGetSchedulerState 1ÎINCLUDE_xTaskGetCurrentTaskHandle 1ÒxPortPendSVHandler PendSV_HandlerÓvPortSVCHandler SVC_HandlerÔxPortSysTickHandler SysTick_Handlerìã ..\..\..\..\config\C:\Keil_v5\ARM\ARMCC\Bin\..\include\..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include\.\configuration\FreeRTOSConfig.hstdint.hPanSeries.hsdk_config.h


..\..\..\..\config\FreeRTOSConfig.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xqSystemCoreClockYqclk_32k_freqY3ÙSystemCoreClockñclk_32k_freqPROJDEFS_H *pdMS_TO_TICKS(xTimeInMs) ( ( TickType_t ) ( ( ( TickType_t ) ( xTimeInMs ) * ( TickType_t ) configTICK_RATE_HZ ) / ( TickType_t ) 1000U ) )-pdFALSE ( ( BaseType_t ) 0 ).pdTRUE ( ( BaseType_t ) 1 )0pdPASS ( pdTRUE )1pdFAIL ( pdFALSE )2errQUEUE_EMPTY ( ( BaseType_t ) 0 )3errQUEUE_FULL ( ( BaseType_t ) 0 )6errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ( -1 )7errQUEUE_BLOCKED ( -4 )8errQUEUE_YIELD ( -5 )BpdINTEGRITY_CHECK_VALUE 0x5a5a5a5aULGpdFREERTOS_ERRNO_NONE 0HpdFREERTOS_ERRNO_ENOENT 2IpdFREERTOS_ERRNO_EINTR 4JpdFREERTOS_ERRNO_EIO 5KpdFREERTOS_ERRNO_ENXIO 6LpdFREERTOS_ERRNO_EBADF 9MpdFREERTOS_ERRNO_EAGAIN 11NpdFREERTOS_ERRNO_EWOULDBLOCK 11OpdFREERTOS_ERRNO_ENOMEM 12PpdFREERTOS_ERRNO_EACCES 13QpdFREERTOS_ERRNO_EFAULT 14RpdFREERTOS_ERRNO_EBUSY 16SpdFREERTOS_ERRNO_EEXIST 17TpdFREERTOS_ERRNO_EXDEV 18UpdFREERTOS_ERRNO_ENODEV 19VpdFREERTOS_ERRNO_ENOTDIR 20WpdFREERTOS_ERRNO_EISDIR 21XpdFREERTOS_ERRNO_EINVAL 22YpdFREERTOS_ERRNO_ENOSPC 28ZpdFREERTOS_ERRNO_ESPIPE 29[pdFREERTOS_ERRNO_EROFS 30\pdFREERTOS_ERRNO_EUNATCH 42]pdFREERTOS_ERRNO_EBADE 50^pdFREERTOS_ERRNO_EFTYPE 79_pdFREERTOS_ERRNO_ENMFILE 89`pdFREERTOS_ERRNO_ENOTEMPTY 90apdFREERTOS_ERRNO_ENAMETOOLONG 91bpdFREERTOS_ERRNO_EOPNOTSUPP 95cpdFREERTOS_ERRNO_ENOBUFS 105dpdFREERTOS_ERRNO_ENOPROTOOPT 109epdFREERTOS_ERRNO_EADDRINUSE 112fpdFREERTOS_ERRNO_ETIMEDOUT 116gpdFREERTOS_ERRNO_EINPROGRESS 119hpdFREERTOS_ERRNO_EALREADY 120ipdFREERTOS_ERRNO_EADDRNOTAVAIL 125jpdFREERTOS_ERRNO_EISCONN 127kpdFREERTOS_ERRNO_ENOTCONN 128lpdFREERTOS_ERRNO_ENOMEDIUM 135mpdFREERTOS_ERRNO_EILSEQ 138npdFREERTOS_ERRNO_ECANCELED 140rpdFREERTOS_LITTLE_ENDIAN 1spdFREERTOS_BIG_ENDIAN 0vpdLITTLE_ENDIAN pdFREERTOS_LITTLE_ENDIANwpdBIG_ENDIAN pdFREERTOS_BIG_ENDIANLB ..\..\..\..\os\freertos\include\projdefs.h


..\..\..\..\os\freertos\include\projdefs.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xuvoid"à"PTaskFunction_tê$OŒ%æ    


DEPRECATED_DEFINITIONS_H \P ..\..\..\..\os\freertos\include\deprecated_definitions.hì


..\..\..\..\os\freertos\include\deprecated_definitions.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x PORTMACRO_H 14portCHAR char5portFLOAT float6portDOUBLE double7portLONG long8portSHORT short9portSTACK_TYPE uint32_t:portBASE_TYPE longIportMAX_DELAY ( TickType_t ) 0xffffffffULNportTICK_TYPE_IS_ATOMIC 1SportSTACK_GROWTH ( -1 )VportBYTE_ALIGNMENT 8\portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )]portNVIC_PENDSVSET_BIT ( 1UL << 28UL )^portYIELD() vPortYield()_portEND_SWITCHING_ISR(xSwitchRequired) do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )`portYIELD_FROM_ISR(x) portEND_SWITCHING_ISR( x )iportSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()jportCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )kportDISABLE_INTERRUPTS() __set_PRIMASK(1)lportENABLE_INTERRUPTS() __set_PRIMASK(0)mportENTER_CRITICAL() vPortEnterCritical()nportEXIT_CRITICAL() vPortExitCritical()uportSUPPRESS_TICKS_AND_SLEEP(xExpectedIdleTime) vPortSuppressTicksAndSleep( xExpectedIdleTime )zportTASK_FUNCTION_PROTO(vFunction,pvParameters) void vFunction( void * pvParameters ){portTASK_FUNCTION(vFunction,pvParameters) void vFunction( void * pvParameters )}portNOP() „y ..\..\..\..\os\freertos\portable\RVDS\ARM_CM0\..\..\..\..\config\portmacro.hFreeRTOSConfig.hT


..\..\..\..\os\freertos\portable\RVDS\ARM_CM0\portmacro.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xlongunsigned longPStackType_tY<PBaseType_tï=PUBaseType_t÷>PTickType_tYHMPU_WRAPPERS_H ±PRIVILEGED_FUNCTION ²PRIVILEGED_DATA ³FREERTOS_SYSTEM_CALL PF ..\..\..\..\os\freertos\include\mpu_wrappers.hä


..\..\..\..\os\freertos\include\mpu_wrappers.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x"PORTABLE_H .5=portBYTE_ALIGNMENT_MASK ( 0x0007 )IportUSING_MPU_WRAPPERS 0MportNUM_CONFIGURABLE_REGIONS 1QportHAS_STACK_OVERFLOW_CHECKING 0UportARCH_NAME NULLZconfigSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0c»pvPortMallocStack pvPortMalloc¼vPortFreeStack vPortFreeèLPTMR_CURR_CNT_VAL_REG (0x50020014)¸® ..\..\..\..\os\freertos\include\..\..\..\..\os\freertos\portable\RVDS\ARM_CM0\portable.hdeprecated_definitions.hportmacro.hmpu_wrappers.h


..\..\..\..\os\freertos\include\portable.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x)HeapRegionpucStartAddress#xSizeInBytesÖ#":PHeapRegion_tà‹)ÌxHeapStatsxAvailableHeapSpaceInBytesÖ#xSizeOfLargestFreeBlockInBytesÖ#xSizeOfSmallestFreeBlockInBytesÖ#xNumberOfFreeBlocksÖ#xMinimumEverFreeBytesRemainingÖ#xNumberOfSuccessfulAllocationsÖ#xNumberOfSuccessfulFreesÖ#PHeapStats_t8—;’élp_get_curr_tmr_cntYa__resultYINC_FREERTOS_H #2;>AjconfigUSE_C_RUNTIME_TLS_SUPPORT 0ÈINCLUDE_xTaskDelayUntil INCLUDE_vTaskDelayUntil“configNUM_THREAD_LOCAL_STORAGE_POINTERS 0§configUSE_ALTERNATIVE_API 0«portCRITICAL_NESTING_IN_TCB 0¾configASSERT_DEFINED 1ÇconfigPRECONDITION(X) configASSERT( X )ÈconfigPRECONDITION_DEFINED 0ÎportMEMORY_BARRIER() ÒportSOFTWARE_BARRIER() ïportCLEAN_UP_TCB(pxTCB) ( void ) ( pxTCB )óportPRE_TASK_DELETE_HOOK(pvTaskToDelete,pxYieldPending) ÷portSETUP_TCB(pxTCB) ( void ) ( pxTCB )…configUSE_MINI_LIST_ITEM 1‰portPOINTER_SIZE_TYPE uint32_t‘traceSTART() ˜traceEND() ŸtraceTASK_SWITCHED_IN() ¦traceINCREASE_TICK_COUNT(x) «traceLOW_POWER_IDLE_BEGIN() °traceLOW_POWER_IDLE_END() ·traceTASK_SWITCHED_OUT() ÁtraceTASK_PRIORITY_INHERIT(pxTCBOfMutexHolder,uxInheritedPriority) ÊtraceTASK_PRIORITY_DISINHERIT(pxTCBOfMutexHolder,uxOriginalPriority) ÓtraceBLOCKING_ON_QUEUE_RECEIVE(pxQueue) ÜtraceBLOCKING_ON_QUEUE_PEEK(pxQueue) åtraceBLOCKING_ON_QUEUE_SEND(pxQueue) íconfigRECORD_STACK_HIGH_ADDRESS 0ñconfigINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 0÷traceMOVED_TASK_TO_READY_STATE(pxTCB) ûtracePOST_MOVED_TASK_TO_READY_STATE(pxTCB) ÿtraceQUEUE_CREATE(pxNewQueue) ƒtraceQUEUE_CREATE_FAILED(ucQueueType) ‡traceCREATE_MUTEX(pxNewQueue) ‹traceCREATE_MUTEX_FAILED() traceGIVE_MUTEX_RECURSIVE(pxMutex) “traceGIVE_MUTEX_RECURSIVE_FAILED(pxMutex) —traceTAKE_MUTEX_RECURSIVE(pxMutex) ›traceTAKE_MUTEX_RECURSIVE_FAILED(pxMutex) ŸtraceCREATE_COUNTING_SEMAPHORE() £traceCREATE_COUNTING_SEMAPHORE_FAILED() §traceQUEUE_SET_SEND traceQUEUE_SEND«traceQUEUE_SEND(pxQueue) ¯traceQUEUE_SEND_FAILED(pxQueue) ³traceQUEUE_RECEIVE(pxQueue) ·traceQUEUE_PEEK(pxQueue) »traceQUEUE_PEEK_FAILED(pxQueue) ¿traceQUEUE_PEEK_FROM_ISR(pxQueue) ÃtraceQUEUE_RECEIVE_FAILED(pxQueue) ÇtraceQUEUE_SEND_FROM_ISR(pxQueue) ËtraceQUEUE_SEND_FROM_ISR_FAILED(pxQueue) ÏtraceQUEUE_RECEIVE_FROM_ISR(pxQueue) ÓtraceQUEUE_RECEIVE_FROM_ISR_FAILED(pxQueue) ×traceQUEUE_PEEK_FROM_ISR_FAILED(pxQueue) ÛtraceQUEUE_DELETE(pxQueue) ßtraceTASK_CREATE(pxNewTCB) ãtraceTASK_CREATE_FAILED() çtraceTASK_DELETE(pxTaskToDelete) ëtraceTASK_DELAY_UNTIL(x) ïtraceTASK_DELAY() ótraceTASK_PRIORITY_SET(pxTask,uxNewPriority) ÷traceTASK_SUSPEND(pxTaskToSuspend) ûtraceTASK_RESUME(pxTaskToResume) ÿtraceTASK_RESUME_FROM_ISR(pxTaskToResume) ƒtraceTASK_INCREMENT_TICK(xTickCount) ‡traceTIMER_CREATE(pxNewTimer) ‹traceTIMER_CREATE_FAILED() traceTIMER_COMMAND_SEND(xTimer,xMessageID,xMessageValueValue,xReturn) “traceTIMER_EXPIRED(pxTimer) —traceTIMER_COMMAND_RECEIVED(pxTimer,xMessageID,xMessageValue) ›traceMALLOC(pvAddress,uiSize) ŸtraceFREE(pvAddress,uiSize) £traceEVENT_GROUP_CREATE(xEventGroup) §traceEVENT_GROUP_CREATE_FAILED() «traceEVENT_GROUP_SYNC_BLOCK(xEventGroup,uxBitsToSet,uxBitsToWaitFor) ¯traceEVENT_GROUP_SYNC_END(xEventGroup,uxBitsToSet,uxBitsToWaitFor,xTimeoutOccurred) ( void ) ( xTimeoutOccurred )³traceEVENT_GROUP_WAIT_BITS_BLOCK(xEventGroup,uxBitsToWaitFor) ·traceEVENT_GROUP_WAIT_BITS_END(xEventGroup,uxBitsToWaitFor,xTimeoutOccurred) ( void ) ( xTimeoutOccurred )»traceEVENT_GROUP_CLEAR_BITS(xEventGroup,uxBitsToClear) ¿traceEVENT_GROUP_CLEAR_BITS_FROM_ISR(xEventGroup,uxBitsToClear) ÃtraceEVENT_GROUP_SET_BITS(xEventGroup,uxBitsToSet) ÇtraceEVENT_GROUP_SET_BITS_FROM_ISR(xEventGroup,uxBitsToSet) ËtraceEVENT_GROUP_DELETE(xEventGroup) ÏtracePEND_FUNC_CALL(xFunctionToPend,pvParameter1,ulParameter2,ret) ÓtracePEND_FUNC_CALL_FROM_ISR(xFunctionToPend,pvParameter1,ulParameter2,ret) ×traceQUEUE_REGISTRY_ADD(xQueue,pcQueueName) ÛtraceTASK_NOTIFY_TAKE_BLOCK(uxIndexToWait) ßtraceTASK_NOTIFY_TAKE(uxIndexToWait) ãtraceTASK_NOTIFY_WAIT_BLOCK(uxIndexToWait) çtraceTASK_NOTIFY_WAIT(uxIndexToWait) ëtraceTASK_NOTIFY(uxIndexToNotify) ïtraceTASK_NOTIFY_FROM_ISR(uxIndexToNotify) ótraceTASK_NOTIFY_GIVE_FROM_ISR(uxIndexToNotify) ÷traceSTREAM_BUFFER_CREATE_FAILED(xIsMessageBuffer) ûtraceSTREAM_BUFFER_CREATE_STATIC_FAILED(xReturn,xIsMessageBuffer) ÿtraceSTREAM_BUFFER_CREATE(pxStreamBuffer,xIsMessageBuffer) ƒtraceSTREAM_BUFFER_DELETE(xStreamBuffer) ‡traceSTREAM_BUFFER_RESET(xStreamBuffer) ‹traceBLOCKING_ON_STREAM_BUFFER_SEND(xStreamBuffer) traceSTREAM_BUFFER_SEND(xStreamBuffer,xBytesSent) “traceSTREAM_BUFFER_SEND_FAILED(xStreamBuffer) —traceSTREAM_BUFFER_SEND_FROM_ISR(xStreamBuffer,xBytesSent) ›traceBLOCKING_ON_STREAM_BUFFER_RECEIVE(xStreamBuffer) ŸtraceSTREAM_BUFFER_RECEIVE(xStreamBuffer,xReceivedLength) £traceSTREAM_BUFFER_RECEIVE_FAILED(xStreamBuffer) §traceSTREAM_BUFFER_RECEIVE_FROM_ISR(xStreamBuffer,xReceivedLength) «configGENERATE_RUN_TIME_STATS 0½portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() ÅportPRIVILEGE_BIT ( ( UBaseType_t ) 0x00 )ÉportYIELD_WITHIN_API portYIELDÝconfigPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING(x) áconfigPRE_SLEEP_PROCESSING(x) åconfigPOST_SLEEP_PROCESSING(x) íportTASK_USES_FLOATING_POINT() ñportALLOCATE_SECURE_CONTEXT(ulSecureStackSize) õportDONT_DISCARD ýconfigINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS 0configUSE_STATS_FORMATTING_FUNCTIONS 0…portASSERT_IF_INTERRUPT_PRIORITY_INVALID() ‰configUSE_TRACE_FACILITY 0mtCOVERAGE_TEST_MARKER() ‘mtCOVERAGE_TEST_DELAY() •portASSERT_IF_IN_ISR() ™configUSE_PORT_OPTIMISED_TASK_SELECTION 0configAPPLICATION_ALLOCATED_HEAP 0¥configTASK_NOTIFICATION_ARRAY_ENTRIES 1­configUSE_POSIX_ERRNO 0³configUSE_SB_COMPLETED_CALLBACK 0ÒconfigSTACK_DEPTH_TYPE uint16_tÚconfigRUN_TIME_COUNTER_TYPE uint32_tâconfigMESSAGE_BUFFER_LENGTH_TYPE size_tïconfigINITIAL_TICK_COUNT 0ÿportTICK_TYPE_ENTER_CRITICAL() €portTICK_TYPE_EXIT_CRITICAL() portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() 0‚portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR(x) ( void ) ( x )ˆconfigENABLE_BACKWARD_COMPATIBILITY 1—configPRINTF(X) žconfigMAX(a,b) ( ( ( a ) > ( b ) ) ? ( a ) : ( b ) )¥configMIN(a,b) ( ( ( a ) < ( b ) ) ? ( a ) : ( b ) )©eTaskStateGet eTaskGetStateªportTickType TickType_t«xTaskHandle TaskHandle_t¬xQueueHandle QueueHandle_t­xSemaphoreHandle SemaphoreHandle_t®xQueueSetHandle QueueSetHandle_t¯xQueueSetMemberHandle QueueSetMemberHandle_t°xTimeOutType TimeOut_t±xMemoryRegion MemoryRegion_t²xTaskParameters TaskParameters_t³xTaskStatusType TaskStatus_t´xTimerHandle TimerHandle_tµxCoRoutineHandle CoRoutineHandle_t¶pdTASK_HOOK_CODE TaskHookFunction_t·portTICK_RATE_MS portTICK_PERIOD_MS¸pcTaskGetTaskName pcTaskGetName¹pcTimerGetTimerName pcTimerGetNameºpcQueueGetQueueName pcQueueGetName»vTaskGetTaskInfo vTaskGetInfo¼xTaskGetIdleRunTimeCounter ulTaskGetIdleRunTimeCounterÀtmrTIMER_CALLBACK TimerCallbackFunction_tÁpdTASK_CODE TaskFunction_tÂxListItem ListItem_tÃxList List_tÇpxContainer pvContainerÓconfigUSE_TASK_FPU_SUPPORT 1åconfigENABLE_MVE 0õconfigRUN_ADDITIONAL_TESTS 0£    tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE ( ( ( portUSING_MPU_WRAPPERS == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) || ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) )Ìà ..\..\..\..\os\freertos\include\C:\Keil_v5\ARM\ARMCC\Bin\..\include\..\..\..\..\config\FreeRTOS.hstddef.hstdint.hFreeRTOSConfig.hprojdefs.hportable.hP


..\..\..\..\os\freertos\include\FreeRTOS.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xuvoid"àPStaticListItem_t¼    ")ÉxSTATIC_MINI_LIST_ITEMxDummy2B#¸æpvDummy3/#PStaticMiniListItem_tÈ    +)©xSTATIC_LISTuxDummy2/#pvDummy3æ#xDummy4I#PStaticList_tfÙ    )›xSTATIC_TCBTpxDummy1æ#çêxDummy3Þ#uxDummy5/#,pxDummy6æ#0£:ucDummy7#4¾/uxDummy123#DÚYulDummy18O#Lö:ucDummy19k#PucDummy21:#QPStaticTask_t¾˜


SÑpvDummy2æuxDummy2/)äxSTATIC_QUEUELìæpvDummy1ã#u°#Ž©xDummy3#¨/uxDummy4#8Ã:ucDummy58#DpvDummy7æ#HPStaticQueue_tÑÂ


PStaticSemaphore_tdÃ


)ÍxSTATIC_EVENT_GROUPxDummy1B#xDummy2©#PStaticEventGroup_t”ß


)ßxSTATIC_TIMER(pvDummy1æ#xDummy2ê#xDummy3B#pvDummy5æ#pvDummy6î# ucDummy8:#$PStaticTimer_tèú


)Ö    xSTATIC_STREAM_BUFFER š    ÖuxDummy1#³    æpvDummy2ª#ucDummy3:#PStaticStreamBuffer_tu•PStaticMessageBuffer_tÖ˜)Ò


xSTATIC_LIST_ITEMxDummy2B#Á


æpvDummy38#;LIST_H ^configLIST_VOLATILE nlistFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE olistSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE plistFIRST_LIST_INTEGRITY_CHECK_VALUE qlistSECOND_LIST_INTEGRITY_CHECK_VALUE rlistSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE(pxItem) slistSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE(pxItem) tlistSET_LIST_INTEGRITY_CHECK_1_VALUE(pxList) ulistSET_LIST_INTEGRITY_CHECK_2_VALUE(pxList) vlistTEST_LIST_ITEM_INTEGRITY(pxItem) wlistTEST_LIST_INTEGRITY(pxList) ¼listSET_LIST_ITEM_OWNER(pxListItem,pxOwner) ( ( pxListItem )->pvOwner = ( void * ) ( pxOwner ) )ÅlistGET_LIST_ITEM_OWNER(pxListItem) ( ( pxListItem )->pvOwner )ÎlistSET_LIST_ITEM_VALUE(pxListItem,xValue) ( ( pxListItem )->xItemValue = ( xValue ) )ØlistGET_LIST_ITEM_VALUE(pxListItem) ( ( pxListItem )->xItemValue )álistGET_ITEM_VALUE_OF_HEAD_ENTRY(pxList) ( ( ( pxList )->xListEnd ).pxNext->xItemValue )élistGET_HEAD_ENTRY(pxList) ( ( ( pxList )->xListEnd ).pxNext )ñlistGET_NEXT(pxListItem) ( ( pxListItem )->pxNext )ùlistGET_END_MARKER(pxList) ( ( ListItem_t const * ) ( &( ( pxList )->xListEnd ) ) )‚listLIST_IS_EMPTY(pxList) ( ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) ? pdTRUE : pdFALSE )‡listCURRENT_LIST_LENGTH(pxList) ( ( pxList )->uxNumberOfItems )listGET_OWNER_OF_NEXT_ENTRY(pxTCB,pxList) { List_t * const pxConstList = ( pxList ); ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; if( ( void * ) ( pxConstList )->pxIndex == ( void * ) &( ( pxConstList )->xListEnd ) ) { ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; } ( pxTCB ) = ( pxConstList )->pxIndex->pvOwner; }ºlistREMOVE_ITEM(pxItemToRemove) { List_t * const pxList = ( pxItemToRemove )->pxContainer; ( pxItemToRemove )->pxNext->pxPrevious = ( pxItemToRemove )->pxPrevious; ( pxItemToRemove )->pxPrevious->pxNext = ( pxItemToRemove )->pxNext; if( pxList->pxIndex == ( pxItemToRemove ) ) { pxList->pxIndex = ( pxItemToRemove )->pxPrevious; } ( pxItemToRemove )->pxContainer = NULL; ( pxList->uxNumberOfItems )--; }âlistINSERT_END(pxList,pxNewListItem) { ListItem_t * const pxIndex = ( pxList )->pxIndex; listTEST_LIST_INTEGRITY( ( pxList ) ); listTEST_LIST_ITEM_INTEGRITY( ( pxNewListItem ) ); ( pxNewListItem )->pxNext = pxIndex; ( pxNewListItem )->pxPrevious = pxIndex->pxPrevious; pxIndex->pxPrevious->pxNext = ( pxNewListItem ); pxIndex->pxPrevious = ( pxNewListItem ); ( pxNewListItem )->pxContainer = ( pxList ); ( ( pxList )->uxNumberOfItems )++; }‹listGET_OWNER_OF_HEAD_ENTRY(pxList) ( ( &( ( pxList )->xListEnd ) )->pxNext->pvOwner )–listIS_CONTAINED_WITHIN(pxList,pxListItem) ( ( ( pxListItem )->pxContainer == ( pxList ) ) ? ( pdTRUE ) : ( pdFALSE ) )žlistLIST_ITEM_CONTAINER(pxListItem) ( ( pxListItem )->pxContainer )¥listLIST_IS_INITIALISED(pxList) ( ( pxList )->xListEnd.xItemValue == portMAX_DELAY )H> ..\..\..\..\os\freertos\include\list.h 


..\..\..\..\os\freertos\include\list.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xuvoid"ÜPListItem_t³š)ÂxMINI_LIST_ITEMxItemValueB#pxNext#pxPrevious#PMiniListItem_tù¤$)šxLISTuxNumberOfItemsš#pxIndex #xListEndB#t/"æPList_tY³)xLIST_ITEMxItemValueB#pxNext#pxPrevious#pvOwnerâ#"YpvContainer#"³!"#INC_TASK_H %8tskKERNEL_VERSION_NUMBER "V10.5.1"9tskKERNEL_VERSION_MAJOR 10:tskKERNEL_VERSION_MINOR 5;tskKERNEL_VERSION_BUILD 1?tskMPU_REGION_READ_ONLY ( 1UL << 0UL )@tskMPU_REGION_READ_WRITE ( 1UL << 1UL )AtskMPU_REGION_EXECUTE_NEVER ( 1UL << 2UL )BtskMPU_REGION_NORMAL_MEMORY ( 1UL << 3UL )CtskMPU_REGION_DEVICE_MEMORY ( 1UL << 4UL )JtskDEFAULT_INDEX_TO_NOTIFY ( 0 )ºtskIDLE_PRIORITY ( ( UBaseType_t ) 0U )ÄtaskYIELD() portYIELD()ÒtaskENTER_CRITICAL() portENTER_CRITICAL()ÓtaskENTER_CRITICAL_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR()átaskEXIT_CRITICAL() portEXIT_CRITICAL()âtaskEXIT_CRITICAL_FROM_ISR(x) portCLEAR_INTERRUPT_MASK_FROM_ISR( x )ìtaskDISABLE_INTERRUPTS() portDISABLE_INTERRUPTS()ötaskENABLE_INTERRUPTS() portENABLE_INTERRUPTS()ûtaskSCHEDULER_SUSPENDED ( ( BaseType_t ) 0 )ütaskSCHEDULER_NOT_STARTED ( ( BaseType_t ) 1 )ýtaskSCHEDULER_RUNNING ( ( BaseType_t ) 2 )ävTaskDelayUntil(pxPreviousWakeTime,xTimeIncrement) do { ( void ) xTaskDelayUntil( ( pxPreviousWakeTime ), ( xTimeIncrement ) ); } while( 0 )™xTaskNotify(xTaskToNotify,ulValue,eAction) xTaskGenericNotify( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), NULL )›xTaskNotifyIndexed(xTaskToNotify,uxIndexToNotify,ulValue,eAction) xTaskGenericNotify( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), NULL )¶xTaskNotifyAndQuery(xTaskToNotify,ulValue,eAction,pulPreviousNotifyValue) xTaskGenericNotify( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) )¸xTaskNotifyAndQueryIndexed(xTaskToNotify,uxIndexToNotify,ulValue,eAction,pulPreviousNotifyValue) xTaskGenericNotify( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) )²xTaskNotifyFromISR(xTaskToNotify,ulValue,eAction,pxHigherPriorityTaskWoken) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), NULL, ( pxHigherPriorityTaskWoken ) )´xTaskNotifyIndexedFromISR(xTaskToNotify,uxIndexToNotify,ulValue,eAction,pxHigherPriorityTaskWoken) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), NULL, ( pxHigherPriorityTaskWoken ) )ÏxTaskNotifyAndQueryIndexedFromISR(xTaskToNotify,uxIndexToNotify,ulValue,eAction,pulPreviousNotificationValue,pxHigherPriorityTaskWoken) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotificationValue ), ( pxHigherPriorityTaskWoken ) )ÑxTaskNotifyAndQueryFromISR(xTaskToNotify,ulValue,eAction,pulPreviousNotificationValue,pxHigherPriorityTaskWoken) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), ( pulPreviousNotificationValue ), ( pxHigherPriorityTaskWoken ) )ÁxTaskNotifyWait(ulBitsToClearOnEntry,ulBitsToClearOnExit,pulNotificationValue,xTicksToWait) xTaskGenericNotifyWait( tskDEFAULT_INDEX_TO_NOTIFY, ( ulBitsToClearOnEntry ), ( ulBitsToClearOnExit ), ( pulNotificationValue ), ( xTicksToWait ) )ÃxTaskNotifyWaitIndexed(uxIndexToWaitOn,ulBitsToClearOnEntry,ulBitsToClearOnExit,pulNotificationValue,xTicksToWait) xTaskGenericNotifyWait( ( uxIndexToWaitOn ), ( ulBitsToClearOnEntry ), ( ulBitsToClearOnExit ), ( pulNotificationValue ), ( xTicksToWait ) )ŽxTaskNotifyGive(xTaskToNotify) xTaskGenericNotify( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( 0 ), eIncrement, NULL )xTaskNotifyGiveIndexed(xTaskToNotify,uxIndexToNotify) xTaskGenericNotify( ( xTaskToNotify ), ( uxIndexToNotify ), ( 0 ), eIncrement, NULL )åvTaskNotifyGiveFromISR(xTaskToNotify,pxHigherPriorityTaskWoken) vTaskGenericNotifyGiveFromISR( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( pxHigherPriorityTaskWoken ) )çvTaskNotifyGiveIndexedFromISR(xTaskToNotify,uxIndexToNotify,pxHigherPriorityTaskWoken) vTaskGenericNotifyGiveFromISR( ( xTaskToNotify ), ( uxIndexToNotify ), ( pxHigherPriorityTaskWoken ) )ÏulTaskNotifyTake(xClearCountOnExit,xTicksToWait) ulTaskGenericNotifyTake( ( tskDEFAULT_INDEX_TO_NOTIFY ), ( xClearCountOnExit ), ( xTicksToWait ) )ÑulTaskNotifyTakeIndexed(uxIndexToWaitOn,xClearCountOnExit,xTicksToWait) ulTaskGenericNotifyTake( ( uxIndexToWaitOn ), ( xClearCountOnExit ), ( xTicksToWait ) )xTaskNotifyStateClear(xTask) xTaskGenericNotifyStateClear( ( xTask ), ( tskDEFAULT_INDEX_TO_NOTIFY ) )‘xTaskNotifyStateClearIndexed(xTask,uxIndexToClear) xTaskGenericNotifyStateClear( ( xTask ), ( uxIndexToClear ) )ÑulTaskNotifyValueClear(xTask,ulBitsToClear) ulTaskGenericNotifyValueClear( ( xTask ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulBitsToClear ) )ÓulTaskNotifyValueClearIndexed(xTask,uxIndexToClear,ulBitsToClear) ulTaskGenericNotifyValueClear( ( xTask ), ( uxIndexToClear ), ( ulBitsToClear ) )TH ..\..\..\..\os\freertos\include\task.hlist.hð


..\..\..\..\os\freertos\include\task.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xuvoidchar"Ü"åPTaskHandle_táW&PTaskHookFunction_tî]íeRunningeReadyeBlockedeSuspendedeDeletedeInvalidPeTaskState hâeNoActioneSetBitseIncrementeSetValueWithOverwriteeSetValueWithoutOverwritePeNotifyActionr)·xTIME_OUTxOverflowCount#xTimeOnEnteringB#PTimeOut_t÷{) xMEMORY_REGIONpvBaseAddressê#ulLengthInBytesY#ulParametersY#PMemoryRegion_tH…)ÜxTASK_PARAMETERS$pvTaskCodeî#pcName`#usStackDepthI#pvParametersê#uxPriority/#puxStackBufferd#Ë xRegionsB#â"\"PTaskParameters_t·–)ÞxTASK_STATUS$xHandleò#pcTaskName`#xTaskNumber/#eCurrentStatem#uxCurrentPriority/#uxBasePriority/#ulRunTimeCounterY#pxStackBased#usStackHighWaterMarkI# PTaskStatus_tƒ©³    eAbortSleepeStandardSleepeNoTasksWaitingTimeoutPeSleepModeStatuss³-tskTaskControlBlock"ÌNò    %ê%&'TIMERS_H '9tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR ( ( BaseType_t ) -2 ):tmrCOMMAND_EXECUTE_CALLBACK ( ( BaseType_t ) -1 );tmrCOMMAND_START_DONT_TRACE ( ( BaseType_t ) 0 )<tmrCOMMAND_START ( ( BaseType_t ) 1 )=tmrCOMMAND_RESET ( ( BaseType_t ) 2 )>tmrCOMMAND_STOP ( ( BaseType_t ) 3 )?tmrCOMMAND_CHANGE_PERIOD ( ( BaseType_t ) 4 )@tmrCOMMAND_DELETE ( ( BaseType_t ) 5 )BtmrFIRST_FROM_ISR_COMMAND ( ( BaseType_t ) 6 )CtmrCOMMAND_START_FROM_ISR ( ( BaseType_t ) 6 )DtmrCOMMAND_RESET_FROM_ISR ( ( BaseType_t ) 7 )EtmrCOMMAND_STOP_FROM_ISR ( ( BaseType_t ) 8 )FtmrCOMMAND_CHANGE_PERIOD_FROM_ISR ( ( BaseType_t ) 9 )ýxTimerStart(xTimer,xTicksToWait) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )¨xTimerStop(xTimer,xTicksToWait) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP, 0U, NULL, ( xTicksToWait ) )ùxTimerChangePeriod(xTimer,xNewPeriod,xTicksToWait) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD, ( xNewPeriod ), NULL, ( xTicksToWait ) ) xTimerDelete(xTimer,xTicksToWait) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_DELETE, 0U, NULL, ( xTicksToWait ) )xTimerReset(xTimer,xTicksToWait) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )ôxTimerStartFromISR(xTimer,pxHigherPriorityTaskWoken) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )´xTimerStopFromISR(xTimer,pxHigherPriorityTaskWoken) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP_FROM_ISR, 0, ( pxHigherPriorityTaskWoken ), 0U )þxTimerChangePeriodFromISR(xTimer,xNewPeriod,pxHigherPriorityTaskWoken) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD_FROM_ISR, ( xNewPeriod ), ( pxHigherPriorityTaskWoken ), 0U )ÕxTimerResetFromISR(xTimer,pxHigherPriorityTaskWoken) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )TJ ..\..\..\..\os\freertos\include\timers.htask.hh


..\..\..\..\os\freertos\include\timers.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107xuvoid"Þ"YPTimerHandle_tIP"PTimerCallbackFunction_tUUPPendedFunction_tè[-tmrTimerControl"8OÕ%ì"MOç%ä%Y)*+EVENT_GROUPS_H %©xEventGroupClearBitsFromISR(xEventGroup,uxBitsToClear) xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) ( xEventGroup ), ( uint32_t ) ( uxBitsToClear ), NULL )ÅxEventGroupSetBitsFromISR(xEventGroup,uxBitsToSet,pxHigherPriorityTaskWoken) xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) ( xEventGroup ), ( uint32_t ) ( uxBitsToSet ), ( pxHigherPriorityTaskWoken ) )ÛxEventGroupGetBits(xEventGroup) xEventGroupClearBits( ( xEventGroup ), 0 )\R ..\..\..\..\os\freertos\include\event_groups.htimers.h


..\..\..\..\os\freertos\include\event_groups.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x"WPEventGroupHandle_täS$PEventBits_tB]"-./0#MPU_WRAPPERS_INCLUDED_FROM_API_FILE &'()/MPU_WRAPPERS_INCLUDED_FROM_API_FILE:eventCLEAR_EVENTS_ON_EXIT_BIT 0x01000000UL;eventUNBLOCKED_DUE_TO_BIT_SET 0x02000000UL<eventWAIT_FOR_ALL_BITS 0x04000000UL=eventEVENT_BITS_CONTROL_BYTES 0xff000000ULôé ..\..\..\..\config\C:\Keil_v5\ARM\ARMCC\Bin\..\include\..\..\..\..\os\freertos\include\soc_config.hstdlib.hFreeRTOS.htask.htimers.hevent_groups.h..\..\..\..\os\freertos\event_groups.cÔ


..\..\..\..\os\freertos\event_groups.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\git-ble\BLE_PAN1070\01_SDK\nimble\samples\bluetooth\ble_central_periph_ota\keil_107x_Complex long_double_Complex double_Complex floatuvoid)º__va_list__ap:#"P__builtin_va_list)ŸEventGroupDef_tuxEventBits#xTasksWaitingForBits¤#PEventGroup_tWL"ŸŸ"ÃÇæ"Ϥ"ÙY8Ô• xEventGroupSetBits$êxEventGroup$·uxBitsToSeta__result\pxListItem \pxNext \pxListEndÕ\pxListß\uxBitsToClear\uxBitsWaitedFor\uxControlBits\pxEventBits³\xMatchFound8ßµprvTestWaitCondition$·uxCurrentEventBits$·uxBitsToWaitFor$½xWaitForAllBitsa__result\xWaitConditionMet8ÖÙ xEventGroupClearBits$êxEventGroup$·uxBitsToCleara__result\pxEventBits³\uxReturn>ØéxEventGroupSetBits_xEventGroupClearBits2!/!I$>%%%%    %C


%C%% %%%C%C&I(( 1111 I8     I  I8    4! I8     "I#7I$I%I&I    'I(I)*+,-./404142434445.:;9?I6.:;9?7.:;9G8.:;9?I 9.:;9? :.:;9G ;.:;9?I<.:;9?=.:;9G>.:;9?I@?.:;9?@@.:;9G@A.:;9?I@


B.:;9?@


C.:;9G@


D1E1F1XYWG1XYWH.1I.1@J.1@


K.1L.<4I?M.<4?NIOPI:;9QI4RSTUVW1X4I    ,Y4I    Z4I[4I,\4I]4I    4^4I    ,4_4I4`4I,4a4I4b41    ,c41d41,e41f1g1hI    iIjIkI    4lI    ,4mI4n1    o1p4I    ?q4I?<r4I,s4It5Iu;v=w%x<%Component: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed]armlink --partial --no_add_relocs_to_undefined --no_generate_mapping_symbols --diag_suppress=9931,9931,6642 --cpu=Cortex-M0 --fpu=SoftVFP --output=.\objects\event_groups.o --vfemode=force


Input Comments:p109ac-3Component: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]armasm --debug --diag_suppress=9931,9931,1602,1073 --cpu=Cortex-M0 --fpu=SoftVFP --apcs=/interwork/interwork --no_divide event_groups.oComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]ArmCC --c99 --split_sections --debug -c --gnu -o.\objects\event_groups.o --depend=.\objects\event_groups.d --cpu=Cortex-M0 --apcs=interwork -O3 -Otime --diag_suppress=9931 --preinclude=soc_config.h -I..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\cmsis\include -I..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\peripheral\inc -I..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\device\Include -I..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\radio\prf_lib\include -I..\..\..\..\..\modules\hal\panchip\panplat\pan1070\bsp\SEGGER_RTT\RTT -I..\..\..\..\os\freertos\include -I..\..\..\..\os\freertos\portable\RVDS\ARM_CM0 -I..\..\..\..\host\nimble\ext\tinycrypt\include -I..\..\..\..\host\nimble\nimble\include -I..\..\..\..\host\nimble\nimble\host\include -I..\..\..\..\host\nimble\nimble\host\util\include -I..\..\..\..\host\nimble\nimble\transport\include -I..\..\..\..\host\nimble\porting\nimble\include -I..\..\..\..\host\nimble\porting\npl\freertos\include -I..\..\..\..\host\nimble\nimble\host\services\gap\include -I..\..\..\..\host\nimble\nimble\host\services\gatt\include -I..\..\..\..\host\nimble\nimble\host\services\ans\include -I..\..\..\..\host\nimble\nimble\host\store\config\include -I..\..\..\..\host\nimble\ext\base64\include -I..\..\..\..\controller\pan107x_spark\include\utils -I..\..\..\..\controller\pan107x_spark\include -I..\..\..\..\host\kv_store -I.\configuration -I..\src -I..\..\..\..\config -I..\..\..\..\component\app_log -I..\..\..\..\soc -I..\..\..\..\utilities -I..\..\..\..\host -I..\..\..\..\component\kv_store -I..\..\..\..\component\ble_dev_filter -I..\..\..\..\host\smp_bt -I..\..\..\..\host\smp_bt\tinycbor\include -I..\..\..\..\host\smp_bt\mcumgr\cborattr\include -I..\..\..\..\host\smp_bt\mcumgr\img_mgmt\include -I..\..\..\..\host\smp_bt\mcumgr\util\include -I..\..\..\..\host -I..\..\..\..\host\smp_bt\mcumgr\mgmt\include -I..\..\..\..\host\smp_bt\mcumgr\smp\include -I.\RTE\_ble_central_periph -IC:\Keil_v5\ARM\PACK\ARM\CMSIS\5.7.0\Device\ARM\ARMCM0\Include -IC:\Keil_v5\ARM\CMSIS\Include -D__MICROLIB -D__UVISION_VERSION=530 -DARMCM0 -D_RTE_ -DIP_107x -DCONFIG_FLASH_LINE_MODE=FLASH_X4_MODE -DBLE_EN=1 -D__ORDER_LITTLE_ENDIAN__=2 -D__BYTE_ORDER__=2 --omf_browse=.\objects\event_groups.crf ..\..\..\..\os\freertos\event_groups.c>B>B>B>B>B>B>B>B>B    >B


>B2B3BñÿùAíA” ”DD AÆAñÿXAXA9AÇ@³@Ç@–@Ç@@Ç@k@Ç@O@Ç@:@    Ç@    (@


Ç@


@Ç@ø?Þ?Ä?ª??v?\?B?(??ø>ß>Æ>­>”> {>!b>"I>#0>$>%>&ç='Î=(µ=)œ=*ƒ=+j=,Q=-8=. =/=0ð<1Ø<2À<3¨<4<5x<6`<7E<8(<9<:î;;Ñ;<´;=—;>z;?a;A5;    ;Ï:2‘:M::½Í9f‰9jF9b9n¼8z8/88+þ7¼77‡B7ƒ7ÅÃ6‘„6¹G6Œ    6•Ì5þ‹5úJ5Í5ÛÆ4х4åD4ñ4àÀ3õ~3Ö=3éû2í¾2¡‚2µC2É2ÁÆ1©‰1™L11{Ì0¥Ž0Q0­0±Õ/–/X//EØ.I›.r_.Q#.Uè-Y¬-Mp-^*-vð,#´,'ƒ,L,,½æ+f¯+jy+bH+n    +Ô*/Ÿ*+r*=* *‡Ý)ƒ©)Åx)‘F)¹)Œå(•µ(þ(úM(Í(Ûã'ѯ'å{'ñG'à'õÜ&Ö¨&és&íC&¡&µâ%ɯ%Á%©O%™%ë${¹$¥ˆ$X$­'$±ö#Ä#“#`#E-#Iý"rÎ"QŸ"Uq"YB"M"^Ú!v­!#~!'@!ü ½ ¼| e8 iõa·mk


).ç*­k.†ñ‚°Är3¸ö‹¸”{ý:ùùÌ·ÚuÐ4äóð²ßoô-Õìèªìm 1´òȲÀu¨8˜û~ºz{¤=œ¬Â°„EÇD‡HJqPÒT—X[L]ÙuŸ"c&"Û™»UdhÈ`‡l8    ó-®)q,ì…¬hÃ'å·¥Šd“$üà øœ ËW Ù ÏÎãŠïFÞó»Ôwç2ëò


Ÿ³


³q


Ç.


¿î    §®    —n    }*    y裧›g«&¯å£ bCÜGœp]OSàW¡Kb\tÜ!%U0ΈGÜÒ¼áuö/×ðZ¦w;A µ@<˜@@$m@Q@<@t    *@š


@ΙeJ:'`˜‰t"ñÿ


[


\


a&


`0


c6


]


S


[


\


V


Z


W


 


Y


aZ


`l


c


b&


a0


SN


_R


cf


cl


^p


Xz


[Œ


\


b0


aR


cz


_~


cŠ


c


^”


Xž


[À


\ZÙÝá„ZÙÝá„8<8<0,4"0-4&0.4(0/4*004 014$024034044]ÔRØ?]Ô"Ø"Ü@ûgÿ""Ig,f]Ô&Ø&ÜAãfç&ë&ïJôføJýfJffJfJ f$J)f0f4J9f?fCJHfLJQf]Ô(Ø(ÜBùgý((KgK-f1KGfKK^ŠbKqggŸg±fµKËŠãŠ]Ô*Ø*ÜCýg**    LgL5f9LLfPLffjL}ŠLg§f«LºgÎgÒLꊊŠ*#*<f@LHfL*P*Yf]LbffLkfqfvffƒ*‡*f”L™fL¢f¨f­f]Ô Ø ÜDãfç ë ïMôføMýfMffMf]Ô$Ø$ÜEg$$N!g%N4gUŠYNkfoN~g]ÔØÜFúþOgO*f.OJfNO]ÔØÜG P*P<f@P]ÔØÜHQ,Q@fDQKfOS\f`QefiQnfsfwQ|fJ"J&J(J*J J$JJJ689;<=>]Ê7Îþ]Í8Ñÿ]‚=†]‚:†]‚;†]<…îf‘]‚>†]Õ]Ӑ.Ba|—¦·Òáò -GVv‘¿Ùè KixŒ«Æâñ (.CQYnt~‘­ÁÇÑäø] Ô]ý֐$2@NgˆŸ¸Ùðþ#1?MfŽ ·Ð:m ½í,b`28`Ln`–œ`°Õ``'`2\b`v™Ÿ³Éäü,O^©ÃÙà`#BH`\k¤³Ñ×ì]ƒ9‡]?


)L^y”©ÃÝó)?ZuŸ¼Ùï    #<Ul~˜ªÆâñ.Mh‚œ®Ìç)B`rŒž¸Ãîù"4Sf€“®ÁÔçú-CNg…™­ÃÙî-’ç    -    H    c    Š         ¸    Ð    è    





1


O


Ç


Ú


ë


 ;Vk…ŸµÐë7Oa~›±Ëåþ . @ Z l ˆ ¤ ¿ Ñ ï 


:L^w‰£µCUt† ³Îáô1Mc…ª¸Óñ/EZoz”]/ö]ý.õ]ýÝǐðHn`›ÆÔö]ýÜNs‹“`¼þ*8`m¬ß`î`#L}±åO`€`´`吐L`j~‘¤·Êáý.<”bvªÏäj]ýáWr‚¶É,`o]þß.=L[±Êãý/G_x‹¤¼Ïåö    8Si‚›¯Çàý?Rl†¢·Òåÿ,v„™¡`ŐӐ鐐"8Tbn„£±½Óû]þâ5Ÿ·à@r°);`ŒÃþ8r«ç"Z‘]ý-ôJy©ìKŽ³Öî$Z£é1|°ô6w¹ú5æ`T ® µ `⠐]þ1øt0Sl3Lš6l“õ`]ý(ï6t“¥¼Õö4@`mªÙ` `>Iq“«ó`-c‡`–¬`Î`ݐó`&`]ÿ0÷jƒÈá :Sƒ³Ì6¹Òò=ý    `¼


]ý,óאí`L¹Í;s­Üê3m©Úè/g¡ÐÞû%]—ÆÔñ    i    ¥    Ö    ä    


DXÃÿ<PzŽÀ]ý2ù]þ3ú§¶Úé]ü)ð"`2`XŠ`»`]ÿà&`f]ÿÒrx]+ò;v`°âí`R†¸çcy©`¹`à``B`x`¦¼ä`"O`ªÀæ`$L`vŒµ`ېñ`KU`]Þ?©`â``Qw¹ÝõD\†·Â`ߐ÷-]ÿ*ñ6La]吋’Àîõ")] ç°`u]%앐ΐ#3CM`SÄ    Ï    æ    -


`B


z]搆m¢m½mØmómm)mHmÁmÓsésþss(sZmw`t]#ê‚Ì‚Þ‚ó‚‚‚*‚@a`xssŸ¯Ê`А֐ܐx]!è0µ,e†`s´sŐ֐èò`øþ]&í‡+‡@Uk]'î;ˆPb]"預3H]$ë    7T…e…wˆ…œ…¬…¾Ò…,`F`£©¶ÏÚû'2y]ä]ýã]Ñ


ÕÑ됐_]Ø6Üý]æê×]ç5ëüO]ÜàÛ]Ø4Üû’d’Œ’µ’Ò’ú’"’D’}Œ]Ø    ÜÐ(Š‚ŠŠ7ŠSo“ÌŠ!Š<¶Š#ŠE‹W“’ΐ1Š]ÔØÚŠœŠÏŠ]Ô@ØŠ/Š‚˜Ù‹ý%ŠfŠÃŠóŠŠ%VéŠ]ÖAÚb]ÜàÙæfŠ]ÔØØyg—h¹g¿ŠÑhÛhågg7gIhVhƒg™g­gÏŠòŠAŠZŠ}g„g±gÑgf.ARM.attributes.strtab.shstrtab.rel.debug_pubnames.rel.debug_frame.rel.debug_line.rel.debug_info.reli.xEventGroupWaitBits.reli.xEventGroupSync.reli.xEventGroupSetBits.reli.xEventGroupGetBitsFromISR.reli.xEventGroupCreate.reli.xEventGroupClearBits.reli.vEventGroupSetBitsCallback.reli.vEventGroupDelete.reli.vEventGroupClearBitsCallback.symtab.comment.arm_vfe_header__ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000__ARM_grp.event_groups.c.2_C26000_Jba1$UA1z66_r10000__ARM_grp.event_groups.h.2_k63000_TdEctOuAgtd_J00000__ARM_grp.timers.h.2_oe2000_wnO$rrMTNBb_700000__ARM_grp.task.h.2_8M4000_m8$qSXJoTC3_s00000__ARM_grp.list.h.2_453000_aueleRUxrRd_e00000__ARM_grp.FreeRTOS.h.2_4q6000_mc10ekuiQGb_z00000__ARM_grp.portable.h.2_kT1000_9$fLUwUsNu6_k00000__ARM_grp.mpu_wrappers.h.2_Iv0000_129_FVqGho9_300000__ARM_grp.portmacro.h.2_cR1000_JvNw8oU4yb2_800000__ARM_grp.deprecated_definitions.h.2_su0000_ufaAXqJJZca_300000__ARM_grp.projdefs.h.2_cm1000__BkgC_ZRmk3_300000__ARM_grp.FreeRTOSConfig.h.2_r14000_zHr5zrkhjG5_h00000__ARM_grp.pan_hal.h.2_cN0000_86JB3mwhXe8_300000__ARM_grp.pan_hal_adc.h.2_4F0000_6PaqsBPRH65_300000__ARM_grp.pan_hal_timer.h.2_t7w100_DhOcBHl88k3_N10000__ARM_grp.pan_hal_pwm.h.2_MbM000_l2sztE5came_310000__ARM_grp.pan_hal_wwdt.h.2_cB1000_BPeA8RMRW_a_g00000__ARM_grp.pan_hal_wdt.h.2_sD1000_2EQcW4a5kB3_e00000__ARM_grp.pan_hal_i2c.h.2_4FL000_C_k7254tHId_A00000__ARM_grp.pan_hal_spi.h.2_R1x100_Jy62XOIodA3_h20000__ARM_grp.pan_hal_dmac.h.2_$9x100_mDhaCoLkf$8_n30000__ARM_grp.pan_hal_uart.h.2_Arv100_NzxGKekfUS5_P00000__ARM_grp.pan_hal_gpio.h.2_JOu100_2M7eFLS7sb8_r00000__ARM_grp.pan_hal_def.h.2_gt1000_uDZz$oGwdX9_e00000__ARM_grp.pan_power.h.2_Ah1000_CnF$gSCrCk1_a00000__ARM_grp.pan_clktrim.h.2_IiL000_0SW2dp5VPra_x00000__ARM_grp.pan_pri_rf.h.2_A9M000_ahqWxy1YfNa_P00000__ARM_grp.PanSeries.h.2_UQq100_PvSs5udcNm2_900000__ARM_grp.pan_efuse.h.2_AcL000_lL$RTVtmEw5_f00000__ARM_grp.pan_lp.h.2_8yL000_w1cp4ldqEA9_h00000__ARM_grp.pan_wwdt.h.2_Mr1000_jt_Pz5BAYP2_a00000__ARM_grp.pan_wdt.h.2_4J0000_qp6XZslpTn9_300000__ARM_grp.pan_pwm.h.2_MXL000_AgKnFS_UB_8_Z00000__ARM_grp.pan_timer.h.2_EKL000_6hboZRTp_$d_v00000__ARM_grp.pan_i2c.h.2_02N000_sRcSZuKs4W5_F00000__ARM_grp.pan_uart.h.2_g1M000_03FDMevg0X5_q00000__ARM_grp.pan_spi.h.2_EWL000_C5cFeo0knQ4_E00000__ARM_grp.pan_gpio.h.2_M3M000_Bh6KnacBBW9_x00000__ARM_grp.pan_dmac.h.2_YvM000_EA0$jHK3eM9_b10000__ARM_grp.pan_fmc.h.2_42v100_I8PQDuNa$l3_B00000__ARM_grp.pan_adc.h.2_8mz100_3yBpQ36S_0b_N60000__ARM_grp.pan_clk.h.2_UUN000_o44MvfxNnt9_m00000__ARM_grp.pan_sys.h.2_oM4000_5eG_0T959c4_300000__ARM_grp.pan_sys_log.h.2_UY0000_qyz3QMYnOqa_300000__ARM_grp.system_PanSeries.h.2_Ma5000__8TRzjzRXn5_f50000__ARM_grp.stdbool.h.2_Au0000_jr0apdtFqw4_300000__ARM_grp.core_cm0.h.2_ggO000_wS1Hrkokh70_k10000__ARM_grp.cmsis_compiler.h.2_Qx0000_LkcGzN6taw0_300000__ARM_grp.cmsis_armcc.h.2_Qa2000_iI$WZV5cdd9_R00000__ARM_grp.cmsis_version.h.2_0A0000_VRG$E9oAPMf_300000__ARM_grp.string.h.2_ww0000_Fb8stYXH4Ac_300000__ARM_grp.stdio.h.2_IE6000_CbKhhDu2Lbf_z10000__ARM_grp.stdint.h.2_8G1000_Y8yz6lqXnp2_300000__ARM_grp.stddef.h.2_cz0000_N3NQOejcnEf_300000__ARM_grp.stdlib.h.2_8U0000_v0hkGxVIVlb_300000__ARM_grp.soc_config.h.2_4A0000_GfUfcwBPsFc_300000__ARM_grp.sdk_config.h.2_0G2000_07odV7k0sg2_300000.debug_abbrev__ARM_asm.debug_abbrev.1.debug_macinfo.debug_loc.revsh_text.rev16_textBuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$EBA8$REQ8$PRES8$EABIv2Lib$$Request$$armlibxTaskResumeAllxTaskGetSchedulerStatevTaskSuspendAllvTaskRemoveFromUnorderedEventListvTaskPlaceOnUnorderedEventListvPortYieldvPortFreevPortExitCriticalvPortEnterCriticalvListInitialisevClearInterruptMaskFromISRuxTaskResetEventItemValueulSetInterruptMaskFromISRpvPortMalloc__ARM_grp..debug_pubnames$system_PanSeries.h$.2_Ma5000__8TRzjzRXn5_f50000__ARM_grp..debug_pubnames$stdio.h$.2_IE6000_CbKhhDu2Lbf_z10000__ARM_grp..debug_pubnames$pan_hal_uart.h$.2_Arv100_NzxGKekfUS5_P00000__ARM_grp..debug_pubnames$pan_hal_timer.h$.2_t7w100_DhOcBHl88k3_N10000__ARM_grp..debug_pubnames$pan_hal_spi.h$.2_R1x100_Jy62XOIodA3_h20000__ARM_grp..debug_pubnames$pan_hal_gpio.h$.2_JOu100_2M7eFLS7sb8_r00000__ARM_grp..debug_pubnames$pan_hal_dmac.h$.2_$9x100_mDhaCoLkf$8_n30000__ARM_grp..debug_pubnames$pan_fmc.h$.2_42v100_I8PQDuNa$l3_B00000__ARM_grp..debug_pubnames$pan_adc.h$.2_8mz100_3yBpQ36S_0b_N60000__ARM_grp..debug_pubnames$event_groups.c$.2_C26000_Jba1$UA1z66_r10000__ARM_grp..debug_pubnames$FreeRTOSConfig.h$.2_r14000_zHr5zrkhjG5_h00000__ARM_grp..debug_macinfo$timers.h$.2_oe2000_wnO$rrMTNBb_700000__ARM_grp..debug_macinfo$task.h$.2_8M4000_m8$qSXJoTC3_s00000__ARM_grp..debug_macinfo$system_PanSeries.h$.2_Ma5000__8TRzjzRXn5_f50000__ARM_grp..debug_macinfo$string.h$.2_ww0000_Fb8stYXH4Ac_300000__ARM_grp..debug_macinfo$stdlib.h$.2_8U0000_v0hkGxVIVlb_300000__ARM_grp..debug_macinfo$stdio.h$.2_IE6000_CbKhhDu2Lbf_z10000__ARM_grp..debug_macinfo$stdint.h$.2_8G1000_Y8yz6lqXnp2_300000__ARM_grp..debug_macinfo$stddef.h$.2_cz0000_N3NQOejcnEf_300000__ARM_grp..debug_macinfo$stdbool.h$.2_Au0000_jr0apdtFqw4_300000__ARM_grp..debug_macinfo$soc_config.h$.2_4A0000_GfUfcwBPsFc_300000__ARM_grp..debug_macinfo$sdk_config.h$.2_0G2000_07odV7k0sg2_300000__ARM_grp..debug_macinfo$projdefs.h$.2_cm1000__BkgC_ZRmk3_300000__ARM_grp..debug_macinfo$portmacro.h$.2_cR1000_JvNw8oU4yb2_800000__ARM_grp..debug_macinfo$portable.h$.2_kT1000_9$fLUwUsNu6_k00000__ARM_grp..debug_macinfo$pan_wwdt.h$.2_Mr1000_jt_Pz5BAYP2_a00000__ARM_grp..debug_macinfo$pan_wdt.h$.2_4J0000_qp6XZslpTn9_300000__ARM_grp..debug_macinfo$pan_uart.h$.2_g1M000_03FDMevg0X5_q00000__ARM_grp..debug_macinfo$pan_timer.h$.2_EKL000_6hboZRTp_$d_v00000__ARM_grp..debug_macinfo$pan_sys_log.h$.2_UY0000_qyz3QMYnOqa_300000__ARM_grp..debug_macinfo$pan_sys.h$.2_oM4000_5eG_0T959c4_300000__ARM_grp..debug_macinfo$pan_spi.h$.2_EWL000_C5cFeo0knQ4_E00000__ARM_grp..debug_macinfo$pan_pwm.h$.2_MXL000_AgKnFS_UB_8_Z00000__ARM_grp..debug_macinfo$pan_pri_rf.h$.2_A9M000_ahqWxy1YfNa_P00000__ARM_grp..debug_macinfo$pan_power.h$.2_Ah1000_CnF$gSCrCk1_a00000__ARM_grp..debug_macinfo$pan_lp.h$.2_8yL000_w1cp4ldqEA9_h00000__ARM_grp..debug_macinfo$pan_i2c.h$.2_02N000_sRcSZuKs4W5_F00000__ARM_grp..debug_macinfo$pan_hal_wwdt.h$.2_cB1000_BPeA8RMRW_a_g00000__ARM_grp..debug_macinfo$pan_hal_wdt.h$.2_sD1000_2EQcW4a5kB3_e00000__ARM_grp..debug_macinfo$pan_hal_uart.h$.2_Arv100_NzxGKekfUS5_P00000__ARM_grp..debug_macinfo$pan_hal_timer.h$.2_t7w100_DhOcBHl88k3_N10000__ARM_grp..debug_macinfo$pan_hal_spi.h$.2_R1x100_Jy62XOIodA3_h20000__ARM_grp..debug_macinfo$pan_hal_pwm.h$.2_MbM000_l2sztE5came_310000__ARM_grp..debug_macinfo$pan_hal_i2c.h$.2_4FL000_C_k7254tHId_A00000__ARM_grp..debug_macinfo$pan_hal_gpio.h$.2_JOu100_2M7eFLS7sb8_r00000__ARM_grp..debug_macinfo$pan_hal_dmac.h$.2_$9x100_mDhaCoLkf$8_n30000__ARM_grp..debug_macinfo$pan_hal_def.h$.2_gt1000_uDZz$oGwdX9_e00000__ARM_grp..debug_macinfo$pan_hal_adc.h$.2_4F0000_6PaqsBPRH65_300000__ARM_grp..debug_macinfo$pan_hal.h$.2_cN0000_86JB3mwhXe8_300000__ARM_grp..debug_macinfo$pan_gpio.h$.2_M3M000_Bh6KnacBBW9_x00000__ARM_grp..debug_macinfo$pan_fmc.h$.2_42v100_I8PQDuNa$l3_B00000__ARM_grp..debug_macinfo$pan_efuse.h$.2_AcL000_lL$RTVtmEw5_f00000__ARM_grp..debug_macinfo$pan_dmac.h$.2_YvM000_EA0$jHK3eM9_b10000__ARM_grp..debug_macinfo$pan_clktrim.h$.2_IiL000_0SW2dp5VPra_x00000__ARM_grp..debug_macinfo$pan_clk.h$.2_UUN000_o44MvfxNnt9_m00000__ARM_grp..debug_macinfo$pan_adc.h$.2_8mz100_3yBpQ36S_0b_N60000__ARM_grp..debug_macinfo$mpu_wrappers.h$.2_Iv0000_129_FVqGho9_300000__ARM_grp..debug_macinfo$list.h$.2_453000_aueleRUxrRd_e00000__ARM_grp..debug_macinfo$event_groups.h$.2_k63000_TdEctOuAgtd_J00000__ARM_grp..debug_macinfo$event_groups.c$.2_C26000_Jba1$UA1z66_r10000__ARM_grp..debug_macinfo$deprecated_definitions.h$.2_su0000_ufaAXqJJZca_300000__ARM_grp..debug_macinfo$core_cm0.h$.2_ggO000_wS1Hrkokh70_k10000__ARM_grp..debug_macinfo$cmsis_version.h$.2_0A0000_VRG$E9oAPMf_300000__ARM_grp..debug_macinfo$cmsis_compiler.h$.2_Qx0000_LkcGzN6taw0_300000__ARM_grp..debug_macinfo$cmsis_armcc.h$.2_Qa2000_iI$WZV5cdd9_R00000__ARM_grp..debug_macinfo$PanSeries.h$.2_UQq100_PvSs5udcNm2_900000__ARM_grp..debug_macinfo$FreeRTOSConfig.h$.2_r14000_zHr5zrkhjG5_h00000__ARM_grp..debug_macinfo$FreeRTOS.h$.2_4q6000_mc10ekuiQGb_z00000__ARM_grp..debug_line$timers.h$.2_oe2000_wnO$rrMTNBb_700000__ARM_grp..debug_line$task.h$.2_8M4000_m8$qSXJoTC3_s00000__ARM_grp..debug_line$system_PanSeries.h$.2_Ma5000__8TRzjzRXn5_f50000__ARM_grp..debug_line$string.h$.2_ww0000_Fb8stYXH4Ac_300000__ARM_grp..debug_line$stdlib.h$.2_8U0000_v0hkGxVIVlb_300000__ARM_grp..debug_line$stdio.h$.2_IE6000_CbKhhDu2Lbf_z10000__ARM_grp..debug_line$stdint.h$.2_8G1000_Y8yz6lqXnp2_300000__ARM_grp..debug_line$stddef.h$.2_cz0000_N3NQOejcnEf_300000__ARM_grp..debug_line$stdbool.h$.2_Au0000_jr0apdtFqw4_300000__ARM_grp..debug_line$soc_config.h$.2_4A0000_GfUfcwBPsFc_300000__ARM_grp..debug_line$sdk_config.h$.2_0G2000_07odV7k0sg2_300000__ARM_grp..debug_line$projdefs.h$.2_cm1000__BkgC_ZRmk3_300000__ARM_grp..debug_line$portmacro.h$.2_cR1000_JvNw8oU4yb2_800000__ARM_grp..debug_line$portable.h$.2_kT1000_9$fLUwUsNu6_k00000__ARM_grp..debug_line$pan_wwdt.h$.2_Mr1000_jt_Pz5BAYP2_a00000__ARM_grp..debug_line$pan_wdt.h$.2_4J0000_qp6XZslpTn9_300000__ARM_grp..debug_line$pan_uart.h$.2_g1M000_03FDMevg0X5_q00000__ARM_grp..debug_line$pan_timer.h$.2_EKL000_6hboZRTp_$d_v00000__ARM_grp..debug_line$pan_sys_log.h$.2_UY0000_qyz3QMYnOqa_300000__ARM_grp..debug_line$pan_sys.h$.2_oM4000_5eG_0T959c4_300000__ARM_grp..debug_line$pan_spi.h$.2_EWL000_C5cFeo0knQ4_E00000__ARM_grp..debug_line$pan_pwm.h$.2_MXL000_AgKnFS_UB_8_Z00000__ARM_grp..debug_line$pan_pri_rf.h$.2_A9M000_ahqWxy1YfNa_P00000__ARM_grp..debug_line$pan_power.h$.2_Ah1000_CnF$gSCrCk1_a00000__ARM_grp..debug_line$pan_lp.h$.2_8yL000_w1cp4ldqEA9_h00000__ARM_grp..debug_line$pan_i2c.h$.2_02N000_sRcSZuKs4W5_F00000__ARM_grp..debug_line$pan_hal_wwdt.h$.2_cB1000_BPeA8RMRW_a_g00000__ARM_grp..debug_line$pan_hal_wdt.h$.2_sD1000_2EQcW4a5kB3_e00000__ARM_grp..debug_line$pan_hal_uart.h$.2_Arv100_NzxGKekfUS5_P00000__ARM_grp..debug_line$pan_hal_timer.h$.2_t7w100_DhOcBHl88k3_N10000__ARM_grp..debug_line$pan_hal_spi.h$.2_R1x100_Jy62XOIodA3_h20000__ARM_grp..debug_line$pan_hal_pwm.h$.2_MbM000_l2sztE5came_310000__ARM_grp..debug_line$pan_hal_i2c.h$.2_4FL000_C_k7254tHId_A00000__ARM_grp..debug_line$pan_hal_gpio.h$.2_JOu100_2M7eFLS7sb8_r00000__ARM_grp..debug_line$pan_hal_dmac.h$.2_$9x100_mDhaCoLkf$8_n30000__ARM_grp..debug_line$pan_hal_def.h$.2_gt1000_uDZz$oGwdX9_e00000__ARM_grp..debug_line$pan_hal_adc.h$.2_4F0000_6PaqsBPRH65_300000__ARM_grp..debug_line$pan_hal.h$.2_cN0000_86JB3mwhXe8_300000__ARM_grp..debug_line$pan_gpio.h$.2_M3M000_Bh6KnacBBW9_x00000__ARM_grp..debug_line$pan_fmc.h$.2_42v100_I8PQDuNa$l3_B00000__ARM_grp..debug_line$pan_efuse.h$.2_AcL000_lL$RTVtmEw5_f00000__ARM_grp..debug_line$pan_dmac.h$.2_YvM000_EA0$jHK3eM9_b10000__ARM_grp..debug_line$pan_clktrim.h$.2_IiL000_0SW2dp5VPra_x00000__ARM_grp..debug_line$pan_clk.h$.2_UUN000_o44MvfxNnt9_m00000__ARM_grp..debug_line$pan_adc.h$.2_8mz100_3yBpQ36S_0b_N60000__ARM_grp..debug_line$mpu_wrappers.h$.2_Iv0000_129_FVqGho9_300000__ARM_grp..debug_line$list.h$.2_453000_aueleRUxrRd_e00000__ARM_grp..debug_line$event_groups.h$.2_k63000_TdEctOuAgtd_J00000__ARM_grp..debug_line$event_groups.c$.2_C26000_Jba1$UA1z66_r10000__ARM_grp..debug_line$deprecated_definitions.h$.2_su0000_ufaAXqJJZca_300000__ARM_grp..debug_line$core_cm0.h$.2_ggO000_wS1Hrkokh70_k10000__ARM_grp..debug_line$cmsis_version.h$.2_0A0000_VRG$E9oAPMf_300000__ARM_grp..debug_line$cmsis_compiler.h$.2_Qx0000_LkcGzN6taw0_300000__ARM_grp..debug_line$cmsis_armcc.h$.2_Qa2000_iI$WZV5cdd9_R00000__ARM_grp..debug_line$PanSeries.h$.2_UQq100_PvSs5udcNm2_900000__ARM_grp..debug_line$FreeRTOSConfig.h$.2_r14000_zHr5zrkhjG5_h00000__ARM_grp..debug_line$FreeRTOS.h$.2_4q6000_mc10ekuiQGb_z00000__ARM_grp.timers.h.2_oe2000_wnO$rrMTNBb_700000__ARM_grp.task.h.2_8M4000_m8$qSXJoTC3_s00000__ARM_grp.system_PanSeries.h.2_Ma5000__8TRzjzRXn5_f50000__ARM_grp.string.h.2_ww0000_Fb8stYXH4Ac_300000__ARM_grp.stdlib.h.2_8U0000_v0hkGxVIVlb_300000__ARM_grp.stdio.h.2_IE6000_CbKhhDu2Lbf_z10000__ARM_grp.stdint.h.2_8G1000_Y8yz6lqXnp2_300000__ARM_grp.stddef.h.2_cz0000_N3NQOejcnEf_300000__ARM_grp.stdbool.h.2_Au0000_jr0apdtFqw4_300000__ARM_grp.soc_config.h.2_4A0000_GfUfcwBPsFc_300000__ARM_grp.sdk_config.h.2_0G2000_07odV7k0sg2_300000__ARM_grp.projdefs.h.2_cm1000__BkgC_ZRmk3_300000__ARM_grp.portmacro.h.2_cR1000_JvNw8oU4yb2_800000__ARM_grp.portable.h.2_kT1000_9$fLUwUsNu6_k00000__ARM_grp.pan_wwdt.h.2_Mr1000_jt_Pz5BAYP2_a00000__ARM_grp.pan_wdt.h.2_4J0000_qp6XZslpTn9_300000__ARM_grp.pan_uart.h.2_g1M000_03FDMevg0X5_q00000__ARM_grp.pan_timer.h.2_EKL000_6hboZRTp_$d_v00000__ARM_grp.pan_sys_log.h.2_UY0000_qyz3QMYnOqa_300000__ARM_grp.pan_sys.h.2_oM4000_5eG_0T959c4_300000__ARM_grp.pan_spi.h.2_EWL000_C5cFeo0knQ4_E00000__ARM_grp.pan_pwm.h.2_MXL000_AgKnFS_UB_8_Z00000__ARM_grp.pan_pri_rf.h.2_A9M000_ahqWxy1YfNa_P00000__ARM_grp.pan_power.h.2_Ah1000_CnF$gSCrCk1_a00000__ARM_grp.pan_lp.h.2_8yL000_w1cp4ldqEA9_h00000__ARM_grp.pan_i2c.h.2_02N000_sRcSZuKs4W5_F00000__ARM_grp.pan_hal_wwdt.h.2_cB1000_BPeA8RMRW_a_g00000__ARM_grp.pan_hal_wdt.h.2_sD1000_2EQcW4a5kB3_e00000__ARM_grp.pan_hal_uart.h.2_Arv100_NzxGKekfUS5_P00000__ARM_grp.pan_hal_timer.h.2_t7w100_DhOcBHl88k3_N10000__ARM_grp.pan_hal_spi.h.2_R1x100_Jy62XOIodA3_h20000__ARM_grp.pan_hal_pwm.h.2_MbM000_l2sztE5came_310000__ARM_grp.pan_hal_i2c.h.2_4FL000_C_k7254tHId_A00000__ARM_grp.pan_hal_gpio.h.2_JOu100_2M7eFLS7sb8_r00000__ARM_grp.pan_hal_dmac.h.2_$9x100_mDhaCoLkf$8_n30000__ARM_grp.pan_hal_def.h.2_gt1000_uDZz$oGwdX9_e00000__ARM_grp.pan_hal_adc.h.2_4F0000_6PaqsBPRH65_300000__ARM_grp.pan_hal.h.2_cN0000_86JB3mwhXe8_300000__ARM_grp.pan_gpio.h.2_M3M000_Bh6KnacBBW9_x00000__ARM_grp.pan_fmc.h.2_42v100_I8PQDuNa$l3_B00000__ARM_grp.pan_efuse.h.2_AcL000_lL$RTVtmEw5_f00000__ARM_grp.pan_dmac.h.2_YvM000_EA0$jHK3eM9_b10000__ARM_grp.pan_clktrim.h.2_IiL000_0SW2dp5VPra_x00000__ARM_grp.pan_clk.h.2_UUN000_o44MvfxNnt9_m00000__ARM_grp.pan_adc.h.2_8mz100_3yBpQ36S_0b_N60000__ARM_grp.mpu_wrappers.h.2_Iv0000_129_FVqGho9_300000__ARM_grp.list.h.2_453000_aueleRUxrRd_e00000__ARM_grp.event_groups.h.2_k63000_TdEctOuAgtd_J00000__ARM_grp.event_groups.c.2_C26000_Jba1$UA1z66_r10000__ARM_grp.deprecated_definitions.h.2_su0000_ufaAXqJJZca_300000__ARM_grp.core_cm0.h.2_ggO000_wS1Hrkokh70_k10000__ARM_grp.cmsis_version.h.2_0A0000_VRG$E9oAPMf_300000__ARM_grp.cmsis_compiler.h.2_Qx0000_LkcGzN6taw0_300000__ARM_grp.cmsis_armcc.h.2_Qa2000_iI$WZV5cdd9_R00000__ARM_grp.PanSeries.h.2_UQq100_PvSs5udcNm2_900000__ARM_grp.FreeRTOSConfig.h.2_r14000_zHr5zrkhjG5_h00000__ARM_grp.FreeRTOS.h.2_4q6000_mc10ekuiQGb_z00000__ARM_grp..debug_info$timers.h$.2_oe2000_wnO$rrMTNBb_700000__ARM_grp..debug_info$task.h$.2_8M4000_m8$qSXJoTC3_s00000__ARM_grp..debug_info$system_PanSeries.h$.2_Ma5000__8TRzjzRXn5_f50000__ARM_grp..debug_info$string.h$.2_ww0000_Fb8stYXH4Ac_300000__ARM_grp..debug_info$stdlib.h$.2_8U0000_v0hkGxVIVlb_300000__ARM_grp..debug_info$stdio.h$.2_IE6000_CbKhhDu2Lbf_z10000__ARM_grp..debug_info$stdint.h$.2_8G1000_Y8yz6lqXnp2_300000__ARM_grp..debug_info$stddef.h$.2_cz0000_N3NQOejcnEf_300000__ARM_grp..debug_info$stdbool.h$.2_Au0000_jr0apdtFqw4_300000__ARM_grp..debug_info$soc_config.h$.2_4A0000_GfUfcwBPsFc_300000__ARM_grp..debug_info$sdk_config.h$.2_0G2000_07odV7k0sg2_300000__ARM_grp..debug_info$projdefs.h$.2_cm1000__BkgC_ZRmk3_300000__ARM_grp..debug_info$portmacro.h$.2_cR1000_JvNw8oU4yb2_800000__ARM_grp..debug_info$portable.h$.2_kT1000_9$fLUwUsNu6_k00000__ARM_grp..debug_info$pan_wwdt.h$.2_Mr1000_jt_Pz5BAYP2_a00000__ARM_grp..debug_info$pan_wdt.h$.2_4J0000_qp6XZslpTn9_300000__ARM_grp..debug_info$pan_uart.h$.2_g1M000_03FDMevg0X5_q00000__ARM_grp..debug_info$pan_timer.h$.2_EKL000_6hboZRTp_$d_v00000__ARM_grp..debug_info$pan_sys_log.h$.2_UY0000_qyz3QMYnOqa_300000__ARM_grp..debug_info$pan_sys.h$.2_oM4000_5eG_0T959c4_300000__ARM_grp..debug_info$pan_spi.h$.2_EWL000_C5cFeo0knQ4_E00000__ARM_grp..debug_info$pan_pwm.h$.2_MXL000_AgKnFS_UB_8_Z00000__ARM_grp..debug_info$pan_pri_rf.h$.2_A9M000_ahqWxy1YfNa_P00000__ARM_grp..debug_info$pan_power.h$.2_Ah1000_CnF$gSCrCk1_a00000__ARM_grp..debug_info$pan_lp.h$.2_8yL000_w1cp4ldqEA9_h00000__ARM_grp..debug_info$pan_i2c.h$.2_02N000_sRcSZuKs4W5_F00000__ARM_grp..debug_info$pan_hal_wwdt.h$.2_cB1000_BPeA8RMRW_a_g00000__ARM_grp..debug_info$pan_hal_wdt.h$.2_sD1000_2EQcW4a5kB3_e00000__ARM_grp..debug_info$pan_hal_uart.h$.2_Arv100_NzxGKekfUS5_P00000__ARM_grp..debug_info$pan_hal_timer.h$.2_t7w100_DhOcBHl88k3_N10000__ARM_grp..debug_info$pan_hal_spi.h$.2_R1x100_Jy62XOIodA3_h20000__ARM_grp..debug_info$pan_hal_pwm.h$.2_MbM000_l2sztE5came_310000__ARM_grp..debug_info$pan_hal_i2c.h$.2_4FL000_C_k7254tHId_A00000__ARM_grp..debug_info$pan_hal_gpio.h$.2_JOu100_2M7eFLS7sb8_r00000__ARM_grp..debug_info$pan_hal_dmac.h$.2_$9x100_mDhaCoLkf$8_n30000__ARM_grp..debug_info$pan_hal_def.h$.2_gt1000_uDZz$oGwdX9_e00000__ARM_grp..debug_info$pan_hal_adc.h$.2_4F0000_6PaqsBPRH65_300000__ARM_grp..debug_info$pan_hal.h$.2_cN0000_86JB3mwhXe8_300000__ARM_grp..debug_info$pan_gpio.h$.2_M3M000_Bh6KnacBBW9_x00000__ARM_grp..debug_info$pan_fmc.h$.2_42v100_I8PQDuNa$l3_B00000__ARM_grp..debug_info$pan_efuse.h$.2_AcL000_lL$RTVtmEw5_f00000__ARM_grp..debug_info$pan_dmac.h$.2_YvM000_EA0$jHK3eM9_b10000__ARM_grp..debug_info$pan_clktrim.h$.2_IiL000_0SW2dp5VPra_x00000__ARM_grp..debug_info$pan_clk.h$.2_UUN000_o44MvfxNnt9_m00000__ARM_grp..debug_info$pan_adc.h$.2_8mz100_3yBpQ36S_0b_N60000__ARM_grp..debug_info$mpu_wrappers.h$.2_Iv0000_129_FVqGho9_300000__ARM_grp..debug_info$list.h$.2_453000_aueleRUxrRd_e00000__ARM_grp..debug_info$event_groups.h$.2_k63000_TdEctOuAgtd_J00000__ARM_grp..debug_info$event_groups.c$.2_C26000_Jba1$UA1z66_r10000__ARM_grp..debug_info$deprecated_definitions.h$.2_su0000_ufaAXqJJZca_300000__ARM_grp..debug_info$core_cm0.h$.2_ggO000_wS1Hrkokh70_k10000__ARM_grp..debug_info$cmsis_version.h$.2_0A0000_VRG$E9oAPMf_300000__ARM_grp..debug_info$cmsis_compiler.h$.2_Qx0000_LkcGzN6taw0_300000__ARM_grp..debug_info$cmsis_armcc.h$.2_Qa2000_iI$WZV5cdd9_R00000__ARM_grp..debug_info$PanSeries.h$.2_UQq100_PvSs5udcNm2_900000__ARM_grp..debug_info$FreeRTOSConfig.h$.2_r14000_zHr5zrkhjG5_h00000__ARM_grp..debug_info$FreeRTOS.h$.2_4q6000_mc10ekuiQGb_z00000__ARM_grp..debug_abbrev.group.2_Am0000_lbphKItke$2_000000__asm___14_event_groups_c_5f98c4ce____REVSH__asm___14_event_groups_c_5f98c4ce____REV16__ARM_asm.debug_abbrev.1__ARM_grp_.debug_pubnames$66__ARM_grp_.debug_pubnames$59__ARM_grp_.debug_pubnames$52__ARM_grp_.debug_pubnames$45__ARM_grp_.debug_pubnames$31__ARM_grp_.debug_pubnames$24__ARM_grp_.debug_pubnames$10__ARM_grp_.debug_macinfo$4__ARM_grp_.debug_loc$68__ARM_grp_.debug_loc$61__ARM_grp_.debug_loc$54__ARM_grp_.debug_loc$47__ARM_grp_.debug_loc$40__ARM_grp_.debug_loc$33__ARM_grp_.debug_loc$26__ARM_grp_.debug_loc$19__ARM_grp_.debug_loc$12__ARM_grp_.debug_line$64__ARM_grp_.debug_line$57__ARM_grp_.debug_line$50__ARM_grp_.debug_line$43__ARM_grp_.debug_line$36__ARM_grp_.debug_line$29__ARM_grp_.debug_line$22__ARM_grp_.debug_line$15__ARM_grp_.debug_line$8__ARM_grp_.debug_line$1__ARM_grp_.debug_info$65__ARM_grp_.debug_info$58__ARM_grp_.debug_info$51__ARM_grp_.debug_info$44__ARM_grp_.debug_info$37__ARM_grp_.debug_info$30__ARM_grp_.debug_info$23__ARM_grp_.debug_info$16__ARM_grp_.debug_info$9__ARM_grp_.debug_info$2__ARM_grp_.debug_frame$69__ARM_grp_.debug_frame$62__ARM_grp_.debug_frame$55__ARM_grp_.debug_frame$48__ARM_grp_.debug_frame$41__ARM_grp_.debug_frame$34__ARM_grp_.debug_frame$27__ARM_grp_.debug_frame$20__ARM_grp_.debug_frame$13i.xEventGroupWaitBitsi.xEventGroupSynci.xEventGroupSetBitsi.xEventGroupGetBitsFromISRi.xEventGroupCreatei.xEventGroupClearBitsi.vEventGroupSetBitsCallbacki.vEventGroupDeleteBuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OTIME$EBA8$REQ8$PRES8$EABIv2i.vEventGroupClearBitsCallbackBuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$EBA8$PRES8$EABIv2..\..\..\..\os\freertos\event_groups.c.revsh_text.rev16_text..\\..\\..\\..\\os\\freertos\\event_groups.c$d.realdata$tAOaeabiCortex-M0        


C2.09ARM


> 42 8A< )\<˜í $Õĵޜðt†dšlþÎ\ÌLè”\|L˜”;,D;pD;´D;øL;DP;”P;äH;,D;pL;¼D;    H\H    à\(


8\`\\¼ì\¨¸\`$\„ˆ\X\dH\¬ˆL4LL€tLôèLÜLðlL\ŒLèpLX¬LdLh' ø ' Ü' ôü' ð ô' ä"|' `#\' ¼#p' ,$H' t$˜ %¨'´*('Ü*&'+*',+0'\+('„+1'µ+3ÿè+5Zñð+ ¾,5Å  ,ÀLà=D\$>Ô‹ø>5Æ ?ÜLä?h\L@Ø\$A5Ë 4A|L°CT\DÄ-ÈF5È ØF°LˆG`\èGþðH5É I˜L˜QT\ìQÐøT5Ê UHLTW\\°W¼'lYp¡ÜY5Ì ìYˆLtZ`\ÔZ¬k€[5œ [¬L<\|\¸\7Ä]5š Ô]”Lhcx\àcàh5› ðh$Li¼\ÐiÏ


àj5 ðjL€Ì\ԀôŸ


ȉ5Ç ؉dL<ŠT\Šf


 ‹5Í 4‹PL„Ž¼\@˜'Ø $2


ü 5½ ¡Lœ¤´\P¥


\¦5¼ l¦,"L˜Èt\É4Ò    @Ê5¤ PÊxLÈßt\<à¢    Hã5£ \ãLhët\Üëð'Ìô8r    õ5¨ õàLøøt\lù`'Ìû A    ìû5¦ üûPLLx\Ä    Ü5© ìÔLÀ¨\h¤à5» @L\t\Ðì ¯¼'5¿ Ì'Lä'x\\(Ü885¶ H8` L¨Et\F„M K5¾ °K0LàKx\XL\W5º lWœLXt\|X| íøe5À fL ft\”fˆ¼k5Á ,k8Ldkx\ÜkôÐo5· ào@L st\”sÌ[`u5§ pu˜Lvx\€v°)0x5™ @xôºL43ð\$6ÔöøU5¹ VL[Ô\Ü[hÂDc5¥ TcLlcx\äc8h5¸ ,hLHhˆ\Ðh€\Pj5¬ `j(Lˆj\”kL'àn5® ôn¼L°oŒ\<p'<u-òlu5³ €u€LvŒ\Œvx


'(½,5­ @„LāŒ\P‚€'Ѕç‰¸†5± ̆„LP‡Œ\܇'ø‹%U Œ5¯ 0ŒLLŒŒ\، !ø‘5´ ’L$’Œ\°’Ü쌔5µ œ” L¼”Œ\H•´¸ü–5° —¼LȗŒ\T˜€‚Ԛ5² 蚈Lp›Œ\ü›<'8 )Nd 5« t L Œ\¡Pl¤5ª |¤L„¥X\ܦèçĨ5˜ بLÜ°ð\̱'Ô²7¶³5Ä ³L8ºP\ˆºw˜»5ž ¨»$LÌ»`\,¼ðE½5à ,½¤LÐÁˆ\XÂX°Ã5¢ ÀÃ\LÄT\pÄèßXÅ5 hÅLL´Æ¼\pÇ”®Ê5— Ê°LÄæÐ\”çTèì5¡ øì4L,øL\xø$Tœú5Î ¬úäL X\è ô%Ü5Ï ìðLÜX\4lð 5  °L¸`\»4 5Ÿ H L\!ø\T"Ø',&Bp&5]ñx&¤q,h ,8`X7`­Z=    ¸M5%    ÈM 5    èM5é    ðM5Ñ    N5±    N5˜     N5    ‚    8NP5


h    ˆNP5X    ØN05H    O5 X    O05H    @O57    HO57    XO57    hO57    xO57    ˆO57    ˜O57    ¨O57    ¸O57    ÈO57    ØO57    èO5X    øO5X    PP5X    `Pà5X    @Q¸5X    øQ˜5X    S€5 X    T€5!X    Th5"X    øTP5#X    HU¨5$H    ðU5&H    øU5'H    V5(H    V5)H    V5*H    V5+H     V5,H    (V5-H    0V5.#    8V59#    @V5:#    HV5;#    PV5<#    XV5=#    `V5>#    hV5?X    pV5EX    ˆV5IX     V5MX    ¸V5QX    ÐV5UX    èV 5Y#    W5ZX    W5^X    (W5bX    @W5fX    ÐX5jX    èXX5nX    @[5rX    X[ 5v#    x`5wX    €`5{X    ˜`5X    °`h5ƒX    aX5‡#    pb5ˆX    xbH5Œ#    Àb5X    Èb5‘X    ØdÀ5•X    ˜eø5™X    fˆ5X    g5¡X    h°5¥X    Èh 5©X    hj5­X    €j85±X    ¸j@5µX    øj05¹X    (k05½X    XkP5ÁX    ¨lÀ5ÅX    hm85ÉX     mX5ÍX    øm 5Ñ#    n5ÒX     n€5Ö#     n5×X    ¨n¨5Û#    Po5ÜX    Xo¨5à#    p5áX    p€5åX    ˆp@5éX    Èp05íX    øp05ñX    (qÈ5õ#    ðq5öX    øq5úX    r5þX    (r(5#    Pr5X    Xr5X    pr5X    ˆr(5X    °r5X    Èrp5X    8s¨5X    às05X    tˆ5#X    ˜t 5'X    ¸t(5+X    àtÐ5/#    °u50¸uJ ƒABpCÅi