#ifndef SDK_CONFIG_H
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#define SDK_CONFIG_H
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//*** <<< Use Configuration Wizard in Context Menu >>> ***
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//******************************************************************************
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// <h> Application Config
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// </h> Application Config End
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//
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//******************************************************************************
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// <h> SoC Platform
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// <o> Chip Power Mode
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// <0=> LDO
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// <1=> DCDC
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#define CONFIG_SOC_DCDC_PAN1070 1
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// <o> System Clock
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// <48=> 48 MHz (DPLL)
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// <32=> 32 MHz (DPLL)
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// <i> System main frequency, Unit MHz
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#define CONFIG_SYSTEM_CLOCK 48
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// <o> APB1 Clock Divisor
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// <0=> No Divider
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// <2=> 2
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// <4=> 4
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// <6=> 6
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// <8=> 8
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// <10=> 10
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// <12=> 12
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// <14=> 14
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// <16=> 16
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// <i> Divisor of peripheral clocks on APB1, It can only be even numbers.
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#define CONFIG_APB1_CLOCK_DIVISOR 2
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// <o> APB2 Clock Divisor
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// <0=> No Divider
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// <2=> 2
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// <4=> 4
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// <6=> 6
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// <8=> 8
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// <10=> 10
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// <12=> 12
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// <14=> 14
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// <16=> 16
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// <i> Divisor of peripheral clocks on APB2, It can only be even numbers.
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#define CONFIG_APB2_CLOCK_DIVISOR 2
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// <o> 32K Low-Speed Clock Source
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// <0=> RCL (32000 Hz)
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// <1=> XTL (32768 Hz)
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// <2=> ACT32K (32000 Hz)
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// <i> Select a low-speed clock source
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#define CONFIG_LOW_SPEED_CLOCK_SRC 1
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// <q> Force Calib RCL Clock
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// <i> Force calibrate the 32K RCL clock at system init stage.
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// <i> NOTE this only take effect when the Low-Speed Clock Source is seleted to RCL.
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#define CONFIG_FORCE_CALIB_RCL_CLK 0
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// <q> Enable RAM Function
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// <i> Adding essential code to SRAM could improve running performance.
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#define CONFIG_RAM_FUNCTION 1
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// <q> Enable Flash LDO
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// <i> Enable the internal 1.8v flash LDO for flash power supply
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// <i> instead of the default flash power from SoC VBAT.
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#define CONFIG_FLASH_LDO_EN 1
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// <q> Remap Vector Table to SRAM
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#define CONFIG_VECTOR_REMAP_TO_RAM 1
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// <e> Enable Auto Power Optimization
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// <i> Several power configurations could be updated due to temperature change.
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#define CONFIG_AUTO_OPTIMIZE_POWER_PARAM 0
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// <o> Temperature Sample Interval (in Seconds)
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#define CONFIG_TEMP_SAMPLE_INTERVAL_S 300
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// <q> Enable DVDD Voltage Optimization
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#define CONFIG_DVDD_VOL_OPTIMIZE_EN 1
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// </e>
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// </h> Soc Platform End
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//
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//******************************************************************************
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// <h> Power Management
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// <q> Enable Low Power Mode
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#define CONFIG_PM 0
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// <q> Enable System Watchdog
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#define CONFIG_SYSTEM_WATCH_DOG_ENABLE 0
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// <q> Keep Flash Power in Low Power Mode
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// <i> Select this means flash power would be retained in Low Power Mode, and
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// <i> there would be a little avg-current increase (about 1uA). The benefit is that
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// <i> the large peak current (>15mA) would not occur.
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#define CONFIG_KEEP_FLASH_POWER_IN_LP_MODE 1
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// <q> Enable DeepSleep Mode 2
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// <i> Enable DeepSleep Mode 2 (Only LPLDOH in use), and the HW APB Timer Wakeup
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// <i> and PWM waveform output can be use in this mode.
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#define CONFIG_DEEPSLEEP_MODE_2 0
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// <o> Increase LPLDOH trim value
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// <0=> +0
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// <1=> +1
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// <2=> +2
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// <3=> +3
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// <4=> +4
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// <5=> +5
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// <6=> +6
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// <7=> +7
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// <8=> +8
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// <i> Increase LPLDOH voltage for specific LowPower scenario use.
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#define CONFIG_SOC_INCREASE_LPLDOH_CALIB_CODE 0
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// <q> Continue Run After Standby M1 Wakeup
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// <i> Check this configuration to let CPU continue run after standby M1 waking up,
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// <i> or CPU would reset after waking up from standby M1.
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#define CONFIG_PM_STANDBY_M1_WAKEUP_WITHOUT_RESET 0
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// <q> Enable AHB Clock Optimization
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#define CONFIG_HCLK_OPTIMIZE_EN 0
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// </h> Power Management End
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//
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//******************************************************************************
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// <h> RTOS Config
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// <q> OS Enable
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#define CONFIG_OS_EN 1
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// <o> The Maximun Numble of OS Task
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#define configMAX_PRIORITIES 8
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// <o> OS Total Heap Size(in byte)
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#define configTOTAL_HEAP_SIZE 11000
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// <o> OS Main Thread Stack Size(in word)
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#define CONFIG_MAIN_TASK_STACK_SIZE 400
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// <o> OS Main Thread Priority
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#define CONFIG_MAIN_TASK_PRIO 3
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// <o> OS BLE Host Thread Stack Size(in word)
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#define CONFIG_BLE_HOST_THREAD_STACK_SIZE 400
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// <o> OS BLE Host Thread Priority
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#define CONFIG_BLE_HOST_THREAD_PRIO 6
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// <q> OS Timer Task Enable
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#define configUSE_TIMERS 1
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// <o> OS Timer Task Stack Size(in word)
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#define configTIMER_TASK_STACK_DEPTH 128
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// <o> OS Timer Task Priority
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#define configTIMER_TASK_PRIORITY 2
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// <o> The Maximun Number of OS Timer Queue Length
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#define configTIMER_QUEUE_LENGTH 12
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// <q> Enable OS Idle Hook
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#define configUSE_IDLE_HOOK 0
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// <q> Enable OS Tick Hook
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#define configUSE_TICK_HOOK 0
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// <q> Enable OS Malloc Fail Hook
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#define configUSE_MALLOC_FAILED_HOOK 1
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// <o> Enable OS Stack OverFlow Hook
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// <0=>Disable <1=>Mode1 <2=>Mode2
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#define configCHECK_FOR_STACK_OVERFLOW 0
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// <q> OS Log: Print Current Heap Usage
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#define CONFIG_FREERTOS_HEAP_PRINT 0
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// </h> RTOS Config End
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//
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//******************************************************************************
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// <h> BLE Resource Config
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// <q> Use Chip unique Mac Address
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#define CONFIG_USER_CHIP_MAC_ADDR 1
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// <o> RF TX power
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// <0=> 0dBm
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// <1=> 1dBm
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// <2=> 2dBm
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// <3=> 3dBm
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// <4=> 4dBm
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// <5=> 5dBm
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// <6=> 6dBm
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// <7=> 7dBm
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// <8=> 8dBm
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// <9=> 9dBm
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#define CONFIG_BT_CTLR_TX_POWER_DFT 0
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// <o> Support Maximun Number of BLE Master Link
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#define CONFIG_BT_MAX_NUM_OF_CENTRAL 1
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// <o> Support Maximun Number of BLE Slave Link
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#define CONFIG_BT_MAX_NUM_OF_PERIPHERAL 1
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// <q> Support GAP Broadcaster Role
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#define MYNEWT_VAL_BLE_ROLE_BROADCASTER 1
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// <q> Support GAP Central Role
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#define MYNEWT_VAL_BLE_ROLE_CENTRAL 1
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// <q> Support GAP Observser Role
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#define MYNEWT_VAL_BLE_ROLE_OBSERVER 1
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// <q> Support GAP Peripheral Role
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#define MYNEWT_VAL_BLE_ROLE_PERIPHERAL 1
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// <o> BLE Host Max ATT MTU Size
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#define MYNEWT_VAL_BLE_ATT_PREFERRED_MTU 247
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// <o> BLE Host HCI Rx ACL buffer counts
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#define MYNEWT_VAL_BLE_TRANSPORT_ACL_FROM_LL_COUNT 8
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// <o> BLE Host HCI Rx ACL buffer size
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#define MYNEWT_VAL_BLE_TRANSPORT_ACL_SIZE 251
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// <o> BLE Host HCI events counts
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#define MYNEWT_VAL_BLE_TRANSPORT_EVT_COUNT 8
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// <o> BLE Host HCI discardable events counts
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#define MYNEWT_VAL_BLE_TRANSPORT_EVT_DISCARDABLE_COUNT 6
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// <o> BLE Host L2CAP buffer counts
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#define MYNEWT_VAL_MSYS_1_BLOCK_COUNT 4
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// <o> BLE Host L2CAP buffer size
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#define MYNEWT_VAL_MSYS_1_BLOCK_SIZE 120
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// <o> BLE Controller RF RX Buffer Number (must be a power of 2)
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#define CONFIG_BLE_CONTROLLER_RF_RX_BUF_NUM 8
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// <o> BLE Controller RF TX Buffer Number (must be a power of 2)
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#define CONFIG_BLE_CONTROLLER_RF_TX_BUF_NUM 4
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// <o> BLE Controller Packet Encrypt Time (unit:us)
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#define CONFIG_BLE_CONTROLLER_LL_ENC_TIME 300
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// <o> BLE Controller More Data Number
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#define CONFIG_BLE_CONTROLLER_MORE_DATA_NUM 6
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// <o> BLE Controller WhiteList Number
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#define CONFIG_BLE_CONTROLLER_WIHTELIST_NUM 1
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// <o> BLE Controller Resolving List Number
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#define CONFIG_BLE_CONTROLLER_RESOLVELIST_NUM 0
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// <o> BLE Controller Master Link Margin (unit:0.625ms)
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#define CONFIG_BLE_CONTROLLER_MASTER_LINK_MARGIN 10
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// <o> BLE LL IRQ Priority
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// <0=>Highest <1=>High <2=>Low <3=>Lowest
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#define CONFIG_BLE_LL_IRQ_PRIO 0
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// <o> BLE Event Handler IRQ Priority
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// <0=>Highest <1=>High <2=>Low <3=>Lowest
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#define CONFIG_BLE_EVT_HANDLER_IRQ_PRIO 1
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// </h> BLE Resource End
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//
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//******************************************************************************
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// <h> BLE Security Manager
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// <o> Select Security Level
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#define MYNEWT_VAL_BLE_SM_SC_LVL 2
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// <q> Enable SM Legacy Pair
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#define MYNEWT_VAL_BLE_SM_LEGACY 1
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// <q> Enable SM Security Pair
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#define MYNEWT_VAL_BLE_SM_SC 0
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// <o> Select IO Capability
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// <0=> DisplayOnly
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// <1=> DisplayYesN
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// <2=> KeyboardOnly
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// <3=> NoInputNoOutput
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// <4=> KeyboardDisplay Only
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#define CONFIG_HS_IO_CAPABILITY 3
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// <q> Enable SM Bonding
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#define MYNEWT_VAL_BLE_SM_BONDING 0
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// <q> Enable SM MITM
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#define MYNEWT_VAL_BLE_SM_MITM 0
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// <q> Enable SM OOB
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#define MYNEWT_VAL_BLE_SM_OOB_DATA_FLAG 0
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// <o> Set Local Distribute Key
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// <0=> None
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// <1=> LTK
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// <3=> LTK and IRK
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// <7=> LTK and IRK and CSRK
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#define MYNEWT_VAL_BLE_SM_OUR_KEY_DIST 1
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// <o> Set Peer Distribute Key
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// <0=> None
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// <1=> LTK
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// <3=> LTK and IRK
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// <7=> LTK and IRK and CSRK
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#define MYNEWT_VAL_BLE_SM_THEIR_KEY_DIST 1
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// <q> Enable SM Info Persist Store
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#define MYNEWT_VAL_BLE_STORE_CONFIG_PERSIST 1
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// <o> Set Maximun Store Bonded Devices Number
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#define MYNEWT_VAL_BLE_STORE_MAX_BONDS 2
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// <o> Set Maximun Store Bonded Device CCCD Number
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#define MYNEWT_VAL_BLE_STORE_MAX_CCCDS 8
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// <q> Enable BLE Host RPA Resovling Function
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#define MYNEWT_VAL_HOST_SOFTWARE_RPA 1
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// </h> BLE Security Manager End
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//
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//******************************************************************************
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// <h> BLE Services Config
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// </h> BLE Services Config End
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//
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//******************************************************************************
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// <h> Flash & Image Config
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// <o> Chip Flash Size
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// <0x7F000=> 508 KB
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// <0x3F000=> 252 KB
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// <i> You can select chip flash size in the pull-down list, but modify the list only when you know what you are doing!
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#define CONFIG_FLASH_SIZE 0x7F000
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// <h> Flash Partition Config
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// <o> Bootloader Flash Partition Address
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// <0x00000=> 0x00000 (Fixed)
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// <i> Start address of bootloader (when use), do not modify this value in any case!
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#define CONFIG_FLASH_PARTITION_BOOTLOADER_ADDR 0x00000
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// <o> Bootloader Flash Partition Size
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// <0x00000=> 0x00000 (0 KB)
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// <0x0A000=> 0x0A000 (40 KB)
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#define CONFIG_FLASH_PARTITION_BOOTLOADER_SIZE 0x0A000
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// <o> App Flash Partition Address
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// <0x00000=> 0x00000 (No Bootloader)
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// <0x0A000=> 0x0A000 (Need Bootloader)
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#define CONFIG_FLASH_PARTITION_APP_ADDR 0x0A000
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// <o> App Flash Partition Size
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// <0x78000=> 0x78000 (480 KB)
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// <0x37000=> 0x37000 (220 KB)
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#define CONFIG_FLASH_PARTITION_APP_SIZE 0x37000
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// <o> App Backup Flash Partition Address
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// <0x00000=> 0x00000
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// <0x41000=> 0x41000
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#define CONFIG_FLASH_PARTITION_APP_BACKUP_ADDR 0x41000
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// <o> App Backup Flash Partition Size
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// <0x00000=> 0x00000 (0 KB)
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// <0x37000=> 0x37000 (220 KB)
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#define CONFIG_FLASH_PARTITION_APP_BACKUP_SIZE 0x37000
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// <o> KVStore Flash Partition Address
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// <0x78000=> 0x78000
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#define CONFIG_FLASH_PARTITION_KVSTORE_ADDR 0x78000
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// <o> KVStore Flash Partition Size
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// <0x04000=> 0x04000 (16 KB)
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// <0x07000=> 0x07000 (28 KB)
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#define CONFIG_FLASH_PARTITION_KVSTORE_SIZE 0x04000
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// <o> User Custom Flash Partition Address
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// <0x7C000=> 0x7C000
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// <0x00000=> 0x00000
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#define CONFIG_FLASH_PARTITION_USER_CUSTOM_ADDR 0x7C000
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// <o> User Custom Flash Partition Size
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// <0x03000=> 0x03000 (12 KB)
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// <0x00000=> 0x00000 (0 KB)
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#define CONFIG_FLASH_PARTITION_USER_CUSTOM_SIZE 0x03000
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// Check if flash partition configs value are valid
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#if CONFIG_FLASH_PARTITION_BOOTLOADER_SIZE % 0x1000
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#error "Bootloader Partition size should be multiple of 0x1000 (4KB)!"
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#endif
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#if CONFIG_FLASH_PARTITION_APP_SIZE % 0x1000
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#error "App Partition size should be multiple of 0x1000 (4KB)!"
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#endif
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#if CONFIG_FLASH_PARTITION_APP_BACKUP_SIZE % 0x1000
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#error "App Backup Partition size should be multiple of 0x1000 (4KB)!"
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#endif
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#if CONFIG_FLASH_PARTITION_KVSTORE_SIZE % 0x1000
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#error "KVStore Partition size should be multiple of 0x1000 (4KB)!"
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#endif
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#if CONFIG_FLASH_PARTITION_USER_CUSTOM_SIZE % 0x1000
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#error "User Custom Partition size should be multiple of 0x1000 (4KB)!"
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#endif
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#if CONFIG_FLASH_PARTITION_APP_SIZE == 0
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#error "App Partition size should not be 0!"
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#endif
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#if (CONFIG_FLASH_PARTITION_APP_ADDR != CONFIG_FLASH_PARTITION_BOOTLOADER_ADDR + CONFIG_FLASH_PARTITION_BOOTLOADER_SIZE)
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#error "Bootloader Partition overlaps the App Partition!"
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#endif
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#if CONFIG_FLASH_PARTITION_APP_BACKUP_SIZE > 0
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#if (CONFIG_FLASH_PARTITION_APP_BACKUP_ADDR != CONFIG_FLASH_PARTITION_APP_ADDR + CONFIG_FLASH_PARTITION_APP_SIZE)
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#error "App Partition overlaps the App Backup Partition!"
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#endif
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#endif
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#if CONFIG_FLASH_PARTITION_KVSTORE_SIZE > 0
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#if (CONFIG_FLASH_PARTITION_KVSTORE_ADDR != CONFIG_FLASH_PARTITION_APP_ADDR + CONFIG_FLASH_PARTITION_APP_SIZE + CONFIG_FLASH_PARTITION_APP_BACKUP_SIZE)
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#error "App or App Backup Partition overlaps the KVStore Partition!"
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#endif
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#endif
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#if CONFIG_FLASH_PARTITION_USER_CUSTOM_SIZE > 0
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#if (CONFIG_FLASH_PARTITION_USER_CUSTOM_ADDR != CONFIG_FLASH_PARTITION_APP_ADDR + CONFIG_FLASH_PARTITION_APP_SIZE + CONFIG_FLASH_PARTITION_APP_BACKUP_SIZE + CONFIG_FLASH_PARTITION_KVSTORE_SIZE)
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#error " KVStore Partition overlaps the User Custom Partition!"
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#endif
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#endif
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#if (CONFIG_FLASH_PARTITION_BOOTLOADER_SIZE + CONFIG_FLASH_PARTITION_APP_SIZE + CONFIG_FLASH_PARTITION_APP_BACKUP_SIZE + CONFIG_FLASH_PARTITION_KVSTORE_SIZE + CONFIG_FLASH_PARTITION_USER_CUSTOM_SIZE > CONFIG_FLASH_SIZE)
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#error "The size of all flash partitions excceeds the total flash size!"
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#endif
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// </h> Flash Partition Config End
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// <e> Enable App Image Header
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// <i> App Image header should only be enabled when there is a bootloader to boot App Image.
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#define CONFIG_APP_USE_IMAGE_HEADER 1
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#if CONFIG_APP_USE_IMAGE_HEADER
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// <o> App Image Version - Major <0-255>
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#define CONFIG_APP_IMG_VER_MAJOR 0
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// <o> App Image Version - Minor <0-255>
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#define CONFIG_APP_IMG_VER_MINOR 0
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// <o> App Image Version - Revision <0-65535>
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#define CONFIG_APP_IMG_VER_REVISION 1
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// <o> App Image Version - Build Num <0x0-0xFFFFFFFF>
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#define CONFIG_APP_IMG_VER_BUILD 0
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#endif
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// Check valid config condition
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#if (!CONFIG_FLASH_PARTITION_APP_ADDR) && CONFIG_APP_USE_IMAGE_HEADER
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#error "Image header should not be enabled when bootloader is not used!"
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#endif
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// </e>
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// <e> Enable Firmware Encryption
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// <i> Generate AES encrypted firmware at build stage for SoC with secure enabled.
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// <i> Should be consistent with encrypt_info.yaml
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#define CONFIG_FIRMWARE_ENCRYPTION 0
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#if CONFIG_FIRMWARE_ENCRYPTION
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// <o> Encrypt Flash Offset
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// <i> Flash offset index to indicate which page should be encrypted.
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// <i> Should be consistent with encrypt_info.yaml file!
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#define CONFIG_ENCRYPT_FLASH_OFFSET 0x001
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#endif /* CONFIG_FIRMWARE_ENCRYPTION */
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// </e>
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// </h> Flash & Image Config End
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//
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//******************************************************************************
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// <h> Log & Debug Config
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// <e> Enable App Log
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#define APP_LOG_EN 1
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// <o> Log Level Select
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// <4=> APP_LOG_LVL_DEBUG
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// <3=> APP_LOG_LVL_INFO
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// <2=> APP_LOG_LVL_WRN
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// <1=> APP_LOG_LVL_ERR
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// <0=> APP_LOG_LVL_NONE
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#define APP_LOG_LVL 4
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// <q> Log Level Output Enable
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#define APP_LOG_LVL_OUTPUT_EN 1
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// <q> Log Trace Output Enable
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#define APP_LOG_TRACE_OUTPUT_EN 0
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// <e> Log to UART
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#define CONFIG_UART_LOG_ENABLE 1
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// <o> Log UART Tx Pin
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// <0=> P05 (UART0)
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// <1=> P11 (UART0)
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// <2=> P16 (UART0)
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// <3=> P01 (UART1)
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// <4=> P10 (UART1)
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// <5=> P12 (UART1)
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// <6=> P25 (UART1)
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// <7=> P31 (UART1)
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// <i> Select a UART Tx pin for logging output.
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#define CONFIG_LOG_UART_PIN 2
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// <o> Log UART Baudrate
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// <115200=> 115200
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// <230400=> 230400
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// <460800=> 460800
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// <921600=> 921600
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// <1000000=> 1M
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// <2000000=> 2M
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#define CONFIG_LOG_UART_BAUDRATE 921600
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// </e> Enable UART Log End
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// <e> Log to RTT
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// <i> Note that the Low Power Mode (CONFIG_PM) should be disabled
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// <i> while using RTT log, since the Jlink SWD connnection would be lost
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// <i> at SoC DeepSleep or Standby Mode.
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#define CONFIG_RTT_LOG_ENABLE 0
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// <o> RTT Log Buffer Size (Bytes)
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// <i> Configure Log RTT Up Buffer Size in Bytes (Channel 0).
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#define CONFIG_LOG_RTT_UP_BUFFER_SIZE 512
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// </e> Enable RTT Log End
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// </e> App Log Enable End
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// <e> Enable IO Timing Track
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#define CONFIG_IO_TIMING_TRACK 0
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// <q> (Internal) Enable BLE Controller Timing Track
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// <i> This config is used to enable timing track of BLE controller internal signals and events.
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// <i> Do NOT enable this config if you are not sure how it actually work!
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// <i> - Some fixed pins are used for RF debugging: P04 / P07 / P10.
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// <i> - Some configurable pins are used for BLE events, see app_track.c for current pin config.
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#define CONFIG_BT_CTLR_LINK_LAYER_DEBUG 0
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// <o> DeepSleep Mode Track Pin
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// <0x99=> None
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// <0x00=> P00 (SWD_CLK)
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// <0x01=> P01 (SWD_DAT)
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// <0x02=> P02
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// <0x03=> P03
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// <0x04=> P04
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// <0x05=> P05
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// <0x06=> P06
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// <0x07=> P07
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// <0x10=> P10
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// <0x11=> P11
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// <0x12=> P12
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// <0x13=> P13
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// <0x14=> P14
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// <0x15=> P15
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// <0x16=> P16
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// <0x17=> P17
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// <0x20=> P20 (XTL1)
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// <0x21=> P21 (XTL0)
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// <0x22=> P22
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// <0x23=> P23
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// <0x24=> P24
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// <0x25=> P25
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// <0x26=> P26
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// <0x27=> P27
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// <0x30=> P30
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// <0x31=> P31
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// <i> Select a GPIO pin for DeepSleep Mode Timing Track.
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#define CONFIG_TRACK_PIN_DEEPSLEEP_MODE 0x22
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// <o> Sleep Mode Track Pin
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// <0x99=> None
|
// <0x00=> P00 (SWD_CLK)
|
// <0x01=> P01 (SWD_DAT)
|
// <0x02=> P02
|
// <0x03=> P03
|
// <0x04=> P04
|
// <0x05=> P05
|
// <0x06=> P06
|
// <0x07=> P07
|
// <0x10=> P10
|
// <0x11=> P11
|
// <0x12=> P12
|
// <0x13=> P13
|
// <0x14=> P14
|
// <0x15=> P15
|
// <0x16=> P16
|
// <0x17=> P17
|
// <0x20=> P20 (XTL1)
|
// <0x21=> P21 (XTL0)
|
// <0x22=> P22
|
// <0x23=> P23
|
// <0x24=> P24
|
// <0x25=> P25
|
// <0x26=> P26
|
// <0x27=> P27
|
// <0x30=> P30
|
// <0x31=> P31
|
// <i> Select a GPIO pin for Sleep Mode Timing Track.
|
#define CONFIG_TRACK_PIN_SLEEP_MODE 0x23
|
|
// <o> LinkLayer IRQ Track Pin
|
// <0x99=> None
|
// <0x00=> P00 (SWD_CLK)
|
// <0x01=> P01 (SWD_DAT)
|
// <0x02=> P02
|
// <0x03=> P03
|
// <0x04=> P04
|
// <0x05=> P05
|
// <0x06=> P06
|
// <0x07=> P07
|
// <0x10=> P10
|
// <0x11=> P11
|
// <0x12=> P12
|
// <0x13=> P13
|
// <0x14=> P14
|
// <0x15=> P15
|
// <0x16=> P16
|
// <0x17=> P17
|
// <0x20=> P20 (XTL1)
|
// <0x21=> P21 (XTL0)
|
// <0x22=> P22
|
// <0x23=> P23
|
// <0x24=> P24
|
// <0x25=> P25
|
// <0x26=> P26
|
// <0x27=> P27
|
// <0x30=> P30
|
// <0x31=> P31
|
// <i> Select a GPIO pin for BLE-LinkLayer / 2.4G-RF IRQ Timing Track.
|
#define CONFIG_TRACK_PIN_LL_IRQ 0x99
|
|
// <o> BLE Event IRQ Track Pin
|
// <0x99=> None
|
// <0x00=> P00 (SWD_CLK)
|
// <0x01=> P01 (SWD_DAT)
|
// <0x02=> P02
|
// <0x03=> P03
|
// <0x04=> P04
|
// <0x05=> P05
|
// <0x06=> P06
|
// <0x07=> P07
|
// <0x10=> P10
|
// <0x11=> P11
|
// <0x12=> P12
|
// <0x13=> P13
|
// <0x14=> P14
|
// <0x15=> P15
|
// <0x16=> P16
|
// <0x17=> P17
|
// <0x20=> P20 (XTL1)
|
// <0x21=> P21 (XTL0)
|
// <0x22=> P22
|
// <0x23=> P23
|
// <0x24=> P24
|
// <0x25=> P25
|
// <0x26=> P26
|
// <0x27=> P27
|
// <0x30=> P30
|
// <0x31=> P31
|
// <i> Select a GPIO pin for BLE Event IRQ Timing Track.
|
// <i> Currently this IRQ is borrowed from an unused peripheral (e.g. ADC).
|
#define CONFIG_TRACK_PIN_BLE_EVNT_IRQ 0x99
|
|
// <o> OS Tick IRQ Track Pin
|
// <0x99=> None
|
// <0x00=> P00 (SWD_CLK)
|
// <0x01=> P01 (SWD_DAT)
|
// <0x02=> P02
|
// <0x03=> P03
|
// <0x04=> P04
|
// <0x05=> P05
|
// <0x06=> P06
|
// <0x07=> P07
|
// <0x10=> P10
|
// <0x11=> P11
|
// <0x12=> P12
|
// <0x13=> P13
|
// <0x14=> P14
|
// <0x15=> P15
|
// <0x16=> P16
|
// <0x17=> P17
|
// <0x20=> P20 (XTL1)
|
// <0x21=> P21 (XTL0)
|
// <0x22=> P22
|
// <0x23=> P23
|
// <0x24=> P24
|
// <0x25=> P25
|
// <0x26=> P26
|
// <0x27=> P27
|
// <0x30=> P30
|
// <0x31=> P31
|
// <i> Select a GPIO pin for OS Tick IRQ Timing Track.
|
#define CONFIG_TRACK_PIN_OS_TICK_IRQ 0x99
|
|
// <o> SleepTimer IRQ Track Pin
|
// <0x99=> None
|
// <0x00=> P00 (SWD_CLK)
|
// <0x01=> P01 (SWD_DAT)
|
// <0x02=> P02
|
// <0x03=> P03
|
// <0x04=> P04
|
// <0x05=> P05
|
// <0x06=> P06
|
// <0x07=> P07
|
// <0x10=> P10
|
// <0x11=> P11
|
// <0x12=> P12
|
// <0x13=> P13
|
// <0x14=> P14
|
// <0x15=> P15
|
// <0x16=> P16
|
// <0x17=> P17
|
// <0x20=> P20 (XTL1)
|
// <0x21=> P21 (XTL0)
|
// <0x22=> P22
|
// <0x23=> P23
|
// <0x24=> P24
|
// <0x25=> P25
|
// <0x26=> P26
|
// <0x27=> P27
|
// <0x30=> P30
|
// <0x31=> P31
|
// <i> Select a GPIO pin for SleepTimer IRQ Timing Track.
|
#define CONFIG_TRACK_PIN_SLPTMR_IRQ 0x99
|
|
// <o> Hardfault IRQ Track Pin
|
// <0x99=> None
|
// <0x00=> P00 (SWD_CLK)
|
// <0x01=> P01 (SWD_DAT)
|
// <0x02=> P02
|
// <0x03=> P03
|
// <0x04=> P04
|
// <0x05=> P05
|
// <0x06=> P06
|
// <0x07=> P07
|
// <0x10=> P10
|
// <0x11=> P11
|
// <0x12=> P12
|
// <0x13=> P13
|
// <0x14=> P14
|
// <0x15=> P15
|
// <0x16=> P16
|
// <0x17=> P17
|
// <0x20=> P20 (XTL1)
|
// <0x21=> P21 (XTL0)
|
// <0x22=> P22
|
// <0x23=> P23
|
// <0x24=> P24
|
// <0x25=> P25
|
// <0x26=> P26
|
// <0x27=> P27
|
// <0x30=> P30
|
// <0x31=> P31
|
// <i> Select a GPIO pin for Hardfault IRQ Timing Track.
|
#define CONFIG_TRACK_PIN_HARDFAULT_IRQ 0x99
|
|
// <o> HAL DMA IRQ Track Pin
|
// <0x99=> None
|
// <0x00=> P00 (SWD_CLK)
|
// <0x01=> P01 (SWD_DAT)
|
// <0x02=> P02
|
// <0x03=> P03
|
// <0x04=> P04
|
// <0x05=> P05
|
// <0x06=> P06
|
// <0x07=> P07
|
// <0x10=> P10
|
// <0x11=> P11
|
// <0x12=> P12
|
// <0x13=> P13
|
// <0x14=> P14
|
// <0x15=> P15
|
// <0x16=> P16
|
// <0x17=> P17
|
// <0x20=> P20 (XTL1)
|
// <0x21=> P21 (XTL0)
|
// <0x22=> P22
|
// <0x23=> P23
|
// <0x24=> P24
|
// <0x25=> P25
|
// <0x26=> P26
|
// <0x27=> P27
|
// <0x30=> P30
|
// <0x31=> P31
|
// <i> Select a GPIO pin for DMA IRQ Timing Track.
|
#define CONFIG_TRACK_PIN_DMA_IRQ 0x99
|
|
// <o> HAL GPIO P0 IRQ Track Pin
|
// <0x99=> None
|
// <0x00=> P00 (SWD_CLK)
|
// <0x01=> P01 (SWD_DAT)
|
// <0x02=> P02
|
// <0x03=> P03
|
// <0x04=> P04
|
// <0x05=> P05
|
// <0x06=> P06
|
// <0x07=> P07
|
// <0x10=> P10
|
// <0x11=> P11
|
// <0x12=> P12
|
// <0x13=> P13
|
// <0x14=> P14
|
// <0x15=> P15
|
// <0x16=> P16
|
// <0x17=> P17
|
// <0x20=> P20 (XTL1)
|
// <0x21=> P21 (XTL0)
|
// <0x22=> P22
|
// <0x23=> P23
|
// <0x24=> P24
|
// <0x25=> P25
|
// <0x26=> P26
|
// <0x27=> P27
|
// <0x30=> P30
|
// <0x31=> P31
|
// <i> Select a GPIO pin for GPIO Port0 IRQ Timing Track.
|
#define CONFIG_TRACK_PIN_GPIO0_IRQ 0x99
|
|
// <o> HAL GPIO P1 IRQ Track Pin
|
// <0x99=> None
|
// <0x00=> P00 (SWD_CLK)
|
// <0x01=> P01 (SWD_DAT)
|
// <0x02=> P02
|
// <0x03=> P03
|
// <0x04=> P04
|
// <0x05=> P05
|
// <0x06=> P06
|
// <0x07=> P07
|
// <0x10=> P10
|
// <0x11=> P11
|
// <0x12=> P12
|
// <0x13=> P13
|
// <0x14=> P14
|
// <0x15=> P15
|
// <0x16=> P16
|
// <0x17=> P17
|
// <0x20=> P20 (XTL1)
|
// <0x21=> P21 (XTL0)
|
// <0x22=> P22
|
// <0x23=> P23
|
// <0x24=> P24
|
// <0x25=> P25
|
// <0x26=> P26
|
// <0x27=> P27
|
// <0x30=> P30
|
// <0x31=> P31
|
// <i> Select a GPIO pin for GPIO Port1 IRQ Timing Track.
|
#define CONFIG_TRACK_PIN_GPIO1_IRQ 0x99
|
|
// <o> HAL GPIO P2 IRQ Track Pin
|
// <0x99=> None
|
// <0x00=> P00 (SWD_CLK)
|
// <0x01=> P01 (SWD_DAT)
|
// <0x02=> P02
|
// <0x03=> P03
|
// <0x04=> P04
|
// <0x05=> P05
|
// <0x06=> P06
|
// <0x07=> P07
|
// <0x10=> P10
|
// <0x11=> P11
|
// <0x12=> P12
|
// <0x13=> P13
|
// <0x14=> P14
|
// <0x15=> P15
|
// <0x16=> P16
|
// <0x17=> P17
|
// <0x20=> P20 (XTL1)
|
// <0x21=> P21 (XTL0)
|
// <0x22=> P22
|
// <0x23=> P23
|
// <0x24=> P24
|
// <0x25=> P25
|
// <0x26=> P26
|
// <0x27=> P27
|
// <0x30=> P30
|
// <0x31=> P31
|
// <i> Select a GPIO pin for GPIO Port2 IRQ Timing Track.
|
#define CONFIG_TRACK_PIN_GPIO2_IRQ 0x99
|
|
// <o> HAL GPIO P3 IRQ Track Pin
|
// <0x99=> None
|
// <0x00=> P00 (SWD_CLK)
|
// <0x01=> P01 (SWD_DAT)
|
// <0x02=> P02
|
// <0x03=> P03
|
// <0x04=> P04
|
// <0x05=> P05
|
// <0x06=> P06
|
// <0x07=> P07
|
// <0x10=> P10
|
// <0x11=> P11
|
// <0x12=> P12
|
// <0x13=> P13
|
// <0x14=> P14
|
// <0x15=> P15
|
// <0x16=> P16
|
// <0x17=> P17
|
// <0x20=> P20 (XTL1)
|
// <0x21=> P21 (XTL0)
|
// <0x22=> P22
|
// <0x23=> P23
|
// <0x24=> P24
|
// <0x25=> P25
|
// <0x26=> P26
|
// <0x27=> P27
|
// <0x30=> P30
|
// <0x31=> P31
|
// <i> Select a GPIO pin for GPIO Port3 IRQ Timing Track.
|
#define CONFIG_TRACK_PIN_GPIO3_IRQ 0x99
|
|
// <o> HAL I2C IRQ Track Pin
|
// <0x99=> None
|
// <0x00=> P00 (SWD_CLK)
|
// <0x01=> P01 (SWD_DAT)
|
// <0x02=> P02
|
// <0x03=> P03
|
// <0x04=> P04
|
// <0x05=> P05
|
// <0x06=> P06
|
// <0x07=> P07
|
// <0x10=> P10
|
// <0x11=> P11
|
// <0x12=> P12
|
// <0x13=> P13
|
// <0x14=> P14
|
// <0x15=> P15
|
// <0x16=> P16
|
// <0x17=> P17
|
// <0x20=> P20 (XTL1)
|
// <0x21=> P21 (XTL0)
|
// <0x22=> P22
|
// <0x23=> P23
|
// <0x24=> P24
|
// <0x25=> P25
|
// <0x26=> P26
|
// <0x27=> P27
|
// <0x30=> P30
|
// <0x31=> P31
|
// <i> Select a GPIO pin for I2C IRQ Timing Track.
|
#define CONFIG_TRACK_PIN_I2C_IRQ 0x99
|
|
// <o> HAL SPI0 IRQ Track Pin
|
// <0x99=> None
|
// <0x00=> P00 (SWD_CLK)
|
// <0x01=> P01 (SWD_DAT)
|
// <0x02=> P02
|
// <0x03=> P03
|
// <0x04=> P04
|
// <0x05=> P05
|
// <0x06=> P06
|
// <0x07=> P07
|
// <0x10=> P10
|
// <0x11=> P11
|
// <0x12=> P12
|
// <0x13=> P13
|
// <0x14=> P14
|
// <0x15=> P15
|
// <0x16=> P16
|
// <0x17=> P17
|
// <0x20=> P20 (XTL1)
|
// <0x21=> P21 (XTL0)
|
// <0x22=> P22
|
// <0x23=> P23
|
// <0x24=> P24
|
// <0x25=> P25
|
// <0x26=> P26
|
// <0x27=> P27
|
// <0x30=> P30
|
// <0x31=> P31
|
// <i> Select a GPIO pin for SPI0 IRQ Timing Track.
|
#define CONFIG_TRACK_PIN_SPI0_IRQ 0x99
|
|
// <o> HAL SPI1 IRQ Track Pin
|
// <0x99=> None
|
// <0x00=> P00 (SWD_CLK)
|
// <0x01=> P01 (SWD_DAT)
|
// <0x02=> P02
|
// <0x03=> P03
|
// <0x04=> P04
|
// <0x05=> P05
|
// <0x06=> P06
|
// <0x07=> P07
|
// <0x10=> P10
|
// <0x11=> P11
|
// <0x12=> P12
|
// <0x13=> P13
|
// <0x14=> P14
|
// <0x15=> P15
|
// <0x16=> P16
|
// <0x17=> P17
|
// <0x20=> P20 (XTL1)
|
// <0x21=> P21 (XTL0)
|
// <0x22=> P22
|
// <0x23=> P23
|
// <0x24=> P24
|
// <0x25=> P25
|
// <0x26=> P26
|
// <0x27=> P27
|
// <0x30=> P30
|
// <0x31=> P31
|
// <i> Select a GPIO pin for SPI1 IRQ Timing Track.
|
#define CONFIG_TRACK_PIN_SPI1_IRQ 0x99
|
|
// <o> HAL TMR0 IRQ Track Pin
|
// <0x99=> None
|
// <0x00=> P00 (SWD_CLK)
|
// <0x01=> P01 (SWD_DAT)
|
// <0x02=> P02
|
// <0x03=> P03
|
// <0x04=> P04
|
// <0x05=> P05
|
// <0x06=> P06
|
// <0x07=> P07
|
// <0x10=> P10
|
// <0x11=> P11
|
// <0x12=> P12
|
// <0x13=> P13
|
// <0x14=> P14
|
// <0x15=> P15
|
// <0x16=> P16
|
// <0x17=> P17
|
// <0x20=> P20 (XTL1)
|
// <0x21=> P21 (XTL0)
|
// <0x22=> P22
|
// <0x23=> P23
|
// <0x24=> P24
|
// <0x25=> P25
|
// <0x26=> P26
|
// <0x27=> P27
|
// <0x30=> P30
|
// <0x31=> P31
|
// <i> Select a GPIO pin for TMR0 IRQ Timing Track.
|
#define CONFIG_TRACK_PIN_TMR0_IRQ 0x99
|
|
// <o> HAL TMR1 IRQ Track Pin
|
// <0x99=> None
|
// <0x00=> P00 (SWD_CLK)
|
// <0x01=> P01 (SWD_DAT)
|
// <0x02=> P02
|
// <0x03=> P03
|
// <0x04=> P04
|
// <0x05=> P05
|
// <0x06=> P06
|
// <0x07=> P07
|
// <0x10=> P10
|
// <0x11=> P11
|
// <0x12=> P12
|
// <0x13=> P13
|
// <0x14=> P14
|
// <0x15=> P15
|
// <0x16=> P16
|
// <0x17=> P17
|
// <0x20=> P20 (XTL1)
|
// <0x21=> P21 (XTL0)
|
// <0x22=> P22
|
// <0x23=> P23
|
// <0x24=> P24
|
// <0x25=> P25
|
// <0x26=> P26
|
// <0x27=> P27
|
// <0x30=> P30
|
// <0x31=> P31
|
// <i> Select a GPIO pin for TMR1 IRQ Timing Track.
|
#define CONFIG_TRACK_PIN_TMR1_IRQ 0x99
|
|
// <o> HAL TMR2 IRQ Track Pin
|
// <0x99=> None
|
// <0x00=> P00 (SWD_CLK)
|
// <0x01=> P01 (SWD_DAT)
|
// <0x02=> P02
|
// <0x03=> P03
|
// <0x04=> P04
|
// <0x05=> P05
|
// <0x06=> P06
|
// <0x07=> P07
|
// <0x10=> P10
|
// <0x11=> P11
|
// <0x12=> P12
|
// <0x13=> P13
|
// <0x14=> P14
|
// <0x15=> P15
|
// <0x16=> P16
|
// <0x17=> P17
|
// <0x20=> P20 (XTL1)
|
// <0x21=> P21 (XTL0)
|
// <0x22=> P22
|
// <0x23=> P23
|
// <0x24=> P24
|
// <0x25=> P25
|
// <0x26=> P26
|
// <0x27=> P27
|
// <0x30=> P30
|
// <0x31=> P31
|
// <i> Select a GPIO pin for TMR2 IRQ Timing Track.
|
#define CONFIG_TRACK_PIN_TMR2_IRQ 0x99
|
|
// <o> HAL UART0 IRQ Track Pin
|
// <0x99=> None
|
// <0x00=> P00 (SWD_CLK)
|
// <0x01=> P01 (SWD_DAT)
|
// <0x02=> P02
|
// <0x03=> P03
|
// <0x04=> P04
|
// <0x05=> P05
|
// <0x06=> P06
|
// <0x07=> P07
|
// <0x10=> P10
|
// <0x11=> P11
|
// <0x12=> P12
|
// <0x13=> P13
|
// <0x14=> P14
|
// <0x15=> P15
|
// <0x16=> P16
|
// <0x17=> P17
|
// <0x20=> P20 (XTL1)
|
// <0x21=> P21 (XTL0)
|
// <0x22=> P22
|
// <0x23=> P23
|
// <0x24=> P24
|
// <0x25=> P25
|
// <0x26=> P26
|
// <0x27=> P27
|
// <0x30=> P30
|
// <0x31=> P31
|
// <i> Select a GPIO pin for UART0 IRQ Timing Track.
|
#define CONFIG_TRACK_PIN_UART0_IRQ 0x99
|
|
// <o> HAL UART1 IRQ Track Pin
|
// <0x99=> None
|
// <0x00=> P00 (SWD_CLK)
|
// <0x01=> P01 (SWD_DAT)
|
// <0x02=> P02
|
// <0x03=> P03
|
// <0x04=> P04
|
// <0x05=> P05
|
// <0x06=> P06
|
// <0x07=> P07
|
// <0x10=> P10
|
// <0x11=> P11
|
// <0x12=> P12
|
// <0x13=> P13
|
// <0x14=> P14
|
// <0x15=> P15
|
// <0x16=> P16
|
// <0x17=> P17
|
// <0x20=> P20 (XTL1)
|
// <0x21=> P21 (XTL0)
|
// <0x22=> P22
|
// <0x23=> P23
|
// <0x24=> P24
|
// <0x25=> P25
|
// <0x26=> P26
|
// <0x27=> P27
|
// <0x30=> P30
|
// <0x31=> P31
|
// <i> Select a GPIO pin for UART1 IRQ Timing Track.
|
#define CONFIG_TRACK_PIN_UART1_IRQ 0x99
|
|
// <o> HAL WDT IRQ Track Pin
|
// <0x99=> None
|
// <0x00=> P00 (SWD_CLK)
|
// <0x01=> P01 (SWD_DAT)
|
// <0x02=> P02
|
// <0x03=> P03
|
// <0x04=> P04
|
// <0x05=> P05
|
// <0x06=> P06
|
// <0x07=> P07
|
// <0x10=> P10
|
// <0x11=> P11
|
// <0x12=> P12
|
// <0x13=> P13
|
// <0x14=> P14
|
// <0x15=> P15
|
// <0x16=> P16
|
// <0x17=> P17
|
// <0x20=> P20 (XTL1)
|
// <0x21=> P21 (XTL0)
|
// <0x22=> P22
|
// <0x23=> P23
|
// <0x24=> P24
|
// <0x25=> P25
|
// <0x26=> P26
|
// <0x27=> P27
|
// <0x30=> P30
|
// <0x31=> P31
|
// <i> Select a GPIO pin for WDT IRQ Timing Track.
|
#define CONFIG_TRACK_PIN_WDT_IRQ 0x99
|
|
// <o> HAL WWDT IRQ Track Pin
|
// <0x99=> None
|
// <0x00=> P00 (SWD_CLK)
|
// <0x01=> P01 (SWD_DAT)
|
// <0x02=> P02
|
// <0x03=> P03
|
// <0x04=> P04
|
// <0x05=> P05
|
// <0x06=> P06
|
// <0x07=> P07
|
// <0x10=> P10
|
// <0x11=> P11
|
// <0x12=> P12
|
// <0x13=> P13
|
// <0x14=> P14
|
// <0x15=> P15
|
// <0x16=> P16
|
// <0x17=> P17
|
// <0x20=> P20 (XTL1)
|
// <0x21=> P21 (XTL0)
|
// <0x22=> P22
|
// <0x23=> P23
|
// <0x24=> P24
|
// <0x25=> P25
|
// <0x26=> P26
|
// <0x27=> P27
|
// <0x30=> P30
|
// <0x31=> P31
|
// <i> Select a GPIO pin for WWDT IRQ Timing Track.
|
#define CONFIG_TRACK_PIN_WWDT_IRQ 0x99
|
|
// <o> User App Channel 0 Track Pin
|
// <0x99=> None
|
// <0x00=> P00 (SWD_CLK)
|
// <0x01=> P01 (SWD_DAT)
|
// <0x02=> P02
|
// <0x03=> P03
|
// <0x04=> P04
|
// <0x05=> P05
|
// <0x06=> P06
|
// <0x07=> P07
|
// <0x10=> P10
|
// <0x11=> P11
|
// <0x12=> P12
|
// <0x13=> P13
|
// <0x14=> P14
|
// <0x15=> P15
|
// <0x16=> P16
|
// <0x17=> P17
|
// <0x20=> P20 (XTL1)
|
// <0x21=> P21 (XTL0)
|
// <0x22=> P22
|
// <0x23=> P23
|
// <0x24=> P24
|
// <0x25=> P25
|
// <0x26=> P26
|
// <0x27=> P27
|
// <0x30=> P30
|
// <0x31=> P31
|
// <i> Select a GPIO pin for User App Timing Track Channel 0.
|
#define CONFIG_TRACK_USER_APP_CHN0 0x99
|
|
// <o> User App Channel 1 Track Pin
|
// <0x99=> None
|
// <0x00=> P00 (SWD_CLK)
|
// <0x01=> P01 (SWD_DAT)
|
// <0x02=> P02
|
// <0x03=> P03
|
// <0x04=> P04
|
// <0x05=> P05
|
// <0x06=> P06
|
// <0x07=> P07
|
// <0x10=> P10
|
// <0x11=> P11
|
// <0x12=> P12
|
// <0x13=> P13
|
// <0x14=> P14
|
// <0x15=> P15
|
// <0x16=> P16
|
// <0x17=> P17
|
// <0x20=> P20 (XTL1)
|
// <0x21=> P21 (XTL0)
|
// <0x22=> P22
|
// <0x23=> P23
|
// <0x24=> P24
|
// <0x25=> P25
|
// <0x26=> P26
|
// <0x27=> P27
|
// <0x30=> P30
|
// <0x31=> P31
|
// <i> Select a GPIO pin for User App Timing Track Channel 1.
|
#define CONFIG_TRACK_USER_APP_CHN1 0x99
|
|
// <o> User App Channel 2 Track Pin
|
// <0x99=> None
|
// <0x00=> P00 (SWD_CLK)
|
// <0x01=> P01 (SWD_DAT)
|
// <0x02=> P02
|
// <0x03=> P03
|
// <0x04=> P04
|
// <0x05=> P05
|
// <0x06=> P06
|
// <0x07=> P07
|
// <0x10=> P10
|
// <0x11=> P11
|
// <0x12=> P12
|
// <0x13=> P13
|
// <0x14=> P14
|
// <0x15=> P15
|
// <0x16=> P16
|
// <0x17=> P17
|
// <0x20=> P20 (XTL1)
|
// <0x21=> P21 (XTL0)
|
// <0x22=> P22
|
// <0x23=> P23
|
// <0x24=> P24
|
// <0x25=> P25
|
// <0x26=> P26
|
// <0x27=> P27
|
// <0x30=> P30
|
// <0x31=> P31
|
// <i> Select a GPIO pin for User App Timing Track Channel 2.
|
#define CONFIG_TRACK_USER_APP_CHN2 0x99
|
|
// <o> User App Channel 3 Track Pin
|
// <0x99=> None
|
// <0x00=> P00 (SWD_CLK)
|
// <0x01=> P01 (SWD_DAT)
|
// <0x02=> P02
|
// <0x03=> P03
|
// <0x04=> P04
|
// <0x05=> P05
|
// <0x06=> P06
|
// <0x07=> P07
|
// <0x10=> P10
|
// <0x11=> P11
|
// <0x12=> P12
|
// <0x13=> P13
|
// <0x14=> P14
|
// <0x15=> P15
|
// <0x16=> P16
|
// <0x17=> P17
|
// <0x20=> P20 (XTL1)
|
// <0x21=> P21 (XTL0)
|
// <0x22=> P22
|
// <0x23=> P23
|
// <0x24=> P24
|
// <0x25=> P25
|
// <0x26=> P26
|
// <0x27=> P27
|
// <0x30=> P30
|
// <0x31=> P31
|
// <i> Select a GPIO pin for User App Timing Track Channel 3.
|
#define CONFIG_TRACK_USER_APP_CHN3 0x99
|
|
// <o> User App Channel 4 Track Pin
|
// <0x99=> None
|
// <0x00=> P00 (SWD_CLK)
|
// <0x01=> P01 (SWD_DAT)
|
// <0x02=> P02
|
// <0x03=> P03
|
// <0x04=> P04
|
// <0x05=> P05
|
// <0x06=> P06
|
// <0x07=> P07
|
// <0x10=> P10
|
// <0x11=> P11
|
// <0x12=> P12
|
// <0x13=> P13
|
// <0x14=> P14
|
// <0x15=> P15
|
// <0x16=> P16
|
// <0x17=> P17
|
// <0x20=> P20 (XTL1)
|
// <0x21=> P21 (XTL0)
|
// <0x22=> P22
|
// <0x23=> P23
|
// <0x24=> P24
|
// <0x25=> P25
|
// <0x26=> P26
|
// <0x27=> P27
|
// <0x30=> P30
|
// <0x31=> P31
|
// <i> Select a GPIO pin for User App Timing Track Channel 4.
|
#define CONFIG_TRACK_USER_APP_CHN4 0x99
|
|
// <o> User App Channel 5 Track Pin
|
// <0x99=> None
|
// <0x00=> P00 (SWD_CLK)
|
// <0x01=> P01 (SWD_DAT)
|
// <0x02=> P02
|
// <0x03=> P03
|
// <0x04=> P04
|
// <0x05=> P05
|
// <0x06=> P06
|
// <0x07=> P07
|
// <0x10=> P10
|
// <0x11=> P11
|
// <0x12=> P12
|
// <0x13=> P13
|
// <0x14=> P14
|
// <0x15=> P15
|
// <0x16=> P16
|
// <0x17=> P17
|
// <0x20=> P20 (XTL1)
|
// <0x21=> P21 (XTL0)
|
// <0x22=> P22
|
// <0x23=> P23
|
// <0x24=> P24
|
// <0x25=> P25
|
// <0x26=> P26
|
// <0x27=> P27
|
// <0x30=> P30
|
// <0x31=> P31
|
// <i> Select a GPIO pin for User App Timing Track Channel 5.
|
#define CONFIG_TRACK_USER_APP_CHN5 0x99
|
|
// <o> User App Channel 6 Track Pin
|
// <0x99=> None
|
// <0x00=> P00 (SWD_CLK)
|
// <0x01=> P01 (SWD_DAT)
|
// <0x02=> P02
|
// <0x03=> P03
|
// <0x04=> P04
|
// <0x05=> P05
|
// <0x06=> P06
|
// <0x07=> P07
|
// <0x10=> P10
|
// <0x11=> P11
|
// <0x12=> P12
|
// <0x13=> P13
|
// <0x14=> P14
|
// <0x15=> P15
|
// <0x16=> P16
|
// <0x17=> P17
|
// <0x20=> P20 (XTL1)
|
// <0x21=> P21 (XTL0)
|
// <0x22=> P22
|
// <0x23=> P23
|
// <0x24=> P24
|
// <0x25=> P25
|
// <0x26=> P26
|
// <0x27=> P27
|
// <0x30=> P30
|
// <0x31=> P31
|
// <i> Select a GPIO pin for User App Timing Track Channel 6.
|
#define CONFIG_TRACK_USER_APP_CHN6 0x99
|
|
// <o> User App Channel 7 Track Pin
|
// <0x99=> None
|
// <0x00=> P00 (SWD_CLK)
|
// <0x01=> P01 (SWD_DAT)
|
// <0x02=> P02
|
// <0x03=> P03
|
// <0x04=> P04
|
// <0x05=> P05
|
// <0x06=> P06
|
// <0x07=> P07
|
// <0x10=> P10
|
// <0x11=> P11
|
// <0x12=> P12
|
// <0x13=> P13
|
// <0x14=> P14
|
// <0x15=> P15
|
// <0x16=> P16
|
// <0x17=> P17
|
// <0x20=> P20 (XTL1)
|
// <0x21=> P21 (XTL0)
|
// <0x22=> P22
|
// <0x23=> P23
|
// <0x24=> P24
|
// <0x25=> P25
|
// <0x26=> P26
|
// <0x27=> P27
|
// <0x30=> P30
|
// <0x31=> P31
|
// <i> Select a GPIO pin for User App Timing Track Channel 7.
|
#define CONFIG_TRACK_USER_APP_CHN7 0x99
|
// </e> Enable IO Timing Track End
|
|
// <q> Enable Startup Long Delay
|
// <i> Add a long delay at system startup stage for debugging purpose.
|
// <i> e.g. This can make jlink programing easier when low-power mode enabled.
|
#define CONFIG_STARTUP_LONG_DELAY 0
|
|
// </h> Log Config End
|
//
|
|
|
//*** <<< end of configuration section >>> ***
|
|
#endif /* SDK_CONFIG_H */
|
