/**
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*******************************************************************************
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* @file soc_32k_cali.c
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* @create 2024-12-11
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* @author Panchip BLE GROUP
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* @note
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* Copyright (c) 2022-2024 Shanghai Panchip Microelectronics Co.,Ltd.
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*
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*******************************************************************************
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*/
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#include "soc_api.h"
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/* For RCL Clock test */
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//#define PRINT_RCL_FREQ_BEFORE_AND_AFTER_CALIBRATE
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#define DST_CLK_CNT 100 /* measure 100 clock-32k period */
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#if (CONFIG_LOW_SPEED_CLOCK_SRC == 1)
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uint32_t clk_32k_freq = 32768;
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#else
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uint32_t clk_32k_freq = 32000;
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#endif
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uint32_t clktrim_measure_32k_clk(uint32_t dst_clk_cnt)
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{
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uint32_t counter_result;
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uint32_t calib_freq;
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CLK_EnableClkTrim(ENABLE);
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CLK_SelectClkTrimSrc(CLKTRIM_CALC_CLK_SEL_32K);
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TRIM_SetCalCnt(TRIM, dst_clk_cnt);
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TRIM_StartTuning(TRIM, TRIM_MEASURE_TUNING_EN_Msk);
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while (!TRIM_IsIntStatusOccured(TRIM, TRIM_FLAG_MEASURE_STOP_Msk)) {
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/* busy-wait */
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}
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TRIM_ClearIntStatusMsk(TRIM, TRIM_FLAG_MEASURE_STOP_Msk);
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counter_result = TRIM_GetRealCnt(TRIM);
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calib_freq = ((uint64_t)FREQ_32MHZ * (uint64_t)dst_clk_cnt) / counter_result;
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clk_32k_freq = calib_freq;
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CLK_EnableClkTrim(DISABLE);
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return calib_freq;
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}
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CONFIG_RAM_CODE void clktrim_32k_clk_measure_start(uint32_t dst_clk_cnt)
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{
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CLK_EnableClkTrim(ENABLE);
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CLK_SelectClkTrimSrc(CLKTRIM_CALC_CLK_SEL_32K);
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TRIM_SetCalCnt(TRIM, dst_clk_cnt);
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TRIM_StartTuning(TRIM, TRIM_MEASURE_TUNING_EN_Msk);
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}
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CONFIG_RAM_CODE uint32_t clktrim_32k_clk_measure_value_get(void)
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{
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uint32_t counter_result;
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while (!TRIM_IsIntStatusOccured(TRIM, TRIM_FLAG_MEASURE_STOP_Msk)) {
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/* busy-wait */
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}
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TRIM_ClearIntStatusMsk(TRIM, TRIM_FLAG_MEASURE_STOP_Msk);
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counter_result = TRIM_GetRealCnt(TRIM);
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CLK_EnableClkTrim(DISABLE);
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return counter_result;
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}
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#if (CONFIG_LOW_SPEED_CLOCK_SRC == 0)
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void calibrate_rcl_clk(uint32_t expected_freq)
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{
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uint32_t AHB_clk_reg;
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const uint8_t coarse_tune_bitwidth = 3;
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const uint8_t fine_tune_bitwidth = 7;
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#ifdef PRINT_RCL_FREQ_BEFORE_AND_AFTER_CALIBRATE
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printf("RCL Freq before calib: %d Hz\n", clktrim_measure_32k_clk(DST_CLK_CNT));
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#endif
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AHB_clk_reg = CLK->AHB_CLK_CTRL;
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CLK->AHB_CLK_CTRL |= CLK_AHBPeriph_APB2;
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TRIM_EnableInt(TRIM, ENABLE);
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/* Start calibration */
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/* Disable hardware calculate. */
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ANA->RCL_HW_CAL_CTRL &= ~ANAC_RCL_HW_CAL_EN_Msk;
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/* Enable Clktrim */
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CLK_SelectClkTrimSrc(CLKTRIM_CALC_CLK_SEL_32K);
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CLK_EnableClkTrim(ENABLE);
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TRIM_SetCalCnt(TRIM, DST_CLK_CNT);
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TRIM_SetIdealCnt(TRIM, FREQ_32MHZ / expected_freq * DST_CLK_CNT - 1);
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/* a. Coarse tuning proc */
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TRIM_SetBitWidth(TRIM, coarse_tune_bitwidth);
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TRIM_SetCoarseCode(TRIM, 1 << coarse_tune_bitwidth);
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TRIM_StartTuning(TRIM, TRIM_COARSE_TUNING_EN_Msk);
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while (!TRIM_IsIntStatusOccured(TRIM, TRIM_FLAG_CTUNE_STOP_Msk)) {
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/* busy-wait */
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}
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TRIM_ClearIntStatusMsk(TRIM, TRIM_FLAG_CTUNE_STOP_Msk);
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/* b. Fine tuning proc */
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TRIM_SetBitWidth(TRIM, fine_tune_bitwidth);
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TRIM_SetFineCode(TRIM, 1 << fine_tune_bitwidth);
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TRIM_StartTuning(TRIM, TRIM_FINE_TUNING_EN_Msk);
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while (!TRIM_IsIntStatusOccured(TRIM, TRIM_FLAG_FTUNE_STOP_Msk)) {
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/* busy-wait */
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}
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TRIM_ClearIntStatusMsk(TRIM, TRIM_FLAG_FTUNE_STOP_Msk);
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/* Disable Clktrim */
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CLK_EnableClkTrim(DISABLE);
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CLK->AHB_CLK_CTRL = AHB_clk_reg;
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#ifdef PRINT_RCL_FREQ_BEFORE_AND_AFTER_CALIBRATE
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printf("RCL Freq after calib: %d Hz\n", clktrim_measure_32k_clk(DST_CLK_CNT));
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#endif
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}
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#endif /* CONFIG_LOW_SPEED_CLOCK_SRC == 0 */
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