/**
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*******************************************************************************
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* @file soc_pm.c
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* @create 2024-12-11
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* @author Panchip BLE GROUP
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* @note
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* Copyright (c) 2022-2024 Shanghai Panchip Microelectronics Co.,Ltd.
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*
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*******************************************************************************
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*/
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#include "soc_api.h"
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#if CONFIG_PM_STANDBY_M1_WAKEUP_WITHOUT_RESET
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#include "FreeRTOS.h"
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#include "task.h"
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/* Constants required to manipulate the NVIC. */
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#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
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#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
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#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
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#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
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#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
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#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
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#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
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#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
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#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
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#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
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#define portNVIC_PEND_SYSTICK_SET_BIT ( 1UL << 26UL )
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#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
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#define portMIN_INTERRUPT_PRIORITY ( 255UL )
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#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )
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#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )
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#define configSYSTICK_CLOCK_HZ ( configCPU_CLOCK_HZ )
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#define portNVIC_SYSTICK_CLK_BIT_CONFIG ( portNVIC_SYSTICK_CLK_BIT )
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#define portSY_FULL_READ_WRITE ( 15 )
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extern uint32_t ulTimerCountsForOneTick;
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extern void UpdateTickAndSch(void);
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extern const uint32_t PanFlashLineMode;
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extern const bool PanFlashEnhanceEnable;
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#endif // CONFIG_PM_STANDBY_M1_WAKEUP_WITHOUT_RESET
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#define FLASH_RDP_WT_CNT 0x400 // Flash RDP wait cycle count
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#if CONFIG_PM
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static uint32_t stbm1_gpio_int_flag = 0;
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uint32_t soc_stbm1_gpio_wakeup_src_get(void)
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{
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return stbm1_gpio_int_flag;
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}
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CONFIG_RAM_CODE void LP_IRQHandler()
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{
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/*
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* Clear DeepSleep int flag (write 1 to clear) in this register, but still
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* retain all other ctrl/status flags.
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*/
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ANA->LP_INT_CTRL = (ANA->LP_INT_CTRL | ANAC_INT_DP_FLAG_Msk)
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& ~(ANAC_INT_SLEEP_TMR0_Msk | ANAC_INT_SLEEP_TMR1_Msk | ANAC_INT_SLEEP_TMR2_Msk
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| ANAC_INT_STANDBY_M1_FLAG_Msk | ANAC_INT_STANDBY_M0_FLAG_Msk | ANAC_INT_SRAM_RET_FLAG_Msk);
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/* Re-disable LP IRQ after use */
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NVIC_DisableIRQ(LP_IRQn);
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}
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void deepsleep_init(void)
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{
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uint32_t RamPowerCtrl = 0x1F; // Enable power of all sram in Deepsleep mode
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// Enable SLPTMR interrupt and wakeup
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ANA->LP_INT_CTRL |= ANAC_INT_SLEEP_TMR_WK_EN_Msk;
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#if CONFIG_DEEPSLEEP_MODE_2
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// Configure power of deepsleep to mode 2 (Only LPLDOH in use)
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ANA->LP_LP_LDO_3V |= ANAC_LPLDO_H_EN_Msk_3v;
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ANA->LP_LP_LDO_3V &= ~ANAC_LPLDO_L_EN_Msk;
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ANA->LP_FL_CTRL_3V |= ANAC_LDOL_POWER_CTL_Msk | ANAC_LDO_POWER_CTL_Msk;
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ANA->LP_FL_CTRL_3V &= ~ANAC_FL_LDO_ISOLATE_EN_Msk;
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#else
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// Configure power of deepsleep to mode 1 (Both LPLDOH & LPLDOL in use)
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ANA->LP_LP_LDO_3V |= ANAC_LPLDO_H_EN_Msk_3v;
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ANA->LP_LP_LDO_3V |= ANAC_LPLDO_L_EN_Msk;
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ANA->LP_FL_CTRL_3V |= ANAC_LDO_POWER_CTL_Msk | ANAC_FL_LDO_ISOLATE_EN_Msk;
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ANA->LP_FL_CTRL_3V &= ~ANAC_LDOL_POWER_CTL_Msk;
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#endif /* CONFIG_DEEPSLEEP_MODE_2 */
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// Enable LPDOH mode 2 to save power
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ANA->LP_LP_LDO_3V |= ANAC_LPLDO_H_MODE_SEL_Msk_3v;
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#if CONFIG_KEEP_FLASH_POWER_IN_LP_MODE
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// Keep flash power in Deepsleep mode
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#if CONFIG_FLASH_LDO_EN
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ANA->LP_FL_CTRL_3V |= ANAC_FL_FLASH_LP_EN_Msk;
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ANA->LP_FL_CTRL_3V &= ~ANAC_FL_FLASH_BP_EN_Msk;
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#else
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ANA->LP_FL_CTRL_3V &= ~ANAC_FL_FLASH_LP_EN_Msk;
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ANA->LP_FL_CTRL_3V |= ANAC_FL_FLASH_BP_EN_Msk;
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#endif /* CONFIG_FLASH_LDO_EN */
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// Configure rdp wait cnt for auto dp use
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FMC_SetRdpWaitCount(FLCTL, FLASH_RDP_WT_CNT);
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#else
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// Power down flash in Deepsleep mode
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ANA->LP_FL_CTRL_3V &= ~ANAC_FL_FLASH_LP_EN_Msk;
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ANA->LP_FL_CTRL_3V &= ~ANAC_FL_FLASH_BP_EN_Msk;
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#endif /* CONFIG_KEEP_FLASH_POWER_IN_LP_MODE */
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// Configure power of SRAM
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ANA->LP_FL_CTRL_3V = ((RamPowerCtrl & 0x1f) << 24u) | (ANA->LP_FL_CTRL_3V & 0xe0FFFFFF);
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// Configure LP delay
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ANA->LP_DLY_CTRL_3V &= ~0x3ff;
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ANA->LP_DLY_CTRL_3V |= LP_DLY_TICK;
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// Configure LP irq
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NVIC_SetPriority(LP_IRQn, 3); // Lowest prio
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#if CONFIG_SYSTEM_WATCH_DOG_ENABLE
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system_watch_dog_init();
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#endif
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}
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void soc_pm_init(void)
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{
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// Init deepsleep flow
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deepsleep_init();
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// Clear phy rxlna icore register (R0062) to avoid power leakage in low power mode
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PHY_SingleRegWrite(0x62, 0x00);
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// printf("phy R0062 reg val after clear: 0x%02x\n", PHY_SingleRegRead(0x62));
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/* Store gpio int flags if any in case of waking up from standby mode 1 by gpio interrupt */
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*((uint8_t *)&stbm1_gpio_int_flag + 0) = P0->INTSRC;
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*((uint8_t *)&stbm1_gpio_int_flag + 1) = P1->INTSRC;
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*((uint8_t *)&stbm1_gpio_int_flag + 2) = P2->INTSRC;
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*((uint8_t *)&stbm1_gpio_int_flag + 3) = P3->INTSRC;
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}
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#if CONFIG_PM_STANDBY_M1_WAKEUP_WITHOUT_RESET
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__ASM void wfi_with_core_regs_backup_and_resume(void)
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{
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push {r0-r7} /* Backup r0 ~ r7 */
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mov r0, r8
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mov r1, r9
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mov r2, r10
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mov r3, r11
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mov r4, r12
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mov r5, lr
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push {r0-r5} /* Backup r8 ~ r12 and lr */
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wfi /* Trigger hw to enter low power mode */
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pop {r0-r5} /* Restore r8 ~ r12 and lr */
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mov r8, r0
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mov r9, r1
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mov r10, r2
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mov r11, r3
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mov r12, r4
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mov lr, r5
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pop {r0-r7} /* Restore r0 ~ r7 */
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bx lr /* Function return */
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}
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#endif /* CONFIG_PM_STANDBY_M1_WAKEUP_WITHOUT_RESET */
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/*
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* Several hw modules can be selectable to retain or lose power in this mode
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*/
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void soc_enter_standby_mode_1(uint32_t wakeup_src, uint32_t retention_sram)
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{
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/* Mask all IRQs when we are on the way to enter standby mode */
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__disable_irq();
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/* Disable Systick clock */
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SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
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/* Clear pending flag of systick (PENDSTCLR) if any */
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SCB->ICSR = (SCB->ICSR & (~BIT26)) | BIT25;
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/* StandbyM1 Power Mode 1, use both LPLDOH and LPLDOL */
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ANA->LP_LP_LDO_3V |= ANAC_LPLDO_H_EN_Msk_3v;
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ANA->LP_LP_LDO_3V |= ANAC_LPLDO_L_EN_Msk;
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ANA->LP_FL_CTRL_3V |= ANAC_FL_LDO_ISOLATE_EN_Msk;
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ANA->LP_FL_CTRL_3V &= ~(ANAC_LDOL_POWER_CTL_Msk | ANAC_LDO_POWER_CTL_Msk);
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/* LPDOH switch to mode 2 for better power consumption performance */
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ANA->LP_LP_LDO_3V |= ANAC_LPLDO_H_MODE_SEL_Msk_3v;
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/* Power down Flash in lp mode discard the dedicated Flash LDO enabled or not */
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ANA->LP_FL_CTRL_3V = (ANA->LP_FL_CTRL_3V & ~(0x3 << 12u)) | (0x0 << 12u);
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/* Enable proper 32k clock in low power mode */
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if (CLK->CLK_TOP_CTRL_3V & CLK_TOPCTL_32K_CLK_SEL_Msk_3v) {
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ANA->LP_FL_CTRL_3V |= ANAC_FL_XTAL32K_EN_Msk_3v;
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ANA->LP_FL_CTRL_3V &= ~ANAC_FL_RC32K_EN_Msk_3v;
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} else {
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ANA->LP_FL_CTRL_3V &= ~ANAC_FL_XTAL32K_EN_Msk_3v;
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ANA->LP_FL_CTRL_3V |= ANAC_FL_RC32K_EN_Msk_3v;
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}
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/*
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* Configure retention SRAM modules in low power mode:
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* - (BIT2) The 256B Decrypt SRAM should be enabled in standby mode 1 in case Firmware Encryption enabled
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* - (BIT3) The 256 B PHY SEQ RAM + PHY Registers should be always enabled in standby mode 1 to avoid
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* possible power leakage of RF phy rxlna icore registers
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* - (BIT0/BIT1/BIT4) The other SRAMs (32KB SRAM0 / 16KB SRAM1 / 8KB LLSRAM) can be configured by user to
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* enable or disable the power supply in standby mode 1
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*/
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#if CONFIG_FIRMWARE_ENCRYPTION
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retention_sram |= BIT2; // Decrypt SRAM
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#endif
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retention_sram |= BIT3; // PHY SEQ RAM + PHY Registers
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ANA->LP_FL_CTRL_3V = ((retention_sram & 0x1f) << 24u) | (ANA->LP_FL_CTRL_3V & 0xe0FFFFFF);
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/* Set digital delay with 32k tick unit */
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ANA->LP_DLY_CTRL_3V &= ~0x3ff;
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ANA->LP_DLY_CTRL_3V |= LP_DLY_TICK;
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/* Insure we are going to enter hw standby mode 1 */
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LP_SetSleepMode(ANA, LP_MODE_SEL_STANDBY_M1_MODE);
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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/* Trigger 3v sync */
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ANA->LP_REG_SYNC |= ANAC_LP_REG_SYNC_3V_Msk | ANAC_LP_REG_SYNC_3V_TRG_Msk;
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// if (wakeup_src & STBM1_WAKEUP_SRC_GPIO) {
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// /* Do nothing here */
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// } else {
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// /* Reset GPIO module to default state */
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// CLK->IPRST1 = CLK_IPRST1_GPIORST_Msk;
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// CLK->IPRST1 = 0x0;
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// }
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/* Set specific slptmr timeout cnt if needed */
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if (wakeup_src & STBM1_WAKEUP_SRC_SLPTMR) {
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// Clear configured OS wakeup timer (sleep timer 0) to avoid unexpected wakeup
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ANA->LP_SPACING_TIME0 = 0;
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} else {
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/* Disable SLPTMR interrupt and wakeup in lp mode (Only enable LP interrupt) */
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ANA->LP_INT_CTRL = ANAC_INT_LP_INT_EN_Msk;
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// Clear configured time of sleep timers
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ANA->LP_SPACING_TIME0 = 0;
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ANA->LP_SPACING_TIME1 = 0;
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ANA->LP_SPACING_TIME2 = 0;
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}
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/* Clear all lowpower related int flags if any */
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ANA->LP_INT_CTRL = ANA->LP_INT_CTRL;
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#if 0
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/* Reset all hw peripheral modules except eFuse and GPIO */
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CLK->IPRST0 = 0x1CC;
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CLK->IPRST0 = 0x0;
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CLK->IPRST1 = 0x17FFF;
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CLK->IPRST1 = 0x0;
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#endif
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/* Disable all IRQs and clear all pending IRQs on NVIC */
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NVIC->ICER[0U] = 0xFFFFFFFF;
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NVIC->ICPR[0U] = 0xFFFFFFFF;
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/* Wait until 3v sync done */
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while (ANA->LP_REG_SYNC & (ANAC_LP_REG_SYNC_3V_TRG_Msk)) {
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__NOP();
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}
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#if !CONFIG_PM_STANDBY_M1_WAKEUP_WITHOUT_RESET
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#if CONFIG_VECTOR_REMAP_TO_RAM
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/* Reset CPU Vector Remap register to avoid issue after waking up */
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ANA->CPU_ADDR_REMAP_CTRL = 0;
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#endif
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/* Trigger hw to enter low power mode */
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__WFI();
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/*
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* ======== (Now SoC is expected in HW Standby Mode 1 and would never return back here) =========
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*/
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#else
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/*
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* Enable CPU core regs retention in standby mode 1
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* The CPU core registers PC, MSP, PSP and CONTROL would automatically
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* be saved and restored by hardware in SoC standby mode 1.
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*/
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ANA->LP_FL_CTRL_3V |= ANAC_FL_CPU_RETENTION_EN_Msk;
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/* Backup the FMC remap register in case we configure it in bootloader */
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uint32_t fmc_remap_bkp = FLCTL->X_FL_REMAP_ADDR;
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/* Records the time the current timestamp is used to calculate the sleep
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* value after the system wakes up */
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vTaskTickSet(lp_get_curr_tmr_cnt());
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/*
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* 1. Backup CPU core registers which are not auto-saved by hardware
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* 2. Enter SoC Standby Mode 1 (WFI)
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* 3. Restore previous backup CPU core registers
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*/
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wfi_with_core_regs_backup_and_resume();
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/* Restore FMC remap register after waking up */
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FLCTL->X_FL_REMAP_ADDR = fmc_remap_bkp;
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/* Reset SoC lp mode to sleep mode (1.2v area, do not need 3v sync) */
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ANA->LP_FL_CTRL_3V = (ANA->LP_FL_CTRL_3V & ~ANAC_FL_SLEEP_MODE_SEL_Msk)
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| (LP_MODE_SEL_SLEEP_MODE << ANAC_FL_SLEEP_MODE_SEL_Pos);
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/* Restore fmc and flash status */
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FMC_SetFlashMode(FLCTL, PanFlashEnhanceEnable, PanFlashEnhanceEnable);
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/* Reinit I-Cache */
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InitIcache(FLCTL, PanFlashEnhanceEnable);
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/*
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* Clear StandbyM1 int flag (write 1 to clear) in this register, but still
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* retain all other ctrl/status flags.
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*/
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ANA->LP_INT_CTRL = (ANA->LP_INT_CTRL | ANAC_INT_STANDBY_M1_FLAG_Msk)
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& ~(ANAC_INT_SLEEP_TMR0_Msk | ANAC_INT_SLEEP_TMR1_Msk | ANAC_INT_SLEEP_TMR2_Msk
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| ANAC_INT_DP_FLAG_Msk | ANAC_INT_STANDBY_M0_FLAG_Msk | ANAC_INT_SRAM_RET_FLAG_Msk);
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/* Restore 32K current counter register LPTMR_CURR_CNT_ENA_REG */
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(*(volatile uint32_t *)0x5002000C) |= BIT1;
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/* Update OS tick and scheduler */
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UpdateTickAndSch();
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/* Restart systick, use configTICK_ON_WAKING_RATE_HZ */
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portNVIC_SYSTICK_CTRL_REG = 0UL;
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portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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/* Configure SysTick to interrupt at the requested rate. */
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portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
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portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT_CONFIG | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
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/* Exit with interrupts enabled. */
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__enable_irq();
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#endif /* CONFIG_PM_STANDBY_M1_WAKEUP_WITHOUT_RESET */
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}
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/*
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* The most power saving mode in which can only be waked up by GPIO P02/P01/P00 pin
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*/
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void soc_enter_standby_mode_0(void)
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{
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/* Mask all IRQs when we are on the way to enter standby mode */
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__disable_irq();
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/* Disable Systick clock */
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SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
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/* Clear pending flag of systick (PENDSTCLR) if any */
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SCB->ICSR = (SCB->ICSR & (~BIT26)) | BIT25;
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#if 0
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/* Enable proper 32k clock in low power mode */
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if (CLK->CLK_TOP_CTRL_3V & CLK_TOPCTL_32K_CLK_SEL_Msk_3v) {
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ANA->LP_FL_CTRL_3V |= ANAC_FL_XTAL32K_EN_Msk_3v;
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ANA->LP_FL_CTRL_3V &= ~ANAC_FL_RC32K_EN_Msk_3v;
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} else {
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ANA->LP_FL_CTRL_3V &= ~ANAC_FL_XTAL32K_EN_Msk_3v;
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ANA->LP_FL_CTRL_3V |= ANAC_FL_RC32K_EN_Msk_3v;
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}
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#else
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// Disable 32K Clock Source to save power
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ANA->LP_FL_CTRL_3V &= ~ANAC_FL_RC32K_EN_Msk_3v;
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ANA->LP_FL_CTRL_3V &= ~ANAC_FL_XTAL32K_EN_Msk_3v;
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#endif
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/* Set digital delay with 32k tick unit */
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ANA->LP_DLY_CTRL_3V &= ~0x3ff;
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ANA->LP_DLY_CTRL_3V |= LP_DLY_TICK;
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/* Insure we are going to enter hw standby mode 1 */
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LP_SetSleepMode(ANA, LP_MODE_SEL_STANDBY_M0_MODE);
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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/* Trigger 3v sync */
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ANA->LP_REG_SYNC |= ANAC_LP_REG_SYNC_3V_Msk | ANAC_LP_REG_SYNC_3V_TRG_Msk;
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/* Disable SLPTMR interrupt and wakeup in lp mode (Only enable LP interrupt) */
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ANA->LP_INT_CTRL = ANAC_INT_LP_INT_EN_Msk;
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// Clear configured time of sleep timers
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ANA->LP_SPACING_TIME0 = 0;
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ANA->LP_SPACING_TIME1 = 0;
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ANA->LP_SPACING_TIME2 = 0;
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/* Clear all lowpower related int flags if any */
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ANA->LP_INT_CTRL = ANA->LP_INT_CTRL;
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#if 0
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/* Reset all hw peripheral modules except eFuse and GPIO */
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CLK->IPRST0 = 0x1CC;
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CLK->IPRST0 = 0x0;
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CLK->IPRST1 = 0x17FFF;
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CLK->IPRST1 = 0x0;
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#endif
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/* Disable all IRQs and clear all pending IRQs on NVIC */
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NVIC->ICER[0U] = 0xFFFFFFFF;
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NVIC->ICPR[0U] = 0xFFFFFFFF;
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/* Wait until 3v sync done */
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while (ANA->LP_REG_SYNC & (ANAC_LP_REG_SYNC_3V_TRG_Msk)) {
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__NOP();
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}
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/* Trigger hw to enter low power mode */
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__WFI();
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/*
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* ======== (Now SoC is expected in HW Standby Mode 0 and would never return back here) =========
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*/
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}
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#endif /* CONFIG_PM */
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