/*
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* Copyright (c) 2019-2023 Beijing Hanwei Innovation Technology Ltd. Co. and
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* its subsidiaries and affiliates (collectly called MKSEMI).
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form, except as embedded into an MKSEMI
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* integrated circuit in a product or a software update for such product,
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* must reproduce the above copyright notice, this list of conditions and
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* the following disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* 3. Neither the name of MKSEMI nor the names of its contributors may be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* 4. This software, with or without modification, must only be used with a
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* MKSEMI integrated circuit.
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*
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* 5. Any software provided in binary form under this license must not be
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* reverse engineered, decompiled, modified and/or disassembled.
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*
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* THIS SOFTWARE IS PROVIDED BY MKSEMI "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL MKSEMI OR CONTRIBUTORS BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "mk_calib.h"
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#include "mk_clock.h"
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#include "mk_reset.h"
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#include "mk_trace.h"
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#include "mk_misc.h"
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#include "mk_rtc.h"
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#include "board.h"
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int calib_open(void)
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{
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// enable CAL clock
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clock_enable(CLOCK_CALIB);
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reset_module(RESET_MODULE_CALIB);
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return DRV_OK;
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}
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int calib_close(void)
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{
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// disable CAL clock
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clock_disable(CLOCK_CALIB);
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return DRV_OK;
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}
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void calib_start(uint32_t items)
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{
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REG_WRITE(CALIB_BASE, items | CALIB_START);
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}
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void calib_check(uint32_t done)
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{
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while ((REG_READ(CALIB_BASE + 0x4) & done) != done)
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{
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}
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}
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void calib_chip(void)
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{
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uint32_t val;
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// load cap
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if (board_param.flag & (1 << BOARD_LOAD_CAP))
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{
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calib_xtal38m4_load_cap_set(board_param.load_cap);
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}
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if (board_param.flag & (1 << BOARD_X32K_LOAD_CAP))
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{
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calib_xtal32k_load_cap_set(board_param.x32k_load_cap);
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}
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clock_enable(CLOCK_CALIB);
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// fix DCDC_EN
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val = REG_READ(0x40000204) & ~0x3U;
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REG_WRITE(0x40000204, val | 0x2);
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// LO PLL configure
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REG_WRITE(0x4000060c, 0x0A106BAF);
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#if HIGH_PERFORMANCE_MODE_EN
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// LPF_BM
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REG_WRITE(0x40000608, 0x03E80004);
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// increase Trim current to promote RF performance
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REG_WRITE_BYTE(0x40010072, 0x77);
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#else
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// decrease Trim current
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// REG_WRITE_BYTE(0x40010072, 0x88); // lowest
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// clear Trim code
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REG_WRITE_BYTE(0x40010072, 0x00); // middle
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val = REG_READ_BYTE(0x40010071) & 0x1F;
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REG_WRITE_BYTE(0x40010071, (uint8_t)val);
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#endif
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#define LO_L (77 + (56 << 8) + (54 << 16) + (80 << 24))
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#define LO_H (49 + (46 << 8) + (50 << 16) + (54 << 24))
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#define WF (7 + (52 << 8))
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// patch for buck calibration voltage
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uint8_t x = REG_READ_BYTE(0x40010075);
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if ((READ_WORD(0x4001007C) == LO_L) && (READ_WORD(0x40010078) == LO_H) && (READ_SHORT(0x40010076) == WF) && (x >= 1) && (x <= 19))
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{
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REG_WRITE_BYTE(0x40010073, 0x20);
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}
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// patch for ADC trim code
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val = REG_READ_BYTE(0x4001006B);
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if ((val & 0x1F) == 0)
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{
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REG_WRITE_BYTE(0x4001006B, (uint8_t)(val | 0x10));
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}
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// Open RCO for calibration
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SYSCON->PMU_CTRL0 &= ~(1U << 5);
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// calibrate
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REG_WRITE(0x40006000, 0x80001cfe);
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while ((REG_READ(0x40006004) & 0x80000000) == 0)
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{
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}
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uint32_t id = mk_chip_id();
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LOG_INFO(TRACE_MODULE_DRIVER, "Chip ID: %08x\r\n", id);
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if (id == 0x0 || id == 0x400 || id == 0x800 || id == 0xC00)
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{
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LOG_INFO(TRACE_MODULE_DRIVER, "Old chip model is not supported by this SDK!!!\r\n");
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while (1)
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{
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}
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}
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// Reduce next PA calibration time
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val = REG_READ(0x400060d4) & ~0xfU;
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REG_WRITE(0x400060d4, val);
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val = REG_READ(0x400060c8) & ~((0xfU << 18) | (0x1));
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REG_WRITE(0x400060c8, val);
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// Reduce turnaround time
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REG_WRITE(0x40000410, 400);
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REG_WRITE(0x4000040c, 0x1f);
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// val = REG_READ(0x4000020c) & ~(0x1fU << 7);
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// REG_WRITE(0x4000020c, val | (0x18 << 7));
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#if (LOW_POWER_EN) && (XTAL32K_EN == 0)
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rco32k_clk_calibrate(RCO32K_MEAS_TIME_64_CYCLES);
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#endif
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}
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void calib_xtal38m4_load_cap_auto_tune(int32_t ppm)
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{
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uint32_t tmp_val = REG_READ(0x40000048);
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uint8_t val = (tmp_val & 0x7FU);
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if (ppm > 2)
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{
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val += 1;
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}
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else if (ppm < -2)
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{
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val -= 1;
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}
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else
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{
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return;
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}
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tmp_val &= ~0x7FU;
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tmp_val |= (val & 0x7FU);
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REG_WRITE(0x40000048, tmp_val);
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LOG_INFO(TRACE_NO_REPORT_HOST | TRACE_MODULE_DRIVER, "XTAL load cap tune %d : %d\r\n", ppm, (tmp_val & 0x7FU));
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}
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void calib_xtal38m4_load_cap_set(uint8_t val)
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{
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uint32_t tmp_val = REG_READ(0x40000048);
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tmp_val &= ~0x7FU;
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val &= 0x7FU;
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REG_WRITE(0x40000048, tmp_val | val);
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LOG_INFO(TRACE_MODULE_DRIVER, "XTAL load cap val %d\r\n", REG_READ(0x40000048) & 0x7FU);
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}
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void calib_xtal38m4_with_clock_out(uint8_t val)
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{
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/* Setting GPIO17 output 38.4M clock. */
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uint32_t tmp_val = REG_READ(0x4000003C);
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tmp_val &= ~0x70U;
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tmp_val |= (0x1U << 4);
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REG_WRITE(0x4000003C, tmp_val);
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/* Setting internal load cap of MK8000, the valid value is from 0 ot 127. */
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tmp_val = REG_READ(0x40000048);
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tmp_val &= ~0x7FU;
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val &= 0x7FU;
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REG_WRITE(0x40000048, tmp_val | val);
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REG_WRITE(0x40000104, 0x3FFF);
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LOG_INFO(TRACE_MODULE_DRIVER, "XTAL load cap val %d\r\n", REG_READ(0x40000048) & 0x7FU);
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}
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void calib_xtal32k_load_cap_set(uint8_t val)
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{
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uint32_t tmp_val = REG_READ(0x4000004C);
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tmp_val &= ~0x7FU;
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val &= 0x7FU;
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REG_WRITE(0x4000004C, tmp_val | val);
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LOG_INFO(TRACE_MODULE_DRIVER, "32K load cap val %d\r\n", REG_READ(0x4000004C) & 0x7FU);
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}
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void calib_xtal32k_with_clock_out(uint8_t val)
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{
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/* Setting GPIO02 output 32K clock. */
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uint32_t tmp_val = REG_READ(0x40000234);
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tmp_val |= (0x1U << 10);
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REG_WRITE(0x40000234, tmp_val);
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/* Setting GPIO02 oupt 32K clock by pin mux. */
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tmp_val = REG_READ(0x40000034);
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tmp_val &= ~(0xFU << 8);
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tmp_val |= (0x4U << 8);
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REG_WRITE(0x40000034, tmp_val);
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/* Setting internal load cap of MK8000, the valid value is from 0 ot 127. */
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tmp_val = REG_READ(0x4000004C);
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tmp_val &= ~0x7FU;
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val &= 0x7FU;
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REG_WRITE(0x4000004C, tmp_val | val);
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LOG_INFO(TRACE_MODULE_DRIVER, "32K load cap val %d\r\n", REG_READ(0x4000004C) & 0x7FU);
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}
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void CALIB_IRQHandler(void)
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{
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}
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