/*
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* Copyright (c) 2019-2023 Beijing Hanwei Innovation Technology Ltd. Co. and
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* its subsidiaries and affiliates (collectly called MKSEMI).
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form, except as embedded into an MKSEMI
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* integrated circuit in a product or a software update for such product,
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* must reproduce the above copyright notice, this list of conditions and
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* the following disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* 3. Neither the name of MKSEMI nor the names of its contributors may be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* 4. This software, with or without modification, must only be used with a
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* MKSEMI integrated circuit.
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*
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* 5. Any software provided in binary form under this license must not be
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* reverse engineered, decompiled, modified and/or disassembled.
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*
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* THIS SOFTWARE IS PROVIDED BY MKSEMI "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL MKSEMI OR CONTRIBUTORS BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef MK_DMA_H_
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#define MK_DMA_H_
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#include "mk_common.h"
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/**
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* @addtogroup MK8000_DMA
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* @{
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*/
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#define DMA_INT_TYPE_ABORT 1 /*!< DMA abort status */
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#define DMA_INT_TYPE_ERROR 2 /*!< DMA error status */
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#define DMA_INT_TYPE_DONE 3 /*!< DMA done status */
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#define DMA_INT_TYPE_FORCE_ABORT 4 /*!< DMA force abort status */
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/**
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* @brief DMA device IDs enumeration
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*/
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enum DMA_DEV_T
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{
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DMA_ID0 = 0,
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DMA_MAX_NUM
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};
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/**
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* @brief DMA Channels definition.
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* @note Avoid multiple peripherals DMA requests mapped on the same channel of DMA.
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*/
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enum DMA_CH_T
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{
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DMA_CH0 = 0, /*!< SPI0-RX DMA requests mapped on DMA channel 0 */
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DMA_CH1, /*!< ADC or SPI0-TX DMA requests mapped on DMA channel 1 */
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DMA_CH2, /*!< AES-IN/FLASH-WRITE/SPI1-RX DMA requests mapped on DMA channel 2 */
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DMA_CH3, /*!< AES-OUT/FLASH-READ/SPI1-TX DMA requests mapped on DMA channel 3 */
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DMA_CH4, /*!< UART0-RX DMA requests mapped on DMA channel 4 */
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DMA_CH5, /*!< UART0-TX DMA requests mapped on DMA channel 5 */
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DMA_CH6, /*!< UART1-TX DMA requests mapped on DMA channel 6 */
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DMA_CH7, /*!< UART1-TX DMA requests mapped on DMA channel 7 */
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DMA_CH_NUM,
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};
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/**
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* @brief DMA FIFO threshold value.
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* @note DMA FIFO space >= DMA_FF_TH, DMA will start to transfer data from source to FIFO.
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* The number of valid data in DMA FIFO >= DMA_FF_TH, the DMA will start to pop out data from FIFO to the destination.
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*/
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enum DMA_FIFO_TH_T
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{
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DMA_FIFO_TH_1 = 0, /*!< FIFO threshold value is 1 */
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DMA_FIFO_TH_2, /*!< FIFO threshold value is 2 */
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DMA_FIFO_TH_4, /*!< FIFO threshold value is 4 */
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DMA_FIFO_TH_8, /*!< FIFO threshold value is 8 */
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DMA_FIFO_TH_16, /*!< FIFO threshold value is 16 */
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};
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/**
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* @brief DMA burst size definition.
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* @note Burst size are set according to the size of the peripheral buffer being accessed.
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*/
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enum DMA_SRC_BURST_SIZE_T
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{
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DMA_SRC_BURST_SIZE_1 = 0,
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DMA_SRC_BURST_SIZE_4,
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DMA_SRC_BURST_SIZE_8,
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DMA_SRC_BURST_SIZE_16,
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DMA_SRC_BURST_SIZE_32,
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DMA_SRC_BURST_SIZE_64,
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DMA_SRC_BURST_SIZE_128,
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DMA_SRC_BURST_SIZE_256,
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};
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/**
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* @brief DMA memory/peripheral data width.
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*
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*/
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enum DMA_WIDTH_T
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{
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DMA_WIDTH_1B = 0, /*!< Data aligned by byte */
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DMA_WIDTH_2B, /*!< Data aligned by halfword */
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DMA_WIDTH_4B /*!< Data aligned by word */
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};
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/**
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* @brief DMA SRC/DEST address control mode.
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*/
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enum DMA_ADDR_CTRL_T
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{
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DMA_ADDR_INC = 0, /*!< ADDR increment mode */
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DMA_ADDR_DEC, /*!< ADDR decrement mode */
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DMA_ADDR_FIXED, /*!< ADDR fixed mode */
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};
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/**
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* @brief DMA source request definition.
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*/
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enum DMA_REQ_SEL_T
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{
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DMA_REQ_MEM = 0x00,
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DMA_REQ_SPI0_RX = 0x10,
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DMA_REQ_SPI0_TX = 0x11,
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DMA_REQ_SPI1_RX = 0x12,
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DMA_REQ_SPI1_TX = 0x13,
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DMA_REQ_FLASH = 0x14,
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DMA_REQ_AES_RX = 0x15,
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DMA_REQ_AES_TX = 0x16,
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DMA_REQ_UART0_RX = 0x17,
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DMA_REQ_UART0_TX = 0x18,
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DMA_REQ_UART1_RX = 0x19,
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DMA_REQ_UART1_TX = 0x1A,
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DMA_REQ_ADC = 0x1B,
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};
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/**
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* @brief DMA channel configure Structure
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*/
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struct DMA_CH_CFG_T
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{
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enum DMA_FIFO_TH_T fifo_th; /*!< Specifies the FIFO threshold level.
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This parameter can be a value of @ref DMA_FIFO_TH_T */
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enum DMA_SRC_BURST_SIZE_T src_burst_size; /*!< Specifies the Burst transfer configuration.
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This parameter can be a value of @ref DMA_SRC_BURST_SIZE_T */
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enum DMA_WIDTH_T src_width; /*!< Specifies the source data width.
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This parameter can be a value of @ref DMA_WIDTH_T */
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enum DMA_WIDTH_T dst_width; /*!< Specifies the destination data width.
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This parameter can be a value of @ref DMA_WIDTH_T */
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enum DMA_ADDR_CTRL_T src_addr_ctrl; /*!< Specifies the source address control mode.
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This parameter can be a value of @ref DMA_ADDR_CTRL_T */
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enum DMA_ADDR_CTRL_T dst_addr_ctrl; /*!< Specifies the destination address control mode.
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This parameter can be a value of @ref DMA_ADDR_CTRL_T */
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enum DMA_REQ_SEL_T src_req_sel; /*!< Specifies the source request dev
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This parameter can be a value of @ref DMA_REQ_SEL_T */
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enum DMA_REQ_SEL_T dst_req_sel; /*!< Specifies the destination request dev
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This parameter can be a value of @ref DMA_REQ_SEL_T*/
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};
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struct DMA_HANDLE_T
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{
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DMA_TypeDef *const base; /*!< DMA registers base address */
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const IRQn_Type irq; /*!< DMA interrupt number */
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drv_callback_t callback[DMA_CH_NUM]; /*!< Callback function provided by the user */
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drv_callback_t abort_callback[DMA_CH_NUM]; /*!< DMA abort callback function provided by the user */
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};
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Function for initializing the DMA.
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*
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* @param[in] ch Enables the specified DMA channel
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* @param[in] config Pointer to a DMA_CH_CFG_T structure that contains the configuration information for DMA.
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* @return
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* @arg DEV_ERROR error id
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* @arg DEV_OK Operation is successful
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*/
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int dma_open(enum DMA_CH_T ch, struct DMA_CH_CFG_T *config);
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/**
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* @brief Function for uninitializing the DMA.
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*
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* @param[in] ch Disables the specified DMA channel
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* @return
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* @arg DEV_ERROR error id
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* @arg DEV_OK Operation is successful
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*/
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int dma_close(enum DMA_CH_T ch);
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/**
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* @brief Starts the DMA transfer.
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*
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* @param[in] ch Specifies the DMA channel
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* @param[in] src_addr The source memory Buffer address
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* @param[out] dst_addr The destination memory Buffer address
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* @param[in] size The length of data to be transferred from source to destination
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* @param[in] callback Callback function provided by the user.
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* @return
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* @arg DEV_ERROR error id
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* @arg DEV_BUSY DMA process is ongoing
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* @arg DEV_OK Operation is successful
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*/
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int dma_transfer(enum DMA_CH_T ch, void *src_addr, void *dst_addr, uint32_t size, drv_callback_t callback);
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/**
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* @brief Stop the DMA transfer.
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*
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* @param[in] ch Specifies the DMA channel
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* @param[in] callback Callback function provided by the user.
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* @note If the dma channel is idle, this abort operation is a no-op and the callback function will not be called.
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* @return
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* @arg DEV_ERROR error id
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* @arg DEV_OK Operation is successful
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*/
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int dma_abort(enum DMA_CH_T ch, drv_callback_t callback);
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/**
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* @brief Force stop DMA transfer.
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*
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* @param[in] ch Specifies the DMA channel
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* @param[in] callback Callback function provided by the user.
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* @note This function will force clear any pending DMA interrupt requests.
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*/
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void dma_force_abort(enum DMA_CH_T ch, drv_callback_t callback);
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/**
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* @brief Function for Interrupt handler for DMA.
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*/
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void DMA_IRQHandler(void);
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/**
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* @brief Function for return cndtr for DMA of uart1 rx.
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*/
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uint32_t get_uart1_dma_cndtr(void);
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/**
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* @brief Function for return cndtr for DMA of uart0 rx.
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*/
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uint32_t get_uart0_dma_cndtr(void);
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#ifdef __cplusplus
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}
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#endif
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/**
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* @}
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*/
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#endif /* MK_DMA_H_ */
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