/**
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******************************************************************************
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* @file stm32f4xx_ll_pwr.h
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* @author MCD Application Team
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* @brief Header file of PWR LL module.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F4xx_LL_PWR_H
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#define __STM32F4xx_LL_PWR_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f4xx.h"
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/** @addtogroup STM32F4xx_LL_Driver
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* @{
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*/
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#if defined(PWR)
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/** @defgroup PWR_LL PWR
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* @{
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*/
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/* Private types -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private constants ---------------------------------------------------------*/
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/* Private macros ------------------------------------------------------------*/
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/* Exported types ------------------------------------------------------------*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
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* @{
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*/
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/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
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* @brief Flags defines which can be used with LL_PWR_WriteReg function
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* @{
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*/
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#define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */
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#define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */
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/**
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* @}
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*/
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/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
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* @brief Flags defines which can be used with LL_PWR_ReadReg function
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* @{
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*/
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#define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */
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#define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */
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#define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */
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#define LL_PWR_CSR_VOS PWR_CSR_VOSRDY /*!< Voltage scaling select flag */
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#if defined(PWR_CSR_EWUP)
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#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP /*!< Enable WKUP pin */
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#elif defined(PWR_CSR_EWUP1)
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#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1 /*!< Enable WKUP pin 1 */
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#endif /* PWR_CSR_EWUP */
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#if defined(PWR_CSR_EWUP2)
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#define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2 /*!< Enable WKUP pin 2 */
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#endif /* PWR_CSR_EWUP2 */
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#if defined(PWR_CSR_EWUP3)
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#define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3 /*!< Enable WKUP pin 3 */
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#endif /* PWR_CSR_EWUP3 */
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/**
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* @}
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*/
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/** @defgroup PWR_LL_EC_REGU_VOLTAGE Regulator Voltage
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* @{
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*/
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#if defined(PWR_CR_VOS_0)
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#define LL_PWR_REGU_VOLTAGE_SCALE3 (PWR_CR_VOS_0)
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#define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR_VOS_1)
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#define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR_VOS_0 | PWR_CR_VOS_1) /* The SCALE1 is not available for STM32F401xx devices */
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#else
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#define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR_VOS)
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#define LL_PWR_REGU_VOLTAGE_SCALE2 0x00000000U
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#endif /* PWR_CR_VOS_0 */
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/**
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* @}
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*/
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/** @defgroup PWR_LL_EC_MODE_PWR Mode Power
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* @{
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*/
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#define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */
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#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */
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#if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)
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#define LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (PWR_CR_MRUDS | PWR_CR_FPDS) /*!< Enter Stop mode (with main Regulator in under-drive mode) when the CPU enters deepsleep */
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#define LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_FPDS) /*!< Enter Stop mode (with low power Regulator in under-drive mode) when the CPU enters deepsleep */
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#endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */
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#if defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)
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#define LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (PWR_CR_MRLVDS | PWR_CR_FPDS) /*!< Enter Stop mode (with main Regulator in Deep Sleep mode) when the CPU enters deepsleep */
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#define LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (PWR_CR_LPDS | PWR_CR_LPLVDS | PWR_CR_FPDS) /*!< Enter Stop mode (with low power Regulator in Deep Sleep mode) when the CPU enters deepsleep */
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#endif /* PWR_CR_MRLVDS && PWR_CR_LPLVDS && PWR_CR_FPDS */
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#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */
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/**
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* @}
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*/
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/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode
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* @{
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*/
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#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */
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#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */
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/**
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* @}
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*/
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/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
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* @{
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*/
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#define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 2.2 V */
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#define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.3 V */
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#define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.4 V */
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#define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */
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#define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.6 V */
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#define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.7 V */
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#define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 2.8 V */
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#define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold detected by PVD 2.9 V */
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/**
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* @}
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*/
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/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins
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* @{
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*/
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#if defined(PWR_CSR_EWUP)
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#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP) /*!< WKUP pin : PA0 */
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#endif /* PWR_CSR_EWUP */
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#if defined(PWR_CSR_EWUP1)
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#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1) /*!< WKUP pin 1 : PA0 */
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#endif /* PWR_CSR_EWUP1 */
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#if defined(PWR_CSR_EWUP2)
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#define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2) /*!< WKUP pin 2 : PC0 or PC13 according to device */
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#endif /* PWR_CSR_EWUP2 */
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#if defined(PWR_CSR_EWUP3)
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#define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PC1 */
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#endif /* PWR_CSR_EWUP3 */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
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* @{
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*/
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/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
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* @{
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*/
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/**
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* @brief Write a value in PWR register
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* @param __REG__ Register to be written
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* @param __VALUE__ Value to be written in the register
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* @retval None
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*/
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#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
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/**
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* @brief Read a value in PWR register
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* @param __REG__ Register to be read
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* @retval Register value
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*/
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#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported functions --------------------------------------------------------*/
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/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
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* @{
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*/
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/** @defgroup PWR_LL_EF_Configuration Configuration
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* @{
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*/
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#if defined(PWR_CR_FISSR)
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/**
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* @brief Enable FLASH interface STOP while system Run is ON
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* @rmtoll CR FISSR LL_PWR_EnableFLASHInterfaceSTOP
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* @note This mode is enabled only with STOP low power mode.
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* @retval None
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*/
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__STATIC_INLINE void LL_PWR_EnableFLASHInterfaceSTOP(void)
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{
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SET_BIT(PWR->CR, PWR_CR_FISSR);
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}
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/**
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* @brief Disable FLASH Interface STOP while system Run is ON
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* @rmtoll CR FISSR LL_PWR_DisableFLASHInterfaceSTOP
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* @retval None
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*/
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__STATIC_INLINE void LL_PWR_DisableFLASHInterfaceSTOP(void)
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{
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CLEAR_BIT(PWR->CR, PWR_CR_FISSR);
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}
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/**
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* @brief Check if FLASH Interface STOP while system Run feature is enabled
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* @rmtoll CR FISSR LL_PWR_IsEnabledFLASHInterfaceSTOP
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_PWR_IsEnabledFLASHInterfaceSTOP(void)
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{
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return (READ_BIT(PWR->CR, PWR_CR_FISSR) == (PWR_CR_FISSR));
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}
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#endif /* PWR_CR_FISSR */
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#if defined(PWR_CR_FMSSR)
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/**
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* @brief Enable FLASH Memory STOP while system Run is ON
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* @rmtoll CR FMSSR LL_PWR_EnableFLASHMemorySTOP
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* @note This mode is enabled only with STOP low power mode.
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* @retval None
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*/
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__STATIC_INLINE void LL_PWR_EnableFLASHMemorySTOP(void)
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{
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SET_BIT(PWR->CR, PWR_CR_FMSSR);
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}
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/**
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* @brief Disable FLASH Memory STOP while system Run is ON
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* @rmtoll CR FMSSR LL_PWR_DisableFLASHMemorySTOP
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* @retval None
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*/
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__STATIC_INLINE void LL_PWR_DisableFLASHMemorySTOP(void)
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{
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CLEAR_BIT(PWR->CR, PWR_CR_FMSSR);
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}
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/**
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* @brief Check if FLASH Memory STOP while system Run feature is enabled
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* @rmtoll CR FMSSR LL_PWR_IsEnabledFLASHMemorySTOP
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_PWR_IsEnabledFLASHMemorySTOP(void)
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{
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return (READ_BIT(PWR->CR, PWR_CR_FMSSR) == (PWR_CR_FMSSR));
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}
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#endif /* PWR_CR_FMSSR */
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#if defined(PWR_CR_UDEN)
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/**
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* @brief Enable Under Drive Mode
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* @rmtoll CR UDEN LL_PWR_EnableUnderDriveMode
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* @note This mode is enabled only with STOP low power mode.
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* In this mode, the 1.2V domain is preserved in reduced leakage mode. This
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* mode is only available when the main Regulator or the low power Regulator
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* is in low voltage mode.
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* @note If the Under-drive mode was enabled, it is automatically disabled after
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* exiting Stop mode.
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* When the voltage Regulator operates in Under-drive mode, an additional
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* startup delay is induced when waking up from Stop mode.
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* @retval None
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*/
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__STATIC_INLINE void LL_PWR_EnableUnderDriveMode(void)
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{
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SET_BIT(PWR->CR, PWR_CR_UDEN);
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}
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/**
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* @brief Disable Under Drive Mode
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* @rmtoll CR UDEN LL_PWR_DisableUnderDriveMode
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* @retval None
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*/
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__STATIC_INLINE void LL_PWR_DisableUnderDriveMode(void)
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{
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CLEAR_BIT(PWR->CR, PWR_CR_UDEN);
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}
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/**
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* @brief Check if Under Drive Mode is enabled
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* @rmtoll CR UDEN LL_PWR_IsEnabledUnderDriveMode
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_PWR_IsEnabledUnderDriveMode(void)
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{
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return (READ_BIT(PWR->CR, PWR_CR_UDEN) == (PWR_CR_UDEN));
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}
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#endif /* PWR_CR_UDEN */
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#if defined(PWR_CR_ODSWEN)
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/**
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* @brief Enable Over drive switching
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* @rmtoll CR ODSWEN LL_PWR_EnableOverDriveSwitching
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* @retval None
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*/
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__STATIC_INLINE void LL_PWR_EnableOverDriveSwitching(void)
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{
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SET_BIT(PWR->CR, PWR_CR_ODSWEN);
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}
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/**
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* @brief Disable Over drive switching
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* @rmtoll CR ODSWEN LL_PWR_DisableOverDriveSwitching
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* @retval None
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*/
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__STATIC_INLINE void LL_PWR_DisableOverDriveSwitching(void)
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{
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CLEAR_BIT(PWR->CR, PWR_CR_ODSWEN);
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}
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/**
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* @brief Check if Over drive switching is enabled
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* @rmtoll CR ODSWEN LL_PWR_IsEnabledOverDriveSwitching
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveSwitching(void)
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{
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return (READ_BIT(PWR->CR, PWR_CR_ODSWEN) == (PWR_CR_ODSWEN));
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}
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#endif /* PWR_CR_ODSWEN */
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#if defined(PWR_CR_ODEN)
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/**
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* @brief Enable Over drive Mode
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* @rmtoll CR ODEN LL_PWR_EnableOverDriveMode
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* @retval None
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*/
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__STATIC_INLINE void LL_PWR_EnableOverDriveMode(void)
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{
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SET_BIT(PWR->CR, PWR_CR_ODEN);
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}
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/**
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* @brief Disable Over drive Mode
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* @rmtoll CR ODEN LL_PWR_DisableOverDriveMode
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* @retval None
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*/
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__STATIC_INLINE void LL_PWR_DisableOverDriveMode(void)
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{
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CLEAR_BIT(PWR->CR, PWR_CR_ODEN);
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}
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/**
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* @brief Check if Over drive switching is enabled
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* @rmtoll CR ODEN LL_PWR_IsEnabledOverDriveMode
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveMode(void)
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{
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return (READ_BIT(PWR->CR, PWR_CR_ODEN) == (PWR_CR_ODEN));
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}
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#endif /* PWR_CR_ODEN */
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#if defined(PWR_CR_MRUDS)
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/**
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* @brief Enable Main Regulator in deepsleep under-drive Mode
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* @rmtoll CR MRUDS LL_PWR_EnableMainRegulatorDeepSleepUDMode
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* @retval None
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*/
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__STATIC_INLINE void LL_PWR_EnableMainRegulatorDeepSleepUDMode(void)
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{
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SET_BIT(PWR->CR, PWR_CR_MRUDS);
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}
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/**
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* @brief Disable Main Regulator in deepsleep under-drive Mode
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* @rmtoll CR MRUDS LL_PWR_DisableMainRegulatorDeepSleepUDMode
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* @retval None
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*/
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__STATIC_INLINE void LL_PWR_DisableMainRegulatorDeepSleepUDMode(void)
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{
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CLEAR_BIT(PWR->CR, PWR_CR_MRUDS);
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}
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/**
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* @brief Check if Main Regulator in deepsleep under-drive Mode is enabled
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* @rmtoll CR MRUDS LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode(void)
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{
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return (READ_BIT(PWR->CR, PWR_CR_MRUDS) == (PWR_CR_MRUDS));
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}
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#endif /* PWR_CR_MRUDS */
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#if defined(PWR_CR_LPUDS)
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/**
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* @brief Enable Low Power Regulator in deepsleep under-drive Mode
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* @rmtoll CR LPUDS LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode
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* @retval None
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*/
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__STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode(void)
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{
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SET_BIT(PWR->CR, PWR_CR_LPUDS);
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}
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/**
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* @brief Disable Low Power Regulator in deepsleep under-drive Mode
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* @rmtoll CR LPUDS LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode
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* @retval None
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*/
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__STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode(void)
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{
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CLEAR_BIT(PWR->CR, PWR_CR_LPUDS);
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}
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/**
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* @brief Check if Low Power Regulator in deepsleep under-drive Mode is enabled
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* @rmtoll CR LPUDS LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode(void)
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{
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return (READ_BIT(PWR->CR, PWR_CR_LPUDS) == (PWR_CR_LPUDS));
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}
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#endif /* PWR_CR_LPUDS */
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#if defined(PWR_CR_MRLVDS)
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/**
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* @brief Enable Main Regulator low voltage Mode
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* @rmtoll CR MRLVDS LL_PWR_EnableMainRegulatorLowVoltageMode
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* @retval None
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*/
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__STATIC_INLINE void LL_PWR_EnableMainRegulatorLowVoltageMode(void)
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{
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SET_BIT(PWR->CR, PWR_CR_MRLVDS);
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}
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/**
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* @brief Disable Main Regulator low voltage Mode
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* @rmtoll CR MRLVDS LL_PWR_DisableMainRegulatorLowVoltageMode
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* @retval None
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*/
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__STATIC_INLINE void LL_PWR_DisableMainRegulatorLowVoltageMode(void)
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{
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CLEAR_BIT(PWR->CR, PWR_CR_MRLVDS);
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}
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/**
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* @brief Check if Main Regulator low voltage Mode is enabled
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* @rmtoll CR MRLVDS LL_PWR_IsEnabledMainRegulatorLowVoltageMode
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorLowVoltageMode(void)
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{
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return (READ_BIT(PWR->CR, PWR_CR_MRLVDS) == (PWR_CR_MRLVDS));
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}
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#endif /* PWR_CR_MRLVDS */
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#if defined(PWR_CR_LPLVDS)
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/**
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* @brief Enable Low Power Regulator low voltage Mode
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* @rmtoll CR LPLVDS LL_PWR_EnableLowPowerRegulatorLowVoltageMode
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* @retval None
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*/
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__STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorLowVoltageMode(void)
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{
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SET_BIT(PWR->CR, PWR_CR_LPLVDS);
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}
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/**
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* @brief Disable Low Power Regulator low voltage Mode
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* @rmtoll CR LPLVDS LL_PWR_DisableLowPowerRegulatorLowVoltageMode
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* @retval None
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*/
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__STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorLowVoltageMode(void)
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{
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CLEAR_BIT(PWR->CR, PWR_CR_LPLVDS);
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}
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/**
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* @brief Check if Low Power Regulator low voltage Mode is enabled
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* @rmtoll CR LPLVDS LL_PWR_IsEnabledLowPowerRegulatorLowVoltageMode
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorLowVoltageMode(void)
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{
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return (READ_BIT(PWR->CR, PWR_CR_LPLVDS) == (PWR_CR_LPLVDS));
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}
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#endif /* PWR_CR_LPLVDS */
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/**
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* @brief Set the main internal Regulator output voltage
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* @rmtoll CR VOS LL_PWR_SetRegulVoltageScaling
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* @param VoltageScaling This parameter can be one of the following values:
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* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 (*)
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* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
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* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
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* (*) LL_PWR_REGU_VOLTAGE_SCALE1 is not available for STM32F401xx devices
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* @retval None
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*/
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__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
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{
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MODIFY_REG(PWR->CR, PWR_CR_VOS, VoltageScaling);
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}
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/**
|
* @brief Get the main internal Regulator output voltage
|
* @rmtoll CR VOS LL_PWR_GetRegulVoltageScaling
|
* @retval Returned value can be one of the following values:
|
* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 (*)
|
* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
|
* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
|
* (*) LL_PWR_REGU_VOLTAGE_SCALE1 is not available for STM32F401xx devices
|
*/
|
__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
|
{
|
return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_VOS));
|
}
|
/**
|
* @brief Enable the Flash Power Down in Stop Mode
|
* @rmtoll CR FPDS LL_PWR_EnableFlashPowerDown
|
* @retval None
|
*/
|
__STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void)
|
{
|
SET_BIT(PWR->CR, PWR_CR_FPDS);
|
}
|
|
/**
|
* @brief Disable the Flash Power Down in Stop Mode
|
* @rmtoll CR FPDS LL_PWR_DisableFlashPowerDown
|
* @retval None
|
*/
|
__STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void)
|
{
|
CLEAR_BIT(PWR->CR, PWR_CR_FPDS);
|
}
|
|
/**
|
* @brief Check if the Flash Power Down in Stop Mode is enabled
|
* @rmtoll CR FPDS LL_PWR_IsEnabledFlashPowerDown
|
* @retval State of bit (1 or 0).
|
*/
|
__STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void)
|
{
|
return (READ_BIT(PWR->CR, PWR_CR_FPDS) == (PWR_CR_FPDS));
|
}
|
|
/**
|
* @brief Enable access to the backup domain
|
* @rmtoll CR DBP LL_PWR_EnableBkUpAccess
|
* @retval None
|
*/
|
__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
|
{
|
SET_BIT(PWR->CR, PWR_CR_DBP);
|
}
|
|
/**
|
* @brief Disable access to the backup domain
|
* @rmtoll CR DBP LL_PWR_DisableBkUpAccess
|
* @retval None
|
*/
|
__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
|
{
|
CLEAR_BIT(PWR->CR, PWR_CR_DBP);
|
}
|
|
/**
|
* @brief Check if the backup domain is enabled
|
* @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess
|
* @retval State of bit (1 or 0).
|
*/
|
__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
|
{
|
return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
|
}
|
/**
|
* @brief Enable the backup Regulator
|
* @rmtoll CSR BRE LL_PWR_EnableBkUpRegulator
|
* @note The BRE bit of the PWR_CSR register is protected against parasitic write access.
|
* The LL_PWR_EnableBkUpAccess() must be called before using this API.
|
* @retval None
|
*/
|
__STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void)
|
{
|
SET_BIT(PWR->CSR, PWR_CSR_BRE);
|
}
|
|
/**
|
* @brief Disable the backup Regulator
|
* @rmtoll CSR BRE LL_PWR_DisableBkUpRegulator
|
* @note The BRE bit of the PWR_CSR register is protected against parasitic write access.
|
* The LL_PWR_EnableBkUpAccess() must be called before using this API.
|
* @retval None
|
*/
|
__STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void)
|
{
|
CLEAR_BIT(PWR->CSR, PWR_CSR_BRE);
|
}
|
|
/**
|
* @brief Check if the backup Regulator is enabled
|
* @rmtoll CSR BRE LL_PWR_IsEnabledBkUpRegulator
|
* @retval State of bit (1 or 0).
|
*/
|
__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void)
|
{
|
return (READ_BIT(PWR->CSR, PWR_CSR_BRE) == (PWR_CSR_BRE));
|
}
|
|
/**
|
* @brief Set voltage Regulator mode during deep sleep mode
|
* @rmtoll CR LPDS LL_PWR_SetRegulModeDS
|
* @param RegulMode This parameter can be one of the following values:
|
* @arg @ref LL_PWR_REGU_DSMODE_MAIN
|
* @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
|
* @retval None
|
*/
|
__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
|
{
|
MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
|
}
|
|
/**
|
* @brief Get voltage Regulator mode during deep sleep mode
|
* @rmtoll CR LPDS LL_PWR_GetRegulModeDS
|
* @retval Returned value can be one of the following values:
|
* @arg @ref LL_PWR_REGU_DSMODE_MAIN
|
* @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
|
*/
|
__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
|
{
|
return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
|
}
|
|
/**
|
* @brief Set Power Down mode when CPU enters deepsleep
|
* @rmtoll CR PDDS LL_PWR_SetPowerMode\n
|
* @rmtoll CR MRUDS LL_PWR_SetPowerMode\n
|
* @rmtoll CR LPUDS LL_PWR_SetPowerMode\n
|
* @rmtoll CR FPDS LL_PWR_SetPowerMode\n
|
* @rmtoll CR MRLVDS LL_PWR_SetPowerMode\n
|
* @rmtoll CR LPlVDS LL_PWR_SetPowerMode\n
|
* @rmtoll CR FPDS LL_PWR_SetPowerMode\n
|
* @rmtoll CR LPDS LL_PWR_SetPowerMode
|
* @param PDMode This parameter can be one of the following values:
|
* @arg @ref LL_PWR_MODE_STOP_MAINREGU
|
* @arg @ref LL_PWR_MODE_STOP_LPREGU
|
* @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (*)
|
* @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (*)
|
* @arg @ref LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (*)
|
* @arg @ref LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (*)
|
*
|
* (*) not available on all devices
|
* @arg @ref LL_PWR_MODE_STANDBY
|
* @retval None
|
*/
|
__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
|
{
|
#if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)
|
MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPUDS | PWR_CR_MRUDS), PDMode);
|
#elif defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)
|
MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPLVDS | PWR_CR_MRLVDS), PDMode);
|
#else
|
MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode);
|
#endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */
|
}
|
|
/**
|
* @brief Get Power Down mode when CPU enters deepsleep
|
* @rmtoll CR PDDS LL_PWR_GetPowerMode\n
|
* @rmtoll CR MRUDS LL_PWR_GetPowerMode\n
|
* @rmtoll CR LPUDS LL_PWR_GetPowerMode\n
|
* @rmtoll CR FPDS LL_PWR_GetPowerMode\n
|
* @rmtoll CR MRLVDS LL_PWR_GetPowerMode\n
|
* @rmtoll CR LPLVDS LL_PWR_GetPowerMode\n
|
* @rmtoll CR FPDS LL_PWR_GetPowerMode\n
|
* @rmtoll CR LPDS LL_PWR_GetPowerMode
|
* @retval Returned value can be one of the following values:
|
* @arg @ref LL_PWR_MODE_STOP_MAINREGU
|
* @arg @ref LL_PWR_MODE_STOP_LPREGU
|
* @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (*)
|
* @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (*)
|
* @arg @ref LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (*)
|
* @arg @ref LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (*)
|
*
|
* (*) not available on all devices
|
* @arg @ref LL_PWR_MODE_STANDBY
|
*/
|
__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
|
{
|
#if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)
|
return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPUDS | PWR_CR_MRUDS)));
|
#elif defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)
|
return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPLVDS | PWR_CR_MRLVDS)));
|
#else
|
return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS)));
|
#endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */
|
}
|
|
/**
|
* @brief Configure the voltage threshold detected by the Power Voltage Detector
|
* @rmtoll CR PLS LL_PWR_SetPVDLevel
|
* @param PVDLevel This parameter can be one of the following values:
|
* @arg @ref LL_PWR_PVDLEVEL_0
|
* @arg @ref LL_PWR_PVDLEVEL_1
|
* @arg @ref LL_PWR_PVDLEVEL_2
|
* @arg @ref LL_PWR_PVDLEVEL_3
|
* @arg @ref LL_PWR_PVDLEVEL_4
|
* @arg @ref LL_PWR_PVDLEVEL_5
|
* @arg @ref LL_PWR_PVDLEVEL_6
|
* @arg @ref LL_PWR_PVDLEVEL_7
|
* @retval None
|
*/
|
__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
|
{
|
MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
|
}
|
|
/**
|
* @brief Get the voltage threshold detection
|
* @rmtoll CR PLS LL_PWR_GetPVDLevel
|
* @retval Returned value can be one of the following values:
|
* @arg @ref LL_PWR_PVDLEVEL_0
|
* @arg @ref LL_PWR_PVDLEVEL_1
|
* @arg @ref LL_PWR_PVDLEVEL_2
|
* @arg @ref LL_PWR_PVDLEVEL_3
|
* @arg @ref LL_PWR_PVDLEVEL_4
|
* @arg @ref LL_PWR_PVDLEVEL_5
|
* @arg @ref LL_PWR_PVDLEVEL_6
|
* @arg @ref LL_PWR_PVDLEVEL_7
|
*/
|
__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
|
{
|
return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
|
}
|
|
/**
|
* @brief Enable Power Voltage Detector
|
* @rmtoll CR PVDE LL_PWR_EnablePVD
|
* @retval None
|
*/
|
__STATIC_INLINE void LL_PWR_EnablePVD(void)
|
{
|
SET_BIT(PWR->CR, PWR_CR_PVDE);
|
}
|
|
/**
|
* @brief Disable Power Voltage Detector
|
* @rmtoll CR PVDE LL_PWR_DisablePVD
|
* @retval None
|
*/
|
__STATIC_INLINE void LL_PWR_DisablePVD(void)
|
{
|
CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
|
}
|
|
/**
|
* @brief Check if Power Voltage Detector is enabled
|
* @rmtoll CR PVDE LL_PWR_IsEnabledPVD
|
* @retval State of bit (1 or 0).
|
*/
|
__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
|
{
|
return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
|
}
|
|
/**
|
* @brief Enable the WakeUp PINx functionality
|
* @rmtoll CSR EWUP LL_PWR_EnableWakeUpPin\n
|
* @rmtoll CSR EWUP1 LL_PWR_EnableWakeUpPin\n
|
* @rmtoll CSR EWUP2 LL_PWR_EnableWakeUpPin\n
|
* @rmtoll CSR EWUP3 LL_PWR_EnableWakeUpPin
|
* @param WakeUpPin This parameter can be one of the following values:
|
* @arg @ref LL_PWR_WAKEUP_PIN1
|
* @arg @ref LL_PWR_WAKEUP_PIN2 (*)
|
* @arg @ref LL_PWR_WAKEUP_PIN3 (*)
|
*
|
* (*) not available on all devices
|
* @retval None
|
*/
|
__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
|
{
|
SET_BIT(PWR->CSR, WakeUpPin);
|
}
|
|
/**
|
* @brief Disable the WakeUp PINx functionality
|
* @rmtoll CSR EWUP LL_PWR_DisableWakeUpPin\n
|
* @rmtoll CSR EWUP1 LL_PWR_DisableWakeUpPin\n
|
* @rmtoll CSR EWUP2 LL_PWR_DisableWakeUpPin\n
|
* @rmtoll CSR EWUP3 LL_PWR_DisableWakeUpPin
|
* @param WakeUpPin This parameter can be one of the following values:
|
* @arg @ref LL_PWR_WAKEUP_PIN1
|
* @arg @ref LL_PWR_WAKEUP_PIN2 (*)
|
* @arg @ref LL_PWR_WAKEUP_PIN3 (*)
|
*
|
* (*) not available on all devices
|
* @retval None
|
*/
|
__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
|
{
|
CLEAR_BIT(PWR->CSR, WakeUpPin);
|
}
|
|
/**
|
* @brief Check if the WakeUp PINx functionality is enabled
|
* @rmtoll CSR EWUP LL_PWR_IsEnabledWakeUpPin\n
|
* @rmtoll CSR EWUP1 LL_PWR_IsEnabledWakeUpPin\n
|
* @rmtoll CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n
|
* @rmtoll CSR EWUP3 LL_PWR_IsEnabledWakeUpPin
|
* @param WakeUpPin This parameter can be one of the following values:
|
* @arg @ref LL_PWR_WAKEUP_PIN1
|
* @arg @ref LL_PWR_WAKEUP_PIN2 (*)
|
* @arg @ref LL_PWR_WAKEUP_PIN3 (*)
|
*
|
* (*) not available on all devices
|
* @retval State of bit (1 or 0).
|
*/
|
__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
|
{
|
return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
|
}
|
|
|
/**
|
* @}
|
*/
|
|
/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
|
* @{
|
*/
|
|
/**
|
* @brief Get Wake-up Flag
|
* @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU
|
* @retval State of bit (1 or 0).
|
*/
|
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
|
{
|
return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
|
}
|
|
/**
|
* @brief Get Standby Flag
|
* @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB
|
* @retval State of bit (1 or 0).
|
*/
|
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
|
{
|
return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
|
}
|
|
/**
|
* @brief Get Backup Regulator ready Flag
|
* @rmtoll CSR BRR LL_PWR_IsActiveFlag_BRR
|
* @retval State of bit (1 or 0).
|
*/
|
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void)
|
{
|
return (READ_BIT(PWR->CSR, PWR_CSR_BRR) == (PWR_CSR_BRR));
|
}
|
/**
|
* @brief Indicate whether VDD voltage is below the selected PVD threshold
|
* @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO
|
* @retval State of bit (1 or 0).
|
*/
|
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
|
{
|
return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
|
}
|
|
/**
|
* @brief Indicate whether the Regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level
|
* @rmtoll CSR VOS LL_PWR_IsActiveFlag_VOS
|
* @retval State of bit (1 or 0).
|
*/
|
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
|
{
|
return (READ_BIT(PWR->CSR, LL_PWR_CSR_VOS) == (LL_PWR_CSR_VOS));
|
}
|
#if defined(PWR_CR_ODEN)
|
/**
|
* @brief Indicate whether the Over-Drive mode is ready or not
|
* @rmtoll CSR ODRDY LL_PWR_IsActiveFlag_OD
|
* @retval State of bit (1 or 0).
|
*/
|
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_OD(void)
|
{
|
return (READ_BIT(PWR->CSR, PWR_CSR_ODRDY) == (PWR_CSR_ODRDY));
|
}
|
#endif /* PWR_CR_ODEN */
|
|
#if defined(PWR_CR_ODSWEN)
|
/**
|
* @brief Indicate whether the Over-Drive mode switching is ready or not
|
* @rmtoll CSR ODSWRDY LL_PWR_IsActiveFlag_ODSW
|
* @retval State of bit (1 or 0).
|
*/
|
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ODSW(void)
|
{
|
return (READ_BIT(PWR->CSR, PWR_CSR_ODSWRDY) == (PWR_CSR_ODSWRDY));
|
}
|
#endif /* PWR_CR_ODSWEN */
|
|
#if defined(PWR_CR_UDEN)
|
/**
|
* @brief Indicate whether the Under-Drive mode is ready or not
|
* @rmtoll CSR UDRDY LL_PWR_IsActiveFlag_UD
|
* @retval State of bit (1 or 0).
|
*/
|
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_UD(void)
|
{
|
return (READ_BIT(PWR->CSR, PWR_CSR_UDRDY) == (PWR_CSR_UDRDY));
|
}
|
#endif /* PWR_CR_UDEN */
|
/**
|
* @brief Clear Standby Flag
|
* @rmtoll CR CSBF LL_PWR_ClearFlag_SB
|
* @retval None
|
*/
|
__STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
|
{
|
SET_BIT(PWR->CR, PWR_CR_CSBF);
|
}
|
|
/**
|
* @brief Clear Wake-up Flags
|
* @rmtoll CR CWUF LL_PWR_ClearFlag_WU
|
* @retval None
|
*/
|
__STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
|
{
|
SET_BIT(PWR->CR, PWR_CR_CWUF);
|
}
|
#if defined(PWR_CSR_UDRDY)
|
/**
|
* @brief Clear Under-Drive ready Flag
|
* @rmtoll CSR UDRDY LL_PWR_ClearFlag_UD
|
* @retval None
|
*/
|
__STATIC_INLINE void LL_PWR_ClearFlag_UD(void)
|
{
|
WRITE_REG(PWR->CSR, PWR_CSR_UDRDY);
|
}
|
#endif /* PWR_CSR_UDRDY */
|
|
/**
|
* @}
|
*/
|
|
#if defined(USE_FULL_LL_DRIVER)
|
/** @defgroup PWR_LL_EF_Init De-initialization function
|
* @{
|
*/
|
ErrorStatus LL_PWR_DeInit(void);
|
/**
|
* @}
|
*/
|
#endif /* USE_FULL_LL_DRIVER */
|
|
/**
|
* @}
|
*/
|
|
/**
|
* @}
|
*/
|
|
#endif /* defined(PWR) */
|
|
/**
|
* @}
|
*/
|
|
#ifdef __cplusplus
|
}
|
#endif
|
|
#endif /* __STM32F4xx_LL_PWR_H */
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
