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Component: ARM Compiler 6.14 Tool: armclang [5db06c00] ../../../../../drivers\mk_calib.c D:\project chen\UWB Double Line\new\SDKs\SDK_V0.6.2\mk8000 sdk\sdk_v0.6.2_r4\boards\mk8000_evk\uwb_examples\uwb_simple_example_ss_twr_Tag\keil unsigned int CLOCK_GPIO CLOCK_SPI0 CLOCK_SPI1 CLOCK_LSP CLOCK_DMA CLOCK_MAC CLOCK_UART0 CLOCK_UART1 CLOCK_I2C CLOCK_EFUSE CLOCK_TIMER0 CLOCK_TIMER1 CLOCK_TIMER2 CLOCK_TIMER3 CLOCK_WDT CLOCK_RTC CLOCK_PWM CLOCK_ADC CLOCK_TRNG CLOCK_FLASH_CTRL CLOCK_AES CLOCK_CALIB CLOCK_RX CLOCK_TX CLOCK_PHY_TIMER CLOCK_GATE_T RESET_MODULE_GPIO RESET_MODULE_SPI0 RESET_MODULE_SPI1 RESET_MODULE_LSP RESET_MODULE_DMA RESET_MODULE_MAC RESET_MODULE_UART0 RESET_MODULE_UART1 RESET_MODULE_I2C RESET_MODULE_EFUSE RESET_MODULE_TIMER0 RESET_MODULE_TIMER1 RESET_MODULE_DUAL_TIMER RESET_MODULE_WDT RESET_MODULE_RTC RESET_MODULE_PWM RESET_MODULE_ADC RESET_MODULE_TRNG RESET_MODULE_FLASH_CTRL RESET_MODULE_AES RESET_MODULE_CALIB RESET_MODULE_DPRX RESET_MODULE_DPTX RESET_MODULE_SYSREG RESET_MODULE_REBOOT RESET_MODULE_LOCKUP_EN RESET_MODULE_T BOARD_LOAD_CAP BOARD_LOCAL_SHORT_ADDR BOARD_PEER_SHORT_ADDR BOARD_RANGING_SESSION_ID BOARD_TX_POWER_FCC_LEVEL BOARD_ANT_DELAYS BOARD_DEV_ROLE BOARD_DEV_ROLE_IDX BOARD_PDOA_DELAYS BOARD_PDOA_GAINS BOARD_PDOA_ANT_SPACE BOARD_PDOA_OFFSETS BOARD_X32K_LOAD_CAP BOARD_NVM_ITEM_ID_T TRACE_MODULE_MAC TRACE_MODULE_PHY TRACE_MODULE_DRIVER TRACE_MODULE_APP TRACE_MODULE_UWB TRACE_MODULE_UCI TRACE_MODULE_TEST TRACE_MODULE_BOOT TRACE_MODULE_OS TRACE_MODULE_FIRA TRACE_MODULE_CCC TRACE_MODULE_SE TRACE_MODULE_SCP03 TRACE_MODULE_NUM TRACE_MODULE_ID_T TRACE_LEVEL_OFF TRACE_LEVEL_ERROR TRACE_LEVEL_WARNING TRACE_LEVEL_INFO TRACE_LEVEL_VERBOSE TRACE_LEVEL_NUM TRACE_LEVEL_T uint32_t unsigned char uint8_t unsigned short uint16_t LOT_ID_0 LOT_ID_1 LOT_WAF_AXIS CHIP_ID DEV_ADDR_LSB DEV_ADDR_MSB SYSTEM_STATUS SYS_RMU SYS_CMU CLK_DIV SYS_CTRL PMU_CTRL0 PMU_CTRL1 PIN_MUX_0 PIN_MUX_1 PIN_MUX_2 WAKEUP_EN WAKEUP_POL XTAL_CFG XTAL32_CFG CAP_DIV_CFG ACMP_CFG BOD_BOR RESET_CAUSE MEM_CFG SYS_TICK_CTRL SHELF_KEY MEM_PG_CTRL RESERVED0 __ARRAY_SIZE_TYPE__ IO_OD IO_DRV IO_EI IO_PDN IO_PUP IO_SLP_OE IO_SLP_OUT IO_SLP_AEN IO_SLP_EI IO_SLP_PDN IO_SLP_PUP RESERVED2 IVREF_ULP REG_DIG IVREF_CP BUCK XTAL_0 XTAL_1 XTAL32 RCO RO REFPLL EFUSE_LDO CLK_STATUS DUM_AO_HI DUM_AO_LO RESERVED3 TRIM0_RD_REG TRIM1_RD_REG TRIM2_RD_REG TRIM3_RD_REG SYSCON_TypeDef calib_xtal38m4_load_cap_set val tmp_val calib_xtal32k_load_cap_set calib_open int calib_close calib_start calib_check calib_chip calib_xtal38m4_load_cap_auto_tune calib_xtal38m4_with_clock_out calib_xtal32k_with_clock_out CALIB_IRQHandler items done x id ppm int32_t ÿÿÿÿ P ÿÿÿÿ P ÿÿÿÿ $ R ÿÿÿÿ 8 H R ÿÿÿÿ r v Q Q ( R ÿÿÿÿ ê ú T ÿÿÿÿ P ÿÿÿÿ
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. î 2 î ? õ M î Q î ^ õ i ï m ï x õ õ ð ð õ £ õ ñ ± ñ · ? À õ Ä Ï Ú õ Þ ê ò î ò ô 9 ý õ õ ó ó & 2 / õ 3 > õ B N ô R ô X - b m ê ê ë ë ì ì í í î $ î ( ï , ï 0 ð 4 ð 8 ñ < ñ @ ò D ò H ó L ó P ô T ô ø ê , ø 0 ë D ø H ì T ø X í d ø h î ø ï ø ð ° ø ´ ñ Ì ø Ð ò ä ø è ó ø ô ì ê ë ì 7 í ] î m ï ð ½ ñ ò < ó u ô .debug_abbrev .text .rel.ARM.exidx.text.calib_xtal32k_with_clock_out .rel.text.calib_xtal32k_with_clock_out .rel.ARM.exidx.text.calib_xtal38m4_with_clock_out .rel.text.calib_xtal38m4_with_clock_out .rel.ARM.exidx.text.calib_start .rel.text.calib_start .comment .rel.ARM.exidx.text.calib_xtal32k_load_cap_set .rel.text.calib_xtal32k_load_cap_set .rel.ARM.exidx.text.calib_xtal38m4_load_cap_set .rel.text.calib_xtal38m4_load_cap_set .ARM.attributes .rel.debug_ranges .debug_str .rel.ARM.exidx.text.CALIB_IRQHandler .rel.ARM.exidx.text.calib_chip .rel.text.calib_chip .rel.debug_info .rel.ARM.exidx.text.calib_open .rel.text.calib_open board_param .rel.ARM.exidx.text.calib_check .rel.text.calib_check .note.GNU-stack trace_printf .rel.ARM.exidx.text.calib_close .rel.text.calib_close .rel.ARM.exidx.text.calib_xtal38m4_load_cap_auto_tune .rel.text.calib_xtal38m4_load_cap_auto_tune .rel.debug_line .rel.debug_frame reset_module clock_disable clock_enable mk_chip_id .rel.debug_loc mk_calib.c .strtab .symtab __arm_cp.4_9 $d.9 __arm_cp.4_8 $t.18 $t.8 __arm_cp.4_7 $d.17 $d.7 __arm_cp.4_6 __arm_cp.4_16 $t.16 $t.6 __arm_cp.4_5 __arm_cp.4_15 $d.15 $d.5 __arm_cp.4_4 __arm_cp.4_14 $t.14 $t.4 .L.str.4 __arm_cp.8_3 __arm_cp.4_3 $d.13 .L.str.3 $d.3 __arm_cp.9_2 __arm_cp.8_2 __arm_cp.4_2 __arm_cp.4_12 $t.12 $t.2 __arm_cp.9_1 __arm_cp.8_1 __arm_cp.7_1 __arm_cp.6_1 __arm_cp.5_1 __arm_cp.4_1 __arm_cp.4_11 $d.11 $t.1 .rodata.str1.1 __arm_cp.9_0 __arm_cp.8_0 __arm_cp.7_0 __arm_cp.6_0 __arm_cp.5_0 __arm_cp.4_0 __arm_cp.3_0 __arm_cp.2_0 __arm_cp.4_10 $t.10 $t.0 ß Ì; 4 i 4 e L0 > J p H F \0 > ý P ù d0 > Ý p \ Ù l0 > ë d ç t0 > Ë p t Ç |0 > ª | ¦ 0 > p 0 > % ¬ ! 0 È > p @ \1 > H ( d1 > ^ p p Z 1 > 9 x ( 5 1 >
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