/******************************************************************************
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* @file MK8000.h
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* @brief CMSIS Cortex-M0 Core
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* Peripheral Access Layer Header File for
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* Device MK8000
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* @version V5.00
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* @date 10. January 2020
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******************************************************************************/
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/*
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* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef MK8000_H
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#define MK8000_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @mainpage MK8000 SDK APIs User Guide
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*
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* @section Introduction
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*
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* MK8000 is a single chip, low power, high-performance UWB SoC platform. It integrates an IEEE802.15.4z
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* compliant radio, PHY and MAC, and provides a single-chip solution for FiRa and CCC compliant applications.
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* The integrated 32-bit ARM Cortex-M0 MCU together with LSP, on-chip memory, as well as lots of digital and
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* analog peripherals provides feasibility for many varieties of UWB products.
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*
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* MK8000 is a true SoC platform, not just a UWB transceiver. An SDK is provided to help the customer to speed up
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* the UWB products development process. The SDK provides example projects for FiRa and CCC applications, as
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* well as ranging and AoA algorithms. These algorithms are implemented based on LSP, which is a dedicated co-processor
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* can speed up many kinds of instructions for location algorithms.
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*
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*
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*
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* @section Modules
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*
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* @ref MK8000_1_Core
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*
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* @ref MK8000_2_System
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*
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* @ref MK8000_3_Peripherals
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*
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* @ref MK8000_4_UWBS
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*
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* @ref MK8000_5_ALGO
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*
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* @ref MK8000_6_Examples
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*
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*
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*
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* \image html MK_logo.png
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*/
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/** @defgroup MK8000_1_Core Core
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* @{
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*/
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/** @defgroup MK8000_NVIC NVIC */
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/** @defgroup MK8000_Address_Map Address Map */
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/**
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* @}
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*/
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/** @defgroup MK8000_2_System System
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* @{
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*/
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/** @defgroup MK8000_Calibration Calibration */
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/** @defgroup MK8000_Clock Clock Management Unit (CMU) */
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/** @defgroup MK8000_Common Common */
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/** @defgroup MK8000_MISC Miscellaneous */
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/** @defgroup MK8000_IO IO */
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/** @defgroup MK8000_Power Power Management Unit (PMU) */
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/** @defgroup MK8000_Reset Reset Management Unit (RMU) */
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/** @defgroup MK8000_Trace Trace */
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/**
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* @}
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*/
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/** @defgroup MK8000_3_Peripherals Peripherals
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* @{
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*/
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/** @defgroup MK8000_ACMP ACMP */
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/** @defgroup MK8000_ADC ADC */
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/** @defgroup MK8000_AES AES */
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/** @defgroup MK8000_DMA DMA */
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/** @defgroup MK8000_Dual_Timer Dual Timer */
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/** @defgroup MK8000_eFuse eFuse */
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/** @defgroup MK8000_Flash Flash */
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/** @defgroup MK8000_GPIO GPIO */
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/** @defgroup MK8000_I2C I2C */
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/** @defgroup MK8000_LSP LSP */
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/** @defgroup MK8000_PWM PWM */
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/** @defgroup MK8000_RTC RTC */
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/** @defgroup MK8000_Sleep_Timer Sleep Timer */
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/** @defgroup MK8000_SPI SPI */
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/** @defgroup MK8000_Timer Timer */
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/** @defgroup MK8000_TRNG TRNG */
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/** @defgroup MK8000_UART UART */
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/** @defgroup MK8000_WDT WDT */
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/**
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* @}
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*/
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/** @defgroup MK8000_4_UWBS UWB Subsystem
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* @{
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*/
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/** @defgroup MK8000_UWBS_Low UWB Low Layer API
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* @{
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*/
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/** @defgroup MK8000_UWB UWB Driver */
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/** @defgroup MK8000_MAC MAC */
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/** @defgroup MK8000_PHY PHY */
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/**
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* @}
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*/
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/** @defgroup MK8000_UWBS_High UWB High Layer API
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* @{
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*/
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/** @defgroup MK8000_UWB_SUBSYSTEM UWB Subsystem API */
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/** @defgroup MK8000_UCI_CMDS UCI Commands API */
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/** @defgroup MK8000_FIRA_LIB FIRA LIB API */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/** @defgroup MK8000_5_ALGO Algorithm
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* @{
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*/
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/** @defgroup MK8000_ALGO_AOA AoA */
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/** @defgroup MK8000_ALGO_Ranging Ranging */
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/** @defgroup MK8000_ALGO_KF Post-process Filter */
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/** @defgroup MK8000_ALGO_PDOA PDoA */
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/**
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* @}
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*/
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/** @defgroup MK8000_6_Examples Examples
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* @{
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*/
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/** @defgroup MK8000_Examples_Driver Driver Examples */
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/** @defgroup MK8000_Examples_UWB UWB Examples */
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/**
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* @}
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*/
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/* =========================================================================================================================== */
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/* ================ Interrupt Number Definition ================ */
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/* =========================================================================================================================== */
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/** @addtogroup MK8000_NVIC NVIC
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* @{
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*/
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typedef enum IRQn
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{
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/* ======================================= ARM Cortex-M0 Specific Interrupt Numbers ==================================== */
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/* ToDo: use this Cortex interrupt numbers if your device is a Cortex-M0 / Cortex-M0+ device */
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Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
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NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
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HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
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SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
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PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
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SysTick_IRQn = -1, /*!< -1 System Tick Timer */
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/* =========================================== MK8000 Specific Interrupt Numbers ======================================= */
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BOD_IRQn = 0, /*!< 0 Brown out detection */
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ACMP0_IRQn = 1, /*!< 1 Analog comparator 0 */
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ACMP1_IRQn = 2, /*!< 2 Analog comparator 1 */
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SLEEP_TIMER_IRQn = 3, /*!< 3 Sleep timer */
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MAC_IRQn = 4, /*!< 4 MAC */
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PHY_IRQn = 5, /*!< 5 PHY */
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DMA_IRQn = 6, /*!< 6 DMA */
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GPIO_IRQn = 7, /*!< 7 GPIO */
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AES_IRQn = 8, /*!< 8 AES */
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ADC_IRQn = 9, /*!< 9 ADC */
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TRNG_IRQn = 10, /*!< 10 TRNG */
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FLASH_CTRL_IRQn = 11, /*!< 11 Flash controller */
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LSP_IRQn = 12, /*!< 12 LSP */
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WDT_IRQn = 13, /*!< 13 Watch dog timer */
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RTC_ALARM_IRQn = 14, /*!< 14 RTC alarm */
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RTC_TICK_IRQn = 15, /*!< 15 RTC tick */
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PWM_IRQn = 16, /*!< 16 PWM */
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TIMER0_IRQn = 17, /*!< 17 Timer0 */
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TIMER1_IRQn = 18, /*!< 18 Timer1 */
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TIMER2_IRQn = 19, /*!< 19 Timer2 */
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TIMER3_IRQn = 20, /*!< 20 Timer3 */
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I2C0_IRQn = 21, /*!< 21 I2C */
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SPI0_IRQn = 22, /*!< 22 SPI0 */
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SPI1_IRQn = 23, /*!< 23 SPI1 */
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UART0_IRQn = 24, /*!< 24 UART0 */
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UART1_IRQn = 25, /*!< 25 UART1 */
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CALIB_IRQn = 26, /*!< 26 Calibration */
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RCO32K_CAL_IRQn = 27, /*!< 27 RCO 32K calibration */
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WAKEUP_IRQn = 28, /*!< 28 wakeup */
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PHY_TIMER_IRQn = 29, /*!< 29 PHY timer */
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/* Interrupts 30 .. 31 are left out */
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} IRQn_Type;
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/**
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* @}
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*/
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/* =========================================================================================================================== */
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/* ================ Processor and Core Peripheral Section ================ */
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/* =========================================================================================================================== */
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/* =========================== Configuration of the Arm Cortex-M0 Processor and Core Peripherals
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* =========================== */
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#define __CM0_REV 0x0000U /*!< Core Revision r0p0 */
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/* ToDo: define the correct core features for the MK8000 */
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#define __MPU_PRESENT 0 /*!< Set to 1 if MPU is present */
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#define __VTOR_PRESENT 0 /*!< Set to 1 if VTOR is present */
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#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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#define __FPU_PRESENT 0 /*!< Set to 1 if FPU is present */
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#define __FPU_DP 0 /*!< Set to 1 if FPU is double precision FPU (default is single precision FPU) */
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#define __ICACHE_PRESENT 0 /*!< Set to 1 if I-Cache is present */
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#define __DCACHE_PRESENT 0 /*!< Set to 1 if D-Cache is present */
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#define __DTCM_PRESENT 0 /*!< Set to 1 if DTCM is present */
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#include "core_cm0.h" /*!< Arm Cortex-M0 processor and core peripherals */
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#include "system_MK800X.h" /*!< MK8000 System */
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/* ======================================== Start of section using anonymous unions ======================================== */
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#if defined(__CC_ARM)
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#pragma push
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#pragma anon_unions
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#elif defined(__ICCARM__)
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#pragma language = extended
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#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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#pragma clang diagnostic push
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#pragma clang diagnostic ignored "-Wc11-extensions"
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#pragma clang diagnostic ignored "-Wreserved-id-macro"
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#elif defined(__GNUC__)
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/* anonymous unions are enabled by default */
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#elif defined(__TMS470__)
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/* anonymous unions are enabled by default */
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#elif defined(__TASKING__)
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#pragma warning 586
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#elif defined(__CSMC__)
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/* anonymous unions are enabled by default */
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#else
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#warning Not supported compiler type
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#endif
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/* =========================================================================================================================== */
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/* ================ Device Specific Peripheral Section ================ */
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/* =========================================================================================================================== */
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/* =========================================================================================================================== */
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/* ================ SYSCON ================ */
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/* =========================================================================================================================== */
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/**
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* @brief SYSCON
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*/
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typedef struct
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{
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__IM uint32_t LOT_ID_0; /*!< (0x000) 32LSB of LOT ID */
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__IM uint32_t LOT_ID_1; /*!< (0x004) 32MSB of LOT ID */
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__IM uint32_t LOT_WAF_AXIS; /*!< (0x008) Axis of die on the wafer */
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__IM uint32_t CHIP_ID; /*!< (0x00C) Chip ID */
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__IOM uint32_t DEV_ADDR_LSB; /*!< (0x010) Device address 32 LSB */
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__IOM uint32_t DEV_ADDR_MSB; /*!< (0x014) Device address 32 MSB */
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__IOM uint32_t SYSTEM_STATUS; /*!< (0x018) System top level and radio status program and read back register */
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__IOM uint32_t SYS_RMU; /*!< (0x01C) Reset Control */
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__IOM uint32_t SYS_CMU; /*!< (0x020) Clock Control */
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__IOM uint32_t CLK_DIV; /*!< (0x024) APB Clock Divider */
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__IOM uint32_t SYS_CTRL; /*!< (0x028) Sleep and wakeup control */
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__IOM uint32_t PMU_CTRL0; /*!< (0x02C) Register controlled power down signal in test mode */
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__IOM uint32_t PMU_CTRL1; /*!< (0x030) Register controlled power down signal in sleep mode */
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__IOM uint32_t PIN_MUX_0; /*!< (0x034) PIN MUX for GPIO00 ~ GPIO07 */
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__IOM uint32_t PIN_MUX_1; /*!< (0x038) PIN MUX for GPIO09 ~ GPIO15 */
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__IOM uint32_t PIN_MUX_2; /*!< (0x03C) PIN MUX for GPIO16 ~ GPIO18 */
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__IOM uint32_t WAKEUP_EN; /*!< (0x040) Wakeup enable */
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__IOM uint32_t WAKEUP_POL; /*!< (0x044) Wakeup IO Polarity Configuration */
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__IOM uint32_t XTAL_CFG; /*!< (0x048) 38.4MHz XTAL Configuration */
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__IOM uint32_t XTAL32_CFG; /*!< (0x04C) 32K XTAL Configuration */
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__IOM uint32_t CAP_DIV_CFG; /*!< (0x050) Sleep Cap Divider Configuration */
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__IOM uint32_t ACMP_CFG; /*!< (0x054) Analog Comparator Configuration */
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__IOM uint32_t BOD_BOR; /*!< (0x058) Brown Out Detection */
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__IOM uint32_t RESET_CAUSE; /*!< (0x05C) Reset cause */
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__IOM uint32_t MEM_CFG; /*!< (0x060) Memory configuration */
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__IOM uint32_t SYS_TICK_CTRL; /*!< (0x064) System Tick Control */
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__IOM uint32_t SHELF_KEY; /*!< (0x068) Shelf Key */
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__IOM uint32_t MEM_PG_CTRL; /*!< (0x06C) SRAM Power Gating Control Register */
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uint32_t RESERVED0[36];
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__IOM uint32_t IO_OD; /*!< (0x100) Register controlled IO output open drain */
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__IOM uint32_t IO_DRV; /*!< (0x104) Register controlled IO output driven capability */
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__IOM uint32_t IO_EI; /*!< (0x108) Register controlled IO input enable */
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__IOM uint32_t IO_PDN; /*!< (0x10C) Register controlled IO pull down enable */
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__IOM uint32_t IO_PUP[3]; /*!< (0x110) Register controlled IO pull up enable */
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__IOM uint32_t IO_SLP_OE; /*!< (0x11C) Register controlled IO output enable in sleep mode */
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__IOM uint32_t IO_SLP_OUT; /*!< (0x120) Register controlled IO output value in sleep mode */
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__IOM uint32_t IO_SLP_AEN; /*!< (0x124) Register controlled Analog IO switch enable in sleep mode */
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__IOM uint32_t IO_SLP_EI; /*!< (0x128) Register controlled IO input enable in sleep mode */
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__IOM uint32_t IO_SLP_PDN; /*!< (0x12C) Register controlled IO pull down enable in sleep mode */
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__IOM uint32_t IO_SLP_PUP[3]; /*!< (0x130) Register controlled IO pull up enable in sleep mode */
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uint32_t RESERVED2[49];
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__IOM uint32_t IVREF_ULP; /*!< (0x200) Ultra-low power Bandgap configure */
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__IOM uint32_t REG_DIG; /*!< (0x204) Digital regulator configure */
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__IOM uint32_t IVREF_CP; /*!< (0x208) IVREF and Charge Pump Configure */
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__IOM uint32_t BUCK; /*!< (0x20C) Buck converter configure */
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__IOM uint32_t XTAL_0; /*!< (0x210) 38.4MHz XTAL configure */
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__IOM uint32_t XTAL_1; /*!< (0x214) 38.4MHz XTAL configure */
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__IOM uint32_t XTAL32; /*!< (0x218) 32.768KHz XTAL configure */
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__IOM uint32_t RCO; /*!< (0x21C) 32KHz RCO configure */
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__IOM uint32_t RO; /*!< (0x220) 48MHz ring oscillator configure */
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__IOM uint32_t REFPLL; /*!< (0x224) REFPLL configure */
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__IOM uint32_t EFUSE_LDO; /*!< (0x228) EFUSE LDO configure */
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__IM uint32_t CLK_STATUS; /*!< (0x22C) Clock status */
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__IM uint32_t DUM_AO_HI; /*!< (0x230) Dummy AO Register Reset High */
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__IM uint32_t DUM_AO_LO; /*!< (0x234) Dummy AO Register Reset Low */
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uint32_t RESERVED3[50];
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__IM uint32_t TRIM0_RD_REG; /*!< (0x300) Trim bits for TS */
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__IM uint32_t TRIM1_RD_REG; /*!< (0x304) Trim bits for analog */
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__IM uint32_t TRIM2_RD_REG; /*!< (0x308) Trim Readout Register for Calibration 1 */
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__IM uint32_t TRIM3_RD_REG; /*!< (0x30C) Trim Readout Register for Calibration 2 */
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} SYSCON_TypeDef;
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// SYSTEM_STATUS
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#define SYSCON_SYSTEM_STATUS_INT_FLASH_POS 17U
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#define SYSCON_SYSTEM_STATUS_INT_FLASH_MSK (1U << SYSCON_SYSTEM_STATUS_INT_FLASH_POS)
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#define SYSCON_SYSTEM_STATUS_EFLOAD_STATUS_POS 16U
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#define SYSCON_SYSTEM_STATUS_EFLOAD_STATUS_MSK (1U << SYSCON_SYSTEM_STATUS_EFLOAD_STATUS_POS)
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// SYS_CMU
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#define SYSCON_SYS_CMU_SYS_CLK_SEL_POS 30U
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#define SYSCON_SYS_CMU_SYS_CLK_SEL_MSK (1U << SYSCON_SYS_CMU_SYS_CLK_SEL_POS)
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#define SYSCON_SYS_CMU_32K_CLK_SEL_POS 29U
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#define SYSCON_SYS_CMU_32K_CLK_SEL_MSK (1U << SYSCON_SYS_CMU_32K_CLK_SEL_POS)
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#define SYSCON_SYS_CMU_HS_CLK_SEL_POS 28U
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#define SYSCON_SYS_CMU_HS_CLK_SEL_MSK (1U << SYSCON_SYS_CMU_HS_CLK_SEL_POS)
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// CLK_DIV
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#define SYSCON_CLK_DIV_UART0_FDIV_POS 0U
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#define SYSCON_CLK_DIV_UART0_FDIV_MSK (0xffU << SYSCON_CLK_DIV_UART0_FDIV_POS)
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#define SYSCON_CLK_DIV_UART0_FDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_DIV_UART0_FDIV_POS)) & SYSCON_CLK_DIV_UART0_FDIV_MSK)
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#define SYSCON_CLK_DIV_UART1_FDIV_POS 8U
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#define SYSCON_CLK_DIV_UART1_FDIV_MSK (0xffU << SYSCON_CLK_DIV_UART1_FDIV_POS)
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#define SYSCON_CLK_DIV_UART1_FDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_DIV_UART1_FDIV_POS)) & SYSCON_CLK_DIV_UART1_FDIV_MSK)
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#define SYSCON_CLK_DIV_FLASH_CTRL_DIV_POS 18U
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#define SYSCON_CLK_DIV_FLASH_CTRL_DIV_MSK (0x3U << SYSCON_CLK_DIV_FLASH_CTRL_DIV_POS)
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#define SYSCON_CLK_DIV_FLASH_CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_DIV_FLASH_CTRL_DIV_POS)) & SYSCON_CLK_DIV_FLASH_CTRL_DIV_MSK)
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#define SYSCON_CLK_DIV_PCLK_DIV_POS 26U
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#define SYSCON_CLK_DIV_PCLK_DIV_MSK (0x3U << SYSCON_CLK_DIV_PCLK_DIV_POS)
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#define SYSCON_CLK_DIV_PCLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_DIV_PCLK_DIV_POS)) & SYSCON_CLK_DIV_PCLK_DIV_MSK)
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#define SYSCON_CLK_DIV_HCLK_DIV_POS 28U
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#define SYSCON_CLK_DIV_HCLK_DIV_MSK (0x3U << SYSCON_CLK_DIV_HCLK_DIV_POS)
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#define SYSCON_CLK_DIV_HCLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLK_DIV_HCLK_DIV_POS)) & SYSCON_CLK_DIV_HCLK_DIV_MSK)
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#define SYSCON_CLK_DIV_WDT_CLK_SEL_POS 30U
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#define SYSCON_CLK_DIV_WDT_CLK_SEL_MSK (1U << SYSCON_CLK_DIV_WDT_CLK_SEL_POS)
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// SYS_CTRL
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#define SYSCON_SYS_CTRL_REMAP_POS 0U
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#define SYSCON_SYS_CTRL_REMAP_MSK (0x3U << SYSCON_SYS_CTRL_REMAP_POS)
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#define SYSCON_SYS_CTRL_REMAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYS_CTRL_REMAP_POS)) & SYSCON_SYS_CTRL_REMAP_MSK)
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// PIN_MUX_x
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#define SYSCON_PIN_MUX_FUNC_MSK (0xFU)
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// WAKEUP_EN
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#define SYSCON_WAKEUP_EN_IO_POS 0U
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#define SYSCON_WAKEUP_EN_IO_MSK (0x3ffffU << SYSCON_WAKEUP_EN_IO_POS)
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#define SYSCON_WAKEUP_EN_IO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WAKEUP_EN_IO_POS)) & SYSCON_WAKEUP_EN_IO_MSK)
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#define SYSCON_WAKEUP_EN_ACMP0_POS 24U
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#define SYSCON_WAKEUP_EN_ACMP0_MSK (0x1U << SYSCON_WAKEUP_EN_ACMP0_POS)
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#define SYSCON_WAKEUP_EN_ACMP1_POS 25U
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#define SYSCON_WAKEUP_EN_ACMP1_MSK (0x1U << SYSCON_WAKEUP_EN_ACMP1_POS)
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#define SYSCON_WAKEUP_EN_SLTIMER_POS 26U
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#define SYSCON_WAKEUP_EN_SLTIMER_MSK (0x1U << SYSCON_WAKEUP_EN_SLTIMER_POS)
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#define SYSCON_WAKEUP_EN_RTC_ALARM_POS 27U
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#define SYSCON_WAKEUP_EN_RTC_ALARM_MSK (0x1U << SYSCON_WAKEUP_EN_RTC_ALARM_POS)
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#define SYSCON_WAKEUP_EN_RTC_TICK_POS 28U
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#define SYSCON_WAKEUP_EN_RTC_TICK_MSK (0x1U << SYSCON_WAKEUP_EN_RTC_TICK_POS)
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#define SYSCON_WAKEUP_EN_POS 31U
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#define SYSCON_WAKEUP_EN_MSK (0x1U << SYSCON_WAKEUP_EN_POS)
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// XTAL_CFG
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#define SYSCON_XTAL_CFG_XTAL_INJ_POS 16U
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#define SYSCON_XTAL_CFG_XTAL_INJ_MSK (0x3U << SYSCON_XTAL_CFG_XTAL_INJ_POS)
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#define SYSCON_XTAL_CFG_XTAL_INJ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_XTAL_CFG_XTAL_INJ_POS)) & SYSCON_XTAL_CFG_XTAL_INJ_MSK)
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#define SYSCON_XTAL_CFG_XTAL_CSEL_POS 0U
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#define SYSCON_XTAL_CFG_XTAL_CSEL_MSK (0x7FU << SYSCON_XTAL_CFG_XTAL_CSEL_POS)
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#define SYSCON_XTAL_CFG_XTAL_CSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_XTAL_CFG_XTAL_CSEL_POS)) & SYSCON_XTAL_CFG_XTAL_CSEL_MSK)
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// XTAL32_CFG
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#define SYSCON_XTAL32_CFG_X32_INJ_POS 16U
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#define SYSCON_XTAL32_CFG_X32_INJ_MSK (0x3U << SYSCON_XTAL32_CFG_X32_INJ_POS)
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#define SYSCON_XTAL32_CFG_X32_INJ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_XTAL32_CFG_X32_INJ_POS)) & SYSCON_XTAL32_CFG_X32_INJ_MSK)
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#define SYSCON_XTAL32_CFG_X32_ICTRL_POS 8U
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#define SYSCON_XTAL32_CFG_X32_ICTRL_MSK (0x3FU << SYSCON_XTAL32_CFG_X32_ICTRL_POS)
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#define SYSCON_XTAL32_CFG_X32_ICTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_XTAL32_CFG_X32_ICTRL_POS)) & SYSCON_XTAL32_CFG_X32_ICTRL_MSK)
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#define SYSCON_XTAL32_CFG_XTAL_CSEL_POS 0U
|
#define SYSCON_XTAL32_CFG_XTAL_CSEL_MSK (0x7FU << SYSCON_XTAL32_CFG_XTAL_CSEL_POS)
|
#define SYSCON_XTAL32_CFG_XTAL_CSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_XTAL32_CFG_XTAL_CSEL_POS)) & SYSCON_XTAL32_CFG_XTAL_CSEL_MSK)
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|
// RESET_CAUSE
|
#define SYSCON_RESET_CAUSE_POR_POS 0U
|
#define SYSCON_RESET_CAUSE_POR_MSK (0x1U << SYSCON_RESET_CAUSE_POR_POS)
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|
#define SYSCON_RESET_CAUSE_BOR_POS 1U
|
#define SYSCON_RESET_CAUSE_BOR_MSK (0x1U << SYSCON_RESET_CAUSE_BOR_POS)
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|
#define SYSCON_RESET_CAUSE_PIN_POS 2U
|
#define SYSCON_RESET_CAUSE_PIN_MSK (0x1U << SYSCON_RESET_CAUSE_PIN_POS)
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#define SYSCON_RESET_CAUSE_WDT_POS 3U
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#define SYSCON_RESET_CAUSE_WDT_MSK (0x1U << SYSCON_RESET_CAUSE_WDT_POS)
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|
#define SYSCON_RESET_CAUSE_LOCKUP_POS 4U
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#define SYSCON_RESET_CAUSE_LOCKUP_MSK (0x1U << SYSCON_RESET_CAUSE_LOCKUP_POS)
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#define SYSCON_RESET_CAUSE_REBOOT_POS 5U
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#define SYSCON_RESET_CAUSE_REBOOT_MSK (0x1U << SYSCON_RESET_CAUSE_REBOOT_POS)
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#define SYSCON_RESET_CAUSE_SYSREQ_POS 6U
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#define SYSCON_RESET_CAUSE_SYSREQ_MSK (0x1U << SYSCON_RESET_CAUSE_SYSREQ_POS)
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#define SYSCON_RESET_CAUSE_DVDD_POS 7U
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#define SYSCON_RESET_CAUSE_DVDD_MSK (0x1U << SYSCON_RESET_CAUSE_DVDD_POS)
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#define SYSCON_RESET_CAUSE_CLR_POS 31U
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#define SYSCON_RESET_CAUSE_CLR_MSK (0x1U << SYSCON_RESET_CAUSE_CLR_POS)
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|
// ACMP_CFG
|
#define SYSCON_ACMP_CFG_ACMP0_EN_POS 0U
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#define SYSCON_ACMP_CFG_ACMP0_EN_MSK (1U << SYSCON_ACMP_CFG_ACMP0_EN_POS)
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|
#define SYSCON_ACMP_CFG_ACMP0_MUX_SP_POS 1U
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#define SYSCON_ACMP_CFG_ACMP0_MUX_SP_MSK (0x7U << SYSCON_ACMP_CFG_ACMP0_MUX_SP_POS)
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#define SYSCON_ACMP_CFG_ACMP0_MUX_SP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ACMP_CFG_ACMP0_MUX_SP_POS)) & SYSCON_ACMP_CFG_ACMP0_MUX_SP_MSK)
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|
#define SYSCON_ACMP_CFG_ACMP0_MUX_SN_POS 4U
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#define SYSCON_ACMP_CFG_ACMP0_MUX_SN_MSK (0x7U << SYSCON_ACMP_CFG_ACMP0_MUX_SN_POS)
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#define SYSCON_ACMP_CFG_ACMP0_MUX_SN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ACMP_CFG_ACMP0_MUX_SN_POS)) & SYSCON_ACMP_CFG_ACMP0_MUX_SN_MSK)
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#define SYSCON_ACMP_CFG_ACMP0_HYST_EN_POS 7U
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#define SYSCON_ACMP_CFG_ACMP0_HYST_EN_MSK (1U << SYSCON_ACMP_CFG_ACMP0_HYST_EN_POS)
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#define SYSCON_ACMP_CFG_ACMP0_HYST_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ACMP_CFG_ACMP0_HYST_EN_POS)) & SYSCON_ACMP_CFG_ACMP0_HYST_EN_MSK)
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#define SYSCON_ACMP_CFG_ACMP0_EDGE_INT_POS 8U
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#define SYSCON_ACMP_CFG_ACMP0_EDGE_INT_MSK (0x3U << SYSCON_ACMP_CFG_ACMP0_EDGE_INT_POS)
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#define SYSCON_ACMP_CFG_ACMP0_EDGE_INT_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ACMP_CFG_ACMP0_EDGE_INT_POS)) & SYSCON_ACMP_CFG_ACMP0_EDGE_INT_MSK)
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#define SYSCON_ACMP_CFG_ACMP0_OUT_POS 10U
|
#define SYSCON_ACMP_CFG_ACMP0_OUT_MSK (1U << SYSCON_ACMP_CFG_ACMP0_OUT_POS)
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#define SYSCON_ACMP_CFG_ACMP0_GET_DATA(x) (((uint32_t)(((uint32_t)(x)) & SYSCON_ACMP_CFG_ACMP0_OUT_MSK)) >> SYSCON_ACMP_CFG_ACMP0_OUT_POS)
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#define SYSCON_ACMP_CFG_ACMP1_EN_POS 16U
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#define SYSCON_ACMP_CFG_ACMP1_EN_MSK (1U << SYSCON_ACMP_CFG_ACMP1_EN_POS)
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#define SYSCON_ACMP_CFG_ACMP1_MUX_SP_POS 17U
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#define SYSCON_ACMP_CFG_ACMP1_MUX_SP_MSK (0x7U << SYSCON_ACMP_CFG_ACMP1_MUX_SP_POS)
|
#define SYSCON_ACMP_CFG_ACMP1_MUX_SP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ACMP_CFG_ACMP1_MUX_SP_POS)) & SYSCON_ACMP_CFG_ACMP1_MUX_SP_MSK)
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#define SYSCON_ACMP_CFG_ACMP1_MUX_SN_POS 20U
|
#define SYSCON_ACMP_CFG_ACMP1_MUX_SN_MSK (0x7U << SYSCON_ACMP_CFG_ACMP1_MUX_SN_POS)
|
#define SYSCON_ACMP_CFG_ACMP1_MUX_SN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ACMP_CFG_ACMP1_MUX_SN_POS)) & SYSCON_ACMP_CFG_ACMP1_MUX_SN_MSK)
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#define SYSCON_ACMP_CFG_ACMP1_HYST_EN_POS 23U
|
#define SYSCON_ACMP_CFG_ACMP1_HYST_EN_MSK (1U << SYSCON_ACMP_CFG_ACMP1_HYST_EN_POS)
|
#define SYSCON_ACMP_CFG_ACMP1_HYST_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ACMP_CFG_ACMP1_HYST_EN_POS)) & SYSCON_ACMP_CFG_ACMP1_HYST_EN_MSK)
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#define SYSCON_ACMP_CFG_ACMP1_EDGE_INT_POS 24U
|
#define SYSCON_ACMP_CFG_ACMP1_EDGE_INT_MSK (0x3U << SYSCON_ACMP_CFG_ACMP1_EDGE_INT_POS)
|
#define SYSCON_ACMP_CFG_ACMP1_EDGE_INT_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ACMP_CFG_ACMP1_EDGE_INT_POS)) & SYSCON_ACMP_CFG_ACMP1_EDGE_INT_MSK)
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#define SYSCON_ACMP_CFG_ACMP1_OUT_POS 26U
|
#define SYSCON_ACMP_CFG_ACMP1_OUT_MSK (1U << SYSCON_ACMP_CFG_ACMP1_OUT_POS)
|
#define SYSCON_ACMP_CFG_ACMP1_GET_DATA(x) (((uint32_t)(((uint32_t)(x)) & SYSCON_ACMP_CFG_ACMP1_OUT_MSK)) >> SYSCON_ACMP_CFG_ACMP1_OUT_POS)
|
|
// BOD_BOR
|
#define SYSCON_BOR_EN_POS 0U
|
#define SYSCON_BOR_EN_MSK (1U << SYSCON_BOR_EN_POS)
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|
#define SYSCON_BOR_TH_SEL_POS 1U
|
#define SYSCON_BOR_TH_SEL_MSK (0x7U << SYSCON_BOR_TH_SEL_POS)
|
#define SYSCON_BOR_TH_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BOR_TH_SEL_POS)) & SYSCON_BOR_TH_SEL_MSK)
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|
#define SYSCON_BOR_HYST_SEL_POS 4U
|
#define SYSCON_BOR_HYST_SEL_MSK (0x3U << SYSCON_BOR_HYST_SEL_POS)
|
#define SYSCON_BOR_HYST_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BOR_HYST_SEL_POS)) & SYSCON_BOR_HYST_SEL_MSK)
|
|
#define SYSCON_BOD_EN_POS 16U
|
#define SYSCON_BOD_EN_MSK (1U << SYSCON_BOD_EN_POS)
|
|
#define SYSCON_BOD_TH_SEL_POS 17U
|
#define SYSCON_BOD_TH_SEL_MSK (0x7U << SYSCON_BOD_TH_SEL_POS)
|
#define SYSCON_BOD_TH_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BOD_TH_SEL_POS)) & SYSCON_BOD_TH_SEL_MSK)
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|
#define SYSCON_BOD_HYST_SEL_POS 20U
|
#define SYSCON_BOD_HYST_SEL_MSK (0x3U << SYSCON_BOD_HYST_SEL_POS)
|
#define SYSCON_BOD_HYST_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BOD_HYST_SEL_POS)) & SYSCON_BOD_HYST_SEL_MSK)
|
|
// CLK_STATUS
|
#define SYSCON_CLK_STATUS_XTAL_38P4M_REDAY_POS 0U
|
#define SYSCON_CLK_STATUS_XTAL_38P4M_REDAY_MSK (1U << SYSCON_CLK_STATUS_XTAL_38P4M_REDAY_POS)
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|
#define SYSCON_CLK_STATUS_XTAL_32K_REDAY_POS 1U
|
#define SYSCON_CLK_STATUS_XTAL_32K_REDAY_MSK (1U << SYSCON_CLK_STATUS_XTAL_32K_REDAY_POS)
|
|
#define SYSCON_CLK_STATUS_RCO_32K_REDAY_POS 2U
|
#define SYSCON_CLK_STATUS_RCO_32K_REDAY_MSK (1U << SYSCON_CLK_STATUS_RCO_32K_REDAY_POS)
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|
#define SYSCON_CLK_STATUS_RO_48M_REDAY_POS 3U
|
#define SYSCON_CLK_STATUS_RO_48M_REDAY_MSK (1U << SYSCON_CLK_STATUS_RO_48M_REDAY_POS)
|
|
#define SYSCON_CLK_STATUS_REFPLL_REDAY_POS 6U
|
#define SYSCON_CLK_STATUS_REFPLL_REDAY_MSK (1U << SYSCON_CLK_STATUS_REFPLL_REDAY_POS)
|
|
// TRIM0_RD_REG
|
#define SYSCON_TRIM0_RD_REG_FLASH_RISECLK_POS 28U
|
#define SYSCON_TRIM0_RD_REG_FLASH_RISECLK_MSK (1U << SYSCON_TRIM0_RD_REG_FLASH_RISECLK_POS)
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|
#define SYSCON_TRIM0_RD_REG_FLASH_FBCLK_POS 29U
|
#define SYSCON_TRIM0_RD_REG_FLASH_FBCLK_MSK (1U << SYSCON_TRIM0_RD_REG_FLASH_FBCLK_POS)
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|
#define SYSCON_TRIM0_RD_REG_FLASH_MODE3_POS 30U
|
#define SYSCON_TRIM0_RD_REG_FLASH_MODE3_MSK (1U << SYSCON_TRIM0_RD_REG_FLASH_MODE3_POS)
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|
#define SYSCON_TRIM0_RD_REG_FLASH_CLKDIV_POS 31U
|
#define SYSCON_TRIM0_RD_REG_FLASH_CLKDIV_MSK (1U << SYSCON_TRIM0_RD_REG_FLASH_CLKDIV_POS)
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|
/* =========================================================================================================================== */
|
/* ================ GPIO ================ */
|
/* =========================================================================================================================== */
|
|
/**
|
* @brief GPIO
|
*/
|
typedef struct
|
{
|
__IM uint32_t DATA; /*!< (0x00) GPIO value register */
|
__IOM uint32_t DATAOUT; /*!< (0x04) GPIO output status register */
|
uint32_t RESERVED0[2];
|
__IOM uint32_t OUTENSET; /*!< (0x10) GPIO output enable set register */
|
__IOM uint32_t OUTENCLR; /*!< (0x14) GPIO output clear register */
|
uint32_t RESERVED1[2];
|
__OM uint32_t INTENSET; /*!< (0x20) GPIO interrupt enable set register */
|
__IOM uint32_t INTENCLR; /*!< (0x24) GPIO interrupt enable clear register */
|
__OM uint32_t INTTYPESET; /*!< (0x28) GPIO interrupt type set register */
|
__IOM uint32_t INTTYPECLR; /*!< (0x2C) GPIO interrupt type set register */
|
__OM uint32_t INTPOLSET; /*!< (0x30) GPIO interrupt polarity set register */
|
__IOM uint32_t INTPOLCLR; /*!< (0x34) GPIO interrupt polarity clear register */
|
__IOM uint32_t INTSTATUS; /*!< (0x38) GPIO interrupt status register */
|
} GPIO_TypeDef;
|
|
// DATA
|
#define GPIO_DATA_DATA_MSK (0x0003FFFFU)
|
#define GPIO_DATA_DATA_POS (0U)
|
|
// DATAOUT
|
#define GPIO_DATAOUT_DATAOUT_MSK (0x0003FFFFU)
|
#define GPIO_DATAOUT_DATAOUT_POS (0U)
|
|
// OUTENSET
|
#define GPIO_OUTENSET_OUTENSET_MSK (0x0003FFFFU)
|
#define GPIO_OUTENSET_OUTENSET_POS (0U)
|
|
// OUTENCLR
|
#define GPIO_OUTENCLR_OUTENCLR_MSK (0x0003FFFFU)
|
#define GPIO_OUTENCLR_OUTENCLR_POS (0U)
|
|
// INTENSET
|
#define GPIO_INTENSET_INTENSET_MSK (0x0003FFFFU)
|
#define GPIO_INTENSET_INTENSET_POS (0U)
|
|
// INTENCLR
|
#define GPIO_INTENCLR_INTENCLR_MSK (0x0003FFFFU)
|
#define GPIO_INTENCLR_INTENCLR_POS (0U)
|
|
// INTTYPESET
|
#define GPIO_INTTYPESET_INTTYPESET_MSK (0x0003FFFFU)
|
#define GPIO_INTTYPESET_INTTYPESET_POS (0U)
|
|
// INTTYPECLR
|
#define GPIO_INTTYPECLR_INTTYPECLR_MSK (0x0003FFFFU)
|
#define GPIO_INTTYPECLR_INTTYPECLR_POS (0U)
|
|
// INTPOLSET
|
#define GPIO_INTPOLSET_INTPOLSET_MSK (0x0003FFFFU)
|
#define GPIO_INTPOLSET_INTPOLSET_POS (0U)
|
|
// INTPOLCLR
|
#define GPIO_INTPOLCLR_INTPOLCLR_MSK (0x0003FFFFU)
|
#define GPIO_INTPOLCLR_INTPOLCLR_POS (0U)
|
|
// INTSTATUS
|
#define GPIO_INTSTATUS_INTSTATUS_MSK (0x0003FFFFU)
|
#define GPIO_INTSTATUS_INTSTATUS_POS (0U)
|
|
/* =========================================================================================================================== */
|
/* ================ UART ================ */
|
/* =========================================================================================================================== */
|
|
/**
|
* @brief UART
|
*/
|
typedef struct
|
{
|
__OM uint32_t TX_DATA; /*!< (0x00) UART TX Data Register */
|
__IM uint32_t RX_DATA; /*!< (0x04) UART RX Data Register */
|
__OM uint32_t CTRL0; /*!< (0x08) UART Control Register 0 */
|
__IOM uint32_t CTRL1; /*!< (0x0C) UART Control Register 1 */
|
__IOM uint32_t CTRL2; /*!< (0x10) UART Control Register 2 */
|
__IM uint32_t STATUS; /*!< (0x14) UART Status Register */
|
__IOM uint32_t INTR_EN; /*!< (0x18) UART Interrupt Enable Register */
|
__IM uint32_t INTR_STATUS; /*!< (0x1C) UART Interrupt Status Register */
|
__OM uint32_t INTR_CLR; /*!< (0x20) UART Interrupt Clear Register */
|
__IM uint32_t TX_FL; /*!< (0x24) UART TX FIFO level */
|
__IM uint32_t RX_FL; /*!< (0x28) UART RX FIFO level */
|
__IOM uint32_t DIVISOR; /*!< (0x2C) UART Divisor Latch Register */
|
} UART_TypeDef;
|
|
// CTRL0
|
#define UART_CTRL0_RX_TRIGGER_POS 6U
|
#define UART_CTRL0_RX_TRIGGER_MSK (3U << UART_CTRL0_RX_TRIGGER_POS) // receiver trigger
|
#define UART_CTRL0_RX_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << UART_CTRL0_RX_TRIGGER_POS)) & UART_CTRL0_RX_TRIGGER_MSK)
|
|
#define UART_CTRL0_TX_TRIGGER_POS 4U
|
#define UART_CTRL0_TX_TRIGGER_MSK (3U << UART_CTRL0_TX_TRIGGER_POS) // transmitter trigger
|
#define UART_CTRL0_TX_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << UART_CTRL0_TX_TRIGGER_POS)) & UART_CTRL0_TX_TRIGGER_MSK)
|
|
#define UART_CTRL0_DMA_MODE_POS 3U
|
#define UART_CTRL0_DMA_MODE_MSK (1U << UART_CTRL0_DMA_MODE_POS) // dma mode
|
#define UART_CTRL0_DMA_MODE(x) (((uint32_t)(((uint32_t)(x)) << UART_CTRL0_DMA_MODE_POS)) & UART_CTRL0_DMA_MODE_MSK)
|
|
#define UART_CTRL0_TX_FIFO_RESET_POS 2U
|
#define UART_CTRL0_TX_FIFO_RESET_MSK (1U << UART_CTRL0_TX_FIFO_RESET_POS) // transmitter FIFO reset
|
|
#define UART_CTRL0_RX_FIFO_RESET_POS 1U
|
#define UART_CTRL0_RX_FIFO_RESET_MSK (1U << UART_CTRL0_RX_FIFO_RESET_POS) // receiver FIFO reset
|
|
#define UART_CTRL0_FIFO_ENABLE_POS 0U
|
#define UART_CTRL0_FIFO_ENABLE_MSK (1U << UART_CTRL0_FIFO_ENABLE_POS) // FIFO enable
|
|
// CTRL1
|
#define UART_CTRL1_DLAB_POS 7U
|
#define UART_CTRL1_DLAB_MSK (1U << UART_CTRL1_DLAB_POS) // divisor latch address bit
|
|
#define UART_CTRL1_BREAK_POS 6U
|
#define UART_CTRL1_BREAK_MSK (1U << UART_CTRL1_BREAK_POS) // line break
|
|
#define UART_CTRL1_STICK_PARITY_POS 5U
|
#define UART_CTRL1_STICK_PARITY_MSK (1U << UART_CTRL1_STICK_PARITY_POS) // unsupported
|
|
#define UART_CTRL1_EVEN_PARITY_POS 4U
|
#define UART_CTRL1_EVEN_PARITY_MSK (1U << UART_CTRL1_EVEN_PARITY_POS) // parity select
|
|
#define UART_CTRL1_PARITY_EN_POS 3U
|
#define UART_CTRL1_PARITY_EN_MSK (1U << UART_CTRL1_PARITY_EN_POS) // parity enable
|
|
#define UART_CTRL1_STOP_POS 2U
|
#define UART_CTRL1_STOP_MSK (1U << UART_CTRL1_STOP_POS) // stop bits
|
|
#define UART_CTRL1_DATA_LEN_POS 0U
|
#define UART_CTRL1_DATA_LEN_MSK (3U << UART_CTRL1_DATA_LEN_POS) // number of bits per character
|
|
// CTRL2
|
#define UART_CTRL2_FLOW_CTRL_EN_POS 5U // automatic flow control
|
#define UART_CTRL2_FLOW_CTRL_EN_MSK (1U << UART_CTRL2_FLOW_CTRL_EN_POS)
|
|
#define UART_CTRL2_RTS_POS 1U // rts
|
#define UART_CTRL2_RTS_MSK (1U << UART_CTRL2_RTS_POS)
|
|
#define UART_CTRL2_DTR_POS 0U // dtr
|
#define UART_CTRL2_DTR_MSK (1U << UART_CTRL2_DTR_POS)
|
|
// STATUS
|
#define UART_STATUS_RFE_POS 15U // receiver FIFO error
|
#define UART_STATUS_RFE_MSK (1U << UART_STATUS_RFE_POS)
|
|
#define UART_STATUS_TEMT_POS 14U // transmitter empty
|
#define UART_STATUS_TEMT_MSK (1U << UART_STATUS_TEMT_POS)
|
|
#define UART_STATUS_THRE_POS 13U // transmitter holding register empty
|
#define UART_STATUS_THRE_MSK (1U << UART_STATUS_THRE_POS)
|
|
#define UART_STATUS_BI_POS 12U // break interrupt
|
#define UART_STATUS_BI_MSK (1U << UART_STATUS_BI_POS)
|
|
#define UART_STATUS_FE_POS 11U // framing error
|
#define UART_STATUS_FE_MSK (1U << UART_STATUS_FE_POS)
|
|
#define UART_STATUS_PE_POS 10U // parity error
|
#define UART_STATUS_PE_MSK (1U << UART_STATUS_PE_POS)
|
|
#define UART_STATUS_OE_POS 9U // overrun error
|
#define UART_STATUS_OE_MSK (1U << UART_STATUS_OE_POS)
|
|
#define UART_STATUS_DR_POS 8U // data ready
|
#define UART_STATUS_DR_MSK (1U << UART_STATUS_DR_POS)
|
|
#define UART_STATUS_RFF_POS 4U // Rx FIFO full
|
#define UART_STATUS_RFF_MSK (1U << UART_STATUS_RFF_POS)
|
|
#define UART_STATUS_RFNE_POS 3U // Rx FIFO not empty
|
#define UART_STATUS_RFNE_MSK (1U << UART_STATUS_RFNE_POS)
|
|
#define UART_STATUS_TFE_POS 2U // Tx FIFO empty
|
#define UART_STATUS_TFE_MSK (1U << UART_STATUS_TFE_POS)
|
|
#define UART_STATUS_TFNF_POS 1U // Tx FIFO not full
|
#define UART_STATUS_TFNF_MSK (1U << UART_STATUS_TFNF_POS)
|
|
#define UART_STATUS_BUSY_POS 0U // serial transfer is in progress
|
#define UART_STATUS_BUSY_MSK (1U << UART_STATUS_BUSY_POS)
|
|
#define UART_STATUS_ERROR_MSK (UART_STATUS_OE_MSK | UART_STATUS_PE_MSK | UART_STATUS_FE_MSK | UART_STATUS_BI_MSK | UART_STATUS_RFE_MSK)
|
|
// INTR_EN
|
#define UART_INTR_EN_PTIME_POS 7U // programmable THRE interrupt mode
|
#define UART_INTR_EN_PTIME_MSK (1U << UART_INTR_EN_PTIME_POS)
|
|
#define UART_INTR_EN_ELCOLR_POS 4U // OE,PE,FE,BI interrupt cleared by W1C only
|
#define UART_INTR_EN_ELCOLR_MSK (1U << UART_INTR_EN_ELCOLR_POS)
|
|
#define UART_INTR_EN_EDSSI_POS 3U // modem status
|
#define UART_INTR_EN_EDSSI_MSK (1U << UART_INTR_EN_EDSSI_POS)
|
|
#define UART_INTR_EN_ELSI_POS 2U // receiver line status
|
#define UART_INTR_EN_ELSI_MSK (1U << UART_INTR_EN_ELSI_POS)
|
|
#define UART_INTR_EN_ETBEI_POS 1U // transmitter holding register
|
#define UART_INTR_EN_ETBEI_MSK (1U << UART_INTR_EN_ETBEI_POS)
|
|
#define UART_INTR_EN_ERBFI_POS 0U // received data available
|
#define UART_INTR_EN_ERBFI_MSK (1U << UART_INTR_EN_ERBFI_POS)
|
|
#define UART_INTR_EN_ALL_MSK (UART_INTR_EN_ELCOLR_MSK | UART_INTR_EN_EDSSI_MSK | UART_INTR_EN_ELSI_MSK | UART_INTR_EN_ETBEI_MSK | UART_INTR_EN_ERBFI_MSK)
|
|
// INTR_CLR
|
#define UART_INTR_CLR_THRE_INT_CLR_POS 3U
|
#define UART_INTR_CLR_THRE_INT_CLR_MSK (1U << UART_INTR_CLR_THRE_INT_CLR_POS)
|
|
#define UART_INTR_CLR_BUSY_INT_CLR_POS 2U
|
#define UART_INTR_CLR_BUSY_INT_CLR_MSK (1U << UART_INTR_CLR_BUSY_INT_CLR_POS)
|
|
#define UART_INTR_CLR_LSR_INT_CLR_POS 1U
|
#define UART_INTR_CLR_LSR_INT_CLR_MSK (1U << UART_INTR_CLR_LSR_INT_CLR_POS)
|
|
#define UART_INTR_CLR_MSR_INT_CLR_POS 0U
|
#define UART_INTR_CLR_MSR_INT_CLR_MSK (1U << UART_INTR_CLR_MSR_INT_CLR_POS)
|
|
// TX_FL
|
#define UART_TX_FL_LEVEL_POS 0U // Tx FIFO data level
|
#define UART_TX_FL_LEVEL_MSK (0xffU << UART_TX_FL_LEVEL_POS)
|
|
// RX_FL
|
#define UART_RX_FL_LEVEL_POS 0U // Rx FIFO data level
|
#define UART_RX_FL_LEVEL_MSK (0xffU << UART_RX_FL_LEVEL_POS)
|
|
// DIVISOR
|
#define UART_DIVISOR_H_POS 8U
|
#define UART_DIVISOR_H_MSK (0xffU << UART_DIVISOR_H_POS)
|
#define UART_DIVISOR_H(x) (((uint32_t)(((uint32_t)(x)) << UART_DIVISOR_H_POS)) & UART_DIVISOR_H_MSK)
|
|
#define UART_DIVISOR_L_POS 0U
|
#define UART_DIVISOR_L_MSK (0xffU << UART_DIVISOR_L_POS)
|
|
/* =========================================================================================================================== */
|
/* ================ SPI ================ */
|
/* =========================================================================================================================== */
|
|
/**
|
* @brief SPI
|
*/
|
|
typedef struct
|
{
|
__IOM uint32_t CTRL0; /*!< (0x00) SPI Control register 0 */
|
__IOM uint32_t CTRL1; /*!< (0x04) SPI Control register 1 */
|
__IOM uint32_t DATA; /*!< (0x08) SPI Data register */
|
__IM uint32_t STATUS0; /*!< (0x0C) SPI Status register */
|
__IOM uint32_t PRESCALER; /*!< (0x10) SPI Clock prescaler register */
|
__IOM uint32_t INTR_EN; /*!< (0x14) SPI Interrupt mask set or clear register */
|
__IM uint32_t STATUS1; /*!< (0x18) SPI Raw interrupt status register */
|
__IM uint32_t INTR_STATUS; /*!< (0x1C) SPI Masked interrupt status register */
|
__OM uint32_t INTR_CLR; /*!< (0x20) SPI Interrupt clear register */
|
__IOM uint32_t DMA_EN; /*!< (0x24) SPI DMA control register */
|
} SPI_TypeDef;
|
|
// CTRL0
|
#define SPI_CTRL0_DSS_POS 0U
|
#define SPI_CTRL0_DSS_MSK (0xfU << SPI_CTRL0_DSS_POS)
|
#define SPI_CTRL0_DSS(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTRL0_DSS_POS)) & SPI_CTRL0_DSS_MSK)
|
|
#define SPI_CTRL0_FRF_POS 4U
|
#define SPI_CTRL0_FRF_MSK (0x3U << SPI_CTRL0_FRF_POS)
|
#define SPI_CTRL0_FRF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTRL0_FRF_POS)) & SPI_CTRL0_FRF_MSK)
|
|
#define SPI_CTRL0_SPO_POS 6U
|
#define SPI_CTRL0_SPO_MSK (1U << SPI_CTRL0_SPO_POS)
|
|
#define SPI_CTRL0_SPH_POS 7U
|
#define SPI_CTRL0_SPH_MSK (1U << SPI_CTRL0_SPH_POS)
|
|
#define SPI_CTRL0_SCR_POS 8U
|
#define SPI_CTRL0_SCR_MSK (0xffU << SPI_CTRL0_SCR_POS)
|
#define SPI_CTRL0_SCR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTRL0_SCR_POS)) & SPI_CTRL0_SCR_MSK)
|
|
// CTRL1
|
#define SPI_CTRL1_LBM_POS 0U
|
#define SPI_CTRL1_LBM_MSK (1U << SPI_CTRL1_LBM_POS)
|
|
#define SPI_CTRL1_SSE_POS 1U
|
#define SPI_CTRL1_SSE_MSK (1U << SPI_CTRL1_SSE_POS)
|
|
#define SPI_CTRL1_MS_POS 2U
|
#define SPI_CTRL1_MS_MSK (1U << SPI_CTRL1_MS_POS)
|
|
#define SPI_CTRL1_SOD_POS 3U
|
#define SPI_CTRL1_SOD_MSK (1U << SPI_CTRL1_SOD_POS)
|
|
// STATUS0
|
#define SPI_STATUS0_TFE_POS 0U
|
#define SPI_STATUS0_TFE_MSK (1U << SPI_STATUS0_TFE_POS)
|
|
#define SPI_STATUS0_TNF_POS 1U
|
#define SPI_STATUS0_TNF_MSK (1U << SPI_STATUS0_TNF_POS)
|
|
#define SPI_STATUS0_RNE_POS 2U
|
#define SPI_STATUS0_RNE_MSK (1U << SPI_STATUS0_RNE_POS)
|
|
#define SPI_STATUS0_RFF_POS 3U
|
#define SPI_STATUS0_RFF_MSK (1U << SPI_STATUS0_RFF_POS)
|
|
#define SPI_STATUS0_BSY_POS 4U
|
#define SPI_STATUS0_BSY_MSK (1U << SPI_STATUS0_BSY_POS)
|
|
// PRESCALER
|
#define SPI_PRESCALER_POS 0U
|
#define SPI_PRESCALER_MSK (0xffU << SPI_PRESCALER_POS)
|
#define SPI_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << SPI_PRESCALER_POS)) & SPI_PRESCALER_MSK)
|
|
// INTR_EN
|
#define SPI_INTR_EN_ROR_POS 0U
|
#define SPI_INTR_EN_ROR_MSK (1U << SPI_INTR_EN_ROR_POS)
|
|
#define SPI_INTR_EN_RT_POS 1U
|
#define SPI_INTR_EN_RT_MSK (1U << SPI_INTR_EN_RT_POS)
|
|
#define SPI_INTR_EN_RX_POS 2U
|
#define SPI_INTR_EN_RX_MSK (1U << SPI_INTR_EN_RX_POS)
|
|
#define SPI_INTR_EN_TX_POS 3U
|
#define SPI_INTR_EN_TX_MSK (1U << SPI_INTR_EN_TX_POS)
|
|
// INTR_STATUS
|
#define SPI_INTR_STATUS_ROR_POS 0U
|
#define SPI_INTR_STATUS_ROR_MSK (1U << SPI_INTR_STATUS_ROR_POS)
|
|
#define SPI_INTR_STATUS_RT_POS 1U
|
#define SPI_INTR_STATUS_RT_MSK (1U << SPI_INTR_STATUS_RT_POS)
|
|
#define SPI_INTR_STATUS_RX_POS 2U
|
#define SPI_INTR_STATUS_RX_MSK (1U << SPI_INTR_STATUS_RX_POS)
|
|
#define SPI_INTR_STATUS_TX_POS 3U
|
#define SPI_INTR_STATUS_TX_MSK (1U << SPI_INTR_STATUS_TX_POS)
|
|
// INTR_CLR
|
#define SPI_INTR_CLR_ROR_POS 0U
|
#define SPI_INTR_CLR_ROR_MSK (1U << SPI_INTR_CLR_ROR_POS)
|
|
#define SPI_INTR_CLR_RT_POS 1U
|
#define SPI_INTR_CLR_RT_MSK (1U << SPI_INTR_CLR_RT_POS)
|
|
// DMA_EN
|
#define SPI_DMA_EN_RX_POS 0U
|
#define SPI_DMA_EN_RX_MSK (1U << SPI_DMA_EN_RX_POS)
|
|
#define SPI_DMA_EN_TX_POS 1U
|
#define SPI_DMA_EN_TX_MSK (1U << SPI_DMA_EN_TX_POS)
|
|
/* =========================================================================================================================== */
|
/* ================ I2C ================ */
|
/* =========================================================================================================================== */
|
|
/**
|
* @brief I2C
|
*/
|
typedef struct
|
{
|
__IOM uint32_t CTRL0; /*!< (0x00) Control Register 0 */
|
__IOM uint32_t CTRL1; /*!< (0x04) Control Register 1 */
|
__IOM uint32_t DATA; /*!< (0x08) Data Register */
|
__IOM uint32_t ADDR; /*!< (0x0c) Address Register */
|
__IOM uint32_t FIFO_TH; /*!< (0x10) FIFO Threshold Register */
|
__IM uint32_t INTR_STATUS; /*!< (0x14) Masked Interrupt Status */
|
__IOM uint32_t INTR_EN; /*!< (0x18) Interrupt Mask Set or Clear */
|
__IM uint32_t STATUS0; /*!< (0x1c) Raw Interrupt Status */
|
__IM uint32_t TX_ABORT; /*!< (0x20) Tx Abort Source Register */
|
__IOM uint32_t INTR_CLR; /*!< (0x24) Interrupt Clear Register */
|
__IM uint32_t STATUS1; /*!< (0x28) Status Register */
|
__IOM uint32_t SSCL; /*!< (0x2c) Standard SCL Timing */
|
__IOM uint32_t FSSCL; /*!< (0x30) Full Speed SCL Timing */
|
__IOM uint32_t HSSCL; /*!< (0x34) High Speed SCL Timing */
|
} I2C_TypeDef;
|
|
// CTRL0
|
#define I2C_CTRL0_ABORT_POS 1U
|
#define I2C_CTRL0_ABORT_MSK ((0x1UL) << I2C_CTRL0_ABORT_POS)
|
|
#define I2C_CTRL0_ENABLE_POS 0U
|
#define I2C_CTRL0_ENABLE_MSK ((0x1UL) << I2C_CTRL0_ENABLE_POS)
|
|
// CTRL1
|
#define I2C_CTRL1_SLAVE_DISABLE_POS (6U)
|
#define I2C_CTRL1_SLAVE_DISABLE_MSK ((0x1UL) << I2C_CTRL1_SLAVE_DISABLE_POS)
|
|
#define I2C_CTRL1_RESTART_EN_POS (5U)
|
#define I2C_CTRL1_RESTART_EN_MSK ((0x1UL) << I2C_CTRL1_RESTART_EN_POS)
|
|
#define I2C_CTRL1_10BITADDR_MASTER_POS (4U)
|
#define I2C_CTRL1_10BITADDR_MASTER_MSK ((0x1UL) << I2C_CTRL1_10BITADDR_MASTER_POS)
|
|
#define I2C_CTRL1_10BITADDR_SLAVE_POS (3U)
|
#define I2C_CTRL1_10BITADDR_SLAVE_MSK ((0x1UL) << I2C_CTRL1_10BITADDR_SLAVE_POS)
|
|
#define I2C_CTRL1_SPEED_POS (1U)
|
#define I2C_CTRL1_SPEED_MSK ((0x3UL) << I2C_CTRL1_SPEED_POS)
|
#define I2C_CTRL1_STANDARD_SPEED ((0x1UL) << I2C_CTRL1_SPEED_POS)
|
#define I2C_CTRL1_FAST_SPEED ((0x2UL) << I2C_CTRL1_SPEED_POS)
|
#define I2C_CTRL1_HIGH_SPEED ((0x3UL) << I2C_CTRL1_SPEED_POS)
|
|
#define I2C_CTRL1_MASTER_MODE_POS (0U)
|
#define I2C_CTRL1_MASTER_MODE_MSK ((0x1UL) << I2C_CTRL1_MASTER_MODE_POS)
|
|
// DATA
|
#define I2C_DATA_RESTART_POS (10U)
|
#define I2C_DATA_RESTART_MSK ((0x1UL) << I2C_DATA_RESTART_POS)
|
|
#define I2C_DATA_STOP_POS (9U)
|
#define I2C_DATA_STOP_MSK ((0x1UL) << I2C_DATA_STOP_POS)
|
|
#define I2C_DATA_CMD_POS (8U)
|
#define I2C_DATA_CMD_MSK ((0x1UL) << I2C_DATA_CMD_POS)
|
#define I2C_DATA_CMD_READ ((0x1UL) << I2C_DATA_CMD_POS)
|
#define I2C_DATA_CMD_WRITE ((0x0UL) << I2C_DATA_CMD_POS)
|
|
#define I2C_DATA_DAT_POS (0U)
|
#define I2C_DATA_DAT_MSK ((0xffUL) << I2C_DATA_DAT_POS)
|
|
// ADDR
|
#define I2C_ADDR_HS_CODE_POS 22U
|
#define I2C_ADDR_HS_CODE_MSK ((0x7UL) << I2C_ADDR_HS_CODE_POS)
|
#define I2C_ADDR_HS_CODE(x) (((uint32_t)(((uint32_t)(x)) << I2C_ADDR_HS_CODE_POS)) & I2C_ADDR_HS_CODE_MSK)
|
|
#define I2C_ADDR_SLV_ADDR_POS (12U)
|
#define I2C_ADDR_SLV_ADDR_MSK ((0x3ffUL) << I2C_ADDR_SLV_ADDR_POS)
|
#define I2C_ADDR_SLV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << I2C_ADDR_SLV_ADDR_POS)) & I2C_ADDR_SLV_ADDR_MSK)
|
|
#define I2C_ADDR_SPECIAL_POS 11U
|
#define I2C_ADDR_SPECIAL_MSK ((0x1UL) << I2C_ADDR_SPECIAL_POS)
|
|
#define I2C_ADDR_GC_OR_START_POS 10U
|
#define I2C_ADDR_GC_OR_START_MSK ((0x1UL) << I2C_ADDR_GC_OR_START_POS)
|
|
#define I2C_ADDR_TGT_ADDR_POS 0U
|
#define I2C_ADDR_TGT_ADDR_MSK ((0x3ffUL) << I2C_ADDR_TGT_ADDR_POS)
|
|
// FIFO_TH
|
#define I2C_FIFO_TH_TX_TL_POS 8U
|
#define I2C_FIFO_TH_TX_TL_MSK ((0xffUL) << I2C_FIFO_TH_TX_TL_POS)
|
#define I2C_FIFO_TH_TX_TL(x) (((uint32_t)(((uint32_t)(x)) << I2C_FIFO_TH_TX_TL_POS)) & I2C_FIFO_TH_TX_TL_MSK)
|
|
#define I2C_FIFO_TH_RX_TL_POS 0U
|
#define I2C_FIFO_TH_RX_TL_MSK ((0xffUL) << I2C_FIFO_TH_RX_TL_POS)
|
#define I2C_FIFO_TH_RX_TL(x) (((uint32_t)(((uint32_t)(x)) << I2C_FIFO_TH_RX_TL_POS)) & I2C_FIFO_TH_RX_TL_MSK)
|
|
// INTR_STATUS
|
// INTR_EN
|
// STATUS0
|
#define I2C_INTR_GEN_CALL_POS (11U)
|
#define I2C_INTR_GEN_CALL_MSK ((0x1UL) << I2C_INTR_GEN_CALL_POS)
|
|
#define I2C_INTR_START_DET_POS (10U)
|
#define I2C_INTR_START_DET_MSK ((0x1UL) << I2C_INTR_START_DET_POS)
|
|
#define I2C_INTR_STOP_DET_POS (9U)
|
#define I2C_INTR_STOP_DET_MSK ((0x1UL) << I2C_INTR_STOP_DET_POS)
|
|
#define I2C_INTR_ACTIVITY_POS (8U)
|
#define I2C_INTR_ACTIVITY_MSK ((0x1UL) << I2C_INTR_ACTIVITY_POS)
|
|
#define I2C_INTR_RX_DONE_POS (7U)
|
#define I2C_INTR_RX_DONE_MSK ((0x1UL) << I2C_INTR_RX_DONE_POS)
|
|
#define I2C_INTR_TX_ABRT_POS (6U)
|
#define I2C_INTR_TX_ABRT_MSK ((0x1UL) << I2C_INTR_TX_ABRT_POS)
|
|
#define I2C_INTR_RD_REQ_POS (5U)
|
#define I2C_INTR_RD_REQ_MSK ((0x1UL) << I2C_INTR_RD_REQ_POS)
|
|
#define I2C_INTR_TX_EMPTY_POS (4U)
|
#define I2C_INTR_TX_EMPTY_MSK ((0x1UL) << I2C_INTR_TX_EMPTY_POS)
|
|
#define I2C_INTR_TX_OVER_POS (3U)
|
#define I2C_INTR_TX_OVER_MSK ((0x1UL) << I2C_INTR_TX_OVER_POS)
|
|
#define I2C_INTR_RX_FULL_POS (2U)
|
#define I2C_INTR_RX_FULL_MSK ((0x1UL) << I2C_INTR_RX_FULL_POS)
|
|
#define I2C_INTR_RX_OVER_POS (1U)
|
#define I2C_INTR_RX_OVER_MSK ((0x1UL) << I2C_INTR_RX_OVER_POS)
|
|
#define I2C_INTR_RX_UNDER_POS (0U)
|
#define I2C_INTR_RX_UNDER_MSK ((0x1UL) << I2C_INTR_RX_UNDER_POS)
|
|
#define I2C_INTR_ALL_MSK (0xfffUL)
|
|
// TX_ABORT
|
#define I2C_TX_ABORT_SLVRD_INTX_POS (15U)
|
#define I2C_TX_ABORT_SLVRD_INTX_MSK ((0x1UL) << I2C_TX_ABORT_SLVRD_INTX_POS)
|
|
#define I2C_TX_ABORT_SLV_ARBLOST_POS (14U)
|
#define I2C_TX_ABORT_SLV_ARBLOST_MSK ((0x1UL) << I2C_TX_ABORT_SLV_ARBLOST_POS)
|
|
#define I2C_TX_ABORT_SLVFLUSH_TXFIFO_POS (13U)
|
#define I2C_TX_ABORT_SLVFLUSH_TXFIFO_MSK ((0x1UL) << I2C_TX_ABORT_SLVFLUSH_TXFIFO_POS)
|
|
#define I2C_TX_ABORT_LOST_POS (12U)
|
#define I2C_TX_ABORT_LOST_MSK ((0x1UL) << I2C_TX_ABORT_LOST_POS)
|
|
#define I2C_TX_ABORT_MASTER_DIS_POS (11U)
|
#define I2C_TX_ABORT_MASTER_DIS_MSK ((0x1UL) << I2C_TX_ABORT_MASTER_DIS_POS)
|
|
#define I2C_TX_ABORT_10B_RD_NORSTRT_POS (10U)
|
#define I2C_TX_ABORT_10B_RD_NORSTRT_MSK ((0x1UL) << I2C_TX_ABORT_10B_RD_NORSTRT_POS)
|
|
#define I2C_TX_ABORT_SBYTE_NORSTRT_POS (9U)
|
#define I2C_TX_ABORT_SBYTE_NORSTRT_MSK ((0x1UL) << I2C_TX_ABORT_SBYTE_NORSTRT_POS)
|
|
#define I2C_TX_ABORT_HS_NORSTRT_POS (8U)
|
#define I2C_TX_ABORT_HS_NORSTRT_MSK ((0x1UL) << I2C_TX_ABORT_HS_NORSTRT_POS)
|
|
#define I2C_TX_ABORT_SBYTE_ACKDET_POS (7U)
|
#define I2C_TX_ABORT_SBYTE_ACKDET_MSK ((0x1UL) << I2C_TX_ABORT_SBYTE_ACKDET_POS)
|
|
#define I2C_TX_ABORT_HS_ACKDET_POS (6U)
|
#define I2C_TX_ABORT_HS_ACKDET_MSK ((0x1UL) << I2C_TX_ABORT_HS_ACKDET_POS)
|
|
#define I2C_TX_ABORT_GCALL_READ_POS (5U)
|
#define I2C_TX_ABORT_GCALL_READ_MSK ((0x1UL) << I2C_TX_ABORT_GCALL_READ_POS)
|
|
#define I2C_TX_ABORT_GCALL_NOACK_POS (4U)
|
#define I2C_TX_ABORT_GCALL_NOACK_MSK ((0x1UL) << I2C_TX_ABORT_GCALL_NOACK_POS)
|
|
#define I2C_TX_ABORT_TXDATA_NOACK_POS (3U)
|
#define I2C_TX_ABORT_TXDATA_NOACK_MSK ((0x1UL) << I2C_TX_ABORT_TXDATA_NOACK_POS)
|
|
#define I2C_TX_ABORT_10ADDR2_NOACK_POS (2U)
|
#define I2C_TX_ABORT_10ADDR2_NOACK_MSK ((0x1UL) << I2C_TX_ABORT_10ADDR2_NOACK_POS)
|
|
#define I2C_TX_ABORT_10ADDR1_NOACK_POS (1U)
|
#define I2C_TX_ABORT_10ADDR1_NOACK_MSK ((0x1UL) << I2C_TX_ABORT_10ADDR1_NOACK_POS)
|
|
#define I2C_TX_ABORT_7B_ADDR_NOACK_POS (0U)
|
#define I2C_TX_ABORT_7B_ADDR_NOACK_MSK ((0x1UL) << I2C_TX_ABORT_7B_ADDR_NOACK_POS)
|
|
// INTR_CLR
|
#define I2C_INTR_CLR_GEN_CALL_POS (10U)
|
#define I2C_INTR_CLR_GEN_CALL_MSK ((0x1UL) << I2C_INTR_CLR_GEN_CALL_POS)
|
|
#define I2C_INTR_CLR_START_DET_POS (9U)
|
#define I2C_INTR_CLR_START_DET_MSK ((0x1UL) << I2C_INTR_CLR_START_DET_POS)
|
|
#define I2C_INTR_CLR_STOP_DET_POS (8U)
|
#define I2C_INTR_CLR_STOP_DET_MSK ((0x1UL) << I2C_INTR_CLR_STOP_DET_POS)
|
|
#define I2C_INTR_CLR_ACTIVITY_POS (7U)
|
#define I2C_INTR_CLR_ACTIVITY_MSK ((0x1UL) << I2C_INTR_CLR_ACTIVITY_POS)
|
|
#define I2C_INTR_CLR_RX_DONE_POS (6U)
|
#define I2C_INTR_CLR_RX_DONE_MSK ((0x1UL) << I2C_INTR_CLR_RX_DONE_POS)
|
|
#define I2C_INTR_CLR_TX_ABRT_POS (5U)
|
#define I2C_INTR_CLR_TX_ABRT_MSK ((0x1UL) << I2C_INTR_CLR_TX_ABRT_POS)
|
|
#define I2C_INTR_CLR_RD_REQ_POS (4U)
|
#define I2C_INTR_CLR_RD_REQ_MSK ((0x1UL) << I2C_INTR_CLR_RD_REQ_POS)
|
|
#define I2C_INTR_CLR_TX_OVER_POS (3U)
|
#define I2C_INTR_CLR_TX_OVER_MSK ((0x1UL) << I2C_INTR_CLR_TX_OVER_POS)
|
|
#define I2C_INTR_CLR_RX_OVER_POS (2U)
|
#define I2C_INTR_CLR_RX_OVER_MSK ((0x1UL) << I2C_INTR_CLR_RX_OVER_POS)
|
|
#define I2C_INTR_CLR_RX_UNDER_POS (1U)
|
#define I2C_INTR_CLR_RX_UNDER_MSK ((0x1UL) << I2C_INTR_CLR_RX_UNDER_POS)
|
|
#define I2C_INTR_CLR_ALL_POS (0U)
|
#define I2C_INTR_CLR_ALL_MSK ((0x1UL) << I2C_INTR_CLR_ALL_POS)
|
|
// STATUS1
|
#define I2C_STATUS1_RXFL_POS 16U
|
#define I2C_STATUS1_RXFL_MSK ((0xfUL) << I2C_STATUS1_RXFL_POS)
|
|
#define I2C_STATUS1_TXFL_POS 12U
|
#define I2C_STATUS1_TXFL_MSK ((0xfUL) << I2C_STATUS1_TXFL_POS)
|
|
#define I2C_STATUS1_SLV_ACTIVITY_POS (6U)
|
#define I2C_STATUS1_SLV_ACTIVITY_MSK ((0x1UL) << I2C_STATUS1_SLV_ACTIVITY_POS)
|
|
#define I2C_STATUS1_MST_ACTIVITY_POS (5U)
|
#define I2C_STATUS1_MST_ACTIVITY_MSK ((0x1UL) << I2C_STATUS1_MST_ACTIVITY_POS)
|
|
#define I2C_STATUS1_RFF_POS (4U)
|
#define I2C_STATUS1_RFF_MSK ((0x1UL) << I2C_STATUS1_RFF_POS)
|
|
#define I2C_STATUS1_RFNE_POS (3U)
|
#define I2C_STATUS1_RFNE_MSK ((0x1UL) << I2C_STATUS1_RFNE_POS)
|
|
#define I2C_STATUS1_TFE_POS (2U)
|
#define I2C_STATUS1_TFE_MSK ((0x1UL) << I2C_STATUS1_TFE_POS)
|
|
#define I2C_STATUS1_TFNF_POS (1U)
|
#define I2C_STATUS1_TFNF_MSK ((0x1UL) << I2C_STATUS1_TFNF_POS)
|
|
#define I2C_STATUS1_ACTIVITY_POS (0U)
|
#define I2C_STATUS1_ACTIVITY_MSK ((0x1UL) << I2C_STATUS1_ACTIVITY_POS)
|
|
// SSCL
|
#define I2C_SSCL_LCNT_POS (16U)
|
#define I2C_SSCL_LCNT_MSK ((0xffffUL) << I2C_SSCL_LCNT_POS)
|
#define I2C_SSCL_LCNT(x) (((uint32_t)(((uint32_t)(x)) << I2C_SSCL_LCNT_POS)) & I2C_SSCL_LCNT_MSK)
|
|
#define I2C_SSCL_HCNT_POS (0U)
|
#define I2C_SSCL_HCNT_MSK ((0xffffUL) << I2C_SSCL_HCNT_POS)
|
#define I2C_SSCL_HCNT(x) (((uint32_t)(((uint32_t)(x)) << I2C_SSCL_HCNT_POS)) & I2C_SSCL_HCNT_MSK)
|
|
// FSSCL
|
#define I2C_FSSCL_LCNT_POS (16U)
|
#define I2C_FSSCL_LCNT_MSK ((0xffffUL) << I2C_FSSCL_LCNT_POS)
|
#define I2C_FSSCL_LCNT(x) (((uint32_t)(((uint32_t)(x)) << I2C_FSSCL_LCNT_POS)) & I2C_FSSCL_LCNT_MSK)
|
|
#define I2C_FSSCL_HCNT_POS (0U)
|
#define I2C_FSSCL_HCNT_MSK ((0xffffUL) << I2C_FSSCL_HCNT_POS)
|
#define I2C_FSSCL_HCNT(x) (((uint32_t)(((uint32_t)(x)) << I2C_FSSCL_HCNT_POS)) & I2C_FSSCL_HCNT_MSK)
|
|
// HSSCL
|
#define I2C_HSSCL_LCNT_POS (16U)
|
#define I2C_HSSCL_LCNT_MSK ((0xffffUL) << I2C_HSSCL_LCNT_POS)
|
#define I2C_HSSCL_LCNT(x) (((uint32_t)(((uint32_t)(x)) << I2C_HSSCL_LCNT_POS)) & I2C_HSSCL_LCNT_MSK)
|
|
#define I2C_HSSCL_HCNT_POS (0U)
|
#define I2C_HSSCL_HCNT_MSK ((0xffffUL) << I2C_HSSCL_HCNT_POS)
|
#define I2C_HSSCL_HCNT(x) (((uint32_t)(((uint32_t)(x)) << I2C_HSSCL_HCNT_POS)) & I2C_HSSCL_HCNT_MSK)
|
|
/* =========================================================================================================================== */
|
/* ================ FLASH_CTRL ================ */
|
/* =========================================================================================================================== */
|
|
/**
|
* @brief Flash
|
*/
|
|
typedef struct
|
{
|
__IOM uint32_t CTRL; /*!< (0x00) FLASH control register */
|
__IOM uint32_t CMD; /*!< (0x04) FLASH command register */
|
__IOM uint32_t ADDR; /*!< (0x08) FLASH address register */
|
uint32_t RESERVED0[2];
|
__IOM uint8_t DATA; /*!< (0x14) FLASH data register */
|
uint8_t RESERVED1[3];
|
__IOM uint32_t MCMD; /*!< (0x18) FLASH memory command register */
|
__IOM uint32_t STATUS; /*!< (0x1C) FLASH status register */
|
} FLASH_CTRL_TypeDef;
|
|
// CTRL
|
#define FLASH_CTRL_TIMEOUT_MSK (0xFFFFU)
|
#define FLASH_CTRL_TIMEOUT_POS (0U)
|
#define FLASH_CTRL_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_TIMEOUT_POS)) & FLASH_CTRL_TIMEOUT_MSK)
|
#define FLASH_CTRL_CSHIGH_MSK (0xF0000U)
|
#define FLASH_CTRL_CSHIGH_POS (16U)
|
#define FLASH_CTRL_CSHIGH(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_CSHIGH_POS)) & FLASH_CTRL_CSHIGH_MSK)
|
#define FLASH_CTRL_D_PRFTCH_DIS_MSK (0x200000U)
|
#define FLASH_CTRL_D_PRFTCH_DIS_POS (21U)
|
#define FLASH_CTRL_D_PRFTCH_DIS(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_D_PRFTCH_DIS_POS)) & FLASH_CTRL_D_PRFTCH_DIS_MSK)
|
#define FLASH_CTRL_INTEN_MSK (0x400000U)
|
#define FLASH_CTRL_INTEN_POS (22U)
|
#define FLASH_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_INTEN_POS)) & FLASH_CTRL_INTEN_MSK)
|
#define FLASH_CTRL_MODE3_MSK (0x800000U)
|
#define FLASH_CTRL_MODE3_POS (23U)
|
#define FLASH_CTRL_MODE3(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_MODE3_POS)) & FLASH_CTRL_MODE3_MSK)
|
#define FLASH_CTRL_PRFTCH_DIS_MSK (0x8000000U)
|
#define FLASH_CTRL_PRFTCH_DIS_POS (27U)
|
#define FLASH_CTRL_PRFTCH_DIS(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_PRFTCH_DIS_POS)) & FLASH_CTRL_PRFTCH_DIS_MSK)
|
#define FLASH_CTRL_DUAL_MSK (0x10000000U)
|
#define FLASH_CTRL_DUAL_POS (28U)
|
#define FLASH_CTRL_DUAL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_DUAL_POS)) & FLASH_CTRL_DUAL_MSK)
|
#define FLASH_CTRL_RFCLK_MSK (0x20000000U)
|
#define FLASH_CTRL_RFCLK_POS (29U)
|
#define FLASH_CTRL_RFCLK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_RFCLK_POS)) & FLASH_CTRL_RFCLK_MSK)
|
#define FLASH_CTRL_FBCLK_MSK (0x40000000U)
|
#define FLASH_CTRL_FBCLK_POS (30U)
|
#define FLASH_CTRL_FBCLK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FBCLK_POS)) & FLASH_CTRL_FBCLK_MSK)
|
#define FLASH_CTRL_DMAEN_MSK (0x80000000U)
|
#define FLASH_CTRL_DMAEN_POS (31U)
|
#define FLASH_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_DMAEN_POS)) & FLASH_CTRL_DMAEN_MSK)
|
|
// CMD
|
#define FLASH_CMD_DATALEN_MSK (0x3FFFU)
|
#define FLASH_CMD_DATALEN_POS (0U)
|
#define FLASH_CMD_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMD_DATALEN_POS)) & FLASH_CMD_DATALEN_MSK)
|
#define FLASH_CMD_POLL_MSK (0x4000U)
|
#define FLASH_CMD_POLL_POS (14U)
|
#define FLASH_CMD_POLL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMD_POLL_POS)) & FLASH_CMD_POLL_MSK)
|
#define FLASH_CMD_DOUT_MSK (0x8000U)
|
#define FLASH_CMD_DOUT_POS (15U)
|
#define FLASH_CMD_DOUT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMD_DOUT_POS)) & FLASH_CMD_DOUT_MSK)
|
#define FLASH_CMD_INTLEN_MSK (0x70000U)
|
#define FLASH_CMD_INTLEN_POS (16U)
|
#define FLASH_CMD_INTLEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMD_INTLEN_POS)) & FLASH_CMD_INTLEN_MSK)
|
#define FLASH_CMD_FIELDFORM_MSK (0x180000U)
|
#define FLASH_CMD_FIELDFORM_POS (19U)
|
#define FLASH_CMD_FIELDFORM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMD_FIELDFORM_POS)) & FLASH_CMD_FIELDFORM_MSK)
|
#define FLASH_CMD_FRAMEFORM_MSK (0xE00000U)
|
#define FLASH_CMD_FRAMEFORM_POS (21U)
|
#define FLASH_CMD_FRAMEFORM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMD_FRAMEFORM_POS)) & FLASH_CMD_FRAMEFORM_MSK)
|
#define FLASH_CMD_OPCODE_MSK (0xFF000000U)
|
#define FLASH_CMD_OPCODE_POS (24U)
|
#define FLASH_CMD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMD_OPCODE_POS)) & FLASH_CMD_OPCODE_MSK)
|
|
// ADDR
|
#define FLASH_ADDR_ADDRESS_MSK (0xFFFFFFFFU)
|
#define FLASH_ADDR_ADDRESS_POS (0U)
|
#define FLASH_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLASH_ADDR_ADDRESS_POS)) & FLASH_ADDR_ADDRESS_MSK)
|
|
// DATA
|
#define FLASH_DATA_DATA_MSK (0xFFFFFFFFU)
|
#define FLASH_DATA_DATA_POS (0U)
|
#define FLASH_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_DATA_DATA_POS)) & FLASH_DATA_DATA_MSK)
|
|
// MCMD
|
#define FLASH_MCMD_POLL_MSK (0x4000U)
|
#define FLASH_MCMD_POLL_POS (14U)
|
#define FLASH_MCMD_POLL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MCMD_POLL_POS)) & FLASH_MCMD_POLL_MSK)
|
#define FLASH_MCMD_DOUT_MSK (0x8000U)
|
#define FLASH_MCMD_DOUT_POS (15U)
|
#define FLASH_MCMD_DOUT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MCMD_DOUT_POS)) & FLASH_MCMD_DOUT_MSK)
|
#define FLASH_MCMD_INTLEN_MSK (0x70000U)
|
#define FLASH_MCMD_INTLEN_POS (16U)
|
#define FLASH_MCMD_INTLEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MCMD_INTLEN_POS)) & FLASH_MCMD_INTLEN_MSK)
|
#define FLASH_MCMD_FIELDFORM_MSK (0x180000U)
|
#define FLASH_MCMD_FIELDFORM_POS (19U)
|
#define FLASH_MCMD_FIELDFORM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MCMD_FIELDFORM_POS)) & FLASH_MCMD_FIELDFORM_MSK)
|
#define FLASH_MCMD_FRAMEFORM_MSK (0xE00000U)
|
#define FLASH_MCMD_FRAMEFORM_POS (21U)
|
#define FLASH_MCMD_FRAMEFORM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MCMD_FRAMEFORM_POS)) & FLASH_MCMD_FRAMEFORM_MSK)
|
#define FLASH_MCMD_OPCODE_MSK (0xFF000000U)
|
#define FLASH_MCMD_OPCODE_POS (24U)
|
#define FLASH_MCMD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MCMD_OPCODE_POS)) & FLASH_MCMD_OPCODE_MSK)
|
|
// STATUS
|
#define FLASH_STATUS_MCINIT_MSK (0x1U)
|
#define FLASH_STATUS_MCINIT_POS (0U)
|
#define FLASH_STATUS_MCINIT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STATUS_MCINIT_POS)) & FLASH_STATUS_MCINIT_MSK)
|
#define FLASH_STATUS_CMD_MSK (0x2U)
|
#define FLASH_STATUS_CMD_POS (1U)
|
#define FLASH_STATUS_CMD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STATUS_CMD_POS)) & FLASH_STATUS_CMD_MSK)
|
#define FLASH_STATUS_RESET_MSK (0x10U)
|
#define FLASH_STATUS_RESET_POS (4U)
|
#define FLASH_STATUS_RESET(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STATUS_RESET_POS)) & FLASH_STATUS_RESET_MSK)
|
#define FLASH_STATUS_INTRQ_MSK (0x20U)
|
#define FLASH_STATUS_INTRQ_POS (5U)
|
#define FLASH_STATUS_INTRQ(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STATUS_INTRQ_POS)) & FLASH_STATUS_INTRQ_MSK)
|
#define FLASH_STATUS_VERSION_MSK (0xFF000000U)
|
#define FLASH_STATUS_VERSION_POS (24U)
|
#define FLASH_STATUS_VERSION(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STATUS_VERSION_POS)) & FLASH_STATUS_VERSION_MSK)
|
|
/* =========================================================================================================================== */
|
/* ================ EFUSE_CTRL ================ */
|
/* =========================================================================================================================== */
|
|
/**
|
* @brief eFuse controller
|
*/
|
|
typedef struct
|
{
|
__IOM uint32_t CTRL; /*!< (0x00) eFuse control register */
|
__IOM uint32_t ADDR; /*!< (0x04) eFuse address register */
|
__IOM uint32_t LENGTH; /*!< (0x08) eFuse length register */
|
__IOM uint32_t SEQUENCE_CNT; /*!< (0x0C) eFuse sequence count register */
|
} EFUSE_CTRL_TypeDef;
|
|
// CTRL
|
#define EFUSE_CTRL_ACCESS_EN_POS 7U
|
#define EFUSE_CTRL_ACCESS_EN_MSK (1U << EFUSE_CTRL_ACCESS_EN_POS)
|
|
#define EFUSE_CTRL_SOFT_RST_POS 6U
|
#define EFUSE_CTRL_SOFT_RST_MSK (1U << EFUSE_CTRL_SOFT_RST_POS)
|
|
#define EFUSE_CTRL_POWER_DOWN_POS 5U
|
#define EFUSE_CTRL_POWER_DOWN_MSK (1U << EFUSE_CTRL_POWER_DOWN_POS)
|
|
#define EFUSE_CTRL_TIME_DOUBLE_POS 4U
|
#define EFUSE_CTRL_TIME_DOUBLE_MSK (1U << EFUSE_CTRL_TIME_DOUBLE_POS)
|
|
#define EFUSE_CTRL_ACCESS_MODE_POS 0U
|
#define EFUSE_CTRL_ACCESS_MODE_MSK (0x7U << EFUSE_CTRL_ACCESS_MODE_POS)
|
#define EFUSE_CTRL_ACCESS_MODE(x) (((uint32_t)(((uint32_t)(x)) << EFUSE_CTRL_ACCESS_MODE_POS)) & EFUSE_CTRL_ACCESS_MODE_MSK)
|
|
// ADDR
|
#define EFUSE_ADDR_BYTE_ADDR_POS 3U
|
#define EFUSE_ADDR_BYTE_ADDR_MSK (0x7FU << EFUSE_ADDR_BYTE_ADDR_POS)
|
#define EFUSE_ADDR_BYTE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << EFUSE_ADDR_BYTE_ADDR_POS)) & EFUSE_ADDR_BYTE_ADDR_MSK)
|
|
#define EFUSE_ADDR_BIT_OFFSET_POS 0U
|
#define EFUSE_ADDR_BIT_OFFSET_MSK (0x7U << EFUSE_ADDR_BIT_OFFSET_POS)
|
#define EFUSE_ADDR_BIT_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << EFUSE_ADDR_BIT_OFFSET_POS)) & EFUSE_ADDR_BIT_OFFSET_MSK)
|
|
// SEQUENCE_CNT
|
#define EFUSE_SEQUENCE_CNT_BUSY_POS 31U
|
#define EFUSE_SEQUENCE_CNT_BUSY_MSK (0x1U << EFUSE_SEQUENCE_CNT_BUSY_POS)
|
|
#define EFUSE_SEQUENCE_CNT_VALUE_POS 0U
|
#define EFUSE_SEQUENCE_CNT_VALUE_MSK (0x3FFU << EFUSE_SEQUENCE_CNT_VALUE_POS)
|
|
/* =========================================================================================================================== */
|
/* ================ TIMER ================ */
|
/* =========================================================================================================================== */
|
|
/**
|
* @brief Timer
|
*/
|
|
typedef struct
|
{
|
__IOM uint32_t CTRL; /*!< (0x00) Timer Control */
|
__IOM uint32_t VALUE; /*!< (0x04) Timer Counter Current Value */
|
__IOM uint32_t RELOAD; /*!< (0x08) Reload value */
|
union
|
{
|
__IOM uint32_t INTR_STATUS; /*!< (0x0C) Timer Interrupt Status, Write one to lear */
|
__IOM uint32_t INTR_CLR;
|
};
|
} TIMER_TypeDef;
|
|
// CTRL
|
#define TIMER_CTRL_INT_EN_POS 3U
|
#define TIMER_CTRL_INT_EN_MSK (1U << TIMER_CTRL_INT_EN_POS)
|
#define TIMER_CTRL_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TIMER_CTRL_INT_EN_POS)) & TIMER_CTRL_INT_EN_MSK)
|
|
#define TIMER_CTRL_EXTIN_POS 1U
|
#define TIMER_CTRL_EXTIN_MSK (0x3U << TIMER_CTRL_EXTIN_POS)
|
#define TIMER_CTRL_EXTIN(x) (((uint32_t)(((uint32_t)(x)) << TIMER_CTRL_EXTIN_POS)) & TIMER_CTRL_EXTIN_MSK)
|
|
#define TIMER_CTRL_ENABLE_POS 0U
|
#define TIMER_CTRL_ENABLE_MSK (1U << TIMER_CTRL_ENABLE_POS)
|
|
// INTR_CLR
|
#define TIMER_INTR_CLR_POS 0U
|
#define TIMER_INTR_CLR_MSK (1U << TIMER_INTR_CLR_POS)
|
|
/* =========================================================================================================================== */
|
/* ================ DUAL TIMER ================ */
|
/* =========================================================================================================================== */
|
|
/**
|
* @brief Dual-Timer
|
*/
|
|
typedef struct
|
{
|
__IOM uint32_t LOAD; /*!< (0x00) Timer Load */
|
__IM uint32_t VALUE; /*!< (0x04) Timer Counter Current Value */
|
__IOM uint32_t CTRL; /*!< (0x08) Timer Control */
|
__OM uint32_t INTR_CLR; /*!< (0x0C) Timer Interrupt Clear */
|
__IM uint32_t STATUS; /*!< (0x10) Timer Raw Interrupt Status */
|
__IM uint32_t INTR_STATUS; /*!< (0x14) Timer Masked Interrupt Status */
|
__IOM uint32_t BG_LOAD; /*!< (0x18) Background Load Register */
|
} DUAL_TIMER_TypeDef;
|
|
// CTRL
|
#define DTIMER_CTRL_EN_POS 7U
|
#define DTIMER_CTRL_EN_MSK (0x1U << DTIMER_CTRL_EN_POS)
|
#define DTIMER_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << DTIMER_CTRL_EN_POS)) & DTIMER_CTRL_EN_MSK)
|
|
#define DTIMER_CTRL_MODE_POS 6U
|
#define DTIMER_CTRL_MODE_MSK (0x1U << DTIMER_CTRL_MODE_POS)
|
|
#define DTIMER_CTRL_INT_EN_POS 5U
|
#define DTIMER_CTRL_INT_EN_MSK (0x1U << DTIMER_CTRL_INT_EN_POS)
|
#define DTIMER_CTRL_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << DTIMER_CTRL_INT_EN_POS)) & DTIMER_CTRL_INT_EN_MSK)
|
|
#define DTIMER_CTRL_PRESCALE_POS 2U
|
#define DTIMER_CTRL_PRESCALE_MSK (0x3U << DTIMER_CTRL_PRESCALE_POS)
|
#define DTIMER_CTRL_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << DTIMER_CTRL_PRESCALE_POS)) & DTIMER_CTRL_PRESCALE_MSK)
|
|
#define DTIMER_CTRL_SIZE_POS 1U
|
#define DTIMER_CTRL_SIZE_MSK (0x1U << DTIMER_CTRL_SIZE_POS)
|
#define DTIMER_CTRL_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DTIMER_CTRL_SIZE_POS)) & DTIMER_CTRL_SIZE_MSK)
|
|
#define DTIMER_CTRL_ONE_SHOT_POS 0U
|
#define DTIMER_CTRL_ONE_SHOT_MSK (0x1U << DTIMER_CTRL_ONE_SHOT_POS)
|
|
// STATUS
|
#define DTIMER_STATUS_MSK 1U
|
|
/* =========================================================================================================================== */
|
/* ================ RTC ================ */
|
/* =========================================================================================================================== */
|
|
/**
|
* @brief RTC
|
*/
|
|
typedef struct
|
{
|
__IM uint32_t DATA; /*!< (0x00) Data Register */
|
__IOM uint32_t MATCH; /*!< (0x04) Match Register */
|
__IOM uint32_t LOAD; /*!< (0x08) Load Register */
|
__IOM uint32_t CTRL; /*!< (0x0C) Control Register */
|
__IOM uint32_t INTR_EN; /*!< (0x10) Interrupt Mask Set or Clear register */
|
__IM uint32_t STATUS; /*!< (0x14) Raw Interrupt Status */
|
__IM uint32_t INTR_STATUS; /*!< (0x18) Masked Interrupt Status */
|
__OM uint32_t INTR_CLR; /*!< (0x1C) Interrupt Clear Register */
|
uint32_t RESERVED0[4];
|
__IOM uint32_t CALIB; /*!< (0x30) CLK 1HZ calibration Register */
|
uint32_t RESERVED1[2];
|
__IOM uint32_t MEASURE; /*!< (0x3C) CLK 1HZ measure Register */
|
__IOM uint32_t TICK_INTR; /*!< (0x40) CLK 1HZ Interrupt Register */
|
} RTC_TypeDef;
|
|
// CTRL
|
#define RTC_CTRL_START_MSK 1U
|
|
// INTR_EN
|
#define RTC_INTR_EN_MSK 1U
|
|
// INTR_STATUS
|
#define RTC_INTR_STATUS_MSK 1U
|
|
// INTR_CLR
|
#define RTC_INTR_CLR_MSK 1U
|
|
// CALIB
|
#define RTC_CALIB_FRACTION_ADJ_POS 0U
|
#define RTC_CALIB_FRACTION_ADJ_MSK (0xfU << RTC_CALIB_FRACTION_ADJ_POS)
|
#define RTC_CALIB_FRACTION_ADJ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CALIB_FRACTION_ADJ_POS)) & RTC_CALIB_FRACTION_ADJ_MSK)
|
|
#define RTC_CALIB_FRACTION_POL_POS 4U
|
#define RTC_CALIB_FRACTION_POL_MSK (1U << RTC_CALIB_FRACTION_POL_POS)
|
#define RTC_CALIB_FRACTION_POL(x) (((uint32_t)(((uint32_t)(x)) << RTC_CALIB_FRACTION_POL_POS)) & RTC_CALIB_FRACTION_POL_MSK)
|
|
#define RTC_CALIB_INTEGER_ADJ_POS 5U
|
#define RTC_CALIB_INTEGER_ADJ_MSK (0x7ffU << RTC_CALIB_INTEGER_ADJ_POS)
|
#define RTC_CALIB_INTEGER_ADJ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CALIB_INTEGER_ADJ_POS)) & RTC_CALIB_INTEGER_ADJ_MSK)
|
|
#define RTC_CALIB_INTEGER_POL_POS 16U
|
#define RTC_CALIB_INTEGER_POL_MSK (1U << RTC_CALIB_INTEGER_POL_POS)
|
#define RTC_CALIB_INTEGER_POL(x) (((uint32_t)(((uint32_t)(x)) << RTC_CALIB_INTEGER_POL_POS)) & RTC_CALIB_INTEGER_POL_MSK)
|
|
#define RTC_CALIB_EN_POS 17U
|
#define RTC_CALIB_EN_MSK (1U << RTC_CALIB_EN_POS)
|
|
// MEASURE
|
#define RTC_MEASURE_CNT_POS 0U
|
#define RTC_MEASURE_CNT_MSK (0x001fffffU << RTC_MEASURE_CNT_POS)
|
|
#define RTC_MEASURE_DONE_POS 26U
|
#define RTC_MEASURE_DONE_MSK (0x3U << RTC_MEASURE_DONE_POS)
|
|
#define RTC_MEASURE_TIME_POS 28U
|
#define RTC_MEASURE_TIME_MSK (0x7U << RTC_MEASURE_TIME_POS)
|
#define RTC_MEASURE_TIME(x) (((uint32_t)(((uint32_t)(x)) << RTC_MEASURE_TIME_POS)) & RTC_MEASURE_TIME_MSK)
|
|
#define RTC_MEASURE_EN_POS 31U
|
#define RTC_MEASURE_EN_MSK (1U << RTC_MEASURE_EN_POS)
|
|
// TICK_INTR
|
#define RTC_TICK_INTR_CLR_POS 0U
|
#define RTC_TICK_INTR_CLR_MSK (1U << RTC_TICK_INTR_CLR_POS)
|
|
#define RTC_TICK_INTR_STATUS_POS 1U
|
#define RTC_TICK_INTR_STATUS_MSK (1U << RTC_TICK_INTR_STATUS_POS)
|
|
#define RTC_TICK_INTR_EN_POS 31U
|
#define RTC_TICK_INTR_EN_MSK (1U << RTC_TICK_INTR_EN_POS)
|
|
/* =========================================================================================================================== */
|
/* ================ WDT ================ */
|
/* =========================================================================================================================== */
|
|
/**
|
* @brief WDT
|
*/
|
|
typedef struct
|
{
|
__IOM uint32_t LOAD; /*!< (0x000) WDT Load Register */
|
__IM uint32_t VALUE; /*!< (0x004) WDT Value Register */
|
__IOM uint32_t CTRL; /*!< (0x008) WDT Control Register */
|
__OM uint32_t INTR_CLR; /*!< (0x00C) WDT Interrupt Clear Register */
|
__IM uint32_t STATUS; /*!< (0x010) WDT Raw Interrupt Register */
|
__IM uint32_t INTR_STATUS; /*!< (0x014) WDT Masked Interrupt Register */
|
uint32_t RESERVED0[762];
|
__IOM uint32_t LOCK; /*!< (0xC00) WDT Lock Register */
|
} WDT_TypeDef;
|
|
// CTRL
|
#define WDT_CTRL_INT_EN_MSK (1U)
|
#define WDT_CTRL_RESET_EN_MSK (2U)
|
|
// STATUS
|
#define WDT_STATUS_MSK (1U)
|
|
// INTR_STATUS
|
#define WDT_INTR_STATUS_MSK (1U)
|
|
/* =========================================================================================================================== */
|
/* ================ PWM ================ */
|
/* =========================================================================================================================== */
|
|
/**
|
* @brief PWM
|
*/
|
|
typedef struct
|
{
|
__IOM uint32_t CFG[5]; /*!< (0x00) PWM Configure Register */
|
uint32_t RESERVED0[3];
|
__IOM uint32_t CTRL; /*!< (0x20) PWM General Control Register */
|
__IOM uint32_t PHASE[2]; /*!< (0x24) PWM Phase Control Register */
|
uint32_t RESERVED1[1];
|
__OM uint32_t INTR_CLR; /*!< (0x30) PWM Interrupt Clear Register */
|
__IM uint32_t INTR_STATUS; /*!< (0x34) PWM Interrupt Status Register */
|
} PWM_TypeDef;
|
|
// CFG
|
#define PWM_PRESCALER_POS 28U
|
#define PWM_PRESCALER_MSK (0xfU << PWM_PRESCALER_POS)
|
#define PWM_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PWM_PRESCALER_POS)) & PWM_PRESCALER_MSK)
|
|
#define PWM_WAVEFORM_POS 24U
|
#define PWM_WAVEFORM_MSK (0x1U << PWM_WAVEFORM_POS)
|
#define PWM_WAVEFORM(x) (((uint32_t)(((uint32_t)(x)) << PWM_WAVEFORM_POS)) & PWM_WAVEFORM_MSK)
|
|
#define PWM_COUNTER_POS 8U
|
#define PWM_COUNTER_MSK (0xffU << PWM_COUNTER_POS)
|
#define PWM_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << PWM_COUNTER_POS)) & PWM_COUNTER_MSK)
|
|
#define PWM_DITHER_POS 0U
|
#define PWM_DITHER_MSK (0xffU << PWM_DITHER_POS)
|
#define PWM_DITHER(x) (((uint32_t)(((uint32_t)(x)) << PWM_DITHER_POS)) & PWM_DITHER_MSK)
|
|
// CTRL
|
#define PWM_CTRL_PWM4_EN_POS 31U
|
#define PWM_CTRL_PWM4_EN_MSK (1U << PWM_CTRL_PWM4_EN_POS)
|
|
#define PWM_CTRL_PWM3_EN_POS 30U
|
#define PWM_CTRL_PWM3_EN_MSK (1U << PWM_CTRL_PWM3_EN_POS)
|
|
#define PWM_CTRL_PWM2_EN_POS 29U
|
#define PWM_CTRL_PWM2_EN_MSK (1U << PWM_CTRL_PWM2_EN_POS)
|
|
#define PWM_CTRL_PWM1_EN_POS 28U
|
#define PWM_CTRL_PWM1_EN_MSK (1U << PWM_CTRL_PWM1_EN_POS)
|
|
#define PWM_CTRL_PWM0_EN_POS 27U
|
#define PWM_CTRL_PWM0_EN_MSK (1U << PWM_CTRL_PWM0_EN_POS)
|
|
#define PWM_CTRL_ALL_EN_POS PWM_CTRL_PWM0_EN_POS
|
#define PWM_CTRL_ALL_EN_MSK (0x1fU << PWM_CTRL_ALL_EN_POS)
|
|
#define PWM_CTRL_PWM4_INT_EN_POS 20U
|
#define PWM_CTRL_PWM4_INT_EN_MSK (1U << PWM_CTRL_PWM4_INT_EN_POS)
|
|
#define PWM_CTRL_PWM3_INT_EN_POS 19U
|
#define PWM_CTRL_PWM3_INT_EN_MSK (1U << PWM_CTRL_PWM3_INT_EN_POS)
|
|
#define PWM_CTRL_PWM2_INT_EN_POS 18U
|
#define PWM_CTRL_PWM2_INT_EN_MSK (1U << PWM_CTRL_PWM2_INT_EN_POS)
|
|
#define PWM_CTRL_PWM1_INT_EN_POS 17U
|
#define PWM_CTRL_PWM1_INT_EN_MSK (1U << PWM_CTRL_PWM1_INT_EN_POS)
|
|
#define PWM_CTRL_PWM0_INT_EN_POS 16U
|
#define PWM_CTRL_PWM0_INT_EN_MSK (1U << PWM_CTRL_PWM0_INT_EN_POS)
|
|
#define PWM_CTRL_ALL_INT_EN_POS PWM_CTRL_PWM0_INT_EN_POS
|
#define PWM_CTRL_ALL_INT_EN_MSK (0x1fU << PWM_CTRL_ALL_INT_EN_POS)
|
|
#define PWM_CTRL_GEN_PRESCALER_EN_POS 12U
|
#define PWM_CTRL_GEN_PRESCALER_EN_MSK (1U << PWM_CTRL_GEN_PRESCALER_EN_POS)
|
|
#define PWM_CTRL_GEN_PRESCALER_POS 8U
|
#define PWM_CTRL_GEN_PRESCALER_MSK (0xfU << PWM_CTRL_GEN_PRESCALER_POS)
|
#define PWM_CTRL_GEN_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PWM_CTRL_GEN_PRESCALER_POS)) & PWM_CTRL_GEN_PRESCALER_MSK)
|
|
#define PWM_CTRL_PWM4_POL_INV_POS 4U
|
#define PWM_CTRL_PWM4_POL_INV_MSK (1U << PWM_CTRL_PWM4_POL_INV_POS)
|
|
#define PWM_CTRL_PWM3_POL_INV_POS 3U
|
#define PWM_CTRL_PWM3_POL_INV_MSK (1U << PWM_CTRL_PWM3_POL_INV_POS)
|
|
#define PWM_CTRL_PWM2_POL_INV_POS 2U
|
#define PWM_CTRL_PWM2_POL_INV_MSK (1U << PWM_CTRL_PWM2_POL_INV_POS)
|
|
#define PWM_CTRL_PWM1_POL_INV_POS 1U
|
#define PWM_CTRL_PWM1_POL_INV_MSK (1U << PWM_CTRL_PWM1_POL_INV_POS)
|
|
#define PWM_CTRL_PWM0_POL_INV_POS 0U
|
#define PWM_CTRL_PWM0_POL_INV_MSK (1U << PWM_CTRL_PWM0_POL_INV_POS)
|
|
// PHASE
|
#define PWM_PHASE_PWM1_DITHER_POS 24U
|
#define PWM_PHASE_PWM1_DITHER_MSK (0xffU << PWM_PHASE_PWM1_DITHER_POS)
|
#define PWM_PHASE_PWM1_DITHER(x) (((uint32_t)(((uint32_t)(x)) << PWM_PHASE_PWM1_DITHER_POS)) & PWM_PHASE_PWM1_DITHER_MSK)
|
|
#define PWM_PHASE_PWM1_COUNTER_POS 16U
|
#define PWM_PHASE_PWM1_COUNTER_MSK (0xffU << PWM_PHASE_PWM1_COUNTER_POS)
|
#define PWM_PHASE_PWM1_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << PWM_PHASE_PWM1_COUNTER_POS)) & PWM_PHASE_PWM1_COUNTER_MSK)
|
|
#define PWM_PHASE_PWM0_DITHER_POS 8U
|
#define PWM_PHASE_PWM0_DITHER_MSK (0xffU << PWM_PHASE_PWM0_DITHER_POS)
|
#define PWM_PHASE_PWM0_DITHER(x) (((uint32_t)(((uint32_t)(x)) << PWM_PHASE_PWM0_DITHER_POS)) & PWM_PHASE_PWM0_DITHER_MSK)
|
|
#define PWM_PHASE_PWM0_COUNTER_POS 0U
|
#define PWM_PHASE_PWM0_COUNTER_MSK (0xffU << PWM_PHASE_PWM0_COUNTER_POS)
|
#define PWM_PHASE_PWM0_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << PWM_PHASE_PWM0_COUNTER_POS)) & PWM_PHASE_PWM0_COUNTER_MSK)
|
|
#define PWM_PHASE_PWM3_DITHER_POS 24U
|
#define PWM_PHASE_PWM3_DITHER_MSK (0xffU << PWM_PHASE_PWM3_DITHER_POS)
|
#define PWM_PHASE_PWM3_DITHER(x) (((uint32_t)(((uint32_t)(x)) << PWM_PHASE_PWM3_DITHER_POS)) & PWM_PHASE_PWM3_DITHER_MSK)
|
|
#define PWM_PHASE_PWM3_COUNTER_POS 16U
|
#define PWM_PHASE_PWM3_COUNTER_MSK (0xffU << PWM_PHASE_PWM3_COUNTER_POS)
|
#define PWM_PHASE_PWM3_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << PWM_PHASE_PWM3_COUNTER_POS)) & PWM_PHASE_PWM3_COUNTER_MSK)
|
|
#define PWM_PHASE_PWM2_DITHER_POS 8U
|
#define PWM_PHASE_PWM2_DITHER_MSK (0xffU << PWM_PHASE_PWM2_DITHER_POS)
|
#define PWM_PHASE_PWM2_DITHER(x) (((uint32_t)(((uint32_t)(x)) << PWM_PHASE_PWM2_DITHER_POS)) & PWM_PHASE_PWM2_DITHER_MSK)
|
|
#define PWM_PHASE_PWM2_COUNTER_POS 0U
|
#define PWM_PHASE_PWM2_COUNTER_MSK (0xffU << PWM_PHASE_PWM2_COUNTER_POS)
|
#define PWM_PHASE_PWM2_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << PWM_PHASE_PWM2_COUNTER_POS)) & PWM_PHASE_PWM2_COUNTER_MSK)
|
|
// INTR_CLR
|
#define PWM_INTR_CLR_CH0_POS 0U
|
#define PWM_INTR_CLR_CH0_MSK (1U << PWM_INTR_CLR_CH0_POS)
|
|
#define PWM_INTR_CLR_CH1_POS 0U
|
#define PWM_INTR_CLR_CH1_MSK (1U << PWM_INTR_CLR_CH1_POS)
|
|
#define PWM_INTR_CLR_CH2_POS 0U
|
#define PWM_INTR_CLR_CH2_MSK (1U << PWM_INTR_CLR_CH2_POS)
|
|
#define PWM_INTR_CLR_CH3_POS 0U
|
#define PWM_INTR_CLR_CH3_MSK (1U << PWM_INTR_CLR_CH3_POS)
|
|
#define PWM_INTR_CLR_CH4_POS 0U
|
#define PWM_INTR_CLR_CH4_MSK (1U << PWM_INTR_CLR_CH4_POS)
|
|
// INTR_STATUS
|
#define PWM_INTR_STATUS_CH0_POS 0U
|
#define PWM_INTR_STATUS_CH0_MSK (1U << PWM_INTR_STATUS_CH0_POS)
|
|
#define PWM_INTR_STATUS_CH1_POS 1U
|
#define PWM_INTR_STATUS_CH1_MSK (1U << PWM_INTR_STATUS_CH1_POS)
|
|
#define PWM_INTR_STATUS_CH2_POS 2U
|
#define PWM_INTR_STATUS_CH2_MSK (1U << PWM_INTR_STATUS_CH2_POS)
|
|
#define PWM_INTR_STATUS_CH3_POS 3U
|
#define PWM_INTR_STATUS_CH3_MSK (1U << PWM_INTR_STATUS_CH3_POS)
|
|
#define PWM_INTR_STATUS_CH4_POS 4U
|
#define PWM_INTR_STATUS_CH4_MSK (1U << PWM_INTR_STATUS_CH4_POS)
|
|
/* =========================================================================================================================== */
|
/* ================ TRNG ================ */
|
/* =========================================================================================================================== */
|
|
/**
|
* @brief TRNG
|
*/
|
|
typedef struct
|
{
|
__IOM uint32_t CTRL0; /*!< (0x00) TRNG Control Register 0 */
|
__IOM uint32_t CTRL1; /*!< (0x04) TRNG Control Register 1 */
|
__IM uint32_t STATUS; /*!< (0x08) TRNG Status Register */
|
uint32_t RESERVED0;
|
__IM uint32_t DATA[4]; /*!< (0x10) TRNG Data Register */
|
__IOM uint32_t INTR_EN; /*!< (0x20) TRNG Interrupt Enable Register */
|
__IOM uint32_t INTR_CLR; /*!< (0x24) TRNG Interrupt Clear Register */
|
__IM uint32_t INTR_STATUS; /*!< (0x28) TRNG Interrupt Status Register */
|
} TRNG_TypeDef;
|
|
// CTRL0
|
#define TRNG_CTRL0_LSB_CFG_POS 0U
|
#define TRNG_CTRL0_LSB_CFG_MSK (0x7U << TRNG_CTRL0_LSB_CFG_POS)
|
#define TRNG_CTRL0_LSB_CFG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_CTRL0_LSB_CFG_POS)) & TRNG_CTRL0_LSB_CFG_MSK)
|
|
// CTRL1
|
#define TRNG_CTRL1_TRNG_REQ_POS 0U
|
#define TRNG_CTRL1_TRNG_REQ_MSK (0x1U << TRNG_CTRL1_TRNG_REQ_POS)
|
|
// STATUS
|
#define TRNG_STATUS_DONE_POS 0U
|
#define TRNG_STATUS_DONE_MSK (0x1U << TRNG_STATUS_DONE_POS)
|
|
// INTR_EN
|
#define TRNG_INTR_EN_POS 0U
|
#define TRNG_INTR_EN_MSK (0x1U << TRNG_INTR_EN_POS)
|
|
// INTR_CLR
|
#define TRNG_INTR_CLR_POS 0U
|
#define TRNG_INTR_CLR_MSK (0x1U << TRNG_INTR_CLR_POS)
|
|
// INTR_STATUS
|
#define TRNG_INTR_STATUS_DONE_POS 0U
|
#define TRNG_INTR_STATUS_DONE_MSK (0x1U << TRNG_INTR_STATUS_DONE_POS)
|
|
/* =========================================================================================================================== */
|
/* ================ ADC ================ */
|
/* =========================================================================================================================== */
|
|
/**
|
* @brief ADC
|
*/
|
|
typedef struct
|
{
|
__IOM uint32_t CTRL0; /*!< (0x00) Control Register 0 */
|
__IOM uint32_t CTRL1; /*!< (0x04) Control Register 1 */
|
__IOM uint32_t CTRL2; /*!< (0x08) Control Register 2 */
|
__IM uint32_t STATUS; /*!< (0x0C) Status Register */
|
__IM uint32_t DATA; /*!< (0x10) Data Register */
|
uint32_t RESERVED0[3];
|
__IOM uint32_t INTR_EN; /*!< (0x20) Interrupt Enable Register */
|
__IOM uint32_t INTR_CLR; /*!< (0x24) Interrupt Clear Register */
|
__IM uint32_t INTR_STATUS; /*!< (0x28) Interrupt Status Register */
|
uint32_t RESERVED1[1];
|
__IOM uint32_t DMA_EN; /*!< (0x30) DMA Request Enable Register */
|
} ADC_TypeDef;
|
|
// CTRL0
|
#define ADC_CTRL0_CONV_MODE_POS 0U
|
#define ADC_CTRL0_CONV_MODE_MSK (0x1U << ADC_CTRL0_CONV_MODE_POS)
|
#define ADC_CTRL0_CONV_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL0_CONV_MODE_POS)) & ADC_CTRL0_CONV_MODE_MSK)
|
|
#define ADC_CTRL0_CLK_SEL_POS 1U
|
#define ADC_CTRL0_CLK_SEL_MSK (0x1U << ADC_CTRL0_CLK_SEL_POS)
|
#define ADC_CTRL0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL0_CLK_SEL_POS)) & ADC_CTRL0_CLK_SEL_MSK)
|
|
#define ADC_CTRL0_CHNL_P_POS 4U
|
#define ADC_CTRL0_CHNL_P_MSK (0xfU << ADC_CTRL0_CHNL_P_POS)
|
#define ADC_CTRL0_CHNL_P(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL0_CHNL_P_POS)) & ADC_CTRL0_CHNL_P_MSK)
|
|
#define ADC_CTRL0_CHNL_N_POS 8U
|
#define ADC_CTRL0_CHNL_N_MSK (0xfU << ADC_CTRL0_CHNL_N_POS)
|
#define ADC_CTRL0_CHNL_N(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL0_CHNL_N_POS)) & ADC_CTRL0_CHNL_N_MSK)
|
|
#define ADC_CTRL0_ACC_NUM_POS 12U
|
#define ADC_CTRL0_ACC_NUM_MSK (0xfU << ADC_CTRL0_ACC_NUM_POS)
|
#define ADC_CTRL0_ACC_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL0_ACC_NUM_POS)) & ADC_CTRL0_ACC_NUM_MSK)
|
|
#define ADC_CTRL0_HIGH_PULSE_WIDTH_POS 20U
|
#define ADC_CTRL0_HIGH_PULSE_WIDTH_MSK (0xfU << ADC_CTRL0_HIGH_PULSE_WIDTH_POS)
|
#define ADC_CTRL0_HIGH_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL0_HIGH_PULSE_WIDTH_POS)) & ADC_CTRL0_HIGH_PULSE_WIDTH_MSK)
|
|
#define ADC_CTRL0_SETTLE_TIME_POS 24U
|
#define ADC_CTRL0_SETTLE_TIME_MSK (0xfU << ADC_CTRL0_SETTLE_TIME_POS)
|
#define ADC_CTRL0_SETTLE_TIME(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL0_SETTLE_TIME_POS)) & ADC_CTRL0_SETTLE_TIME_MSK)
|
|
// CTRL1
|
#define ADC_CTRL1_CONV_RATE_POS 0U
|
#define ADC_CTRL1_CONV_RATE_MSK (0xffffU << ADC_CTRL1_CONV_RATE_POS)
|
#define ADC_CTRL1_CONV_RATE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL1_CONV_RATE_POS)) & ADC_CTRL1_CONV_RATE_MSK)
|
|
#define ADC_CTRL1_TS_EN_POS 16U
|
#define ADC_CTRL1_TS_EN_MSK (0x1U << ADC_CTRL1_TS_EN_POS)
|
|
#define ADC_CTRL1_VS_EN_POS 17U
|
#define ADC_CTRL1_VS_EN_MSK (0x1U << ADC_CTRL1_VS_EN_POS)
|
|
// CTRL2
|
#define ADC_CTRL2_CONV_EN_POS 0U
|
#define ADC_CTRL2_CONV_EN_MSK (0x1U << ADC_CTRL2_CONV_EN_POS)
|
|
// STATUS
|
#define ADC_STATUS_DONE_POS 0U
|
#define ADC_STATUS_DONE_MSK (0x1U << ADC_STATUS_DONE_POS)
|
|
#define ADC_STATUS_BUSY_POS 1U
|
#define ADC_STATUS_BUSY_MSK (0x1U << ADC_STATUS_BUSY_POS)
|
|
#define ADC_STATUS_CONFLICT_POS 2U
|
#define ADC_STATUS_CONFLICT_MSK (0x1U << ADC_STATUS_CONFLICT_POS)
|
|
#define ADC_STATUS_OVERWRITE_POS 3U
|
#define ADC_STATUS_OVERWRITE_MSK (0x1U << ADC_STATUS_OVERWRITE_POS)
|
|
// INTR_EN
|
#define ADC_INTR_DONE_EN_POS 0U
|
#define ADC_INTR_DONE_EN_MSK (0x1U << ADC_INTR_DONE_EN_POS)
|
|
#define ADC_INTR_CONFLICT_EN_POS 1U
|
#define ADC_INTR_CONFLICT_EN_MSK (0x1U << ADC_INTR_CONFLICT_EN_POS)
|
|
#define ADC_INTR_OVERWRITE_EN_POS 2U
|
#define ADC_INTR_OVERWRITE_EN_MSK (0x1U << ADC_INTR_OVERWRITE_EN_POS)
|
|
// INTR_CLR
|
#define ADC_INTR_DONE_CLR_POS 0U
|
#define ADC_INTR_DONE_CLR_MSK (0x1U << ADC_INTR_DONE_CLR_POS)
|
|
#define ADC_INTR_CONFLICT_CLR_POS 1U
|
#define ADC_INTR_CONFLICT_CLR_MSK (0x1U << ADC_INTR_CONFLICT_CLR_POS)
|
|
#define ADC_INTR_OVERWRITE_CLR_POS 2U
|
#define ADC_INTR_OVERWRITE_CLR_MSK (0x1U << ADC_INTR_OVERWRITE_CLR_POS)
|
|
// INTR_STATUS
|
#define ADC_INTR_STATUS_DONE_POS 0U
|
#define ADC_INTR_STATUS_DONE_MSK (0x1U << ADC_INTR_STATUS_DONE_POS)
|
|
#define ADC_INTR_STATUS_CONFLICT_POS 1U
|
#define ADC_INTR_STATUS_CONFLICT_MSK (0x1U << ADC_INTR_STATUS_CONFLICT_POS)
|
|
#define ADC_INTR_STATUS_OVERWRITE_POS 2U
|
#define ADC_INTR_STATUS_OVERWRITE_MSK (0x1U << ADC_INTR_STATUS_OVERWRITE_POS)
|
|
// DMA_EN
|
#define ADC_DMA_EN_POS 0U
|
#define ADC_DMA_EN_MSK (0x1U << ADC_DMA_EN_POS)
|
|
/* =========================================================================================================================== */
|
/* ================ AES ================ */
|
/* =========================================================================================================================== */
|
|
/**
|
* @brief AES
|
*/
|
|
typedef struct
|
{
|
__IOM uint32_t CTRL0; /*!< (0x00) Control Register 0 */
|
__IOM uint32_t CTRL1; /*!< (0x04) Control Register 1 */
|
__IOM uint32_t CTRL2; /*!< (0x08) Control Register 2 */
|
__IOM uint32_t STATUS; /*!< (0x0C) Status Register */
|
__OM uint32_t DIN; /*!< (0x10) Data In Register */
|
__IM uint32_t DOUT; /*!< (0x14) Data Out Register */
|
uint32_t RESERVED0[2];
|
__IOM uint32_t DMA_EN; /*!< (0x20) DMA Request Enable Register */
|
__IOM uint32_t INTR_EN; /*!< (0x24) Interrupt Enable Register */
|
__IOM uint32_t INTR_STATUS; /*!< (0x28) Interrupt Status and Clear Register */
|
uint32_t RESERVED1[1];
|
__IOM uint32_t KEY[4]; /*!< (0x30) KEY Register */
|
__IOM uint32_t IV[4]; /*!< (0x40) IV Register */
|
} AES_TypeDef;
|
|
// CTRL0
|
#define AES_CTRL0_START_POS 0U
|
#define AES_CTRL0_START_MSK (1U << AES_CTRL0_START_POS)
|
|
#define AES_CTRL0_CLEAR_POS 1U
|
#define AES_CTRL0_CLEAR_MSK (1U << AES_CTRL0_CLEAR_POS)
|
|
// CTRL1
|
#define AES_CTRL1_MODE_POS 0U
|
#define AES_CTRL1_MODE_MSK (0x7U << AES_CTRL1_MODE_POS)
|
#define AES_CTRL1_MODE(x) (((uint32_t)(((uint32_t)(x)) << AES_CTRL1_MODE_POS)) & AES_CTRL1_MODE_MSK)
|
|
#define AES_CTRL1_DIR_POS 4U
|
#define AES_CTRL1_DIR_MSK (1U << AES_CTRL1_DIR_POS)
|
#define AES_CTRL1_DIR(x) (((uint32_t)(((uint32_t)(x)) << AES_CTRL1_DIR_POS)) & AES_CTRL1_DIR_MSK)
|
|
#define AES_CTRL1_MIC_LEN_POS 8U
|
#define AES_CTRL1_MIC_LEN_MSK (0x1fU << AES_CTRL1_MIC_LEN_POS)
|
#define AES_CTRL1_MIC_LEN(x) (((uint32_t)(((uint32_t)(x)) << AES_CTRL1_MIC_LEN_POS)) & AES_CTRL1_MIC_LEN_MSK)
|
|
// CTRL2
|
#define AES_CTRL2_PLEN_POS 0U
|
#define AES_CTRL2_PLEN_MSK (0xffffU << AES_CTRL2_PLEN_POS)
|
#define AES_CTRL2_PLEN(x) (((uint32_t)(((uint32_t)(x)) << AES_CTRL2_PLEN_POS)) & AES_CTRL2_PLEN_MSK)
|
|
#define AES_CTRL2_ALEN_POS 16U
|
#define AES_CTRL2_ALEN_MSK (0xffffU << AES_CTRL2_ALEN_POS)
|
#define AES_CTRL2_ALEN(x) (((uint32_t)(((uint32_t)(x)) << AES_CTRL2_ALEN_POS)) & AES_CTRL2_ALEN_MSK)
|
|
// STATUS
|
#define AES_STATUS_DONE_POS 0U
|
#define AES_STATUS_DONE_MSK (0x1U << AES_STATUS_DONE_POS)
|
|
#define AES_STATUS_MIC_VALID_POS 1U
|
#define AES_STATUS_MIC_VALID_MSK (0x1U << AES_STATUS_MIC_VALID_POS)
|
|
#define AES_STATUS_DIN_OVERFLOW_POS 2U
|
#define AES_STATUS_DIN_OVERFLOW_MSK (0x1U << AES_STATUS_DIN_OVERFLOW_POS)
|
|
#define AES_STATUS_DOUT_UNDERFLOW_POS 3U
|
#define AES_STATUS_DOUT_UNDERFLOW_MSK (0x1U << AES_STATUS_DOUT_UNDERFLOW_POS)
|
|
#define AES_STATUS_BUSY_POS 4U
|
#define AES_STATUS_BUSY_MSK (0x1U << AES_STATUS_BUSY_POS)
|
|
#define AES_STATUS_DIN_BUF_SPACE_POS 5U
|
#define AES_STATUS_DIN_BUF_SPACE_MSK (0x1FU << AES_STATUS_DIN_BUF_SPACE_POS)
|
|
#define AES_STATUS_DOUT_BUF_CNT_POS 10U
|
#define AES_STATUS_DOUT_BUF_CNT_MSK (0x1FU << AES_STATUS_DOUT_BUF_CNT_POS)
|
|
// DMA_EN
|
#define AES_DMA_EN_DIN_DMA_EN_POS 0U
|
#define AES_DMA_EN_DIN_DMA_EN_MSK (0x1U << AES_DMA_EN_DIN_DMA_EN_POS)
|
|
#define AES_DMA_EN_DIN_DMA_BURST_SIZE_POS 1U
|
#define AES_DMA_EN_DIN_DMA_BURST_SIZE_MSK (0x1FU << AES_DMA_EN_DIN_DMA_BURST_SIZE_POS)
|
#define AES_DMA_EN_DIN_DMA_BURST_SIZE(x) (((uint32_t)(((uint32_t)(x)) << AES_DMA_EN_DIN_DMA_BURST_SIZE_POS)) & AES_DMA_EN_DIN_DMA_BURST_SIZE_MSK)
|
|
#define AES_DMA_EN_DOUT_DMA_EN_POS 8U
|
#define AES_DMA_EN_DOUT_DMA_EN_MSK (0x1U << AES_DMA_EN_DOUT_DMA_EN_POS)
|
|
#define AES_DMA_EN_DOUT_DMA_BURST_SIZE_POS 9U
|
#define AES_DMA_EN_DIUT_DMA_BURST_SIZE_MSK (0x1FU << AES_DMA_EN_DOUT_DMA_BURST_SIZE_POS)
|
#define AES_DMA_EN_DIUT_DMA_BURST_SIZE(x) (((uint32_t)(((uint32_t)(x)) << AES_DMA_EN_DOUT_DMA_BURST_SIZE_POS)) & AES_DMA_EN_DIUT_DMA_BURST_SIZE_MSK)
|
|
// INTR_EN
|
#define AES_INTR_EN_DONE_EN_POS 0U
|
#define AES_INTR_EN_DONE_EN_MSK (0x1U << AES_INTR_EN_DONE_EN_POS)
|
|
#define AES_INTR_EN_DIN_OVERFLOW_EN_POS 1U
|
#define AES_INTR_EN_DIN_OVERFLOW_EN_MSK (0x1U << AES_INTR_EN_DIN_OVERFLOW_EN_POS)
|
|
#define AES_INTR_EN_DOUT_UNDERFLOW_EN_POS 2U
|
#define AES_INTR_EN_DOUT_UNDERFLOW_EN_MSK (0x1U << AES_INTR_EN_DOUT_UNDERFLOW_EN_POS)
|
|
#define AES_INTR_EN_DIN_EMPTY_EN_POS 3U
|
#define AES_INTR_EN_DIN_EMPTY_EN_MSK (0x1U << AES_INTR_EN_DIN_EMPTY_EN_POS)
|
|
#define AES_INTR_EN_DOUT_NOT_EMPTY_EN_POS 4U
|
#define AES_INTR_EN_DOUT_NOT_EMPTY_EN_MSK (0x1U << AES_INTR_EN_DOUT_NOT_EMPTY_EN_POS)
|
|
// INTR_STATUS
|
#define AES_INTR_STATUS_DONE_POS 0U
|
#define AES_INTR_STATUS_DONE_MSK (0x1U << AES_INTR_STATUS_DONE_POS)
|
|
#define AES_INTR_STATUS_DIN_OVERFLOW_POS 1U
|
#define AES_INTR_STATUS_DIN_OVERFLOW_MSK (0x1U << AES_INTR_STATUS_DIN_OVERFLOW_POS)
|
|
#define AES_INTR_STATUS_DOUT_UNDERFLOW_POS 2U
|
#define AES_INTR_STATUS_DOUT_UNDERFLOW_MSK (0x1U << AES_INTR_STATUS_DOUT_UNDERFLOW_POS)
|
|
#define AES_INTR_STATUS_DIN_EMPTY_POS 3U
|
#define AES_INTR_STATUS_DIN_EMPTY_MSK (0x1U << AES_INTR_STATUS_DIN_EMPTY_POS)
|
|
#define AES_INTR_STATUS_DOUT_NOT_EMPTY_POS 4U
|
#define AES_INTR_STATUS_DOUT_NOT_EMPTY_MSK (0x1U << AES_INTR_STATUS_DOUT_NOT_EMPTY_POS)
|
|
/* =========================================================================================================================== */
|
/* ================ DMA ================ */
|
/* =========================================================================================================================== */
|
|
/**
|
* @brief DMA
|
*/
|
|
typedef struct
|
{
|
__IM uint32_t INTR_STATUS; /*!< (0x00) Interrupt Status Register */
|
__OM uint32_t INTR_CLR; /*!< (0x04) Interrupt Status Clear Register */
|
__IM uint32_t STATUS0; /*!< (0x08) Status Register 0 */
|
__IM uint32_t STATUS1; /*!< (0x0C) Status Register 1 */
|
__IOM uint32_t CTRL0; /*!< (0x10) Global Control Register */
|
uint32_t RESERVED0[59];
|
struct CH_T
|
{
|
__IOM uint32_t CTRL; /*!< (0x100) DMA CH Control Register */
|
__IOM uint32_t CFG; /*!< (0x104) DMA CH Configuration Register */
|
__IOM uint32_t DATA_SIZE; /*!< (0x108) DMA CH Transcation length Register */
|
__IOM uint32_t ADDR_SRC; /*!< (0x10C) DMA CH Source Address Register */
|
__IOM uint32_t ADDR_DST; /*!< (0x110) DMA CH Destination Address Register */
|
uint32_t RESERVED1[3];
|
} CH[8];
|
} DMA_TypeDef;
|
|
// INTR_STATUS
|
#define DMA_INTR_STATUS_ABORT_POS 16U
|
#define DMA_INTR_STATUS_ABORT_MSK (0xffU << DMA_INTR_STATUS_ABORT_POS)
|
|
#define DMA_INTR_STATUS_ERR_POS 8U
|
#define DMA_INTR_STATUS_ERR_MSK (0xffU << DMA_INTR_STATUS_ERR_POS)
|
|
#define DMA_INTR_STATUS_DONE_POS 0U
|
#define DMA_INTR_STATUS_DONE_MSK (0xffU << DMA_INTR_STATUS_DONE_POS)
|
|
// INTR_CLR
|
#define DMA_INTR_CLR_ABORT_POS 16U
|
#define DMA_INTR_CLR_ABORT_MSK (0xffU << DMA_INTR_CLR_ABORT_POS)
|
#define DMA_INTR_CLR_ABORT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTR_CLR_ABORT_POS)) & DMA_INTR_CLR_ABORT_MSK)
|
|
#define DMA_INTR_CLR_ERR_POS 8U
|
#define DMA_INTR_CLR_ERR_MSK (0xffU << DMA_INTR_CLR_ERR_POS)
|
#define DMA_INTR_CLR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTR_CLR_ERR_POS)) & DMA_INTR_CLR_ERR_MSK)
|
|
#define DMA_INTR_CLR_DONE_POS 0U
|
#define DMA_INTR_CLR_DONE_MSK (0xffU << DMA_INTR_CLR_DONE_POS)
|
#define DMA_INTR_CLR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTR_CLR_DONE_POS)) & DMA_INTR_CLR_DONE_MSK)
|
|
// STATUS0
|
#define DMA_STATUS0_ABORT_POS 16U
|
#define DMA_STATUS0_ABORT_MSK (0xffU << DMA_STATUS0_ABORT_POS)
|
|
#define DMA_STATUS0_ERR_POS 8U
|
#define DMA_STATUS0_ERR_MSK (0xffU << DMA_STATUS0_ERR_POS)
|
|
#define DMA_STATUS0_DONE_POS 0U
|
#define DMA_STATUS0_DONE_MSK (0xffU << DMA_STATUS0_DONE_POS)
|
|
// STATUS1
|
#define DMA_STATUS1_ENABLE_POS 8U
|
#define DMA_STATUS1_ENABLE_MSK (0xffU << DMA_STATUS1_ENABLE_POS)
|
|
#define DMA_STATUS1_CH_BUSY_POS 0U
|
#define DMA_STATUS1_CH_BUSY_MSK (0xffU << DMA_STATUS1_CH_BUSY_POS)
|
|
// CTRL0
|
#define DMA_CTRL0_ENABLE_POS 0U
|
#define DMA_CTRL0_ENABLE_MSK (1U << DMA_CTRL0_ENABLE_POS)
|
|
// CTRL
|
#define DMA_CH_CTRL_FIFO_TH_POS 24U
|
#define DMA_CH_CTRL_FIFO_TH_MSK (0x7U << DMA_CH_CTRL_FIFO_TH_POS)
|
#define DMA_CH_CTRL_FIFO_TH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CTRL_FIFO_TH_POS)) & DMA_CH_CTRL_FIFO_TH_MSK)
|
|
#define DMA_CH_CTRL_AHB_HPROT_POS 19U
|
#define DMA_CH_CTRL_AHB_HPROT_MSK (0x7U << DMA_CH_CTRL_AHB_HPROT_POS)
|
#define DMA_CH_CTRL_AHB_HPROT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CTRL_AHB_HPROT_POS)) & DMA_CH_CTRL_AHB_HPROT_MSK)
|
|
#define DMA_CH_CTRL_SRC_BURST_SIZE_POS 16U
|
#define DMA_CH_CTRL_SRC_BURST_SIZE_MSK (0x7U << DMA_CH_CTRL_SRC_BURST_SIZE_POS)
|
#define DMA_CH_CTRL_SRC_BURST_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CTRL_SRC_BURST_SIZE_POS)) & DMA_CH_CTRL_SRC_BURST_SIZE_MSK)
|
|
#define DMA_CH_CTRL_ABORT_POS 15U
|
#define DMA_CH_CTRL_ABORT_MSK (0x1U << DMA_CH_CTRL_ABORT_POS)
|
|
#define DMA_CH_CTRL_SRC_DATA_WIDTH_POS 11U
|
#define DMA_CH_CTRL_SRC_DATA_WIDTH_MSK (0x7U << DMA_CH_CTRL_SRC_DATA_WIDTH_POS)
|
#define DMA_CH_CTRL_SRC_DATA_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CTRL_SRC_DATA_WIDTH_POS)) & DMA_CH_CTRL_SRC_DATA_WIDTH_MSK)
|
|
#define DMA_CH_CTRL_DST_DATA_WIDTH_POS 8U
|
#define DMA_CH_CTRL_DST_DATA_WIDTH_MSK (0x7U << DMA_CH_CTRL_DST_DATA_WIDTH_POS)
|
#define DMA_CH_CTRL_DST_DATA_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CTRL_DST_DATA_WIDTH_POS)) & DMA_CH_CTRL_DST_DATA_WIDTH_MSK)
|
|
#define DMA_CH_CTRL_MODE_POS 7U
|
#define DMA_CH_CTRL_MODE_MSK (0x1U << DMA_CH_CTRL_MODE_POS)
|
|
#define DMA_CH_CTRL_SRC_ADDR_CTRL_POS 5U
|
#define DMA_CH_CTRL_SRC_ADDR_CTRL_MSK (0x3U << DMA_CH_CTRL_SRC_ADDR_CTRL_POS)
|
#define DMA_CH_CTRL_SRC_ADDR_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CTRL_SRC_ADDR_CTRL_POS)) & DMA_CH_CTRL_SRC_ADDR_CTRL_MSK)
|
|
#define DMA_CH_CTRL_DST_ADDR_CTRL_POS 3U
|
#define DMA_CH_CTRL_DST_ADDR_CTRL_MSK (0x3U << DMA_CH_CTRL_DST_ADDR_CTRL_POS)
|
#define DMA_CH_CTRL_DST_ADDR_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CTRL_DST_ADDR_CTRL_POS)) & DMA_CH_CTRL_DST_ADDR_CTRL_MSK)
|
|
#define DMA_CH_CTRL_EN_POS 0U
|
#define DMA_CH_CTRL_EN_MSK (0x1U << DMA_CH_CTRL_EN_POS)
|
|
// CFG
|
#define DMA_CH_CFG_DST_REQ_SEL_POS 9U
|
#define DMA_CH_CFG_DST_REQ_SEL_MSK (0x1fU << DMA_CH_CFG_DST_REQ_SEL_POS)
|
#define DMA_CH_CFG_DST_REQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CFG_DST_REQ_SEL_POS)) & DMA_CH_CFG_DST_REQ_SEL_MSK)
|
|
#define DMA_CH_CFG_SRC_REQ_SEL_POS 3U
|
#define DMA_CH_CFG_SRC_REQ_SEL_MSK (0x1fU << DMA_CH_CFG_SRC_REQ_SEL_POS)
|
#define DMA_CH_CFG_SRC_REQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CFG_SRC_REQ_SEL_POS)) & DMA_CH_CFG_SRC_REQ_SEL_MSK)
|
|
#define DMA_CH_CFG_INT_ABORT_POS 2U
|
#define DMA_CH_CFG_INT_ABORT_MSK (0x1U << DMA_CH_CFG_INT_ABORT_POS)
|
|
#define DMA_CH_CFG_INT_ERR_POS 1U
|
#define DMA_CH_CFG_INT_ERR_MSK (0x1U << DMA_CH_CFG_INT_ERR_POS)
|
|
#define DMA_CH_CFG_INT_DONE_POS 0U
|
#define DMA_CH_CFG_INT_DONE_MSK (0x1U << DMA_CH_CFG_INT_DONE_POS)
|
|
// DATA_SIZE
|
#define DMA_CH_DATA_SIZE_POS 0U
|
#define DMA_CH_DATA_SIZE_MSK (0x3fffffU << DMA_CH_DATA_SIZE_POS)
|
#define DMA_CH_DATA_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_DATA_SIZE_POS)) & DMA_CH_DATA_SIZE_MSK)
|
|
/* ========================================= End of section using anonymous unions ========================================= */
|
#if defined(__CC_ARM)
|
#pragma pop
|
#elif defined(__ICCARM__)
|
/* leave anonymous unions enabled */
|
#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
|
#pragma clang diagnostic pop
|
#elif defined(__GNUC__)
|
/* anonymous unions are enabled by default */
|
#elif defined(__TMS470__)
|
/* anonymous unions are enabled by default */
|
#elif defined(__TASKING__)
|
#pragma warning restore
|
#elif defined(__CSMC__)
|
/* anonymous unions are enabled by default */
|
#else
|
#warning Not supported compiler type
|
#endif
|
|
/* =========================================================================================================================== */
|
/* ================ Device Specific Peripheral Address Map ================ */
|
/* =========================================================================================================================== */
|
|
/** @addtogroup MK8000_Address_Map
|
* @{
|
*/
|
|
/* Peripheral and SRAM base address */
|
#define FLASH_BASE (0x04000000U) /*!< (FLASH ) Base Address */
|
#define ROM_BASE (0x03000000U) /*!< (ROM ) Base Address */
|
#define SRAM_BASE (0x02000000U) /*!< (SRAM ) Base Address */
|
#define CODE_BASE (0x00000000U) /*!< (CODE ) Base Address */
|
|
#define APB_BASE (0x40000000U) /*!< (APB ) Base Address */
|
#define AHB_BASE (0x50000000U) /*!< (AHB ) Base Address */
|
|
/* Peripheral memory map */
|
#define EFUSE_CTRL_BASE (APB_BASE + 0x10080) /*!< (eFuse controller ) Base Address */
|
#define EFUSE_SHADOW_BASE (APB_BASE + 0x10000) /*!< (eFuse shadow register ) Base Address */
|
|
#define RTC_BASE (APB_BASE + 0x11000) /*!< (RTC ) Base Address */
|
|
#define I2C0_BASE (APB_BASE + 0x12000) /*!< (I2C0 ) Base Address */
|
|
#define PWM_BASE (APB_BASE + 0x13000) /*!< (PWM ) Base Address */
|
|
#define WDT_BASE (APB_BASE + 0x14000) /*!< (WDT ) Base Address */
|
|
#define TIMER0_BASE (APB_BASE + 0x15000) /*!< (Timer0 ) Base Address */
|
#define TIMER1_BASE (APB_BASE + 0x16000) /*!< (Timer1 ) Base Address */
|
#define TIMER2_BASE (APB_BASE + 0x17000) /*!< (Timer2 ) Base Address */
|
#define TIMER3_BASE (APB_BASE + 0x17020) /*!< (Timer3 ) Base Address */
|
|
#define UART0_BASE (APB_BASE + 0x19000) /*!< (UART0 ) Base Address */
|
#define UART1_BASE (APB_BASE + 0x1A000) /*!< (UART1 ) Base Address */
|
|
#define TRNG_BASE (APB_BASE + 0x1C000) /*!< (TRNG ) Base Address */
|
|
#define ADC_BASE (APB_BASE + 0x1D000) /*!< (ADC ) Base Address */
|
|
#define DMA_BASE (AHB_BASE + 0x0000) /*!< (DMA ) Base Address */
|
|
#define GPIO_BASE (AHB_BASE + 0x2000) /*!< (GPIO ) Base Address */
|
|
#define SPI0_BASE (AHB_BASE + 0x3000) /*!< (SPI0 ) Base Address */
|
#define SPI1_BASE (AHB_BASE + 0x8000) /*!< (SPI1 ) Base Address */
|
|
#define AES_BASE (AHB_BASE + 0x9000) /*!< (AES ) Base Address */
|
|
#define FLASH_CTRL_BASE (AHB_BASE + 0xB000) /*!< (FLASH_CTRL ) Base Address */
|
|
/**
|
* @}
|
*/
|
|
/* =========================================================================================================================== */
|
/* ================ Peripheral declaration ================ */
|
/* =========================================================================================================================== */
|
|
#define FLASH_SIZE 0x80000
|
#define ROM_SIZE 0x20000
|
#define SRAM_SIZE 0x30000
|
|
#define SYSCON ((SYSCON_TypeDef *)APB_BASE)
|
|
#define UART0 ((UART_TypeDef *)UART0_BASE)
|
#define UART1 ((UART_TypeDef *)UART1_BASE)
|
|
#define RTC ((RTC_TypeDef *)RTC_BASE)
|
|
#define I2C0 ((I2C_TypeDef *)I2C0_BASE)
|
|
#define PWM ((PWM_TypeDef *)PWM_BASE)
|
|
#define WDT ((WDT_TypeDef *)WDT_BASE)
|
|
#define TIMER0 ((TIMER_TypeDef *)TIMER0_BASE)
|
#define TIMER1 ((TIMER_TypeDef *)TIMER1_BASE)
|
|
#define TIMER2 ((DUAL_TIMER_TypeDef *)TIMER2_BASE)
|
#define TIMER3 ((DUAL_TIMER_TypeDef *)TIMER3_BASE)
|
|
#define SPI0 ((SPI_TypeDef *)SPI0_BASE)
|
#define SPI1 ((SPI_TypeDef *)SPI1_BASE)
|
|
#define GPIO ((GPIO_TypeDef *)GPIO_BASE)
|
|
#define FLASH_CTRL ((FLASH_CTRL_TypeDef *)FLASH_CTRL_BASE)
|
|
#define EFUSE_CTRL ((EFUSE_CTRL_TypeDef *)EFUSE_CTRL_BASE)
|
|
#define TRNG ((TRNG_TypeDef *)TRNG_BASE)
|
|
#define ADC ((ADC_TypeDef *)ADC_BASE)
|
|
#define AES ((AES_TypeDef *)AES_BASE)
|
|
#define DMA ((DMA_TypeDef *)DMA_BASE)
|
|
#ifdef __cplusplus
|
}
|
#endif
|
|
#endif /* MK8000_H */
|
