/*
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* Copyright (c) 2019-2023 Beijing Hanwei Innovation Technology Ltd. Co. and
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* its subsidiaries and affiliates (collectly called MKSEMI).
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form, except as embedded into an MKSEMI
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* integrated circuit in a product or a software update for such product,
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* must reproduce the above copyright notice, this list of conditions and
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* the following disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* 3. Neither the name of MKSEMI nor the names of its contributors may be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* 4. This software, with or without modification, must only be used with a
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* MKSEMI integrated circuit.
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*
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* 5. Any software provided in binary form under this license must not be
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* reverse engineered, decompiled, modified and/or disassembled.
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*
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* THIS SOFTWARE IS PROVIDED BY MKSEMI "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL MKSEMI OR CONTRIBUTORS BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef MK_FLASH_H_
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#define MK_FLASH_H_
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#include "mk_common.h"
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#include "mk_dma.h"
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#include "mk_misc.h"
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#ifndef FLASH_INT_MODE_EN
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#define FLASH_INT_MODE_EN (1)
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#endif
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#ifndef FLASH_DMA_MODE_EN
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#define FLASH_DMA_MODE_EN (1)
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#endif
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#ifndef FLASH_WRITE_EN
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#define FLASH_WRITE_EN (1)
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#endif
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/**
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* @addtogroup MK8000_Flash
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* @{
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*/
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#define FLASH_PAGE_SIZE 0x100U
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#define FLASH_SECTOR_SIZE 0x1000U
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#define FLASH_BLOCK_SIZE 0x10000U
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#define FLASH_OP_ERASE 1
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#define FLASH_OP_WRITE 2
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#define FLASH_OP_READ 3
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// Flash status check timeout
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#define FLASH_OP_ERASE_SECTOR_TIMEOUT __MS_TO_TICKS(600)
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#define FLASH_OP_ERASE_BLOCK_TIMEOUT __MS_TO_TICKS(4000)
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#define FLASH_OP_WRITE_PAGE_TIMEOUT __MS_TO_TICKS(6)
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#define FLASH_OP_WRITE_STATUS_TIMEOUT __MS_TO_TICKS(40)
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/** FLASH device instance */
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enum FLASH_DEV_T
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{
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FLASH_ID0 = 0,
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FLASH_MAX_NUM
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};
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/** FLASH operation code */
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enum FLASH_OPCODE_T
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{
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FLASH_OPCODE_READ = 0,
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FLASH_OPCODE_PROGRAM_PAGE,
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FLASH_OPCODE_GET_STATUS,
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FLASH_OPCODE_GET_STATUS1,
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FLASH_OPCODE_ERASE_SECTOR,
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FLASH_OPCODE_ERASE_BLOCK,
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FLASH_OPCODE_WRITE_ENABLE,
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FLASH_OPCODE_WRITE_REGISTER,
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FLASH_OPCODE_RDID,
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FLASH_OPCODE_POWER_DOWN,
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FLASH_OPCODE_RELEASE_POWER_DOWN,
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FLASH_OPCODE_NUM,
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};
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/** FLASH operation state */
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enum FLASH_STATE_T
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{
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FLASH_STATE_RESET = 0,
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FLASH_STATE_READY,
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FLASH_STATE_BUSY_READ,
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FLASH_STATE_BUSY_ERASE,
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FLASH_STATE_BUSY_WRITE,
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FLASH_STATE_TIMEOUT,
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FLASH_STATE_ERROR
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};
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/*! @brief FLASH data direction */
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enum FLASH_DATA_DIR_TYPE_T
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{
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FLASH_DATA_IN = 0x0U, /*!< Data input from serial flash. */
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FLASH_DATA_OUT = 0x1U /*!< Data output to serial flash. */
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};
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/*! @brief FLASH command opcode format */
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enum FLASH_CMD_FORMAT_T
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{
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FLASH_CMD_ALL_SERIAL = 0x0, /*!< All fields of command are serial. */
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FLASH_CMD_DATA_QUAD_DUAL = 0x1U, /*!< Only data field is dual/quad, others are serial. */
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FLASH_CMD_OP_SERIAL = 0x2U, /*!< Only opcode field is serial, others are quad/dual. */
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FLASH_CMD_ALL_QUAD_DUAL = 0x3U /*!< All fields of command are dual/quad mode. */
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};
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/*! @brief FLASH command type */
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enum FLASH_CMD_TYPE_T
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{
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FLASH_CMD_OP_ONLY = 0x1U, /*!< Command only have opcode, no address field */
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FLASH_CMD_OP_ADDR_1B = 0x2U, /*!< Command have opcode and also one byte address field */
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FLASH_CMD_OP_ADDR_2B = 0x3U, /*!< Command have opcode and also two bytes address field */
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FLASH_CMD_OP_ADDR_3B = 0x4U, /*!< Command have opcode and also three bytes address field. */
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FLASH_CMD_OP_ADDR_4B = 0x5U, /*!< Command have opcode and also four bytes address field */
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FLASH_CMD_NO_OP_ADDR_3B = 0x6U, /*!< Command have no opcode and three bytes address field */
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FLASH_CMD_NO_OP_ADDR_4B = 0x7U /*!< Command have no opcode and four bytes address field */
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};
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/*! @brief FLASH command structure */
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struct FLASH_CMD_T
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{
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uint32_t polling_mode; /*!< For command need to read data from serial flash */
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enum FLASH_DATA_DIR_TYPE_T data_dir; /*!< Data direction of this command. */
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enum FLASH_CMD_FORMAT_T format; /*!< Command format */
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enum FLASH_CMD_TYPE_T type; /*!< Command type */
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uint16_t data_len; /*!< How many data bytes are needed in this command. */
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uint8_t dummy_len; /*!< How many intermediate bytes needed */
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uint8_t opcode; /*!< Command opcode value */
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};
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/*!
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* @brief FLASH configuration structure.
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*/
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struct FLASH_CFG_T
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{
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uint16_t timeout; /*!< SPI transfer timeout, the unit is SCK cycles */
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uint8_t cs_high_time; /*!< CS high time cycles */
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bool dual_mode : 1; /*!< true: dual mode, false: quad mode */
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bool prefetch_dis : 1; /*!< True means FLASH will not attempt a speculative prefetch */
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bool cache_prefetch_dis : 1; /*!< Disable prefetch of cache line */
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bool feedback_clk_sel : 1; /*!< Is data sample uses feedback clock */
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bool spi_sck_high : 1; /*!< FLASH spi mode select */
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bool spi_falling_edge_active : 1; /*!< If enable read full clock cycle. */
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bool dma_en : 1;
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bool int_en : 1;
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uint32_t start_addr;
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uint32_t total_size;
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uint32_t block_size;
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uint16_t sector_size;
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uint16_t page_size;
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};
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struct FLASH_DMA_OP_CFG_T
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{
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uint32_t start_addr;
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const uint8_t *buf;
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uint32_t len;
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uint32_t count;
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};
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struct FLASH_WRITE_NBYTES_CFG_T
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{
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const uint8_t *src_addr;
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uint32_t write_start_addr;
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uint32_t write_end_addr;
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uint32_t offset_addr;
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uint32_t page_start;
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uint32_t page_end;
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uint32_t page_count;
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uint32_t write_num;
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uint32_t write_count;
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uint32_t start_page_inc_data_len;
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uint32_t end_page_inc_data_len;
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uint32_t src_buf_pos;
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__IOM uint32_t dest_tmp_addr;
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};
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struct FLASH_HANDLE_T
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{
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FLASH_CTRL_TypeDef *const base;
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const IRQn_Type irq;
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enum DMA_CH_T dma_wr_ch;
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enum DMA_CH_T dma_rd_ch;
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enum FLASH_STATE_T state;
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struct FLASH_CFG_T config;
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struct FLASH_WRITE_NBYTES_CFG_T wr_nbyte_cfg;
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struct FLASH_DMA_OP_CFG_T dma_op;
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uint32_t code; // reserved | err_code | int_flag | op_code
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drv_callback_t callback;
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uint8_t flash_type;
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uint8_t wrsr_type;
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uint8_t work_mode;
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uint8_t promote_fclk;
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uint8_t is_open;
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};
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#ifdef __cplusplus
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extern "C" {
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#endif
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extern struct FLASH_HANDLE_T flash_handle[FLASH_MAX_NUM];
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int flash_open(enum FLASH_DEV_T id, struct FLASH_CFG_T *cfg);
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int flash_close(enum FLASH_DEV_T id);
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void RAM_FUNC flash_power_up(enum FLASH_DEV_T id);
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void RAM_FUNC flash_power_down(enum FLASH_DEV_T id);
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int flash_sector_erase(enum FLASH_DEV_T id, uint32_t sector);
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int flash_block_erase(enum FLASH_DEV_T id, uint32_t block);
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int flash_erase(enum FLASH_DEV_T id, uint32_t start_addr, uint32_t len);
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int flash_write_nbytes(enum FLASH_DEV_T id, uint32_t start_addr, const uint8_t *buf, uint32_t len);
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int flash_write(enum FLASH_DEV_T id, uint32_t start_addr, const uint8_t *buf, uint32_t len);
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int flash_read(enum FLASH_DEV_T id, uint32_t start_addr, uint8_t *buf, uint32_t len);
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void FLASH_CTRL_IRQHandler(void);
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bool flash_check_busy(enum FLASH_DEV_T id);
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int RAM_FUNC flash_open_for_xip(enum FLASH_DEV_T id);
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#ifdef __cplusplus
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}
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#endif
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/**
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* @}
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*/
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#endif /* MK_FLASH_H_ */
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