/*
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* Copyright (c) 2019-2023 Beijing Hanwei Innovation Technology Ltd. Co. and
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* its subsidiaries and affiliates (collectly called MKSEMI).
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form, except as embedded into an MKSEMI
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* integrated circuit in a product or a software update for such product,
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* must reproduce the above copyright notice, this list of conditions and
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* the following disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* 3. Neither the name of MKSEMI nor the names of its contributors may be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* 4. This software, with or without modification, must only be used with a
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* MKSEMI integrated circuit.
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*
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* 5. Any software provided in binary form under this license must not be
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* reverse engineered, decompiled, modified and/or disassembled.
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*
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* THIS SOFTWARE IS PROVIDED BY MKSEMI "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL MKSEMI OR CONTRIBUTORS BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef MK_PHY_H_
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#define MK_PHY_H_
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#include "mk_common.h"
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/**
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* @addtogroup MK8000_PHY
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* @{
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*/
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/** PHY supported maximum payload length */
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#ifndef PHY_PAYLOAD_LEN_MAX
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#define PHY_PAYLOAD_LEN_MAX 1023
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#endif
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/** us to PHY timer count converter, x <= 3,441,480 us */
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#define US_TO_PHY_TIMER_COUNT(x) ((x)*1248U / 10U)
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/** ms to PHY timer count converter x <= 34,414 ms */
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#define MS_TO_PHY_TIMER_COUNT(x) ((x)*124800U)
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/** PHY timer count to us converter, resolution 10us */
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#define PHY_TIMER_COUNT_TO_US(x) (((x) / 1248U) * 10U)
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/** PHY timer count to us converter, allow long long type multiply operation to promote precision */
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#define PHY_TIMER_COUNT_TO_US_LL(x) (uint32_t)(((uint64_t)(x)*10U / 1248U))
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/** PHY timer count to ms converter */
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#define PHY_TIMER_COUNT_TO_MS(x) ((x) / 124800U)
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/** PHY timer count to MAC timer count converter */
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#define PHY_TIMER_COUNT_TO_MAC_TIMER_COUNT(x) ((x) >> 1)
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/** RSTU to PHY timer count converter, x <= 41,297,762 RSTU */
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#define RSTU_TO_PHY_TIMER_COUNT(x) ((x)*104U)
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/** RSTU to us converter, x <= 429,496,729 RSTU */
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#define RSTU_TO_US(x) ((x)*10U / 12U)
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/** RSTU to ms converter */
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#define RSTU_TO_MS(x) ((x) / 1200U)
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/** Timestamp unit is 15.65ps */
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#define TIMESTAMP_UNIT_TO_NS(x) ((x) * (1000 / 499.2 / 128))
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/// MeanPRF 62.4M, Data rate 6.8M, x=preamble length, y=SFD length, z=payload length
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#define PHY_SP0_FRAME_TIME_US(x, y, z) ((((x) + (y)) * 508 + 21 * 512 + ((((z)*8) / 330) * (378) + (((z)*8) % 330) + 48) * 64) / 499 + 1)
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/// MeanPRF 62.4M, Data rate 6.8M, x=preamble length, y=SFD length, z=payload length, s=STS length
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#define PHY_FRAME_TIME_US(x, y, z, s) ((((x) + (y)) * 508 + 21 * 512 + ((((z)*8) / 330) * (378) + (((z)*8) % 330) + 48) * 64 + (s)*512 + 1024) / 499 + 1)
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/** sleep count to PHY timer count converter */
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#define SLEEP_COUNT_TO_PHY_TIMER_COUNT(x) ((uint32_t)((float)(x) * (124800000.0f / 32768.0f)))
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/** The maximum sleep time of PHY, 10s */
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#define PHY_SLEEP_TIME_MS_MAX (10000U)
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/** The minimum sleep time of PHY, 2000us */
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#define PHY_SLEEP_TIME_US_MIN (2000U)
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/// Low power mode clock drift compensation for phy timer count, p = ppm, t = interval(ms)
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#define LPM_PPM_COMPENSATION(p, t) ((p)*2 * (t)*1248 / 10000)
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#define TX_PAYLOAD_ADDR 0x02080000
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#define RX_PAYLOAD_ADDR 0x02081000
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/// Data bit rate, range 0 to 4. 0 - 0.11, 1 - 0.85, 2 - 1.70, 3 - 6.81, 4 - 27.24 Mbps, 5 - 54.48 Mbps
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#define DATA_BR_110K 0
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#define DATA_BR_850K 1
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#define DATA_BR_1M7 2
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#define DATA_BR_6M8 3
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#define DATA_BR_27M2 4
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#define DATA_BR_54M4 5
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/// PHR bit rate
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#define PHR_BR_110K 0
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#define PHR_BR_850K 1
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/// PHR bit rate in BPRF and HPRF mode
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#define BPRF_PHR_BR_850K 0
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#define BPRF_PHR_BR_6M8 1
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/// mean prf. 0 - 4, 1 - 16, 2 - 64, 3 - 128, 4 - 256
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#define MEAN_PRF_4M 0
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#define MEAN_PRF_16M 1
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#define MEAN_PRF_64M 2
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#define MEAN_PRF_128M 3
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#define MEAN_PRF_256M 4
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/// Preamble duration, length of preamble sync: 0 - 16, 1 - 64, 2 - 128, 3 - 256, 4 - 512, 5 - 1024, 6 - 2048, 7 - 4096
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#define PREAM_LEN_16 0
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#define PREAM_LEN_64 1
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#define PREAM_LEN_128 2
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#define PREAM_LEN_256 3
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#define PREAM_LEN_512 4
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#define PREAM_LEN_1024 5
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#define PREAM_LEN_2048 6
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#define PREAM_LEN_4096 7
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/// HRPF mode: 0 - 16, 1 - 24, 2 - 32, 3 - 48, 4 - 64, 5 - 96, 6 - 128, 7 - 256
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#define HPRF_PREAM_LEN_16 0
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#define HPRF_PREAM_LEN_24 1
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#define HPRF_PREAM_LEN_32 2
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#define HPRF_PREAM_LEN_48 3
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#define HPRF_PREAM_LEN_64 4
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#define HPRF_PREAM_LEN_96 5
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#define HPRF_PREAM_LEN_128 6
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#define HPRF_PREAM_LEN_256 7
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/// Length of preamble SFD: 0 - 8, 1 - 64
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#define NSFD_8 0
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#define NSFD_64 1
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/// BPRF SFD: 0 - 8 SFD, 2 - 8 SFD2
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#define BPRF_NSFD_8 0
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#define BPRF_NSFD2_8 2
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/// HPRF SFD: 0 - 8 SFD, 1 - 4 SFD1, 2 - 8 SFD2, 3 - 16 SFD3, 4 - 32 SFD4
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#define HPRF_NSFD0_8 0
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#define HPRF_NSFD1_4 1
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#define HPRF_NSFD2_8 2
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#define HPRF_NSFD3_16 3
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#define HPRF_NSFD4_32 4
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/// Non-standard SFD
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#define NON_STD_NSFD5_8 5
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#define NON_STD_NSFD6_16 6
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#define HPRF_PSDU_SIZE_1023 0
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#define HPRF_PSDU_SIZE_2047 1
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#define HPRF_PSDU_SIZE_4095 2
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/// 0 - 15.4a(2015), 1 - BPRF, 2 - HPRF, 3 - Proprietary
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#define TRX_MODE_15_4A 0
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#define TRX_MODE_15_4Z_BPRF 1
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#define TRX_MODE_15_4Z_HPRF 2
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#define TRX_MODE_PROPRIETARY 3
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/// SYNC-SFD-PHR-PSDU
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#define STS_PKT_CFG_0 0
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/// SYNC-SFD-STS-PHR-PSDU
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#define STS_PKT_CFG_1 1
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/// SYNC-SFD-PHR-PSDU-STS
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#define STS_PKT_CFG_2 2
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/// SYNC-SFD-STS
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#define STS_PKT_CFG_3 3
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/// STS_SEGNUM
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/// BPRF: 0 - 1
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/// HPRF: 0 - 1, 1 - 2, 2 - 3 (optional), 3 - 4 (optional)
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#define STS_SEGNUM_BPRF_1 0
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#define STS_SEGNUM_HPRF_1 0
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#define STS_SEGNUM_HPRF_2 1
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#define STS_SEGNUM_HPRF_3 2
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#define STS_SEGNUM_HPRF_4 3
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/// STS_SEGLEN
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/// BPRF: 2 - 64
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/// HPRF: 0 - 16 (optional), 1 - 32, 2 - 64, 3 - 128, 4 - 256 (optional)
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#define STS_SEGLEN_BPRF_64 2
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#define STS_SEGLEN_HPRF_16 0
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#define STS_SEGLEN_HPRF_32 1
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#define STS_SEGLEN_HPRF_64 2
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#define STS_SEGLEN_HPRF_128 3
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#define STS_SEGLEN_HPRF_256 4
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/** PHY work mode */
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enum PHY_WORK_MODE_T
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{
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PHY_IDLE = 0,
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PHY_TX = 1,
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PHY_RX = 2,
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};
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/** PHY protocol data unit parameters */
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struct UWB_CONFIG_T
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{
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uint8_t ch_num;
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uint8_t code_index;
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uint8_t mean_prf;
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uint8_t data_bit_rate;
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uint8_t sync_sym;
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uint8_t sfd_sym;
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uint8_t ranging_bit;
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uint8_t trx_mode;
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uint8_t sts_pkt_cfg;
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uint8_t sts_segnum;
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uint8_t sts_seglen;
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uint8_t rx_ant_id;
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uint8_t fcs_type;
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};
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/** STS key configuration*/
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struct UWB_STS_KEY_CONFIG_T
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{
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uint32_t sts_vcounter;
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uint32_t sts_vupper0;
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uint32_t sts_vupper1;
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uint32_t sts_vupper2;
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uint32_t sts_key0;
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uint32_t sts_key1;
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uint32_t sts_key2;
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uint32_t sts_key3;
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};
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/** PHY advanced configuration*/
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struct PHY_ADV_CONFIG_T
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{
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// 20-200, default:40
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uint16_t thres_fap_detect;
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// 0-15, default:4
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uint8_t nth_scale_factor;
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// 0: high STDEV mode (default), 1: high 1st path dynamic range mode (20db+), 2: STS based FAP, 3: preamble FAP and STS FAP combination
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uint8_t ranging_performance_mode;
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// 0: disable, 1: enable
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uint8_t skip_weakest_port_en;
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};
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/** PHY user configuration*/
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struct PHY_USER_CONFIG_T
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{
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// AGC
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uint8_t highTH;
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uint8_t lowTH;
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uint8_t nCHUP;
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uint8_t nLEAK;
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// Preamble
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uint8_t symPerBlk[2];
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uint8_t pdbLen;
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uint8_t passNum;
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uint8_t bdAbsThr[4];
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uint8_t deltaPos;
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uint8_t testSf[2];
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uint8_t prmKp;
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uint8_t prmKi;
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uint8_t prmKp_time;
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uint8_t prmKi_time;
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// CE
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uint8_t ceStartSym;
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uint8_t ceAvgIdx;
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uint8_t ceTapSidx;
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uint8_t nthr;
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uint8_t firTapThr[2];
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uint8_t srchWinLenM1;
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// SFD
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uint8_t engthr0[2];
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uint8_t engthr1[2];
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// PLD
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uint8_t pldKp;
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uint8_t pldKi;
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uint8_t pldKp_time;
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uint8_t pldKi_time;
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// ALGO
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uint8_t frac_comp_opt[2];
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uint8_t lut_step_size[2];
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uint8_t win_adj_sf[2];
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uint8_t en_simple_frac[2];
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uint8_t Coeff0[4];
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};
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/** STS receive mode */
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enum STS_SWITCH_MODE_T
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{
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STS_SWITCH_EVERY_4SYM = 0,
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STS_NEVER_SWITCH = 2,
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};
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#ifdef __cplusplus
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extern "C" {
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#endif
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extern const float ch_center_freq_map[16];
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extern const uint8_t rx_ant_code[4];
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extern struct PHY_USER_CONFIG_T phy_user_params;
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/**
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* @brief Initialize PHY.
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* @param[in] priority PHY interrupt priority @ref IRQ_PRIORITY_LEVEL_T
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* @return 0 represent intialization successful
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*/
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int phy_init(enum IRQ_PRIORITY_LEVEL_T priority);
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/**
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* @brief Register PHY interrupt callback function.
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* @param[in] callback Callback function of PHY interrupt
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*/
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void phy_register_callback(drv_callback_t callback);
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/**
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* @brief set TRX mode.
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* @param[in] mode TRX mode: 0 - 15.4a(2015), 1 - BPRF, 2 - HPRF, 3 - Proprietary
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* @note: In most of case, change TRX mode needs to reconfigure PHY parameters
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*/
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void phy_trx_mode_set(uint8_t mode);
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/**
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* @brief Enable PHY parameter sets.
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* @param[in] sets PHY parameter sets to be enabled, if input NULL the default parameter sets will be used
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*/
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void phy_params_sets_enable(void *sets);
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/**
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* @brief Generate PHY parameters Configuration.
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* @param[in] mode Work mode, PHY_TX or PHY_RX or both
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* @param[in] high_pfm_en Enable or disable high performance mode
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* @param[in] config PHY protocol data unit parameters @ref UWB_CONFIG_T
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* @param[in] sets Specify a buffer to store the parameter sets, if input NULL the default parameter sets buffer will be used,
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* the buffer size is 128 Words, i.e. uint32_t sets[128]
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* @return the pointer of input parameter sets, if input parameter sets is NULL, the default parameter sets pointer will be returned
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*/
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void *phy_params_generate(uint8_t mode, uint8_t high_pfm_en, const struct UWB_CONFIG_T *config, void *sets);
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/**
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* @brief Configure PHY adv parameters.
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* @param[in] config PHY advanced configuration parameters @ref PHY_ADV_CONFIG_T
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* @return 0 represent configure successfully
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*/
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int phy_adv_params_configure(struct PHY_ADV_CONFIG_T *adv_config);
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/**
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* @brief Configure PHY parameters for user scenarios.
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* @param[in] config PHY user configuration parameters @ref PHY_USER_CONFIG_T
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* @param[in] len PHY user configuration parameters length
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* @param[in] enable Enable PHY user parameters
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* @return 0 represent configure successfully
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*/
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int phy_loop_params_configure(const struct PHY_USER_CONFIG_T *user_config, uint8_t len, uint8_t enable);
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/**
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* @brief Configure PHY transmitter registers.
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* @param[in] sets PHY parameter sets to be set, if input NULL the default parameter sets will be set
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* @return 0 represent configure successfully
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*/
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int phy_tx_regs_config(void *sets);
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/**
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* @brief Configure PHY receiver registers.
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* @param[in] sets PHY parameter sets to be set, if input NULL the default parameter sets will be set
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* @return 0 represent configure successfully
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*/
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int phy_rx_regs_config(void *sets);
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/**
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* @brief Set ranging bit in PHY header.
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*/
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void phy_ranging_bit_set(uint8_t bit);
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/**
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* @brief Configure UWB TX packet payload
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* @param[in] data Pointer of the TX packet buffer
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* @param[in] len TX packet length
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*/
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void phy_tx_payload(const uint8_t *data, uint16_t len);
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/**
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* @brief the length of synchronization header depends on preamble and SFD symbols, i.e. from the start point of TX_EN/RX_EN to Rframe marker.
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* @return the time of synchronization header(SHR), unit: 1/124.8M (~8ns)
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*/
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uint32_t phy_shr_duration(void);
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/**
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* @brief Restore PHY from power-down.
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* @param[in] sets PHY parameter sets to be restored, if input NULL the default parameter sets will be restored
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*/
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void phy_restore(void *sets);
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/**
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* @brief Set receiver antenna mode.
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* @param[in] mode Receiver antenna mode @ref macro definition RX_xPORTS_ANT_xxx
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*/
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void phy_rx_ant_mode_set(uint8_t mode);
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/**
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* @brief Set AoA symbol count.
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* @param[in] cnt AoA symbol count, 0x30 or 0x40
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*/
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void phy_aoa_sym_cnt_set(uint16_t cnt);
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/**
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* @brief Set STS packet configuration.
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* @param[in] cfg STS packet configuration, 0 ~ 3
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*/
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void phy_sts_pkt_cfg_set(uint8_t cfg);
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/**
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* @brief Set STS key configuration.
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* @param[in] sts STS key configuration @ref UWB_STS_KEY_CONFIG_T
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*/
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void phy_sts_key_configure(struct UWB_STS_KEY_CONFIG_T *sts);
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/**
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* @brief Set STS RX antenna switching mode (AoA).
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* @param[in] sts_pkt_cfg STS packet configuration, SP1 or SP3
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* @param[in] mode STS RX antenna switching mode @ref enum STS_SWITCH_MODE_T, this API should be called after configure UWB parameters
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* @param[in] main_ant_update Update main antenna or not
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* @param[in] rx_ant_id RX antenna ID
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*/
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void phy_rx_sts_switch_mode_set(uint8_t sts_pkt_cfg, enum STS_SWITCH_MODE_T mode, uint8_t main_ant_update, uint8_t rx_ant_id);
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/**
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* @brief Set STS TX antenna switching mode (AoD).
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* @param[in] tx_ant_num Then number of TX antennas to be used for switching, from 1 to 16
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* @param[in] mode STS TX antenna switching mode @ref enum STS_SWITCH_MODE_T
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*/
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void phy_tx_sts_switch_mode_set(uint8_t tx_ant_num, enum STS_SWITCH_MODE_T mode);
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/**
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* @brief Open the PHY timer (124.8MHz free running counter).
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* @param[in] int_en Enable interrupt flag
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* @param[in] priority PHY timer interrupt priority @ref IRQ_PRIORITY_LEVEL_T
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* @return 0 reresent PHY timer is opened
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*/
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int phy_timer_open(uint8_t int_en, enum IRQ_PRIORITY_LEVEL_T priority);
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/**
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* @brief Close the PHY timer.
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* @return 0 reresent PHY timer is closed
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*/
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int phy_timer_close(void);
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/**
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* @brief Set a target time for the PHY timer.
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* @param[in] target Target time (124.8MHz clock).
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* @param[in] callback Callback function for the target time
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*/
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void phy_timer_target_set(uint32_t target, drv_callback_t callback);
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/**
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* @brief Get the flag that PHY timer is set or not.
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* @return 0 means PHY timer is not set.
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*/
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uint8_t phy_timer_is_programmed(void);
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/**
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* @brief Get the PHY timer count.
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* @return PHY timer count (124.8MHz clock).
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*/
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uint32_t phy_timer_count_get(void);
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/**
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* @brief Get the PHY timer left count.
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* @return PHY timer left count (124.8MHz clock).
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*/
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uint32_t phy_timer_count_left(void);
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/**
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* @brief Pause the PHY timer.
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*/
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void phy_timer_pause(void);
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/**
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* @brief Resume the PHY timer.
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* @return sleep count @32KHz.
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*/
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uint32_t phy_timer_resume(void);
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/**
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* @brief Get Burst Detection count
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* @return Burst Detection count.
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*/
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uint16_t phy_bd_cnt_get(void);
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/**
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* @brief Get SFD detection count
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* @return SFD detection count.
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*/
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uint16_t phy_sfd_cnt_get(void);
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/**
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* @brief Get the UWB Receiver frequency offset compared to the transmitter
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* @return frequency offset (Hz).
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*/
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int32_t phy_freq_offset_get(void);
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/**
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* @brief Configure narrow band filter.
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* @param[in] en Enable or disable
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* @param[in] in_band_freq_offset In band frequency offset -249.6 ~ 249.6 MHz
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* @param[in] band_width Narrow band filter band width
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* 6 - 1.24M
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* 5 - 2.48M
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* 4 - 4.96M
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* 3 - 9.92M
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* 2 - 19.84M
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* @return 0 represent configure successfully
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*/
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int phy_nb_filter_config(uint8_t en, int16_t in_band_freq_offset, uint8_t band_width);
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/**
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* @brief Get narrow band energy.
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* @return narrow band energy
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*/
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int32_t phy_nb_energy_get(void);
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/**
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* @brief Configure CCA.
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*/
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void phy_cca_config(void);
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/**
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* @brief Start CCA.
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* @param[in] int_en 1 - Interrupt mode, 0 - Polling mode
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* @param[in] callback Callback function of PHY interrupt
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* @return RSSI in polling mode, for interrupt mode, the result should be read in callback function
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*/
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uint16_t phy_cca_start(uint8_t int_en, drv_callback_t callback);
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/**
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* @brief Get CCA RSSI.
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* @return CCA RSSI
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*/
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int32_t phy_cca_rssi_get(void);
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/**
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* @brief Enable dump mode.
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* @param[in] en 1 - Enable, 0 - Disable
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*/
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void phy_dump_en(uint8_t en);
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/**
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* @brief Enter debug mode.
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*/
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void enter_debug_mode(void);
|
|
#ifdef __cplusplus
|
}
|
#endif
|
|
/**
|
* @}
|
*/
|
|
#endif /* MK_PHY_H_ */
|
