/*
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* Copyright (c) 2019-2023 Beijing Hanwei Innovation Technology Ltd. Co. and
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* its subsidiaries and affiliates (collectly called MKSEMI).
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form, except as embedded into an MKSEMI
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* integrated circuit in a product or a software update for such product,
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* must reproduce the above copyright notice, this list of conditions and
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* the following disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* 3. Neither the name of MKSEMI nor the names of its contributors may be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* 4. This software, with or without modification, must only be used with a
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* MKSEMI integrated circuit.
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*
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* 5. Any software provided in binary form under this license must not be
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* reverse engineered, decompiled, modified and/or disassembled.
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*
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* THIS SOFTWARE IS PROVIDED BY MKSEMI "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL MKSEMI OR CONTRIBUTORS BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef USER_CONFIG_H_
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#define USER_CONFIG_H_
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/* =========================================================================================================================== */
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/* ================ Silicon configuration ================ */
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/* =========================================================================================================================== */
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/** CPU model */
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#define CPU_MK8000
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/* =========================================================================================================================== */
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/* ================ Board configuration ================ */
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/* =========================================================================================================================== */
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/** Enable radar presence detection processing locally, otherwise the radar raw data will be outputted by UART */
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#define UWB_RADAR_DETECT_PROCESS_EN (1)
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/** Define radar data dump port */
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#if UWB_RADAR_DETECT_PROCESS_EN == 0
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#define DUMP_DATA_PORT UART_ID1
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#endif
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/** Define trace port */
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#define TRACE_PORT TRACE_PORT_UART0
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/* =========================================================================================================================== */
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/* ================ Driver configuration ================ */
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/* =========================================================================================================================== */
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// ACMP work mode
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#define ACMP_INT_MODE_EN (0)
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// ADC work mode
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#define ADC_INT_MODE_EN (0)
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#define ADC_DMA_MODE_EN (0)
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#define ADC_POLL_MODE_EN (1)
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// AES work mode
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#define AES_INT_MODE_EN (0)
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#define AES_DMA_MODE_EN (1)
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#define AES_POLL_MODE_EN (0)
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// Flash work mode
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#define FLASH_INT_MODE_EN (0)
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#define FLASH_DMA_MODE_EN (0)
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// I2C work mode
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#define I2C_INT_MODE_EN (0)
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#define I2C_POLL_MODE_EN (1)
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// LSP work mode
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#define LSP_INT_MODE_EN (0)
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// PWM work mode
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#define PWM_INT_MODE_EN (0)
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// RTC work mode
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#define RTC_FREE_COUNTER_EN (0)
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// SPI work mode
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#define SPI_INT_MODE_EN (0)
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#define SPI_DMA_MODE_EN (1)
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#define SPI_POLL_MODE_EN (1)
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// TRNG work mode
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#define TRNG_INT_MODE_EN (0)
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#define TRNG_POLL_MODE_EN (1)
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// UART work mode
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#define UART_INT_MODE_EN (0)
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#define UART_DMA_MODE_EN (1)
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#define UART_POLL_MODE_EN (0)
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// Dual Timer work mode
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#define TIMER0_INT_MODE_EN (1)
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#define TIMER1_INT_MODE_EN (1)
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// Timer work mode
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#define TIMER2_INT_MODE_EN (0)
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#define TIMER3_INT_MODE_EN (1)
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/* =========================================================================================================================== */
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/* ================ Debug/TRACE configuration ================ */
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/* =========================================================================================================================== */
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/** Enable trace output */
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#define TRACE_EN (1)
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/** Enable exception reboot */
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#ifndef TRACE_REBOOT_EN
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#define TRACE_REBOOT_EN (1)
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#endif
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/** Enable standard format output */
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#define TRACE_STD_LIB_EN (0)
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/** Configure trace level for modules: BOOT | TEST | UCI | UWB | APP | DRIVER | PHY | MAC */
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#define TRACE_LVL_CONFIG_0 (0x44444444)
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/** Configure trace level for modules: CCC | FIRA | OS */
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#define TRACE_LVL_CONFIG_1 (0x00000444)
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/** Configure trace buffer size (in bytes) */
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#define TRACE_BUF_SIZE (1024)
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/* =========================================================================================================================== */
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/* ================ Power configuration ================ */
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/* =========================================================================================================================== */
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/** Enable low power mode */
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#ifndef LOW_POWER_EN
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#define LOW_POWER_EN (0)
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#endif
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/** Enable 32.768K crystal as low power mode clock source */
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#ifndef XTAL32K_EN
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#define XTAL32K_EN (1)
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#endif
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/** Enable DC-DC */
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#ifndef DCDC_EN
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#define DCDC_EN (1)
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#endif
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/** Enable BOR */
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#ifndef BOR_EN
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#define BOR_EN (0)
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#endif
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/** Enable BOD */
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#ifndef BOD_EN
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#define BOD_EN (0)
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#endif
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/** Enable UWB high performance mode, it will increase power consumption */
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#ifndef HIGH_PERFORMANCE_MODE_EN
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#define HIGH_PERFORMANCE_MODE_EN (1)
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#endif
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/* =========================================================================================================================== */
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/* ================ Clock configuration ================ */
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/* =========================================================================================================================== */
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/** Configure system clock source @ref enum CLOCK_ATTACH_TYPE_T */
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#define SYS_CLK_SOURCE (CLOCK_62P4M_XTAL38P4M_TO_SYS_CLK)
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/** AHBCLK = SYSCLK/(div) @ref enum CLOCK_BUS_DIVIDER_VAL_T */
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#define AHB_DIV (CLOCK_DIVIDED_BY_1)
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/** APBCLK = AHBCLK/(div) @ref enum CLOCK_BUS_DIVIDER_VAL_T */
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#define APB_DIV (CLOCK_DIVIDED_BY_1)
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/** Configure 32K clock source @ref enum CLOCK_ATTACH_TYPE_T */
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#if XTAL32K_EN
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#define CLK_32K_SOURCE (CLOCK_XTAL32K_TO_32K_CLK)
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#define LOW_POWER_CLOCK_PPM (50)
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#else
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#define CLK_32K_SOURCE (CLOCK_RCO32K_TO_32K_CLK)
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#define LOW_POWER_CLOCK_PPM (1000)
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#endif
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/** Enable system tick timer (period = 10ms), needed by OS */
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#define SYS_TICK_EN (1)
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/* =========================================================================================================================== */
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/* ================ UWB configuration ================ */
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/* =========================================================================================================================== */
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/** Enable Post-process filter */
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#define FILTER_EN (0)
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/** Enable RSSI output */
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#define RSSI_EN (1)
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/** Enable Channel status information output */
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#define CSI_EN (0)
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/** Enable PDoA 3D */
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#define PDOA_3D_EN (1)
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/** Enable AoA */
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#define AOA_EN (0)
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/** Measure angle on 1 (responder side), 2 (initiator side), 3 (both sides), 0 (None) */
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#define MEASURE_ANGLE_ON_ROLE (1)
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/** TX power level: 0 ~ 60 */
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#define TX_POWER_LEVEL (36)
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/** Antenna ports combination, @ref macro definition RX_xPORTS_ANT_xxx */
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#define RX_ANT_PORTS_COMBINATION (RX_4PORTS_ANT_3_0_1_2)
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/** Dynamic update RX main antenna, can be enabled only when 4 ports are in use */
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#define DYNAMIC_UPDATE_MAIN_ANTENNA_EN (0)
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#if PDOA_3D_EN
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/// Antenna pattern
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#define ANT_PATTERN (ANT_PATTERN_SQUARE)
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/// Antenna layout, @ref enum ANT_LAYOUT_T
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#define ANT_LAYOUT (ANT_LAYOUT_HORIZONTAL)
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#else
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/// Antenna pattern
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#define ANT_PATTERN (ANT_PATTERN_LINEAR)
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#endif
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/** Enable load cap automatic tuning during ranging procedure */
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#define XTAL_AUTO_TUNE_EN (1)
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/** Enable kalman filter as post process filter, FILTER_EN should be enabled meanwhile */
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#define KF_EN (1)
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/** Velocity of propagation (%) */
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#define VP_VAL (100)
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/* =========================================================================================================================== */
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/* ================ UWB Radar configuration ================ */
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/* =========================================================================================================================== */
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/** Time Division Multiplexing Radar Ranging */
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#define TDM_RANGING_AND_RADAR
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/** UWB radar STS segment length, 0:STS segment length 16, 1:STS segment length 32, 2:STS segment length 64 */
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#define UWB_RADAR_STS_LENGTH (2)
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/** UWB radar pulse period, 0:16ns, 1:32ns, 2:64ns, 3:128ns, 4:256ns*/
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#define UWB_RADAR_PULSE_PERIOD (2)
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/** UWB radar channel number: 5, 9 */
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#define UWB_RADAR_CHANNEL_NUM (9)
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/** UWB radar rx filter gain level 0 ~ 21 */
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#define UWB_RADAR_FILTRE_GAIN_LEVEL (14)
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/** UWB radar lna gain level 0 ~ 5 */
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#define UWB_RADAR_LNA_GAIN_LEVEL (5)
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/** UWB radar tx power level 0 ~ 60 */
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#define UWB_RADAR_TX_POWER_LEVEL (46)
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/** UWB radar tx pulse width 0:2ns (Bandwidth 500M), 1:0.92ns (Bandwidth 900M), 2: 0.75ns (Bandwidth 1.3G) */
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#define UWB_RADAR_BANDWIDTH (2)
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/** 1TnR radar mdoe: 0: Single, 1: Overlay */
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#define UWB_RADAR_1TNR_MODE 1
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/** 1TnR mode RX port number */
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#define UWB_RADAR_RX_PORT_NUM 1
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/** UWB radar rx antenna start port @ref enum UWB_RX_ANT_T: UWB_RX_ANT_0, UWB_RX_ANT_1, UWB_RX_ANT_2 */
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#define UWB_RADAR_RX_ANT_ID (UWB_RX_ANT_0)
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/** Enable UWB radar on role: 1 (responder side), 2 (initiator side), 3 (both sides), 0 (None) */
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#define UWB_RADAR_ON_ROLE (1)
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/** Enable radar control by UCI */
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#define UWB_RADAR_UCI_EN (0)
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/* ========================================== PPDU configuration ======================================== */
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/** channel number: 2, 5, 9 */
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#define UWB_CH_NUM (9)
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/** mean PRF: @ref enum PRF_MODE_T */
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#define UWB_MEAN_PRF (PRF_62M4)
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/** preamble code index: 1 ~ 8, 9 ~ 24, 25 ~ 32 */
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#define UWB_PREAMBLE_CODE_IDX (10)
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/** preamble duration: @ref enum PREAMBLE_DURATION_T */
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#define UWB_PREAMBLE_DURATION (SYMBOLS_64)
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/** SFD ID: @ref enum SFD_ID_T */
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#define UWB_SFD_ID (SFD2_LEN8)
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/** PSDU data rate: @ref enum PSDU_DATA_RATE_T */
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#define UWB_PSDU_DATA_RATE (BPS_6M8)
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/** STS segment number: @ref enum STS_SEGMENTS_NUM_T */
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#define UWB_STS_SEGMENT_NUM (STS_SEGMENTS_1)
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/** STS segment length: @ref enum STS_SEGMENTS_LENGTH_T */
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#define UWB_STS_SEGMENT_LEN (STS_SEG_LEN64)
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/** Ranging frame packet type: @ref enum RFRAME_TYPE_T, if AoA is enabled, the frame should contain STS */
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#define UWB_RFRAME_TYPE (SP3)
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/** Maximum PHY payload length */
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#define PHY_PAYLOAD_LEN_MAX (127)
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/* ========================================== Timing configuration ======================================== */
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/// Period prefetch time for event program from wakeup - 600us+
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#define UWB_PERIOD_PREFETCH_TIME (US_TO_PHY_TIMER_COUNT(600))
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/// Event prefetch time for event program - 300us
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#define UWB_EVT_PREFETCH_TIME (US_TO_PHY_TIMER_COUNT(300))
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/// RX window open in advance time - 10us
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#define UWB_RX_OPEN_IN_ADVANCE (US_TO_PHY_TIMER_COUNT(10))
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/// RX window - 400us
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#define UWB_RX_WINDOW (US_TO_PHY_TIMER_COUNT(400))
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/** Ranging slot duration, unit: RSTU (1200 = 1ms), maximum: 65535 */
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#define UWB_RANGING_SLOT_DURATION (3600)
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/** Ranging block duration, unit: ms */
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#define UWB_RANGING_INTERVAL (96)
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/* =========================================================================================================================== */
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/* ================ End ================ */
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/* =========================================================================================================================== */
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#endif /* USER_CONFIG_H_ */
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