/*
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* Copyright (c) 2019-2023 Beijing Hanwei Innovation Technology Ltd. Co. and
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* its subsidiaries and affiliates (collectly called MKSEMI).
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form, except as embedded into an MKSEMI
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* integrated circuit in a product or a software update for such product,
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* must reproduce the above copyright notice, this list of conditions and
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* the following disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* 3. Neither the name of MKSEMI nor the names of its contributors may be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* 4. This software, with or without modification, must only be used with a
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* MKSEMI integrated circuit.
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*
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* 5. Any software provided in binary form under this license must not be
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* reverse engineered, decompiled, modified and/or disassembled.
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*
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* THIS SOFTWARE IS PROVIDED BY MKSEMI "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL MKSEMI OR CONTRIBUTORS BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "mk_gpio.h"
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#include "mk_clock.h"
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#include "mk_reset.h"
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#include "mk_trace.h"
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struct GPIO_HANDLE_T
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{
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GPIO_TypeDef *const base;
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const IRQn_Type irq;
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uint32_t irq_mask;
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GPIO_IRQ_HANDLER_T irq_handler[IO_PIN_MAX];
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};
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static struct GPIO_HANDLE_T gpio_handle[GPIO_MAX_NUM] = {
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{
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.base = GPIO,
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.irq = GPIO_IRQn,
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.irq_mask = 0,
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.irq_handler = {0},
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},
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};
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int gpio_open(void)
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{
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// enable GPIO clock
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clock_enable(CLOCK_GPIO);
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reset_module(RESET_MODULE_GPIO);
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return DRV_OK;
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}
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int gpio_close(void)
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{
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// disable GPIO clock
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clock_disable(CLOCK_GPIO);
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return DRV_OK;
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}
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void gpio_write(uint32_t value)
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{
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gpio_handle[0].base->DATAOUT = value;
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}
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uint32_t gpio_read(void)
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{
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return gpio_handle[0].base->DATA;
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}
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void gpio_pin_set(enum IO_PIN_T pin)
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{
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gpio_handle[0].base->DATAOUT = gpio_handle[0].base->DATAOUT | (1U << pin);
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}
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void gpio_pin_clr(enum IO_PIN_T pin)
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{
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gpio_handle[0].base->DATAOUT = gpio_handle[0].base->DATAOUT & (~(1U << pin));
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}
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void gpio_pin_toggle(enum IO_PIN_T pin)
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{
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gpio_handle[0].base->DATAOUT = gpio_handle[0].base->DATAOUT ^ (1U << pin);
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}
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uint8_t gpio_pin_get_val(enum IO_PIN_T pin)
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{
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return (((gpio_handle[0].base->DATA) >> pin) & 0x1U);
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}
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void gpio_pin_set_dir(enum IO_PIN_T pin, enum GPIO_DIR_T dir, uint8_t out_val)
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{
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if (dir == GPIO_DIR_IN)
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{
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SYSCON->IO_EI |= (1U << pin);
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gpio_handle[0].base->OUTENCLR = (1U << pin);
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}
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else if (dir == GPIO_DIR_OUT)
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{
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if (out_val)
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{
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gpio_pin_set(pin);
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}
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else
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{
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gpio_pin_clr(pin);
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}
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gpio_handle[0].base->OUTENSET = (1U << pin);
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}
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else
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{
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SYSCON->IO_EI &= ~(1U << pin);
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gpio_handle[0].base->OUTENCLR = (1U << pin);
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}
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}
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void gpio_enable_irq(enum IO_PIN_T pin, enum GPIO_IRQ_TYPE_T irq_type, GPIO_IRQ_HANDLER_T irq_handler)
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{
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switch (irq_type)
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{
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case GPIO_IRQ_TYPE_LOW_LEVEL:
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gpio_handle[0].base->INTPOLCLR = (1U << pin);
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gpio_handle[0].base->INTTYPECLR = (1U << pin);
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break;
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case GPIO_IRQ_TYPE_HIGH_LEVEL:
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gpio_handle[0].base->INTPOLSET = (1U << pin);
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gpio_handle[0].base->INTTYPECLR = (1U << pin);
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break;
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case GPIO_IRQ_TYPE_FALLING_EDGE:
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gpio_handle[0].base->INTPOLCLR = (1U << pin);
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gpio_handle[0].base->INTTYPESET = (1U << pin);
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break;
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case GPIO_IRQ_TYPE_RISING_EDGE:
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gpio_handle[0].base->INTPOLSET = (1U << pin);
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gpio_handle[0].base->INTTYPESET = (1U << pin);
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break;
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}
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gpio_handle[0].irq_handler[pin] = irq_handler;
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if (gpio_handle[0].irq_mask == 0)
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{
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NVIC_SetPriority(gpio_handle[0].irq, IRQ_PRIORITY_NORMAL);
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NVIC_ClearPendingIRQ(gpio_handle[0].irq);
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NVIC_EnableIRQ(gpio_handle[0].irq);
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}
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gpio_handle[0].irq_mask |= (1U << pin);
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gpio_handle[0].base->INTENSET = (1U << pin);
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}
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void gpio_disable_irq(enum IO_PIN_T pin)
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{
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gpio_handle[0].base->INTENCLR = (1U << pin);
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gpio_handle[0].irq_mask &= ~(1U << pin);
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if (gpio_handle[0].irq_mask == 0)
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{
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NVIC_DisableIRQ(gpio_handle[0].irq);
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NVIC_ClearPendingIRQ(gpio_handle[0].irq);
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}
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}
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void GPIO_IRQHandler(void)
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{
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uint32_t int_stat = gpio_handle[0].base->INTSTATUS;
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for (enum IO_PIN_T i = 0; i < IO_PIN_MAX; i++)
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{
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if ((int_stat & (1U << i)) && (gpio_handle[0].irq_handler[i]))
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{
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gpio_handle[0].irq_handler[i](i);
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gpio_handle[0].base->INTSTATUS = (1 << i);
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}
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}
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}
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